drivers/net/ixgbe/base/ixgbe_x550.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2018
   3  */
   4
   5 #include "ixgbe_x550.h"
   6 #include "ixgbe_x540.h"
   7 #include "ixgbe_type.h"
   8 #include "ixgbe_api.h"
   9 #include "ixgbe_common.h"
  10 #include "ixgbe_phy.h"
  11
  12 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  13 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  14 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  15 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
  16
  17 /**
  18  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  19  *  @hw: pointer to hardware structure
  20  *
  21  *  Initialize the function pointers and assign the MAC type for X550.
  22  *  Does not touch the hardware.
  23  **/
  24 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  25 {
  26         struct ixgbe_mac_info *mac = &hw->mac;
  27         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  28         s32 ret_val;
  29
  30         DEBUGFUNC("ixgbe_init_ops_X550");
  31
  32         ret_val = ixgbe_init_ops_X540(hw);
  33         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  34         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  35         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  36         mac->ops.setup_eee = NULL;
  37         mac->ops.set_source_address_pruning =
  38                         ixgbe_set_source_address_pruning_X550;
  39         mac->ops.set_ethertype_anti_spoofing =
  40                         ixgbe_set_ethertype_anti_spoofing_X550;
  41
  42         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  43         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  44         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  45         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  46         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  47         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  48         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  49         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  50         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  51
  52         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  53         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  54         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  55         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  56         mac->ops.fw_recovery_mode = ixgbe_fw_recovery_mode_X550;
  57         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  58         /* Manageability interface */
  59         mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550;
  60         switch (hw->device_id) {
  61         case IXGBE_DEV_ID_X550EM_X_1G_T:
  62                 hw->mac.ops.led_on = NULL;
  63                 hw->mac.ops.led_off = NULL;
  64                 break;
  65         case IXGBE_DEV_ID_X550EM_X_10G_T:
  66         case IXGBE_DEV_ID_X550EM_A_10G_T:
  67                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  68                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  69                 break;
  70         default:
  71                 break;
  72         }
  73         return ret_val;
  74 }
  75
  76 /**
  77  * ixgbe_read_cs4227 - Read CS4227 register
  78  * @hw: pointer to hardware structure
  79  * @reg: register number to write
  80  * @value: pointer to receive value read
  81  *
  82  * Returns status code
  83  **/
  84 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  85 {
  86         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
  87 }
  88
  89 /**
  90  * ixgbe_write_cs4227 - Write CS4227 register
  91  * @hw: pointer to hardware structure
  92  * @reg: register number to write
  93  * @value: value to write to register
  94  *
  95  * Returns status code
  96  **/
  97 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
  98 {
  99         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 100 }
 101
 102 /**
 103  * ixgbe_read_pe - Read register from port expander
 104  * @hw: pointer to hardware structure
 105  * @reg: register number to read
 106  * @value: pointer to receive read value
 107  *
 108  * Returns status code
 109  **/
 110 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 111 {
 112         s32 status;
 113
 114         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 115         if (status != IXGBE_SUCCESS)
 116                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 117                               "port expander access failed with %d\n", status);
 118         return status;
 119 }
 120
 121 /**
 122  * ixgbe_write_pe - Write register to port expander
 123  * @hw: pointer to hardware structure
 124  * @reg: register number to write
 125  * @value: value to write
 126  *
 127  * Returns status code
 128  **/
 129 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 130 {
 131         s32 status;
 132
 133         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 134         if (status != IXGBE_SUCCESS)
 135                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 136                               "port expander access failed with %d\n", status);
 137         return status;
 138 }
 139
 140 /**
 141  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 142  * @hw: pointer to hardware structure
 143  *
 144  * This function assumes that the caller has acquired the proper semaphore.
 145  * Returns error code
 146  **/
 147 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 148 {
 149         s32 status;
 150         u32 retry;
 151         u16 value;
 152         u8 reg;
 153
 154         /* Trigger hard reset. */
 155         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 156         if (status != IXGBE_SUCCESS)
 157                 return status;
 158         reg |= IXGBE_PE_BIT1;
 159         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 160         if (status != IXGBE_SUCCESS)
 161                 return status;
 162
 163         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 164         if (status != IXGBE_SUCCESS)
 165                 return status;
 166         reg &= ~IXGBE_PE_BIT1;
 167         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 168         if (status != IXGBE_SUCCESS)
 169                 return status;
 170
 171         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 172         if (status != IXGBE_SUCCESS)
 173                 return status;
 174         reg &= ~IXGBE_PE_BIT1;
 175         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 176         if (status != IXGBE_SUCCESS)
 177                 return status;
 178
 179         usec_delay(IXGBE_CS4227_RESET_HOLD);
 180
 181         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 182         if (status != IXGBE_SUCCESS)
 183                 return status;
 184         reg |= IXGBE_PE_BIT1;
 185         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 186         if (status != IXGBE_SUCCESS)
 187                 return status;
 188
 189         /* Wait for the reset to complete. */
 190         msec_delay(IXGBE_CS4227_RESET_DELAY);
 191         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 192                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 193                                            &value);
 194                 if (status == IXGBE_SUCCESS &&
 195                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 196                         break;
 197                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 198         }
 199         if (retry == IXGBE_CS4227_RETRIES) {
 200                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 201                         "CS4227 reset did not complete.");
 202                 return IXGBE_ERR_PHY;
 203         }
 204
 205         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 206         if (status != IXGBE_SUCCESS ||
 207             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 208                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 209                         "CS4227 EEPROM did not load successfully.");
 210                 return IXGBE_ERR_PHY;
 211         }
 212
 213         return IXGBE_SUCCESS;
 214 }
 215
 216 /**
 217  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 218  * @hw: pointer to hardware structure
 219  **/
 220 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 221 {
 222         s32 status = IXGBE_SUCCESS;
 223         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 224         u16 value = 0;
 225         u8 retry;
 226
 227         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 228                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 229                 if (status != IXGBE_SUCCESS) {
 230                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 231                                 "semaphore failed with %d", status);
 232                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 233                         continue;
 234                 }
 235
 236                 /* Get status of reset flow. */
 237                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 238
 239                 if (status == IXGBE_SUCCESS &&
 240                     value == IXGBE_CS4227_RESET_COMPLETE)
 241                         goto out;
 242
 243                 if (status != IXGBE_SUCCESS ||
 244                     value != IXGBE_CS4227_RESET_PENDING)
 245                         break;
 246
 247                 /* Reset is pending. Wait and check again. */
 248                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 249                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 250         }
 251
 252         /* If still pending, assume other instance failed. */
 253         if (retry == IXGBE_CS4227_RETRIES) {
 254                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 255                 if (status != IXGBE_SUCCESS) {
 256                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 257                                       "semaphore failed with %d", status);
 258                         return;
 259                 }
 260         }
 261
 262         /* Reset the CS4227. */
 263         status = ixgbe_reset_cs4227(hw);
 264         if (status != IXGBE_SUCCESS) {
 265                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 266                         "CS4227 reset failed: %d", status);
 267                 goto out;
 268         }
 269
 270         /* Reset takes so long, temporarily release semaphore in case the
 271          * other driver instance is waiting for the reset indication.
 272          */
 273         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 274                            IXGBE_CS4227_RESET_PENDING);
 275         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 276         msec_delay(10);
 277         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 278         if (status != IXGBE_SUCCESS) {
 279                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 280                         "semaphore failed with %d", status);
 281                 return;
 282         }
 283
 284         /* Record completion for next time. */
 285         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 286                 IXGBE_CS4227_RESET_COMPLETE);
 287
 288 out:
 289         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 290         msec_delay(hw->eeprom.semaphore_delay);
 291 }
 292
 293 /**
 294  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 295  * @hw: pointer to hardware structure
 296  **/
 297 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 298 {
 299         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 300
 301         if (hw->bus.lan_id) {
 302                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 303                 esdp |= IXGBE_ESDP_SDP1_DIR;
 304         }
 305         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 306         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 307         IXGBE_WRITE_FLUSH(hw);
 308 }
 309
 310 /**
 311  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 312  * @hw: pointer to hardware structure
 313  *
 314  * Returns error code
 315  */
 316 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 317 {
 318         hw->mac.ops.set_lan_id(hw);
 319
 320         ixgbe_read_mng_if_sel_x550em(hw);
 321
 322         switch (hw->device_id) {
 323         case IXGBE_DEV_ID_X550EM_A_SFP:
 324                 return ixgbe_identify_sfp_module_X550em(hw);
 325         case IXGBE_DEV_ID_X550EM_X_SFP:
 326                 /* set up for CS4227 usage */
 327                 ixgbe_setup_mux_ctl(hw);
 328                 ixgbe_check_cs4227(hw);
 329                 /* Fallthrough */
 330
 331         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 332                 return ixgbe_identify_sfp_module_X550em(hw);
 333                 break;
 334         case IXGBE_DEV_ID_X550EM_X_KX4:
 335                 hw->phy.type = ixgbe_phy_x550em_kx4;
 336                 break;
 337         case IXGBE_DEV_ID_X550EM_X_XFI:
 338                 hw->phy.type = ixgbe_phy_x550em_xfi;
 339                 break;
 340         case IXGBE_DEV_ID_X550EM_X_KR:
 341         case IXGBE_DEV_ID_X550EM_A_KR:
 342         case IXGBE_DEV_ID_X550EM_A_KR_L:
 343                 hw->phy.type = ixgbe_phy_x550em_kr;
 344                 break;
 345         case IXGBE_DEV_ID_X550EM_A_10G_T:
 346         case IXGBE_DEV_ID_X550EM_X_10G_T:
 347                 return ixgbe_identify_phy_generic(hw);
 348         case IXGBE_DEV_ID_X550EM_X_1G_T:
 349                 hw->phy.type = ixgbe_phy_ext_1g_t;
 350                 break;
 351         case IXGBE_DEV_ID_X550EM_A_1G_T:
 352         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 353                 hw->phy.type = ixgbe_phy_fw;
 354                 if (hw->bus.lan_id)
 355                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 356                 else
 357                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 358                 break;
 359         default:
 360                 break;
 361         }
 362         return IXGBE_SUCCESS;
 363 }
 364
 365 /**
 366  * ixgbe_fw_phy_activity - Perform an activity on a PHY
 367  * @hw: pointer to hardware structure
 368  * @activity: activity to perform
 369  * @data: Pointer to 4 32-bit words of data
 370  */
 371 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
 372                           u32 (*data)[FW_PHY_ACT_DATA_COUNT])
 373 {
 374         union {
 375                 struct ixgbe_hic_phy_activity_req cmd;
 376                 struct ixgbe_hic_phy_activity_resp rsp;
 377         } hic;
 378         u16 retries = FW_PHY_ACT_RETRIES;
 379         s32 rc;
 380         u16 i;
 381
 382         do {
 383                 memset(&hic, 0, sizeof(hic));
 384                 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
 385                 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
 386                 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 387                 hic.cmd.port_number = hw->bus.lan_id;
 388                 hic.cmd.activity_id = IXGBE_CPU_TO_LE16(activity);
 389                 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 390                         hic.cmd.data[i] = IXGBE_CPU_TO_BE32((*data)[i]);
 391
 392                 rc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
 393                                                   sizeof(hic.cmd),
 394                                                   IXGBE_HI_COMMAND_TIMEOUT,
 395                                                   true);
 396                 if (rc != IXGBE_SUCCESS)
 397                         return rc;
 398                 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
 399                     FW_CEM_RESP_STATUS_SUCCESS) {
 400                         for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 401                                 (*data)[i] = IXGBE_BE32_TO_CPU(hic.rsp.data[i]);
 402                         return IXGBE_SUCCESS;
 403                 }
 404                 usec_delay(20);
 405                 --retries;
 406         } while (retries > 0);
 407
 408         return IXGBE_ERR_HOST_INTERFACE_COMMAND;
 409 }
 410
 411 static const struct {
 412         u16 fw_speed;
 413         ixgbe_link_speed phy_speed;
 414 } ixgbe_fw_map[] = {
 415         { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
 416         { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
 417         { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
 418         { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
 419         { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
 420         { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
 421 };
 422
 423 /**
 424  * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
 425  * @hw: pointer to hardware structure
 426  *
 427  * Returns error code
 428  */
 429 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
 430 {
 431         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
 432         u16 phy_speeds;
 433         u16 phy_id_lo;
 434         s32 rc;
 435         u16 i;
 436
 437         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
 438         if (rc)
 439                 return rc;
 440
 441         hw->phy.speeds_supported = 0;
 442         phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
 443         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 444                 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
 445                         hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
 446         }
 447         if (!hw->phy.autoneg_advertised)
 448                 hw->phy.autoneg_advertised = hw->phy.speeds_supported;
 449
 450         hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
 451         phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
 452         hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
 453         hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
 454         if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
 455                 return IXGBE_ERR_PHY_ADDR_INVALID;
 456         return IXGBE_SUCCESS;
 457 }
 458
 459 /**
 460  * ixgbe_identify_phy_fw - Get PHY type based on firmware command
 461  * @hw: pointer to hardware structure
 462  *
 463  * Returns error code
 464  */
 465 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
 466 {
 467         if (hw->bus.lan_id)
 468                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 469         else
 470                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 471
 472         hw->phy.type = ixgbe_phy_fw;
 473         hw->phy.ops.read_reg = NULL;
 474         hw->phy.ops.write_reg = NULL;
 475         return ixgbe_get_phy_id_fw(hw);
 476 }
 477
 478 /**
 479  * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
 480  * @hw: pointer to hardware structure
 481  *
 482  * Returns error code
 483  */
 484 s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
 485 {
 486         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 487
 488         setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
 489         return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
 490 }
 491
 492 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 493                                      u32 device_type, u16 *phy_data)
 494 {
 495         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 496         return IXGBE_NOT_IMPLEMENTED;
 497 }
 498
 499 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 500                                       u32 device_type, u16 phy_data)
 501 {
 502         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 503         return IXGBE_NOT_IMPLEMENTED;
 504 }
 505
 506 /**
 507  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 508  * @hw: pointer to the hardware structure
 509  * @addr: I2C bus address to read from
 510  * @reg: I2C device register to read from
 511  * @val: pointer to location to receive read value
 512  *
 513  * Returns an error code on error.
 514  **/
 515 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 516                                            u16 reg, u16 *val)
 517 {
 518         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 519 }
 520
 521 /**
 522  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 523  * @hw: pointer to the hardware structure
 524  * @addr: I2C bus address to read from
 525  * @reg: I2C device register to read from
 526  * @val: pointer to location to receive read value
 527  *
 528  * Returns an error code on error.
 529  **/
 530 STATIC s32
 531 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 532                                          u16 reg, u16 *val)
 533 {
 534         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 535 }
 536
 537 /**
 538  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 539  * @hw: pointer to the hardware structure
 540  * @addr: I2C bus address to write to
 541  * @reg: I2C device register to write to
 542  * @val: value to write
 543  *
 544  * Returns an error code on error.
 545  **/
 546 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 547                                             u8 addr, u16 reg, u16 val)
 548 {
 549         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 550 }
 551
 552 /**
 553  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 554  * @hw: pointer to the hardware structure
 555  * @addr: I2C bus address to write to
 556  * @reg: I2C device register to write to
 557  * @val: value to write
 558  *
 559  * Returns an error code on error.
 560  **/
 561 STATIC s32
 562 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 563                                           u8 addr, u16 reg, u16 val)
 564 {
 565         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 566 }
 567
 568 /**
 569 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 570 *  @hw: pointer to hardware structure
 571 *
 572 *  Initialize the function pointers and for MAC type X550EM.
 573 *  Does not touch the hardware.
 574 **/
 575 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 576 {
 577         struct ixgbe_mac_info *mac = &hw->mac;
 578         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 579         struct ixgbe_phy_info *phy = &hw->phy;
 580         s32 ret_val;
 581
 582         DEBUGFUNC("ixgbe_init_ops_X550EM");
 583
 584         /* Similar to X550 so start there. */
 585         ret_val = ixgbe_init_ops_X550(hw);
 586
 587         /* Since this function eventually calls
 588          * ixgbe_init_ops_540 by design, we are setting
 589          * the pointers to NULL explicitly here to overwrite
 590          * the values being set in the x540 function.
 591          */
 592         /* Thermal sensor not supported in x550EM */
 593         mac->ops.get_thermal_sensor_data = NULL;
 594         mac->ops.init_thermal_sensor_thresh = NULL;
 595         mac->thermal_sensor_enabled = false;
 596
 597         /* FCOE not supported in x550EM */
 598         mac->ops.get_san_mac_addr = NULL;
 599         mac->ops.set_san_mac_addr = NULL;
 600         mac->ops.get_wwn_prefix = NULL;
 601         mac->ops.get_fcoe_boot_status = NULL;
 602
 603         /* IPsec not supported in x550EM */
 604         mac->ops.disable_sec_rx_path = NULL;
 605         mac->ops.enable_sec_rx_path = NULL;
 606
 607         /* AUTOC register is not present in x550EM. */
 608         mac->ops.prot_autoc_read = NULL;
 609         mac->ops.prot_autoc_write = NULL;
 610
 611         /* X550EM bus type is internal*/
 612         hw->bus.type = ixgbe_bus_type_internal;
 613         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 614
 615
 616         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 617         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 618         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 619         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 620         mac->ops.get_supported_physical_layer =
 621                                     ixgbe_get_supported_physical_layer_X550em;
 622
 623         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 624                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 625         else
 626                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 627
 628         /* PHY */
 629         phy->ops.init = ixgbe_init_phy_ops_X550em;
 630         switch (hw->device_id) {
 631         case IXGBE_DEV_ID_X550EM_A_1G_T:
 632         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 633                 mac->ops.setup_fc = NULL;
 634                 phy->ops.identify = ixgbe_identify_phy_fw;
 635                 phy->ops.set_phy_power = NULL;
 636                 phy->ops.get_firmware_version = NULL;
 637                 break;
 638         case IXGBE_DEV_ID_X550EM_X_1G_T:
 639                 mac->ops.setup_fc = NULL;
 640                 phy->ops.identify = ixgbe_identify_phy_x550em;
 641                 phy->ops.set_phy_power = NULL;
 642                 break;
 643         default:
 644                 phy->ops.identify = ixgbe_identify_phy_x550em;
 645         }
 646
 647         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 648                 phy->ops.set_phy_power = NULL;
 649
 650
 651         /* EEPROM */
 652         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 653         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 654         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 655         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 656         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 657         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 658         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 659         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 660
 661         return ret_val;
 662 }
 663
 664 /**
 665  * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
 666  * @hw: pointer to hardware structure
 667  */
 668 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
 669 {
 670         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 671         s32 rc;
 672         u16 i;
 673
 674         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
 675                 return 0;
 676
 677         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
 678                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
 679                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
 680                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
 681         }
 682
 683         switch (hw->fc.requested_mode) {
 684         case ixgbe_fc_full:
 685                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
 686                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 687                 break;
 688         case ixgbe_fc_rx_pause:
 689                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
 690                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 691                 break;
 692         case ixgbe_fc_tx_pause:
 693                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
 694                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 695                 break;
 696         default:
 697                 break;
 698         }
 699
 700         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 701                 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
 702                         setup[0] |= ixgbe_fw_map[i].fw_speed;
 703         }
 704         setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
 705
 706         if (hw->phy.eee_speeds_advertised)
 707                 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
 708
 709         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
 710         if (rc)
 711                 return rc;
 712         if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
 713                 return IXGBE_ERR_OVERTEMP;
 714         return IXGBE_SUCCESS;
 715 }
 716
 717 /**
 718  * ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs
 719  * @hw: pointer to hardware structure
 720  *
 721  *  Called at init time to set up flow control.
 722  */
 723 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
 724 {
 725         if (hw->fc.requested_mode == ixgbe_fc_default)
 726                 hw->fc.requested_mode = ixgbe_fc_full;
 727
 728         return ixgbe_setup_fw_link(hw);
 729 }
 730
 731 /**
 732  * ixgbe_setup_eee_fw - Enable/disable EEE support
 733  * @hw: pointer to the HW structure
 734  * @enable_eee: boolean flag to enable EEE
 735  *
 736  * Enable/disable EEE based on enable_eee flag.
 737  * This function controls EEE for firmware-based PHY implementations.
 738  */
 739 static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee)
 740 {
 741         if (!!hw->phy.eee_speeds_advertised == enable_eee)
 742                 return IXGBE_SUCCESS;
 743         if (enable_eee)
 744                 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 745         else
 746                 hw->phy.eee_speeds_advertised = 0;
 747         return hw->phy.ops.setup_link(hw);
 748 }
 749
 750 /**
 751 *  ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
 752 *  @hw: pointer to hardware structure
 753 *
 754 *  Initialize the function pointers and for MAC type X550EM_a.
 755 *  Does not touch the hardware.
 756 **/
 757 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
 758 {
 759         struct ixgbe_mac_info *mac = &hw->mac;
 760         s32 ret_val;
 761
 762         DEBUGFUNC("ixgbe_init_ops_X550EM_a");
 763
 764         /* Start with generic X550EM init */
 765         ret_val = ixgbe_init_ops_X550EM(hw);
 766
 767         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
 768             hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
 769                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 770                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 771         } else {
 772                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
 773                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
 774         }
 775         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 776         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 777
 778         switch (mac->ops.get_media_type(hw)) {
 779         case ixgbe_media_type_fiber:
 780                 mac->ops.setup_fc = NULL;
 781                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
 782                 break;
 783         case ixgbe_media_type_backplane:
 784                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
 785                 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
 786                 break;
 787         default:
 788                 break;
 789         }
 790
 791         switch (hw->device_id) {
 792         case IXGBE_DEV_ID_X550EM_A_1G_T:
 793         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 794                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
 795                 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
 796                 mac->ops.setup_eee = ixgbe_setup_eee_fw;
 797                 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
 798                                                IXGBE_LINK_SPEED_1GB_FULL;
 799                 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 800                 break;
 801         default:
 802                 break;
 803         }
 804
 805         return ret_val;
 806 }
 807
 808 /**
 809 *  ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
 810 *  @hw: pointer to hardware structure
 811 *
 812 *  Initialize the function pointers and for MAC type X550EM_x.
 813 *  Does not touch the hardware.
 814 **/
 815 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
 816 {
 817         struct ixgbe_mac_info *mac = &hw->mac;
 818         struct ixgbe_link_info *link = &hw->link;
 819         s32 ret_val;
 820
 821         DEBUGFUNC("ixgbe_init_ops_X550EM_x");
 822
 823         /* Start with generic X550EM init */
 824         ret_val = ixgbe_init_ops_X550EM(hw);
 825
 826         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 827         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 828         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 829         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 830         link->ops.read_link = ixgbe_read_i2c_combined_generic;
 831         link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
 832         link->ops.write_link = ixgbe_write_i2c_combined_generic;
 833         link->ops.write_link_unlocked =
 834                                       ixgbe_write_i2c_combined_generic_unlocked;
 835         link->addr = IXGBE_CS4227;
 836
 837         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) {
 838                 mac->ops.setup_fc = NULL;
 839                 mac->ops.setup_eee = NULL;
 840                 mac->ops.init_led_link_act = NULL;
 841         }
 842
 843         return ret_val;
 844 }
 845
 846 /**
 847  *  ixgbe_dmac_config_X550
 848  *  @hw: pointer to hardware structure
 849  *
 850  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 851  *  When disabling dmac, dmac enable dmac bit is cleared.
 852  **/
 853 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 854 {
 855         u32 reg, high_pri_tc;
 856
 857         DEBUGFUNC("ixgbe_dmac_config_X550");
 858
 859         /* Disable DMA coalescing before configuring */
 860         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 861         reg &= ~IXGBE_DMACR_DMAC_EN;
 862         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 863
 864         /* Disable DMA Coalescing if the watchdog timer is 0 */
 865         if (!hw->mac.dmac_config.watchdog_timer)
 866                 goto out;
 867
 868         ixgbe_dmac_config_tcs_X550(hw);
 869
 870         /* Configure DMA Coalescing Control Register */
 871         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 872
 873         /* Set the watchdog timer in units of 40.96 usec */
 874         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 875         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 876
 877         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 878         /* If fcoe is enabled, set high priority traffic class */
 879         if (hw->mac.dmac_config.fcoe_en) {
 880                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 881                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 882                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 883         }
 884         reg |= IXGBE_DMACR_EN_MNG_IND;
 885
 886         /* Enable DMA coalescing after configuration */
 887         reg |= IXGBE_DMACR_DMAC_EN;
 888         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 889
 890 out:
 891         return IXGBE_SUCCESS;
 892 }
 893
 894 /**
 895  *  ixgbe_dmac_config_tcs_X550
 896  *  @hw: pointer to hardware structure
 897  *
 898  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 899  *  be cleared before configuring.
 900  **/
 901 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 902 {
 903         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 904
 905         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 906
 907         /* Configure DMA coalescing enabled */
 908         switch (hw->mac.dmac_config.link_speed) {
 909         case IXGBE_LINK_SPEED_10_FULL:
 910         case IXGBE_LINK_SPEED_100_FULL:
 911                 pb_headroom = IXGBE_DMACRXT_100M;
 912                 break;
 913         case IXGBE_LINK_SPEED_1GB_FULL:
 914                 pb_headroom = IXGBE_DMACRXT_1G;
 915                 break;
 916         default:
 917                 pb_headroom = IXGBE_DMACRXT_10G;
 918                 break;
 919         }
 920
 921         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 922                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 923
 924         /* Set the per Rx packet buffer receive threshold */
 925         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 926                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 927                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 928
 929                 if (tc < hw->mac.dmac_config.num_tcs) {
 930                         /* Get Rx PB size */
 931                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 932                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 933                                 IXGBE_RXPBSIZE_SHIFT;
 934
 935                         /* Calculate receive buffer threshold in kilobytes */
 936                         if (rx_pb_size > pb_headroom)
 937                                 rx_pb_size = rx_pb_size - pb_headroom;
 938                         else
 939                                 rx_pb_size = 0;
 940
 941                         /* Minimum of MFS shall be set for DMCTH */
 942                         reg |= (rx_pb_size > maxframe_size_kb) ?
 943                                 rx_pb_size : maxframe_size_kb;
 944                 }
 945                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 946         }
 947         return IXGBE_SUCCESS;
 948 }
 949
 950 /**
 951  *  ixgbe_dmac_update_tcs_X550
 952  *  @hw: pointer to hardware structure
 953  *
 954  *  Disables dmac, updates per TC settings, and then enables dmac.
 955  **/
 956 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 957 {
 958         u32 reg;
 959
 960         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 961
 962         /* Disable DMA coalescing before configuring */
 963         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 964         reg &= ~IXGBE_DMACR_DMAC_EN;
 965         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 966
 967         ixgbe_dmac_config_tcs_X550(hw);
 968
 969         /* Enable DMA coalescing after configuration */
 970         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 971         reg |= IXGBE_DMACR_DMAC_EN;
 972         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 973
 974         return IXGBE_SUCCESS;
 975 }
 976
 977 /**
 978  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 979  *  @hw: pointer to hardware structure
 980  *
 981  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 982  *  ixgbe_hw struct in order to set up EEPROM access.
 983  **/
 984 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 985 {
 986         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 987         u32 eec;
 988         u16 eeprom_size;
 989
 990         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 991
 992         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 993                 eeprom->semaphore_delay = 10;
 994                 eeprom->type = ixgbe_flash;
 995
 996                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 997                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 998                                     IXGBE_EEC_SIZE_SHIFT);
 999                 eeprom->word_size = 1 << (eeprom_size +
1000                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
1001
1002                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
1003                           eeprom->type, eeprom->word_size);
1004         }
1005
1006         return IXGBE_SUCCESS;
1007 }
1008
1009 /**
1010  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1011  * @hw: pointer to hardware structure
1012  * @enable: enable or disable source address pruning
1013  * @pool: Rx pool to set source address pruning for
1014  **/
1015 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1016                                            unsigned int pool)
1017 {
1018         u64 pfflp;
1019
1020         /* max rx pool is 63 */
1021         if (pool > 63)
1022                 return;
1023
1024         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1025         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1026
1027         if (enable)
1028                 pfflp |= (1ULL << pool);
1029         else
1030                 pfflp &= ~(1ULL << pool);
1031
1032         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1033         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1034 }
1035
1036 /**
1037  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1038  *  @hw: pointer to hardware structure
1039  *  @enable: enable or disable switch for Ethertype anti-spoofing
1040  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1041  *
1042  **/
1043 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1044                 bool enable, int vf)
1045 {
1046         int vf_target_reg = vf >> 3;
1047         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1048         u32 pfvfspoof;
1049
1050         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1051
1052         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1053         if (enable)
1054                 pfvfspoof |= (1 << vf_target_shift);
1055         else
1056                 pfvfspoof &= ~(1 << vf_target_shift);
1057
1058         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1059 }
1060
1061 /**
1062  * ixgbe_iosf_wait - Wait for IOSF command completion
1063  * @hw: pointer to hardware structure
1064  * @ctrl: pointer to location to receive final IOSF control value
1065  *
1066  * Returns failing status on timeout
1067  *
1068  * Note: ctrl can be NULL if the IOSF control register value is not needed
1069  **/
1070 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1071 {
1072         u32 i, command = 0;
1073
1074         /* Check every 10 usec to see if the address cycle completed.
1075          * The SB IOSF BUSY bit will clear when the operation is
1076          * complete
1077          */
1078         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1079                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1080                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1081                         break;
1082                 usec_delay(10);
1083         }
1084         if (ctrl)
1085                 *ctrl = command;
1086         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1087                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1088                 return IXGBE_ERR_PHY;
1089         }
1090
1091         return IXGBE_SUCCESS;
1092 }
1093
1094 /**
1095  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1096  *  of the IOSF device
1097  *  @hw: pointer to hardware structure
1098  *  @reg_addr: 32 bit PHY register to write
1099  *  @device_type: 3 bit device type
1100  *  @data: Data to write to the register
1101  **/
1102 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1103                             u32 device_type, u32 data)
1104 {
1105         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1106         u32 command, error;
1107         s32 ret;
1108
1109         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1110         if (ret != IXGBE_SUCCESS)
1111                 return ret;
1112
1113         ret = ixgbe_iosf_wait(hw, NULL);
1114         if (ret != IXGBE_SUCCESS)
1115                 goto out;
1116
1117         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1118                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1119
1120         /* Write IOSF control register */
1121         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1122
1123         /* Write IOSF data register */
1124         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1125
1126         ret = ixgbe_iosf_wait(hw, &command);
1127
1128         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1129                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1130                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1131                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1132                               "Failed to write, error %x\n", error);
1133                 ret = IXGBE_ERR_PHY;
1134         }
1135
1136 out:
1137         ixgbe_release_swfw_semaphore(hw, gssr);
1138         return ret;
1139 }
1140
1141 /**
1142  *  ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1143  *  @hw: pointer to hardware structure
1144  *  @reg_addr: 32 bit PHY register to write
1145  *  @device_type: 3 bit device type
1146  *  @data: Pointer to read data from the register
1147  **/
1148 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1149                            u32 device_type, u32 *data)
1150 {
1151         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1152         u32 command, error;
1153         s32 ret;
1154
1155         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1156         if (ret != IXGBE_SUCCESS)
1157                 return ret;
1158
1159         ret = ixgbe_iosf_wait(hw, NULL);
1160         if (ret != IXGBE_SUCCESS)
1161                 goto out;
1162
1163         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1164                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1165
1166         /* Write IOSF control register */
1167         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1168
1169         ret = ixgbe_iosf_wait(hw, &command);
1170
1171         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1172                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1173                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1174                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1175                                 "Failed to read, error %x\n", error);
1176                 ret = IXGBE_ERR_PHY;
1177         }
1178
1179         if (ret == IXGBE_SUCCESS)
1180                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1181
1182 out:
1183         ixgbe_release_swfw_semaphore(hw, gssr);
1184         return ret;
1185 }
1186
1187 /**
1188  * ixgbe_get_phy_token - Get the token for shared phy access
1189  * @hw: Pointer to hardware structure
1190  */
1191
1192 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1193 {
1194         struct ixgbe_hic_phy_token_req token_cmd;
1195         s32 status;
1196
1197         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1198         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1199         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1200         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1201         token_cmd.port_number = hw->bus.lan_id;
1202         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1203         token_cmd.pad = 0;
1204         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1205                                               sizeof(token_cmd),
1206                                               IXGBE_HI_COMMAND_TIMEOUT,
1207                                               true);
1208         if (status) {
1209                 DEBUGOUT1("Issuing host interface command failed with Status = %d\n",
1210                           status);
1211                 return status;
1212         }
1213         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1214                 return IXGBE_SUCCESS;
1215         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY) {
1216                 DEBUGOUT1("Host interface command returned 0x%08x , returning IXGBE_ERR_FW_RESP_INVALID\n",
1217                           token_cmd.hdr.cmd_or_resp.ret_status);
1218                 return IXGBE_ERR_FW_RESP_INVALID;
1219         }
1220
1221         DEBUGOUT("Returning  IXGBE_ERR_TOKEN_RETRY\n");
1222         return IXGBE_ERR_TOKEN_RETRY;
1223 }
1224
1225 /**
1226  * ixgbe_put_phy_token - Put the token for shared phy access
1227  * @hw: Pointer to hardware structure
1228  */
1229
1230 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1231 {
1232         struct ixgbe_hic_phy_token_req token_cmd;
1233         s32 status;
1234
1235         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1236         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1237         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1238         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1239         token_cmd.port_number = hw->bus.lan_id;
1240         token_cmd.command_type = FW_PHY_TOKEN_REL;
1241         token_cmd.pad = 0;
1242         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1243                                               sizeof(token_cmd),
1244                                               IXGBE_HI_COMMAND_TIMEOUT,
1245                                               true);
1246         if (status)
1247                 return status;
1248         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1249                 return IXGBE_SUCCESS;
1250
1251         DEBUGOUT("Put PHY Token host interface command failed");
1252         return IXGBE_ERR_FW_RESP_INVALID;
1253 }
1254
1255 /**
1256  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1257  *  of the IOSF device
1258  *  @hw: pointer to hardware structure
1259  *  @reg_addr: 32 bit PHY register to write
1260  *  @device_type: 3 bit device type
1261  *  @data: Data to write to the register
1262  **/
1263 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1264                                   u32 device_type, u32 data)
1265 {
1266         struct ixgbe_hic_internal_phy_req write_cmd;
1267         s32 status;
1268         UNREFERENCED_1PARAMETER(device_type);
1269
1270         memset(&write_cmd, 0, sizeof(write_cmd));
1271         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1272         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1273         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1274         write_cmd.port_number = hw->bus.lan_id;
1275         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1276         write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1277         write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1278
1279         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1280                                               sizeof(write_cmd),
1281                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1282
1283         return status;
1284 }
1285
1286 /**
1287  *  ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1288  *  @hw: pointer to hardware structure
1289  *  @reg_addr: 32 bit PHY register to write
1290  *  @device_type: 3 bit device type
1291  *  @data: Pointer to read data from the register
1292  **/
1293 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1294                                  u32 device_type, u32 *data)
1295 {
1296         union {
1297                 struct ixgbe_hic_internal_phy_req cmd;
1298                 struct ixgbe_hic_internal_phy_resp rsp;
1299         } hic;
1300         s32 status;
1301         UNREFERENCED_1PARAMETER(device_type);
1302
1303         memset(&hic, 0, sizeof(hic));
1304         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1305         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1306         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1307         hic.cmd.port_number = hw->bus.lan_id;
1308         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1309         hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1310
1311         status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1312                                               sizeof(hic.cmd),
1313                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1314
1315         /* Extract the register value from the response. */
1316         *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1317
1318         return status;
1319 }
1320
1321 /**
1322  *  ixgbe_disable_mdd_X550
1323  *  @hw: pointer to hardware structure
1324  *
1325  *  Disable malicious driver detection
1326  **/
1327 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1328 {
1329         u32 reg;
1330
1331         DEBUGFUNC("ixgbe_disable_mdd_X550");
1332
1333         /* Disable MDD for TX DMA and interrupt */
1334         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1335         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1336         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1337
1338         /* Disable MDD for RX and interrupt */
1339         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1340         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1341         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1342 }
1343
1344 /**
1345  *  ixgbe_enable_mdd_X550
1346  *  @hw: pointer to hardware structure
1347  *
1348  *  Enable malicious driver detection
1349  **/
1350 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1351 {
1352         u32 reg;
1353
1354         DEBUGFUNC("ixgbe_enable_mdd_X550");
1355
1356         /* Enable MDD for TX DMA and interrupt */
1357         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1358         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1359         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1360
1361         /* Enable MDD for RX and interrupt */
1362         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1363         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1364         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1365 }
1366
1367 /**
1368  *  ixgbe_restore_mdd_vf_X550
1369  *  @hw: pointer to hardware structure
1370  *  @vf: vf index
1371  *
1372  *  Restore VF that was disabled during malicious driver detection event
1373  **/
1374 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1375 {
1376         u32 idx, reg, num_qs, start_q, bitmask;
1377
1378         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1379
1380         /* Map VF to queues */
1381         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1382         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1383         case IXGBE_MRQC_VMDQRT8TCEN:
1384                 num_qs = 8;  /* 16 VFs / pools */
1385                 bitmask = 0x000000FF;
1386                 break;
1387         case IXGBE_MRQC_VMDQRSS32EN:
1388         case IXGBE_MRQC_VMDQRT4TCEN:
1389                 num_qs = 4;  /* 32 VFs / pools */
1390                 bitmask = 0x0000000F;
1391                 break;
1392         default:            /* 64 VFs / pools */
1393                 num_qs = 2;
1394                 bitmask = 0x00000003;
1395                 break;
1396         }
1397         start_q = vf * num_qs;
1398
1399         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1400         idx = start_q / 32;
1401         reg = 0;
1402         reg |= (bitmask << (start_q % 32));
1403         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1404         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1405 }
1406
1407 /**
1408  *  ixgbe_mdd_event_X550
1409  *  @hw: pointer to hardware structure
1410  *  @vf_bitmap: vf bitmap of malicious vfs
1411  *
1412  *  Handle malicious driver detection event.
1413  **/
1414 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1415 {
1416         u32 wqbr;
1417         u32 i, j, reg, q, shift, vf, idx;
1418
1419         DEBUGFUNC("ixgbe_mdd_event_X550");
1420
1421         /* figure out pool size for mapping to vf's */
1422         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1423         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1424         case IXGBE_MRQC_VMDQRT8TCEN:
1425                 shift = 3;  /* 16 VFs / pools */
1426                 break;
1427         case IXGBE_MRQC_VMDQRSS32EN:
1428         case IXGBE_MRQC_VMDQRT4TCEN:
1429                 shift = 2;  /* 32 VFs / pools */
1430                 break;
1431         default:
1432                 shift = 1;  /* 64 VFs / pools */
1433                 break;
1434         }
1435
1436         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1437         for (i = 0; i < 4; i++) {
1438                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1439                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1440
1441                 if (!wqbr)
1442                         continue;
1443
1444                 /* Get malicious queue */
1445                 for (j = 0; j < 32 && wqbr; j++) {
1446
1447                         if (!(wqbr & (1 << j)))
1448                                 continue;
1449
1450                         /* Get queue from bitmask */
1451                         q = j + (i * 32);
1452
1453                         /* Map queue to vf */
1454                         vf = (q >> shift);
1455
1456                         /* Set vf bit in vf_bitmap */
1457                         idx = vf / 32;
1458                         vf_bitmap[idx] |= (1 << (vf % 32));
1459                         wqbr &= ~(1 << j);
1460                 }
1461         }
1462 }
1463
1464 /**
1465  *  ixgbe_get_media_type_X550em - Get media type
1466  *  @hw: pointer to hardware structure
1467  *
1468  *  Returns the media type (fiber, copper, backplane)
1469  */
1470 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1471 {
1472         enum ixgbe_media_type media_type;
1473
1474         DEBUGFUNC("ixgbe_get_media_type_X550em");
1475
1476         /* Detect if there is a copper PHY attached. */
1477         switch (hw->device_id) {
1478         case IXGBE_DEV_ID_X550EM_X_KR:
1479         case IXGBE_DEV_ID_X550EM_X_KX4:
1480         case IXGBE_DEV_ID_X550EM_X_XFI:
1481         case IXGBE_DEV_ID_X550EM_A_KR:
1482         case IXGBE_DEV_ID_X550EM_A_KR_L:
1483                 media_type = ixgbe_media_type_backplane;
1484                 break;
1485         case IXGBE_DEV_ID_X550EM_X_SFP:
1486         case IXGBE_DEV_ID_X550EM_A_SFP:
1487         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1488         case IXGBE_DEV_ID_X550EM_A_QSFP:
1489         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1490                 media_type = ixgbe_media_type_fiber;
1491                 break;
1492         case IXGBE_DEV_ID_X550EM_X_1G_T:
1493         case IXGBE_DEV_ID_X550EM_X_10G_T:
1494         case IXGBE_DEV_ID_X550EM_A_10G_T:
1495                 media_type = ixgbe_media_type_copper;
1496                 break;
1497         case IXGBE_DEV_ID_X550EM_A_SGMII:
1498         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1499                 media_type = ixgbe_media_type_backplane;
1500                 hw->phy.type = ixgbe_phy_sgmii;
1501                 break;
1502         case IXGBE_DEV_ID_X550EM_A_1G_T:
1503         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1504                 media_type = ixgbe_media_type_copper;
1505                 break;
1506         default:
1507                 media_type = ixgbe_media_type_unknown;
1508                 break;
1509         }
1510         return media_type;
1511 }
1512
1513 /**
1514  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1515  *  @hw: pointer to hardware structure
1516  *  @linear: true if SFP module is linear
1517  */
1518 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1519 {
1520         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1521
1522         switch (hw->phy.sfp_type) {
1523         case ixgbe_sfp_type_not_present:
1524                 return IXGBE_ERR_SFP_NOT_PRESENT;
1525         case ixgbe_sfp_type_da_cu_core0:
1526         case ixgbe_sfp_type_da_cu_core1:
1527                 *linear = true;
1528                 break;
1529         case ixgbe_sfp_type_srlr_core0:
1530         case ixgbe_sfp_type_srlr_core1:
1531         case ixgbe_sfp_type_da_act_lmt_core0:
1532         case ixgbe_sfp_type_da_act_lmt_core1:
1533         case ixgbe_sfp_type_1g_sx_core0:
1534         case ixgbe_sfp_type_1g_sx_core1:
1535         case ixgbe_sfp_type_1g_lx_core0:
1536         case ixgbe_sfp_type_1g_lx_core1:
1537         case ixgbe_sfp_type_1g_lha_core0:
1538         case ixgbe_sfp_type_1g_lha_core1:
1539                 *linear = false;
1540                 break;
1541         case ixgbe_sfp_type_unknown:
1542         case ixgbe_sfp_type_1g_cu_core0:
1543         case ixgbe_sfp_type_1g_cu_core1:
1544         default:
1545                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1546         }
1547
1548         return IXGBE_SUCCESS;
1549 }
1550
1551 /**
1552  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1553  *  @hw: pointer to hardware structure
1554  *
1555  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1556  **/
1557 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1558 {
1559         s32 status;
1560         bool linear;
1561
1562         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1563
1564         status = ixgbe_identify_module_generic(hw);
1565
1566         if (status != IXGBE_SUCCESS)
1567                 return status;
1568
1569         /* Check if SFP module is supported */
1570         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1571
1572         return status;
1573 }
1574
1575 /**
1576  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1577  *  @hw: pointer to hardware structure
1578  */
1579 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1580 {
1581         s32 status;
1582         bool linear;
1583
1584         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1585
1586         /* Check if SFP module is supported */
1587         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1588
1589         if (status != IXGBE_SUCCESS)
1590                 return status;
1591
1592         ixgbe_init_mac_link_ops_X550em(hw);
1593         hw->phy.ops.reset = NULL;
1594
1595         return IXGBE_SUCCESS;
1596 }
1597
1598 /**
1599 *  ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1600 *  internal PHY
1601 *  @hw: pointer to hardware structure
1602 **/
1603 STATIC s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1604 {
1605         s32 status;
1606         u32 link_ctrl;
1607
1608         /* Restart auto-negotiation. */
1609         status = hw->mac.ops.read_iosf_sb_reg(hw,
1610                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1611                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1612
1613         if (status) {
1614                 DEBUGOUT("Auto-negotiation did not complete\n");
1615                 return status;
1616         }
1617
1618         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1619         status = hw->mac.ops.write_iosf_sb_reg(hw,
1620                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1621                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1622
1623         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1624                 u32 flx_mask_st20;
1625
1626                 /* Indicate to FW that AN restart has been asserted */
1627                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1628                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1629                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1630
1631                 if (status) {
1632                         DEBUGOUT("Auto-negotiation did not complete\n");
1633                         return status;
1634                 }
1635
1636                 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1637                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1638                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1639                                 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1640         }
1641
1642         return status;
1643 }
1644
1645 #ifndef PREBOOT_SUPPORT
1646 /**
1647  * ixgbe_setup_sgmii - Set up link for sgmii
1648  * @hw: pointer to hardware structure
1649  * @speed: new link speed
1650  * @autoneg_wait: true when waiting for completion is needed
1651  */
1652 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1653                              bool autoneg_wait)
1654 {
1655         struct ixgbe_mac_info *mac = &hw->mac;
1656         u32 lval, sval, flx_val;
1657         s32 rc;
1658
1659         rc = mac->ops.read_iosf_sb_reg(hw,
1660                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1661                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1662         if (rc)
1663                 return rc;
1664
1665         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1666         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1667         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1668         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1669         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1670         rc = mac->ops.write_iosf_sb_reg(hw,
1671                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1672                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1673         if (rc)
1674                 return rc;
1675
1676         rc = mac->ops.read_iosf_sb_reg(hw,
1677                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1678                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1679         if (rc)
1680                 return rc;
1681
1682         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1683         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1684         rc = mac->ops.write_iosf_sb_reg(hw,
1685                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1686                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1687         if (rc)
1688                 return rc;
1689
1690         rc = mac->ops.read_iosf_sb_reg(hw,
1691                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1692                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1693         if (rc)
1694                 return rc;
1695
1696         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1697         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1698         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1699         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1700         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1701
1702         rc = mac->ops.write_iosf_sb_reg(hw,
1703                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1704                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1705         if (rc)
1706                 return rc;
1707
1708         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1709         if (rc)
1710                 return rc;
1711
1712         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1713 }
1714
1715 #endif /* PREBOOT_SUPPORT */
1716 /**
1717  * ixgbe_setup_sgmii_fw - Set up link for internal PHY SGMII auto-negotiation
1718  * @hw: pointer to hardware structure
1719  * @speed: new link speed
1720  * @autoneg_wait: true when waiting for completion is needed
1721  */
1722 STATIC s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1723                                 bool autoneg_wait)
1724 {
1725         struct ixgbe_mac_info *mac = &hw->mac;
1726         u32 lval, sval, flx_val;
1727         s32 rc;
1728
1729         rc = mac->ops.read_iosf_sb_reg(hw,
1730                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1731                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1732         if (rc)
1733                 return rc;
1734
1735         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1736         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1737         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1738         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1739         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1740         rc = mac->ops.write_iosf_sb_reg(hw,
1741                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1742                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1743         if (rc)
1744                 return rc;
1745
1746         rc = mac->ops.read_iosf_sb_reg(hw,
1747                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1748                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1749         if (rc)
1750                 return rc;
1751
1752         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1753         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1754         rc = mac->ops.write_iosf_sb_reg(hw,
1755                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1756                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1757         if (rc)
1758                 return rc;
1759
1760         rc = mac->ops.write_iosf_sb_reg(hw,
1761                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1762                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1763         if (rc)
1764                 return rc;
1765
1766         rc = mac->ops.read_iosf_sb_reg(hw,
1767                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1768                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1769         if (rc)
1770                 return rc;
1771
1772         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1773         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
1774         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1775         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1776         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1777
1778         rc = mac->ops.write_iosf_sb_reg(hw,
1779                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1780                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1781         if (rc)
1782                 return rc;
1783
1784         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1785
1786         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1787 }
1788
1789 /**
1790  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1791  *  @hw: pointer to hardware structure
1792  */
1793 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1794 {
1795         struct ixgbe_mac_info *mac = &hw->mac;
1796
1797         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1798
1799         switch (hw->mac.ops.get_media_type(hw)) {
1800         case ixgbe_media_type_fiber:
1801                 /* CS4227 does not support autoneg, so disable the laser control
1802                  * functions for SFP+ fiber
1803                  */
1804                 mac->ops.disable_tx_laser = NULL;
1805                 mac->ops.enable_tx_laser = NULL;
1806                 mac->ops.flap_tx_laser = NULL;
1807                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1808                 mac->ops.set_rate_select_speed =
1809                                         ixgbe_set_soft_rate_select_speed;
1810
1811                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1812                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1813                         mac->ops.setup_mac_link =
1814                                                 ixgbe_setup_mac_link_sfp_x550a;
1815                 else
1816                         mac->ops.setup_mac_link =
1817                                                 ixgbe_setup_mac_link_sfp_x550em;
1818                 break;
1819         case ixgbe_media_type_copper:
1820                 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T)
1821                         break;
1822                 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1823                         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1824                             hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1825                                 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
1826                                 mac->ops.check_link =
1827                                                    ixgbe_check_mac_link_generic;
1828                         } else {
1829                                 mac->ops.setup_link =
1830                                                   ixgbe_setup_mac_link_t_X550em;
1831                         }
1832                 } else {
1833                         mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1834                         mac->ops.check_link = ixgbe_check_link_t_X550em;
1835                 }
1836                 break;
1837         case ixgbe_media_type_backplane:
1838                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1839                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1840 #ifdef PREBOOT_SUPPORT
1841                         mac->ops.setup_link = ixgbe_setup_sgmii_fw;
1842 #else
1843                         mac->ops.setup_link = ixgbe_setup_sgmii;
1844 #endif /* PREBOOT_SUPPORT */
1845                 break;
1846         default:
1847                 break;
1848         }
1849 }
1850
1851 /**
1852  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1853  *  @hw: pointer to hardware structure
1854  *  @speed: pointer to link speed
1855  *  @autoneg: true when autoneg or autotry is enabled
1856  */
1857 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1858                                        ixgbe_link_speed *speed,
1859                                        bool *autoneg)
1860 {
1861         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1862
1863
1864         if (hw->phy.type == ixgbe_phy_fw) {
1865                 *autoneg = true;
1866                 *speed = hw->phy.speeds_supported;
1867                 return 0;
1868         }
1869
1870         /* SFP */
1871         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1872
1873                 /* CS4227 SFP must not enable auto-negotiation */
1874                 *autoneg = false;
1875
1876                 /* Check if 1G SFP module. */
1877                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1878                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1879                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core0 ||
1880                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core1
1881                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1882                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1883                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1884                         return IXGBE_SUCCESS;
1885                 }
1886
1887                 /* Link capabilities are based on SFP */
1888                 if (hw->phy.multispeed_fiber)
1889                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1890                                  IXGBE_LINK_SPEED_1GB_FULL;
1891                 else
1892                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1893         } else {
1894                 switch (hw->phy.type) {
1895                 case ixgbe_phy_ext_1g_t:
1896 #ifdef PREBOOT_SUPPORT
1897                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1898                         break;
1899 #endif /* PREBOOT_SUPPORT */
1900                 case ixgbe_phy_sgmii:
1901 #ifdef PREBOOT_SUPPORT
1902                         *speed = IXGBE_LINK_SPEED_1GB_FULL |
1903                                  IXGBE_LINK_SPEED_100_FULL |
1904                                  IXGBE_LINK_SPEED_10_FULL;
1905 #else
1906                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1907 #endif /* PREBOOT_SUPPORT */
1908                         break;
1909                 case ixgbe_phy_x550em_kr:
1910                         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1911                                 /* check different backplane modes */
1912                                 if (hw->phy.nw_mng_if_sel &
1913                                            IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
1914                                         *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
1915                                         break;
1916                                 } else if (hw->device_id ==
1917                                                    IXGBE_DEV_ID_X550EM_A_KR_L) {
1918                                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1919                                         break;
1920                                 }
1921                         }
1922                         /* fall through */
1923                 default:
1924                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1925                                  IXGBE_LINK_SPEED_1GB_FULL;
1926                         break;
1927                 }
1928                 *autoneg = true;
1929         }
1930
1931         return IXGBE_SUCCESS;
1932 }
1933
1934 /**
1935  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1936  * @hw: pointer to hardware structure
1937  * @lsc: pointer to boolean flag which indicates whether external Base T
1938  *       PHY interrupt is lsc
1939  *
1940  * Determime if external Base T PHY interrupt cause is high temperature
1941  * failure alarm or link status change.
1942  *
1943  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1944  * failure alarm, else return PHY access status.
1945  */
1946 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1947 {
1948         u32 status;
1949         u16 reg;
1950
1951         *lsc = false;
1952
1953         /* Vendor alarm triggered */
1954         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1955                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1956                                       &reg);
1957
1958         if (status != IXGBE_SUCCESS ||
1959             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1960                 return status;
1961
1962         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1963         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1964                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1965                                       &reg);
1966
1967         if (status != IXGBE_SUCCESS ||
1968             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1969             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1970                 return status;
1971
1972         /* Global alarm triggered */
1973         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1974                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1975                                       &reg);
1976
1977         if (status != IXGBE_SUCCESS)
1978                 return status;
1979
1980         /* If high temperature failure, then return over temp error and exit */
1981         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1982                 /* power down the PHY in case the PHY FW didn't already */
1983                 ixgbe_set_copper_phy_power(hw, false);
1984                 return IXGBE_ERR_OVERTEMP;
1985         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1986                 /*  device fault alarm triggered */
1987                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1988                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1989                                           &reg);
1990
1991                 if (status != IXGBE_SUCCESS)
1992                         return status;
1993
1994                 /* if device fault was due to high temp alarm handle and exit */
1995                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1996                         /* power down the PHY in case the PHY FW didn't */
1997                         ixgbe_set_copper_phy_power(hw, false);
1998                         return IXGBE_ERR_OVERTEMP;
1999                 }
2000         }
2001
2002         /* Vendor alarm 2 triggered */
2003         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2004                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2005
2006         if (status != IXGBE_SUCCESS ||
2007             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2008                 return status;
2009
2010         /* link connect/disconnect event occurred */
2011         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2012                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2013
2014         if (status != IXGBE_SUCCESS)
2015                 return status;
2016
2017         /* Indicate LSC */
2018         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2019                 *lsc = true;
2020
2021         return IXGBE_SUCCESS;
2022 }
2023
2024 /**
2025  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2026  * @hw: pointer to hardware structure
2027  *
2028  * Enable link status change and temperature failure alarm for the external
2029  * Base T PHY
2030  *
2031  * Returns PHY access status
2032  */
2033 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2034 {
2035         u32 status;
2036         u16 reg;
2037         bool lsc;
2038
2039         /* Clear interrupt flags */
2040         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2041
2042         /* Enable link status change alarm */
2043
2044         /* Enable the LASI interrupts on X552 devices to receive notifications
2045          * of the link configurations of the external PHY and correspondingly
2046          * support the configuration of the internal iXFI link, since iXFI does
2047          * not support auto-negotiation. This is not required for X553 devices
2048          * having KR support, which performs auto-negotiations and which is used
2049          * as the internal link to the external PHY. Hence adding a check here
2050          * to avoid enabling LASI interrupts for X553 devices.
2051          */
2052         if (hw->mac.type != ixgbe_mac_X550EM_a) {
2053                 status = hw->phy.ops.read_reg(hw,
2054                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2055                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2056
2057                 if (status != IXGBE_SUCCESS)
2058                         return status;
2059
2060                 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2061
2062                 status = hw->phy.ops.write_reg(hw,
2063                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2064                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2065
2066                 if (status != IXGBE_SUCCESS)
2067                         return status;
2068         }
2069
2070         /* Enable high temperature failure and global fault alarms */
2071         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2072                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2073                                       &reg);
2074
2075         if (status != IXGBE_SUCCESS)
2076                 return status;
2077
2078         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2079                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2080
2081         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2082                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2083                                        reg);
2084
2085         if (status != IXGBE_SUCCESS)
2086                 return status;
2087
2088         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2089         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2090                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2091                                       &reg);
2092
2093         if (status != IXGBE_SUCCESS)
2094                 return status;
2095
2096         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2097                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2098
2099         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2100                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2101                                        reg);
2102
2103         if (status != IXGBE_SUCCESS)
2104                 return status;
2105
2106         /* Enable chip-wide vendor alarm */
2107         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2108                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2109                                       &reg);
2110
2111         if (status != IXGBE_SUCCESS)
2112                 return status;
2113
2114         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2115
2116         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2117                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2118                                        reg);
2119
2120         return status;
2121 }
2122
2123 /**
2124  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2125  *  @hw: pointer to hardware structure
2126  *  @speed: link speed
2127  *
2128  *  Configures the integrated KR PHY.
2129  **/
2130 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2131                                        ixgbe_link_speed speed)
2132 {
2133         s32 status;
2134         u32 reg_val;
2135
2136         status = hw->mac.ops.read_iosf_sb_reg(hw,
2137                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2138                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2139         if (status)
2140                 return status;
2141
2142         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2143         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2144                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2145
2146         /* Advertise 10G support. */
2147         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2148                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2149
2150         /* Advertise 1G support. */
2151         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2152                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2153
2154         status = hw->mac.ops.write_iosf_sb_reg(hw,
2155                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2156                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2157
2158         if (hw->mac.type == ixgbe_mac_X550EM_a) {
2159                 /* Set lane mode  to KR auto negotiation */
2160                 status = hw->mac.ops.read_iosf_sb_reg(hw,
2161                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2162                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2163
2164                 if (status)
2165                         return status;
2166
2167                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2168                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2169                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2170                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2171                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2172
2173                 status = hw->mac.ops.write_iosf_sb_reg(hw,
2174                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2175                                     IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2176         }
2177
2178         return ixgbe_restart_an_internal_phy_x550em(hw);
2179 }
2180
2181 /**
2182  * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
2183  * @hw: pointer to hardware structure
2184  */
2185 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
2186 {
2187         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2188         s32 rc;
2189
2190         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2191                 return IXGBE_SUCCESS;
2192
2193         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
2194         if (rc)
2195                 return rc;
2196         memset(store, 0, sizeof(store));
2197
2198         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
2199         if (rc)
2200                 return rc;
2201
2202         return ixgbe_setup_fw_link(hw);
2203 }
2204
2205 /**
2206  * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
2207  * @hw: pointer to hardware structure
2208  */
2209 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
2210 {
2211         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2212         s32 rc;
2213
2214         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
2215         if (rc)
2216                 return rc;
2217
2218         if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
2219                 ixgbe_shutdown_fw_phy(hw);
2220                 return IXGBE_ERR_OVERTEMP;
2221         }
2222         return IXGBE_SUCCESS;
2223 }
2224
2225 /**
2226  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2227  *  @hw: pointer to hardware structure
2228  *
2229  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
2230  *  values.
2231  **/
2232 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2233 {
2234         /* Save NW management interface connected on board. This is used
2235          * to determine internal PHY mode.
2236          */
2237         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2238
2239         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2240          * PHY address. This register field was has only been used for X552.
2241          */
2242         if (hw->mac.type == ixgbe_mac_X550EM_a &&
2243             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2244                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2245                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2246                                IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2247         }
2248
2249         return IXGBE_SUCCESS;
2250 }
2251
2252 /**
2253  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2254  *  @hw: pointer to hardware structure
2255  *
2256  *  Initialize any function pointers that were not able to be
2257  *  set during init_shared_code because the PHY/SFP type was
2258  *  not known.  Perform the SFP init if necessary.
2259  */
2260 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2261 {
2262         struct ixgbe_phy_info *phy = &hw->phy;
2263         s32 ret_val;
2264
2265         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2266
2267         hw->mac.ops.set_lan_id(hw);
2268         ixgbe_read_mng_if_sel_x550em(hw);
2269
2270         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2271                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2272                 ixgbe_setup_mux_ctl(hw);
2273                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2274         }
2275
2276         switch (hw->device_id) {
2277         case IXGBE_DEV_ID_X550EM_A_1G_T:
2278         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2279                 phy->ops.read_reg_mdi = NULL;
2280                 phy->ops.write_reg_mdi = NULL;
2281                 hw->phy.ops.read_reg = NULL;
2282                 hw->phy.ops.write_reg = NULL;
2283                 phy->ops.check_overtemp = ixgbe_check_overtemp_fw;
2284                 if (hw->bus.lan_id)
2285                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2286                 else
2287                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2288
2289                 break;
2290         case IXGBE_DEV_ID_X550EM_A_10G_T:
2291         case IXGBE_DEV_ID_X550EM_A_SFP:
2292                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2293                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2294                 if (hw->bus.lan_id)
2295                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2296                 else
2297                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2298                 break;
2299         case IXGBE_DEV_ID_X550EM_X_SFP:
2300                 /* set up for CS4227 usage */
2301                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2302                 break;
2303         case IXGBE_DEV_ID_X550EM_X_1G_T:
2304                 phy->ops.read_reg_mdi = NULL;
2305                 phy->ops.write_reg_mdi = NULL;
2306         default:
2307                 break;
2308         }
2309
2310         /* Identify the PHY or SFP module */
2311         ret_val = phy->ops.identify(hw);
2312         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED ||
2313             ret_val == IXGBE_ERR_PHY_ADDR_INVALID)
2314                 return ret_val;
2315
2316         /* Setup function pointers based on detected hardware */
2317         ixgbe_init_mac_link_ops_X550em(hw);
2318         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2319                 phy->ops.reset = NULL;
2320
2321         /* Set functions pointers based on phy type */
2322         switch (hw->phy.type) {
2323         case ixgbe_phy_x550em_kx4:
2324                 phy->ops.setup_link = NULL;
2325                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2326                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2327                 break;
2328         case ixgbe_phy_x550em_kr:
2329                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2330                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2331                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2332                 break;
2333         case ixgbe_phy_ext_1g_t:
2334                 /* link is managed by FW */
2335                 phy->ops.setup_link = NULL;
2336                 phy->ops.reset = NULL;
2337                 break;
2338         case ixgbe_phy_x550em_xfi:
2339                 /* link is managed by HW */
2340                 phy->ops.setup_link = NULL;
2341                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2342                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2343                 break;
2344         case ixgbe_phy_x550em_ext_t:
2345                 /* If internal link mode is XFI, then setup iXFI internal link,
2346                  * else setup KR now.
2347                  */
2348                 phy->ops.setup_internal_link =
2349                                               ixgbe_setup_internal_phy_t_x550em;
2350
2351                 /* setup SW LPLU only for first revision of X550EM_x */
2352                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2353                     !(IXGBE_FUSES0_REV_MASK &
2354                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2355                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2356
2357                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2358                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2359                 break;
2360         case ixgbe_phy_sgmii:
2361                 phy->ops.setup_link = NULL;
2362                 break;
2363         case ixgbe_phy_fw:
2364                 phy->ops.setup_link = ixgbe_setup_fw_link;
2365                 phy->ops.reset = ixgbe_reset_phy_fw;
2366                 break;
2367         default:
2368                 break;
2369         }
2370         return ret_val;
2371 }
2372
2373 /**
2374  * ixgbe_set_mdio_speed - Set MDIO clock speed
2375  *  @hw: pointer to hardware structure
2376  */
2377 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2378 {
2379         u32 hlreg0;
2380
2381         switch (hw->device_id) {
2382         case IXGBE_DEV_ID_X550EM_X_10G_T:
2383         case IXGBE_DEV_ID_X550EM_A_SGMII:
2384         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2385         case IXGBE_DEV_ID_X550EM_A_10G_T:
2386         case IXGBE_DEV_ID_X550EM_A_SFP:
2387         case IXGBE_DEV_ID_X550EM_A_QSFP:
2388                 /* Config MDIO clock speed before the first MDIO PHY access */
2389                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2390                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2391                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2392                 break;
2393         case IXGBE_DEV_ID_X550EM_A_1G_T:
2394         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2395                 /* Select fast MDIO clock speed for these devices */
2396                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2397                 hlreg0 |= IXGBE_HLREG0_MDCSPD;
2398                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2399                 break;
2400         default:
2401                 break;
2402         }
2403 }
2404
2405 /**
2406  *  ixgbe_reset_hw_X550em - Perform hardware reset
2407  *  @hw: pointer to hardware structure
2408  *
2409  *  Resets the hardware by resetting the transmit and receive units, masks
2410  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2411  *  reset.
2412  */
2413 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2414 {
2415         ixgbe_link_speed link_speed;
2416         s32 status;
2417         u32 ctrl = 0;
2418         u32 i;
2419         bool link_up = false;
2420         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2421
2422         DEBUGFUNC("ixgbe_reset_hw_X550em");
2423
2424         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2425         status = hw->mac.ops.stop_adapter(hw);
2426         if (status != IXGBE_SUCCESS) {
2427                 DEBUGOUT1("Failed to stop adapter, STATUS = %d\n", status);
2428                 return status;
2429         }
2430         /* flush pending Tx transactions */
2431         ixgbe_clear_tx_pending(hw);
2432
2433         ixgbe_set_mdio_speed(hw);
2434
2435         /* PHY ops must be identified and initialized prior to reset */
2436         status = hw->phy.ops.init(hw);
2437
2438         if (status)
2439                 DEBUGOUT1("Failed to initialize PHY ops, STATUS = %d\n",
2440                           status);
2441
2442         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED ||
2443             status == IXGBE_ERR_PHY_ADDR_INVALID) {
2444                 DEBUGOUT("Returning from reset HW due to PHY init failure\n");
2445                 return status;
2446         }
2447
2448         /* start the external PHY */
2449         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2450                 status = ixgbe_init_ext_t_x550em(hw);
2451                 if (status) {
2452                         DEBUGOUT1("Failed to start the external PHY, STATUS = %d\n",
2453                                   status);
2454                         return status;
2455                 }
2456         }
2457
2458         /* Setup SFP module if there is one present. */
2459         if (hw->phy.sfp_setup_needed) {
2460                 status = hw->mac.ops.setup_sfp(hw);
2461                 hw->phy.sfp_setup_needed = false;
2462         }
2463
2464         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2465                 return status;
2466
2467         /* Reset PHY */
2468         if (!hw->phy.reset_disable && hw->phy.ops.reset) {
2469                 if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP)
2470                         return IXGBE_ERR_OVERTEMP;
2471         }
2472
2473 mac_reset_top:
2474         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2475          * If link reset is used when link is up, it might reset the PHY when
2476          * mng is using it.  If link is down or the flag to force full link
2477          * reset is set, then perform link reset.
2478          */
2479         ctrl = IXGBE_CTRL_LNK_RST;
2480         if (!hw->force_full_reset) {
2481                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2482                 if (link_up)
2483                         ctrl = IXGBE_CTRL_RST;
2484         }
2485
2486         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2487         if (status != IXGBE_SUCCESS) {
2488                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
2489                         "semaphore failed with %d", status);
2490                 return IXGBE_ERR_SWFW_SYNC;
2491         }
2492         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2493         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2494         IXGBE_WRITE_FLUSH(hw);
2495         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2496
2497         /* Poll for reset bit to self-clear meaning reset is complete */
2498         for (i = 0; i < 10; i++) {
2499                 usec_delay(1);
2500                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2501                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2502                         break;
2503         }
2504
2505         if (ctrl & IXGBE_CTRL_RST_MASK) {
2506                 status = IXGBE_ERR_RESET_FAILED;
2507                 DEBUGOUT("Reset polling failed to complete.\n");
2508         }
2509
2510         msec_delay(50);
2511
2512         /* Double resets are required for recovery from certain error
2513          * conditions.  Between resets, it is necessary to stall to
2514          * allow time for any pending HW events to complete.
2515          */
2516         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2517                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2518                 goto mac_reset_top;
2519         }
2520
2521         /* Store the permanent mac address */
2522         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2523
2524         /* Store MAC address from RAR0, clear receive address registers, and
2525          * clear the multicast table.  Also reset num_rar_entries to 128,
2526          * since we modify this value when programming the SAN MAC address.
2527          */
2528         hw->mac.num_rar_entries = 128;
2529         hw->mac.ops.init_rx_addrs(hw);
2530
2531         ixgbe_set_mdio_speed(hw);
2532
2533         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2534                 ixgbe_setup_mux_ctl(hw);
2535
2536         if (status != IXGBE_SUCCESS)
2537                 DEBUGOUT1("Reset HW failed, STATUS = %d\n", status);
2538
2539         return status;
2540 }
2541
2542 /**
2543  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2544  * @hw: pointer to hardware structure
2545  */
2546 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2547 {
2548         u32 status;
2549         u16 reg;
2550
2551         status = hw->phy.ops.read_reg(hw,
2552                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2553                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2554                                       &reg);
2555
2556         if (status != IXGBE_SUCCESS)
2557                 return status;
2558
2559         /* If PHY FW reset completed bit is set then this is the first
2560          * SW instance after a power on so the PHY FW must be un-stalled.
2561          */
2562         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2563                 status = hw->phy.ops.read_reg(hw,
2564                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2565                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2566                                         &reg);
2567
2568                 if (status != IXGBE_SUCCESS)
2569                         return status;
2570
2571                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2572
2573                 status = hw->phy.ops.write_reg(hw,
2574                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2575                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2576                                         reg);
2577
2578                 if (status != IXGBE_SUCCESS)
2579                         return status;
2580         }
2581
2582         return status;
2583 }
2584
2585 /**
2586  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2587  *  @hw: pointer to hardware structure
2588  **/
2589 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2590 {
2591         /* leave link alone for 2.5G */
2592         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
2593                 return IXGBE_SUCCESS;
2594
2595         if (ixgbe_check_reset_blocked(hw))
2596                 return 0;
2597
2598         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2599 }
2600
2601 /**
2602  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2603  *  @hw: pointer to hardware structure
2604  *  @speed: new link speed
2605  *  @autoneg_wait_to_complete: unused
2606  *
2607  *  Configure the external PHY and the integrated KR PHY for SFP support.
2608  **/
2609 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2610                                     ixgbe_link_speed speed,
2611                                     bool autoneg_wait_to_complete)
2612 {
2613         s32 ret_val;
2614         u16 reg_slice, reg_val;
2615         bool setup_linear = false;
2616         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2617
2618         /* Check if SFP module is supported and linear */
2619         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2620
2621         /* If no SFP module present, then return success. Return success since
2622          * there is no reason to configure CS4227 and SFP not present error is
2623          * not excepted in the setup MAC link flow.
2624          */
2625         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2626                 return IXGBE_SUCCESS;
2627
2628         if (ret_val != IXGBE_SUCCESS)
2629                 return ret_val;
2630
2631         /* Configure internal PHY for KR/KX. */
2632         ixgbe_setup_kr_speed_x550em(hw, speed);
2633
2634         /* Configure CS4227 LINE side to proper mode. */
2635         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2636                     (hw->bus.lan_id << 12);
2637         if (setup_linear)
2638                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2639         else
2640                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2641         ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2642                                           reg_val);
2643         return ret_val;
2644 }
2645
2646 /**
2647  *  ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
2648  *  @hw: pointer to hardware structure
2649  *  @speed: the link speed to force
2650  *
2651  *  Configures the integrated PHY for native SFI mode. Used to connect the
2652  *  internal PHY directly to an SFP cage, without autonegotiation.
2653  **/
2654 STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2655 {
2656         struct ixgbe_mac_info *mac = &hw->mac;
2657         s32 status;
2658         u32 reg_val;
2659
2660         /* Disable all AN and force speed to 10G Serial. */
2661         status = mac->ops.read_iosf_sb_reg(hw,
2662                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2663                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2664         if (status != IXGBE_SUCCESS)
2665                 return status;
2666
2667         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2668         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2669         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2670         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2671
2672         /* Select forced link speed for internal PHY. */
2673         switch (*speed) {
2674         case IXGBE_LINK_SPEED_10GB_FULL:
2675                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2676                 break;
2677         case IXGBE_LINK_SPEED_1GB_FULL:
2678                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2679                 break;
2680         default:
2681                 /* Other link speeds are not supported by internal PHY. */
2682                 return IXGBE_ERR_LINK_SETUP;
2683         }
2684
2685         status = mac->ops.write_iosf_sb_reg(hw,
2686                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2687                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2688
2689         /* Toggle port SW reset by AN reset. */
2690         status = ixgbe_restart_an_internal_phy_x550em(hw);
2691
2692         return status;
2693 }
2694
2695 /**
2696  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2697  *  @hw: pointer to hardware structure
2698  *  @speed: new link speed
2699  *  @autoneg_wait_to_complete: unused
2700  *
2701  *  Configure the integrated PHY for SFP support.
2702  **/
2703 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2704                                     ixgbe_link_speed speed,
2705                                     bool autoneg_wait_to_complete)
2706 {
2707         s32 ret_val;
2708         u16 reg_phy_ext;
2709         bool setup_linear = false;
2710         u32 reg_slice, reg_phy_int, slice_offset;
2711
2712         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2713
2714         /* Check if SFP module is supported and linear */
2715         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2716
2717         /* If no SFP module present, then return success. Return success since
2718          * SFP not present error is not excepted in the setup MAC link flow.
2719          */
2720         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2721                 return IXGBE_SUCCESS;
2722
2723         if (ret_val != IXGBE_SUCCESS)
2724                 return ret_val;
2725
2726         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2727                 /* Configure internal PHY for native SFI based on module type */
2728                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2729                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2730                                    IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
2731
2732                 if (ret_val != IXGBE_SUCCESS)
2733                         return ret_val;
2734
2735                 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
2736                 if (!setup_linear)
2737                         reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
2738
2739                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2740                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2741                                    IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2742
2743                 if (ret_val != IXGBE_SUCCESS)
2744                         return ret_val;
2745
2746                 /* Setup SFI internal link. */
2747                 ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
2748         } else {
2749                 /* Configure internal PHY for KR/KX. */
2750                 ixgbe_setup_kr_speed_x550em(hw, speed);
2751
2752                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2753                         /* Find Address */
2754                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2755                         return IXGBE_ERR_PHY_ADDR_INVALID;
2756                 }
2757
2758                 /* Get external PHY SKU id */
2759                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
2760                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2761
2762                 if (ret_val != IXGBE_SUCCESS)
2763                         return ret_val;
2764
2765                 /* When configuring quad port CS4223, the MAC instance is part
2766                  * of the slice offset.
2767                  */
2768                 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
2769                         slice_offset = (hw->bus.lan_id +
2770                                         (hw->bus.instance_id << 1)) << 12;
2771                 else
2772                         slice_offset = hw->bus.lan_id << 12;
2773
2774                 /* Configure CS4227/CS4223 LINE side to proper mode. */
2775                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2776
2777                 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
2778                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2779
2780                 if (ret_val != IXGBE_SUCCESS)
2781                         return ret_val;
2782
2783                 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
2784                                  (IXGBE_CS4227_EDC_MODE_SR << 1));
2785
2786                 if (setup_linear)
2787                         reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2788                 else
2789                         reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2790                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2791                                          IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2792
2793                 /* Flush previous write with a read */
2794                 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
2795                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2796         }
2797         return ret_val;
2798 }
2799
2800 /**
2801  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2802  *  @hw: pointer to hardware structure
2803  *
2804  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2805  **/
2806 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2807 {
2808         struct ixgbe_mac_info *mac = &hw->mac;
2809         s32 status;
2810         u32 reg_val;
2811
2812         /* Disable training protocol FSM. */
2813         status = mac->ops.read_iosf_sb_reg(hw,
2814                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2815                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2816         if (status != IXGBE_SUCCESS)
2817                 return status;
2818         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2819         status = mac->ops.write_iosf_sb_reg(hw,
2820                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2821                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2822         if (status != IXGBE_SUCCESS)
2823                 return status;
2824
2825         /* Disable Flex from training TXFFE. */
2826         status = mac->ops.read_iosf_sb_reg(hw,
2827                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2828                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2829         if (status != IXGBE_SUCCESS)
2830                 return status;
2831         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2832         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2833         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2834         status = mac->ops.write_iosf_sb_reg(hw,
2835                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2836                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2837         if (status != IXGBE_SUCCESS)
2838                 return status;
2839         status = mac->ops.read_iosf_sb_reg(hw,
2840                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2841                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2842         if (status != IXGBE_SUCCESS)
2843                 return status;
2844         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2845         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2846         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2847         status = mac->ops.write_iosf_sb_reg(hw,
2848                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2849                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2850         if (status != IXGBE_SUCCESS)
2851                 return status;
2852
2853         /* Enable override for coefficients. */
2854         status = mac->ops.read_iosf_sb_reg(hw,
2855                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2856                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2857         if (status != IXGBE_SUCCESS)
2858                 return status;
2859         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2860         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2861         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2862         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2863         status = mac->ops.write_iosf_sb_reg(hw,
2864                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2865                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2866         return status;
2867 }
2868
2869 /**
2870  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2871  *  @hw: pointer to hardware structure
2872  *  @speed: the link speed to force
2873  *
2874  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
2875  *  internal and external PHY at a specific speed, without autonegotiation.
2876  **/
2877 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2878 {
2879         struct ixgbe_mac_info *mac = &hw->mac;
2880         s32 status;
2881         u32 reg_val;
2882
2883         /* iXFI is only supported with X552 */
2884         if (mac->type != ixgbe_mac_X550EM_x)
2885                 return IXGBE_ERR_LINK_SETUP;
2886
2887         /* Disable AN and force speed to 10G Serial. */
2888         status = mac->ops.read_iosf_sb_reg(hw,
2889                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2890                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2891         if (status != IXGBE_SUCCESS)
2892                 return status;
2893
2894         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2895         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2896
2897         /* Select forced link speed for internal PHY. */
2898         switch (*speed) {
2899         case IXGBE_LINK_SPEED_10GB_FULL:
2900                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2901                 break;
2902         case IXGBE_LINK_SPEED_1GB_FULL:
2903                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2904                 break;
2905         default:
2906                 /* Other link speeds are not supported by internal KR PHY. */
2907                 return IXGBE_ERR_LINK_SETUP;
2908         }
2909
2910         status = mac->ops.write_iosf_sb_reg(hw,
2911                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2912                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2913         if (status != IXGBE_SUCCESS)
2914                 return status;
2915
2916         /* Additional configuration needed for x550em_x */
2917         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2918                 status = ixgbe_setup_ixfi_x550em_x(hw);
2919                 if (status != IXGBE_SUCCESS)
2920                         return status;
2921         }
2922
2923         /* Toggle port SW reset by AN reset. */
2924         status = ixgbe_restart_an_internal_phy_x550em(hw);
2925
2926         return status;
2927 }
2928
2929 /**
2930  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2931  * @hw: address of hardware structure
2932  * @link_up: address of boolean to indicate link status
2933  *
2934  * Returns error code if unable to get link status.
2935  */
2936 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2937 {
2938         u32 ret;
2939         u16 autoneg_status;
2940
2941         *link_up = false;
2942
2943         /* read this twice back to back to indicate current status */
2944         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2945                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2946                                    &autoneg_status);
2947         if (ret != IXGBE_SUCCESS)
2948                 return ret;
2949
2950         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2951                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2952                                    &autoneg_status);
2953         if (ret != IXGBE_SUCCESS)
2954                 return ret;
2955
2956         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2957
2958         return IXGBE_SUCCESS;
2959 }
2960
2961 /**
2962  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2963  * @hw: point to hardware structure
2964  *
2965  * Configures the link between the integrated KR PHY and the external X557 PHY
2966  * The driver will call this function when it gets a link status change
2967  * interrupt from the X557 PHY. This function configures the link speed
2968  * between the PHYs to match the link speed of the BASE-T link.
2969  *
2970  * A return of a non-zero value indicates an error, and the base driver should
2971  * not report link up.
2972  */
2973 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2974 {
2975         ixgbe_link_speed force_speed;
2976         bool link_up;
2977         u32 status;
2978         u16 speed;
2979
2980         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2981                 return IXGBE_ERR_CONFIG;
2982
2983         if (hw->mac.type == ixgbe_mac_X550EM_x &&
2984             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2985                 /* If link is down, there is no setup necessary so return  */
2986                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2987                 if (status != IXGBE_SUCCESS)
2988                         return status;
2989
2990                 if (!link_up)
2991                         return IXGBE_SUCCESS;
2992
2993                 status = hw->phy.ops.read_reg(hw,
2994                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2995                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2996                                               &speed);
2997                 if (status != IXGBE_SUCCESS)
2998                         return status;
2999
3000                 /* If link is still down - no setup is required so return */
3001                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3002                 if (status != IXGBE_SUCCESS)
3003                         return status;
3004                 if (!link_up)
3005                         return IXGBE_SUCCESS;
3006
3007                 /* clear everything but the speed and duplex bits */
3008                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3009
3010                 switch (speed) {
3011                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3012                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3013                         break;
3014                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3015                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3016                         break;
3017                 default:
3018                         /* Internal PHY does not support anything else */
3019                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
3020                 }
3021
3022                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3023         } else {
3024                 speed = IXGBE_LINK_SPEED_10GB_FULL |
3025                         IXGBE_LINK_SPEED_1GB_FULL;
3026                 return ixgbe_setup_kr_speed_x550em(hw, speed);
3027         }
3028 }
3029
3030 /**
3031  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3032  *  @hw: pointer to hardware structure
3033  *
3034  *  Configures the integrated KR PHY to use internal loopback mode.
3035  **/
3036 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3037 {
3038         s32 status;
3039         u32 reg_val;
3040
3041         /* Disable AN and force speed to 10G Serial. */
3042         status = hw->mac.ops.read_iosf_sb_reg(hw,
3043                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3044                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3045         if (status != IXGBE_SUCCESS)
3046                 return status;
3047         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3048         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3049         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3050         status = hw->mac.ops.write_iosf_sb_reg(hw,
3051                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3052                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3053         if (status != IXGBE_SUCCESS)
3054                 return status;
3055
3056         /* Set near-end loopback clocks. */
3057         status = hw->mac.ops.read_iosf_sb_reg(hw,
3058                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3059                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3060         if (status != IXGBE_SUCCESS)
3061                 return status;
3062         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3063         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3064         status = hw->mac.ops.write_iosf_sb_reg(hw,
3065                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3066                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3067         if (status != IXGBE_SUCCESS)
3068                 return status;
3069
3070         /* Set loopback enable. */
3071         status = hw->mac.ops.read_iosf_sb_reg(hw,
3072                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3073                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3074         if (status != IXGBE_SUCCESS)
3075                 return status;
3076         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3077         status = hw->mac.ops.write_iosf_sb_reg(hw,
3078                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3079                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3080         if (status != IXGBE_SUCCESS)
3081                 return status;
3082
3083         /* Training bypass. */
3084         status = hw->mac.ops.read_iosf_sb_reg(hw,
3085                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3086                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3087         if (status != IXGBE_SUCCESS)
3088                 return status;
3089         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3090         status = hw->mac.ops.write_iosf_sb_reg(hw,
3091                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3092                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3093
3094         return status;
3095 }
3096
3097 /**
3098  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3099  *  assuming that the semaphore is already obtained.
3100  *  @hw: pointer to hardware structure
3101  *  @offset: offset of  word in the EEPROM to read
3102  *  @data: word read from the EEPROM
3103  *
3104  *  Reads a 16 bit word from the EEPROM using the hostif.
3105  **/
3106 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
3107 {
3108         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3109         struct ixgbe_hic_read_shadow_ram buffer;
3110         s32 status;
3111
3112         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3113         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3114         buffer.hdr.req.buf_lenh = 0;
3115         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3116         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3117
3118         /* convert offset from words to bytes */
3119         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3120         /* one word */
3121         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3122         buffer.pad2 = 0;
3123         buffer.pad3 = 0;
3124
3125         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3126         if (status)
3127                 return status;
3128
3129         status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3130                                     IXGBE_HI_COMMAND_TIMEOUT);
3131         if (!status) {
3132                 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3133                                                   FW_NVM_DATA_OFFSET);
3134         }
3135
3136         hw->mac.ops.release_swfw_sync(hw, mask);
3137         return status;
3138 }
3139
3140 /**
3141  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3142  *  @hw: pointer to hardware structure
3143  *  @offset: offset of  word in the EEPROM to read
3144  *  @words: number of words
3145  *  @data: word(s) read from the EEPROM
3146  *
3147  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
3148  **/
3149 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3150                                      u16 offset, u16 words, u16 *data)
3151 {
3152         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3153         struct ixgbe_hic_read_shadow_ram buffer;
3154         u32 current_word = 0;
3155         u16 words_to_read;
3156         s32 status;
3157         u32 i;
3158
3159         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3160
3161         /* Take semaphore for the entire operation. */
3162         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3163         if (status) {
3164                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3165                 return status;
3166         }
3167
3168         while (words) {
3169                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3170                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3171                 else
3172                         words_to_read = words;
3173
3174                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3175                 buffer.hdr.req.buf_lenh = 0;
3176                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3177                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3178
3179                 /* convert offset from words to bytes */
3180                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3181                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3182                 buffer.pad2 = 0;
3183                 buffer.pad3 = 0;
3184
3185                 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3186                                             IXGBE_HI_COMMAND_TIMEOUT);
3187
3188                 if (status) {
3189                         DEBUGOUT("Host interface command failed\n");
3190                         goto out;
3191                 }
3192
3193                 for (i = 0; i < words_to_read; i++) {
3194                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3195                                   2 * i;
3196                         u32 value = IXGBE_READ_REG(hw, reg);
3197
3198                         data[current_word] = (u16)(value & 0xffff);
3199                         current_word++;
3200                         i++;
3201                         if (i < words_to_read) {
3202                                 value >>= 16;
3203                                 data[current_word] = (u16)(value & 0xffff);
3204                                 current_word++;
3205                         }
3206                 }
3207                 words -= words_to_read;
3208         }
3209
3210 out:
3211         hw->mac.ops.release_swfw_sync(hw, mask);
3212         return status;
3213 }
3214
3215 /**
3216  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3217  *  @hw: pointer to hardware structure
3218  *  @offset: offset of  word in the EEPROM to write
3219  *  @data: word write to the EEPROM
3220  *
3221  *  Write a 16 bit word to the EEPROM using the hostif.
3222  **/
3223 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3224                                     u16 data)
3225 {
3226         s32 status;
3227         struct ixgbe_hic_write_shadow_ram buffer;
3228
3229         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3230
3231         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3232         buffer.hdr.req.buf_lenh = 0;
3233         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3234         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3235
3236          /* one word */
3237         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3238         buffer.data = data;
3239         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3240
3241         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3242                                               sizeof(buffer),
3243                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3244
3245         return status;
3246 }
3247
3248 /**
3249  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3250  *  @hw: pointer to hardware structure
3251  *  @offset: offset of  word in the EEPROM to write
3252  *  @data: word write to the EEPROM
3253  *
3254  *  Write a 16 bit word to the EEPROM using the hostif.
3255  **/
3256 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3257                                u16 data)
3258 {
3259         s32 status = IXGBE_SUCCESS;
3260
3261         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3262
3263         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3264             IXGBE_SUCCESS) {
3265                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3266                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3267         } else {
3268                 DEBUGOUT("write ee hostif failed to get semaphore");
3269                 status = IXGBE_ERR_SWFW_SYNC;
3270         }
3271
3272         return status;
3273 }
3274
3275 /**
3276  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3277  *  @hw: pointer to hardware structure
3278  *  @offset: offset of  word in the EEPROM to write
3279  *  @words: number of words
3280  *  @data: word(s) write to the EEPROM
3281  *
3282  *  Write a 16 bit word(s) to the EEPROM using the hostif.
3283  **/
3284 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3285                                       u16 offset, u16 words, u16 *data)
3286 {
3287         s32 status = IXGBE_SUCCESS;
3288         u32 i = 0;
3289
3290         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3291
3292         /* Take semaphore for the entire operation. */
3293         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3294         if (status != IXGBE_SUCCESS) {
3295                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3296                 goto out;
3297         }
3298
3299         for (i = 0; i < words; i++) {
3300                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3301                                                          data[i]);
3302
3303                 if (status != IXGBE_SUCCESS) {
3304                         DEBUGOUT("Eeprom buffered write failed\n");
3305                         break;
3306                 }
3307         }
3308
3309         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3310 out:
3311
3312         return status;
3313 }
3314
3315 /**
3316  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3317  * @hw: pointer to hardware structure
3318  * @ptr: pointer offset in eeprom
3319  * @size: size of section pointed by ptr, if 0 first word will be used as size
3320  * @csum: address of checksum to update
3321  * @buffer: pointer to buffer containing calculated checksum
3322  * @buffer_size: size of buffer
3323  *
3324  * Returns error status for any failure
3325  */
3326 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3327                                    u16 size, u16 *csum, u16 *buffer,
3328                                    u32 buffer_size)
3329 {
3330         u16 buf[256];
3331         s32 status;
3332         u16 length, bufsz, i, start;
3333         u16 *local_buffer;
3334
3335         bufsz = sizeof(buf) / sizeof(buf[0]);
3336
3337         /* Read a chunk at the pointer location */
3338         if (!buffer) {
3339                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3340                 if (status) {
3341                         DEBUGOUT("Failed to read EEPROM image\n");
3342                         return status;
3343                 }
3344                 local_buffer = buf;
3345         } else {
3346                 if (buffer_size < ptr)
3347                         return  IXGBE_ERR_PARAM;
3348                 local_buffer = &buffer[ptr];
3349         }
3350
3351         if (size) {
3352                 start = 0;
3353                 length = size;
3354         } else {
3355                 start = 1;
3356                 length = local_buffer[0];
3357
3358                 /* Skip pointer section if length is invalid. */
3359                 if (length == 0xFFFF || length == 0 ||
3360                     (ptr + length) >= hw->eeprom.word_size)
3361                         return IXGBE_SUCCESS;
3362         }
3363
3364         if (buffer && ((u32)start + (u32)length > buffer_size))
3365                 return IXGBE_ERR_PARAM;
3366
3367         for (i = start; length; i++, length--) {
3368                 if (i == bufsz && !buffer) {
3369                         ptr += bufsz;
3370                         i = 0;
3371                         if (length < bufsz)
3372                                 bufsz = length;
3373
3374                         /* Read a chunk at the pointer location */
3375                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3376                                                                   bufsz, buf);
3377                         if (status) {
3378                                 DEBUGOUT("Failed to read EEPROM image\n");
3379                                 return status;
3380                         }
3381                 }
3382                 *csum += local_buffer[i];
3383         }
3384         return IXGBE_SUCCESS;
3385 }
3386
3387 /**
3388  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3389  *  @hw: pointer to hardware structure
3390  *  @buffer: pointer to buffer containing calculated checksum
3391  *  @buffer_size: size of buffer
3392  *
3393  *  Returns a negative error code on error, or the 16-bit checksum
3394  **/
3395 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3396 {
3397         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3398         u16 *local_buffer;
3399         s32 status;
3400         u16 checksum = 0;
3401         u16 pointer, i, size;
3402
3403         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3404
3405         hw->eeprom.ops.init_params(hw);
3406
3407         if (!buffer) {
3408                 /* Read pointer area */
3409                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3410                                                      IXGBE_EEPROM_LAST_WORD + 1,
3411                                                      eeprom_ptrs);
3412                 if (status) {
3413                         DEBUGOUT("Failed to read EEPROM image\n");
3414                         return status;
3415                 }
3416                 local_buffer = eeprom_ptrs;
3417         } else {
3418                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3419                         return IXGBE_ERR_PARAM;
3420                 local_buffer = buffer;
3421         }
3422
3423         /*
3424          * For X550 hardware include 0x0-0x41 in the checksum, skip the
3425          * checksum word itself
3426          */
3427         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3428                 if (i != IXGBE_EEPROM_CHECKSUM)
3429                         checksum += local_buffer[i];
3430
3431         /*
3432          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
3433          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3434          */
3435         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3436                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3437                         continue;
3438
3439                 pointer = local_buffer[i];
3440
3441                 /* Skip pointer section if the pointer is invalid. */
3442                 if (pointer == 0xFFFF || pointer == 0 ||
3443                     pointer >= hw->eeprom.word_size)
3444                         continue;
3445
3446                 switch (i) {
3447                 case IXGBE_PCIE_GENERAL_PTR:
3448                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3449                         break;
3450                 case IXGBE_PCIE_CONFIG0_PTR:
3451                 case IXGBE_PCIE_CONFIG1_PTR:
3452                         size = IXGBE_PCIE_CONFIG_SIZE;
3453                         break;
3454                 default:
3455                         size = 0;
3456                         break;
3457                 }
3458
3459                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3460                                                 buffer, buffer_size);
3461                 if (status)
3462                         return status;
3463         }
3464
3465         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3466
3467         return (s32)checksum;
3468 }
3469
3470 /**
3471  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3472  *  @hw: pointer to hardware structure
3473  *
3474  *  Returns a negative error code on error, or the 16-bit checksum
3475  **/
3476 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3477 {
3478         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3479 }
3480
3481 /**
3482  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3483  *  @hw: pointer to hardware structure
3484  *  @checksum_val: calculated checksum
3485  *
3486  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3487  *  caller does not need checksum_val, the value can be NULL.
3488  **/
3489 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3490 {
3491         s32 status;
3492         u16 checksum;
3493         u16 read_checksum = 0;
3494
3495         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3496
3497         /* Read the first word from the EEPROM. If this times out or fails, do
3498          * not continue or we could be in for a very long wait while every
3499          * EEPROM read fails
3500          */
3501         status = hw->eeprom.ops.read(hw, 0, &checksum);
3502         if (status) {
3503                 DEBUGOUT("EEPROM read failed\n");
3504                 return status;
3505         }
3506
3507         status = hw->eeprom.ops.calc_checksum(hw);
3508         if (status < 0)
3509                 return status;
3510
3511         checksum = (u16)(status & 0xffff);
3512
3513         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3514                                            &read_checksum);
3515         if (status)
3516                 return status;
3517
3518         /* Verify read checksum from EEPROM is the same as
3519          * calculated checksum
3520          */
3521         if (read_checksum != checksum) {
3522                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3523                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3524                              "Invalid EEPROM checksum");
3525         }
3526
3527         /* If the user cares, return the calculated checksum */
3528         if (checksum_val)
3529                 *checksum_val = checksum;
3530
3531         return status;
3532 }
3533
3534 /**
3535  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3536  * @hw: pointer to hardware structure
3537  *
3538  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3539  * checksum and updates the EEPROM and instructs the hardware to update
3540  * the flash.
3541  **/
3542 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3543 {
3544         s32 status;
3545         u16 checksum = 0;
3546
3547         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3548
3549         /* Read the first word from the EEPROM. If this times out or fails, do
3550          * not continue or we could be in for a very long wait while every
3551          * EEPROM read fails
3552          */
3553         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3554         if (status) {
3555                 DEBUGOUT("EEPROM read failed\n");
3556                 return status;
3557         }
3558
3559         status = ixgbe_calc_eeprom_checksum_X550(hw);
3560         if (status < 0)
3561                 return status;
3562
3563         checksum = (u16)(status & 0xffff);
3564
3565         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3566                                             checksum);
3567         if (status)
3568                 return status;
3569
3570         status = ixgbe_update_flash_X550(hw);
3571
3572         return status;
3573 }
3574
3575 /**
3576  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3577  *  @hw: pointer to hardware structure
3578  *
3579  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3580  **/
3581 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3582 {
3583         s32 status = IXGBE_SUCCESS;
3584         union ixgbe_hic_hdr2 buffer;
3585
3586         DEBUGFUNC("ixgbe_update_flash_X550");
3587
3588         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3589         buffer.req.buf_lenh = 0;
3590         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3591         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3592
3593         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3594                                               sizeof(buffer),
3595                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3596
3597         return status;
3598 }
3599
3600 /**
3601  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3602  *  @hw: pointer to hardware structure
3603  *
3604  *  Determines physical layer capabilities of the current configuration.
3605  **/
3606 u64 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3607 {
3608         u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3609         u16 ext_ability = 0;
3610
3611         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3612
3613         hw->phy.ops.identify(hw);
3614
3615         switch (hw->phy.type) {
3616         case ixgbe_phy_x550em_kr:
3617                 if (hw->mac.type == ixgbe_mac_X550EM_a) {
3618                         if (hw->phy.nw_mng_if_sel &
3619                             IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
3620                                 physical_layer =
3621                                         IXGBE_PHYSICAL_LAYER_2500BASE_KX;
3622                                 break;
3623                         } else if (hw->device_id ==
3624                                    IXGBE_DEV_ID_X550EM_A_KR_L) {
3625                                 physical_layer =
3626                                         IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3627                                 break;
3628                         }
3629                 }
3630                 /* fall through */
3631         case ixgbe_phy_x550em_xfi:
3632                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3633                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3634                 break;
3635         case ixgbe_phy_x550em_kx4:
3636                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3637                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3638                 break;
3639         case ixgbe_phy_x550em_ext_t:
3640                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3641                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3642                                      &ext_ability);
3643                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3644                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3645                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3646                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3647                 break;
3648         case ixgbe_phy_fw:
3649                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_1GB_FULL)
3650                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3651                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_100_FULL)
3652                         physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
3653                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_10_FULL)
3654                         physical_layer |= IXGBE_PHYSICAL_LAYER_10BASE_T;
3655                 break;
3656         case ixgbe_phy_sgmii:
3657 #ifdef PREBOOT_SUPPORT
3658                 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
3659                                  IXGBE_PHYSICAL_LAYER_100BASE_TX |
3660                                  IXGBE_PHYSICAL_LAYER_10BASE_T;
3661 #else
3662                 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3663 #endif /* PREBOOT_SUPPORT */
3664                 break;
3665         case ixgbe_phy_ext_1g_t:
3666                 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3667                 break;
3668         default:
3669                 break;
3670         }
3671
3672         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3673                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3674
3675         return physical_layer;
3676 }
3677
3678 /**
3679  * ixgbe_get_bus_info_x550em - Set PCI bus info
3680  * @hw: pointer to hardware structure
3681  *
3682  * Sets bus link width and speed to unknown because X550em is
3683  * not a PCI device.
3684  **/
3685 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3686 {
3687
3688         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3689
3690         hw->bus.width = ixgbe_bus_width_unknown;
3691         hw->bus.speed = ixgbe_bus_speed_unknown;
3692
3693         hw->mac.ops.set_lan_id(hw);
3694
3695         return IXGBE_SUCCESS;
3696 }
3697
3698 /**
3699  * ixgbe_disable_rx_x550 - Disable RX unit
3700  * @hw: pointer to hardware structure
3701  *
3702  * Enables the Rx DMA unit for x550
3703  **/
3704 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3705 {
3706         u32 rxctrl, pfdtxgswc;
3707         s32 status;
3708         struct ixgbe_hic_disable_rxen fw_cmd;
3709
3710         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3711
3712         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3713         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3714                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3715                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3716                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3717                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3718                         hw->mac.set_lben = true;
3719                 } else {
3720                         hw->mac.set_lben = false;
3721                 }
3722
3723                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3724                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3725                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3726                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3727
3728                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3729                                         sizeof(struct ixgbe_hic_disable_rxen),
3730                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3731
3732                 /* If we fail - disable RX using register write */
3733                 if (status) {
3734                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3735                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3736                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3737                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3738                         }
3739                 }
3740         }
3741 }
3742
3743 /**
3744  * ixgbe_enter_lplu_x550em - Transition to low power states
3745  *  @hw: pointer to hardware structure
3746  *
3747  * Configures Low Power Link Up on transition to low power states
3748  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3749  * X557 PHY immediately prior to entering LPLU.
3750  **/
3751 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3752 {
3753         u16 an_10g_cntl_reg, autoneg_reg, speed;
3754         s32 status;
3755         ixgbe_link_speed lcd_speed;
3756         u32 save_autoneg;
3757         bool link_up;
3758
3759         /* SW LPLU not required on later HW revisions. */
3760         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3761             (IXGBE_FUSES0_REV_MASK &
3762              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3763                 return IXGBE_SUCCESS;
3764
3765         /* If blocked by MNG FW, then don't restart AN */
3766         if (ixgbe_check_reset_blocked(hw))
3767                 return IXGBE_SUCCESS;
3768
3769         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3770         if (status != IXGBE_SUCCESS)
3771                 return status;
3772
3773         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3774
3775         if (status != IXGBE_SUCCESS)
3776                 return status;
3777
3778         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3779          * disabled, then force link down by entering low power mode.
3780          */
3781         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3782             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3783                 return ixgbe_set_copper_phy_power(hw, FALSE);
3784
3785         /* Determine LCD */
3786         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3787
3788         if (status != IXGBE_SUCCESS)
3789                 return status;
3790
3791         /* If no valid LCD link speed, then force link down and exit. */
3792         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3793                 return ixgbe_set_copper_phy_power(hw, FALSE);
3794
3795         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3796                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3797                                       &speed);
3798
3799         if (status != IXGBE_SUCCESS)
3800                 return status;
3801
3802         /* If no link now, speed is invalid so take link down */
3803         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3804         if (status != IXGBE_SUCCESS)
3805                 return ixgbe_set_copper_phy_power(hw, false);
3806
3807         /* clear everything but the speed bits */
3808         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3809
3810         /* If current speed is already LCD, then exit. */
3811         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3812              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3813             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3814              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3815                 return status;
3816
3817         /* Clear AN completed indication */
3818         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3819                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3820                                       &autoneg_reg);
3821
3822         if (status != IXGBE_SUCCESS)
3823                 return status;
3824
3825         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3826                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3827                              &an_10g_cntl_reg);
3828
3829         if (status != IXGBE_SUCCESS)
3830                 return status;
3831
3832         status = hw->phy.ops.read_reg(hw,
3833                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3834                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3835                              &autoneg_reg);
3836
3837         if (status != IXGBE_SUCCESS)
3838                 return status;
3839
3840         save_autoneg = hw->phy.autoneg_advertised;
3841
3842         /* Setup link at least common link speed */
3843         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3844
3845         /* restore autoneg from before setting lplu speed */
3846         hw->phy.autoneg_advertised = save_autoneg;
3847
3848         return status;
3849 }
3850
3851 /**
3852  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3853  *  @hw: pointer to hardware structure
3854  *  @lcd_speed: pointer to lowest common link speed
3855  *
3856  * Determine lowest common link speed with link partner.
3857  **/
3858 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3859 {
3860         u16 an_lp_status;
3861         s32 status;
3862         u16 word = hw->eeprom.ctrl_word_3;
3863
3864         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3865
3866         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3867                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3868                                       &an_lp_status);
3869
3870         if (status != IXGBE_SUCCESS)
3871                 return status;
3872
3873         /* If link partner advertised 1G, return 1G */
3874         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3875                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3876                 return status;
3877         }
3878
3879         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3880         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3881             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3882                 return status;
3883
3884         /* Link partner not capable of lower speeds, return 10G */
3885         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3886         return status;
3887 }
3888
3889 /**
3890  *  ixgbe_setup_fc_X550em - Set up flow control
3891  *  @hw: pointer to hardware structure
3892  *
3893  *  Called at init time to set up flow control.
3894  **/
3895 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3896 {
3897         s32 ret_val = IXGBE_SUCCESS;
3898         u32 pause, asm_dir, reg_val;
3899
3900         DEBUGFUNC("ixgbe_setup_fc_X550em");
3901
3902         /* Validate the requested mode */
3903         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3904                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3905                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3906                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3907                 goto out;
3908         }
3909
3910         /* 10gig parts do not have a word in the EEPROM to determine the
3911          * default flow control setting, so we explicitly set it to full.
3912          */
3913         if (hw->fc.requested_mode == ixgbe_fc_default)
3914                 hw->fc.requested_mode = ixgbe_fc_full;
3915
3916         /* Determine PAUSE and ASM_DIR bits. */
3917         switch (hw->fc.requested_mode) {
3918         case ixgbe_fc_none:
3919                 pause = 0;
3920                 asm_dir = 0;
3921                 break;
3922         case ixgbe_fc_tx_pause:
3923                 pause = 0;
3924                 asm_dir = 1;
3925                 break;
3926         case ixgbe_fc_rx_pause:
3927                 /* Rx Flow control is enabled and Tx Flow control is
3928                  * disabled by software override. Since there really
3929                  * isn't a way to advertise that we are capable of RX
3930                  * Pause ONLY, we will advertise that we support both
3931                  * symmetric and asymmetric Rx PAUSE, as such we fall
3932                  * through to the fc_full statement.  Later, we will
3933                  * disable the adapter's ability to send PAUSE frames.
3934                  */
3935         case ixgbe_fc_full:
3936                 pause = 1;
3937                 asm_dir = 1;
3938                 break;
3939         default:
3940                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3941                         "Flow control param set incorrectly\n");
3942                 ret_val = IXGBE_ERR_CONFIG;
3943                 goto out;
3944         }
3945
3946         switch (hw->device_id) {
3947         case IXGBE_DEV_ID_X550EM_X_KR:
3948         case IXGBE_DEV_ID_X550EM_A_KR:
3949         case IXGBE_DEV_ID_X550EM_A_KR_L:
3950                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3951                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3952                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3953                 if (ret_val != IXGBE_SUCCESS)
3954                         goto out;
3955                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3956                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3957                 if (pause)
3958                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3959                 if (asm_dir)
3960                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3961                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3962                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3963                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3964
3965                 /* This device does not fully support AN. */
3966                 hw->fc.disable_fc_autoneg = true;
3967                 break;
3968         case IXGBE_DEV_ID_X550EM_X_XFI:
3969                 hw->fc.disable_fc_autoneg = true;
3970                 break;
3971         default:
3972                 break;
3973         }
3974
3975 out:
3976         return ret_val;
3977 }
3978
3979 /**
3980  *  ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
3981  *  @hw: pointer to hardware structure
3982  *
3983  *  Enable flow control according to IEEE clause 37.
3984  **/
3985 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
3986 {
3987         u32 link_s1, lp_an_page_low, an_cntl_1;
3988         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
3989         ixgbe_link_speed speed;
3990         bool link_up;
3991
3992         /* AN should have completed when the cable was plugged in.
3993          * Look for reasons to bail out.  Bail out if:
3994          * - FC autoneg is disabled, or if
3995          * - link is not up.
3996          */
3997         if (hw->fc.disable_fc_autoneg) {
3998                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3999                              "Flow control autoneg is disabled");
4000                 goto out;
4001         }
4002
4003         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4004         if (!link_up) {
4005                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4006                 goto out;
4007         }
4008
4009         /* Check at auto-negotiation has completed */
4010         status = hw->mac.ops.read_iosf_sb_reg(hw,
4011                                         IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4012                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4013
4014         if (status != IXGBE_SUCCESS ||
4015             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4016                 DEBUGOUT("Auto-Negotiation did not complete\n");
4017                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4018                 goto out;
4019         }
4020
4021         /* Read the 10g AN autoc and LP ability registers and resolve
4022          * local flow control settings accordingly
4023          */
4024         status = hw->mac.ops.read_iosf_sb_reg(hw,
4025                                 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4026                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4027
4028         if (status != IXGBE_SUCCESS) {
4029                 DEBUGOUT("Auto-Negotiation did not complete\n");
4030                 goto out;
4031         }
4032
4033         status = hw->mac.ops.read_iosf_sb_reg(hw,
4034                                 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4035                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4036
4037         if (status != IXGBE_SUCCESS) {
4038                 DEBUGOUT("Auto-Negotiation did not complete\n");
4039                 goto out;
4040         }
4041
4042         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4043                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4044                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4045                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4046                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4047
4048 out:
4049         if (status == IXGBE_SUCCESS) {
4050                 hw->fc.fc_was_autonegged = true;
4051         } else {
4052                 hw->fc.fc_was_autonegged = false;
4053                 hw->fc.current_mode = hw->fc.requested_mode;
4054         }
4055 }
4056
4057 /**
4058  *  ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
4059  *  @hw: pointer to hardware structure
4060  *
4061  **/
4062 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4063 {
4064         hw->fc.fc_was_autonegged = false;
4065         hw->fc.current_mode = hw->fc.requested_mode;
4066 }
4067
4068 /**
4069  *  ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4070  *  @hw: pointer to hardware structure
4071  *
4072  *  Enable flow control according to IEEE clause 37.
4073  **/
4074 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4075 {
4076         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4077         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
4078         ixgbe_link_speed speed;
4079         bool link_up;
4080
4081         /* AN should have completed when the cable was plugged in.
4082          * Look for reasons to bail out.  Bail out if:
4083          * - FC autoneg is disabled, or if
4084          * - link is not up.
4085          */
4086         if (hw->fc.disable_fc_autoneg) {
4087                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4088                              "Flow control autoneg is disabled");
4089                 goto out;
4090         }
4091
4092         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4093         if (!link_up) {
4094                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4095                 goto out;
4096         }
4097
4098         /* Check if auto-negotiation has completed */
4099         status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
4100         if (status != IXGBE_SUCCESS ||
4101             !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
4102                 DEBUGOUT("Auto-Negotiation did not complete\n");
4103                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4104                 goto out;
4105         }
4106
4107         /* Negotiate the flow control */
4108         status = ixgbe_negotiate_fc(hw, info[0], info[0],
4109                                     FW_PHY_ACT_GET_LINK_INFO_FC_RX,
4110                                     FW_PHY_ACT_GET_LINK_INFO_FC_TX,
4111                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
4112                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
4113
4114 out:
4115         if (status == IXGBE_SUCCESS) {
4116                 hw->fc.fc_was_autonegged = true;
4117         } else {
4118                 hw->fc.fc_was_autonegged = false;
4119                 hw->fc.current_mode = hw->fc.requested_mode;
4120         }
4121 }
4122
4123 /**
4124  *  ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4125  *  @hw: pointer to hardware structure
4126  *
4127  *  Called at init time to set up flow control.
4128  **/
4129 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4130 {
4131         s32 status = IXGBE_SUCCESS;
4132         u32 an_cntl = 0;
4133
4134         DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4135
4136         /* Validate the requested mode */
4137         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4138                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4139                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4140                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4141         }
4142
4143         if (hw->fc.requested_mode == ixgbe_fc_default)
4144                 hw->fc.requested_mode = ixgbe_fc_full;
4145
4146         /* Set up the 1G and 10G flow control advertisement registers so the
4147          * HW will be able to do FC autoneg once the cable is plugged in.  If
4148          * we link at 10G, the 1G advertisement is harmless and vice versa.
4149          */
4150         status = hw->mac.ops.read_iosf_sb_reg(hw,
4151                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4152                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4153
4154         if (status != IXGBE_SUCCESS) {
4155                 DEBUGOUT("Auto-Negotiation did not complete\n");
4156                 return status;
4157         }
4158
4159         /* The possible values of fc.requested_mode are:
4160          * 0: Flow control is completely disabled
4161          * 1: Rx flow control is enabled (we can receive pause frames,
4162          *    but not send pause frames).
4163          * 2: Tx flow control is enabled (we can send pause frames but
4164          *    we do not support receiving pause frames).
4165          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4166          * other: Invalid.
4167          */
4168         switch (hw->fc.requested_mode) {
4169         case ixgbe_fc_none:
4170                 /* Flow control completely disabled by software override. */
4171                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4172                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4173                 break;
4174         case ixgbe_fc_tx_pause:
4175                 /* Tx Flow control is enabled, and Rx Flow control is
4176                  * disabled by software override.
4177                  */
4178                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4179                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4180                 break;
4181         case ixgbe_fc_rx_pause:
4182                 /* Rx Flow control is enabled and Tx Flow control is
4183                  * disabled by software override. Since there really
4184                  * isn't a way to advertise that we are capable of RX
4185                  * Pause ONLY, we will advertise that we support both
4186                  * symmetric and asymmetric Rx PAUSE, as such we fall
4187                  * through to the fc_full statement.  Later, we will
4188                  * disable the adapter's ability to send PAUSE frames.
4189                  */
4190         case ixgbe_fc_full:
4191                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4192                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4193                            IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4194                 break;
4195         default:
4196                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4197                               "Flow control param set incorrectly\n");
4198                 return IXGBE_ERR_CONFIG;
4199         }
4200
4201         status = hw->mac.ops.write_iosf_sb_reg(hw,
4202                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4203                                         IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4204
4205         /* Restart auto-negotiation. */
4206         status = ixgbe_restart_an_internal_phy_x550em(hw);
4207
4208         return status;
4209 }
4210
4211 /**
4212  * ixgbe_set_mux - Set mux for port 1 access with CS4227
4213  * @hw: pointer to hardware structure
4214  * @state: set mux if 1, clear if 0
4215  */
4216 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4217 {
4218         u32 esdp;
4219
4220         if (!hw->bus.lan_id)
4221                 return;
4222         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4223         if (state)
4224                 esdp |= IXGBE_ESDP_SDP1;
4225         else
4226                 esdp &= ~IXGBE_ESDP_SDP1;
4227         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4228         IXGBE_WRITE_FLUSH(hw);
4229 }
4230
4231 /**
4232  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4233  *  @hw: pointer to hardware structure
4234  *  @mask: Mask to specify which semaphore to acquire
4235  *
4236  *  Acquires the SWFW semaphore and sets the I2C MUX
4237  **/
4238 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4239 {
4240         s32 status;
4241
4242         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4243
4244         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4245         if (status)
4246                 return status;
4247
4248         if (mask & IXGBE_GSSR_I2C_MASK)
4249                 ixgbe_set_mux(hw, 1);
4250
4251         return IXGBE_SUCCESS;
4252 }
4253
4254 /**
4255  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4256  *  @hw: pointer to hardware structure
4257  *  @mask: Mask to specify which semaphore to release
4258  *
4259  *  Releases the SWFW semaphore and sets the I2C MUX
4260  **/
4261 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4262 {
4263         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4264
4265         if (mask & IXGBE_GSSR_I2C_MASK)
4266                 ixgbe_set_mux(hw, 0);
4267
4268         ixgbe_release_swfw_sync_X540(hw, mask);
4269 }
4270
4271 /**
4272  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4273  *  @hw: pointer to hardware structure
4274  *  @mask: Mask to specify which semaphore to acquire
4275  *
4276  *  Acquires the SWFW semaphore and get the shared phy token as needed
4277  */
4278 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4279 {
4280         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4281         int retries = FW_PHY_TOKEN_RETRIES;
4282         s32 status = IXGBE_SUCCESS;
4283
4284         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4285
4286         while (--retries) {
4287                 status = IXGBE_SUCCESS;
4288                 if (hmask)
4289                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4290                 if (status) {
4291                         DEBUGOUT1("Could not acquire SWFW semaphore, Status = %d\n",
4292                                   status);
4293                         return status;
4294                 }
4295                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4296                         return IXGBE_SUCCESS;
4297
4298                 status = ixgbe_get_phy_token(hw);
4299                 if (status == IXGBE_ERR_TOKEN_RETRY)
4300                         DEBUGOUT1("Could not acquire PHY token, Status = %d\n",
4301                                   status);
4302
4303                 if (status == IXGBE_SUCCESS)
4304                         return IXGBE_SUCCESS;
4305
4306                 if (hmask)
4307                         ixgbe_release_swfw_sync_X540(hw, hmask);
4308
4309                 if (status != IXGBE_ERR_TOKEN_RETRY) {
4310                         DEBUGOUT1("Unable to retry acquiring the PHY token, Status = %d\n",
4311                                   status);
4312                         return status;
4313                 }
4314         }
4315
4316         DEBUGOUT1("Semaphore acquisition retries failed!: PHY ID = 0x%08X\n",
4317                   hw->phy.id);
4318         return status;
4319 }
4320
4321 /**
4322  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4323  *  @hw: pointer to hardware structure
4324  *  @mask: Mask to specify which semaphore to release
4325  *
4326  *  Releases the SWFW semaphore and puts the shared phy token as needed
4327  */
4328 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4329 {
4330         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4331
4332         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4333
4334         if (mask & IXGBE_GSSR_TOKEN_SM)
4335                 ixgbe_put_phy_token(hw);
4336
4337         if (hmask)
4338                 ixgbe_release_swfw_sync_X540(hw, hmask);
4339 }
4340
4341 /**
4342  *  ixgbe_read_phy_reg_x550a  - Reads specified PHY register
4343  *  @hw: pointer to hardware structure
4344  *  @reg_addr: 32 bit address of PHY register to read
4345  *  @device_type: 5 bit device type
4346  *  @phy_data: Pointer to read data from PHY register
4347  *
4348  *  Reads a value from a specified PHY register using the SWFW lock and PHY
4349  *  Token. The PHY Token is needed since the MDIO is shared between to MAC
4350  *  instances.
4351  **/
4352 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4353                                u32 device_type, u16 *phy_data)
4354 {
4355         s32 status;
4356         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4357
4358         DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4359
4360         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4361                 return IXGBE_ERR_SWFW_SYNC;
4362
4363         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4364
4365         hw->mac.ops.release_swfw_sync(hw, mask);
4366
4367         return status;
4368 }
4369
4370 /**
4371  *  ixgbe_write_phy_reg_x550a - Writes specified PHY register
4372  *  @hw: pointer to hardware structure
4373  *  @reg_addr: 32 bit PHY register to write
4374  *  @device_type: 5 bit device type
4375  *  @phy_data: Data to write to the PHY register
4376  *
4377  *  Writes a value to specified PHY register using the SWFW lock and PHY Token.
4378  *  The PHY Token is needed since the MDIO is shared between to MAC instances.
4379  **/
4380 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4381                                 u32 device_type, u16 phy_data)
4382 {
4383         s32 status;
4384         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4385
4386         DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4387
4388         if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4389                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4390                                                  phy_data);
4391                 hw->mac.ops.release_swfw_sync(hw, mask);
4392         } else {
4393                 status = IXGBE_ERR_SWFW_SYNC;
4394         }
4395
4396         return status;
4397 }
4398
4399 /**
4400  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4401  * @hw: pointer to hardware structure
4402  *
4403  * Handle external Base T PHY interrupt. If high temperature
4404  * failure alarm then return error, else if link status change
4405  * then setup internal/external PHY link
4406  *
4407  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4408  * failure alarm, else return PHY access status.
4409  */
4410 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4411 {
4412         bool lsc;
4413         u32 status;
4414
4415         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4416
4417         if (status != IXGBE_SUCCESS)
4418                 return status;
4419
4420         if (lsc)
4421                 return ixgbe_setup_internal_phy(hw);
4422
4423         return IXGBE_SUCCESS;
4424 }
4425
4426 /**
4427  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4428  * @hw: pointer to hardware structure
4429  * @speed: new link speed
4430  * @autoneg_wait_to_complete: true when waiting for completion is needed
4431  *
4432  * Setup internal/external PHY link speed based on link speed, then set
4433  * external PHY auto advertised link speed.
4434  *
4435  * Returns error status for any failure
4436  **/
4437 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4438                                   ixgbe_link_speed speed,
4439                                   bool autoneg_wait_to_complete)
4440 {
4441         s32 status;
4442         ixgbe_link_speed force_speed;
4443         u32 i;
4444         bool link_up = false;
4445
4446         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4447
4448         /* Setup internal/external PHY link speed to iXFI (10G), unless
4449          * only 1G is auto advertised then setup KX link.
4450          */
4451         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4452                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4453         else
4454                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4455
4456         /* If X552 and internal link mode is XFI, then setup XFI internal link.
4457          */
4458         if (hw->mac.type == ixgbe_mac_X550EM_x &&
4459             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4460                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4461
4462                 if (status != IXGBE_SUCCESS)
4463                         return status;
4464
4465                 /* Wait for the controller to acquire link */
4466                 for (i = 0; i < 10; i++) {
4467                         msec_delay(100);
4468
4469                         status = ixgbe_check_link(hw, &force_speed, &link_up,
4470                                                   false);
4471                         if (status != IXGBE_SUCCESS)
4472                                 return status;
4473
4474                         if (link_up)
4475                                 break;
4476                 }
4477         }
4478
4479         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4480 }
4481
4482 /**
4483  * ixgbe_check_link_t_X550em - Determine link and speed status
4484  * @hw: pointer to hardware structure
4485  * @speed: pointer to link speed
4486  * @link_up: true when link is up
4487  * @link_up_wait_to_complete: bool used to wait for link up or not
4488  *
4489  * Check that both the MAC and X557 external PHY have link.
4490  **/
4491 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4492                               bool *link_up, bool link_up_wait_to_complete)
4493 {
4494         u32 status;
4495         u16 i, autoneg_status = 0;
4496
4497         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4498                 return IXGBE_ERR_CONFIG;
4499
4500         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4501                                               link_up_wait_to_complete);
4502
4503         /* If check link fails or MAC link is not up, then return */
4504         if (status != IXGBE_SUCCESS || !(*link_up))
4505                 return status;
4506
4507         /* MAC link is up, so check external PHY link.
4508          * X557 PHY. Link status is latching low, and can only be used to detect
4509          * link drop, and not the current status of the link without performing
4510          * back-to-back reads.
4511          */
4512         for (i = 0; i < 2; i++) {
4513                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4514                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4515                                               &autoneg_status);
4516
4517                 if (status != IXGBE_SUCCESS)
4518                         return status;
4519         }
4520
4521         /* If external PHY link is not up, then indicate link not up */
4522         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4523                 *link_up = false;
4524
4525         return IXGBE_SUCCESS;
4526 }
4527
4528 /**
4529  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4530  *  @hw: pointer to hardware structure
4531  **/
4532 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4533 {
4534         s32 status;
4535
4536         status = ixgbe_reset_phy_generic(hw);
4537
4538         if (status != IXGBE_SUCCESS)
4539                 return status;
4540
4541         /* Configure Link Status Alarm and Temperature Threshold interrupts */
4542         return ixgbe_enable_lasi_ext_t_x550em(hw);
4543 }
4544
4545 /**
4546  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4547  *  @hw: pointer to hardware structure
4548  *  @led_idx: led number to turn on
4549  **/
4550 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4551 {
4552         u16 phy_data;
4553
4554         DEBUGFUNC("ixgbe_led_on_t_X550em");
4555
4556         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4557                 return IXGBE_ERR_PARAM;
4558
4559         /* To turn on the LED, set mode to ON. */
4560         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4561                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4562         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4563         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4564                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4565
4566         /* Some designs have the LEDs wired to the MAC */
4567         return ixgbe_led_on_generic(hw, led_idx);
4568 }
4569
4570 /**
4571  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4572  *  @hw: pointer to hardware structure
4573  *  @led_idx: led number to turn off
4574  **/
4575 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4576 {
4577         u16 phy_data;
4578
4579         DEBUGFUNC("ixgbe_led_off_t_X550em");
4580
4581         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4582                 return IXGBE_ERR_PARAM;
4583
4584         /* To turn on the LED, set mode to ON. */
4585         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4586                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4587         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4588         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4589                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4590
4591         /* Some designs have the LEDs wired to the MAC */
4592         return ixgbe_led_off_generic(hw, led_idx);
4593 }
4594
4595 /**
4596  *  ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
4597  *  @hw: pointer to the HW structure
4598  *  @maj: driver version major number
4599  *  @min: driver version minor number
4600  *  @build: driver version build number
4601  *  @sub: driver version sub build number
4602  *  @len: length of driver_ver string
4603  *  @driver_ver: driver string
4604  *
4605  *  Sends driver version number to firmware through the manageability
4606  *  block.  On success return IXGBE_SUCCESS
4607  *  else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4608  *  semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4609  **/
4610 s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
4611                               u8 build, u8 sub, u16 len, const char *driver_ver)
4612 {
4613         struct ixgbe_hic_drv_info2 fw_cmd;
4614         s32 ret_val = IXGBE_SUCCESS;
4615         int i;
4616
4617         DEBUGFUNC("ixgbe_set_fw_drv_ver_x550");
4618
4619         if ((len == 0) || (driver_ver == NULL) ||
4620            (len > sizeof(fw_cmd.driver_string)))
4621                 return IXGBE_ERR_INVALID_ARGUMENT;
4622
4623         fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4624         fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
4625         fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4626         fw_cmd.port_num = (u8)hw->bus.func;
4627         fw_cmd.ver_maj = maj;
4628         fw_cmd.ver_min = min;
4629         fw_cmd.ver_build = build;
4630         fw_cmd.ver_sub = sub;
4631         fw_cmd.hdr.checksum = 0;
4632         memcpy(fw_cmd.driver_string, driver_ver, len);
4633         fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4634                                 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4635
4636         for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4637                 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4638                                                        sizeof(fw_cmd),
4639                                                        IXGBE_HI_COMMAND_TIMEOUT,
4640                                                        true);
4641                 if (ret_val != IXGBE_SUCCESS)
4642                         continue;
4643
4644                 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4645                     FW_CEM_RESP_STATUS_SUCCESS)
4646                         ret_val = IXGBE_SUCCESS;
4647                 else
4648                         ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4649
4650                 break;
4651         }
4652
4653         return ret_val;
4654 }
4655
4656 /**
4657  * ixgbe_fw_recovery_mode_X550 - Check FW NVM recovery mode
4658  * @hw: pointer t hardware structure
4659  *
4660  * Returns true if in FW NVM recovery mode.
4661  **/
4662 bool ixgbe_fw_recovery_mode_X550(struct ixgbe_hw *hw)
4663 {
4664         u32 fwsm;
4665
4666         fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
4667
4668         return !!(fwsm & IXGBE_FWSM_FW_NVM_RECOVERY_MODE);
4669 }