drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41
  42 /**
  43  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  44  *  @hw: pointer to hardware structure
  45  *
  46  *  Initialize the function pointers and assign the MAC type for X550.
  47  *  Does not touch the hardware.
  48  **/
  49 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  50 {
  51         struct ixgbe_mac_info *mac = &hw->mac;
  52         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  53         s32 ret_val;
  54
  55         DEBUGFUNC("ixgbe_init_ops_X550");
  56
  57         ret_val = ixgbe_init_ops_X540(hw);
  58         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  59         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  60         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  61         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  62         mac->ops.set_source_address_pruning =
  63                         ixgbe_set_source_address_pruning_X550;
  64         mac->ops.set_ethertype_anti_spoofing =
  65                         ixgbe_set_ethertype_anti_spoofing_X550;
  66
  67         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  68         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  69         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  70         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  71         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  72         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  73         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  74         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  75         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  76
  77         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  78         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  79         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  80         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  81         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  82         return ret_val;
  83 }
  84
  85 /**
  86  * ixgbe_read_cs4227 - Read CS4227 register
  87  * @hw: pointer to hardware structure
  88  * @reg: register number to write
  89  * @value: pointer to receive value read
  90  *
  91  * Returns status code
  92  **/
  93 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  94 {
  95         return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
  96 }
  97
  98 /**
  99  * ixgbe_write_cs4227 - Write CS4227 register
 100  * @hw: pointer to hardware structure
 101  * @reg: register number to write
 102  * @value: value to write to register
 103  *
 104  * Returns status code
 105  **/
 106 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 107 {
 108         return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 109 }
 110
 111 /**
 112  * ixgbe_get_cs4227_status - Return CS4227 status
 113  * @hw: pointer to hardware structure
 114  *
 115  * Returns error if CS4227 not successfully initialized
 116  **/
 117 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
 118 {
 119         s32 status;
 120         u16 value = 0;
 121         u8 retry;
 122
 123         for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
 124                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
 125                                            &value);
 126                 if (status != IXGBE_SUCCESS)
 127                         return status;
 128                 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
 129                         break;
 130                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 131         }
 132         if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
 133                 return IXGBE_ERR_PHY;
 134
 135         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 136                                     IXGBE_CS4227_SCRATCH_VALUE);
 137         if (status != IXGBE_SUCCESS)
 138                 return status;
 139         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 140         if (status != IXGBE_SUCCESS)
 141                 return status;
 142         if (value != IXGBE_CS4227_SCRATCH_VALUE)
 143                 return IXGBE_ERR_PHY;
 144         return IXGBE_SUCCESS;
 145 }
 146
 147 /**
 148  * ixgbe_read_pe - Read register from port expander
 149  * @hw: pointer to hardware structure
 150  * @reg: register number to read
 151  * @value: pointer to receive read value
 152  *
 153  * Returns status code
 154  **/
 155 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 156 {
 157         s32 status;
 158
 159         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 160         if (status != IXGBE_SUCCESS)
 161                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 162                               "port expander access failed with %d\n", status);
 163         return status;
 164 }
 165
 166 /**
 167  * ixgbe_write_pe - Write register to port expander
 168  * @hw: pointer to hardware structure
 169  * @reg: register number to write
 170  * @value: value to write
 171  *
 172  * Returns status code
 173  **/
 174 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 175 {
 176         s32 status;
 177
 178         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 179         if (status != IXGBE_SUCCESS)
 180                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 181                               "port expander access failed with %d\n", status);
 182         return status;
 183 }
 184
 185 /**
 186  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 187  * @hw: pointer to hardware structure
 188  *
 189  * Returns error code
 190  **/
 191 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 192 {
 193         s32 status;
 194         u8 reg;
 195
 196         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199         reg |= IXGBE_PE_BIT1;
 200         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 201         if (status != IXGBE_SUCCESS)
 202                 return status;
 203
 204         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 205         if (status != IXGBE_SUCCESS)
 206                 return status;
 207         reg &= ~IXGBE_PE_BIT1;
 208         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 209         if (status != IXGBE_SUCCESS)
 210                 return status;
 211
 212         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 213         if (status != IXGBE_SUCCESS)
 214                 return status;
 215         reg &= ~IXGBE_PE_BIT1;
 216         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 217         if (status != IXGBE_SUCCESS)
 218                 return status;
 219
 220         usec_delay(IXGBE_CS4227_RESET_HOLD);
 221
 222         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 223         if (status != IXGBE_SUCCESS)
 224                 return status;
 225         reg |= IXGBE_PE_BIT1;
 226         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 227         if (status != IXGBE_SUCCESS)
 228                 return status;
 229
 230         msec_delay(IXGBE_CS4227_RESET_DELAY);
 231
 232         return IXGBE_SUCCESS;
 233 }
 234
 235 /**
 236  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 237  * @hw: pointer to hardware structure
 238  **/
 239 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 240 {
 241         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 242         s32 status;
 243         u8 retry;
 244
 245         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 246                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 247                 if (status != IXGBE_SUCCESS) {
 248                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 249                                       "semaphore failed with %d\n", status);
 250                         return;
 251                 }
 252                 status = ixgbe_get_cs4227_status(hw);
 253                 if (status == IXGBE_SUCCESS) {
 254                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 255                         msec_delay(hw->eeprom.semaphore_delay);
 256                         return;
 257                 }
 258                 ixgbe_reset_cs4227(hw);
 259                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 260                 msec_delay(hw->eeprom.semaphore_delay);
 261         }
 262         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 263                       "Unable to initialize CS4227, err=%d\n", status);
 264 }
 265
 266 /**
 267  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 268  * @hw: pointer to hardware structure
 269  **/
 270 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 271 {
 272         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 273
 274         if (hw->bus.lan_id) {
 275                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 276                 esdp |= IXGBE_ESDP_SDP1_DIR;
 277         }
 278         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 279         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 280         IXGBE_WRITE_FLUSH(hw);
 281 }
 282
 283 /**
 284  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 285  * @hw: pointer to hardware structure
 286  *
 287  * Returns error code
 288  */
 289 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 290 {
 291         switch (hw->device_id) {
 292         case IXGBE_DEV_ID_X550EM_X_SFP:
 293                 /* set up for CS4227 usage */
 294                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 295                 ixgbe_setup_mux_ctl(hw);
 296                 ixgbe_check_cs4227(hw);
 297
 298                 return ixgbe_identify_module_generic(hw);
 299                 break;
 300         case IXGBE_DEV_ID_X550EM_X_KX4:
 301                 hw->phy.type = ixgbe_phy_x550em_kx4;
 302                 break;
 303         case IXGBE_DEV_ID_X550EM_X_KR:
 304                 hw->phy.type = ixgbe_phy_x550em_kr;
 305                 break;
 306         case IXGBE_DEV_ID_X550EM_X_1G_T:
 307         case IXGBE_DEV_ID_X550EM_X_10G_T:
 308                 return ixgbe_identify_phy_generic(hw);
 309         default:
 310                 break;
 311         }
 312         return IXGBE_SUCCESS;
 313 }
 314
 315 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 316                                      u32 device_type, u16 *phy_data)
 317 {
 318         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 319         return IXGBE_NOT_IMPLEMENTED;
 320 }
 321
 322 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 323                                       u32 device_type, u16 phy_data)
 324 {
 325         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 326         return IXGBE_NOT_IMPLEMENTED;
 327 }
 328
 329 /**
 330 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 331 *  @hw: pointer to hardware structure
 332 *
 333 *  Initialize the function pointers and for MAC type X550EM.
 334 *  Does not touch the hardware.
 335 **/
 336 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 337 {
 338         struct ixgbe_mac_info *mac = &hw->mac;
 339         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 340         struct ixgbe_phy_info *phy = &hw->phy;
 341         s32 ret_val;
 342
 343         DEBUGFUNC("ixgbe_init_ops_X550EM");
 344
 345         /* Similar to X550 so start there. */
 346         ret_val = ixgbe_init_ops_X550(hw);
 347
 348         /* Since this function eventually calls
 349          * ixgbe_init_ops_540 by design, we are setting
 350          * the pointers to NULL explicitly here to overwrite
 351          * the values being set in the x540 function.
 352          */
 353         /* Thermal sensor not supported in x550EM */
 354         mac->ops.get_thermal_sensor_data = NULL;
 355         mac->ops.init_thermal_sensor_thresh = NULL;
 356         mac->thermal_sensor_enabled = false;
 357
 358         /* FCOE not supported in x550EM */
 359         mac->ops.get_san_mac_addr = NULL;
 360         mac->ops.set_san_mac_addr = NULL;
 361         mac->ops.get_wwn_prefix = NULL;
 362         mac->ops.get_fcoe_boot_status = NULL;
 363
 364         /* IPsec not supported in x550EM */
 365         mac->ops.disable_sec_rx_path = NULL;
 366         mac->ops.enable_sec_rx_path = NULL;
 367
 368         /* AUTOC register is not present in x550EM. */
 369         mac->ops.prot_autoc_read = NULL;
 370         mac->ops.prot_autoc_write = NULL;
 371
 372         /* X550EM bus type is internal*/
 373         hw->bus.type = ixgbe_bus_type_internal;
 374         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 375
 376         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 377         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 378         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 379         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 380         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 381         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 382         mac->ops.get_supported_physical_layer =
 383                                     ixgbe_get_supported_physical_layer_X550em;
 384
 385         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 386                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 387         else
 388                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 389
 390         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 391         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 392
 393         /* PHY */
 394         phy->ops.init = ixgbe_init_phy_ops_X550em;
 395         phy->ops.identify = ixgbe_identify_phy_x550em;
 396         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 397                 phy->ops.set_phy_power = NULL;
 398
 399
 400         /* EEPROM */
 401         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 402         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 403         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 404         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 405         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 406         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 407         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 408         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 409
 410         return ret_val;
 411 }
 412
 413 /**
 414  *  ixgbe_dmac_config_X550
 415  *  @hw: pointer to hardware structure
 416  *
 417  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 418  *  When disabling dmac, dmac enable dmac bit is cleared.
 419  **/
 420 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 421 {
 422         u32 reg, high_pri_tc;
 423
 424         DEBUGFUNC("ixgbe_dmac_config_X550");
 425
 426         /* Disable DMA coalescing before configuring */
 427         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 428         reg &= ~IXGBE_DMACR_DMAC_EN;
 429         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 430
 431         /* Disable DMA Coalescing if the watchdog timer is 0 */
 432         if (!hw->mac.dmac_config.watchdog_timer)
 433                 goto out;
 434
 435         ixgbe_dmac_config_tcs_X550(hw);
 436
 437         /* Configure DMA Coalescing Control Register */
 438         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 439
 440         /* Set the watchdog timer in units of 40.96 usec */
 441         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 442         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 443
 444         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 445         /* If fcoe is enabled, set high priority traffic class */
 446         if (hw->mac.dmac_config.fcoe_en) {
 447                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 448                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 449                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 450         }
 451         reg |= IXGBE_DMACR_EN_MNG_IND;
 452
 453         /* Enable DMA coalescing after configuration */
 454         reg |= IXGBE_DMACR_DMAC_EN;
 455         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 456
 457 out:
 458         return IXGBE_SUCCESS;
 459 }
 460
 461 /**
 462  *  ixgbe_dmac_config_tcs_X550
 463  *  @hw: pointer to hardware structure
 464  *
 465  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 466  *  be cleared before configuring.
 467  **/
 468 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 469 {
 470         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 471
 472         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 473
 474         /* Configure DMA coalescing enabled */
 475         switch (hw->mac.dmac_config.link_speed) {
 476         case IXGBE_LINK_SPEED_100_FULL:
 477                 pb_headroom = IXGBE_DMACRXT_100M;
 478                 break;
 479         case IXGBE_LINK_SPEED_1GB_FULL:
 480                 pb_headroom = IXGBE_DMACRXT_1G;
 481                 break;
 482         default:
 483                 pb_headroom = IXGBE_DMACRXT_10G;
 484                 break;
 485         }
 486
 487         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 488                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 489
 490         /* Set the per Rx packet buffer receive threshold */
 491         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 492                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 493                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 494
 495                 if (tc < hw->mac.dmac_config.num_tcs) {
 496                         /* Get Rx PB size */
 497                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 498                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 499                                 IXGBE_RXPBSIZE_SHIFT;
 500
 501                         /* Calculate receive buffer threshold in kilobytes */
 502                         if (rx_pb_size > pb_headroom)
 503                                 rx_pb_size = rx_pb_size - pb_headroom;
 504                         else
 505                                 rx_pb_size = 0;
 506
 507                         /* Minimum of MFS shall be set for DMCTH */
 508                         reg |= (rx_pb_size > maxframe_size_kb) ?
 509                                 rx_pb_size : maxframe_size_kb;
 510                 }
 511                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 512         }
 513         return IXGBE_SUCCESS;
 514 }
 515
 516 /**
 517  *  ixgbe_dmac_update_tcs_X550
 518  *  @hw: pointer to hardware structure
 519  *
 520  *  Disables dmac, updates per TC settings, and then enables dmac.
 521  **/
 522 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 523 {
 524         u32 reg;
 525
 526         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 527
 528         /* Disable DMA coalescing before configuring */
 529         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 530         reg &= ~IXGBE_DMACR_DMAC_EN;
 531         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 532
 533         ixgbe_dmac_config_tcs_X550(hw);
 534
 535         /* Enable DMA coalescing after configuration */
 536         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 537         reg |= IXGBE_DMACR_DMAC_EN;
 538         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 539
 540         return IXGBE_SUCCESS;
 541 }
 542
 543 /**
 544  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 545  *  @hw: pointer to hardware structure
 546  *
 547  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 548  *  ixgbe_hw struct in order to set up EEPROM access.
 549  **/
 550 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 551 {
 552         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 553         u32 eec;
 554         u16 eeprom_size;
 555
 556         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 557
 558         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 559                 eeprom->semaphore_delay = 10;
 560                 eeprom->type = ixgbe_flash;
 561
 562                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 563                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 564                                     IXGBE_EEC_SIZE_SHIFT);
 565                 eeprom->word_size = 1 << (eeprom_size +
 566                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 567
 568                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 569                           eeprom->type, eeprom->word_size);
 570         }
 571
 572         return IXGBE_SUCCESS;
 573 }
 574
 575 /**
 576  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 577  *  @hw: pointer to the HW structure
 578  *  @enable_eee: boolean flag to enable EEE
 579  *
 580  *  Enable/disable EEE based on enable_eee flag.
 581  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 582  *  are modified.
 583  *
 584  **/
 585 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 586 {
 587         u32 eeer;
 588         u16 autoneg_eee_reg;
 589         u32 link_reg;
 590         s32 status;
 591
 592         DEBUGFUNC("ixgbe_setup_eee_X550");
 593
 594         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 595         /* Enable or disable EEE per flag */
 596         if (enable_eee) {
 597                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 598
 599                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 600                         /* Advertise EEE capability */
 601                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 602                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 603
 604                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 605                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 606                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 607
 608                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 609                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 610                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 611                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 612                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 613                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 614                         if (status != IXGBE_SUCCESS)
 615                                 return status;
 616
 617                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 618                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 619
 620                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 621                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 622                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 623                         if (status != IXGBE_SUCCESS)
 624                                 return status;
 625                 }
 626         } else {
 627                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 628
 629                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 630                         /* Disable advertised EEE capability */
 631                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 632                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 633
 634                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 635                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 636                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 637
 638                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 639                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 640                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 641                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 642                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 643                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 644                         if (status != IXGBE_SUCCESS)
 645                                 return status;
 646
 647                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 648                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 649
 650                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 651                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 652                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 653                         if (status != IXGBE_SUCCESS)
 654                                 return status;
 655                 }
 656         }
 657         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 658
 659         return IXGBE_SUCCESS;
 660 }
 661
 662 /**
 663  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 664  * @hw: pointer to hardware structure
 665  * @enable: enable or disable source address pruning
 666  * @pool: Rx pool to set source address pruning for
 667  **/
 668 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 669                                            unsigned int pool)
 670 {
 671         u64 pfflp;
 672
 673         /* max rx pool is 63 */
 674         if (pool > 63)
 675                 return;
 676
 677         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 678         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 679
 680         if (enable)
 681                 pfflp |= (1ULL << pool);
 682         else
 683                 pfflp &= ~(1ULL << pool);
 684
 685         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 686         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 687 }
 688
 689 /**
 690  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 691  *  @hw: pointer to hardware structure
 692  *  @enable: enable or disable switch for Ethertype anti-spoofing
 693  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 694  *
 695  **/
 696 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 697                 bool enable, int vf)
 698 {
 699         int vf_target_reg = vf >> 3;
 700         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 701         u32 pfvfspoof;
 702
 703         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 704
 705         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 706         if (enable)
 707                 pfvfspoof |= (1 << vf_target_shift);
 708         else
 709                 pfvfspoof &= ~(1 << vf_target_shift);
 710
 711         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 712 }
 713
 714 /**
 715  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 716  *  device
 717  *  @hw: pointer to hardware structure
 718  *  @reg_addr: 32 bit PHY register to write
 719  *  @device_type: 3 bit device type
 720  *  @data: Data to write to the register
 721  **/
 722 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 723                             u32 device_type, u32 data)
 724 {
 725         u32 i, command, error;
 726
 727         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 728                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 729
 730         /* Write IOSF control register */
 731         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 732
 733         /* Write IOSF data register */
 734         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 735         /*
 736          * Check every 10 usec to see if the address cycle completed.
 737          * The SB IOSF BUSY bit will clear when the operation is
 738          * complete
 739          */
 740         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 741                 usec_delay(10);
 742
 743                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 744                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 745                         break;
 746         }
 747
 748         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 749                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 750                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 751                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 752                               "Failed to write, error %x\n", error);
 753                 return IXGBE_ERR_PHY;
 754         }
 755
 756         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 757                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
 758                 return IXGBE_ERR_PHY;
 759         }
 760
 761         return IXGBE_SUCCESS;
 762 }
 763
 764 /**
 765  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 766  *  device
 767  *  @hw: pointer to hardware structure
 768  *  @reg_addr: 32 bit PHY register to write
 769  *  @device_type: 3 bit device type
 770  *  @phy_data: Pointer to read data from the register
 771  **/
 772 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 773                            u32 device_type, u32 *data)
 774 {
 775         u32 i, command, error;
 776
 777         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 778                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 779
 780         /* Write IOSF control register */
 781         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 782
 783         /*
 784          * Check every 10 usec to see if the address cycle completed.
 785          * The SB IOSF BUSY bit will clear when the operation is
 786          * complete
 787          */
 788         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 789                 usec_delay(10);
 790
 791                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 792                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 793                         break;
 794         }
 795
 796         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 797                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 798                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 799                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 800                                 "Failed to read, error %x\n", error);
 801                 return IXGBE_ERR_PHY;
 802         }
 803
 804         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 805                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
 806                 return IXGBE_ERR_PHY;
 807         }
 808
 809         *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 810
 811         return IXGBE_SUCCESS;
 812 }
 813
 814 /**
 815  *  ixgbe_disable_mdd_X550
 816  *  @hw: pointer to hardware structure
 817  *
 818  *  Disable malicious driver detection
 819  **/
 820 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 821 {
 822         u32 reg;
 823
 824         DEBUGFUNC("ixgbe_disable_mdd_X550");
 825
 826         /* Disable MDD for TX DMA and interrupt */
 827         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 828         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 829         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 830
 831         /* Disable MDD for RX and interrupt */
 832         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 833         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 834         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 835 }
 836
 837 /**
 838  *  ixgbe_enable_mdd_X550
 839  *  @hw: pointer to hardware structure
 840  *
 841  *  Enable malicious driver detection
 842  **/
 843 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 844 {
 845         u32 reg;
 846
 847         DEBUGFUNC("ixgbe_enable_mdd_X550");
 848
 849         /* Enable MDD for TX DMA and interrupt */
 850         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 851         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 852         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 853
 854         /* Enable MDD for RX and interrupt */
 855         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 856         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 857         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 858 }
 859
 860 /**
 861  *  ixgbe_restore_mdd_vf_X550
 862  *  @hw: pointer to hardware structure
 863  *  @vf: vf index
 864  *
 865  *  Restore VF that was disabled during malicious driver detection event
 866  **/
 867 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 868 {
 869         u32 idx, reg, num_qs, start_q, bitmask;
 870
 871         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 872
 873         /* Map VF to queues */
 874         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 875         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 876         case IXGBE_MRQC_VMDQRT8TCEN:
 877                 num_qs = 8;  /* 16 VFs / pools */
 878                 bitmask = 0x000000FF;
 879                 break;
 880         case IXGBE_MRQC_VMDQRSS32EN:
 881         case IXGBE_MRQC_VMDQRT4TCEN:
 882                 num_qs = 4;  /* 32 VFs / pools */
 883                 bitmask = 0x0000000F;
 884                 break;
 885         default:            /* 64 VFs / pools */
 886                 num_qs = 2;
 887                 bitmask = 0x00000003;
 888                 break;
 889         }
 890         start_q = vf * num_qs;
 891
 892         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
 893         idx = start_q / 32;
 894         reg = 0;
 895         reg |= (bitmask << (start_q % 32));
 896         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
 897         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
 898 }
 899
 900 /**
 901  *  ixgbe_mdd_event_X550
 902  *  @hw: pointer to hardware structure
 903  *  @vf_bitmap: vf bitmap of malicious vfs
 904  *
 905  *  Handle malicious driver detection event.
 906  **/
 907 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
 908 {
 909         u32 wqbr;
 910         u32 i, j, reg, q, shift, vf, idx;
 911
 912         DEBUGFUNC("ixgbe_mdd_event_X550");
 913
 914         /* figure out pool size for mapping to vf's */
 915         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 916         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 917         case IXGBE_MRQC_VMDQRT8TCEN:
 918                 shift = 3;  /* 16 VFs / pools */
 919                 break;
 920         case IXGBE_MRQC_VMDQRSS32EN:
 921         case IXGBE_MRQC_VMDQRT4TCEN:
 922                 shift = 2;  /* 32 VFs / pools */
 923                 break;
 924         default:
 925                 shift = 1;  /* 64 VFs / pools */
 926                 break;
 927         }
 928
 929         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
 930         for (i = 0; i < 4; i++) {
 931                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
 932                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
 933
 934                 if (!wqbr)
 935                         continue;
 936
 937                 /* Get malicious queue */
 938                 for (j = 0; j < 32 && wqbr; j++) {
 939
 940                         if (!(wqbr & (1 << j)))
 941                                 continue;
 942
 943                         /* Get queue from bitmask */
 944                         q = j + (i * 32);
 945
 946                         /* Map queue to vf */
 947                         vf = (q >> shift);
 948
 949                         /* Set vf bit in vf_bitmap */
 950                         idx = vf / 32;
 951                         vf_bitmap[idx] |= (1 << (vf % 32));
 952                         wqbr &= ~(1 << j);
 953                 }
 954         }
 955 }
 956
 957 /**
 958  *  ixgbe_get_media_type_X550em - Get media type
 959  *  @hw: pointer to hardware structure
 960  *
 961  *  Returns the media type (fiber, copper, backplane)
 962  */
 963 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
 964 {
 965         enum ixgbe_media_type media_type;
 966
 967         DEBUGFUNC("ixgbe_get_media_type_X550em");
 968
 969         /* Detect if there is a copper PHY attached. */
 970         switch (hw->device_id) {
 971         case IXGBE_DEV_ID_X550EM_X_KR:
 972         case IXGBE_DEV_ID_X550EM_X_KX4:
 973                 media_type = ixgbe_media_type_backplane;
 974                 break;
 975         case IXGBE_DEV_ID_X550EM_X_SFP:
 976                 media_type = ixgbe_media_type_fiber;
 977                 break;
 978         case IXGBE_DEV_ID_X550EM_X_1G_T:
 979         case IXGBE_DEV_ID_X550EM_X_10G_T:
 980                 media_type = ixgbe_media_type_copper;
 981                 break;
 982         default:
 983                 media_type = ixgbe_media_type_unknown;
 984                 break;
 985         }
 986         return media_type;
 987 }
 988
 989 /**
 990  *  ixgbe_setup_sfp_modules_X550em - Setup SFP module
 991  *  @hw: pointer to hardware structure
 992  */
 993 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
 994 {
 995         bool setup_linear;
 996         u16 reg_slice, edc_mode;
 997         s32 ret_val;
 998
 999         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1000
1001         switch (hw->phy.sfp_type) {
1002         case ixgbe_sfp_type_unknown:
1003                 return IXGBE_SUCCESS;
1004         case ixgbe_sfp_type_not_present:
1005                 return IXGBE_ERR_SFP_NOT_PRESENT;
1006         case ixgbe_sfp_type_da_cu_core0:
1007         case ixgbe_sfp_type_da_cu_core1:
1008                 setup_linear = true;
1009                 break;
1010         case ixgbe_sfp_type_srlr_core0:
1011         case ixgbe_sfp_type_srlr_core1:
1012         case ixgbe_sfp_type_da_act_lmt_core0:
1013         case ixgbe_sfp_type_da_act_lmt_core1:
1014         case ixgbe_sfp_type_1g_sx_core0:
1015         case ixgbe_sfp_type_1g_sx_core1:
1016         case ixgbe_sfp_type_1g_lx_core0:
1017         case ixgbe_sfp_type_1g_lx_core1:
1018                 setup_linear = false;
1019                 break;
1020         default:
1021                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1022         }
1023
1024         ixgbe_init_mac_link_ops_X550em(hw);
1025         hw->phy.ops.reset = NULL;
1026
1027         /* The CS4227 slice address is the base address + the port-pair reg
1028          * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
1029          */
1030         reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12);
1031
1032         if (setup_linear)
1033                 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1034         else
1035                 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1036
1037         /* Configure CS4227 for connection type. */
1038         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1039                                            edc_mode);
1040
1041         if (ret_val != IXGBE_SUCCESS)
1042                 ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice,
1043                                                    edc_mode);
1044
1045         return ret_val;
1046 }
1047
1048 /**
1049  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1050  *  @hw: pointer to hardware structure
1051  */
1052 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1053 {
1054         struct ixgbe_mac_info *mac = &hw->mac;
1055
1056         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1057
1058         /* CS4227 does not support autoneg, so disable the laser control
1059          * functions for SFP+ fiber
1060          */
1061          if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1062                 mac->ops.disable_tx_laser = NULL;
1063                 mac->ops.enable_tx_laser = NULL;
1064                 mac->ops.flap_tx_laser = NULL;
1065                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1066                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1067                 mac->ops.set_rate_select_speed =
1068                                         ixgbe_set_soft_rate_select_speed;
1069          }
1070 }
1071
1072 /**
1073  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1074  *  @hw: pointer to hardware structure
1075  *  @speed: pointer to link speed
1076  *  @autoneg: true when autoneg or autotry is enabled
1077  */
1078 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1079                                        ixgbe_link_speed *speed,
1080                                        bool *autoneg)
1081 {
1082         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1083
1084         /* SFP */
1085         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1086
1087                 /* CS4227 SFP must not enable auto-negotiation */
1088                 *autoneg = false;
1089
1090                 /* Check if 1G SFP module. */
1091                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1092                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1093                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1094                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1095                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1096                         return IXGBE_SUCCESS;
1097                 }
1098
1099                 /* Link capabilities are based on SFP */
1100                 if (hw->phy.multispeed_fiber)
1101                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1102                                  IXGBE_LINK_SPEED_1GB_FULL;
1103                 else
1104                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1105         } else {
1106                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1107                          IXGBE_LINK_SPEED_1GB_FULL;
1108                 *autoneg = true;
1109         }
1110
1111         return IXGBE_SUCCESS;
1112 }
1113
1114 /**
1115  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1116  *  @hw: pointer to hardware structure
1117  *
1118  *  Initialize any function pointers that were not able to be
1119  *  set during init_shared_code because the PHY/SFP type was
1120  *  not known.  Perform the SFP init if necessary.
1121  */
1122 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1123 {
1124         struct ixgbe_phy_info *phy = &hw->phy;
1125         s32 ret_val;
1126
1127         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1128
1129         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1130                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1131                 ixgbe_setup_mux_ctl(hw);
1132         }
1133
1134         /* Identify the PHY or SFP module */
1135         ret_val = phy->ops.identify(hw);
1136         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1137                 return ret_val;
1138
1139         /* Setup function pointers based on detected SFP module and speeds */
1140         ixgbe_init_mac_link_ops_X550em(hw);
1141         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1142                 phy->ops.reset = NULL;
1143
1144         /* Set functions pointers based on phy type */
1145         switch (hw->phy.type) {
1146         case ixgbe_phy_x550em_kx4:
1147                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1148                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1149                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1150                 break;
1151         case ixgbe_phy_x550em_kr:
1152                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1153                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1154                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1155                 break;
1156         case ixgbe_phy_x550em_ext_t:
1157                 phy->ops.setup_internal_link =
1158                                          ixgbe_setup_internal_phy_t_x550em;
1159                 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1160                 break;
1161         default:
1162                 break;
1163         }
1164         return ret_val;
1165 }
1166
1167 /**
1168  *  ixgbe_reset_hw_X550em - Perform hardware reset
1169  *  @hw: pointer to hardware structure
1170  *
1171  *  Resets the hardware by resetting the transmit and receive units, masks
1172  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1173  *  reset.
1174  */
1175 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1176 {
1177         struct ixgbe_hic_hdr fw_cmd;
1178         ixgbe_link_speed link_speed;
1179         s32 status;
1180         u32 ctrl = 0;
1181         u32 i;
1182         bool link_up = false;
1183
1184         DEBUGFUNC("ixgbe_reset_hw_X550em");
1185
1186         fw_cmd.cmd = FW_PHY_MGMT_REQ_CMD;
1187         fw_cmd.buf_len = 0;
1188         fw_cmd.cmd_or_resp.cmd_resv = 0;
1189         fw_cmd.checksum = FW_DEFAULT_CHECKSUM;
1190         status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
1191                                               sizeof(fw_cmd),
1192                                               IXGBE_HI_PHY_MGMT_REQ_TIMEOUT,
1193                                               true);
1194         if (status)
1195                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1196                               "PHY mgmt command failed with %d\n", status);
1197         else if (fw_cmd.cmd_or_resp.ret_status != FW_CEM_RESP_STATUS_SUCCESS)
1198                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1199                               "PHY mgmt command returned %d\n",
1200                               fw_cmd.cmd_or_resp.ret_status);
1201
1202         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1203         status = hw->mac.ops.stop_adapter(hw);
1204         if (status != IXGBE_SUCCESS)
1205                 return status;
1206
1207         /* flush pending Tx transactions */
1208         ixgbe_clear_tx_pending(hw);
1209
1210         /* PHY ops must be identified and initialized prior to reset */
1211
1212         /* Identify PHY and related function pointers */
1213         status = hw->phy.ops.init(hw);
1214
1215         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1216                 return status;
1217
1218         /* start the external PHY */
1219         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1220                 status = ixgbe_init_ext_t_x550em(hw);
1221                 if (status)
1222                         return status;
1223         }
1224
1225         /* Setup SFP module if there is one present. */
1226         if (hw->phy.sfp_setup_needed) {
1227                 status = hw->mac.ops.setup_sfp(hw);
1228                 hw->phy.sfp_setup_needed = false;
1229         }
1230
1231         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1232                 return status;
1233
1234         /* Reset PHY */
1235         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1236                 hw->phy.ops.reset(hw);
1237
1238 mac_reset_top:
1239         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1240          * If link reset is used when link is up, it might reset the PHY when
1241          * mng is using it.  If link is down or the flag to force full link
1242          * reset is set, then perform link reset.
1243          */
1244         ctrl = IXGBE_CTRL_LNK_RST;
1245         if (!hw->force_full_reset) {
1246                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1247                 if (link_up)
1248                         ctrl = IXGBE_CTRL_RST;
1249         }
1250
1251         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1252         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1253         IXGBE_WRITE_FLUSH(hw);
1254
1255         /* Poll for reset bit to self-clear meaning reset is complete */
1256         for (i = 0; i < 10; i++) {
1257                 usec_delay(1);
1258                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1259                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1260                         break;
1261         }
1262
1263         if (ctrl & IXGBE_CTRL_RST_MASK) {
1264                 status = IXGBE_ERR_RESET_FAILED;
1265                 DEBUGOUT("Reset polling failed to complete.\n");
1266         }
1267
1268         msec_delay(50);
1269
1270         /* Double resets are required for recovery from certain error
1271          * conditions.  Between resets, it is necessary to stall to
1272          * allow time for any pending HW events to complete.
1273          */
1274         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1275                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1276                 goto mac_reset_top;
1277         }
1278
1279         /* Store the permanent mac address */
1280         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1281
1282         /* Store MAC address from RAR0, clear receive address registers, and
1283          * clear the multicast table.  Also reset num_rar_entries to 128,
1284          * since we modify this value when programming the SAN MAC address.
1285          */
1286         hw->mac.num_rar_entries = 128;
1287         hw->mac.ops.init_rx_addrs(hw);
1288
1289
1290         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1291                 ixgbe_setup_mux_ctl(hw);
1292
1293         return status;
1294 }
1295
1296 /**
1297  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1298  * @hw: pointer to hardware structure
1299  */
1300 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1301 {
1302         u32 status;
1303         u16 reg;
1304
1305         status = hw->phy.ops.read_reg(hw,
1306                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1307                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1308                                       &reg);
1309
1310         if (status != IXGBE_SUCCESS)
1311                 return status;
1312
1313         /* If PHY FW reset completed bit is set then this is the first
1314          * SW instance after a power on so the PHY FW must be un-stalled.
1315          */
1316         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1317                 status = hw->phy.ops.read_reg(hw,
1318                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1319                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1320                                         &reg);
1321
1322                 if (status != IXGBE_SUCCESS)
1323                         return status;
1324
1325                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1326
1327                 status = hw->phy.ops.write_reg(hw,
1328                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1329                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1330                                         reg);
1331
1332                 if (status != IXGBE_SUCCESS)
1333                         return status;
1334         }
1335
1336         return status;
1337 }
1338
1339 /**
1340  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1341  *  @hw: pointer to hardware structure
1342  *
1343  *  Configures the integrated KR PHY.
1344  **/
1345 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1346 {
1347         s32 status;
1348         u32 reg_val;
1349
1350         status = ixgbe_read_iosf_sb_reg_x550(hw,
1351                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1352                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1353         if (status)
1354                 return status;
1355
1356         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1357         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1358                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1359         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1360                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1361
1362         /* Advertise 10G support. */
1363         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1364                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1365
1366         /* Advertise 1G support. */
1367         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1368                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1369
1370         /* Restart auto-negotiation. */
1371         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1372         status = ixgbe_write_iosf_sb_reg_x550(hw,
1373                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1374                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1375
1376         return status;
1377 }
1378
1379 /**
1380  *  ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1381  *  @hw: pointer to hardware structure
1382  *
1383  *  Configures the integrated KX4 PHY.
1384  **/
1385 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1386 {
1387         s32 status;
1388         u32 reg_val;
1389
1390         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1391                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, &reg_val);
1392         if (status)
1393                 return status;
1394
1395         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1396                         IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1397
1398         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1399
1400         /* Advertise 10G support. */
1401         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1402                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1403
1404         /* Advertise 1G support. */
1405         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1406                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1407
1408         /* Restart auto-negotiation. */
1409         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1410         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1411                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, reg_val);
1412
1413         return status;
1414 }
1415
1416 /**
1417  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1418  *  @hw: pointer to hardware structure
1419  *  @speed: the link speed to force
1420  *
1421  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1422  *  internal and external PHY at a specific speed, without autonegotiation.
1423  **/
1424 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1425 {
1426         s32 status;
1427         u32 reg_val;
1428
1429         /* Disable AN and force speed to 10G Serial. */
1430         status = ixgbe_read_iosf_sb_reg_x550(hw,
1431                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1432                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1433         if (status != IXGBE_SUCCESS)
1434                 return status;
1435
1436         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1437         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1438
1439         /* Select forced link speed for internal PHY. */
1440         switch (*speed) {
1441         case IXGBE_LINK_SPEED_10GB_FULL:
1442                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1443                 break;
1444         case IXGBE_LINK_SPEED_1GB_FULL:
1445                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1446                 break;
1447         default:
1448                 /* Other link speeds are not supported by internal KR PHY. */
1449                 return IXGBE_ERR_LINK_SETUP;
1450         }
1451
1452         status = ixgbe_write_iosf_sb_reg_x550(hw,
1453                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1454                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1455         if (status != IXGBE_SUCCESS)
1456                 return status;
1457
1458         /* Disable training protocol FSM. */
1459         status = ixgbe_read_iosf_sb_reg_x550(hw,
1460                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1461                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1462         if (status != IXGBE_SUCCESS)
1463                 return status;
1464         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1465         status = ixgbe_write_iosf_sb_reg_x550(hw,
1466                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1467                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1468         if (status != IXGBE_SUCCESS)
1469                 return status;
1470
1471         /* Disable Flex from training TXFFE. */
1472         status = ixgbe_read_iosf_sb_reg_x550(hw,
1473                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1474                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1475         if (status != IXGBE_SUCCESS)
1476                 return status;
1477         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1478         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1479         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1480         status = ixgbe_write_iosf_sb_reg_x550(hw,
1481                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1482                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1483         if (status != IXGBE_SUCCESS)
1484                 return status;
1485         status = ixgbe_read_iosf_sb_reg_x550(hw,
1486                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1487                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1488         if (status != IXGBE_SUCCESS)
1489                 return status;
1490         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1491         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1492         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1493         status = ixgbe_write_iosf_sb_reg_x550(hw,
1494                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1495                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1496         if (status != IXGBE_SUCCESS)
1497                 return status;
1498
1499         /* Enable override for coefficients. */
1500         status = ixgbe_read_iosf_sb_reg_x550(hw,
1501                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1502                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1503         if (status != IXGBE_SUCCESS)
1504                 return status;
1505         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1506         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1507         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1508         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1509         status = ixgbe_write_iosf_sb_reg_x550(hw,
1510                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1511                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1512         if (status != IXGBE_SUCCESS)
1513                 return status;
1514
1515         /* Toggle port SW reset by AN reset. */
1516         status = ixgbe_read_iosf_sb_reg_x550(hw,
1517                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1518                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1519         if (status != IXGBE_SUCCESS)
1520                 return status;
1521         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1522         status = ixgbe_write_iosf_sb_reg_x550(hw,
1523                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1524                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1525
1526         return status;
1527 }
1528
1529 /**
1530  *  ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1531  *  @hw: pointer to hardware structure
1532  *
1533  *  Configures the integrated KR PHY for SFP support.
1534  **/
1535 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1536                                     ixgbe_link_speed speed,
1537                                     bool autoneg_wait_to_complete)
1538 {
1539         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1540
1541         return ixgbe_setup_ixfi_x550em(hw, &speed);
1542 }
1543
1544 /**
1545  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1546  * @hw: point to hardware structure
1547  *
1548  * Configures the link between the integrated KR PHY and the external X557 PHY
1549  * The driver will call this function when it gets a link status change
1550  * interrupt from the X557 PHY. This function configures the link speed
1551  * between the PHYs to match the link speed of the BASE-T link.
1552  *
1553  * A return of a non-zero value indicates an error, and the base driver should
1554  * not report link up.
1555  */
1556 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1557 {
1558         u32 status;
1559         u16 autoneg_status, speed;
1560         ixgbe_link_speed force_speed;
1561
1562         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1563                 return IXGBE_ERR_CONFIG;
1564
1565         /* read this twice back to back to indicate current status */
1566         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1567                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1568                                       &autoneg_status);
1569         if (status != IXGBE_SUCCESS)
1570                 return status;
1571
1572         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1573                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1574                                       &autoneg_status);
1575         if (status != IXGBE_SUCCESS)
1576                 return status;
1577
1578         /* If link is not up, then there is no setup necessary so return  */
1579         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1580                 return IXGBE_SUCCESS;
1581
1582         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1583                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1584                                       &speed);
1585
1586         /* clear everything but the speed and duplex bits */
1587         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1588
1589         switch (speed) {
1590         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1591                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1592                 break;
1593         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1594                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1595                 break;
1596         default:
1597                 /* Internal PHY does not support anything else */
1598                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1599         }
1600
1601         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1602 }
1603
1604 /**
1605  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1606  *  @hw: pointer to hardware structure
1607  *
1608  *  Configures the integrated KR PHY to use internal loopback mode.
1609  **/
1610 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1611 {
1612         s32 status;
1613         u32 reg_val;
1614
1615         /* Disable AN and force speed to 10G Serial. */
1616         status = ixgbe_read_iosf_sb_reg_x550(hw,
1617                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1618                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1619         if (status != IXGBE_SUCCESS)
1620                 return status;
1621         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1622         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1623         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1624         status = ixgbe_write_iosf_sb_reg_x550(hw,
1625                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1626                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1627         if (status != IXGBE_SUCCESS)
1628                 return status;
1629
1630         /* Set near-end loopback clocks. */
1631         status = ixgbe_read_iosf_sb_reg_x550(hw,
1632                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1633                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1634         if (status != IXGBE_SUCCESS)
1635                 return status;
1636         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1637         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1638         status = ixgbe_write_iosf_sb_reg_x550(hw,
1639                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1640                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1641         if (status != IXGBE_SUCCESS)
1642                 return status;
1643
1644         /* Set loopback enable. */
1645         status = ixgbe_read_iosf_sb_reg_x550(hw,
1646                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1647                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1648         if (status != IXGBE_SUCCESS)
1649                 return status;
1650         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1651         status = ixgbe_write_iosf_sb_reg_x550(hw,
1652                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1653                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1654         if (status != IXGBE_SUCCESS)
1655                 return status;
1656
1657         /* Training bypass. */
1658         status = ixgbe_read_iosf_sb_reg_x550(hw,
1659                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1660                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1661         if (status != IXGBE_SUCCESS)
1662                 return status;
1663         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1664         status = ixgbe_write_iosf_sb_reg_x550(hw,
1665                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1666                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1667
1668         return status;
1669 }
1670
1671 /**
1672  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1673  *  assuming that the semaphore is already obtained.
1674  *  @hw: pointer to hardware structure
1675  *  @offset: offset of  word in the EEPROM to read
1676  *  @data: word read from the EEPROM
1677  *
1678  *  Reads a 16 bit word from the EEPROM using the hostif.
1679  **/
1680 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1681                                    u16 *data)
1682 {
1683         s32 status;
1684         struct ixgbe_hic_read_shadow_ram buffer;
1685
1686         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1687         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1688         buffer.hdr.req.buf_lenh = 0;
1689         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1690         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1691
1692         /* convert offset from words to bytes */
1693         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1694         /* one word */
1695         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1696
1697         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1698                                               sizeof(buffer),
1699                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1700
1701         if (status)
1702                 return status;
1703
1704         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1705                                           FW_NVM_DATA_OFFSET);
1706
1707         return 0;
1708 }
1709
1710 /**
1711  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1712  *  @hw: pointer to hardware structure
1713  *  @offset: offset of  word in the EEPROM to read
1714  *  @data: word read from the EEPROM
1715  *
1716  *  Reads a 16 bit word from the EEPROM using the hostif.
1717  **/
1718 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1719                               u16 *data)
1720 {
1721         s32 status = IXGBE_SUCCESS;
1722
1723         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1724
1725         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1726             IXGBE_SUCCESS) {
1727                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1728                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1729         } else {
1730                 status = IXGBE_ERR_SWFW_SYNC;
1731         }
1732
1733         return status;
1734 }
1735
1736 /**
1737  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1738  *  @hw: pointer to hardware structure
1739  *  @offset: offset of  word in the EEPROM to read
1740  *  @words: number of words
1741  *  @data: word(s) read from the EEPROM
1742  *
1743  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
1744  **/
1745 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1746                                      u16 offset, u16 words, u16 *data)
1747 {
1748         struct ixgbe_hic_read_shadow_ram buffer;
1749         u32 current_word = 0;
1750         u16 words_to_read;
1751         s32 status;
1752         u32 i;
1753
1754         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1755
1756         /* Take semaphore for the entire operation. */
1757         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1758         if (status) {
1759                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1760                 return status;
1761         }
1762         while (words) {
1763                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1764                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1765                 else
1766                         words_to_read = words;
1767
1768                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1769                 buffer.hdr.req.buf_lenh = 0;
1770                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1771                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1772
1773                 /* convert offset from words to bytes */
1774                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1775                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1776
1777                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1778                                                       sizeof(buffer),
1779                                                       IXGBE_HI_COMMAND_TIMEOUT,
1780                                                       false);
1781
1782                 if (status) {
1783                         DEBUGOUT("Host interface command failed\n");
1784                         goto out;
1785                 }
1786
1787                 for (i = 0; i < words_to_read; i++) {
1788                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1789                                   2 * i;
1790                         u32 value = IXGBE_READ_REG(hw, reg);
1791
1792                         data[current_word] = (u16)(value & 0xffff);
1793                         current_word++;
1794                         i++;
1795                         if (i < words_to_read) {
1796                                 value >>= 16;
1797                                 data[current_word] = (u16)(value & 0xffff);
1798                                 current_word++;
1799                         }
1800                 }
1801                 words -= words_to_read;
1802         }
1803
1804 out:
1805         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1806         return status;
1807 }
1808
1809 /**
1810  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1811  *  @hw: pointer to hardware structure
1812  *  @offset: offset of  word in the EEPROM to write
1813  *  @data: word write to the EEPROM
1814  *
1815  *  Write a 16 bit word to the EEPROM using the hostif.
1816  **/
1817 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1818                                     u16 data)
1819 {
1820         s32 status;
1821         struct ixgbe_hic_write_shadow_ram buffer;
1822
1823         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1824
1825         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1826         buffer.hdr.req.buf_lenh = 0;
1827         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
1828         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1829
1830          /* one word */
1831         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1832         buffer.data = data;
1833         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1834
1835         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1836                                               sizeof(buffer),
1837                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1838
1839         return status;
1840 }
1841
1842 /**
1843  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1844  *  @hw: pointer to hardware structure
1845  *  @offset: offset of  word in the EEPROM to write
1846  *  @data: word write to the EEPROM
1847  *
1848  *  Write a 16 bit word to the EEPROM using the hostif.
1849  **/
1850 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1851                                u16 data)
1852 {
1853         s32 status = IXGBE_SUCCESS;
1854
1855         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
1856
1857         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1858             IXGBE_SUCCESS) {
1859                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1860                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1861         } else {
1862                 DEBUGOUT("write ee hostif failed to get semaphore");
1863                 status = IXGBE_ERR_SWFW_SYNC;
1864         }
1865
1866         return status;
1867 }
1868
1869 /**
1870  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1871  *  @hw: pointer to hardware structure
1872  *  @offset: offset of  word in the EEPROM to write
1873  *  @words: number of words
1874  *  @data: word(s) write to the EEPROM
1875  *
1876  *  Write a 16 bit word(s) to the EEPROM using the hostif.
1877  **/
1878 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1879                                       u16 offset, u16 words, u16 *data)
1880 {
1881         s32 status = IXGBE_SUCCESS;
1882         u32 i = 0;
1883
1884         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
1885
1886         /* Take semaphore for the entire operation. */
1887         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1888         if (status != IXGBE_SUCCESS) {
1889                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
1890                 goto out;
1891         }
1892
1893         for (i = 0; i < words; i++) {
1894                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1895                                                          data[i]);
1896
1897                 if (status != IXGBE_SUCCESS) {
1898                         DEBUGOUT("Eeprom buffered write failed\n");
1899                         break;
1900                 }
1901         }
1902
1903         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1904 out:
1905
1906         return status;
1907 }
1908
1909 /**
1910  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
1911  * @hw: pointer to hardware structure
1912  * @ptr: pointer offset in eeprom
1913  * @size: size of section pointed by ptr, if 0 first word will be used as size
1914  * @csum: address of checksum to update
1915  *
1916  * Returns error status for any failure
1917  */
1918 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
1919                                    u16 size, u16 *csum, u16 *buffer,
1920                                    u32 buffer_size)
1921 {
1922         u16 buf[256];
1923         s32 status;
1924         u16 length, bufsz, i, start;
1925         u16 *local_buffer;
1926
1927         bufsz = sizeof(buf) / sizeof(buf[0]);
1928
1929         /* Read a chunk at the pointer location */
1930         if (!buffer) {
1931                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
1932                 if (status) {
1933                         DEBUGOUT("Failed to read EEPROM image\n");
1934                         return status;
1935                 }
1936                 local_buffer = buf;
1937         } else {
1938                 if (buffer_size < ptr)
1939                         return  IXGBE_ERR_PARAM;
1940                 local_buffer = &buffer[ptr];
1941         }
1942
1943         if (size) {
1944                 start = 0;
1945                 length = size;
1946         } else {
1947                 start = 1;
1948                 length = local_buffer[0];
1949
1950                 /* Skip pointer section if length is invalid. */
1951                 if (length == 0xFFFF || length == 0 ||
1952                     (ptr + length) >= hw->eeprom.word_size)
1953                         return IXGBE_SUCCESS;
1954         }
1955
1956         if (buffer && ((u32)start + (u32)length > buffer_size))
1957                 return IXGBE_ERR_PARAM;
1958
1959         for (i = start; length; i++, length--) {
1960                 if (i == bufsz && !buffer) {
1961                         ptr += bufsz;
1962                         i = 0;
1963                         if (length < bufsz)
1964                                 bufsz = length;
1965
1966                         /* Read a chunk at the pointer location */
1967                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
1968                                                                   bufsz, buf);
1969                         if (status) {
1970                                 DEBUGOUT("Failed to read EEPROM image\n");
1971                                 return status;
1972                         }
1973                 }
1974                 *csum += local_buffer[i];
1975         }
1976         return IXGBE_SUCCESS;
1977 }
1978
1979 /**
1980  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
1981  *  @hw: pointer to hardware structure
1982  *  @buffer: pointer to buffer containing calculated checksum
1983  *  @buffer_size: size of buffer
1984  *
1985  *  Returns a negative error code on error, or the 16-bit checksum
1986  **/
1987 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
1988 {
1989         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
1990         u16 *local_buffer;
1991         s32 status;
1992         u16 checksum = 0;
1993         u16 pointer, i, size;
1994
1995         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
1996
1997         hw->eeprom.ops.init_params(hw);
1998
1999         if (!buffer) {
2000                 /* Read pointer area */
2001                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2002                                                      IXGBE_EEPROM_LAST_WORD + 1,
2003                                                      eeprom_ptrs);
2004                 if (status) {
2005                         DEBUGOUT("Failed to read EEPROM image\n");
2006                         return status;
2007                 }
2008                 local_buffer = eeprom_ptrs;
2009         } else {
2010                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2011                         return IXGBE_ERR_PARAM;
2012                 local_buffer = buffer;
2013         }
2014
2015         /*
2016          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2017          * checksum word itself
2018          */
2019         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2020                 if (i != IXGBE_EEPROM_CHECKSUM)
2021                         checksum += local_buffer[i];
2022
2023         /*
2024          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2025          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2026          */
2027         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2028                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2029                         continue;
2030
2031                 pointer = local_buffer[i];
2032
2033                 /* Skip pointer section if the pointer is invalid. */
2034                 if (pointer == 0xFFFF || pointer == 0 ||
2035                     pointer >= hw->eeprom.word_size)
2036                         continue;
2037
2038                 switch (i) {
2039                 case IXGBE_PCIE_GENERAL_PTR:
2040                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2041                         break;
2042                 case IXGBE_PCIE_CONFIG0_PTR:
2043                 case IXGBE_PCIE_CONFIG1_PTR:
2044                         size = IXGBE_PCIE_CONFIG_SIZE;
2045                         break;
2046                 default:
2047                         size = 0;
2048                         break;
2049                 }
2050
2051                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2052                                                 buffer, buffer_size);
2053                 if (status)
2054                         return status;
2055         }
2056
2057         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2058
2059         return (s32)checksum;
2060 }
2061
2062 /**
2063  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2064  *  @hw: pointer to hardware structure
2065  *
2066  *  Returns a negative error code on error, or the 16-bit checksum
2067  **/
2068 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2069 {
2070         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2071 }
2072
2073 /**
2074  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2075  *  @hw: pointer to hardware structure
2076  *  @checksum_val: calculated checksum
2077  *
2078  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2079  *  caller does not need checksum_val, the value can be NULL.
2080  **/
2081 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2082 {
2083         s32 status;
2084         u16 checksum;
2085         u16 read_checksum = 0;
2086
2087         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2088
2089         /* Read the first word from the EEPROM. If this times out or fails, do
2090          * not continue or we could be in for a very long wait while every
2091          * EEPROM read fails
2092          */
2093         status = hw->eeprom.ops.read(hw, 0, &checksum);
2094         if (status) {
2095                 DEBUGOUT("EEPROM read failed\n");
2096                 return status;
2097         }
2098
2099         status = hw->eeprom.ops.calc_checksum(hw);
2100         if (status < 0)
2101                 return status;
2102
2103         checksum = (u16)(status & 0xffff);
2104
2105         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2106                                            &read_checksum);
2107         if (status)
2108                 return status;
2109
2110         /* Verify read checksum from EEPROM is the same as
2111          * calculated checksum
2112          */
2113         if (read_checksum != checksum) {
2114                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2115                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2116                              "Invalid EEPROM checksum");
2117         }
2118
2119         /* If the user cares, return the calculated checksum */
2120         if (checksum_val)
2121                 *checksum_val = checksum;
2122
2123         return status;
2124 }
2125
2126 /**
2127  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2128  * @hw: pointer to hardware structure
2129  *
2130  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2131  * checksum and updates the EEPROM and instructs the hardware to update
2132  * the flash.
2133  **/
2134 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2135 {
2136         s32 status;
2137         u16 checksum = 0;
2138
2139         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2140
2141         /* Read the first word from the EEPROM. If this times out or fails, do
2142          * not continue or we could be in for a very long wait while every
2143          * EEPROM read fails
2144          */
2145         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2146         if (status) {
2147                 DEBUGOUT("EEPROM read failed\n");
2148                 return status;
2149         }
2150
2151         status = ixgbe_calc_eeprom_checksum_X550(hw);
2152         if (status < 0)
2153                 return status;
2154
2155         checksum = (u16)(status & 0xffff);
2156
2157         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2158                                             checksum);
2159         if (status)
2160                 return status;
2161
2162         status = ixgbe_update_flash_X550(hw);
2163
2164         return status;
2165 }
2166
2167 /**
2168  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2169  *  @hw: pointer to hardware structure
2170  *
2171  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2172  **/
2173 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2174 {
2175         s32 status = IXGBE_SUCCESS;
2176         union ixgbe_hic_hdr2 buffer;
2177
2178         DEBUGFUNC("ixgbe_update_flash_X550");
2179
2180         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2181         buffer.req.buf_lenh = 0;
2182         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2183         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2184
2185         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2186                                               sizeof(buffer),
2187                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2188
2189         return status;
2190 }
2191
2192 /**
2193  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2194  *  @hw: pointer to hardware structure
2195  *
2196  *  Determines physical layer capabilities of the current configuration.
2197  **/
2198 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2199 {
2200         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2201         u16 ext_ability = 0;
2202
2203         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2204
2205         hw->phy.ops.identify(hw);
2206
2207         switch (hw->phy.type) {
2208         case ixgbe_phy_x550em_kr:
2209                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2210                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2211                 break;
2212         case ixgbe_phy_x550em_kx4:
2213                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2214                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2215                 break;
2216         case ixgbe_phy_x550em_ext_t:
2217                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2218                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2219                                      &ext_ability);
2220                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2221                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2222                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2223                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2224                 break;
2225         default:
2226                 break;
2227         }
2228
2229         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2230                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2231
2232         return physical_layer;
2233 }
2234
2235 /**
2236  * ixgbe_get_bus_info_x550em - Set PCI bus info
2237  * @hw: pointer to hardware structure
2238  *
2239  * Sets bus link width and speed to unknown because X550em is
2240  * not a PCI device.
2241  **/
2242 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2243 {
2244
2245         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2246
2247         hw->bus.width = ixgbe_bus_width_unknown;
2248         hw->bus.speed = ixgbe_bus_speed_unknown;
2249
2250         return IXGBE_SUCCESS;
2251 }
2252
2253 /**
2254  * ixgbe_disable_rx_x550 - Disable RX unit
2255  *
2256  * Enables the Rx DMA unit for x550
2257  **/
2258 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2259 {
2260         u32 rxctrl, pfdtxgswc;
2261         s32 status;
2262         struct ixgbe_hic_disable_rxen fw_cmd;
2263
2264         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2265
2266         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2267         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2268                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2269                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2270                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2271                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2272                         hw->mac.set_lben = true;
2273                 } else {
2274                         hw->mac.set_lben = false;
2275                 }
2276
2277                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2278                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2279                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2280                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2281
2282                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2283                                         sizeof(struct ixgbe_hic_disable_rxen),
2284                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2285
2286                 /* If we fail - disable RX using register write */
2287                 if (status) {
2288                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2289                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2290                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2291                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2292                         }
2293                 }
2294         }
2295 }
2296
2297 /**
2298  * ixgbe_enter_lplu_x550em - Transition to low power states
2299  *  @hw: pointer to hardware structure
2300  *
2301  * Configures Low Power Link Up on transition to low power states
2302  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2303  * X557 PHY immediately prior to entering LPLU.
2304  **/
2305 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2306 {
2307         u16 autoneg_status, an_10g_cntl_reg, autoneg_reg, speed;
2308         s32 status;
2309         ixgbe_link_speed lcd_speed;
2310
2311         /* If blocked by MNG FW, then don't restart AN */
2312         if (ixgbe_check_reset_blocked(hw))
2313                 return IXGBE_SUCCESS;
2314
2315         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2316                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2317                                       &autoneg_status);
2318
2319         if (status != IXGBE_SUCCESS)
2320                 return status;
2321
2322         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2323
2324         if (status != IXGBE_SUCCESS)
2325                 return status;
2326
2327         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2328          * disabled, then force link down by entering low power mode.
2329          */
2330         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS) ||
2331             !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2332             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2333                 return ixgbe_set_copper_phy_power(hw, FALSE);
2334
2335         /* Determine LCD */
2336         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2337
2338         if (status != IXGBE_SUCCESS)
2339                 return status;
2340
2341         /* If no valid LCD link speed, then force link down and exit. */
2342         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2343                 return ixgbe_set_copper_phy_power(hw, FALSE);
2344
2345         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2346                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2347                                       &speed);
2348
2349         if (status != IXGBE_SUCCESS)
2350                 return status;
2351
2352         /* clear everything but the speed bits */
2353         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2354
2355         /* If current speed is already LCD, then exit. */
2356         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2357              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2358             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2359              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2360                 return status;
2361
2362         /* Clear AN completed indication */
2363         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2364                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2365                                       &autoneg_status);
2366
2367         if (status != IXGBE_SUCCESS)
2368                 return status;
2369
2370         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2371                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2372                              &an_10g_cntl_reg);
2373
2374         if (status != IXGBE_SUCCESS)
2375                 return status;
2376
2377         status = hw->phy.ops.read_reg(hw,
2378                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2379                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2380                              &autoneg_reg);
2381
2382         if (status != IXGBE_SUCCESS)
2383                 return status;
2384
2385         /* Set AN advertizement to only include LCD  */
2386         if (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL) {
2387                 an_10g_cntl_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
2388                 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
2389         }
2390
2391         if (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL) {
2392                 an_10g_cntl_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
2393                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
2394         }
2395
2396         status = hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2397                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2398                               an_10g_cntl_reg);
2399
2400         if (status != IXGBE_SUCCESS)
2401                 return status;
2402
2403         status = hw->phy.ops.write_reg(hw,
2404                               IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2405                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2406                               autoneg_reg);
2407
2408         if (status != IXGBE_SUCCESS)
2409                 return status;
2410
2411         /* Restart PHY auto-negotiation. */
2412         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
2413                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
2414
2415         if (status != IXGBE_SUCCESS)
2416                 return status;
2417
2418         autoneg_reg |= IXGBE_MII_RESTART;
2419
2420         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
2421                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
2422
2423         if (status != IXGBE_SUCCESS)
2424                 return status;
2425
2426         status = ixgbe_setup_ixfi_x550em(hw, &lcd_speed);
2427
2428         return status;
2429 }
2430
2431 /**
2432  * ixgbe_get_lcd_x550em - Determine lowest common denominator
2433  *  @hw: pointer to hardware structure
2434  *  @lcd_speed: pointer to lowest common link speed
2435  *
2436  * Determine lowest common link speed with link partner.
2437  **/
2438 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2439 {
2440         u16 an_lp_status;
2441         s32 status;
2442         u16 word = hw->eeprom.ctrl_word_3;
2443
2444         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2445
2446         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2447                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2448                                       &an_lp_status);
2449
2450         if (status != IXGBE_SUCCESS)
2451                 return status;
2452
2453         /* If link partner advertised 1G, return 1G */
2454         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2455                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2456                 return status;
2457         }
2458
2459         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2460         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2461             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2462                 return status;
2463
2464         /* Link partner not capable of lower speeds, return 10G */
2465         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2466         return status;
2467 }
2468
2469 /**
2470  *  ixgbe_setup_fc_X550em - Set up flow control
2471  *  @hw: pointer to hardware structure
2472  *
2473  *  Called at init time to set up flow control.
2474  **/
2475 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2476 {
2477         s32 ret_val = IXGBE_SUCCESS;
2478         u32 pause, asm_dir, reg_val;
2479
2480         DEBUGFUNC("ixgbe_setup_fc_X550em");
2481
2482         /* Validate the requested mode */
2483         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2484                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2485                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2486                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2487                 goto out;
2488         }
2489
2490         /* 10gig parts do not have a word in the EEPROM to determine the
2491          * default flow control setting, so we explicitly set it to full.
2492          */
2493         if (hw->fc.requested_mode == ixgbe_fc_default)
2494                 hw->fc.requested_mode = ixgbe_fc_full;
2495
2496         /* Determine PAUSE and ASM_DIR bits. */
2497         switch (hw->fc.requested_mode) {
2498         case ixgbe_fc_none:
2499                 pause = 0;
2500                 asm_dir = 0;
2501                 break;
2502         case ixgbe_fc_tx_pause:
2503                 pause = 0;
2504                 asm_dir = 1;
2505                 break;
2506         case ixgbe_fc_rx_pause:
2507                 /* Rx Flow control is enabled and Tx Flow control is
2508                  * disabled by software override. Since there really
2509                  * isn't a way to advertise that we are capable of RX
2510                  * Pause ONLY, we will advertise that we support both
2511                  * symmetric and asymmetric Rx PAUSE, as such we fall
2512                  * through to the fc_full statement.  Later, we will
2513                  * disable the adapter's ability to send PAUSE frames.
2514                  */
2515         case ixgbe_fc_full:
2516                 pause = 1;
2517                 asm_dir = 1;
2518                 break;
2519         default:
2520                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2521                         "Flow control param set incorrectly\n");
2522                 ret_val = IXGBE_ERR_CONFIG;
2523                 goto out;
2524         }
2525
2526         if (hw->phy.media_type == ixgbe_media_type_backplane) {
2527                 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2528                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2529                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2530                 if (ret_val != IXGBE_SUCCESS)
2531                         goto out;
2532                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2533                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2534                 if (pause)
2535                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2536                 if (asm_dir)
2537                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2538                 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2539                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2540                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2541
2542                 /* Not all devices fully support AN. */
2543                 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR)
2544                         hw->fc.disable_fc_autoneg = true;
2545         }
2546
2547 out:
2548         return ret_val;
2549 }
2550
2551 /**
2552  * ixgbe_set_mux - Set mux for port 1 access with CS4227
2553  * @hw: pointer to hardware structure
2554  * @state: set mux if 1, clear if 0
2555  */
2556 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2557 {
2558         u32 esdp;
2559
2560         if (!hw->bus.lan_id)
2561                 return;
2562         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2563         if (state)
2564                 esdp |= IXGBE_ESDP_SDP1;
2565         else
2566                 esdp &= ~IXGBE_ESDP_SDP1;
2567         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2568         IXGBE_WRITE_FLUSH(hw);
2569 }
2570
2571 /**
2572  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2573  *  @hw: pointer to hardware structure
2574  *  @mask: Mask to specify which semaphore to acquire
2575  *
2576  *  Acquires the SWFW semaphore and sets the I2C MUX
2577  **/
2578 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2579 {
2580         s32 status;
2581
2582         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2583
2584         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2585         if (status)
2586                 return status;
2587
2588         if (mask & IXGBE_GSSR_I2C_MASK)
2589                 ixgbe_set_mux(hw, 1);
2590
2591         return IXGBE_SUCCESS;
2592 }
2593
2594 /**
2595  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2596  *  @hw: pointer to hardware structure
2597  *  @mask: Mask to specify which semaphore to release
2598  *
2599  *  Releases the SWFW semaphore and sets the I2C MUX
2600  **/
2601 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2602 {
2603         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
2604
2605         if (mask & IXGBE_GSSR_I2C_MASK)
2606                 ixgbe_set_mux(hw, 0);
2607
2608         ixgbe_release_swfw_sync_X540(hw, mask);
2609 }