drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41
  42 /**
  43  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  44  *  @hw: pointer to hardware structure
  45  *
  46  *  Initialize the function pointers and assign the MAC type for X550.
  47  *  Does not touch the hardware.
  48  **/
  49 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  50 {
  51         struct ixgbe_mac_info *mac = &hw->mac;
  52         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  53         s32 ret_val;
  54
  55         DEBUGFUNC("ixgbe_init_ops_X550");
  56
  57         ret_val = ixgbe_init_ops_X540(hw);
  58         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  59         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  60         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  61         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  62         mac->ops.set_source_address_pruning =
  63                         ixgbe_set_source_address_pruning_X550;
  64         mac->ops.set_ethertype_anti_spoofing =
  65                         ixgbe_set_ethertype_anti_spoofing_X550;
  66
  67         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  68         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  69         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  70         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  71         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  72         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  73         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  74         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  75         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  76
  77         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  78         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  79         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  80         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  81         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  82         return ret_val;
  83 }
  84
  85 /**
  86  * ixgbe_read_cs4227 - Read CS4227 register
  87  * @hw: pointer to hardware structure
  88  * @reg: register number to write
  89  * @value: pointer to receive value read
  90  *
  91  * Returns status code
  92  **/
  93 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  94 {
  95         return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
  96 }
  97
  98 /**
  99  * ixgbe_write_cs4227 - Write CS4227 register
 100  * @hw: pointer to hardware structure
 101  * @reg: register number to write
 102  * @value: value to write to register
 103  *
 104  * Returns status code
 105  **/
 106 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 107 {
 108         return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 109 }
 110
 111 /**
 112  * ixgbe_get_cs4227_status - Return CS4227 status
 113  * @hw: pointer to hardware structure
 114  *
 115  * Returns error if CS4227 not successfully initialized
 116  **/
 117 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
 118 {
 119         s32 status;
 120         u16 value = 0;
 121         u8 retry;
 122
 123         for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
 124                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
 125                                            &value);
 126                 if (status != IXGBE_SUCCESS)
 127                         return status;
 128                 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
 129                         break;
 130                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 131         }
 132         if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
 133                 return IXGBE_ERR_PHY;
 134
 135         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 136                                     IXGBE_CS4227_SCRATCH_VALUE);
 137         if (status != IXGBE_SUCCESS)
 138                 return status;
 139         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 140         if (status != IXGBE_SUCCESS)
 141                 return status;
 142         if (value != IXGBE_CS4227_SCRATCH_VALUE)
 143                 return IXGBE_ERR_PHY;
 144         return IXGBE_SUCCESS;
 145 }
 146
 147 /**
 148  * ixgbe_read_pe - Read register from port expander
 149  * @hw: pointer to hardware structure
 150  * @reg: register number to read
 151  * @value: pointer to receive read value
 152  *
 153  * Returns status code
 154  **/
 155 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 156 {
 157         s32 status;
 158
 159         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 160         if (status != IXGBE_SUCCESS)
 161                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 162                               "port expander access failed with %d\n", status);
 163         return status;
 164 }
 165
 166 /**
 167  * ixgbe_write_pe - Write register to port expander
 168  * @hw: pointer to hardware structure
 169  * @reg: register number to write
 170  * @value: value to write
 171  *
 172  * Returns status code
 173  **/
 174 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 175 {
 176         s32 status;
 177
 178         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 179         if (status != IXGBE_SUCCESS)
 180                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 181                               "port expander access failed with %d\n", status);
 182         return status;
 183 }
 184
 185 /**
 186  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 187  * @hw: pointer to hardware structure
 188  *
 189  * Returns error code
 190  **/
 191 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 192 {
 193         s32 status;
 194         u8 reg;
 195
 196         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199         reg |= IXGBE_PE_BIT1;
 200         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 201         if (status != IXGBE_SUCCESS)
 202                 return status;
 203
 204         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 205         if (status != IXGBE_SUCCESS)
 206                 return status;
 207         reg &= ~IXGBE_PE_BIT1;
 208         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 209         if (status != IXGBE_SUCCESS)
 210                 return status;
 211
 212         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 213         if (status != IXGBE_SUCCESS)
 214                 return status;
 215         reg &= ~IXGBE_PE_BIT1;
 216         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 217         if (status != IXGBE_SUCCESS)
 218                 return status;
 219
 220         usec_delay(IXGBE_CS4227_RESET_HOLD);
 221
 222         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 223         if (status != IXGBE_SUCCESS)
 224                 return status;
 225         reg |= IXGBE_PE_BIT1;
 226         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 227         if (status != IXGBE_SUCCESS)
 228                 return status;
 229
 230         msec_delay(IXGBE_CS4227_RESET_DELAY);
 231
 232         return IXGBE_SUCCESS;
 233 }
 234
 235 /**
 236  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 237  * @hw: pointer to hardware structure
 238  **/
 239 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 240 {
 241         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 242         s32 status;
 243         u8 retry;
 244
 245         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 246                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 247                 if (status != IXGBE_SUCCESS) {
 248                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 249                                       "semaphore failed with %d\n", status);
 250                         return;
 251                 }
 252                 status = ixgbe_get_cs4227_status(hw);
 253                 if (status == IXGBE_SUCCESS) {
 254                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 255                         msec_delay(hw->eeprom.semaphore_delay);
 256                         return;
 257                 }
 258                 ixgbe_reset_cs4227(hw);
 259                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 260                 msec_delay(hw->eeprom.semaphore_delay);
 261         }
 262         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 263                       "Unable to initialize CS4227, err=%d\n", status);
 264 }
 265
 266 /**
 267  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 268  * @hw: pointer to hardware structure
 269  **/
 270 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 271 {
 272         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 273
 274         if (hw->bus.lan_id) {
 275                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 276                 esdp |= IXGBE_ESDP_SDP1_DIR;
 277         }
 278         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 279         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 280         IXGBE_WRITE_FLUSH(hw);
 281 }
 282
 283 /**
 284  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 285  * @hw: pointer to hardware structure
 286  *
 287  * Returns error code
 288  */
 289 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 290 {
 291         switch (hw->device_id) {
 292         case IXGBE_DEV_ID_X550EM_X_SFP:
 293                 /* set up for CS4227 usage */
 294                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 295                 ixgbe_setup_mux_ctl(hw);
 296                 ixgbe_check_cs4227(hw);
 297
 298                 return ixgbe_identify_module_generic(hw);
 299                 break;
 300         case IXGBE_DEV_ID_X550EM_X_KX4:
 301                 hw->phy.type = ixgbe_phy_x550em_kx4;
 302                 break;
 303         case IXGBE_DEV_ID_X550EM_X_KR:
 304                 hw->phy.type = ixgbe_phy_x550em_kr;
 305                 break;
 306         case IXGBE_DEV_ID_X550EM_X_1G_T:
 307         case IXGBE_DEV_ID_X550EM_X_10G_T:
 308                 return ixgbe_identify_phy_generic(hw);
 309         default:
 310                 break;
 311         }
 312         return IXGBE_SUCCESS;
 313 }
 314
 315 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 316                                      u32 device_type, u16 *phy_data)
 317 {
 318         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 319         return IXGBE_NOT_IMPLEMENTED;
 320 }
 321
 322 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 323                                       u32 device_type, u16 phy_data)
 324 {
 325         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 326         return IXGBE_NOT_IMPLEMENTED;
 327 }
 328
 329 /**
 330 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 331 *  @hw: pointer to hardware structure
 332 *
 333 *  Initialize the function pointers and for MAC type X550EM.
 334 *  Does not touch the hardware.
 335 **/
 336 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 337 {
 338         struct ixgbe_mac_info *mac = &hw->mac;
 339         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 340         struct ixgbe_phy_info *phy = &hw->phy;
 341         s32 ret_val;
 342
 343         DEBUGFUNC("ixgbe_init_ops_X550EM");
 344
 345         /* Similar to X550 so start there. */
 346         ret_val = ixgbe_init_ops_X550(hw);
 347
 348         /* Since this function eventually calls
 349          * ixgbe_init_ops_540 by design, we are setting
 350          * the pointers to NULL explicitly here to overwrite
 351          * the values being set in the x540 function.
 352          */
 353         /* Thermal sensor not supported in x550EM */
 354         mac->ops.get_thermal_sensor_data = NULL;
 355         mac->ops.init_thermal_sensor_thresh = NULL;
 356         mac->thermal_sensor_enabled = false;
 357
 358         /* FCOE not supported in x550EM */
 359         mac->ops.get_san_mac_addr = NULL;
 360         mac->ops.set_san_mac_addr = NULL;
 361         mac->ops.get_wwn_prefix = NULL;
 362         mac->ops.get_fcoe_boot_status = NULL;
 363
 364         /* IPsec not supported in x550EM */
 365         mac->ops.disable_sec_rx_path = NULL;
 366         mac->ops.enable_sec_rx_path = NULL;
 367
 368         /* AUTOC register is not present in x550EM. */
 369         mac->ops.prot_autoc_read = NULL;
 370         mac->ops.prot_autoc_write = NULL;
 371
 372         /* X550EM bus type is internal*/
 373         hw->bus.type = ixgbe_bus_type_internal;
 374         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 375
 376         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 377         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 378         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 379         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 380         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 381         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 382         mac->ops.get_supported_physical_layer =
 383                                     ixgbe_get_supported_physical_layer_X550em;
 384
 385         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 386                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 387         else
 388                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 389
 390         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 391         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 392
 393         /* PHY */
 394         phy->ops.init = ixgbe_init_phy_ops_X550em;
 395         phy->ops.identify = ixgbe_identify_phy_x550em;
 396         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 397                 phy->ops.set_phy_power = NULL;
 398
 399
 400         /* EEPROM */
 401         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 402         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 403         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 404         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 405         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 406         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 407         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 408         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 409
 410         return ret_val;
 411 }
 412
 413 /**
 414  *  ixgbe_dmac_config_X550
 415  *  @hw: pointer to hardware structure
 416  *
 417  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 418  *  When disabling dmac, dmac enable dmac bit is cleared.
 419  **/
 420 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 421 {
 422         u32 reg, high_pri_tc;
 423
 424         DEBUGFUNC("ixgbe_dmac_config_X550");
 425
 426         /* Disable DMA coalescing before configuring */
 427         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 428         reg &= ~IXGBE_DMACR_DMAC_EN;
 429         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 430
 431         /* Disable DMA Coalescing if the watchdog timer is 0 */
 432         if (!hw->mac.dmac_config.watchdog_timer)
 433                 goto out;
 434
 435         ixgbe_dmac_config_tcs_X550(hw);
 436
 437         /* Configure DMA Coalescing Control Register */
 438         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 439
 440         /* Set the watchdog timer in units of 40.96 usec */
 441         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 442         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 443
 444         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 445         /* If fcoe is enabled, set high priority traffic class */
 446         if (hw->mac.dmac_config.fcoe_en) {
 447                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 448                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 449                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 450         }
 451         reg |= IXGBE_DMACR_EN_MNG_IND;
 452
 453         /* Enable DMA coalescing after configuration */
 454         reg |= IXGBE_DMACR_DMAC_EN;
 455         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 456
 457 out:
 458         return IXGBE_SUCCESS;
 459 }
 460
 461 /**
 462  *  ixgbe_dmac_config_tcs_X550
 463  *  @hw: pointer to hardware structure
 464  *
 465  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 466  *  be cleared before configuring.
 467  **/
 468 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 469 {
 470         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 471
 472         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 473
 474         /* Configure DMA coalescing enabled */
 475         switch (hw->mac.dmac_config.link_speed) {
 476         case IXGBE_LINK_SPEED_100_FULL:
 477                 pb_headroom = IXGBE_DMACRXT_100M;
 478                 break;
 479         case IXGBE_LINK_SPEED_1GB_FULL:
 480                 pb_headroom = IXGBE_DMACRXT_1G;
 481                 break;
 482         default:
 483                 pb_headroom = IXGBE_DMACRXT_10G;
 484                 break;
 485         }
 486
 487         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 488                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 489
 490         /* Set the per Rx packet buffer receive threshold */
 491         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 492                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 493                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 494
 495                 if (tc < hw->mac.dmac_config.num_tcs) {
 496                         /* Get Rx PB size */
 497                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 498                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 499                                 IXGBE_RXPBSIZE_SHIFT;
 500
 501                         /* Calculate receive buffer threshold in kilobytes */
 502                         if (rx_pb_size > pb_headroom)
 503                                 rx_pb_size = rx_pb_size - pb_headroom;
 504                         else
 505                                 rx_pb_size = 0;
 506
 507                         /* Minimum of MFS shall be set for DMCTH */
 508                         reg |= (rx_pb_size > maxframe_size_kb) ?
 509                                 rx_pb_size : maxframe_size_kb;
 510                 }
 511                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 512         }
 513         return IXGBE_SUCCESS;
 514 }
 515
 516 /**
 517  *  ixgbe_dmac_update_tcs_X550
 518  *  @hw: pointer to hardware structure
 519  *
 520  *  Disables dmac, updates per TC settings, and then enables dmac.
 521  **/
 522 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 523 {
 524         u32 reg;
 525
 526         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 527
 528         /* Disable DMA coalescing before configuring */
 529         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 530         reg &= ~IXGBE_DMACR_DMAC_EN;
 531         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 532
 533         ixgbe_dmac_config_tcs_X550(hw);
 534
 535         /* Enable DMA coalescing after configuration */
 536         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 537         reg |= IXGBE_DMACR_DMAC_EN;
 538         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 539
 540         return IXGBE_SUCCESS;
 541 }
 542
 543 /**
 544  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 545  *  @hw: pointer to hardware structure
 546  *
 547  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 548  *  ixgbe_hw struct in order to set up EEPROM access.
 549  **/
 550 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 551 {
 552         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 553         u32 eec;
 554         u16 eeprom_size;
 555
 556         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 557
 558         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 559                 eeprom->semaphore_delay = 10;
 560                 eeprom->type = ixgbe_flash;
 561
 562                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 563                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 564                                     IXGBE_EEC_SIZE_SHIFT);
 565                 eeprom->word_size = 1 << (eeprom_size +
 566                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 567
 568                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 569                           eeprom->type, eeprom->word_size);
 570         }
 571
 572         return IXGBE_SUCCESS;
 573 }
 574
 575 /**
 576  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 577  *  @hw: pointer to the HW structure
 578  *  @enable_eee: boolean flag to enable EEE
 579  *
 580  *  Enable/disable EEE based on enable_eee flag.
 581  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 582  *  are modified.
 583  *
 584  **/
 585 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 586 {
 587         u32 eeer;
 588         u16 autoneg_eee_reg;
 589         u32 link_reg;
 590         s32 status;
 591
 592         DEBUGFUNC("ixgbe_setup_eee_X550");
 593
 594         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 595         /* Enable or disable EEE per flag */
 596         if (enable_eee) {
 597                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 598
 599                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 600                         /* Advertise EEE capability */
 601                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 602                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 603
 604                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 605                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 606                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 607
 608                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 609                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 610                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 611                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 612                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 613                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 614                         if (status != IXGBE_SUCCESS)
 615                                 return status;
 616
 617                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 618                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 619
 620                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 621                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 622                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 623                         if (status != IXGBE_SUCCESS)
 624                                 return status;
 625                 }
 626         } else {
 627                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 628
 629                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 630                         /* Disable advertised EEE capability */
 631                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 632                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 633
 634                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 635                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 636                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 637
 638                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 639                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 640                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 641                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 642                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 643                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 644                         if (status != IXGBE_SUCCESS)
 645                                 return status;
 646
 647                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 648                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 649
 650                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 651                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 652                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 653                         if (status != IXGBE_SUCCESS)
 654                                 return status;
 655                 }
 656         }
 657         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 658
 659         return IXGBE_SUCCESS;
 660 }
 661
 662 /**
 663  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 664  * @hw: pointer to hardware structure
 665  * @enable: enable or disable source address pruning
 666  * @pool: Rx pool to set source address pruning for
 667  **/
 668 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 669                                            unsigned int pool)
 670 {
 671         u64 pfflp;
 672
 673         /* max rx pool is 63 */
 674         if (pool > 63)
 675                 return;
 676
 677         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 678         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 679
 680         if (enable)
 681                 pfflp |= (1ULL << pool);
 682         else
 683                 pfflp &= ~(1ULL << pool);
 684
 685         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 686         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 687 }
 688
 689 /**
 690  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 691  *  @hw: pointer to hardware structure
 692  *  @enable: enable or disable switch for Ethertype anti-spoofing
 693  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 694  *
 695  **/
 696 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 697                 bool enable, int vf)
 698 {
 699         int vf_target_reg = vf >> 3;
 700         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 701         u32 pfvfspoof;
 702
 703         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 704
 705         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 706         if (enable)
 707                 pfvfspoof |= (1 << vf_target_shift);
 708         else
 709                 pfvfspoof &= ~(1 << vf_target_shift);
 710
 711         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 712 }
 713
 714 /**
 715  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 716  *  device
 717  *  @hw: pointer to hardware structure
 718  *  @reg_addr: 32 bit PHY register to write
 719  *  @device_type: 3 bit device type
 720  *  @data: Data to write to the register
 721  **/
 722 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 723                             u32 device_type, u32 data)
 724 {
 725         u32 i, command, error;
 726
 727         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 728                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 729
 730         /* Write IOSF control register */
 731         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 732
 733         /* Write IOSF data register */
 734         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 735         /*
 736          * Check every 10 usec to see if the address cycle completed.
 737          * The SB IOSF BUSY bit will clear when the operation is
 738          * complete
 739          */
 740         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 741                 usec_delay(10);
 742
 743                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 744                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 745                         break;
 746         }
 747
 748         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 749                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 750                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 751                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 752                               "Failed to write, error %x\n", error);
 753                 return IXGBE_ERR_PHY;
 754         }
 755
 756         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 757                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
 758                 return IXGBE_ERR_PHY;
 759         }
 760
 761         return IXGBE_SUCCESS;
 762 }
 763
 764 /**
 765  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 766  *  device
 767  *  @hw: pointer to hardware structure
 768  *  @reg_addr: 32 bit PHY register to write
 769  *  @device_type: 3 bit device type
 770  *  @phy_data: Pointer to read data from the register
 771  **/
 772 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 773                            u32 device_type, u32 *data)
 774 {
 775         u32 i, command, error;
 776
 777         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 778                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 779
 780         /* Write IOSF control register */
 781         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 782
 783         /*
 784          * Check every 10 usec to see if the address cycle completed.
 785          * The SB IOSF BUSY bit will clear when the operation is
 786          * complete
 787          */
 788         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 789                 usec_delay(10);
 790
 791                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 792                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 793                         break;
 794         }
 795
 796         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 797                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 798                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 799                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 800                                 "Failed to read, error %x\n", error);
 801                 return IXGBE_ERR_PHY;
 802         }
 803
 804         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 805                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
 806                 return IXGBE_ERR_PHY;
 807         }
 808
 809         *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 810
 811         return IXGBE_SUCCESS;
 812 }
 813
 814 /**
 815  *  ixgbe_disable_mdd_X550
 816  *  @hw: pointer to hardware structure
 817  *
 818  *  Disable malicious driver detection
 819  **/
 820 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 821 {
 822         u32 reg;
 823
 824         DEBUGFUNC("ixgbe_disable_mdd_X550");
 825
 826         /* Disable MDD for TX DMA and interrupt */
 827         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 828         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 829         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 830
 831         /* Disable MDD for RX and interrupt */
 832         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 833         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 834         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 835 }
 836
 837 /**
 838  *  ixgbe_enable_mdd_X550
 839  *  @hw: pointer to hardware structure
 840  *
 841  *  Enable malicious driver detection
 842  **/
 843 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 844 {
 845         u32 reg;
 846
 847         DEBUGFUNC("ixgbe_enable_mdd_X550");
 848
 849         /* Enable MDD for TX DMA and interrupt */
 850         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 851         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 852         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 853
 854         /* Enable MDD for RX and interrupt */
 855         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 856         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 857         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 858 }
 859
 860 /**
 861  *  ixgbe_restore_mdd_vf_X550
 862  *  @hw: pointer to hardware structure
 863  *  @vf: vf index
 864  *
 865  *  Restore VF that was disabled during malicious driver detection event
 866  **/
 867 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 868 {
 869         u32 idx, reg, num_qs, start_q, bitmask;
 870
 871         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 872
 873         /* Map VF to queues */
 874         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 875         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 876         case IXGBE_MRQC_VMDQRT8TCEN:
 877                 num_qs = 8;  /* 16 VFs / pools */
 878                 bitmask = 0x000000FF;
 879                 break;
 880         case IXGBE_MRQC_VMDQRSS32EN:
 881         case IXGBE_MRQC_VMDQRT4TCEN:
 882                 num_qs = 4;  /* 32 VFs / pools */
 883                 bitmask = 0x0000000F;
 884                 break;
 885         default:            /* 64 VFs / pools */
 886                 num_qs = 2;
 887                 bitmask = 0x00000003;
 888                 break;
 889         }
 890         start_q = vf * num_qs;
 891
 892         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
 893         idx = start_q / 32;
 894         reg = 0;
 895         reg |= (bitmask << (start_q % 32));
 896         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
 897         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
 898 }
 899
 900 /**
 901  *  ixgbe_mdd_event_X550
 902  *  @hw: pointer to hardware structure
 903  *  @vf_bitmap: vf bitmap of malicious vfs
 904  *
 905  *  Handle malicious driver detection event.
 906  **/
 907 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
 908 {
 909         u32 wqbr;
 910         u32 i, j, reg, q, shift, vf, idx;
 911
 912         DEBUGFUNC("ixgbe_mdd_event_X550");
 913
 914         /* figure out pool size for mapping to vf's */
 915         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 916         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 917         case IXGBE_MRQC_VMDQRT8TCEN:
 918                 shift = 3;  /* 16 VFs / pools */
 919                 break;
 920         case IXGBE_MRQC_VMDQRSS32EN:
 921         case IXGBE_MRQC_VMDQRT4TCEN:
 922                 shift = 2;  /* 32 VFs / pools */
 923                 break;
 924         default:
 925                 shift = 1;  /* 64 VFs / pools */
 926                 break;
 927         }
 928
 929         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
 930         for (i = 0; i < 4; i++) {
 931                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
 932                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
 933
 934                 if (!wqbr)
 935                         continue;
 936
 937                 /* Get malicious queue */
 938                 for (j = 0; j < 32 && wqbr; j++) {
 939
 940                         if (!(wqbr & (1 << j)))
 941                                 continue;
 942
 943                         /* Get queue from bitmask */
 944                         q = j + (i * 32);
 945
 946                         /* Map queue to vf */
 947                         vf = (q >> shift);
 948
 949                         /* Set vf bit in vf_bitmap */
 950                         idx = vf / 32;
 951                         vf_bitmap[idx] |= (1 << (vf % 32));
 952                         wqbr &= ~(1 << j);
 953                 }
 954         }
 955 }
 956
 957 /**
 958  *  ixgbe_get_media_type_X550em - Get media type
 959  *  @hw: pointer to hardware structure
 960  *
 961  *  Returns the media type (fiber, copper, backplane)
 962  */
 963 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
 964 {
 965         enum ixgbe_media_type media_type;
 966
 967         DEBUGFUNC("ixgbe_get_media_type_X550em");
 968
 969         /* Detect if there is a copper PHY attached. */
 970         switch (hw->device_id) {
 971         case IXGBE_DEV_ID_X550EM_X_KR:
 972         case IXGBE_DEV_ID_X550EM_X_KX4:
 973                 media_type = ixgbe_media_type_backplane;
 974                 break;
 975         case IXGBE_DEV_ID_X550EM_X_SFP:
 976                 media_type = ixgbe_media_type_fiber;
 977                 break;
 978         case IXGBE_DEV_ID_X550EM_X_1G_T:
 979         case IXGBE_DEV_ID_X550EM_X_10G_T:
 980                 media_type = ixgbe_media_type_copper;
 981                 break;
 982         default:
 983                 media_type = ixgbe_media_type_unknown;
 984                 break;
 985         }
 986         return media_type;
 987 }
 988
 989 /**
 990  *  ixgbe_setup_sfp_modules_X550em - Setup SFP module
 991  *  @hw: pointer to hardware structure
 992  */
 993 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
 994 {
 995         bool setup_linear;
 996         u16 reg_slice, edc_mode;
 997         s32 ret_val;
 998
 999         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1000
1001         switch (hw->phy.sfp_type) {
1002         case ixgbe_sfp_type_unknown:
1003                 return IXGBE_SUCCESS;
1004         case ixgbe_sfp_type_not_present:
1005                 return IXGBE_ERR_SFP_NOT_PRESENT;
1006         case ixgbe_sfp_type_da_cu_core0:
1007         case ixgbe_sfp_type_da_cu_core1:
1008                 setup_linear = true;
1009                 break;
1010         case ixgbe_sfp_type_srlr_core0:
1011         case ixgbe_sfp_type_srlr_core1:
1012         case ixgbe_sfp_type_da_act_lmt_core0:
1013         case ixgbe_sfp_type_da_act_lmt_core1:
1014         case ixgbe_sfp_type_1g_sx_core0:
1015         case ixgbe_sfp_type_1g_sx_core1:
1016         case ixgbe_sfp_type_1g_lx_core0:
1017         case ixgbe_sfp_type_1g_lx_core1:
1018                 setup_linear = false;
1019                 break;
1020         default:
1021                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1022         }
1023
1024         ixgbe_init_mac_link_ops_X550em(hw);
1025         hw->phy.ops.reset = NULL;
1026
1027         /* The CS4227 slice address is the base address + the port-pair reg
1028          * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
1029          */
1030         reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12);
1031
1032         if (setup_linear)
1033                 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1034         else
1035                 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1036
1037         /* Configure CS4227 for connection type. */
1038         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1039                                            edc_mode);
1040
1041         if (ret_val != IXGBE_SUCCESS)
1042                 ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice,
1043                                                    edc_mode);
1044
1045         return ret_val;
1046 }
1047
1048 /**
1049  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1050  *  @hw: pointer to hardware structure
1051  */
1052 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1053 {
1054         struct ixgbe_mac_info *mac = &hw->mac;
1055
1056         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1057
1058          switch (hw->mac.ops.get_media_type(hw)) {
1059          case ixgbe_media_type_fiber:
1060                 /* CS4227 does not support autoneg, so disable the laser control
1061                  * functions for SFP+ fiber
1062                  */
1063                 mac->ops.disable_tx_laser = NULL;
1064                 mac->ops.enable_tx_laser = NULL;
1065                 mac->ops.flap_tx_laser = NULL;
1066                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1067                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1068                 mac->ops.set_rate_select_speed =
1069                                         ixgbe_set_soft_rate_select_speed;
1070                 break;
1071         case ixgbe_media_type_copper:
1072                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1073                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1074                 break;
1075         default:
1076                 break;
1077          }
1078 }
1079
1080 /**
1081  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1082  *  @hw: pointer to hardware structure
1083  *  @speed: pointer to link speed
1084  *  @autoneg: true when autoneg or autotry is enabled
1085  */
1086 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1087                                        ixgbe_link_speed *speed,
1088                                        bool *autoneg)
1089 {
1090         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1091
1092         /* SFP */
1093         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1094
1095                 /* CS4227 SFP must not enable auto-negotiation */
1096                 *autoneg = false;
1097
1098                 /* Check if 1G SFP module. */
1099                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1100                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1101                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1102                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1103                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1104                         return IXGBE_SUCCESS;
1105                 }
1106
1107                 /* Link capabilities are based on SFP */
1108                 if (hw->phy.multispeed_fiber)
1109                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1110                                  IXGBE_LINK_SPEED_1GB_FULL;
1111                 else
1112                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1113         } else {
1114                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1115                          IXGBE_LINK_SPEED_1GB_FULL;
1116                 *autoneg = true;
1117         }
1118
1119         return IXGBE_SUCCESS;
1120 }
1121
1122 /**
1123  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1124  * @hw: pointer to hardware structure
1125  * @lsc: pointer to boolean flag which indicates whether external Base T
1126  *       PHY interrupt is lsc
1127  *
1128  * Determime if external Base T PHY interrupt cause is high temperature
1129  * failure alarm or link status change.
1130  *
1131  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1132  * failure alarm, else return PHY access status.
1133  */
1134 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1135 {
1136         u32 status;
1137         u16 reg;
1138
1139         *lsc = false;
1140
1141         /* Vendor alarm triggered */
1142         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1143                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1144                                       &reg);
1145
1146         if (status != IXGBE_SUCCESS ||
1147             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1148                 return status;
1149
1150         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1151         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1152                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1153                                       &reg);
1154
1155         if (status != IXGBE_SUCCESS ||
1156             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1157             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1158                 return status;
1159
1160         /* High temperature failure alarm triggered */
1161         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1162                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1163                                       &reg);
1164
1165         if (status != IXGBE_SUCCESS)
1166                 return status;
1167
1168         /* If high temperature failure, then return over temp error and exit */
1169         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL)
1170                 return IXGBE_ERR_OVERTEMP;
1171
1172         /* Vendor alarm 2 triggered */
1173         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1174                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1175
1176         if (status != IXGBE_SUCCESS ||
1177             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1178                 return status;
1179
1180         /* link connect/disconnect event occurred */
1181         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1182                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1183
1184         if (status != IXGBE_SUCCESS)
1185                 return status;
1186
1187         /* Indicate LSC */
1188         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1189                 *lsc = true;
1190
1191         return IXGBE_SUCCESS;
1192 }
1193
1194 /**
1195  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1196  * @hw: pointer to hardware structure
1197  *
1198  * Enable link status change and temperature failure alarm for the external
1199  * Base T PHY
1200  *
1201  * Returns PHY access status
1202  */
1203 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1204 {
1205         u32 status;
1206         u16 reg;
1207         bool lsc;
1208
1209         /* Clear interrupt flags */
1210         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1211
1212         /* Enable link status change alarm */
1213         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1214                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1215
1216         if (status != IXGBE_SUCCESS)
1217                 return status;
1218
1219         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1220
1221         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1222                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1223
1224         if (status != IXGBE_SUCCESS)
1225                 return status;
1226
1227         /* Enables high temperature failure alarm */
1228         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1229                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1230                                       &reg);
1231
1232         if (status != IXGBE_SUCCESS)
1233                 return status;
1234
1235         reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1236
1237         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1238                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1239                                        reg);
1240
1241         if (status != IXGBE_SUCCESS)
1242                 return status;
1243
1244         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1245         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1246                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1247                                       &reg);
1248
1249         if (status != IXGBE_SUCCESS)
1250                 return status;
1251
1252         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1253                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1254
1255         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1256                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1257                                        reg);
1258
1259         if (status != IXGBE_SUCCESS)
1260                 return status;
1261
1262         /* Enable chip-wide vendor alarm */
1263         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1264                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1265                                       &reg);
1266
1267         if (status != IXGBE_SUCCESS)
1268                 return status;
1269
1270         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1271
1272         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1273                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1274                                        reg);
1275
1276         return status;
1277 }
1278
1279 /**
1280  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1281  *  @hw: pointer to hardware structure
1282  *
1283  *  Initialize any function pointers that were not able to be
1284  *  set during init_shared_code because the PHY/SFP type was
1285  *  not known.  Perform the SFP init if necessary.
1286  */
1287 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1288 {
1289         struct ixgbe_phy_info *phy = &hw->phy;
1290         s32 ret_val;
1291
1292         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1293
1294         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1295                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1296                 ixgbe_setup_mux_ctl(hw);
1297         }
1298
1299         /* Identify the PHY or SFP module */
1300         ret_val = phy->ops.identify(hw);
1301         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1302                 return ret_val;
1303
1304         /* Setup function pointers based on detected hardware */
1305         ixgbe_init_mac_link_ops_X550em(hw);
1306         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1307                 phy->ops.reset = NULL;
1308
1309         /* Set functions pointers based on phy type */
1310         switch (hw->phy.type) {
1311         case ixgbe_phy_x550em_kx4:
1312                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1313                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1314                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1315                 break;
1316         case ixgbe_phy_x550em_kr:
1317                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1318                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1319                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1320                 break;
1321         case ixgbe_phy_x550em_ext_t:
1322                 phy->ops.setup_internal_link =
1323                                          ixgbe_setup_internal_phy_t_x550em;
1324                 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1325                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1326                 break;
1327         default:
1328                 break;
1329         }
1330         return ret_val;
1331 }
1332
1333 /**
1334  *  ixgbe_reset_hw_X550em - Perform hardware reset
1335  *  @hw: pointer to hardware structure
1336  *
1337  *  Resets the hardware by resetting the transmit and receive units, masks
1338  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1339  *  reset.
1340  */
1341 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1342 {
1343         struct ixgbe_hic_hdr fw_cmd;
1344         ixgbe_link_speed link_speed;
1345         s32 status;
1346         u32 ctrl = 0;
1347         u32 i;
1348         bool link_up = false;
1349
1350         DEBUGFUNC("ixgbe_reset_hw_X550em");
1351
1352         fw_cmd.cmd = FW_PHY_MGMT_REQ_CMD;
1353         fw_cmd.buf_len = 0;
1354         fw_cmd.cmd_or_resp.cmd_resv = 0;
1355         fw_cmd.checksum = FW_DEFAULT_CHECKSUM;
1356         status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
1357                                               sizeof(fw_cmd),
1358                                               IXGBE_HI_PHY_MGMT_REQ_TIMEOUT,
1359                                               true);
1360         if (status)
1361                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1362                               "PHY mgmt command failed with %d\n", status);
1363         else if (fw_cmd.cmd_or_resp.ret_status != FW_CEM_RESP_STATUS_SUCCESS)
1364                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1365                               "PHY mgmt command returned %d\n",
1366                               fw_cmd.cmd_or_resp.ret_status);
1367
1368         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1369         status = hw->mac.ops.stop_adapter(hw);
1370         if (status != IXGBE_SUCCESS)
1371                 return status;
1372
1373         /* flush pending Tx transactions */
1374         ixgbe_clear_tx_pending(hw);
1375
1376         /* PHY ops must be identified and initialized prior to reset */
1377
1378         /* Identify PHY and related function pointers */
1379         status = hw->phy.ops.init(hw);
1380
1381         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1382                 return status;
1383
1384         /* start the external PHY */
1385         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1386                 status = ixgbe_init_ext_t_x550em(hw);
1387                 if (status)
1388                         return status;
1389         }
1390
1391         /* Setup SFP module if there is one present. */
1392         if (hw->phy.sfp_setup_needed) {
1393                 status = hw->mac.ops.setup_sfp(hw);
1394                 hw->phy.sfp_setup_needed = false;
1395         }
1396
1397         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1398                 return status;
1399
1400         /* Reset PHY */
1401         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1402                 hw->phy.ops.reset(hw);
1403
1404 mac_reset_top:
1405         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1406          * If link reset is used when link is up, it might reset the PHY when
1407          * mng is using it.  If link is down or the flag to force full link
1408          * reset is set, then perform link reset.
1409          */
1410         ctrl = IXGBE_CTRL_LNK_RST;
1411         if (!hw->force_full_reset) {
1412                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1413                 if (link_up)
1414                         ctrl = IXGBE_CTRL_RST;
1415         }
1416
1417         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1418         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1419         IXGBE_WRITE_FLUSH(hw);
1420
1421         /* Poll for reset bit to self-clear meaning reset is complete */
1422         for (i = 0; i < 10; i++) {
1423                 usec_delay(1);
1424                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1425                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1426                         break;
1427         }
1428
1429         if (ctrl & IXGBE_CTRL_RST_MASK) {
1430                 status = IXGBE_ERR_RESET_FAILED;
1431                 DEBUGOUT("Reset polling failed to complete.\n");
1432         }
1433
1434         msec_delay(50);
1435
1436         /* Double resets are required for recovery from certain error
1437          * conditions.  Between resets, it is necessary to stall to
1438          * allow time for any pending HW events to complete.
1439          */
1440         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1441                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1442                 goto mac_reset_top;
1443         }
1444
1445         /* Store the permanent mac address */
1446         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1447
1448         /* Store MAC address from RAR0, clear receive address registers, and
1449          * clear the multicast table.  Also reset num_rar_entries to 128,
1450          * since we modify this value when programming the SAN MAC address.
1451          */
1452         hw->mac.num_rar_entries = 128;
1453         hw->mac.ops.init_rx_addrs(hw);
1454
1455
1456         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1457                 ixgbe_setup_mux_ctl(hw);
1458
1459         return status;
1460 }
1461
1462 /**
1463  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1464  * @hw: pointer to hardware structure
1465  */
1466 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1467 {
1468         u32 status;
1469         u16 reg;
1470
1471         status = hw->phy.ops.read_reg(hw,
1472                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1473                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1474                                       &reg);
1475
1476         if (status != IXGBE_SUCCESS)
1477                 return status;
1478
1479         /* If PHY FW reset completed bit is set then this is the first
1480          * SW instance after a power on so the PHY FW must be un-stalled.
1481          */
1482         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1483                 status = hw->phy.ops.read_reg(hw,
1484                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1485                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1486                                         &reg);
1487
1488                 if (status != IXGBE_SUCCESS)
1489                         return status;
1490
1491                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1492
1493                 status = hw->phy.ops.write_reg(hw,
1494                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1495                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1496                                         reg);
1497
1498                 if (status != IXGBE_SUCCESS)
1499                         return status;
1500         }
1501
1502         /* Configure Link Status Alarm and Temperature Threshold interrupts */
1503         status = ixgbe_enable_lasi_ext_t_x550em(hw);
1504
1505         return status;
1506 }
1507
1508 /**
1509  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1510  *  @hw: pointer to hardware structure
1511  *
1512  *  Configures the integrated KR PHY.
1513  **/
1514 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1515 {
1516         s32 status;
1517         u32 reg_val;
1518
1519         status = ixgbe_read_iosf_sb_reg_x550(hw,
1520                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1521                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1522         if (status)
1523                 return status;
1524
1525         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1526         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1527                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1528         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1529                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1530
1531         /* Advertise 10G support. */
1532         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1533                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1534
1535         /* Advertise 1G support. */
1536         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1537                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1538
1539         /* Restart auto-negotiation. */
1540         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1541         status = ixgbe_write_iosf_sb_reg_x550(hw,
1542                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1543                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1544
1545         return status;
1546 }
1547
1548 /**
1549  *  ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1550  *  @hw: pointer to hardware structure
1551  *
1552  *  Configures the integrated KX4 PHY.
1553  **/
1554 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1555 {
1556         s32 status;
1557         u32 reg_val;
1558
1559         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1560                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, &reg_val);
1561         if (status)
1562                 return status;
1563
1564         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1565                         IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1566
1567         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1568
1569         /* Advertise 10G support. */
1570         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1571                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1572
1573         /* Advertise 1G support. */
1574         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1575                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1576
1577         /* Restart auto-negotiation. */
1578         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1579         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1580                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, reg_val);
1581
1582         return status;
1583 }
1584
1585 /**
1586  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1587  *  @hw: pointer to hardware structure
1588  *  @speed: the link speed to force
1589  *
1590  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1591  *  internal and external PHY at a specific speed, without autonegotiation.
1592  **/
1593 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1594 {
1595         s32 status;
1596         u32 reg_val;
1597
1598         /* Disable AN and force speed to 10G Serial. */
1599         status = ixgbe_read_iosf_sb_reg_x550(hw,
1600                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1601                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1602         if (status != IXGBE_SUCCESS)
1603                 return status;
1604
1605         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1606         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1607
1608         /* Select forced link speed for internal PHY. */
1609         switch (*speed) {
1610         case IXGBE_LINK_SPEED_10GB_FULL:
1611                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1612                 break;
1613         case IXGBE_LINK_SPEED_1GB_FULL:
1614                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1615                 break;
1616         default:
1617                 /* Other link speeds are not supported by internal KR PHY. */
1618                 return IXGBE_ERR_LINK_SETUP;
1619         }
1620
1621         status = ixgbe_write_iosf_sb_reg_x550(hw,
1622                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1623                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1624         if (status != IXGBE_SUCCESS)
1625                 return status;
1626
1627         /* Disable training protocol FSM. */
1628         status = ixgbe_read_iosf_sb_reg_x550(hw,
1629                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1630                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1631         if (status != IXGBE_SUCCESS)
1632                 return status;
1633         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1634         status = ixgbe_write_iosf_sb_reg_x550(hw,
1635                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1636                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1637         if (status != IXGBE_SUCCESS)
1638                 return status;
1639
1640         /* Disable Flex from training TXFFE. */
1641         status = ixgbe_read_iosf_sb_reg_x550(hw,
1642                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1643                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1644         if (status != IXGBE_SUCCESS)
1645                 return status;
1646         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1647         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1648         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1649         status = ixgbe_write_iosf_sb_reg_x550(hw,
1650                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1651                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1652         if (status != IXGBE_SUCCESS)
1653                 return status;
1654         status = ixgbe_read_iosf_sb_reg_x550(hw,
1655                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1656                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1657         if (status != IXGBE_SUCCESS)
1658                 return status;
1659         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1660         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1661         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1662         status = ixgbe_write_iosf_sb_reg_x550(hw,
1663                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1664                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1665         if (status != IXGBE_SUCCESS)
1666                 return status;
1667
1668         /* Enable override for coefficients. */
1669         status = ixgbe_read_iosf_sb_reg_x550(hw,
1670                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1671                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1672         if (status != IXGBE_SUCCESS)
1673                 return status;
1674         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1675         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1676         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1677         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1678         status = ixgbe_write_iosf_sb_reg_x550(hw,
1679                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1680                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1681         if (status != IXGBE_SUCCESS)
1682                 return status;
1683
1684         /* Toggle port SW reset by AN reset. */
1685         status = ixgbe_read_iosf_sb_reg_x550(hw,
1686                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1687                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1688         if (status != IXGBE_SUCCESS)
1689                 return status;
1690         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1691         status = ixgbe_write_iosf_sb_reg_x550(hw,
1692                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1693                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1694
1695         return status;
1696 }
1697
1698 /**
1699  *  ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1700  *  @hw: pointer to hardware structure
1701  *
1702  *  Configures the integrated KR PHY for SFP support.
1703  **/
1704 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1705                                     ixgbe_link_speed speed,
1706                                     bool autoneg_wait_to_complete)
1707 {
1708         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1709
1710         return ixgbe_setup_ixfi_x550em(hw, &speed);
1711 }
1712
1713 /**
1714  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1715  * @hw: point to hardware structure
1716  *
1717  * Configures the link between the integrated KR PHY and the external X557 PHY
1718  * The driver will call this function when it gets a link status change
1719  * interrupt from the X557 PHY. This function configures the link speed
1720  * between the PHYs to match the link speed of the BASE-T link.
1721  *
1722  * A return of a non-zero value indicates an error, and the base driver should
1723  * not report link up.
1724  */
1725 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1726 {
1727         u32 status;
1728         u16 autoneg_status, speed;
1729         ixgbe_link_speed force_speed;
1730
1731         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1732                 return IXGBE_ERR_CONFIG;
1733
1734         /* read this twice back to back to indicate current status */
1735         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1736                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1737                                       &autoneg_status);
1738         if (status != IXGBE_SUCCESS)
1739                 return status;
1740
1741         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1742                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1743                                       &autoneg_status);
1744         if (status != IXGBE_SUCCESS)
1745                 return status;
1746
1747         /* If link is not up, then there is no setup necessary so return  */
1748         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1749                 return IXGBE_SUCCESS;
1750
1751         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1752                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1753                                       &speed);
1754
1755         /* clear everything but the speed and duplex bits */
1756         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1757
1758         switch (speed) {
1759         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1760                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1761                 break;
1762         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1763                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1764                 break;
1765         default:
1766                 /* Internal PHY does not support anything else */
1767                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1768         }
1769
1770         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1771 }
1772
1773 /**
1774  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1775  *  @hw: pointer to hardware structure
1776  *
1777  *  Configures the integrated KR PHY to use internal loopback mode.
1778  **/
1779 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1780 {
1781         s32 status;
1782         u32 reg_val;
1783
1784         /* Disable AN and force speed to 10G Serial. */
1785         status = ixgbe_read_iosf_sb_reg_x550(hw,
1786                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1787                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1788         if (status != IXGBE_SUCCESS)
1789                 return status;
1790         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1791         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1792         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1793         status = ixgbe_write_iosf_sb_reg_x550(hw,
1794                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1795                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1796         if (status != IXGBE_SUCCESS)
1797                 return status;
1798
1799         /* Set near-end loopback clocks. */
1800         status = ixgbe_read_iosf_sb_reg_x550(hw,
1801                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1802                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1803         if (status != IXGBE_SUCCESS)
1804                 return status;
1805         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1806         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1807         status = ixgbe_write_iosf_sb_reg_x550(hw,
1808                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1809                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1810         if (status != IXGBE_SUCCESS)
1811                 return status;
1812
1813         /* Set loopback enable. */
1814         status = ixgbe_read_iosf_sb_reg_x550(hw,
1815                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1816                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1817         if (status != IXGBE_SUCCESS)
1818                 return status;
1819         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1820         status = ixgbe_write_iosf_sb_reg_x550(hw,
1821                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1822                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1823         if (status != IXGBE_SUCCESS)
1824                 return status;
1825
1826         /* Training bypass. */
1827         status = ixgbe_read_iosf_sb_reg_x550(hw,
1828                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1829                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1830         if (status != IXGBE_SUCCESS)
1831                 return status;
1832         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1833         status = ixgbe_write_iosf_sb_reg_x550(hw,
1834                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1835                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1836
1837         return status;
1838 }
1839
1840 /**
1841  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1842  *  assuming that the semaphore is already obtained.
1843  *  @hw: pointer to hardware structure
1844  *  @offset: offset of  word in the EEPROM to read
1845  *  @data: word read from the EEPROM
1846  *
1847  *  Reads a 16 bit word from the EEPROM using the hostif.
1848  **/
1849 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1850                                    u16 *data)
1851 {
1852         s32 status;
1853         struct ixgbe_hic_read_shadow_ram buffer;
1854
1855         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1856         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1857         buffer.hdr.req.buf_lenh = 0;
1858         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1859         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1860
1861         /* convert offset from words to bytes */
1862         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1863         /* one word */
1864         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1865
1866         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1867                                               sizeof(buffer),
1868                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1869
1870         if (status)
1871                 return status;
1872
1873         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1874                                           FW_NVM_DATA_OFFSET);
1875
1876         return 0;
1877 }
1878
1879 /**
1880  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1881  *  @hw: pointer to hardware structure
1882  *  @offset: offset of  word in the EEPROM to read
1883  *  @data: word read from the EEPROM
1884  *
1885  *  Reads a 16 bit word from the EEPROM using the hostif.
1886  **/
1887 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1888                               u16 *data)
1889 {
1890         s32 status = IXGBE_SUCCESS;
1891
1892         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1893
1894         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1895             IXGBE_SUCCESS) {
1896                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1897                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1898         } else {
1899                 status = IXGBE_ERR_SWFW_SYNC;
1900         }
1901
1902         return status;
1903 }
1904
1905 /**
1906  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1907  *  @hw: pointer to hardware structure
1908  *  @offset: offset of  word in the EEPROM to read
1909  *  @words: number of words
1910  *  @data: word(s) read from the EEPROM
1911  *
1912  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
1913  **/
1914 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1915                                      u16 offset, u16 words, u16 *data)
1916 {
1917         struct ixgbe_hic_read_shadow_ram buffer;
1918         u32 current_word = 0;
1919         u16 words_to_read;
1920         s32 status;
1921         u32 i;
1922
1923         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1924
1925         /* Take semaphore for the entire operation. */
1926         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1927         if (status) {
1928                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1929                 return status;
1930         }
1931         while (words) {
1932                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1933                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1934                 else
1935                         words_to_read = words;
1936
1937                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1938                 buffer.hdr.req.buf_lenh = 0;
1939                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1940                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1941
1942                 /* convert offset from words to bytes */
1943                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1944                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1945
1946                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1947                                                       sizeof(buffer),
1948                                                       IXGBE_HI_COMMAND_TIMEOUT,
1949                                                       false);
1950
1951                 if (status) {
1952                         DEBUGOUT("Host interface command failed\n");
1953                         goto out;
1954                 }
1955
1956                 for (i = 0; i < words_to_read; i++) {
1957                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1958                                   2 * i;
1959                         u32 value = IXGBE_READ_REG(hw, reg);
1960
1961                         data[current_word] = (u16)(value & 0xffff);
1962                         current_word++;
1963                         i++;
1964                         if (i < words_to_read) {
1965                                 value >>= 16;
1966                                 data[current_word] = (u16)(value & 0xffff);
1967                                 current_word++;
1968                         }
1969                 }
1970                 words -= words_to_read;
1971         }
1972
1973 out:
1974         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1975         return status;
1976 }
1977
1978 /**
1979  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1980  *  @hw: pointer to hardware structure
1981  *  @offset: offset of  word in the EEPROM to write
1982  *  @data: word write to the EEPROM
1983  *
1984  *  Write a 16 bit word to the EEPROM using the hostif.
1985  **/
1986 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1987                                     u16 data)
1988 {
1989         s32 status;
1990         struct ixgbe_hic_write_shadow_ram buffer;
1991
1992         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1993
1994         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1995         buffer.hdr.req.buf_lenh = 0;
1996         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
1997         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1998
1999          /* one word */
2000         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2001         buffer.data = data;
2002         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2003
2004         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2005                                               sizeof(buffer),
2006                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2007
2008         return status;
2009 }
2010
2011 /**
2012  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2013  *  @hw: pointer to hardware structure
2014  *  @offset: offset of  word in the EEPROM to write
2015  *  @data: word write to the EEPROM
2016  *
2017  *  Write a 16 bit word to the EEPROM using the hostif.
2018  **/
2019 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2020                                u16 data)
2021 {
2022         s32 status = IXGBE_SUCCESS;
2023
2024         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2025
2026         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2027             IXGBE_SUCCESS) {
2028                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2029                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2030         } else {
2031                 DEBUGOUT("write ee hostif failed to get semaphore");
2032                 status = IXGBE_ERR_SWFW_SYNC;
2033         }
2034
2035         return status;
2036 }
2037
2038 /**
2039  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2040  *  @hw: pointer to hardware structure
2041  *  @offset: offset of  word in the EEPROM to write
2042  *  @words: number of words
2043  *  @data: word(s) write to the EEPROM
2044  *
2045  *  Write a 16 bit word(s) to the EEPROM using the hostif.
2046  **/
2047 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2048                                       u16 offset, u16 words, u16 *data)
2049 {
2050         s32 status = IXGBE_SUCCESS;
2051         u32 i = 0;
2052
2053         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2054
2055         /* Take semaphore for the entire operation. */
2056         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2057         if (status != IXGBE_SUCCESS) {
2058                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2059                 goto out;
2060         }
2061
2062         for (i = 0; i < words; i++) {
2063                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2064                                                          data[i]);
2065
2066                 if (status != IXGBE_SUCCESS) {
2067                         DEBUGOUT("Eeprom buffered write failed\n");
2068                         break;
2069                 }
2070         }
2071
2072         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2073 out:
2074
2075         return status;
2076 }
2077
2078 /**
2079  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2080  * @hw: pointer to hardware structure
2081  * @ptr: pointer offset in eeprom
2082  * @size: size of section pointed by ptr, if 0 first word will be used as size
2083  * @csum: address of checksum to update
2084  *
2085  * Returns error status for any failure
2086  */
2087 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2088                                    u16 size, u16 *csum, u16 *buffer,
2089                                    u32 buffer_size)
2090 {
2091         u16 buf[256];
2092         s32 status;
2093         u16 length, bufsz, i, start;
2094         u16 *local_buffer;
2095
2096         bufsz = sizeof(buf) / sizeof(buf[0]);
2097
2098         /* Read a chunk at the pointer location */
2099         if (!buffer) {
2100                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2101                 if (status) {
2102                         DEBUGOUT("Failed to read EEPROM image\n");
2103                         return status;
2104                 }
2105                 local_buffer = buf;
2106         } else {
2107                 if (buffer_size < ptr)
2108                         return  IXGBE_ERR_PARAM;
2109                 local_buffer = &buffer[ptr];
2110         }
2111
2112         if (size) {
2113                 start = 0;
2114                 length = size;
2115         } else {
2116                 start = 1;
2117                 length = local_buffer[0];
2118
2119                 /* Skip pointer section if length is invalid. */
2120                 if (length == 0xFFFF || length == 0 ||
2121                     (ptr + length) >= hw->eeprom.word_size)
2122                         return IXGBE_SUCCESS;
2123         }
2124
2125         if (buffer && ((u32)start + (u32)length > buffer_size))
2126                 return IXGBE_ERR_PARAM;
2127
2128         for (i = start; length; i++, length--) {
2129                 if (i == bufsz && !buffer) {
2130                         ptr += bufsz;
2131                         i = 0;
2132                         if (length < bufsz)
2133                                 bufsz = length;
2134
2135                         /* Read a chunk at the pointer location */
2136                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2137                                                                   bufsz, buf);
2138                         if (status) {
2139                                 DEBUGOUT("Failed to read EEPROM image\n");
2140                                 return status;
2141                         }
2142                 }
2143                 *csum += local_buffer[i];
2144         }
2145         return IXGBE_SUCCESS;
2146 }
2147
2148 /**
2149  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2150  *  @hw: pointer to hardware structure
2151  *  @buffer: pointer to buffer containing calculated checksum
2152  *  @buffer_size: size of buffer
2153  *
2154  *  Returns a negative error code on error, or the 16-bit checksum
2155  **/
2156 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2157 {
2158         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2159         u16 *local_buffer;
2160         s32 status;
2161         u16 checksum = 0;
2162         u16 pointer, i, size;
2163
2164         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2165
2166         hw->eeprom.ops.init_params(hw);
2167
2168         if (!buffer) {
2169                 /* Read pointer area */
2170                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2171                                                      IXGBE_EEPROM_LAST_WORD + 1,
2172                                                      eeprom_ptrs);
2173                 if (status) {
2174                         DEBUGOUT("Failed to read EEPROM image\n");
2175                         return status;
2176                 }
2177                 local_buffer = eeprom_ptrs;
2178         } else {
2179                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2180                         return IXGBE_ERR_PARAM;
2181                 local_buffer = buffer;
2182         }
2183
2184         /*
2185          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2186          * checksum word itself
2187          */
2188         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2189                 if (i != IXGBE_EEPROM_CHECKSUM)
2190                         checksum += local_buffer[i];
2191
2192         /*
2193          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2194          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2195          */
2196         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2197                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2198                         continue;
2199
2200                 pointer = local_buffer[i];
2201
2202                 /* Skip pointer section if the pointer is invalid. */
2203                 if (pointer == 0xFFFF || pointer == 0 ||
2204                     pointer >= hw->eeprom.word_size)
2205                         continue;
2206
2207                 switch (i) {
2208                 case IXGBE_PCIE_GENERAL_PTR:
2209                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2210                         break;
2211                 case IXGBE_PCIE_CONFIG0_PTR:
2212                 case IXGBE_PCIE_CONFIG1_PTR:
2213                         size = IXGBE_PCIE_CONFIG_SIZE;
2214                         break;
2215                 default:
2216                         size = 0;
2217                         break;
2218                 }
2219
2220                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2221                                                 buffer, buffer_size);
2222                 if (status)
2223                         return status;
2224         }
2225
2226         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2227
2228         return (s32)checksum;
2229 }
2230
2231 /**
2232  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2233  *  @hw: pointer to hardware structure
2234  *
2235  *  Returns a negative error code on error, or the 16-bit checksum
2236  **/
2237 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2238 {
2239         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2240 }
2241
2242 /**
2243  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2244  *  @hw: pointer to hardware structure
2245  *  @checksum_val: calculated checksum
2246  *
2247  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2248  *  caller does not need checksum_val, the value can be NULL.
2249  **/
2250 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2251 {
2252         s32 status;
2253         u16 checksum;
2254         u16 read_checksum = 0;
2255
2256         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2257
2258         /* Read the first word from the EEPROM. If this times out or fails, do
2259          * not continue or we could be in for a very long wait while every
2260          * EEPROM read fails
2261          */
2262         status = hw->eeprom.ops.read(hw, 0, &checksum);
2263         if (status) {
2264                 DEBUGOUT("EEPROM read failed\n");
2265                 return status;
2266         }
2267
2268         status = hw->eeprom.ops.calc_checksum(hw);
2269         if (status < 0)
2270                 return status;
2271
2272         checksum = (u16)(status & 0xffff);
2273
2274         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2275                                            &read_checksum);
2276         if (status)
2277                 return status;
2278
2279         /* Verify read checksum from EEPROM is the same as
2280          * calculated checksum
2281          */
2282         if (read_checksum != checksum) {
2283                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2284                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2285                              "Invalid EEPROM checksum");
2286         }
2287
2288         /* If the user cares, return the calculated checksum */
2289         if (checksum_val)
2290                 *checksum_val = checksum;
2291
2292         return status;
2293 }
2294
2295 /**
2296  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2297  * @hw: pointer to hardware structure
2298  *
2299  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2300  * checksum and updates the EEPROM and instructs the hardware to update
2301  * the flash.
2302  **/
2303 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2304 {
2305         s32 status;
2306         u16 checksum = 0;
2307
2308         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2309
2310         /* Read the first word from the EEPROM. If this times out or fails, do
2311          * not continue or we could be in for a very long wait while every
2312          * EEPROM read fails
2313          */
2314         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2315         if (status) {
2316                 DEBUGOUT("EEPROM read failed\n");
2317                 return status;
2318         }
2319
2320         status = ixgbe_calc_eeprom_checksum_X550(hw);
2321         if (status < 0)
2322                 return status;
2323
2324         checksum = (u16)(status & 0xffff);
2325
2326         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2327                                             checksum);
2328         if (status)
2329                 return status;
2330
2331         status = ixgbe_update_flash_X550(hw);
2332
2333         return status;
2334 }
2335
2336 /**
2337  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2338  *  @hw: pointer to hardware structure
2339  *
2340  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2341  **/
2342 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2343 {
2344         s32 status = IXGBE_SUCCESS;
2345         union ixgbe_hic_hdr2 buffer;
2346
2347         DEBUGFUNC("ixgbe_update_flash_X550");
2348
2349         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2350         buffer.req.buf_lenh = 0;
2351         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2352         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2353
2354         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2355                                               sizeof(buffer),
2356                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2357
2358         return status;
2359 }
2360
2361 /**
2362  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2363  *  @hw: pointer to hardware structure
2364  *
2365  *  Determines physical layer capabilities of the current configuration.
2366  **/
2367 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2368 {
2369         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2370         u16 ext_ability = 0;
2371
2372         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2373
2374         hw->phy.ops.identify(hw);
2375
2376         switch (hw->phy.type) {
2377         case ixgbe_phy_x550em_kr:
2378                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2379                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2380                 break;
2381         case ixgbe_phy_x550em_kx4:
2382                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2383                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2384                 break;
2385         case ixgbe_phy_x550em_ext_t:
2386                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2387                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2388                                      &ext_ability);
2389                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2390                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2391                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2392                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2393                 break;
2394         default:
2395                 break;
2396         }
2397
2398         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2399                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2400
2401         return physical_layer;
2402 }
2403
2404 /**
2405  * ixgbe_get_bus_info_x550em - Set PCI bus info
2406  * @hw: pointer to hardware structure
2407  *
2408  * Sets bus link width and speed to unknown because X550em is
2409  * not a PCI device.
2410  **/
2411 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2412 {
2413
2414         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2415
2416         hw->bus.width = ixgbe_bus_width_unknown;
2417         hw->bus.speed = ixgbe_bus_speed_unknown;
2418
2419         return IXGBE_SUCCESS;
2420 }
2421
2422 /**
2423  * ixgbe_disable_rx_x550 - Disable RX unit
2424  *
2425  * Enables the Rx DMA unit for x550
2426  **/
2427 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2428 {
2429         u32 rxctrl, pfdtxgswc;
2430         s32 status;
2431         struct ixgbe_hic_disable_rxen fw_cmd;
2432
2433         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2434
2435         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2436         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2437                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2438                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2439                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2440                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2441                         hw->mac.set_lben = true;
2442                 } else {
2443                         hw->mac.set_lben = false;
2444                 }
2445
2446                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2447                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2448                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2449                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2450
2451                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2452                                         sizeof(struct ixgbe_hic_disable_rxen),
2453                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2454
2455                 /* If we fail - disable RX using register write */
2456                 if (status) {
2457                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2458                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2459                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2460                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2461                         }
2462                 }
2463         }
2464 }
2465
2466 /**
2467  * ixgbe_enter_lplu_x550em - Transition to low power states
2468  *  @hw: pointer to hardware structure
2469  *
2470  * Configures Low Power Link Up on transition to low power states
2471  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2472  * X557 PHY immediately prior to entering LPLU.
2473  **/
2474 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2475 {
2476         u16 autoneg_status, an_10g_cntl_reg, autoneg_reg, speed;
2477         s32 status;
2478         ixgbe_link_speed lcd_speed;
2479
2480         /* If blocked by MNG FW, then don't restart AN */
2481         if (ixgbe_check_reset_blocked(hw))
2482                 return IXGBE_SUCCESS;
2483
2484         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2485                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2486                                       &autoneg_status);
2487
2488         if (status != IXGBE_SUCCESS)
2489                 return status;
2490
2491         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2492
2493         if (status != IXGBE_SUCCESS)
2494                 return status;
2495
2496         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2497          * disabled, then force link down by entering low power mode.
2498          */
2499         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS) ||
2500             !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2501             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2502                 return ixgbe_set_copper_phy_power(hw, FALSE);
2503
2504         /* Determine LCD */
2505         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2506
2507         if (status != IXGBE_SUCCESS)
2508                 return status;
2509
2510         /* If no valid LCD link speed, then force link down and exit. */
2511         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2512                 return ixgbe_set_copper_phy_power(hw, FALSE);
2513
2514         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2515                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2516                                       &speed);
2517
2518         if (status != IXGBE_SUCCESS)
2519                 return status;
2520
2521         /* clear everything but the speed bits */
2522         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2523
2524         /* If current speed is already LCD, then exit. */
2525         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2526              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2527             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2528              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2529                 return status;
2530
2531         /* Clear AN completed indication */
2532         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2533                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2534                                       &autoneg_status);
2535
2536         if (status != IXGBE_SUCCESS)
2537                 return status;
2538
2539         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2540                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2541                              &an_10g_cntl_reg);
2542
2543         if (status != IXGBE_SUCCESS)
2544                 return status;
2545
2546         status = hw->phy.ops.read_reg(hw,
2547                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2548                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2549                              &autoneg_reg);
2550
2551         if (status != IXGBE_SUCCESS)
2552                 return status;
2553
2554         /* Set AN advertizement to only include LCD  */
2555         if (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL) {
2556                 an_10g_cntl_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
2557                 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
2558         }
2559
2560         if (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL) {
2561                 an_10g_cntl_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
2562                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
2563         }
2564
2565         status = hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2566                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2567                               an_10g_cntl_reg);
2568
2569         if (status != IXGBE_SUCCESS)
2570                 return status;
2571
2572         status = hw->phy.ops.write_reg(hw,
2573                               IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2574                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2575                               autoneg_reg);
2576
2577         if (status != IXGBE_SUCCESS)
2578                 return status;
2579
2580         /* Restart PHY auto-negotiation. */
2581         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
2582                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
2583
2584         if (status != IXGBE_SUCCESS)
2585                 return status;
2586
2587         autoneg_reg |= IXGBE_MII_RESTART;
2588
2589         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
2590                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
2591
2592         if (status != IXGBE_SUCCESS)
2593                 return status;
2594
2595         status = ixgbe_setup_ixfi_x550em(hw, &lcd_speed);
2596
2597         return status;
2598 }
2599
2600 /**
2601  * ixgbe_get_lcd_x550em - Determine lowest common denominator
2602  *  @hw: pointer to hardware structure
2603  *  @lcd_speed: pointer to lowest common link speed
2604  *
2605  * Determine lowest common link speed with link partner.
2606  **/
2607 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2608 {
2609         u16 an_lp_status;
2610         s32 status;
2611         u16 word = hw->eeprom.ctrl_word_3;
2612
2613         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2614
2615         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2616                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2617                                       &an_lp_status);
2618
2619         if (status != IXGBE_SUCCESS)
2620                 return status;
2621
2622         /* If link partner advertised 1G, return 1G */
2623         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2624                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2625                 return status;
2626         }
2627
2628         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2629         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2630             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2631                 return status;
2632
2633         /* Link partner not capable of lower speeds, return 10G */
2634         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2635         return status;
2636 }
2637
2638 /**
2639  *  ixgbe_setup_fc_X550em - Set up flow control
2640  *  @hw: pointer to hardware structure
2641  *
2642  *  Called at init time to set up flow control.
2643  **/
2644 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2645 {
2646         s32 ret_val = IXGBE_SUCCESS;
2647         u32 pause, asm_dir, reg_val;
2648
2649         DEBUGFUNC("ixgbe_setup_fc_X550em");
2650
2651         /* Validate the requested mode */
2652         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2653                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2654                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2655                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2656                 goto out;
2657         }
2658
2659         /* 10gig parts do not have a word in the EEPROM to determine the
2660          * default flow control setting, so we explicitly set it to full.
2661          */
2662         if (hw->fc.requested_mode == ixgbe_fc_default)
2663                 hw->fc.requested_mode = ixgbe_fc_full;
2664
2665         /* Determine PAUSE and ASM_DIR bits. */
2666         switch (hw->fc.requested_mode) {
2667         case ixgbe_fc_none:
2668                 pause = 0;
2669                 asm_dir = 0;
2670                 break;
2671         case ixgbe_fc_tx_pause:
2672                 pause = 0;
2673                 asm_dir = 1;
2674                 break;
2675         case ixgbe_fc_rx_pause:
2676                 /* Rx Flow control is enabled and Tx Flow control is
2677                  * disabled by software override. Since there really
2678                  * isn't a way to advertise that we are capable of RX
2679                  * Pause ONLY, we will advertise that we support both
2680                  * symmetric and asymmetric Rx PAUSE, as such we fall
2681                  * through to the fc_full statement.  Later, we will
2682                  * disable the adapter's ability to send PAUSE frames.
2683                  */
2684         case ixgbe_fc_full:
2685                 pause = 1;
2686                 asm_dir = 1;
2687                 break;
2688         default:
2689                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2690                         "Flow control param set incorrectly\n");
2691                 ret_val = IXGBE_ERR_CONFIG;
2692                 goto out;
2693         }
2694
2695         if (hw->phy.media_type == ixgbe_media_type_backplane) {
2696                 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2697                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2698                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2699                 if (ret_val != IXGBE_SUCCESS)
2700                         goto out;
2701                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2702                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2703                 if (pause)
2704                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2705                 if (asm_dir)
2706                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2707                 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2708                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2709                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2710
2711                 /* Not all devices fully support AN. */
2712                 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR)
2713                         hw->fc.disable_fc_autoneg = true;
2714         }
2715
2716 out:
2717         return ret_val;
2718 }
2719
2720 /**
2721  * ixgbe_set_mux - Set mux for port 1 access with CS4227
2722  * @hw: pointer to hardware structure
2723  * @state: set mux if 1, clear if 0
2724  */
2725 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2726 {
2727         u32 esdp;
2728
2729         if (!hw->bus.lan_id)
2730                 return;
2731         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2732         if (state)
2733                 esdp |= IXGBE_ESDP_SDP1;
2734         else
2735                 esdp &= ~IXGBE_ESDP_SDP1;
2736         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2737         IXGBE_WRITE_FLUSH(hw);
2738 }
2739
2740 /**
2741  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2742  *  @hw: pointer to hardware structure
2743  *  @mask: Mask to specify which semaphore to acquire
2744  *
2745  *  Acquires the SWFW semaphore and sets the I2C MUX
2746  **/
2747 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2748 {
2749         s32 status;
2750
2751         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2752
2753         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2754         if (status)
2755                 return status;
2756
2757         if (mask & IXGBE_GSSR_I2C_MASK)
2758                 ixgbe_set_mux(hw, 1);
2759
2760         return IXGBE_SUCCESS;
2761 }
2762
2763 /**
2764  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2765  *  @hw: pointer to hardware structure
2766  *  @mask: Mask to specify which semaphore to release
2767  *
2768  *  Releases the SWFW semaphore and sets the I2C MUX
2769  **/
2770 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2771 {
2772         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
2773
2774         if (mask & IXGBE_GSSR_I2C_MASK)
2775                 ixgbe_set_mux(hw, 0);
2776
2777         ixgbe_release_swfw_sync_X540(hw, mask);
2778 }
2779
2780 /**
2781  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2782  * @hw: pointer to hardware structure
2783  *
2784  * Handle external Base T PHY interrupt. If high temperature
2785  * failure alarm then return error, else if link status change
2786  * then setup internal/external PHY link
2787  *
2788  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2789  * failure alarm, else return PHY access status.
2790  */
2791 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2792 {
2793         bool lsc;
2794         u32 status;
2795
2796         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2797
2798         if (status != IXGBE_SUCCESS)
2799                 return status;
2800
2801         if (lsc)
2802                 return ixgbe_setup_internal_phy_t_x550em(hw);
2803
2804         return IXGBE_SUCCESS;
2805 }
2806
2807 /**
2808  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
2809  * @hw: pointer to hardware structure
2810  * @speed: new link speed
2811  * @autoneg_wait_to_complete: true when waiting for completion is needed
2812  *
2813  * Setup internal/external PHY link speed based on link speed, then set
2814  * external PHY auto advertised link speed.
2815  *
2816  * Returns error status for any failure
2817  **/
2818 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
2819                                   ixgbe_link_speed speed,
2820                                   bool autoneg_wait_to_complete)
2821 {
2822         s32 status;
2823         ixgbe_link_speed force_speed;
2824
2825         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
2826
2827         /* Setup internal/external PHY link speed to iXFI (10G), unless
2828          * only 1G is auto advertised then setup KX link.
2829          */
2830         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2831                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2832         else
2833                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2834
2835         status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
2836
2837         if (status != IXGBE_SUCCESS)
2838                 return status;
2839
2840         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
2841 }
2842
2843 /**
2844  * ixgbe_check_link_t_X550em - Determine link and speed status
2845  * @hw: pointer to hardware structure
2846  * @speed: pointer to link speed
2847  * @link_up: true when link is up
2848  * @link_up_wait_to_complete: bool used to wait for link up or not
2849  *
2850  * Check that both the MAC and X557 external PHY have link.
2851  **/
2852 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
2853                               bool *link_up, bool link_up_wait_to_complete)
2854 {
2855         u32 status;
2856         u16 autoneg_status;
2857
2858         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2859                 return IXGBE_ERR_CONFIG;
2860
2861         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
2862                                               link_up_wait_to_complete);
2863
2864         /* If check link fails or MAC link is not up, then return */
2865         if (status != IXGBE_SUCCESS || !(*link_up))
2866                 return status;
2867
2868         /* MAC link is up, so check external PHY link.
2869          * Read this twice back to back to indicate current status.
2870          */
2871         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2872                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2873                                       &autoneg_status);
2874
2875         if (status != IXGBE_SUCCESS)
2876                 return status;
2877
2878         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2879                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2880                                       &autoneg_status);
2881
2882         if (status != IXGBE_SUCCESS)
2883                 return status;
2884
2885         /* If external PHY link is not up, then indicate link not up */
2886         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
2887                 *link_up = false;
2888
2889         return IXGBE_SUCCESS;
2890 }