drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44
  45 /**
  46  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  47  *  @hw: pointer to hardware structure
  48  *
  49  *  Initialize the function pointers and assign the MAC type for X550.
  50  *  Does not touch the hardware.
  51  **/
  52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  53 {
  54         struct ixgbe_mac_info *mac = &hw->mac;
  55         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  56         s32 ret_val;
  57
  58         DEBUGFUNC("ixgbe_init_ops_X550");
  59
  60         ret_val = ixgbe_init_ops_X540(hw);
  61         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  62         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  63         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  64         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  65         mac->ops.set_source_address_pruning =
  66                         ixgbe_set_source_address_pruning_X550;
  67         mac->ops.set_ethertype_anti_spoofing =
  68                         ixgbe_set_ethertype_anti_spoofing_X550;
  69
  70         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  71         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  72         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  73         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  74         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  75         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  76         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  77         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  78         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  79
  80         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  81         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  82         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  83         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  84         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  85         switch (hw->device_id) {
  86         case IXGBE_DEV_ID_X550EM_X_10G_T:
  87         case IXGBE_DEV_ID_X550EM_A_10G_T:
  88                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  89                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  90                 break;
  91         default:
  92                 break;
  93         }
  94         return ret_val;
  95 }
  96
  97 /**
  98  * ixgbe_read_cs4227 - Read CS4227 register
  99  * @hw: pointer to hardware structure
 100  * @reg: register number to write
 101  * @value: pointer to receive value read
 102  *
 103  * Returns status code
 104  **/
 105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 106 {
 107         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
 108 }
 109
 110 /**
 111  * ixgbe_write_cs4227 - Write CS4227 register
 112  * @hw: pointer to hardware structure
 113  * @reg: register number to write
 114  * @value: value to write to register
 115  *
 116  * Returns status code
 117  **/
 118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 119 {
 120         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 121 }
 122
 123 /**
 124  * ixgbe_read_pe - Read register from port expander
 125  * @hw: pointer to hardware structure
 126  * @reg: register number to read
 127  * @value: pointer to receive read value
 128  *
 129  * Returns status code
 130  **/
 131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 132 {
 133         s32 status;
 134
 135         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 136         if (status != IXGBE_SUCCESS)
 137                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 138                               "port expander access failed with %d\n", status);
 139         return status;
 140 }
 141
 142 /**
 143  * ixgbe_write_pe - Write register to port expander
 144  * @hw: pointer to hardware structure
 145  * @reg: register number to write
 146  * @value: value to write
 147  *
 148  * Returns status code
 149  **/
 150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 151 {
 152         s32 status;
 153
 154         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 155         if (status != IXGBE_SUCCESS)
 156                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 157                               "port expander access failed with %d\n", status);
 158         return status;
 159 }
 160
 161 /**
 162  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 163  * @hw: pointer to hardware structure
 164  *
 165  * This function assumes that the caller has acquired the proper semaphore.
 166  * Returns error code
 167  **/
 168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 169 {
 170         s32 status;
 171         u32 retry;
 172         u16 value;
 173         u8 reg;
 174
 175         /* Trigger hard reset. */
 176         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 177         if (status != IXGBE_SUCCESS)
 178                 return status;
 179         reg |= IXGBE_PE_BIT1;
 180         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 181         if (status != IXGBE_SUCCESS)
 182                 return status;
 183
 184         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 185         if (status != IXGBE_SUCCESS)
 186                 return status;
 187         reg &= ~IXGBE_PE_BIT1;
 188         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 189         if (status != IXGBE_SUCCESS)
 190                 return status;
 191
 192         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 193         if (status != IXGBE_SUCCESS)
 194                 return status;
 195         reg &= ~IXGBE_PE_BIT1;
 196         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199
 200         usec_delay(IXGBE_CS4227_RESET_HOLD);
 201
 202         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 203         if (status != IXGBE_SUCCESS)
 204                 return status;
 205         reg |= IXGBE_PE_BIT1;
 206         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 207         if (status != IXGBE_SUCCESS)
 208                 return status;
 209
 210         /* Wait for the reset to complete. */
 211         msec_delay(IXGBE_CS4227_RESET_DELAY);
 212         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 213                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 214                                            &value);
 215                 if (status == IXGBE_SUCCESS &&
 216                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 217                         break;
 218                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 219         }
 220         if (retry == IXGBE_CS4227_RETRIES) {
 221                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 222                         "CS4227 reset did not complete.");
 223                 return IXGBE_ERR_PHY;
 224         }
 225
 226         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 227         if (status != IXGBE_SUCCESS ||
 228             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 229                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 230                         "CS4227 EEPROM did not load successfully.");
 231                 return IXGBE_ERR_PHY;
 232         }
 233
 234         return IXGBE_SUCCESS;
 235 }
 236
 237 /**
 238  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 239  * @hw: pointer to hardware structure
 240  **/
 241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 242 {
 243         s32 status = IXGBE_SUCCESS;
 244         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 245         u16 value = 0;
 246         u8 retry;
 247
 248         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 249                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 250                 if (status != IXGBE_SUCCESS) {
 251                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 252                                 "semaphore failed with %d", status);
 253                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 254                         continue;
 255                 }
 256
 257                 /* Get status of reset flow. */
 258                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 259
 260                 if (status == IXGBE_SUCCESS &&
 261                     value == IXGBE_CS4227_RESET_COMPLETE)
 262                         goto out;
 263
 264                 if (status != IXGBE_SUCCESS ||
 265                     value != IXGBE_CS4227_RESET_PENDING)
 266                         break;
 267
 268                 /* Reset is pending. Wait and check again. */
 269                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 270                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 271         }
 272
 273         /* If still pending, assume other instance failed. */
 274         if (retry == IXGBE_CS4227_RETRIES) {
 275                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 276                 if (status != IXGBE_SUCCESS) {
 277                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 278                                       "semaphore failed with %d", status);
 279                         return;
 280                 }
 281         }
 282
 283         /* Reset the CS4227. */
 284         status = ixgbe_reset_cs4227(hw);
 285         if (status != IXGBE_SUCCESS) {
 286                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 287                         "CS4227 reset failed: %d", status);
 288                 goto out;
 289         }
 290
 291         /* Reset takes so long, temporarily release semaphore in case the
 292          * other driver instance is waiting for the reset indication.
 293          */
 294         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 295                            IXGBE_CS4227_RESET_PENDING);
 296         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 297         msec_delay(10);
 298         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 299         if (status != IXGBE_SUCCESS) {
 300                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 301                         "semaphore failed with %d", status);
 302                 return;
 303         }
 304
 305         /* Record completion for next time. */
 306         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 307                 IXGBE_CS4227_RESET_COMPLETE);
 308
 309 out:
 310         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 311         msec_delay(hw->eeprom.semaphore_delay);
 312 }
 313
 314 /**
 315  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 316  * @hw: pointer to hardware structure
 317  **/
 318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 319 {
 320         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 321
 322         if (hw->bus.lan_id) {
 323                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 324                 esdp |= IXGBE_ESDP_SDP1_DIR;
 325         }
 326         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 327         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 328         IXGBE_WRITE_FLUSH(hw);
 329 }
 330
 331 /**
 332  * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
 333  * @hw: pointer to hardware structure
 334  * @reg_addr: 32 bit address of PHY register to read
 335  * @dev_type: always unused
 336  * @phy_data: Pointer to read data from PHY register
 337  */
 338 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 339                                      u32 dev_type, u16 *phy_data)
 340 {
 341         u32 i, data, command;
 342         UNREFERENCED_1PARAMETER(dev_type);
 343
 344         /* Setup and write the read command */
 345         command = (reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 346                 (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 347                 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 348                 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ |
 349                 IXGBE_MSCA_MDI_COMMAND;
 350
 351         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 352
 353         /* Check every 10 usec to see if the access completed.
 354          * The MDI Command bit will clear when the operation is
 355          * complete
 356          */
 357         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 358                 usec_delay(10);
 359
 360                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 361                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 362                         break;
 363         }
 364
 365         if (command & IXGBE_MSCA_MDI_COMMAND) {
 366                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 367                               "PHY read command did not complete.\n");
 368                 return IXGBE_ERR_PHY;
 369         }
 370
 371         /* Read operation is complete.  Get the data from MSRWD */
 372         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 373         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 374         *phy_data = (u16)data;
 375
 376         return IXGBE_SUCCESS;
 377 }
 378
 379 /**
 380  * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
 381  * @hw: pointer to hardware structure
 382  * @reg_addr: 32 bit PHY register to write
 383  * @dev_type: always unused
 384  * @phy_data: Data to write to the PHY register
 385  */
 386 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 387                                       u32 dev_type, u16 phy_data)
 388 {
 389         u32 i, command;
 390         UNREFERENCED_1PARAMETER(dev_type);
 391
 392         /* Put the data in the MDI single read and write data register*/
 393         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 394
 395         /* Setup and write the write command */
 396         command = (reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 397                 (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 398                 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 399                 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
 400                 IXGBE_MSCA_MDI_COMMAND;
 401
 402         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 403
 404         /* Check every 10 usec to see if the access completed.
 405          * The MDI Command bit will clear when the operation is
 406          * complete
 407          */
 408         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 409                 usec_delay(10);
 410
 411                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 412                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 413                         break;
 414         }
 415
 416         if (command & IXGBE_MSCA_MDI_COMMAND) {
 417                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 418                               "PHY write cmd didn't complete\n");
 419                 return IXGBE_ERR_PHY;
 420         }
 421
 422         return IXGBE_SUCCESS;
 423 }
 424
 425 /**
 426  * ixgbe_identify_phy_1g - Get 1g PHY type based on device id
 427  * @hw: pointer to hardware structure
 428  *
 429  * Returns error code
 430  */
 431 STATIC s32 ixgbe_identify_phy_1g(struct ixgbe_hw *hw)
 432 {
 433         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 434         u16 phy_id_high;
 435         u16 phy_id_low;
 436         s32 rc;
 437
 438         rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 439         if (rc)
 440                 return rc;
 441
 442         rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_MDIO_PHY_ID_HIGH, 0,
 443                                        &phy_id_high);
 444         if (rc)
 445                 goto rel_out;
 446
 447         rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_MDIO_PHY_ID_LOW, 0,
 448                                        &phy_id_low);
 449         if (rc)
 450                 goto rel_out;
 451
 452         hw->phy.id = (u32)phy_id_high << 16;
 453         hw->phy.id |= phy_id_low & IXGBE_PHY_REVISION_MASK;
 454         hw->phy.revision = (u32)phy_id_low & ~IXGBE_PHY_REVISION_MASK;
 455
 456 rel_out:
 457         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 458
 459         return rc;
 460 }
 461
 462 /**
 463  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 464  * @hw: pointer to hardware structure
 465  *
 466  * Returns error code
 467  */
 468 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 469 {
 470         switch (hw->device_id) {
 471         case IXGBE_DEV_ID_X550EM_A_SFP:
 472                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
 473                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
 474                 if (hw->bus.lan_id)
 475                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 476                 else
 477                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 478                 return ixgbe_identify_module_generic(hw);
 479         case IXGBE_DEV_ID_X550EM_X_SFP:
 480                 /* set up for CS4227 usage */
 481                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 482                 ixgbe_setup_mux_ctl(hw);
 483                 ixgbe_check_cs4227(hw);
 484                 /* Fallthrough */
 485
 486         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 487                 return ixgbe_identify_module_generic(hw);
 488                 break;
 489         case IXGBE_DEV_ID_X550EM_X_KX4:
 490                 hw->phy.type = ixgbe_phy_x550em_kx4;
 491                 break;
 492         case IXGBE_DEV_ID_X550EM_X_KR:
 493         case IXGBE_DEV_ID_X550EM_A_KR:
 494         case IXGBE_DEV_ID_X550EM_A_KR_L:
 495                 hw->phy.type = ixgbe_phy_x550em_kr;
 496                 break;
 497         case IXGBE_DEV_ID_X550EM_X_1G_T:
 498         case IXGBE_DEV_ID_X550EM_X_10G_T:
 499         case IXGBE_DEV_ID_X550EM_A_10G_T:
 500                 return ixgbe_identify_phy_generic(hw);
 501         case IXGBE_DEV_ID_X550EM_A_1G_T:
 502         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 503                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
 504                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
 505                 if (hw->bus.lan_id)
 506                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 507                 else
 508                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 509                 return ixgbe_identify_phy_1g(hw);
 510         default:
 511                 break;
 512         }
 513         return IXGBE_SUCCESS;
 514 }
 515
 516 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 517                                      u32 device_type, u16 *phy_data)
 518 {
 519         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 520         return IXGBE_NOT_IMPLEMENTED;
 521 }
 522
 523 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 524                                       u32 device_type, u16 phy_data)
 525 {
 526         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 527         return IXGBE_NOT_IMPLEMENTED;
 528 }
 529
 530 /**
 531  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 532  * @hw: pointer to the hardware structure
 533  * @addr: I2C bus address to read from
 534  * @reg: I2C device register to read from
 535  * @val: pointer to location to receive read value
 536  *
 537  * Returns an error code on error.
 538  **/
 539 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 540                                            u16 reg, u16 *val)
 541 {
 542         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 543 }
 544
 545 /**
 546  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 547  * @hw: pointer to the hardware structure
 548  * @addr: I2C bus address to read from
 549  * @reg: I2C device register to read from
 550  * @val: pointer to location to receive read value
 551  *
 552  * Returns an error code on error.
 553  **/
 554 STATIC s32
 555 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 556                                          u16 reg, u16 *val)
 557 {
 558         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 559 }
 560
 561 /**
 562  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 563  * @hw: pointer to the hardware structure
 564  * @addr: I2C bus address to write to
 565  * @reg: I2C device register to write to
 566  * @val: value to write
 567  *
 568  * Returns an error code on error.
 569  **/
 570 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 571                                             u8 addr, u16 reg, u16 val)
 572 {
 573         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 574 }
 575
 576 /**
 577  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 578  * @hw: pointer to the hardware structure
 579  * @addr: I2C bus address to write to
 580  * @reg: I2C device register to write to
 581  * @val: value to write
 582  *
 583  * Returns an error code on error.
 584  **/
 585 STATIC s32
 586 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 587                                           u8 addr, u16 reg, u16 val)
 588 {
 589         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 590 }
 591
 592 /**
 593 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 594 *  @hw: pointer to hardware structure
 595 *
 596 *  Initialize the function pointers and for MAC type X550EM.
 597 *  Does not touch the hardware.
 598 **/
 599 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 600 {
 601         struct ixgbe_mac_info *mac = &hw->mac;
 602         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 603         struct ixgbe_phy_info *phy = &hw->phy;
 604         struct ixgbe_link_info *link = &hw->link;
 605         s32 ret_val;
 606
 607         DEBUGFUNC("ixgbe_init_ops_X550EM");
 608
 609         /* Similar to X550 so start there. */
 610         ret_val = ixgbe_init_ops_X550(hw);
 611
 612         /* Since this function eventually calls
 613          * ixgbe_init_ops_540 by design, we are setting
 614          * the pointers to NULL explicitly here to overwrite
 615          * the values being set in the x540 function.
 616          */
 617         /* Thermal sensor not supported in x550EM */
 618         mac->ops.get_thermal_sensor_data = NULL;
 619         mac->ops.init_thermal_sensor_thresh = NULL;
 620         mac->thermal_sensor_enabled = false;
 621
 622         /* FCOE not supported in x550EM */
 623         mac->ops.get_san_mac_addr = NULL;
 624         mac->ops.set_san_mac_addr = NULL;
 625         mac->ops.get_wwn_prefix = NULL;
 626         mac->ops.get_fcoe_boot_status = NULL;
 627
 628         /* IPsec not supported in x550EM */
 629         mac->ops.disable_sec_rx_path = NULL;
 630         mac->ops.enable_sec_rx_path = NULL;
 631
 632         /* AUTOC register is not present in x550EM. */
 633         mac->ops.prot_autoc_read = NULL;
 634         mac->ops.prot_autoc_write = NULL;
 635
 636         /* X550EM bus type is internal*/
 637         hw->bus.type = ixgbe_bus_type_internal;
 638         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 639
 640         if (hw->mac.type == ixgbe_mac_X550EM_x) {
 641                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 642                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 643                 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 644                 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 645                 link->ops.read_link = ixgbe_read_i2c_combined_generic;
 646                 link->ops.read_link_unlocked =
 647                                 ixgbe_read_i2c_combined_generic_unlocked;
 648                 link->ops.write_link = ixgbe_write_i2c_combined_generic;
 649                 link->ops.write_link_unlocked =
 650                                 ixgbe_write_i2c_combined_generic_unlocked;
 651                 link->addr = IXGBE_CS4227;
 652         }
 653         if (hw->mac.type == ixgbe_mac_X550EM_a) {
 654                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 655                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 656                 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 657                 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 658         }
 659
 660         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 661         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 662         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 663         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 664         mac->ops.get_supported_physical_layer =
 665                                     ixgbe_get_supported_physical_layer_X550em;
 666
 667         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 668                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 669         else
 670                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 671
 672         switch (hw->device_id) {
 673         case IXGBE_DEV_ID_X550EM_X_KR:
 674         case IXGBE_DEV_ID_X550EM_A_KR:
 675         case IXGBE_DEV_ID_X550EM_A_KR_L:
 676                 break;
 677         default:
 678                 mac->ops.setup_eee = NULL;
 679         }
 680
 681         /* PHY */
 682         phy->ops.init = ixgbe_init_phy_ops_X550em;
 683         phy->ops.identify = ixgbe_identify_phy_x550em;
 684         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 685                 phy->ops.set_phy_power = NULL;
 686
 687
 688         /* EEPROM */
 689         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 690         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 691         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 692         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 693         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 694         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 695         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 696         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 697
 698         return ret_val;
 699 }
 700
 701 /**
 702  *  ixgbe_dmac_config_X550
 703  *  @hw: pointer to hardware structure
 704  *
 705  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 706  *  When disabling dmac, dmac enable dmac bit is cleared.
 707  **/
 708 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 709 {
 710         u32 reg, high_pri_tc;
 711
 712         DEBUGFUNC("ixgbe_dmac_config_X550");
 713
 714         /* Disable DMA coalescing before configuring */
 715         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 716         reg &= ~IXGBE_DMACR_DMAC_EN;
 717         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 718
 719         /* Disable DMA Coalescing if the watchdog timer is 0 */
 720         if (!hw->mac.dmac_config.watchdog_timer)
 721                 goto out;
 722
 723         ixgbe_dmac_config_tcs_X550(hw);
 724
 725         /* Configure DMA Coalescing Control Register */
 726         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 727
 728         /* Set the watchdog timer in units of 40.96 usec */
 729         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 730         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 731
 732         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 733         /* If fcoe is enabled, set high priority traffic class */
 734         if (hw->mac.dmac_config.fcoe_en) {
 735                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 736                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 737                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 738         }
 739         reg |= IXGBE_DMACR_EN_MNG_IND;
 740
 741         /* Enable DMA coalescing after configuration */
 742         reg |= IXGBE_DMACR_DMAC_EN;
 743         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 744
 745 out:
 746         return IXGBE_SUCCESS;
 747 }
 748
 749 /**
 750  *  ixgbe_dmac_config_tcs_X550
 751  *  @hw: pointer to hardware structure
 752  *
 753  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 754  *  be cleared before configuring.
 755  **/
 756 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 757 {
 758         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 759
 760         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 761
 762         /* Configure DMA coalescing enabled */
 763         switch (hw->mac.dmac_config.link_speed) {
 764         case IXGBE_LINK_SPEED_100_FULL:
 765                 pb_headroom = IXGBE_DMACRXT_100M;
 766                 break;
 767         case IXGBE_LINK_SPEED_1GB_FULL:
 768                 pb_headroom = IXGBE_DMACRXT_1G;
 769                 break;
 770         default:
 771                 pb_headroom = IXGBE_DMACRXT_10G;
 772                 break;
 773         }
 774
 775         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 776                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 777
 778         /* Set the per Rx packet buffer receive threshold */
 779         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 780                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 781                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 782
 783                 if (tc < hw->mac.dmac_config.num_tcs) {
 784                         /* Get Rx PB size */
 785                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 786                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 787                                 IXGBE_RXPBSIZE_SHIFT;
 788
 789                         /* Calculate receive buffer threshold in kilobytes */
 790                         if (rx_pb_size > pb_headroom)
 791                                 rx_pb_size = rx_pb_size - pb_headroom;
 792                         else
 793                                 rx_pb_size = 0;
 794
 795                         /* Minimum of MFS shall be set for DMCTH */
 796                         reg |= (rx_pb_size > maxframe_size_kb) ?
 797                                 rx_pb_size : maxframe_size_kb;
 798                 }
 799                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 800         }
 801         return IXGBE_SUCCESS;
 802 }
 803
 804 /**
 805  *  ixgbe_dmac_update_tcs_X550
 806  *  @hw: pointer to hardware structure
 807  *
 808  *  Disables dmac, updates per TC settings, and then enables dmac.
 809  **/
 810 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 811 {
 812         u32 reg;
 813
 814         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 815
 816         /* Disable DMA coalescing before configuring */
 817         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 818         reg &= ~IXGBE_DMACR_DMAC_EN;
 819         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 820
 821         ixgbe_dmac_config_tcs_X550(hw);
 822
 823         /* Enable DMA coalescing after configuration */
 824         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 825         reg |= IXGBE_DMACR_DMAC_EN;
 826         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 827
 828         return IXGBE_SUCCESS;
 829 }
 830
 831 /**
 832  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 833  *  @hw: pointer to hardware structure
 834  *
 835  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 836  *  ixgbe_hw struct in order to set up EEPROM access.
 837  **/
 838 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 839 {
 840         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 841         u32 eec;
 842         u16 eeprom_size;
 843
 844         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 845
 846         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 847                 eeprom->semaphore_delay = 10;
 848                 eeprom->type = ixgbe_flash;
 849
 850                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 851                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 852                                     IXGBE_EEC_SIZE_SHIFT);
 853                 eeprom->word_size = 1 << (eeprom_size +
 854                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 855
 856                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 857                           eeprom->type, eeprom->word_size);
 858         }
 859
 860         return IXGBE_SUCCESS;
 861 }
 862
 863 /**
 864  * ixgbe_enable_eee_x550 - Enable EEE support
 865  * @hw: pointer to hardware structure
 866  */
 867 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
 868 {
 869         u16 autoneg_eee_reg;
 870         u32 link_reg;
 871         s32 status;
 872
 873         if (hw->mac.type == ixgbe_mac_X550) {
 874                 /* Advertise EEE capability */
 875                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 876                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 877                                      &autoneg_eee_reg);
 878
 879                 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 880                                     IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 881                                     IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 882
 883                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 884                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 885                                       autoneg_eee_reg);
 886                 return IXGBE_SUCCESS;
 887         }
 888
 889         switch (hw->device_id) {
 890         case IXGBE_DEV_ID_X550EM_X_KR:
 891         case IXGBE_DEV_ID_X550EM_A_KR:
 892         case IXGBE_DEV_ID_X550EM_A_KR_L:
 893                 status = hw->mac.ops.read_iosf_sb_reg(hw,
 894                                      IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 895                                      IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 896                 if (status != IXGBE_SUCCESS)
 897                         return status;
 898
 899                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 900                         IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 901
 902                 /* Don't advertise FEC capability when EEE enabled. */
 903                 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 904
 905                 status = hw->mac.ops.write_iosf_sb_reg(hw,
 906                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 907                                       IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 908                 if (status != IXGBE_SUCCESS)
 909                         return status;
 910                 break;
 911         default:
 912                 break;
 913         }
 914
 915         return IXGBE_SUCCESS;
 916 }
 917
 918 /**
 919  * ixgbe_disable_eee_x550 - Disable EEE support
 920  * @hw: pointer to hardware structure
 921  */
 922 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
 923 {
 924         u16 autoneg_eee_reg;
 925         u32 link_reg;
 926         s32 status;
 927
 928         if (hw->mac.type == ixgbe_mac_X550) {
 929                 /* Disable advertised EEE capability */
 930                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 931                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 932                                      &autoneg_eee_reg);
 933
 934                 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 935                                      IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 936                                      IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 937
 938                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 939                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 940                                       autoneg_eee_reg);
 941                 return IXGBE_SUCCESS;
 942         }
 943
 944         switch (hw->device_id) {
 945         case IXGBE_DEV_ID_X550EM_X_KR:
 946         case IXGBE_DEV_ID_X550EM_A_KR:
 947         case IXGBE_DEV_ID_X550EM_A_KR_L:
 948                 status = hw->mac.ops.read_iosf_sb_reg(hw,
 949                                      IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 950                                      IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 951                 if (status != IXGBE_SUCCESS)
 952                         return status;
 953
 954                 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 955                               IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 956
 957                 /* Advertise FEC capability when EEE is disabled. */
 958                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 959
 960                 status = hw->mac.ops.write_iosf_sb_reg(hw,
 961                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 962                                       IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 963                 if (status != IXGBE_SUCCESS)
 964                         return status;
 965                 break;
 966         default:
 967                 break;
 968         }
 969
 970         return IXGBE_SUCCESS;
 971 }
 972
 973 /**
 974  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 975  *  @hw: pointer to the HW structure
 976  *  @enable_eee: boolean flag to enable EEE
 977  *
 978  *  Enable/disable EEE based on enable_eee flag.
 979  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 980  *  are modified.
 981  *
 982  **/
 983 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 984 {
 985         s32 status;
 986         u32 eeer;
 987
 988         DEBUGFUNC("ixgbe_setup_eee_X550");
 989
 990         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 991         /* Enable or disable EEE per flag */
 992         if (enable_eee) {
 993                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 994
 995                 /* Not supported on first revision of X550EM_x. */
 996                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
 997                     !(IXGBE_FUSES0_REV_MASK &
 998                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
 999                         return IXGBE_SUCCESS;
1000                 status = ixgbe_enable_eee_x550(hw);
1001                 if (status)
1002                         return status;
1003         } else {
1004                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1005
1006                 status = ixgbe_disable_eee_x550(hw);
1007                 if (status)
1008                         return status;
1009         }
1010         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1011
1012         return IXGBE_SUCCESS;
1013 }
1014
1015 /**
1016  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1017  * @hw: pointer to hardware structure
1018  * @enable: enable or disable source address pruning
1019  * @pool: Rx pool to set source address pruning for
1020  **/
1021 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1022                                            unsigned int pool)
1023 {
1024         u64 pfflp;
1025
1026         /* max rx pool is 63 */
1027         if (pool > 63)
1028                 return;
1029
1030         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1031         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1032
1033         if (enable)
1034                 pfflp |= (1ULL << pool);
1035         else
1036                 pfflp &= ~(1ULL << pool);
1037
1038         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1039         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1040 }
1041
1042 /**
1043  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1044  *  @hw: pointer to hardware structure
1045  *  @enable: enable or disable switch for Ethertype anti-spoofing
1046  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1047  *
1048  **/
1049 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1050                 bool enable, int vf)
1051 {
1052         int vf_target_reg = vf >> 3;
1053         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1054         u32 pfvfspoof;
1055
1056         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1057
1058         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1059         if (enable)
1060                 pfvfspoof |= (1 << vf_target_shift);
1061         else
1062                 pfvfspoof &= ~(1 << vf_target_shift);
1063
1064         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1065 }
1066
1067 /**
1068  * ixgbe_iosf_wait - Wait for IOSF command completion
1069  * @hw: pointer to hardware structure
1070  * @ctrl: pointer to location to receive final IOSF control value
1071  *
1072  * Returns failing status on timeout
1073  *
1074  * Note: ctrl can be NULL if the IOSF control register value is not needed
1075  **/
1076 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1077 {
1078         u32 i, command = 0;
1079
1080         /* Check every 10 usec to see if the address cycle completed.
1081          * The SB IOSF BUSY bit will clear when the operation is
1082          * complete
1083          */
1084         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1085                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1086                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1087                         break;
1088                 usec_delay(10);
1089         }
1090         if (ctrl)
1091                 *ctrl = command;
1092         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1093                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1094                 return IXGBE_ERR_PHY;
1095         }
1096
1097         return IXGBE_SUCCESS;
1098 }
1099
1100 /**
1101  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1102  *  device
1103  *  @hw: pointer to hardware structure
1104  *  @reg_addr: 32 bit PHY register to write
1105  *  @device_type: 3 bit device type
1106  *  @data: Data to write to the register
1107  **/
1108 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1109                             u32 device_type, u32 data)
1110 {
1111         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1112         u32 command, error;
1113         s32 ret;
1114
1115         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1116         if (ret != IXGBE_SUCCESS)
1117                 return ret;
1118
1119         ret = ixgbe_iosf_wait(hw, NULL);
1120         if (ret != IXGBE_SUCCESS)
1121                 goto out;
1122
1123         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1124                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1125
1126         /* Write IOSF control register */
1127         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1128
1129         /* Write IOSF data register */
1130         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1131
1132         ret = ixgbe_iosf_wait(hw, &command);
1133
1134         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1135                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1136                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1137                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1138                               "Failed to write, error %x\n", error);
1139                 ret = IXGBE_ERR_PHY;
1140         }
1141
1142 out:
1143         ixgbe_release_swfw_semaphore(hw, gssr);
1144         return ret;
1145 }
1146
1147 /**
1148  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1149  *  device
1150  *  @hw: pointer to hardware structure
1151  *  @reg_addr: 32 bit PHY register to write
1152  *  @device_type: 3 bit device type
1153  *  @phy_data: Pointer to read data from the register
1154  **/
1155 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1156                            u32 device_type, u32 *data)
1157 {
1158         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1159         u32 command, error;
1160         s32 ret;
1161
1162         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1163         if (ret != IXGBE_SUCCESS)
1164                 return ret;
1165
1166         ret = ixgbe_iosf_wait(hw, NULL);
1167         if (ret != IXGBE_SUCCESS)
1168                 goto out;
1169
1170         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1171                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1172
1173         /* Write IOSF control register */
1174         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1175
1176         ret = ixgbe_iosf_wait(hw, &command);
1177
1178         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1179                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1180                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1181                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1182                                 "Failed to read, error %x\n", error);
1183                 ret = IXGBE_ERR_PHY;
1184         }
1185
1186         if (ret == IXGBE_SUCCESS)
1187                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1188
1189 out:
1190         ixgbe_release_swfw_semaphore(hw, gssr);
1191         return ret;
1192 }
1193
1194 /**
1195  * ixgbe_get_phy_token - Get the token for shared phy access
1196  * @hw: Pointer to hardware structure
1197  */
1198
1199 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1200 {
1201         struct ixgbe_hic_phy_token_req token_cmd;
1202         s32 status;
1203
1204         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1205         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1206         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1207         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1208         token_cmd.port_number = hw->bus.lan_id;
1209         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1210         token_cmd.pad = 0;
1211         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1212                                               sizeof(token_cmd),
1213                                               IXGBE_HI_COMMAND_TIMEOUT,
1214                                               true);
1215         if (status)
1216                 return status;
1217         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1218                 return IXGBE_SUCCESS;
1219         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1220                 return IXGBE_ERR_FW_RESP_INVALID;
1221
1222         return IXGBE_ERR_TOKEN_RETRY;
1223 }
1224
1225 /**
1226  * ixgbe_put_phy_token - Put the token for shared phy access
1227  * @hw: Pointer to hardware structure
1228  */
1229
1230 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1231 {
1232         struct ixgbe_hic_phy_token_req token_cmd;
1233         s32 status;
1234
1235         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1236         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1237         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1238         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1239         token_cmd.port_number = hw->bus.lan_id;
1240         token_cmd.command_type = FW_PHY_TOKEN_REL;
1241         token_cmd.pad = 0;
1242         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1243                                               sizeof(token_cmd),
1244                                               IXGBE_HI_COMMAND_TIMEOUT,
1245                                               true);
1246         if (status)
1247                 return status;
1248         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1249                 return IXGBE_SUCCESS;
1250
1251         DEBUGOUT("Put PHY Token host interface command failed");
1252         return IXGBE_ERR_FW_RESP_INVALID;
1253 }
1254
1255 /**
1256  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1257  *  of the IOSF device
1258  *  @hw: pointer to hardware structure
1259  *  @reg_addr: 32 bit PHY register to write
1260  *  @device_type: 3 bit device type
1261  *  @data: Data to write to the register
1262  **/
1263 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1264                                   u32 device_type, u32 data)
1265 {
1266         struct ixgbe_hic_internal_phy_req write_cmd;
1267         s32 status;
1268         UNREFERENCED_1PARAMETER(device_type);
1269
1270         memset(&write_cmd, 0, sizeof(write_cmd));
1271         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1272         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1273         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1274         write_cmd.port_number = hw->bus.lan_id;
1275         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1276         write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1277         write_cmd.write_data = IXGBE_CPU_TO_LE32(data);
1278
1279         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1280                                               sizeof(write_cmd),
1281                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1282
1283         return status;
1284 }
1285
1286 /**
1287  *  ixgbe_read_iosf_sb_reg_x550a - Writes a value to specified register
1288  *  of the IOSF device.
1289  *  @hw: pointer to hardware structure
1290  *  @reg_addr: 32 bit PHY register to write
1291  *  @device_type: 3 bit device type
1292  *  @data: Pointer to read data from the register
1293  **/
1294 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1295                                  u32 device_type, u32 *data)
1296 {
1297         union {
1298                 struct ixgbe_hic_internal_phy_req cmd;
1299                 struct ixgbe_hic_internal_phy_resp rsp;
1300         } hic;
1301         s32 status;
1302         UNREFERENCED_1PARAMETER(device_type);
1303
1304         memset(&hic, 0, sizeof(hic));
1305         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1306         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1307         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1308         hic.cmd.port_number = hw->bus.lan_id;
1309         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1310         hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1311
1312         status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1313                                               sizeof(hic.cmd),
1314                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1315
1316         /* Extract the register value from the response. */
1317         *data = IXGBE_LE32_TO_CPU(hic.rsp.read_data);
1318
1319         return status;
1320 }
1321
1322 /**
1323  *  ixgbe_disable_mdd_X550
1324  *  @hw: pointer to hardware structure
1325  *
1326  *  Disable malicious driver detection
1327  **/
1328 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1329 {
1330         u32 reg;
1331
1332         DEBUGFUNC("ixgbe_disable_mdd_X550");
1333
1334         /* Disable MDD for TX DMA and interrupt */
1335         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1336         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1337         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1338
1339         /* Disable MDD for RX and interrupt */
1340         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1341         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1342         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1343 }
1344
1345 /**
1346  *  ixgbe_enable_mdd_X550
1347  *  @hw: pointer to hardware structure
1348  *
1349  *  Enable malicious driver detection
1350  **/
1351 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1352 {
1353         u32 reg;
1354
1355         DEBUGFUNC("ixgbe_enable_mdd_X550");
1356
1357         /* Enable MDD for TX DMA and interrupt */
1358         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1359         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1360         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1361
1362         /* Enable MDD for RX and interrupt */
1363         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1364         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1365         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1366 }
1367
1368 /**
1369  *  ixgbe_restore_mdd_vf_X550
1370  *  @hw: pointer to hardware structure
1371  *  @vf: vf index
1372  *
1373  *  Restore VF that was disabled during malicious driver detection event
1374  **/
1375 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1376 {
1377         u32 idx, reg, num_qs, start_q, bitmask;
1378
1379         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1380
1381         /* Map VF to queues */
1382         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1383         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1384         case IXGBE_MRQC_VMDQRT8TCEN:
1385                 num_qs = 8;  /* 16 VFs / pools */
1386                 bitmask = 0x000000FF;
1387                 break;
1388         case IXGBE_MRQC_VMDQRSS32EN:
1389         case IXGBE_MRQC_VMDQRT4TCEN:
1390                 num_qs = 4;  /* 32 VFs / pools */
1391                 bitmask = 0x0000000F;
1392                 break;
1393         default:            /* 64 VFs / pools */
1394                 num_qs = 2;
1395                 bitmask = 0x00000003;
1396                 break;
1397         }
1398         start_q = vf * num_qs;
1399
1400         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1401         idx = start_q / 32;
1402         reg = 0;
1403         reg |= (bitmask << (start_q % 32));
1404         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1405         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1406 }
1407
1408 /**
1409  *  ixgbe_mdd_event_X550
1410  *  @hw: pointer to hardware structure
1411  *  @vf_bitmap: vf bitmap of malicious vfs
1412  *
1413  *  Handle malicious driver detection event.
1414  **/
1415 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1416 {
1417         u32 wqbr;
1418         u32 i, j, reg, q, shift, vf, idx;
1419
1420         DEBUGFUNC("ixgbe_mdd_event_X550");
1421
1422         /* figure out pool size for mapping to vf's */
1423         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1424         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1425         case IXGBE_MRQC_VMDQRT8TCEN:
1426                 shift = 3;  /* 16 VFs / pools */
1427                 break;
1428         case IXGBE_MRQC_VMDQRSS32EN:
1429         case IXGBE_MRQC_VMDQRT4TCEN:
1430                 shift = 2;  /* 32 VFs / pools */
1431                 break;
1432         default:
1433                 shift = 1;  /* 64 VFs / pools */
1434                 break;
1435         }
1436
1437         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1438         for (i = 0; i < 4; i++) {
1439                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1440                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1441
1442                 if (!wqbr)
1443                         continue;
1444
1445                 /* Get malicious queue */
1446                 for (j = 0; j < 32 && wqbr; j++) {
1447
1448                         if (!(wqbr & (1 << j)))
1449                                 continue;
1450
1451                         /* Get queue from bitmask */
1452                         q = j + (i * 32);
1453
1454                         /* Map queue to vf */
1455                         vf = (q >> shift);
1456
1457                         /* Set vf bit in vf_bitmap */
1458                         idx = vf / 32;
1459                         vf_bitmap[idx] |= (1 << (vf % 32));
1460                         wqbr &= ~(1 << j);
1461                 }
1462         }
1463 }
1464
1465 /**
1466  *  ixgbe_get_media_type_X550em - Get media type
1467  *  @hw: pointer to hardware structure
1468  *
1469  *  Returns the media type (fiber, copper, backplane)
1470  */
1471 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1472 {
1473         enum ixgbe_media_type media_type;
1474
1475         DEBUGFUNC("ixgbe_get_media_type_X550em");
1476
1477         /* Detect if there is a copper PHY attached. */
1478         switch (hw->device_id) {
1479         case IXGBE_DEV_ID_X550EM_X_KR:
1480         case IXGBE_DEV_ID_X550EM_X_KX4:
1481         case IXGBE_DEV_ID_X550EM_A_KR:
1482         case IXGBE_DEV_ID_X550EM_A_KR_L:
1483                 media_type = ixgbe_media_type_backplane;
1484                 break;
1485         case IXGBE_DEV_ID_X550EM_X_SFP:
1486         case IXGBE_DEV_ID_X550EM_A_SFP:
1487         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1488         case IXGBE_DEV_ID_X550EM_A_QSFP:
1489         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1490                 media_type = ixgbe_media_type_fiber;
1491                 break;
1492         case IXGBE_DEV_ID_X550EM_X_1G_T:
1493         case IXGBE_DEV_ID_X550EM_X_10G_T:
1494         case IXGBE_DEV_ID_X550EM_A_10G_T:
1495                 media_type = ixgbe_media_type_copper;
1496                 break;
1497         case IXGBE_DEV_ID_X550EM_A_SGMII:
1498         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1499                 media_type = ixgbe_media_type_backplane;
1500                 hw->phy.type = ixgbe_phy_sgmii;
1501                 break;
1502         case IXGBE_DEV_ID_X550EM_A_1G_T:
1503         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1504                 media_type = ixgbe_media_type_copper;
1505                 hw->phy.type = ixgbe_phy_m88;
1506                 break;
1507         default:
1508                 media_type = ixgbe_media_type_unknown;
1509                 break;
1510         }
1511         return media_type;
1512 }
1513
1514 /**
1515  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1516  *  @hw: pointer to hardware structure
1517  *  @linear: true if SFP module is linear
1518  */
1519 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1520 {
1521         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1522
1523         switch (hw->phy.sfp_type) {
1524         case ixgbe_sfp_type_not_present:
1525                 return IXGBE_ERR_SFP_NOT_PRESENT;
1526         case ixgbe_sfp_type_da_cu_core0:
1527         case ixgbe_sfp_type_da_cu_core1:
1528                 *linear = true;
1529                 break;
1530         case ixgbe_sfp_type_srlr_core0:
1531         case ixgbe_sfp_type_srlr_core1:
1532         case ixgbe_sfp_type_da_act_lmt_core0:
1533         case ixgbe_sfp_type_da_act_lmt_core1:
1534         case ixgbe_sfp_type_1g_sx_core0:
1535         case ixgbe_sfp_type_1g_sx_core1:
1536         case ixgbe_sfp_type_1g_lx_core0:
1537         case ixgbe_sfp_type_1g_lx_core1:
1538                 *linear = false;
1539                 break;
1540         case ixgbe_sfp_type_unknown:
1541         case ixgbe_sfp_type_1g_cu_core0:
1542         case ixgbe_sfp_type_1g_cu_core1:
1543         default:
1544                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1545         }
1546
1547         return IXGBE_SUCCESS;
1548 }
1549
1550 /**
1551  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1552  *  @hw: pointer to hardware structure
1553  *
1554  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1555  **/
1556 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1557 {
1558         s32 status;
1559         bool linear;
1560
1561         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1562
1563         status = ixgbe_identify_module_generic(hw);
1564
1565         if (status != IXGBE_SUCCESS)
1566                 return status;
1567
1568         /* Check if SFP module is supported */
1569         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1570
1571         return status;
1572 }
1573
1574 /**
1575  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1576  *  @hw: pointer to hardware structure
1577  */
1578 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1579 {
1580         s32 status;
1581         bool linear;
1582
1583         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1584
1585         /* Check if SFP module is supported */
1586         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1587
1588         if (status != IXGBE_SUCCESS)
1589                 return status;
1590
1591         ixgbe_init_mac_link_ops_X550em(hw);
1592         hw->phy.ops.reset = NULL;
1593
1594         return IXGBE_SUCCESS;
1595 }
1596
1597 /**
1598  * ixgbe_setup_sgmii - Set up link for sgmii
1599  * @hw: pointer to hardware structure
1600  */
1601 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1602                              bool autoneg_wait_to_complete)
1603 {
1604         struct ixgbe_mac_info *mac = &hw->mac;
1605         u32 lval, sval;
1606         s32 rc;
1607         UNREFERENCED_2PARAMETER(speed, autoneg_wait_to_complete);
1608
1609         rc = mac->ops.read_iosf_sb_reg(hw,
1610                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1611                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1612         if (rc)
1613                 return rc;
1614
1615         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1616         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1617         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1618         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1619         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1620         rc = mac->ops.write_iosf_sb_reg(hw,
1621                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1622                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1623         if (rc)
1624                 return rc;
1625
1626         rc = mac->ops.read_iosf_sb_reg(hw,
1627                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1628                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1629         if (rc)
1630                 return rc;
1631
1632         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1633         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1634         rc = mac->ops.write_iosf_sb_reg(hw,
1635                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1636                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1637         if (rc)
1638                 return rc;
1639
1640         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1641         rc = mac->ops.write_iosf_sb_reg(hw,
1642                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1643                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1644
1645         return rc;
1646 }
1647
1648 /**
1649  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1650  *  @hw: pointer to hardware structure
1651  */
1652 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1653 {
1654         struct ixgbe_mac_info *mac = &hw->mac;
1655
1656         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1657
1658         switch (hw->mac.ops.get_media_type(hw)) {
1659         case ixgbe_media_type_fiber:
1660                 /* CS4227 does not support autoneg, so disable the laser control
1661                  * functions for SFP+ fiber
1662                  */
1663                 mac->ops.disable_tx_laser = NULL;
1664                 mac->ops.enable_tx_laser = NULL;
1665                 mac->ops.flap_tx_laser = NULL;
1666                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1667                 mac->ops.set_rate_select_speed =
1668                                         ixgbe_set_soft_rate_select_speed;
1669                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1670                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1671                         mac->ops.setup_mac_link =
1672                                 ixgbe_setup_mac_link_sfp_x550a;
1673                 else
1674                         mac->ops.setup_mac_link =
1675                                 ixgbe_setup_mac_link_sfp_x550em;
1676                 break;
1677         case ixgbe_media_type_copper:
1678                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1679                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1680                 break;
1681         case ixgbe_media_type_backplane:
1682                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1683                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1684                         mac->ops.setup_link = ixgbe_setup_sgmii;
1685                 break;
1686         default:
1687                 break;
1688         }
1689 }
1690
1691 /**
1692  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1693  *  @hw: pointer to hardware structure
1694  *  @speed: pointer to link speed
1695  *  @autoneg: true when autoneg or autotry is enabled
1696  */
1697 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1698                                        ixgbe_link_speed *speed,
1699                                        bool *autoneg)
1700 {
1701         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1702
1703         /* SFP */
1704         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1705
1706                 /* CS4227 SFP must not enable auto-negotiation */
1707                 *autoneg = false;
1708
1709                 /* Check if 1G SFP module. */
1710                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1711                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1712                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1713                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1714                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1715                         return IXGBE_SUCCESS;
1716                 }
1717
1718                 /* Link capabilities are based on SFP */
1719                 if (hw->phy.multispeed_fiber)
1720                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1721                                  IXGBE_LINK_SPEED_1GB_FULL;
1722                 else
1723                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1724         } else {
1725                 switch (hw->phy.type) {
1726                 case ixgbe_phy_m88:
1727                         *speed = IXGBE_LINK_SPEED_100_FULL |
1728                                  IXGBE_LINK_SPEED_1GB_FULL;
1729                         break;
1730                 case ixgbe_phy_sgmii:
1731                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1732                         break;
1733                 default:
1734                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1735                                  IXGBE_LINK_SPEED_1GB_FULL;
1736                         break;
1737                 }
1738                 *autoneg = true;
1739         }
1740
1741         return IXGBE_SUCCESS;
1742 }
1743
1744 /**
1745  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1746  * @hw: pointer to hardware structure
1747  * @lsc: pointer to boolean flag which indicates whether external Base T
1748  *       PHY interrupt is lsc
1749  *
1750  * Determime if external Base T PHY interrupt cause is high temperature
1751  * failure alarm or link status change.
1752  *
1753  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1754  * failure alarm, else return PHY access status.
1755  */
1756 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1757 {
1758         u32 status;
1759         u16 reg;
1760
1761         *lsc = false;
1762
1763         /* Vendor alarm triggered */
1764         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1765                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1766                                       &reg);
1767
1768         if (status != IXGBE_SUCCESS ||
1769             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1770                 return status;
1771
1772         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1773         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1774                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1775                                       &reg);
1776
1777         if (status != IXGBE_SUCCESS ||
1778             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1779             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1780                 return status;
1781
1782         /* Global alarm triggered */
1783         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1784                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1785                                       &reg);
1786
1787         if (status != IXGBE_SUCCESS)
1788                 return status;
1789
1790         /* If high temperature failure, then return over temp error and exit */
1791         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1792                 /* power down the PHY in case the PHY FW didn't already */
1793                 ixgbe_set_copper_phy_power(hw, false);
1794                 return IXGBE_ERR_OVERTEMP;
1795         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1796                 /*  device fault alarm triggered */
1797                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1798                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1799                                           &reg);
1800
1801                 if (status != IXGBE_SUCCESS)
1802                         return status;
1803
1804                 /* if device fault was due to high temp alarm handle and exit */
1805                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1806                         /* power down the PHY in case the PHY FW didn't */
1807                         ixgbe_set_copper_phy_power(hw, false);
1808                         return IXGBE_ERR_OVERTEMP;
1809                 }
1810         }
1811
1812         /* Vendor alarm 2 triggered */
1813         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1814                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1815
1816         if (status != IXGBE_SUCCESS ||
1817             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1818                 return status;
1819
1820         /* link connect/disconnect event occurred */
1821         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1822                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1823
1824         if (status != IXGBE_SUCCESS)
1825                 return status;
1826
1827         /* Indicate LSC */
1828         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1829                 *lsc = true;
1830
1831         return IXGBE_SUCCESS;
1832 }
1833
1834 /**
1835  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1836  * @hw: pointer to hardware structure
1837  *
1838  * Enable link status change and temperature failure alarm for the external
1839  * Base T PHY
1840  *
1841  * Returns PHY access status
1842  */
1843 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1844 {
1845         u32 status;
1846         u16 reg;
1847         bool lsc;
1848
1849         /* Clear interrupt flags */
1850         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1851
1852         /* Enable link status change alarm */
1853         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1854                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1855
1856         if (status != IXGBE_SUCCESS)
1857                 return status;
1858
1859         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1860
1861         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1862                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1863
1864         if (status != IXGBE_SUCCESS)
1865                 return status;
1866
1867         /* Enable high temperature failure and global fault alarms */
1868         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1869                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1870                                       &reg);
1871
1872         if (status != IXGBE_SUCCESS)
1873                 return status;
1874
1875         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1876                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1877
1878         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1879                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1880                                        reg);
1881
1882         if (status != IXGBE_SUCCESS)
1883                 return status;
1884
1885         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1886         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1887                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1888                                       &reg);
1889
1890         if (status != IXGBE_SUCCESS)
1891                 return status;
1892
1893         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1894                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1895
1896         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1897                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1898                                        reg);
1899
1900         if (status != IXGBE_SUCCESS)
1901                 return status;
1902
1903         /* Enable chip-wide vendor alarm */
1904         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1905                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1906                                       &reg);
1907
1908         if (status != IXGBE_SUCCESS)
1909                 return status;
1910
1911         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1912
1913         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1914                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1915                                        reg);
1916
1917         return status;
1918 }
1919
1920 /**
1921  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1922  *  @hw: pointer to hardware structure
1923  *  @speed: link speed
1924  *
1925  *  Configures the integrated KR PHY.
1926  **/
1927 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1928                                        ixgbe_link_speed speed)
1929 {
1930         s32 status;
1931         u32 reg_val;
1932
1933         status = hw->mac.ops.read_iosf_sb_reg(hw,
1934                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1935                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1936         if (status)
1937                 return status;
1938
1939         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1940         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1941                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1942
1943         /* Advertise 10G support. */
1944         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1945                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1946
1947         /* Advertise 1G support. */
1948         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1949                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1950
1951         /* Restart auto-negotiation. */
1952         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1953         status = hw->mac.ops.write_iosf_sb_reg(hw,
1954                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1955                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1956
1957         return status;
1958 }
1959
1960 /**
1961  * ixgbe_set_master_slave_mode - Set up PHY for master/slave mode
1962  * @hw: pointer to hardware structure
1963  *
1964  * Must be called while holding the PHY semaphore and token
1965  */
1966 STATIC s32 ixgbe_set_master_slave_mode(struct ixgbe_hw *hw)
1967 {
1968         u16 phy_data;
1969         s32 rc;
1970
1971         /* Resolve master/slave mode */
1972         rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_M88E1500_1000T_CTRL, 0,
1973                                        &phy_data);
1974         if (rc)
1975                 return rc;
1976
1977         /* load defaults for future use */
1978         if (phy_data & IXGBE_M88E1500_1000T_CTRL_MS_ENABLE) {
1979                 if (phy_data & IXGBE_M88E1500_1000T_CTRL_MS_VALUE)
1980                         hw->phy.original_ms_type = ixgbe_ms_force_master;
1981                 else
1982                         hw->phy.original_ms_type = ixgbe_ms_force_slave;
1983         } else {
1984                 hw->phy.original_ms_type = ixgbe_ms_auto;
1985         }
1986
1987         switch (hw->phy.ms_type) {
1988         case ixgbe_ms_force_master:
1989                 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
1990                 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_VALUE;
1991                 break;
1992         case ixgbe_ms_force_slave:
1993                 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
1994                 phy_data &= ~IXGBE_M88E1500_1000T_CTRL_MS_VALUE;
1995                 break;
1996         case ixgbe_ms_auto:
1997                 phy_data &= ~IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
1998                 break;
1999         default:
2000                 break;
2001         }
2002
2003         return ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_1000T_CTRL, 0,
2004                                           phy_data);
2005 }
2006
2007 /**
2008  * ixgbe_reset_phy_m88_nolock - Reset m88 PHY without locking
2009  * @hw: pointer to hardware structure
2010  *
2011  * Must be called while holding the PHY semaphore and token
2012  */
2013 STATIC s32 ixgbe_reset_phy_m88_nolock(struct ixgbe_hw *hw)
2014 {
2015         s32 rc;
2016
2017         rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2018         if (rc)
2019                 return rc;
2020
2021         rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_FIBER_CTRL, 0,
2022                                         IXGBE_M88E1500_FIBER_CTRL_RESET |
2023                                         IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2024                                         IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB);
2025         if (rc)
2026                 goto res_out;
2027
2028         rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2029         if (rc)
2030                 goto res_out;
2031
2032         rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_GEN_CTRL, 0,
2033                                         IXGBE_M88E1500_GEN_CTRL_RESET |
2034                                         IXGBE_M88E1500_GEN_CTRL_SGMII_COPPER);
2035         if (rc)
2036                 goto res_out;
2037
2038         rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2039         if (rc)
2040                 goto res_out;
2041
2042         rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2043                                         IXGBE_M88E1500_COPPER_CTRL_RESET |
2044                                         IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2045                                         IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2046                                         IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2047                                         IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB);
2048
2049 res_out:
2050         ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2051         return rc;
2052 }
2053
2054 /**
2055  * ixgbe_reset_phy_m88 - Reset m88 PHY
2056  * @hw: pointer to hardware structure
2057  */
2058 STATIC s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2059 {
2060         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2061         s32 rc;
2062
2063         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2064                 return IXGBE_SUCCESS;
2065
2066         rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2067         if (rc)
2068                 return rc;
2069
2070         rc = ixgbe_reset_phy_m88_nolock(hw);
2071
2072         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2073         return rc;
2074 }
2075
2076 /**
2077  * ixgbe_setup_m88 - setup m88 PHY
2078  * @hw: pointer to hardware structure
2079  */
2080 STATIC s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2081 {
2082         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2083         struct ixgbe_phy_info *phy = &hw->phy;
2084         u16 phy_data;
2085         s32 rc;
2086
2087         if (phy->reset_disable || ixgbe_check_reset_blocked(hw))
2088                 return IXGBE_SUCCESS;
2089
2090         rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2091         if (rc)
2092                 return rc;
2093
2094         rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_M88E1500_PHY_SPEC_CTRL, 0,
2095                                        &phy_data);
2096         if (rc)
2097                 goto rel_out;
2098
2099         /* Enable downshift and setting it to X6 */
2100         phy_data &= ~IXGBE_M88E1500_PSCR_DOWNSHIFT_ENABLE;
2101         phy_data |= IXGBE_M88E1500_PSCR_DOWNSHIFT_6X;
2102         phy_data |= IXGBE_M88E1500_PSCR_DOWNSHIFT_ENABLE;
2103         rc = ixgbe_write_phy_reg_mdi_22(hw,
2104                                         IXGBE_M88E1500_PHY_SPEC_CTRL, 0,
2105                                         phy_data);
2106         if (rc)
2107                 goto rel_out;
2108
2109         ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2110
2111         /* Commit the changes */
2112         rc = ixgbe_reset_phy_m88_nolock(hw);
2113         if (rc) {
2114                 DEBUGOUT("Error committing the PHY changes\n");
2115                 goto rel_out;
2116         }
2117
2118         rc = ixgbe_set_master_slave_mode(hw);
2119
2120         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2121         return rc;
2122
2123 rel_out:
2124         ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2125         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2126         return rc;
2127 }
2128
2129 /**
2130  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2131  *  @hw: pointer to hardware structure
2132  *
2133  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
2134  *  values.
2135  **/
2136 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2137 {
2138         /* Save NW management interface connected on board. This is used
2139          * to determine internal PHY mode.
2140          */
2141         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2142
2143         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2144          * PHY address. This register field was has only been used for X552.
2145          */
2146         if (hw->mac.type == ixgbe_mac_X550EM_a &&
2147             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2148                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2149                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2150                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2151         }
2152
2153         return IXGBE_SUCCESS;
2154 }
2155
2156 /**
2157  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2158  *  @hw: pointer to hardware structure
2159  *
2160  *  Initialize any function pointers that were not able to be
2161  *  set during init_shared_code because the PHY/SFP type was
2162  *  not known.  Perform the SFP init if necessary.
2163  */
2164 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2165 {
2166         struct ixgbe_phy_info *phy = &hw->phy;
2167         s32 ret_val;
2168
2169         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2170
2171         hw->mac.ops.set_lan_id(hw);
2172
2173         ixgbe_read_mng_if_sel_x550em(hw);
2174
2175         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2176                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2177                 ixgbe_setup_mux_ctl(hw);
2178                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2179         }
2180
2181         /* Identify the PHY or SFP module */
2182         ret_val = phy->ops.identify(hw);
2183         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2184                 return ret_val;
2185
2186         /* Setup function pointers based on detected hardware */
2187         ixgbe_init_mac_link_ops_X550em(hw);
2188         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2189                 phy->ops.reset = NULL;
2190
2191         /* Set functions pointers based on phy type */
2192         switch (hw->phy.type) {
2193         case ixgbe_phy_x550em_kx4:
2194                 phy->ops.setup_link = NULL;
2195                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2196                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2197                 break;
2198         case ixgbe_phy_x550em_kr:
2199                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2200                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2201                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2202                 break;
2203         case ixgbe_phy_x550em_ext_t:
2204                 /* If internal link mode is XFI, then setup iXFI internal link,
2205                  * else setup KR now.
2206                  */
2207                 phy->ops.setup_internal_link =
2208                                               ixgbe_setup_internal_phy_t_x550em;
2209
2210                 /* setup SW LPLU only for first revision of X550EM_x */
2211                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2212                     !(IXGBE_FUSES0_REV_MASK &
2213                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2214                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2215
2216                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2217                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2218                 break;
2219         case ixgbe_phy_sgmii:
2220                 phy->ops.setup_link = NULL;
2221                 break;
2222         case ixgbe_phy_m88:
2223                 phy->ops.setup_link = ixgbe_setup_m88;
2224                 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2225                 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2226                 phy->ops.reset = ixgbe_reset_phy_m88;
2227                 break;
2228         default:
2229                 break;
2230         }
2231         return ret_val;
2232 }
2233
2234 /**
2235  * ixgbe_set_mdio_speed - Set MDIO clock speed
2236  *  @hw: pointer to hardware structure
2237  */
2238 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2239 {
2240         u32 hlreg0;
2241
2242         switch (hw->device_id) {
2243         case IXGBE_DEV_ID_X550EM_X_10G_T:
2244         case IXGBE_DEV_ID_X550EM_A_SGMII:
2245         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2246         case IXGBE_DEV_ID_X550EM_A_1G_T:
2247         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2248         case IXGBE_DEV_ID_X550EM_A_10G_T:
2249         case IXGBE_DEV_ID_X550EM_A_SFP:
2250         case IXGBE_DEV_ID_X550EM_A_QSFP:
2251                 /* Config MDIO clock speed before the first MDIO PHY access */
2252                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2253                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2254                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2255                 break;
2256         default:
2257                 break;
2258         }
2259 }
2260
2261 /**
2262  *  ixgbe_reset_hw_X550em - Perform hardware reset
2263  *  @hw: pointer to hardware structure
2264  *
2265  *  Resets the hardware by resetting the transmit and receive units, masks
2266  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2267  *  reset.
2268  */
2269 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2270 {
2271         ixgbe_link_speed link_speed;
2272         s32 status;
2273         u32 ctrl = 0;
2274         u32 i;
2275         bool link_up = false;
2276
2277         DEBUGFUNC("ixgbe_reset_hw_X550em");
2278
2279         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2280         status = hw->mac.ops.stop_adapter(hw);
2281         if (status != IXGBE_SUCCESS)
2282                 return status;
2283
2284         /* flush pending Tx transactions */
2285         ixgbe_clear_tx_pending(hw);
2286
2287         ixgbe_set_mdio_speed(hw);
2288
2289         /* PHY ops must be identified and initialized prior to reset */
2290         status = hw->phy.ops.init(hw);
2291
2292         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2293                 return status;
2294
2295         /* start the external PHY */
2296         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2297                 status = ixgbe_init_ext_t_x550em(hw);
2298                 if (status)
2299                         return status;
2300         }
2301
2302         /* Setup SFP module if there is one present. */
2303         if (hw->phy.sfp_setup_needed) {
2304                 status = hw->mac.ops.setup_sfp(hw);
2305                 hw->phy.sfp_setup_needed = false;
2306         }
2307
2308         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2309                 return status;
2310
2311         /* Reset PHY */
2312         if (!hw->phy.reset_disable && hw->phy.ops.reset)
2313                 hw->phy.ops.reset(hw);
2314
2315 mac_reset_top:
2316         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2317          * If link reset is used when link is up, it might reset the PHY when
2318          * mng is using it.  If link is down or the flag to force full link
2319          * reset is set, then perform link reset.
2320          */
2321         ctrl = IXGBE_CTRL_LNK_RST;
2322         if (!hw->force_full_reset) {
2323                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2324                 if (link_up)
2325                         ctrl = IXGBE_CTRL_RST;
2326         }
2327
2328         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2329         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2330         IXGBE_WRITE_FLUSH(hw);
2331
2332         /* Poll for reset bit to self-clear meaning reset is complete */
2333         for (i = 0; i < 10; i++) {
2334                 usec_delay(1);
2335                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2336                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2337                         break;
2338         }
2339
2340         if (ctrl & IXGBE_CTRL_RST_MASK) {
2341                 status = IXGBE_ERR_RESET_FAILED;
2342                 DEBUGOUT("Reset polling failed to complete.\n");
2343         }
2344
2345         msec_delay(50);
2346
2347         /* Double resets are required for recovery from certain error
2348          * conditions.  Between resets, it is necessary to stall to
2349          * allow time for any pending HW events to complete.
2350          */
2351         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2352                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2353                 goto mac_reset_top;
2354         }
2355
2356         /* Store the permanent mac address */
2357         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2358
2359         /* Store MAC address from RAR0, clear receive address registers, and
2360          * clear the multicast table.  Also reset num_rar_entries to 128,
2361          * since we modify this value when programming the SAN MAC address.
2362          */
2363         hw->mac.num_rar_entries = 128;
2364         hw->mac.ops.init_rx_addrs(hw);
2365
2366         ixgbe_set_mdio_speed(hw);
2367
2368         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2369                 ixgbe_setup_mux_ctl(hw);
2370
2371         return status;
2372 }
2373
2374 /**
2375  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2376  * @hw: pointer to hardware structure
2377  */
2378 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2379 {
2380         u32 status;
2381         u16 reg;
2382
2383         status = hw->phy.ops.read_reg(hw,
2384                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2385                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2386                                       &reg);
2387
2388         if (status != IXGBE_SUCCESS)
2389                 return status;
2390
2391         /* If PHY FW reset completed bit is set then this is the first
2392          * SW instance after a power on so the PHY FW must be un-stalled.
2393          */
2394         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2395                 status = hw->phy.ops.read_reg(hw,
2396                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2397                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2398                                         &reg);
2399
2400                 if (status != IXGBE_SUCCESS)
2401                         return status;
2402
2403                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2404
2405                 status = hw->phy.ops.write_reg(hw,
2406                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2407                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2408                                         reg);
2409
2410                 if (status != IXGBE_SUCCESS)
2411                         return status;
2412         }
2413
2414         return status;
2415 }
2416
2417 /**
2418  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2419  *  @hw: pointer to hardware structure
2420  *
2421  *  Configures the integrated KR PHY for X550EM_x.
2422  **/
2423 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2424 {
2425         if (hw->mac.type != ixgbe_mac_X550EM_x)
2426                 return IXGBE_SUCCESS;
2427
2428         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2429 }
2430
2431 /**
2432  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2433  *  @hw: pointer to hardware structure
2434  *
2435  *  Configure the external PHY and the integrated KR PHY for SFP support.
2436  **/
2437 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2438                                     ixgbe_link_speed speed,
2439                                     bool autoneg_wait_to_complete)
2440 {
2441         s32 ret_val;
2442         u16 reg_slice, reg_val;
2443         bool setup_linear = false;
2444         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2445
2446         /* Check if SFP module is supported and linear */
2447         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2448
2449         /* If no SFP module present, then return success. Return success since
2450          * there is no reason to configure CS4227 and SFP not present error is
2451          * not excepted in the setup MAC link flow.
2452          */
2453         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2454                 return IXGBE_SUCCESS;
2455
2456         if (ret_val != IXGBE_SUCCESS)
2457                 return ret_val;
2458
2459         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2460                 /* Configure CS4227 LINE side to 10G SR. */
2461                 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2462                             (hw->bus.lan_id << 12);
2463                 reg_val = IXGBE_CS4227_SPEED_10G;
2464                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2465                                                   reg_val);
2466
2467                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2468                             (hw->bus.lan_id << 12);
2469                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2470                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2471                                                   reg_val);
2472
2473                 /* Configure CS4227 for HOST connection rate then type. */
2474                 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2475                             (hw->bus.lan_id << 12);
2476                 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2477                 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2478                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2479                                                   reg_val);
2480
2481                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2482                             (hw->bus.lan_id << 12);
2483                 if (setup_linear)
2484                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2485                 else
2486                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2487                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2488                                                   reg_val);
2489
2490                 /* Setup XFI internal link. */
2491                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2492         } else {
2493                 /* Configure internal PHY for KR/KX. */
2494                 ixgbe_setup_kr_speed_x550em(hw, speed);
2495
2496                 /* Configure CS4227 LINE side to proper mode. */
2497                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2498                             (hw->bus.lan_id << 12);
2499                 if (setup_linear)
2500                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2501                 else
2502                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2503                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2504                                                   reg_val);
2505         }
2506         return ret_val;
2507 }
2508
2509 /**
2510  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2511  *  @hw: pointer to hardware structure
2512  *
2513  *  Configure the the integrated PHY for SFP support.
2514  **/
2515 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2516                                    ixgbe_link_speed speed,
2517                                    bool autoneg_wait_to_complete)
2518 {
2519         s32 ret_val;
2520         u16 reg_phy_ext;
2521         bool setup_linear = false;
2522         u32 reg_slice, reg_phy_int, slice_offset;
2523
2524         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2525
2526         /* Check if SFP module is supported and linear */
2527         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2528
2529         /* If no SFP module present, then return success. Return success since
2530          * SFP not present error is not excepted in the setup MAC link flow.
2531          */
2532         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2533                 return IXGBE_SUCCESS;
2534
2535         if (ret_val != IXGBE_SUCCESS)
2536                 return ret_val;
2537
2538         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2539                 /* Configure internal PHY for native SFI */
2540                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2541                                IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2542                                IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
2543
2544                 if (ret_val != IXGBE_SUCCESS)
2545                         return ret_val;
2546
2547                 if (setup_linear) {
2548                         reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
2549                         reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;
2550                 } else {
2551                         reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;
2552                         reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
2553                 }
2554
2555                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2556                                 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2557                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2558
2559                 if (ret_val != IXGBE_SUCCESS)
2560                         return ret_val;
2561
2562                 /* Setup XFI/SFI internal link. */
2563                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2564         } else {
2565                 /* Configure internal PHY for KR/KX. */
2566                 ixgbe_setup_kr_speed_x550em(hw, speed);
2567
2568                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2569                         /* Find Address */
2570                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2571                         return IXGBE_ERR_PHY_ADDR_INVALID;
2572                 }
2573
2574                 /* Get external PHY device id */
2575                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
2576                                        IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2577
2578                 if (ret_val != IXGBE_SUCCESS)
2579                         return ret_val;
2580
2581                 /* When configuring quad port CS4223, the MAC instance is part
2582                  * of the slice offset.
2583                  */
2584                 if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
2585                         slice_offset = (hw->bus.lan_id +
2586                                         (hw->bus.instance_id << 1)) << 12;
2587                 else
2588                         slice_offset = hw->bus.lan_id << 12;
2589
2590                 /* Configure CS4227/CS4223 LINE side to proper mode. */
2591                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2592                 if (setup_linear)
2593                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2594                 else
2595                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2596                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2597                                         IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2598         }
2599         return ret_val;
2600 }
2601
2602 /**
2603  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2604  *  @hw: pointer to hardware structure
2605  *
2606  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2607  **/
2608 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2609 {
2610         s32 status;
2611         u32 reg_val;
2612
2613         /* Disable training protocol FSM. */
2614         status = ixgbe_read_iosf_sb_reg_x550(hw,
2615                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2616                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2617         if (status != IXGBE_SUCCESS)
2618                 return status;
2619         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2620         status = ixgbe_write_iosf_sb_reg_x550(hw,
2621                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2622                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2623         if (status != IXGBE_SUCCESS)
2624                 return status;
2625
2626         /* Disable Flex from training TXFFE. */
2627         status = ixgbe_read_iosf_sb_reg_x550(hw,
2628                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2629                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2630         if (status != IXGBE_SUCCESS)
2631                 return status;
2632         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2633         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2634         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2635         status = ixgbe_write_iosf_sb_reg_x550(hw,
2636                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2637                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2638         if (status != IXGBE_SUCCESS)
2639                 return status;
2640         status = ixgbe_read_iosf_sb_reg_x550(hw,
2641                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2642                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2643         if (status != IXGBE_SUCCESS)
2644                 return status;
2645         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2646         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2647         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2648         status = ixgbe_write_iosf_sb_reg_x550(hw,
2649                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2650                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2651         if (status != IXGBE_SUCCESS)
2652                 return status;
2653
2654         /* Enable override for coefficients. */
2655         status = ixgbe_read_iosf_sb_reg_x550(hw,
2656                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2657                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2658         if (status != IXGBE_SUCCESS)
2659                 return status;
2660         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2661         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2662         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2663         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2664         status = ixgbe_write_iosf_sb_reg_x550(hw,
2665                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2666                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2667         return status;
2668 }
2669
2670 /**
2671  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2672  *  @hw: pointer to hardware structure
2673  *  @speed: the link speed to force
2674  *
2675  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
2676  *  internal and external PHY at a specific speed, without autonegotiation.
2677  **/
2678 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2679 {
2680         s32 status;
2681         u32 reg_val;
2682
2683         /* Disable AN and force speed to 10G Serial. */
2684         status = ixgbe_read_iosf_sb_reg_x550(hw,
2685                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2686                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2687         if (status != IXGBE_SUCCESS)
2688                 return status;
2689
2690         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2691         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2692
2693         /* Select forced link speed for internal PHY. */
2694         switch (*speed) {
2695         case IXGBE_LINK_SPEED_10GB_FULL:
2696                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2697                 break;
2698         case IXGBE_LINK_SPEED_1GB_FULL:
2699                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2700                 break;
2701         default:
2702                 /* Other link speeds are not supported by internal KR PHY. */
2703                 return IXGBE_ERR_LINK_SETUP;
2704         }
2705
2706         status = ixgbe_write_iosf_sb_reg_x550(hw,
2707                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2708                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2709         if (status != IXGBE_SUCCESS)
2710                 return status;
2711
2712         /* Additional configuration needed for x550em_x */
2713         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2714                 status = ixgbe_setup_ixfi_x550em_x(hw);
2715                 if (status != IXGBE_SUCCESS)
2716                         return status;
2717         }
2718
2719         /* Toggle port SW reset by AN reset. */
2720         status = ixgbe_read_iosf_sb_reg_x550(hw,
2721                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2722                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2723         if (status != IXGBE_SUCCESS)
2724                 return status;
2725         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2726         status = ixgbe_write_iosf_sb_reg_x550(hw,
2727                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2728                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2729
2730         return status;
2731 }
2732
2733 /**
2734  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2735  * @hw: address of hardware structure
2736  * @link_up: address of boolean to indicate link status
2737  *
2738  * Returns error code if unable to get link status.
2739  */
2740 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2741 {
2742         u32 ret;
2743         u16 autoneg_status;
2744
2745         *link_up = false;
2746
2747         /* read this twice back to back to indicate current status */
2748         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2749                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2750                                    &autoneg_status);
2751         if (ret != IXGBE_SUCCESS)
2752                 return ret;
2753
2754         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2755                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2756                                    &autoneg_status);
2757         if (ret != IXGBE_SUCCESS)
2758                 return ret;
2759
2760         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2761
2762         return IXGBE_SUCCESS;
2763 }
2764
2765 /**
2766  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2767  * @hw: point to hardware structure
2768  *
2769  * Configures the link between the integrated KR PHY and the external X557 PHY
2770  * The driver will call this function when it gets a link status change
2771  * interrupt from the X557 PHY. This function configures the link speed
2772  * between the PHYs to match the link speed of the BASE-T link.
2773  *
2774  * A return of a non-zero value indicates an error, and the base driver should
2775  * not report link up.
2776  */
2777 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2778 {
2779         ixgbe_link_speed force_speed;
2780         bool link_up;
2781         u32 status;
2782         u16 speed;
2783
2784         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2785                 return IXGBE_ERR_CONFIG;
2786
2787         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2788                 /* If link is down, there is no setup necessary so return  */
2789                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2790                 if (status != IXGBE_SUCCESS)
2791                         return status;
2792
2793                 if (!link_up)
2794                         return IXGBE_SUCCESS;
2795
2796                 status = hw->phy.ops.read_reg(hw,
2797                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2798                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2799                                               &speed);
2800                 if (status != IXGBE_SUCCESS)
2801                         return status;
2802
2803                 /* If link is still down - no setup is required so return */
2804                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2805                 if (status != IXGBE_SUCCESS)
2806                         return status;
2807                 if (!link_up)
2808                         return IXGBE_SUCCESS;
2809
2810                 /* clear everything but the speed and duplex bits */
2811                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2812
2813                 switch (speed) {
2814                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2815                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2816                         break;
2817                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2818                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2819                         break;
2820                 default:
2821                         /* Internal PHY does not support anything else */
2822                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
2823                 }
2824
2825                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2826         } else {
2827                 speed = IXGBE_LINK_SPEED_10GB_FULL |
2828                         IXGBE_LINK_SPEED_1GB_FULL;
2829                 return ixgbe_setup_kr_speed_x550em(hw, speed);
2830         }
2831 }
2832
2833 /**
2834  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2835  *  @hw: pointer to hardware structure
2836  *
2837  *  Configures the integrated KR PHY to use internal loopback mode.
2838  **/
2839 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2840 {
2841         s32 status;
2842         u32 reg_val;
2843
2844         /* Disable AN and force speed to 10G Serial. */
2845         status = hw->mac.ops.read_iosf_sb_reg(hw,
2846                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2847                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2848         if (status != IXGBE_SUCCESS)
2849                 return status;
2850         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2851         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2852         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2853         status = hw->mac.ops.write_iosf_sb_reg(hw,
2854                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2855                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2856         if (status != IXGBE_SUCCESS)
2857                 return status;
2858
2859         /* Set near-end loopback clocks. */
2860         status = hw->mac.ops.read_iosf_sb_reg(hw,
2861                       IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2862                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2863         if (status != IXGBE_SUCCESS)
2864                 return status;
2865         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2866         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2867         status = hw->mac.ops.write_iosf_sb_reg(hw,
2868                        IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2869                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2870         if (status != IXGBE_SUCCESS)
2871                 return status;
2872
2873         /* Set loopback enable. */
2874         status = hw->mac.ops.read_iosf_sb_reg(hw,
2875                       IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2876                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2877         if (status != IXGBE_SUCCESS)
2878                 return status;
2879         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2880         status = hw->mac.ops.write_iosf_sb_reg(hw,
2881                        IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2882                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2883         if (status != IXGBE_SUCCESS)
2884                 return status;
2885
2886         /* Training bypass. */
2887         status = hw->mac.ops.read_iosf_sb_reg(hw,
2888                       IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2889                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2890         if (status != IXGBE_SUCCESS)
2891                 return status;
2892         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2893         status = hw->mac.ops.write_iosf_sb_reg(hw,
2894                        IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2895                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2896
2897         return status;
2898 }
2899
2900 /**
2901  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2902  *  assuming that the semaphore is already obtained.
2903  *  @hw: pointer to hardware structure
2904  *  @offset: offset of  word in the EEPROM to read
2905  *  @data: word read from the EEPROM
2906  *
2907  *  Reads a 16 bit word from the EEPROM using the hostif.
2908  **/
2909 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2910                                    u16 *data)
2911 {
2912         s32 status;
2913         struct ixgbe_hic_read_shadow_ram buffer;
2914
2915         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2916         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2917         buffer.hdr.req.buf_lenh = 0;
2918         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2919         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2920
2921         /* convert offset from words to bytes */
2922         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2923         /* one word */
2924         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2925
2926         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2927                                               sizeof(buffer),
2928                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2929
2930         if (status)
2931                 return status;
2932
2933         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2934                                           FW_NVM_DATA_OFFSET);
2935
2936         return 0;
2937 }
2938
2939 /**
2940  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2941  *  @hw: pointer to hardware structure
2942  *  @offset: offset of  word in the EEPROM to read
2943  *  @data: word read from the EEPROM
2944  *
2945  *  Reads a 16 bit word from the EEPROM using the hostif.
2946  **/
2947 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2948                               u16 *data)
2949 {
2950         s32 status = IXGBE_SUCCESS;
2951
2952         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2953
2954         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2955             IXGBE_SUCCESS) {
2956                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2957                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2958         } else {
2959                 status = IXGBE_ERR_SWFW_SYNC;
2960         }
2961
2962         return status;
2963 }
2964
2965 /**
2966  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2967  *  @hw: pointer to hardware structure
2968  *  @offset: offset of  word in the EEPROM to read
2969  *  @words: number of words
2970  *  @data: word(s) read from the EEPROM
2971  *
2972  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
2973  **/
2974 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2975                                      u16 offset, u16 words, u16 *data)
2976 {
2977         struct ixgbe_hic_read_shadow_ram buffer;
2978         u32 current_word = 0;
2979         u16 words_to_read;
2980         s32 status;
2981         u32 i;
2982
2983         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2984
2985         /* Take semaphore for the entire operation. */
2986         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2987         if (status) {
2988                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2989                 return status;
2990         }
2991         while (words) {
2992                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2993                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2994                 else
2995                         words_to_read = words;
2996
2997                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2998                 buffer.hdr.req.buf_lenh = 0;
2999                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3000                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3001
3002                 /* convert offset from words to bytes */
3003                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3004                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3005
3006                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3007                                                       sizeof(buffer),
3008                                                       IXGBE_HI_COMMAND_TIMEOUT,
3009                                                       false);
3010
3011                 if (status) {
3012                         DEBUGOUT("Host interface command failed\n");
3013                         goto out;
3014                 }
3015
3016                 for (i = 0; i < words_to_read; i++) {
3017                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3018                                   2 * i;
3019                         u32 value = IXGBE_READ_REG(hw, reg);
3020
3021                         data[current_word] = (u16)(value & 0xffff);
3022                         current_word++;
3023                         i++;
3024                         if (i < words_to_read) {
3025                                 value >>= 16;
3026                                 data[current_word] = (u16)(value & 0xffff);
3027                                 current_word++;
3028                         }
3029                 }
3030                 words -= words_to_read;
3031         }
3032
3033 out:
3034         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3035         return status;
3036 }
3037
3038 /**
3039  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3040  *  @hw: pointer to hardware structure
3041  *  @offset: offset of  word in the EEPROM to write
3042  *  @data: word write to the EEPROM
3043  *
3044  *  Write a 16 bit word to the EEPROM using the hostif.
3045  **/
3046 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3047                                     u16 data)
3048 {
3049         s32 status;
3050         struct ixgbe_hic_write_shadow_ram buffer;
3051
3052         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3053
3054         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3055         buffer.hdr.req.buf_lenh = 0;
3056         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3057         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3058
3059          /* one word */
3060         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3061         buffer.data = data;
3062         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3063
3064         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3065                                               sizeof(buffer),
3066                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3067
3068         return status;
3069 }
3070
3071 /**
3072  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3073  *  @hw: pointer to hardware structure
3074  *  @offset: offset of  word in the EEPROM to write
3075  *  @data: word write to the EEPROM
3076  *
3077  *  Write a 16 bit word to the EEPROM using the hostif.
3078  **/
3079 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3080                                u16 data)
3081 {
3082         s32 status = IXGBE_SUCCESS;
3083
3084         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3085
3086         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3087             IXGBE_SUCCESS) {
3088                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3089                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3090         } else {
3091                 DEBUGOUT("write ee hostif failed to get semaphore");
3092                 status = IXGBE_ERR_SWFW_SYNC;
3093         }
3094
3095         return status;
3096 }
3097
3098 /**
3099  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3100  *  @hw: pointer to hardware structure
3101  *  @offset: offset of  word in the EEPROM to write
3102  *  @words: number of words
3103  *  @data: word(s) write to the EEPROM
3104  *
3105  *  Write a 16 bit word(s) to the EEPROM using the hostif.
3106  **/
3107 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3108                                       u16 offset, u16 words, u16 *data)
3109 {
3110         s32 status = IXGBE_SUCCESS;
3111         u32 i = 0;
3112
3113         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3114
3115         /* Take semaphore for the entire operation. */
3116         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3117         if (status != IXGBE_SUCCESS) {
3118                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3119                 goto out;
3120         }
3121
3122         for (i = 0; i < words; i++) {
3123                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3124                                                          data[i]);
3125
3126                 if (status != IXGBE_SUCCESS) {
3127                         DEBUGOUT("Eeprom buffered write failed\n");
3128                         break;
3129                 }
3130         }
3131
3132         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3133 out:
3134
3135         return status;
3136 }
3137
3138 /**
3139  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3140  * @hw: pointer to hardware structure
3141  * @ptr: pointer offset in eeprom
3142  * @size: size of section pointed by ptr, if 0 first word will be used as size
3143  * @csum: address of checksum to update
3144  *
3145  * Returns error status for any failure
3146  */
3147 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3148                                    u16 size, u16 *csum, u16 *buffer,
3149                                    u32 buffer_size)
3150 {
3151         u16 buf[256];
3152         s32 status;
3153         u16 length, bufsz, i, start;
3154         u16 *local_buffer;
3155
3156         bufsz = sizeof(buf) / sizeof(buf[0]);
3157
3158         /* Read a chunk at the pointer location */
3159         if (!buffer) {
3160                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3161                 if (status) {
3162                         DEBUGOUT("Failed to read EEPROM image\n");
3163                         return status;
3164                 }
3165                 local_buffer = buf;
3166         } else {
3167                 if (buffer_size < ptr)
3168                         return  IXGBE_ERR_PARAM;
3169                 local_buffer = &buffer[ptr];
3170         }
3171
3172         if (size) {
3173                 start = 0;
3174                 length = size;
3175         } else {
3176                 start = 1;
3177                 length = local_buffer[0];
3178
3179                 /* Skip pointer section if length is invalid. */
3180                 if (length == 0xFFFF || length == 0 ||
3181                     (ptr + length) >= hw->eeprom.word_size)
3182                         return IXGBE_SUCCESS;
3183         }
3184
3185         if (buffer && ((u32)start + (u32)length > buffer_size))
3186                 return IXGBE_ERR_PARAM;
3187
3188         for (i = start; length; i++, length--) {
3189                 if (i == bufsz && !buffer) {
3190                         ptr += bufsz;
3191                         i = 0;
3192                         if (length < bufsz)
3193                                 bufsz = length;
3194
3195                         /* Read a chunk at the pointer location */
3196                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3197                                                                   bufsz, buf);
3198                         if (status) {
3199                                 DEBUGOUT("Failed to read EEPROM image\n");
3200                                 return status;
3201                         }
3202                 }
3203                 *csum += local_buffer[i];
3204         }
3205         return IXGBE_SUCCESS;
3206 }
3207
3208 /**
3209  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3210  *  @hw: pointer to hardware structure
3211  *  @buffer: pointer to buffer containing calculated checksum
3212  *  @buffer_size: size of buffer
3213  *
3214  *  Returns a negative error code on error, or the 16-bit checksum
3215  **/
3216 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3217 {
3218         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3219         u16 *local_buffer;
3220         s32 status;
3221         u16 checksum = 0;
3222         u16 pointer, i, size;
3223
3224         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3225
3226         hw->eeprom.ops.init_params(hw);
3227
3228         if (!buffer) {
3229                 /* Read pointer area */
3230                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3231                                                      IXGBE_EEPROM_LAST_WORD + 1,
3232                                                      eeprom_ptrs);
3233                 if (status) {
3234                         DEBUGOUT("Failed to read EEPROM image\n");
3235                         return status;
3236                 }
3237                 local_buffer = eeprom_ptrs;
3238         } else {
3239                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3240                         return IXGBE_ERR_PARAM;
3241                 local_buffer = buffer;
3242         }
3243
3244         /*
3245          * For X550 hardware include 0x0-0x41 in the checksum, skip the
3246          * checksum word itself
3247          */
3248         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3249                 if (i != IXGBE_EEPROM_CHECKSUM)
3250                         checksum += local_buffer[i];
3251
3252         /*
3253          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
3254          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3255          */
3256         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3257                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3258                         continue;
3259
3260                 pointer = local_buffer[i];
3261
3262                 /* Skip pointer section if the pointer is invalid. */
3263                 if (pointer == 0xFFFF || pointer == 0 ||
3264                     pointer >= hw->eeprom.word_size)
3265                         continue;
3266
3267                 switch (i) {
3268                 case IXGBE_PCIE_GENERAL_PTR:
3269                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3270                         break;
3271                 case IXGBE_PCIE_CONFIG0_PTR:
3272                 case IXGBE_PCIE_CONFIG1_PTR:
3273                         size = IXGBE_PCIE_CONFIG_SIZE;
3274                         break;
3275                 default:
3276                         size = 0;
3277                         break;
3278                 }
3279
3280                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3281                                                 buffer, buffer_size);
3282                 if (status)
3283                         return status;
3284         }
3285
3286         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3287
3288         return (s32)checksum;
3289 }
3290
3291 /**
3292  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3293  *  @hw: pointer to hardware structure
3294  *
3295  *  Returns a negative error code on error, or the 16-bit checksum
3296  **/
3297 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3298 {
3299         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3300 }
3301
3302 /**
3303  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3304  *  @hw: pointer to hardware structure
3305  *  @checksum_val: calculated checksum
3306  *
3307  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3308  *  caller does not need checksum_val, the value can be NULL.
3309  **/
3310 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3311 {
3312         s32 status;
3313         u16 checksum;
3314         u16 read_checksum = 0;
3315
3316         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3317
3318         /* Read the first word from the EEPROM. If this times out or fails, do
3319          * not continue or we could be in for a very long wait while every
3320          * EEPROM read fails
3321          */
3322         status = hw->eeprom.ops.read(hw, 0, &checksum);
3323         if (status) {
3324                 DEBUGOUT("EEPROM read failed\n");
3325                 return status;
3326         }
3327
3328         status = hw->eeprom.ops.calc_checksum(hw);
3329         if (status < 0)
3330                 return status;
3331
3332         checksum = (u16)(status & 0xffff);
3333
3334         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3335                                            &read_checksum);
3336         if (status)
3337                 return status;
3338
3339         /* Verify read checksum from EEPROM is the same as
3340          * calculated checksum
3341          */
3342         if (read_checksum != checksum) {
3343                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3344                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3345                              "Invalid EEPROM checksum");
3346         }
3347
3348         /* If the user cares, return the calculated checksum */
3349         if (checksum_val)
3350                 *checksum_val = checksum;
3351
3352         return status;
3353 }
3354
3355 /**
3356  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3357  * @hw: pointer to hardware structure
3358  *
3359  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3360  * checksum and updates the EEPROM and instructs the hardware to update
3361  * the flash.
3362  **/
3363 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3364 {
3365         s32 status;
3366         u16 checksum = 0;
3367
3368         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3369
3370         /* Read the first word from the EEPROM. If this times out or fails, do
3371          * not continue or we could be in for a very long wait while every
3372          * EEPROM read fails
3373          */
3374         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3375         if (status) {
3376                 DEBUGOUT("EEPROM read failed\n");
3377                 return status;
3378         }
3379
3380         status = ixgbe_calc_eeprom_checksum_X550(hw);
3381         if (status < 0)
3382                 return status;
3383
3384         checksum = (u16)(status & 0xffff);
3385
3386         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3387                                             checksum);
3388         if (status)
3389                 return status;
3390
3391         status = ixgbe_update_flash_X550(hw);
3392
3393         return status;
3394 }
3395
3396 /**
3397  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3398  *  @hw: pointer to hardware structure
3399  *
3400  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3401  **/
3402 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3403 {
3404         s32 status = IXGBE_SUCCESS;
3405         union ixgbe_hic_hdr2 buffer;
3406
3407         DEBUGFUNC("ixgbe_update_flash_X550");
3408
3409         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3410         buffer.req.buf_lenh = 0;
3411         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3412         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3413
3414         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3415                                               sizeof(buffer),
3416                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3417
3418         return status;
3419 }
3420
3421 /**
3422  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3423  *  @hw: pointer to hardware structure
3424  *
3425  *  Determines physical layer capabilities of the current configuration.
3426  **/
3427 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3428 {
3429         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3430         u16 ext_ability = 0;
3431
3432         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3433
3434         hw->phy.ops.identify(hw);
3435
3436         switch (hw->phy.type) {
3437         case ixgbe_phy_x550em_kr:
3438                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3439                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3440                 break;
3441         case ixgbe_phy_x550em_kx4:
3442                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3443                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3444                 break;
3445         case ixgbe_phy_x550em_ext_t:
3446                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3447                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3448                                      &ext_ability);
3449                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3450                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3451                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3452                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3453                 break;
3454         default:
3455                 break;
3456         }
3457
3458         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3459                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3460
3461         return physical_layer;
3462 }
3463
3464 /**
3465  * ixgbe_get_bus_info_x550em - Set PCI bus info
3466  * @hw: pointer to hardware structure
3467  *
3468  * Sets bus link width and speed to unknown because X550em is
3469  * not a PCI device.
3470  **/
3471 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3472 {
3473
3474         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3475
3476         hw->bus.width = ixgbe_bus_width_unknown;
3477         hw->bus.speed = ixgbe_bus_speed_unknown;
3478
3479         hw->mac.ops.set_lan_id(hw);
3480
3481         return IXGBE_SUCCESS;
3482 }
3483
3484 /**
3485  * ixgbe_disable_rx_x550 - Disable RX unit
3486  *
3487  * Enables the Rx DMA unit for x550
3488  **/
3489 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3490 {
3491         u32 rxctrl, pfdtxgswc;
3492         s32 status;
3493         struct ixgbe_hic_disable_rxen fw_cmd;
3494
3495         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3496
3497         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3498         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3499                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3500                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3501                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3502                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3503                         hw->mac.set_lben = true;
3504                 } else {
3505                         hw->mac.set_lben = false;
3506                 }
3507
3508                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3509                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3510                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3511                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3512
3513                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3514                                         sizeof(struct ixgbe_hic_disable_rxen),
3515                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3516
3517                 /* If we fail - disable RX using register write */
3518                 if (status) {
3519                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3520                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3521                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3522                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3523                         }
3524                 }
3525         }
3526 }
3527
3528 /**
3529  * ixgbe_enter_lplu_x550em - Transition to low power states
3530  *  @hw: pointer to hardware structure
3531  *
3532  * Configures Low Power Link Up on transition to low power states
3533  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3534  * X557 PHY immediately prior to entering LPLU.
3535  **/
3536 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3537 {
3538         u16 an_10g_cntl_reg, autoneg_reg, speed;
3539         s32 status;
3540         ixgbe_link_speed lcd_speed;
3541         u32 save_autoneg;
3542         bool link_up;
3543
3544         /* SW LPLU not required on later HW revisions. */
3545         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3546             (IXGBE_FUSES0_REV_MASK &
3547              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3548                 return IXGBE_SUCCESS;
3549
3550         /* If blocked by MNG FW, then don't restart AN */
3551         if (ixgbe_check_reset_blocked(hw))
3552                 return IXGBE_SUCCESS;
3553
3554         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3555         if (status != IXGBE_SUCCESS)
3556                 return status;
3557
3558         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3559
3560         if (status != IXGBE_SUCCESS)
3561                 return status;
3562
3563         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3564          * disabled, then force link down by entering low power mode.
3565          */
3566         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3567             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3568                 return ixgbe_set_copper_phy_power(hw, FALSE);
3569
3570         /* Determine LCD */
3571         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3572
3573         if (status != IXGBE_SUCCESS)
3574                 return status;
3575
3576         /* If no valid LCD link speed, then force link down and exit. */
3577         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3578                 return ixgbe_set_copper_phy_power(hw, FALSE);
3579
3580         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3581                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3582                                       &speed);
3583
3584         if (status != IXGBE_SUCCESS)
3585                 return status;
3586
3587         /* If no link now, speed is invalid so take link down */
3588         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3589         if (status != IXGBE_SUCCESS)
3590                 return ixgbe_set_copper_phy_power(hw, false);
3591
3592         /* clear everything but the speed bits */
3593         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3594
3595         /* If current speed is already LCD, then exit. */
3596         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3597              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3598             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3599              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3600                 return status;
3601
3602         /* Clear AN completed indication */
3603         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3604                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3605                                       &autoneg_reg);
3606
3607         if (status != IXGBE_SUCCESS)
3608                 return status;
3609
3610         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3611                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3612                              &an_10g_cntl_reg);
3613
3614         if (status != IXGBE_SUCCESS)
3615                 return status;
3616
3617         status = hw->phy.ops.read_reg(hw,
3618                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3619                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3620                              &autoneg_reg);
3621
3622         if (status != IXGBE_SUCCESS)
3623                 return status;
3624
3625         save_autoneg = hw->phy.autoneg_advertised;
3626
3627         /* Setup link at least common link speed */
3628         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3629
3630         /* restore autoneg from before setting lplu speed */
3631         hw->phy.autoneg_advertised = save_autoneg;
3632
3633         return status;
3634 }
3635
3636 /**
3637  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3638  *  @hw: pointer to hardware structure
3639  *  @lcd_speed: pointer to lowest common link speed
3640  *
3641  * Determine lowest common link speed with link partner.
3642  **/
3643 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3644 {
3645         u16 an_lp_status;
3646         s32 status;
3647         u16 word = hw->eeprom.ctrl_word_3;
3648
3649         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3650
3651         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3652                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3653                                       &an_lp_status);
3654
3655         if (status != IXGBE_SUCCESS)
3656                 return status;
3657
3658         /* If link partner advertised 1G, return 1G */
3659         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3660                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3661                 return status;
3662         }
3663
3664         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3665         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3666             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3667                 return status;
3668
3669         /* Link partner not capable of lower speeds, return 10G */
3670         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3671         return status;
3672 }
3673
3674 /**
3675  *  ixgbe_setup_fc_X550em - Set up flow control
3676  *  @hw: pointer to hardware structure
3677  *
3678  *  Called at init time to set up flow control.
3679  **/
3680 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3681 {
3682         s32 ret_val = IXGBE_SUCCESS;
3683         u32 pause, asm_dir, reg_val;
3684
3685         DEBUGFUNC("ixgbe_setup_fc_X550em");
3686
3687         /* Validate the requested mode */
3688         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3689                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3690                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3691                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3692                 goto out;
3693         }
3694
3695         /* 10gig parts do not have a word in the EEPROM to determine the
3696          * default flow control setting, so we explicitly set it to full.
3697          */
3698         if (hw->fc.requested_mode == ixgbe_fc_default)
3699                 hw->fc.requested_mode = ixgbe_fc_full;
3700
3701         /* Determine PAUSE and ASM_DIR bits. */
3702         switch (hw->fc.requested_mode) {
3703         case ixgbe_fc_none:
3704                 pause = 0;
3705                 asm_dir = 0;
3706                 break;
3707         case ixgbe_fc_tx_pause:
3708                 pause = 0;
3709                 asm_dir = 1;
3710                 break;
3711         case ixgbe_fc_rx_pause:
3712                 /* Rx Flow control is enabled and Tx Flow control is
3713                  * disabled by software override. Since there really
3714                  * isn't a way to advertise that we are capable of RX
3715                  * Pause ONLY, we will advertise that we support both
3716                  * symmetric and asymmetric Rx PAUSE, as such we fall
3717                  * through to the fc_full statement.  Later, we will
3718                  * disable the adapter's ability to send PAUSE frames.
3719                  */
3720         case ixgbe_fc_full:
3721                 pause = 1;
3722                 asm_dir = 1;
3723                 break;
3724         default:
3725                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3726                         "Flow control param set incorrectly\n");
3727                 ret_val = IXGBE_ERR_CONFIG;
3728                 goto out;
3729         }
3730
3731         switch (hw->device_id) {
3732         case IXGBE_DEV_ID_X550EM_X_KR:
3733         case IXGBE_DEV_ID_X550EM_A_KR:
3734         case IXGBE_DEV_ID_X550EM_A_KR_L:
3735                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3736                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3737                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3738                 if (ret_val != IXGBE_SUCCESS)
3739                         goto out;
3740                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3741                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3742                 if (pause)
3743                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3744                 if (asm_dir)
3745                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3746                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3747                                        IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3748                                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3749
3750                 /* This device does not fully support AN. */
3751                 hw->fc.disable_fc_autoneg = true;
3752                 break;
3753         default:
3754                 break;
3755         }
3756
3757 out:
3758         return ret_val;
3759 }
3760
3761 /**
3762  * ixgbe_set_mux - Set mux for port 1 access with CS4227
3763  * @hw: pointer to hardware structure
3764  * @state: set mux if 1, clear if 0
3765  */
3766 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3767 {
3768         u32 esdp;
3769
3770         if (!hw->bus.lan_id)
3771                 return;
3772         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3773         if (state)
3774                 esdp |= IXGBE_ESDP_SDP1;
3775         else
3776                 esdp &= ~IXGBE_ESDP_SDP1;
3777         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3778         IXGBE_WRITE_FLUSH(hw);
3779 }
3780
3781 /**
3782  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3783  *  @hw: pointer to hardware structure
3784  *  @mask: Mask to specify which semaphore to acquire
3785  *
3786  *  Acquires the SWFW semaphore and sets the I2C MUX
3787  **/
3788 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3789 {
3790         s32 status;
3791
3792         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
3793
3794         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3795         if (status)
3796                 return status;
3797
3798         if (mask & IXGBE_GSSR_I2C_MASK)
3799                 ixgbe_set_mux(hw, 1);
3800
3801         return IXGBE_SUCCESS;
3802 }
3803
3804 /**
3805  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3806  *  @hw: pointer to hardware structure
3807  *  @mask: Mask to specify which semaphore to release
3808  *
3809  *  Releases the SWFW semaphore and sets the I2C MUX
3810  **/
3811 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3812 {
3813         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
3814
3815         if (mask & IXGBE_GSSR_I2C_MASK)
3816                 ixgbe_set_mux(hw, 0);
3817
3818         ixgbe_release_swfw_sync_X540(hw, mask);
3819 }
3820
3821 /**
3822  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
3823  *  @hw: pointer to hardware structure
3824  *  @mask: Mask to specify which semaphore to acquire
3825  *
3826  *  Acquires the SWFW semaphore and get the shared phy token as needed
3827  */
3828 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3829 {
3830         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3831         int retries = FW_PHY_TOKEN_RETRIES;
3832         s32 status = IXGBE_SUCCESS;
3833
3834         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
3835
3836         while (--retries) {
3837                 status = IXGBE_SUCCESS;
3838                 if (hmask)
3839                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3840                 if (status)
3841                         return status;
3842                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3843                         return IXGBE_SUCCESS;
3844
3845                 status = ixgbe_get_phy_token(hw);
3846                 if (status == IXGBE_SUCCESS)
3847                         return IXGBE_SUCCESS;
3848
3849                 if (hmask)
3850                         ixgbe_release_swfw_sync_X540(hw, hmask);
3851                 if (status != IXGBE_ERR_TOKEN_RETRY)
3852                         return status;
3853                 msec_delay(FW_PHY_TOKEN_DELAY);
3854         }
3855
3856         return status;
3857 }
3858
3859 /**
3860  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
3861  *  @hw: pointer to hardware structure
3862  *  @mask: Mask to specify which semaphore to release
3863  *
3864  *  Releases the SWFW semaphore and puts the shared phy token as needed
3865  */
3866 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3867 {
3868         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3869
3870         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
3871
3872         if (mask & IXGBE_GSSR_TOKEN_SM)
3873                 ixgbe_put_phy_token(hw);
3874
3875         if (hmask)
3876                 ixgbe_release_swfw_sync_X540(hw, hmask);
3877 }
3878
3879 /**
3880  *  ixgbe_read_phy_reg_x550a  - Reads specified PHY register
3881  *  @hw: pointer to hardware structure
3882  *  @reg_addr: 32 bit address of PHY register to read
3883  *  @phy_data: Pointer to read data from PHY register
3884  *
3885  *  Reads a value from a specified PHY register using the SWFW lock and PHY
3886  *  Token. The PHY Token is needed since the MDIO is shared between to MAC
3887  *  instances.
3888  **/
3889 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3890                              u32 device_type, u16 *phy_data)
3891 {
3892         s32 status;
3893         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3894
3895         DEBUGFUNC("ixgbe_read_phy_reg_x550a");
3896
3897         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
3898                 return IXGBE_ERR_SWFW_SYNC;
3899
3900         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
3901
3902         hw->mac.ops.release_swfw_sync(hw, mask);
3903
3904         return status;
3905 }
3906
3907 /**
3908  *  ixgbe_write_phy_reg_x550a - Writes specified PHY register
3909  *  @hw: pointer to hardware structure
3910  *  @reg_addr: 32 bit PHY register to write
3911  *  @device_type: 5 bit device type
3912  *  @phy_data: Data to write to the PHY register
3913  *
3914  *  Writes a value to specified PHY register using the SWFW lock and PHY Token.
3915  *  The PHY Token is needed since the MDIO is shared between to MAC instances.
3916  **/
3917 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3918                               u32 device_type, u16 phy_data)
3919 {
3920         s32 status;
3921         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3922
3923         DEBUGFUNC("ixgbe_write_phy_reg_x550a");
3924
3925         if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
3926                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
3927                                                  phy_data);
3928                 hw->mac.ops.release_swfw_sync(hw, mask);
3929         } else {
3930                 status = IXGBE_ERR_SWFW_SYNC;
3931         }
3932
3933         return status;
3934 }
3935
3936 /**
3937  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
3938  * @hw: pointer to hardware structure
3939  *
3940  * Handle external Base T PHY interrupt. If high temperature
3941  * failure alarm then return error, else if link status change
3942  * then setup internal/external PHY link
3943  *
3944  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
3945  * failure alarm, else return PHY access status.
3946  */
3947 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
3948 {
3949         bool lsc;
3950         u32 status;
3951
3952         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
3953
3954         if (status != IXGBE_SUCCESS)
3955                 return status;
3956
3957         if (lsc)
3958                 return ixgbe_setup_internal_phy(hw);
3959
3960         return IXGBE_SUCCESS;
3961 }
3962
3963 /**
3964  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
3965  * @hw: pointer to hardware structure
3966  * @speed: new link speed
3967  * @autoneg_wait_to_complete: true when waiting for completion is needed
3968  *
3969  * Setup internal/external PHY link speed based on link speed, then set
3970  * external PHY auto advertised link speed.
3971  *
3972  * Returns error status for any failure
3973  **/
3974 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3975                                   ixgbe_link_speed speed,
3976                                   bool autoneg_wait_to_complete)
3977 {
3978         s32 status;
3979         ixgbe_link_speed force_speed;
3980
3981         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3982
3983         /* Setup internal/external PHY link speed to iXFI (10G), unless
3984          * only 1G is auto advertised then setup KX link.
3985          */
3986         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3987                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3988         else
3989                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3990
3991         /* If internal link mode is XFI, then setup XFI internal link. */
3992         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3993                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3994
3995                 if (status != IXGBE_SUCCESS)
3996                         return status;
3997         }
3998
3999         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4000 }
4001
4002 /**
4003  * ixgbe_check_link_t_X550em - Determine link and speed status
4004  * @hw: pointer to hardware structure
4005  * @speed: pointer to link speed
4006  * @link_up: true when link is up
4007  * @link_up_wait_to_complete: bool used to wait for link up or not
4008  *
4009  * Check that both the MAC and X557 external PHY have link.
4010  **/
4011 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4012                               bool *link_up, bool link_up_wait_to_complete)
4013 {
4014         u32 status;
4015         u16 autoneg_status;
4016
4017         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4018                 return IXGBE_ERR_CONFIG;
4019
4020         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4021                                               link_up_wait_to_complete);
4022
4023         /* If check link fails or MAC link is not up, then return */
4024         if (status != IXGBE_SUCCESS || !(*link_up))
4025                 return status;
4026
4027         /* MAC link is up, so check external PHY link.
4028          * Read this twice back to back to indicate current status.
4029          */
4030         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4031                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4032                                       &autoneg_status);
4033
4034         if (status != IXGBE_SUCCESS)
4035                 return status;
4036
4037         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4038                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4039                                       &autoneg_status);
4040
4041         if (status != IXGBE_SUCCESS)
4042                 return status;
4043
4044         /* If external PHY link is not up, then indicate link not up */
4045         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4046                 *link_up = false;
4047
4048         return IXGBE_SUCCESS;
4049 }
4050
4051 /**
4052  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4053  *  @hw: pointer to hardware structure
4054  **/
4055 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4056 {
4057         s32 status;
4058
4059         status = ixgbe_reset_phy_generic(hw);
4060
4061         if (status != IXGBE_SUCCESS)
4062                 return status;
4063
4064         /* Configure Link Status Alarm and Temperature Threshold interrupts */
4065         return ixgbe_enable_lasi_ext_t_x550em(hw);
4066 }
4067
4068 /**
4069  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4070  *  @hw: pointer to hardware structure
4071  *  @led_idx: led number to turn on
4072  **/
4073 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4074 {
4075         u16 phy_data;
4076
4077         DEBUGFUNC("ixgbe_led_on_t_X550em");
4078
4079         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4080                 return IXGBE_ERR_PARAM;
4081
4082         /* To turn on the LED, set mode to ON. */
4083         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4084                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4085         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4086         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4087                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4088
4089         return IXGBE_SUCCESS;
4090 }
4091
4092 /**
4093  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4094  *  @hw: pointer to hardware structure
4095  *  @led_idx: led number to turn off
4096  **/
4097 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4098 {
4099         u16 phy_data;
4100
4101         DEBUGFUNC("ixgbe_led_off_t_X550em");
4102
4103         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4104                 return IXGBE_ERR_PARAM;
4105
4106         /* To turn on the LED, set mode to ON. */
4107         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4108                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4109         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4110         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4111                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4112
4113         return IXGBE_SUCCESS;
4114 }
4115