drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41
  42 /**
  43  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  44  *  @hw: pointer to hardware structure
  45  *
  46  *  Initialize the function pointers and assign the MAC type for X550.
  47  *  Does not touch the hardware.
  48  **/
  49 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  50 {
  51         struct ixgbe_mac_info *mac = &hw->mac;
  52         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  53         s32 ret_val;
  54
  55         DEBUGFUNC("ixgbe_init_ops_X550");
  56
  57         ret_val = ixgbe_init_ops_X540(hw);
  58         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  59         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  60         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  61         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  62         mac->ops.set_source_address_pruning =
  63                         ixgbe_set_source_address_pruning_X550;
  64         mac->ops.set_ethertype_anti_spoofing =
  65                         ixgbe_set_ethertype_anti_spoofing_X550;
  66
  67         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  68         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  69         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  70         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  71         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  72         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  73         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  74         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  75         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  76
  77         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  78         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  79         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  80         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  81         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  82         return ret_val;
  83 }
  84
  85 /**
  86  * ixgbe_read_cs4227 - Read CS4227 register
  87  * @hw: pointer to hardware structure
  88  * @reg: register number to write
  89  * @value: pointer to receive value read
  90  *
  91  * Returns status code
  92  **/
  93 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  94 {
  95         return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
  96 }
  97
  98 /**
  99  * ixgbe_write_cs4227 - Write CS4227 register
 100  * @hw: pointer to hardware structure
 101  * @reg: register number to write
 102  * @value: value to write to register
 103  *
 104  * Returns status code
 105  **/
 106 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 107 {
 108         return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 109 }
 110
 111 /**
 112  * ixgbe_get_cs4227_status - Return CS4227 status
 113  * @hw: pointer to hardware structure
 114  *
 115  * Returns error if CS4227 not successfully initialized
 116  **/
 117 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
 118 {
 119         s32 status;
 120         u16 value = 0;
 121         u8 retry;
 122
 123         for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
 124                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
 125                                            &value);
 126                 if (status != IXGBE_SUCCESS)
 127                         return status;
 128                 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
 129                         break;
 130                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 131         }
 132         if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
 133                 return IXGBE_ERR_PHY;
 134
 135         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 136                                     IXGBE_CS4227_SCRATCH_VALUE);
 137         if (status != IXGBE_SUCCESS)
 138                 return status;
 139         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 140         if (status != IXGBE_SUCCESS)
 141                 return status;
 142         if (value != IXGBE_CS4227_SCRATCH_VALUE)
 143                 return IXGBE_ERR_PHY;
 144         return IXGBE_SUCCESS;
 145 }
 146
 147 /**
 148  * ixgbe_read_pe - Read register from port expander
 149  * @hw: pointer to hardware structure
 150  * @reg: register number to read
 151  * @value: pointer to receive read value
 152  *
 153  * Returns status code
 154  **/
 155 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 156 {
 157         s32 status;
 158
 159         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 160         if (status != IXGBE_SUCCESS)
 161                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 162                               "port expander access failed with %d\n", status);
 163         return status;
 164 }
 165
 166 /**
 167  * ixgbe_write_pe - Write register to port expander
 168  * @hw: pointer to hardware structure
 169  * @reg: register number to write
 170  * @value: value to write
 171  *
 172  * Returns status code
 173  **/
 174 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 175 {
 176         s32 status;
 177
 178         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 179         if (status != IXGBE_SUCCESS)
 180                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 181                               "port expander access failed with %d\n", status);
 182         return status;
 183 }
 184
 185 /**
 186  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 187  * @hw: pointer to hardware structure
 188  *
 189  * Returns error code
 190  **/
 191 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 192 {
 193         s32 status;
 194         u8 reg;
 195
 196         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199         reg |= IXGBE_PE_BIT1;
 200         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 201         if (status != IXGBE_SUCCESS)
 202                 return status;
 203
 204         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 205         if (status != IXGBE_SUCCESS)
 206                 return status;
 207         reg &= ~IXGBE_PE_BIT1;
 208         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 209         if (status != IXGBE_SUCCESS)
 210                 return status;
 211
 212         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 213         if (status != IXGBE_SUCCESS)
 214                 return status;
 215         reg &= ~IXGBE_PE_BIT1;
 216         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 217         if (status != IXGBE_SUCCESS)
 218                 return status;
 219
 220         usec_delay(IXGBE_CS4227_RESET_HOLD);
 221
 222         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 223         if (status != IXGBE_SUCCESS)
 224                 return status;
 225         reg |= IXGBE_PE_BIT1;
 226         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 227         if (status != IXGBE_SUCCESS)
 228                 return status;
 229
 230         msec_delay(IXGBE_CS4227_RESET_DELAY);
 231
 232         return IXGBE_SUCCESS;
 233 }
 234
 235 /**
 236  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 237  * @hw: pointer to hardware structure
 238  **/
 239 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 240 {
 241         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 242         s32 status;
 243         u8 retry;
 244
 245         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 246                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 247                 if (status != IXGBE_SUCCESS) {
 248                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 249                                       "semaphore failed with %d\n", status);
 250                         return;
 251                 }
 252                 status = ixgbe_get_cs4227_status(hw);
 253                 if (status == IXGBE_SUCCESS) {
 254                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 255                         msec_delay(hw->eeprom.semaphore_delay);
 256                         return;
 257                 }
 258                 ixgbe_reset_cs4227(hw);
 259                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 260                 msec_delay(hw->eeprom.semaphore_delay);
 261         }
 262         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 263                       "Unable to initialize CS4227, err=%d\n", status);
 264 }
 265
 266 /**
 267  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 268  * @hw: pointer to hardware structure
 269  **/
 270 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 271 {
 272         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 273
 274         if (hw->bus.lan_id) {
 275                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 276                 esdp |= IXGBE_ESDP_SDP1_DIR;
 277         }
 278         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 279         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 280         IXGBE_WRITE_FLUSH(hw);
 281 }
 282
 283 /**
 284  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 285  * @hw: pointer to hardware structure
 286  *
 287  * Returns error code
 288  */
 289 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 290 {
 291         switch (hw->device_id) {
 292         case IXGBE_DEV_ID_X550EM_X_SFP:
 293                 /* set up for CS4227 usage */
 294                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 295                 ixgbe_setup_mux_ctl(hw);
 296                 ixgbe_check_cs4227(hw);
 297
 298                 return ixgbe_identify_module_generic(hw);
 299                 break;
 300         case IXGBE_DEV_ID_X550EM_X_KX4:
 301                 hw->phy.type = ixgbe_phy_x550em_kx4;
 302                 break;
 303         case IXGBE_DEV_ID_X550EM_X_KR:
 304                 hw->phy.type = ixgbe_phy_x550em_kr;
 305                 break;
 306         case IXGBE_DEV_ID_X550EM_X_1G_T:
 307         case IXGBE_DEV_ID_X550EM_X_10G_T:
 308                 return ixgbe_identify_phy_generic(hw);
 309         default:
 310                 break;
 311         }
 312         return IXGBE_SUCCESS;
 313 }
 314
 315 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 316                                      u32 device_type, u16 *phy_data)
 317 {
 318         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 319         return IXGBE_NOT_IMPLEMENTED;
 320 }
 321
 322 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 323                                       u32 device_type, u16 phy_data)
 324 {
 325         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 326         return IXGBE_NOT_IMPLEMENTED;
 327 }
 328
 329 /**
 330 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 331 *  @hw: pointer to hardware structure
 332 *
 333 *  Initialize the function pointers and for MAC type X550EM.
 334 *  Does not touch the hardware.
 335 **/
 336 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 337 {
 338         struct ixgbe_mac_info *mac = &hw->mac;
 339         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 340         struct ixgbe_phy_info *phy = &hw->phy;
 341         s32 ret_val;
 342
 343         DEBUGFUNC("ixgbe_init_ops_X550EM");
 344
 345         /* Similar to X550 so start there. */
 346         ret_val = ixgbe_init_ops_X550(hw);
 347
 348         /* Since this function eventually calls
 349          * ixgbe_init_ops_540 by design, we are setting
 350          * the pointers to NULL explicitly here to overwrite
 351          * the values being set in the x540 function.
 352          */
 353         /* Thermal sensor not supported in x550EM */
 354         mac->ops.get_thermal_sensor_data = NULL;
 355         mac->ops.init_thermal_sensor_thresh = NULL;
 356         mac->thermal_sensor_enabled = false;
 357
 358         /* FCOE not supported in x550EM */
 359         mac->ops.get_san_mac_addr = NULL;
 360         mac->ops.set_san_mac_addr = NULL;
 361         mac->ops.get_wwn_prefix = NULL;
 362         mac->ops.get_fcoe_boot_status = NULL;
 363
 364         /* IPsec not supported in x550EM */
 365         mac->ops.disable_sec_rx_path = NULL;
 366         mac->ops.enable_sec_rx_path = NULL;
 367
 368         /* X550EM bus type is internal*/
 369         hw->bus.type = ixgbe_bus_type_internal;
 370         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 371
 372         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 373         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 374         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 375         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 376         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 377         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 378         mac->ops.get_supported_physical_layer =
 379                                     ixgbe_get_supported_physical_layer_X550em;
 380
 381         /* PHY */
 382         phy->ops.init = ixgbe_init_phy_ops_X550em;
 383         phy->ops.identify = ixgbe_identify_phy_x550em;
 384         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 385                 phy->ops.set_phy_power = NULL;
 386
 387
 388         /* EEPROM */
 389         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 390         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 391         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 392         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 393         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 394         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 395         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 396         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 397
 398         return ret_val;
 399 }
 400
 401 /**
 402  *  ixgbe_dmac_config_X550
 403  *  @hw: pointer to hardware structure
 404  *
 405  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 406  *  When disabling dmac, dmac enable dmac bit is cleared.
 407  **/
 408 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 409 {
 410         u32 reg, high_pri_tc;
 411
 412         DEBUGFUNC("ixgbe_dmac_config_X550");
 413
 414         /* Disable DMA coalescing before configuring */
 415         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 416         reg &= ~IXGBE_DMACR_DMAC_EN;
 417         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 418
 419         /* Disable DMA Coalescing if the watchdog timer is 0 */
 420         if (!hw->mac.dmac_config.watchdog_timer)
 421                 goto out;
 422
 423         ixgbe_dmac_config_tcs_X550(hw);
 424
 425         /* Configure DMA Coalescing Control Register */
 426         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 427
 428         /* Set the watchdog timer in units of 40.96 usec */
 429         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 430         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 431
 432         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 433         /* If fcoe is enabled, set high priority traffic class */
 434         if (hw->mac.dmac_config.fcoe_en) {
 435                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 436                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 437                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 438         }
 439         reg |= IXGBE_DMACR_EN_MNG_IND;
 440
 441         /* Enable DMA coalescing after configuration */
 442         reg |= IXGBE_DMACR_DMAC_EN;
 443         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 444
 445 out:
 446         return IXGBE_SUCCESS;
 447 }
 448
 449 /**
 450  *  ixgbe_dmac_config_tcs_X550
 451  *  @hw: pointer to hardware structure
 452  *
 453  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 454  *  be cleared before configuring.
 455  **/
 456 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 457 {
 458         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 459
 460         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 461
 462         /* Configure DMA coalescing enabled */
 463         switch (hw->mac.dmac_config.link_speed) {
 464         case IXGBE_LINK_SPEED_100_FULL:
 465                 pb_headroom = IXGBE_DMACRXT_100M;
 466                 break;
 467         case IXGBE_LINK_SPEED_1GB_FULL:
 468                 pb_headroom = IXGBE_DMACRXT_1G;
 469                 break;
 470         default:
 471                 pb_headroom = IXGBE_DMACRXT_10G;
 472                 break;
 473         }
 474
 475         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 476                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 477
 478         /* Set the per Rx packet buffer receive threshold */
 479         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 480                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 481                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 482
 483                 if (tc < hw->mac.dmac_config.num_tcs) {
 484                         /* Get Rx PB size */
 485                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 486                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 487                                 IXGBE_RXPBSIZE_SHIFT;
 488
 489                         /* Calculate receive buffer threshold in kilobytes */
 490                         if (rx_pb_size > pb_headroom)
 491                                 rx_pb_size = rx_pb_size - pb_headroom;
 492                         else
 493                                 rx_pb_size = 0;
 494
 495                         /* Minimum of MFS shall be set for DMCTH */
 496                         reg |= (rx_pb_size > maxframe_size_kb) ?
 497                                 rx_pb_size : maxframe_size_kb;
 498                 }
 499                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 500         }
 501         return IXGBE_SUCCESS;
 502 }
 503
 504 /**
 505  *  ixgbe_dmac_update_tcs_X550
 506  *  @hw: pointer to hardware structure
 507  *
 508  *  Disables dmac, updates per TC settings, and then enables dmac.
 509  **/
 510 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 511 {
 512         u32 reg;
 513
 514         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 515
 516         /* Disable DMA coalescing before configuring */
 517         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 518         reg &= ~IXGBE_DMACR_DMAC_EN;
 519         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 520
 521         ixgbe_dmac_config_tcs_X550(hw);
 522
 523         /* Enable DMA coalescing after configuration */
 524         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 525         reg |= IXGBE_DMACR_DMAC_EN;
 526         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 527
 528         return IXGBE_SUCCESS;
 529 }
 530
 531 /**
 532  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 533  *  @hw: pointer to hardware structure
 534  *
 535  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 536  *  ixgbe_hw struct in order to set up EEPROM access.
 537  **/
 538 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 539 {
 540         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 541         u32 eec;
 542         u16 eeprom_size;
 543
 544         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 545
 546         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 547                 eeprom->semaphore_delay = 10;
 548                 eeprom->type = ixgbe_flash;
 549
 550                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 551                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 552                                     IXGBE_EEC_SIZE_SHIFT);
 553                 eeprom->word_size = 1 << (eeprom_size +
 554                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 555
 556                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 557                           eeprom->type, eeprom->word_size);
 558         }
 559
 560         return IXGBE_SUCCESS;
 561 }
 562
 563 /**
 564  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 565  *  @hw: pointer to the HW structure
 566  *  @enable_eee: boolean flag to enable EEE
 567  *
 568  *  Enable/disable EEE based on enable_eee flag.
 569  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 570  *  are modified.
 571  *
 572  **/
 573 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 574 {
 575         u32 eeer;
 576         u16 autoneg_eee_reg;
 577         u32 link_reg;
 578         s32 status;
 579
 580         DEBUGFUNC("ixgbe_setup_eee_X550");
 581
 582         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 583         /* Enable or disable EEE per flag */
 584         if (enable_eee) {
 585                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 586
 587                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 588                         /* Advertise EEE capability */
 589                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 590                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 591
 592                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 593                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 594                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 595
 596                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 597                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 598                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 599                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 600                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 601                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 602                         if (status != IXGBE_SUCCESS)
 603                                 return status;
 604
 605                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 606                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 607
 608                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 609                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 610                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 611                         if (status != IXGBE_SUCCESS)
 612                                 return status;
 613                 }
 614         } else {
 615                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 616
 617                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 618                         /* Disable advertised EEE capability */
 619                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 620                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 621
 622                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 623                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 624                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 625
 626                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 627                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 628                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 629                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 630                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 631                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 632                         if (status != IXGBE_SUCCESS)
 633                                 return status;
 634
 635                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 636                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 637
 638                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 639                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 640                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 641                         if (status != IXGBE_SUCCESS)
 642                                 return status;
 643                 }
 644         }
 645         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 646
 647         return IXGBE_SUCCESS;
 648 }
 649
 650 /**
 651  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 652  * @hw: pointer to hardware structure
 653  * @enable: enable or disable source address pruning
 654  * @pool: Rx pool to set source address pruning for
 655  **/
 656 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 657                                            unsigned int pool)
 658 {
 659         u64 pfflp;
 660
 661         /* max rx pool is 63 */
 662         if (pool > 63)
 663                 return;
 664
 665         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 666         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 667
 668         if (enable)
 669                 pfflp |= (1ULL << pool);
 670         else
 671                 pfflp &= ~(1ULL << pool);
 672
 673         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 674         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 675 }
 676
 677 /**
 678  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 679  *  @hw: pointer to hardware structure
 680  *  @enable: enable or disable switch for Ethertype anti-spoofing
 681  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 682  *
 683  **/
 684 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 685                 bool enable, int vf)
 686 {
 687         int vf_target_reg = vf >> 3;
 688         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 689         u32 pfvfspoof;
 690
 691         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 692
 693         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 694         if (enable)
 695                 pfvfspoof |= (1 << vf_target_shift);
 696         else
 697                 pfvfspoof &= ~(1 << vf_target_shift);
 698
 699         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 700 }
 701
 702 /**
 703  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 704  *  device
 705  *  @hw: pointer to hardware structure
 706  *  @reg_addr: 32 bit PHY register to write
 707  *  @device_type: 3 bit device type
 708  *  @data: Data to write to the register
 709  **/
 710 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 711                             u32 device_type, u32 data)
 712 {
 713         u32 i, command, error;
 714
 715         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 716                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 717
 718         /* Write IOSF control register */
 719         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 720
 721         /* Write IOSF data register */
 722         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 723         /*
 724          * Check every 10 usec to see if the address cycle completed.
 725          * The SB IOSF BUSY bit will clear when the operation is
 726          * complete
 727          */
 728         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 729                 usec_delay(10);
 730
 731                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 732                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 733                         break;
 734         }
 735
 736         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 737                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 738                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 739                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 740                               "Failed to write, error %x\n", error);
 741                 return IXGBE_ERR_PHY;
 742         }
 743
 744         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 745                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
 746                 return IXGBE_ERR_PHY;
 747         }
 748
 749         return IXGBE_SUCCESS;
 750 }
 751
 752 /**
 753  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 754  *  device
 755  *  @hw: pointer to hardware structure
 756  *  @reg_addr: 32 bit PHY register to write
 757  *  @device_type: 3 bit device type
 758  *  @phy_data: Pointer to read data from the register
 759  **/
 760 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 761                            u32 device_type, u32 *data)
 762 {
 763         u32 i, command, error;
 764
 765         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 766                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 767
 768         /* Write IOSF control register */
 769         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 770
 771         /*
 772          * Check every 10 usec to see if the address cycle completed.
 773          * The SB IOSF BUSY bit will clear when the operation is
 774          * complete
 775          */
 776         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 777                 usec_delay(10);
 778
 779                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 780                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 781                         break;
 782         }
 783
 784         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 785                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 786                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 787                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 788                                 "Failed to read, error %x\n", error);
 789                 return IXGBE_ERR_PHY;
 790         }
 791
 792         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 793                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
 794                 return IXGBE_ERR_PHY;
 795         }
 796
 797         *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 798
 799         return IXGBE_SUCCESS;
 800 }
 801
 802 /**
 803  *  ixgbe_disable_mdd_X550
 804  *  @hw: pointer to hardware structure
 805  *
 806  *  Disable malicious driver detection
 807  **/
 808 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 809 {
 810         u32 reg;
 811
 812         DEBUGFUNC("ixgbe_disable_mdd_X550");
 813
 814         /* Disable MDD for TX DMA and interrupt */
 815         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 816         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 817         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 818
 819         /* Disable MDD for RX and interrupt */
 820         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 821         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 822         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 823 }
 824
 825 /**
 826  *  ixgbe_enable_mdd_X550
 827  *  @hw: pointer to hardware structure
 828  *
 829  *  Enable malicious driver detection
 830  **/
 831 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 832 {
 833         u32 reg;
 834
 835         DEBUGFUNC("ixgbe_enable_mdd_X550");
 836
 837         /* Enable MDD for TX DMA and interrupt */
 838         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 839         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 840         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 841
 842         /* Enable MDD for RX and interrupt */
 843         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 844         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 845         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 846 }
 847
 848 /**
 849  *  ixgbe_restore_mdd_vf_X550
 850  *  @hw: pointer to hardware structure
 851  *  @vf: vf index
 852  *
 853  *  Restore VF that was disabled during malicious driver detection event
 854  **/
 855 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 856 {
 857         u32 idx, reg, num_qs, start_q, bitmask;
 858
 859         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 860
 861         /* Map VF to queues */
 862         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 863         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 864         case IXGBE_MRQC_VMDQRT8TCEN:
 865                 num_qs = 8;  /* 16 VFs / pools */
 866                 bitmask = 0x000000FF;
 867                 break;
 868         case IXGBE_MRQC_VMDQRSS32EN:
 869         case IXGBE_MRQC_VMDQRT4TCEN:
 870                 num_qs = 4;  /* 32 VFs / pools */
 871                 bitmask = 0x0000000F;
 872                 break;
 873         default:            /* 64 VFs / pools */
 874                 num_qs = 2;
 875                 bitmask = 0x00000003;
 876                 break;
 877         }
 878         start_q = vf * num_qs;
 879
 880         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
 881         idx = start_q / 32;
 882         reg = 0;
 883         reg |= (bitmask << (start_q % 32));
 884         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
 885         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
 886 }
 887
 888 /**
 889  *  ixgbe_mdd_event_X550
 890  *  @hw: pointer to hardware structure
 891  *  @vf_bitmap: vf bitmap of malicious vfs
 892  *
 893  *  Handle malicious driver detection event.
 894  **/
 895 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
 896 {
 897         u32 wqbr;
 898         u32 i, j, reg, q, shift, vf, idx;
 899
 900         DEBUGFUNC("ixgbe_mdd_event_X550");
 901
 902         /* figure out pool size for mapping to vf's */
 903         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 904         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 905         case IXGBE_MRQC_VMDQRT8TCEN:
 906                 shift = 3;  /* 16 VFs / pools */
 907                 break;
 908         case IXGBE_MRQC_VMDQRSS32EN:
 909         case IXGBE_MRQC_VMDQRT4TCEN:
 910                 shift = 2;  /* 32 VFs / pools */
 911                 break;
 912         default:
 913                 shift = 1;  /* 64 VFs / pools */
 914                 break;
 915         }
 916
 917         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
 918         for (i = 0; i < 4; i++) {
 919                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
 920                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
 921
 922                 if (!wqbr)
 923                         continue;
 924
 925                 /* Get malicious queue */
 926                 for (j = 0; j < 32 && wqbr; j++) {
 927
 928                         if (!(wqbr & (1 << j)))
 929                                 continue;
 930
 931                         /* Get queue from bitmask */
 932                         q = j + (i * 32);
 933
 934                         /* Map queue to vf */
 935                         vf = (q >> shift);
 936
 937                         /* Set vf bit in vf_bitmap */
 938                         idx = vf / 32;
 939                         vf_bitmap[idx] |= (1 << (vf % 32));
 940                         wqbr &= ~(1 << j);
 941                 }
 942         }
 943 }
 944
 945 /**
 946  *  ixgbe_get_media_type_X550em - Get media type
 947  *  @hw: pointer to hardware structure
 948  *
 949  *  Returns the media type (fiber, copper, backplane)
 950  */
 951 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
 952 {
 953         enum ixgbe_media_type media_type;
 954
 955         DEBUGFUNC("ixgbe_get_media_type_X550em");
 956
 957         /* Detect if there is a copper PHY attached. */
 958         switch (hw->device_id) {
 959         case IXGBE_DEV_ID_X550EM_X_KR:
 960         case IXGBE_DEV_ID_X550EM_X_KX4:
 961                 media_type = ixgbe_media_type_backplane;
 962                 break;
 963         case IXGBE_DEV_ID_X550EM_X_SFP:
 964                 media_type = ixgbe_media_type_fiber;
 965                 break;
 966         case IXGBE_DEV_ID_X550EM_X_1G_T:
 967         case IXGBE_DEV_ID_X550EM_X_10G_T:
 968                 media_type = ixgbe_media_type_copper;
 969                 break;
 970         default:
 971                 media_type = ixgbe_media_type_unknown;
 972                 break;
 973         }
 974         return media_type;
 975 }
 976
 977 /**
 978  *  ixgbe_setup_sfp_modules_X550em - Setup SFP module
 979  *  @hw: pointer to hardware structure
 980  */
 981 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
 982 {
 983         bool setup_linear;
 984         u16 reg_slice, edc_mode;
 985         s32 ret_val;
 986
 987         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
 988
 989         switch (hw->phy.sfp_type) {
 990         case ixgbe_sfp_type_unknown:
 991                 return IXGBE_SUCCESS;
 992         case ixgbe_sfp_type_not_present:
 993                 return IXGBE_ERR_SFP_NOT_PRESENT;
 994         case ixgbe_sfp_type_da_cu_core0:
 995         case ixgbe_sfp_type_da_cu_core1:
 996                 setup_linear = true;
 997                 break;
 998         case ixgbe_sfp_type_srlr_core0:
 999         case ixgbe_sfp_type_srlr_core1:
1000         case ixgbe_sfp_type_da_act_lmt_core0:
1001         case ixgbe_sfp_type_da_act_lmt_core1:
1002         case ixgbe_sfp_type_1g_sx_core0:
1003         case ixgbe_sfp_type_1g_sx_core1:
1004         case ixgbe_sfp_type_1g_lx_core0:
1005         case ixgbe_sfp_type_1g_lx_core1:
1006                 setup_linear = false;
1007                 break;
1008         default:
1009                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1010         }
1011
1012         ixgbe_init_mac_link_ops_X550em(hw);
1013         hw->phy.ops.reset = NULL;
1014
1015         /* The CS4227 slice address is the base address + the port-pair reg
1016          * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
1017          */
1018         reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12);
1019
1020         if (setup_linear)
1021                 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1022         else
1023                 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1024
1025         /* Configure CS4227 for connection type. */
1026         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1027                                            edc_mode);
1028
1029         if (ret_val != IXGBE_SUCCESS)
1030                 ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice,
1031                                                    edc_mode);
1032
1033         return ret_val;
1034 }
1035
1036 /**
1037  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1038  *  @hw: pointer to hardware structure
1039  */
1040 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1041 {
1042         struct ixgbe_mac_info *mac = &hw->mac;
1043
1044         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1045
1046         /* CS4227 does not support autoneg, so disable the laser control
1047          * functions for SFP+ fiber
1048          */
1049          if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
1050                 mac->ops.disable_tx_laser = NULL;
1051                 mac->ops.enable_tx_laser = NULL;
1052                 mac->ops.flap_tx_laser = NULL;
1053          }
1054 }
1055
1056 /**
1057  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1058  *  @hw: pointer to hardware structure
1059  *  @speed: pointer to link speed
1060  *  @autoneg: true when autoneg or autotry is enabled
1061  */
1062 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1063                                        ixgbe_link_speed *speed,
1064                                        bool *autoneg)
1065 {
1066         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1067
1068         /* SFP */
1069         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1070
1071                 /* CS4227 SFP must not enable auto-negotiation */
1072                 *autoneg = false;
1073
1074                 /* Check if 1G SFP module. */
1075                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1076                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1077                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1078                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1079                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1080                         return IXGBE_SUCCESS;
1081                 }
1082
1083                 /* Link capabilities are based on SFP */
1084                 if (hw->phy.multispeed_fiber)
1085                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1086                                  IXGBE_LINK_SPEED_1GB_FULL;
1087                 else
1088                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1089         } else {
1090                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1091                          IXGBE_LINK_SPEED_1GB_FULL;
1092                 *autoneg = true;
1093         }
1094
1095         return IXGBE_SUCCESS;
1096 }
1097
1098 /**
1099  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1100  *  @hw: pointer to hardware structure
1101  *
1102  *  Initialize any function pointers that were not able to be
1103  *  set during init_shared_code because the PHY/SFP type was
1104  *  not known.  Perform the SFP init if necessary.
1105  */
1106 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1107 {
1108         struct ixgbe_phy_info *phy = &hw->phy;
1109         s32 ret_val;
1110
1111         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1112
1113         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
1114                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1115                 ixgbe_setup_mux_ctl(hw);
1116         }
1117
1118         /* Identify the PHY or SFP module */
1119         ret_val = phy->ops.identify(hw);
1120         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1121                 return ret_val;
1122
1123         /* Setup function pointers based on detected SFP module and speeds */
1124         ixgbe_init_mac_link_ops_X550em(hw);
1125         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1126                 phy->ops.reset = NULL;
1127
1128         /* Set functions pointers based on phy type */
1129         switch (hw->phy.type) {
1130         case ixgbe_phy_x550em_kx4:
1131                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1132                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1133                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1134                 break;
1135         case ixgbe_phy_x550em_kr:
1136                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1137                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1138                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1139                 break;
1140         case ixgbe_phy_x550em_ext_t:
1141                 phy->ops.setup_internal_link = ixgbe_setup_internal_phy_x550em;
1142                 break;
1143         default:
1144                 break;
1145         }
1146         return ret_val;
1147 }
1148
1149 /**
1150  *  ixgbe_reset_hw_X550em - Perform hardware reset
1151  *  @hw: pointer to hardware structure
1152  *
1153  *  Resets the hardware by resetting the transmit and receive units, masks
1154  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1155  *  reset.
1156  */
1157 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1158 {
1159         struct ixgbe_hic_hdr fw_cmd;
1160         ixgbe_link_speed link_speed;
1161         s32 status;
1162         u32 ctrl = 0;
1163         u32 i;
1164         bool link_up = false;
1165
1166         DEBUGFUNC("ixgbe_reset_hw_X550em");
1167
1168         fw_cmd.cmd = FW_PHY_MGMT_REQ_CMD;
1169         fw_cmd.buf_len = 0;
1170         fw_cmd.cmd_or_resp.cmd_resv = 0;
1171         fw_cmd.checksum = FW_DEFAULT_CHECKSUM;
1172         status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
1173                                               sizeof(fw_cmd),
1174                                               IXGBE_HI_PHY_MGMT_REQ_TIMEOUT,
1175                                               true);
1176         if (status)
1177                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1178                               "PHY mgmt command failed with %d\n", status);
1179         else if (fw_cmd.cmd_or_resp.ret_status != FW_CEM_RESP_STATUS_SUCCESS)
1180                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1181                               "PHY mgmt command returned %d\n",
1182                               fw_cmd.cmd_or_resp.ret_status);
1183
1184         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1185         status = hw->mac.ops.stop_adapter(hw);
1186         if (status != IXGBE_SUCCESS)
1187                 return status;
1188
1189         /* flush pending Tx transactions */
1190         ixgbe_clear_tx_pending(hw);
1191
1192         /* PHY ops must be identified and initialized prior to reset */
1193
1194         /* Identify PHY and related function pointers */
1195         status = hw->phy.ops.init(hw);
1196
1197         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1198                 return status;
1199
1200         /* start the external PHY */
1201         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1202                 status = ixgbe_init_ext_t_x550em(hw);
1203                 if (status)
1204                         return status;
1205         }
1206
1207         /* Setup SFP module if there is one present. */
1208         if (hw->phy.sfp_setup_needed) {
1209                 status = hw->mac.ops.setup_sfp(hw);
1210                 hw->phy.sfp_setup_needed = false;
1211         }
1212
1213         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1214                 return status;
1215
1216         /* Reset PHY */
1217         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1218                 hw->phy.ops.reset(hw);
1219
1220 mac_reset_top:
1221         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1222          * If link reset is used when link is up, it might reset the PHY when
1223          * mng is using it.  If link is down or the flag to force full link
1224          * reset is set, then perform link reset.
1225          */
1226         ctrl = IXGBE_CTRL_LNK_RST;
1227         if (!hw->force_full_reset) {
1228                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1229                 if (link_up)
1230                         ctrl = IXGBE_CTRL_RST;
1231         }
1232
1233         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1234         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1235         IXGBE_WRITE_FLUSH(hw);
1236
1237         /* Poll for reset bit to self-clear meaning reset is complete */
1238         for (i = 0; i < 10; i++) {
1239                 usec_delay(1);
1240                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1241                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1242                         break;
1243         }
1244
1245         if (ctrl & IXGBE_CTRL_RST_MASK) {
1246                 status = IXGBE_ERR_RESET_FAILED;
1247                 DEBUGOUT("Reset polling failed to complete.\n");
1248         }
1249
1250         msec_delay(50);
1251
1252         /* Double resets are required for recovery from certain error
1253          * conditions.  Between resets, it is necessary to stall to
1254          * allow time for any pending HW events to complete.
1255          */
1256         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1257                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1258                 goto mac_reset_top;
1259         }
1260
1261         /* Store the permanent mac address */
1262         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1263
1264         /* Store MAC address from RAR0, clear receive address registers, and
1265          * clear the multicast table.  Also reset num_rar_entries to 128,
1266          * since we modify this value when programming the SAN MAC address.
1267          */
1268         hw->mac.num_rar_entries = 128;
1269         hw->mac.ops.init_rx_addrs(hw);
1270
1271
1272         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1273                 ixgbe_setup_mux_ctl(hw);
1274
1275         return status;
1276 }
1277
1278 /**
1279  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1280  * @hw: pointer to hardware structure
1281  */
1282 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1283 {
1284         u32 status;
1285         u16 reg;
1286         u32 retries = 1;
1287
1288         /* TODO: The number of attempts and delay between attempts is undefined */
1289         do {
1290                 /* decrement retries counter and exit if we hit 0 */
1291                 if (retries < 1) {
1292                         ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
1293                                       "External PHY not yet finished resetting.");
1294                         return IXGBE_ERR_PHY;
1295                 }
1296                 retries--;
1297
1298                 usec_delay(0);
1299
1300                 status = hw->phy.ops.read_reg(hw,
1301                                               IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1302                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1303                                               &reg);
1304
1305                 if (status != IXGBE_SUCCESS)
1306                         return status;
1307
1308                 /* Verify PHY FW reset has completed */
1309         } while ((reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) != 1);
1310
1311         /* Set port to low power mode */
1312         status = hw->phy.ops.read_reg(hw,
1313                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
1314                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1315                                       &reg);
1316
1317         if (status != IXGBE_SUCCESS)
1318                 return status;
1319
1320         reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
1321
1322         status = hw->phy.ops.write_reg(hw,
1323                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
1324                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1325                                        reg);
1326
1327         if (status != IXGBE_SUCCESS)
1328                 return status;
1329
1330         /* Enable the transmitter */
1331         status = hw->phy.ops.read_reg(hw,
1332                                       IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR,
1333                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1334                                       &reg);
1335
1336         if (status != IXGBE_SUCCESS)
1337                 return status;
1338
1339         reg &= ~IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE;
1340
1341         status = hw->phy.ops.write_reg(hw,
1342                                        IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR,
1343                                        IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1344                                        reg);
1345
1346         if (status != IXGBE_SUCCESS)
1347                 return status;
1348
1349         /* Un-stall the PHY FW */
1350         status = hw->phy.ops.read_reg(hw,
1351                                       IXGBE_MDIO_GLOBAL_RES_PR_10,
1352                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1353                                       &reg);
1354
1355         if (status != IXGBE_SUCCESS)
1356                 return status;
1357
1358         reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1359
1360         status = hw->phy.ops.write_reg(hw,
1361                                        IXGBE_MDIO_GLOBAL_RES_PR_10,
1362                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1363                                        reg);
1364
1365         return status;
1366 }
1367
1368 /**
1369  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1370  *  @hw: pointer to hardware structure
1371  *
1372  *  Configures the integrated KR PHY.
1373  **/
1374 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1375 {
1376         s32 status;
1377         u32 reg_val;
1378
1379         status = ixgbe_read_iosf_sb_reg_x550(hw,
1380                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1381                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1382         if (status)
1383                 return status;
1384
1385         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1386         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1387                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1388         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1389                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1390
1391         /* Advertise 10G support. */
1392         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1393                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1394
1395         /* Advertise 1G support. */
1396         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1397                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1398
1399         /* Restart auto-negotiation. */
1400         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1401         status = ixgbe_write_iosf_sb_reg_x550(hw,
1402                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1403                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1404
1405         return status;
1406 }
1407
1408 /**
1409  *  ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1410  *  @hw: pointer to hardware structure
1411  *
1412  *  Configures the integrated KX4 PHY.
1413  **/
1414 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1415 {
1416         s32 status;
1417         u32 reg_val;
1418
1419         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1420                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, &reg_val);
1421         if (status)
1422                 return status;
1423
1424         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1425                         IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1426
1427         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1428
1429         /* Advertise 10G support. */
1430         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1431                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1432
1433         /* Advertise 1G support. */
1434         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1435                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1436
1437         /* Restart auto-negotiation. */
1438         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1439         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1440                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, reg_val);
1441
1442         return status;
1443 }
1444
1445 /**
1446  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1447  *  @hw: pointer to hardware structure
1448  *  @speed: the link speed to force
1449  *
1450  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1451  *  internal and external PHY at a specific speed, without autonegotiation.
1452  **/
1453 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1454 {
1455         s32 status;
1456         u32 reg_val;
1457
1458         /* Disable AN and force speed to 10G Serial. */
1459         status = ixgbe_read_iosf_sb_reg_x550(hw,
1460                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1461                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1462         if (status != IXGBE_SUCCESS)
1463                 return status;
1464
1465         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1466         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1467
1468         /* Select forced link speed for internal PHY. */
1469         switch (*speed) {
1470         case IXGBE_LINK_SPEED_10GB_FULL:
1471                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1472                 break;
1473         case IXGBE_LINK_SPEED_1GB_FULL:
1474                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1475                 break;
1476         default:
1477                 /* Other link speeds are not supported by internal KR PHY. */
1478                 return IXGBE_ERR_LINK_SETUP;
1479         }
1480
1481         status = ixgbe_write_iosf_sb_reg_x550(hw,
1482                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1483                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1484         if (status != IXGBE_SUCCESS)
1485                 return status;
1486
1487         /* Disable training protocol FSM. */
1488         status = ixgbe_read_iosf_sb_reg_x550(hw,
1489                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1490                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1491         if (status != IXGBE_SUCCESS)
1492                 return status;
1493         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1494         status = ixgbe_write_iosf_sb_reg_x550(hw,
1495                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1496                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1497         if (status != IXGBE_SUCCESS)
1498                 return status;
1499
1500         /* Disable Flex from training TXFFE. */
1501         status = ixgbe_read_iosf_sb_reg_x550(hw,
1502                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1503                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1504         if (status != IXGBE_SUCCESS)
1505                 return status;
1506         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1507         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1508         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1509         status = ixgbe_write_iosf_sb_reg_x550(hw,
1510                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1511                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1512         if (status != IXGBE_SUCCESS)
1513                 return status;
1514         status = ixgbe_read_iosf_sb_reg_x550(hw,
1515                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1516                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1517         if (status != IXGBE_SUCCESS)
1518                 return status;
1519         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1520         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1521         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1522         status = ixgbe_write_iosf_sb_reg_x550(hw,
1523                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1524                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1525         if (status != IXGBE_SUCCESS)
1526                 return status;
1527
1528         /* Enable override for coefficients. */
1529         status = ixgbe_read_iosf_sb_reg_x550(hw,
1530                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1531                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1532         if (status != IXGBE_SUCCESS)
1533                 return status;
1534         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1535         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1536         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1537         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1538         status = ixgbe_write_iosf_sb_reg_x550(hw,
1539                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1540                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1541         if (status != IXGBE_SUCCESS)
1542                 return status;
1543
1544         /* Toggle port SW reset by AN reset. */
1545         status = ixgbe_read_iosf_sb_reg_x550(hw,
1546                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1547                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1548         if (status != IXGBE_SUCCESS)
1549                 return status;
1550         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1551         status = ixgbe_write_iosf_sb_reg_x550(hw,
1552                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1553                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1554
1555         return status;
1556 }
1557
1558 /**
1559  * ixgbe_setup_internal_phy_x550em - Configure integrated KR PHY
1560  * @hw: point to hardware structure
1561  *
1562  * Configures the integrated KR PHY to talk to the external PHY. The base
1563  * driver will call this function when it gets notification via interrupt from
1564  * the external PHY. This function forces the internal PHY into iXFI mode at
1565  * the correct speed.
1566  *
1567  * A return of a non-zero value indicates an error, and the base driver should
1568  * not report link up.
1569  */
1570 s32 ixgbe_setup_internal_phy_x550em(struct ixgbe_hw *hw)
1571 {
1572         u32 status;
1573         u16 lasi, autoneg_status, speed;
1574         ixgbe_link_speed force_speed;
1575
1576         /* Verify that the external link status has changed */
1577         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_XENPAK_LASI_STATUS,
1578                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1579                                       &lasi);
1580         if (status != IXGBE_SUCCESS)
1581                 return status;
1582
1583         /* If there was no change in link status, we can just exit */
1584         if (!(lasi & IXGBE_XENPAK_LASI_LINK_STATUS_ALARM))
1585                 return IXGBE_SUCCESS;
1586
1587         /* we read this twice back to back to indicate current status */
1588         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1589                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1590                                       &autoneg_status);
1591         if (status != IXGBE_SUCCESS)
1592                 return status;
1593
1594         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1595                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1596                                       &autoneg_status);
1597         if (status != IXGBE_SUCCESS)
1598                 return status;
1599
1600         /* If link is not up return an error indicating treat link as down */
1601         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1602                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1603
1604         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1605                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1606                                       &speed);
1607
1608         /* clear everything but the speed and duplex bits */
1609         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1610
1611         switch (speed) {
1612         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1613                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1614                 break;
1615         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1616                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1617                 break;
1618         default:
1619                 /* Internal PHY does not support anything else */
1620                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1621         }
1622
1623         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1624 }
1625
1626 /**
1627  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1628  *  @hw: pointer to hardware structure
1629  *
1630  *  Configures the integrated KR PHY to use internal loopback mode.
1631  **/
1632 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1633 {
1634         s32 status;
1635         u32 reg_val;
1636
1637         /* Disable AN and force speed to 10G Serial. */
1638         status = ixgbe_read_iosf_sb_reg_x550(hw,
1639                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1640                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1641         if (status != IXGBE_SUCCESS)
1642                 return status;
1643         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1644         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1645         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1646         status = ixgbe_write_iosf_sb_reg_x550(hw,
1647                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1648                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1649         if (status != IXGBE_SUCCESS)
1650                 return status;
1651
1652         /* Set near-end loopback clocks. */
1653         status = ixgbe_read_iosf_sb_reg_x550(hw,
1654                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1655                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1656         if (status != IXGBE_SUCCESS)
1657                 return status;
1658         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1659         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1660         status = ixgbe_write_iosf_sb_reg_x550(hw,
1661                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1662                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1663         if (status != IXGBE_SUCCESS)
1664                 return status;
1665
1666         /* Set loopback enable. */
1667         status = ixgbe_read_iosf_sb_reg_x550(hw,
1668                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1669                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1670         if (status != IXGBE_SUCCESS)
1671                 return status;
1672         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1673         status = ixgbe_write_iosf_sb_reg_x550(hw,
1674                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1675                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1676         if (status != IXGBE_SUCCESS)
1677                 return status;
1678
1679         /* Training bypass. */
1680         status = ixgbe_read_iosf_sb_reg_x550(hw,
1681                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1682                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1683         if (status != IXGBE_SUCCESS)
1684                 return status;
1685         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1686         status = ixgbe_write_iosf_sb_reg_x550(hw,
1687                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1688                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1689
1690         return status;
1691 }
1692
1693 /**
1694  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1695  *  assuming that the semaphore is already obtained.
1696  *  @hw: pointer to hardware structure
1697  *  @offset: offset of  word in the EEPROM to read
1698  *  @data: word read from the EEPROM
1699  *
1700  *  Reads a 16 bit word from the EEPROM using the hostif.
1701  **/
1702 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1703                                    u16 *data)
1704 {
1705         s32 status;
1706         struct ixgbe_hic_read_shadow_ram buffer;
1707
1708         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1709         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1710         buffer.hdr.req.buf_lenh = 0;
1711         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1712         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1713
1714         /* convert offset from words to bytes */
1715         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1716         /* one word */
1717         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1718
1719         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1720                                               sizeof(buffer),
1721                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1722
1723         if (status)
1724                 return status;
1725
1726         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1727                                           FW_NVM_DATA_OFFSET);
1728
1729         return 0;
1730 }
1731
1732 /**
1733  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1734  *  @hw: pointer to hardware structure
1735  *  @offset: offset of  word in the EEPROM to read
1736  *  @data: word read from the EEPROM
1737  *
1738  *  Reads a 16 bit word from the EEPROM using the hostif.
1739  **/
1740 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1741                               u16 *data)
1742 {
1743         s32 status = IXGBE_SUCCESS;
1744
1745         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1746
1747         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1748             IXGBE_SUCCESS) {
1749                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1750                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1751         } else {
1752                 status = IXGBE_ERR_SWFW_SYNC;
1753         }
1754
1755         return status;
1756 }
1757
1758 /**
1759  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1760  *  @hw: pointer to hardware structure
1761  *  @offset: offset of  word in the EEPROM to read
1762  *  @words: number of words
1763  *  @data: word(s) read from the EEPROM
1764  *
1765  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
1766  **/
1767 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1768                                      u16 offset, u16 words, u16 *data)
1769 {
1770         struct ixgbe_hic_read_shadow_ram buffer;
1771         u32 current_word = 0;
1772         u16 words_to_read;
1773         s32 status;
1774         u32 i;
1775
1776         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1777
1778         /* Take semaphore for the entire operation. */
1779         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1780         if (status) {
1781                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1782                 return status;
1783         }
1784         while (words) {
1785                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1786                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1787                 else
1788                         words_to_read = words;
1789
1790                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1791                 buffer.hdr.req.buf_lenh = 0;
1792                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1793                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1794
1795                 /* convert offset from words to bytes */
1796                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1797                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1798
1799                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1800                                                       sizeof(buffer),
1801                                                       IXGBE_HI_COMMAND_TIMEOUT,
1802                                                       false);
1803
1804                 if (status) {
1805                         DEBUGOUT("Host interface command failed\n");
1806                         goto out;
1807                 }
1808
1809                 for (i = 0; i < words_to_read; i++) {
1810                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1811                                   2 * i;
1812                         u32 value = IXGBE_READ_REG(hw, reg);
1813
1814                         data[current_word] = (u16)(value & 0xffff);
1815                         current_word++;
1816                         i++;
1817                         if (i < words_to_read) {
1818                                 value >>= 16;
1819                                 data[current_word] = (u16)(value & 0xffff);
1820                                 current_word++;
1821                         }
1822                 }
1823                 words -= words_to_read;
1824         }
1825
1826 out:
1827         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1828         return status;
1829 }
1830
1831 /**
1832  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1833  *  @hw: pointer to hardware structure
1834  *  @offset: offset of  word in the EEPROM to write
1835  *  @data: word write to the EEPROM
1836  *
1837  *  Write a 16 bit word to the EEPROM using the hostif.
1838  **/
1839 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1840                                     u16 data)
1841 {
1842         s32 status;
1843         struct ixgbe_hic_write_shadow_ram buffer;
1844
1845         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1846
1847         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1848         buffer.hdr.req.buf_lenh = 0;
1849         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
1850         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1851
1852          /* one word */
1853         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1854         buffer.data = data;
1855         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1856
1857         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1858                                               sizeof(buffer),
1859                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1860
1861         return status;
1862 }
1863
1864 /**
1865  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1866  *  @hw: pointer to hardware structure
1867  *  @offset: offset of  word in the EEPROM to write
1868  *  @data: word write to the EEPROM
1869  *
1870  *  Write a 16 bit word to the EEPROM using the hostif.
1871  **/
1872 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1873                                u16 data)
1874 {
1875         s32 status = IXGBE_SUCCESS;
1876
1877         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
1878
1879         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1880             IXGBE_SUCCESS) {
1881                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1882                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1883         } else {
1884                 DEBUGOUT("write ee hostif failed to get semaphore");
1885                 status = IXGBE_ERR_SWFW_SYNC;
1886         }
1887
1888         return status;
1889 }
1890
1891 /**
1892  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1893  *  @hw: pointer to hardware structure
1894  *  @offset: offset of  word in the EEPROM to write
1895  *  @words: number of words
1896  *  @data: word(s) write to the EEPROM
1897  *
1898  *  Write a 16 bit word(s) to the EEPROM using the hostif.
1899  **/
1900 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1901                                       u16 offset, u16 words, u16 *data)
1902 {
1903         s32 status = IXGBE_SUCCESS;
1904         u32 i = 0;
1905
1906         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
1907
1908         /* Take semaphore for the entire operation. */
1909         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1910         if (status != IXGBE_SUCCESS) {
1911                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
1912                 goto out;
1913         }
1914
1915         for (i = 0; i < words; i++) {
1916                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1917                                                          data[i]);
1918
1919                 if (status != IXGBE_SUCCESS) {
1920                         DEBUGOUT("Eeprom buffered write failed\n");
1921                         break;
1922                 }
1923         }
1924
1925         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1926 out:
1927
1928         return status;
1929 }
1930
1931 /**
1932  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
1933  * @hw: pointer to hardware structure
1934  * @ptr: pointer offset in eeprom
1935  * @size: size of section pointed by ptr, if 0 first word will be used as size
1936  * @csum: address of checksum to update
1937  *
1938  * Returns error status for any failure
1939  */
1940 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
1941                                    u16 size, u16 *csum, u16 *buffer,
1942                                    u32 buffer_size)
1943 {
1944         u16 buf[256];
1945         s32 status;
1946         u16 length, bufsz, i, start;
1947         u16 *local_buffer;
1948
1949         bufsz = sizeof(buf) / sizeof(buf[0]);
1950
1951         /* Read a chunk at the pointer location */
1952         if (!buffer) {
1953                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
1954                 if (status) {
1955                         DEBUGOUT("Failed to read EEPROM image\n");
1956                         return status;
1957                 }
1958                 local_buffer = buf;
1959         } else {
1960                 if (buffer_size < ptr)
1961                         return  IXGBE_ERR_PARAM;
1962                 local_buffer = &buffer[ptr];
1963         }
1964
1965         if (size) {
1966                 start = 0;
1967                 length = size;
1968         } else {
1969                 start = 1;
1970                 length = local_buffer[0];
1971
1972                 /* Skip pointer section if length is invalid. */
1973                 if (length == 0xFFFF || length == 0 ||
1974                     (ptr + length) >= hw->eeprom.word_size)
1975                         return IXGBE_SUCCESS;
1976         }
1977
1978         if (buffer && ((u32)start + (u32)length > buffer_size))
1979                 return IXGBE_ERR_PARAM;
1980
1981         for (i = start; length; i++, length--) {
1982                 if (i == bufsz && !buffer) {
1983                         ptr += bufsz;
1984                         i = 0;
1985                         if (length < bufsz)
1986                                 bufsz = length;
1987
1988                         /* Read a chunk at the pointer location */
1989                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
1990                                                                   bufsz, buf);
1991                         if (status) {
1992                                 DEBUGOUT("Failed to read EEPROM image\n");
1993                                 return status;
1994                         }
1995                 }
1996                 *csum += local_buffer[i];
1997         }
1998         return IXGBE_SUCCESS;
1999 }
2000
2001 /**
2002  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2003  *  @hw: pointer to hardware structure
2004  *  @buffer: pointer to buffer containing calculated checksum
2005  *  @buffer_size: size of buffer
2006  *
2007  *  Returns a negative error code on error, or the 16-bit checksum
2008  **/
2009 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2010 {
2011         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2012         u16 *local_buffer;
2013         s32 status;
2014         u16 checksum = 0;
2015         u16 pointer, i, size;
2016
2017         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2018
2019         hw->eeprom.ops.init_params(hw);
2020
2021         if (!buffer) {
2022                 /* Read pointer area */
2023                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2024                                                      IXGBE_EEPROM_LAST_WORD + 1,
2025                                                      eeprom_ptrs);
2026                 if (status) {
2027                         DEBUGOUT("Failed to read EEPROM image\n");
2028                         return status;
2029                 }
2030                 local_buffer = eeprom_ptrs;
2031         } else {
2032                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2033                         return IXGBE_ERR_PARAM;
2034                 local_buffer = buffer;
2035         }
2036
2037         /*
2038          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2039          * checksum word itself
2040          */
2041         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2042                 if (i != IXGBE_EEPROM_CHECKSUM)
2043                         checksum += local_buffer[i];
2044
2045         /*
2046          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2047          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2048          */
2049         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2050                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2051                         continue;
2052
2053                 pointer = local_buffer[i];
2054
2055                 /* Skip pointer section if the pointer is invalid. */
2056                 if (pointer == 0xFFFF || pointer == 0 ||
2057                     pointer >= hw->eeprom.word_size)
2058                         continue;
2059
2060                 switch (i) {
2061                 case IXGBE_PCIE_GENERAL_PTR:
2062                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2063                         break;
2064                 case IXGBE_PCIE_CONFIG0_PTR:
2065                 case IXGBE_PCIE_CONFIG1_PTR:
2066                         size = IXGBE_PCIE_CONFIG_SIZE;
2067                         break;
2068                 default:
2069                         size = 0;
2070                         break;
2071                 }
2072
2073                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2074                                                 buffer, buffer_size);
2075                 if (status)
2076                         return status;
2077         }
2078
2079         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2080
2081         return (s32)checksum;
2082 }
2083
2084 /**
2085  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2086  *  @hw: pointer to hardware structure
2087  *
2088  *  Returns a negative error code on error, or the 16-bit checksum
2089  **/
2090 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2091 {
2092         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2093 }
2094
2095 /**
2096  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2097  *  @hw: pointer to hardware structure
2098  *  @checksum_val: calculated checksum
2099  *
2100  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2101  *  caller does not need checksum_val, the value can be NULL.
2102  **/
2103 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2104 {
2105         s32 status;
2106         u16 checksum;
2107         u16 read_checksum = 0;
2108
2109         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2110
2111         /* Read the first word from the EEPROM. If this times out or fails, do
2112          * not continue or we could be in for a very long wait while every
2113          * EEPROM read fails
2114          */
2115         status = hw->eeprom.ops.read(hw, 0, &checksum);
2116         if (status) {
2117                 DEBUGOUT("EEPROM read failed\n");
2118                 return status;
2119         }
2120
2121         status = hw->eeprom.ops.calc_checksum(hw);
2122         if (status < 0)
2123                 return status;
2124
2125         checksum = (u16)(status & 0xffff);
2126
2127         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2128                                            &read_checksum);
2129         if (status)
2130                 return status;
2131
2132         /* Verify read checksum from EEPROM is the same as
2133          * calculated checksum
2134          */
2135         if (read_checksum != checksum) {
2136                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2137                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2138                              "Invalid EEPROM checksum");
2139         }
2140
2141         /* If the user cares, return the calculated checksum */
2142         if (checksum_val)
2143                 *checksum_val = checksum;
2144
2145         return status;
2146 }
2147
2148 /**
2149  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2150  * @hw: pointer to hardware structure
2151  *
2152  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2153  * checksum and updates the EEPROM and instructs the hardware to update
2154  * the flash.
2155  **/
2156 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2157 {
2158         s32 status;
2159         u16 checksum = 0;
2160
2161         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2162
2163         /* Read the first word from the EEPROM. If this times out or fails, do
2164          * not continue or we could be in for a very long wait while every
2165          * EEPROM read fails
2166          */
2167         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2168         if (status) {
2169                 DEBUGOUT("EEPROM read failed\n");
2170                 return status;
2171         }
2172
2173         status = ixgbe_calc_eeprom_checksum_X550(hw);
2174         if (status < 0)
2175                 return status;
2176
2177         checksum = (u16)(status & 0xffff);
2178
2179         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2180                                             checksum);
2181         if (status)
2182                 return status;
2183
2184         status = ixgbe_update_flash_X550(hw);
2185
2186         return status;
2187 }
2188
2189 /**
2190  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2191  *  @hw: pointer to hardware structure
2192  *
2193  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2194  **/
2195 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2196 {
2197         s32 status = IXGBE_SUCCESS;
2198         union ixgbe_hic_hdr2 buffer;
2199
2200         DEBUGFUNC("ixgbe_update_flash_X550");
2201
2202         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2203         buffer.req.buf_lenh = 0;
2204         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2205         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2206
2207         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2208                                               sizeof(buffer),
2209                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2210
2211         return status;
2212 }
2213
2214 /**
2215  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2216  *  @hw: pointer to hardware structure
2217  *
2218  *  Determines physical layer capabilities of the current configuration.
2219  **/
2220 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2221 {
2222         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2223         u16 ext_ability = 0;
2224
2225         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2226
2227         hw->phy.ops.identify(hw);
2228
2229         switch (hw->phy.type) {
2230         case ixgbe_phy_x550em_kr:
2231                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2232                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2233                 break;
2234         case ixgbe_phy_x550em_kx4:
2235                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2236                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2237                 break;
2238         case ixgbe_phy_x550em_ext_t:
2239                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2240                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2241                                      &ext_ability);
2242                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2243                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2244                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2245                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2246                 break;
2247         default:
2248                 break;
2249         }
2250
2251         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2252                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2253
2254         return physical_layer;
2255 }
2256
2257 /**
2258  * ixgbe_get_bus_info_x550em - Set PCI bus info
2259  * @hw: pointer to hardware structure
2260  *
2261  * Sets bus link width and speed to unknown because X550em is
2262  * not a PCI device.
2263  **/
2264 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2265 {
2266
2267         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2268
2269         hw->bus.width = ixgbe_bus_width_unknown;
2270         hw->bus.speed = ixgbe_bus_speed_unknown;
2271
2272         return IXGBE_SUCCESS;
2273 }
2274
2275 /**
2276  * ixgbe_disable_rx_x550 - Disable RX unit
2277  *
2278  * Enables the Rx DMA unit for x550
2279  **/
2280 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2281 {
2282         u32 rxctrl, pfdtxgswc;
2283         s32 status;
2284         struct ixgbe_hic_disable_rxen fw_cmd;
2285
2286         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2287
2288         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2289         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2290                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2291                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2292                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2293                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2294                         hw->mac.set_lben = true;
2295                 } else {
2296                         hw->mac.set_lben = false;
2297                 }
2298
2299                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2300                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2301                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2302                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2303
2304                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2305                                         sizeof(struct ixgbe_hic_disable_rxen),
2306                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2307
2308                 /* If we fail - disable RX using register write */
2309                 if (status) {
2310                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2311                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2312                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2313                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2314                         }
2315                 }
2316         }
2317 }