drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44
  45 /**
  46  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  47  *  @hw: pointer to hardware structure
  48  *
  49  *  Initialize the function pointers and assign the MAC type for X550.
  50  *  Does not touch the hardware.
  51  **/
  52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  53 {
  54         struct ixgbe_mac_info *mac = &hw->mac;
  55         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  56         s32 ret_val;
  57
  58         DEBUGFUNC("ixgbe_init_ops_X550");
  59
  60         ret_val = ixgbe_init_ops_X540(hw);
  61         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  62         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  63         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  64         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  65         mac->ops.set_source_address_pruning =
  66                         ixgbe_set_source_address_pruning_X550;
  67         mac->ops.set_ethertype_anti_spoofing =
  68                         ixgbe_set_ethertype_anti_spoofing_X550;
  69
  70         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  71         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  72         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  73         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  74         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  75         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  76         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  77         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  78         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  79
  80         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  81         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  82         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  83         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  84         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  85         switch (hw->device_id) {
  86         case IXGBE_DEV_ID_X550EM_X_10G_T:
  87         case IXGBE_DEV_ID_X550EM_A_10G_T:
  88                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  89                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  90                 break;
  91         default:
  92                 break;
  93         }
  94         return ret_val;
  95 }
  96
  97 /**
  98  * ixgbe_read_cs4227 - Read CS4227 register
  99  * @hw: pointer to hardware structure
 100  * @reg: register number to write
 101  * @value: pointer to receive value read
 102  *
 103  * Returns status code
 104  **/
 105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 106 {
 107         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
 108 }
 109
 110 /**
 111  * ixgbe_write_cs4227 - Write CS4227 register
 112  * @hw: pointer to hardware structure
 113  * @reg: register number to write
 114  * @value: value to write to register
 115  *
 116  * Returns status code
 117  **/
 118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 119 {
 120         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 121 }
 122
 123 /**
 124  * ixgbe_read_pe - Read register from port expander
 125  * @hw: pointer to hardware structure
 126  * @reg: register number to read
 127  * @value: pointer to receive read value
 128  *
 129  * Returns status code
 130  **/
 131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 132 {
 133         s32 status;
 134
 135         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 136         if (status != IXGBE_SUCCESS)
 137                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 138                               "port expander access failed with %d\n", status);
 139         return status;
 140 }
 141
 142 /**
 143  * ixgbe_write_pe - Write register to port expander
 144  * @hw: pointer to hardware structure
 145  * @reg: register number to write
 146  * @value: value to write
 147  *
 148  * Returns status code
 149  **/
 150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 151 {
 152         s32 status;
 153
 154         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 155         if (status != IXGBE_SUCCESS)
 156                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 157                               "port expander access failed with %d\n", status);
 158         return status;
 159 }
 160
 161 /**
 162  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 163  * @hw: pointer to hardware structure
 164  *
 165  * This function assumes that the caller has acquired the proper semaphore.
 166  * Returns error code
 167  **/
 168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 169 {
 170         s32 status;
 171         u32 retry;
 172         u16 value;
 173         u8 reg;
 174
 175         /* Trigger hard reset. */
 176         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 177         if (status != IXGBE_SUCCESS)
 178                 return status;
 179         reg |= IXGBE_PE_BIT1;
 180         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 181         if (status != IXGBE_SUCCESS)
 182                 return status;
 183
 184         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 185         if (status != IXGBE_SUCCESS)
 186                 return status;
 187         reg &= ~IXGBE_PE_BIT1;
 188         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 189         if (status != IXGBE_SUCCESS)
 190                 return status;
 191
 192         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 193         if (status != IXGBE_SUCCESS)
 194                 return status;
 195         reg &= ~IXGBE_PE_BIT1;
 196         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199
 200         usec_delay(IXGBE_CS4227_RESET_HOLD);
 201
 202         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 203         if (status != IXGBE_SUCCESS)
 204                 return status;
 205         reg |= IXGBE_PE_BIT1;
 206         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 207         if (status != IXGBE_SUCCESS)
 208                 return status;
 209
 210         /* Wait for the reset to complete. */
 211         msec_delay(IXGBE_CS4227_RESET_DELAY);
 212         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 213                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 214                                            &value);
 215                 if (status == IXGBE_SUCCESS &&
 216                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 217                         break;
 218                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 219         }
 220         if (retry == IXGBE_CS4227_RETRIES) {
 221                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 222                         "CS4227 reset did not complete.");
 223                 return IXGBE_ERR_PHY;
 224         }
 225
 226         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 227         if (status != IXGBE_SUCCESS ||
 228             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 229                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 230                         "CS4227 EEPROM did not load successfully.");
 231                 return IXGBE_ERR_PHY;
 232         }
 233
 234         return IXGBE_SUCCESS;
 235 }
 236
 237 /**
 238  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 239  * @hw: pointer to hardware structure
 240  **/
 241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 242 {
 243         s32 status = IXGBE_SUCCESS;
 244         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 245         u16 value = 0;
 246         u8 retry;
 247
 248         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 249                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 250                 if (status != IXGBE_SUCCESS) {
 251                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 252                                 "semaphore failed with %d", status);
 253                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 254                         continue;
 255                 }
 256
 257                 /* Get status of reset flow. */
 258                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 259
 260                 if (status == IXGBE_SUCCESS &&
 261                     value == IXGBE_CS4227_RESET_COMPLETE)
 262                         goto out;
 263
 264                 if (status != IXGBE_SUCCESS ||
 265                     value != IXGBE_CS4227_RESET_PENDING)
 266                         break;
 267
 268                 /* Reset is pending. Wait and check again. */
 269                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 270                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 271         }
 272
 273         /* If still pending, assume other instance failed. */
 274         if (retry == IXGBE_CS4227_RETRIES) {
 275                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 276                 if (status != IXGBE_SUCCESS) {
 277                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 278                                       "semaphore failed with %d", status);
 279                         return;
 280                 }
 281         }
 282
 283         /* Reset the CS4227. */
 284         status = ixgbe_reset_cs4227(hw);
 285         if (status != IXGBE_SUCCESS) {
 286                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 287                         "CS4227 reset failed: %d", status);
 288                 goto out;
 289         }
 290
 291         /* Reset takes so long, temporarily release semaphore in case the
 292          * other driver instance is waiting for the reset indication.
 293          */
 294         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 295                            IXGBE_CS4227_RESET_PENDING);
 296         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 297         msec_delay(10);
 298         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 299         if (status != IXGBE_SUCCESS) {
 300                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 301                         "semaphore failed with %d", status);
 302                 return;
 303         }
 304
 305         /* Record completion for next time. */
 306         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 307                 IXGBE_CS4227_RESET_COMPLETE);
 308
 309 out:
 310         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 311         msec_delay(hw->eeprom.semaphore_delay);
 312 }
 313
 314 /**
 315  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 316  * @hw: pointer to hardware structure
 317  **/
 318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 319 {
 320         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 321
 322         if (hw->bus.lan_id) {
 323                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 324                 esdp |= IXGBE_ESDP_SDP1_DIR;
 325         }
 326         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 327         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 328         IXGBE_WRITE_FLUSH(hw);
 329 }
 330
 331 /**
 332  * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
 333  * @hw: pointer to hardware structure
 334  * @reg_addr: 32 bit address of PHY register to read
 335  * @dev_type: always unused
 336  * @phy_data: Pointer to read data from PHY register
 337  */
 338 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 339                                      u32 dev_type, u16 *phy_data)
 340 {
 341         u32 i, data, command;
 342         UNREFERENCED_1PARAMETER(dev_type);
 343
 344         /* Setup and write the read command */
 345         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 346                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 347                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
 348                   IXGBE_MSCA_MDI_COMMAND;
 349
 350         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 351
 352         /* Check every 10 usec to see if the access completed.
 353          * The MDI Command bit will clear when the operation is
 354          * complete
 355          */
 356         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 357                 usec_delay(10);
 358
 359                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 360                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 361                         break;
 362         }
 363
 364         if (command & IXGBE_MSCA_MDI_COMMAND) {
 365                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 366                               "PHY read command did not complete.\n");
 367                 return IXGBE_ERR_PHY;
 368         }
 369
 370         /* Read operation is complete.  Get the data from MSRWD */
 371         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 372         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 373         *phy_data = (u16)data;
 374
 375         return IXGBE_SUCCESS;
 376 }
 377
 378 /**
 379  * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
 380  * @hw: pointer to hardware structure
 381  * @reg_addr: 32 bit PHY register to write
 382  * @dev_type: always unused
 383  * @phy_data: Data to write to the PHY register
 384  */
 385 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 386                                       u32 dev_type, u16 phy_data)
 387 {
 388         u32 i, command;
 389         UNREFERENCED_1PARAMETER(dev_type);
 390
 391         /* Put the data in the MDI single read and write data register*/
 392         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 393
 394         /* Setup and write the write command */
 395         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 396                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 397                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
 398                   IXGBE_MSCA_MDI_COMMAND;
 399
 400         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 401
 402         /* Check every 10 usec to see if the access completed.
 403          * The MDI Command bit will clear when the operation is
 404          * complete
 405          */
 406         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 407                 usec_delay(10);
 408
 409                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 410                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 411                         break;
 412         }
 413
 414         if (command & IXGBE_MSCA_MDI_COMMAND) {
 415                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 416                               "PHY write cmd didn't complete\n");
 417                 return IXGBE_ERR_PHY;
 418         }
 419
 420         return IXGBE_SUCCESS;
 421 }
 422
 423 /**
 424  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 425  * @hw: pointer to hardware structure
 426  *
 427  * Returns error code
 428  */
 429 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 430 {
 431         switch (hw->device_id) {
 432         case IXGBE_DEV_ID_X550EM_A_SFP:
 433                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
 434                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
 435                 if (hw->bus.lan_id)
 436                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 437                 else
 438                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 439                 return ixgbe_identify_module_generic(hw);
 440         case IXGBE_DEV_ID_X550EM_X_SFP:
 441                 /* set up for CS4227 usage */
 442                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 443                 ixgbe_setup_mux_ctl(hw);
 444                 ixgbe_check_cs4227(hw);
 445                 /* Fallthrough */
 446
 447         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 448                 return ixgbe_identify_module_generic(hw);
 449                 break;
 450         case IXGBE_DEV_ID_X550EM_X_KX4:
 451                 hw->phy.type = ixgbe_phy_x550em_kx4;
 452                 break;
 453         case IXGBE_DEV_ID_X550EM_X_KR:
 454         case IXGBE_DEV_ID_X550EM_A_KR:
 455         case IXGBE_DEV_ID_X550EM_A_KR_L:
 456                 hw->phy.type = ixgbe_phy_x550em_kr;
 457                 break;
 458         case IXGBE_DEV_ID_X550EM_A_10G_T:
 459                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
 460                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
 461        /* Fallthrough to ixgbe_identify_phy_generic */
 462         case IXGBE_DEV_ID_X550EM_A_1G_T:
 463         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 464         case IXGBE_DEV_ID_X550EM_X_1G_T:
 465         case IXGBE_DEV_ID_X550EM_X_10G_T:
 466                 return ixgbe_identify_phy_generic(hw);
 467         default:
 468                 break;
 469         }
 470         return IXGBE_SUCCESS;
 471 }
 472
 473 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 474                                      u32 device_type, u16 *phy_data)
 475 {
 476         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 477         return IXGBE_NOT_IMPLEMENTED;
 478 }
 479
 480 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 481                                       u32 device_type, u16 phy_data)
 482 {
 483         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 484         return IXGBE_NOT_IMPLEMENTED;
 485 }
 486
 487 /**
 488  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 489  * @hw: pointer to the hardware structure
 490  * @addr: I2C bus address to read from
 491  * @reg: I2C device register to read from
 492  * @val: pointer to location to receive read value
 493  *
 494  * Returns an error code on error.
 495  **/
 496 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 497                                            u16 reg, u16 *val)
 498 {
 499         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 500 }
 501
 502 /**
 503  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 504  * @hw: pointer to the hardware structure
 505  * @addr: I2C bus address to read from
 506  * @reg: I2C device register to read from
 507  * @val: pointer to location to receive read value
 508  *
 509  * Returns an error code on error.
 510  **/
 511 STATIC s32
 512 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 513                                          u16 reg, u16 *val)
 514 {
 515         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 516 }
 517
 518 /**
 519  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 520  * @hw: pointer to the hardware structure
 521  * @addr: I2C bus address to write to
 522  * @reg: I2C device register to write to
 523  * @val: value to write
 524  *
 525  * Returns an error code on error.
 526  **/
 527 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 528                                             u8 addr, u16 reg, u16 val)
 529 {
 530         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 531 }
 532
 533 /**
 534  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 535  * @hw: pointer to the hardware structure
 536  * @addr: I2C bus address to write to
 537  * @reg: I2C device register to write to
 538  * @val: value to write
 539  *
 540  * Returns an error code on error.
 541  **/
 542 STATIC s32
 543 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 544                                           u8 addr, u16 reg, u16 val)
 545 {
 546         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 547 }
 548
 549 /**
 550 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 551 *  @hw: pointer to hardware structure
 552 *
 553 *  Initialize the function pointers and for MAC type X550EM.
 554 *  Does not touch the hardware.
 555 **/
 556 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 557 {
 558         struct ixgbe_mac_info *mac = &hw->mac;
 559         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 560         struct ixgbe_phy_info *phy = &hw->phy;
 561         s32 ret_val;
 562
 563         DEBUGFUNC("ixgbe_init_ops_X550EM");
 564
 565         /* Similar to X550 so start there. */
 566         ret_val = ixgbe_init_ops_X550(hw);
 567
 568         /* Since this function eventually calls
 569          * ixgbe_init_ops_540 by design, we are setting
 570          * the pointers to NULL explicitly here to overwrite
 571          * the values being set in the x540 function.
 572          */
 573         /* Thermal sensor not supported in x550EM */
 574         mac->ops.get_thermal_sensor_data = NULL;
 575         mac->ops.init_thermal_sensor_thresh = NULL;
 576         mac->thermal_sensor_enabled = false;
 577
 578         /* FCOE not supported in x550EM */
 579         mac->ops.get_san_mac_addr = NULL;
 580         mac->ops.set_san_mac_addr = NULL;
 581         mac->ops.get_wwn_prefix = NULL;
 582         mac->ops.get_fcoe_boot_status = NULL;
 583
 584         /* IPsec not supported in x550EM */
 585         mac->ops.disable_sec_rx_path = NULL;
 586         mac->ops.enable_sec_rx_path = NULL;
 587
 588         /* AUTOC register is not present in x550EM. */
 589         mac->ops.prot_autoc_read = NULL;
 590         mac->ops.prot_autoc_write = NULL;
 591
 592         /* X550EM bus type is internal*/
 593         hw->bus.type = ixgbe_bus_type_internal;
 594         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 595
 596
 597         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 598         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 599         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 600         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 601         mac->ops.get_supported_physical_layer =
 602                                     ixgbe_get_supported_physical_layer_X550em;
 603
 604         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 605                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 606         else
 607                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 608
 609         switch (hw->device_id) {
 610         case IXGBE_DEV_ID_X550EM_X_KR:
 611         case IXGBE_DEV_ID_X550EM_A_KR:
 612         case IXGBE_DEV_ID_X550EM_A_KR_L:
 613                 break;
 614         default:
 615                 mac->ops.setup_eee = NULL;
 616         }
 617
 618         /* PHY */
 619         phy->ops.init = ixgbe_init_phy_ops_X550em;
 620         phy->ops.identify = ixgbe_identify_phy_x550em;
 621         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 622                 phy->ops.set_phy_power = NULL;
 623
 624
 625         /* EEPROM */
 626         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 627         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 628         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 629         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 630         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 631         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 632         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 633         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 634
 635         return ret_val;
 636 }
 637
 638 /**
 639 *  ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
 640 *  @hw: pointer to hardware structure
 641 *
 642 *  Initialize the function pointers and for MAC type X550EM_a.
 643 *  Does not touch the hardware.
 644 **/
 645 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
 646 {
 647         struct ixgbe_mac_info *mac = &hw->mac;
 648         s32 ret_val;
 649
 650         DEBUGFUNC("ixgbe_init_ops_X550EM_a");
 651
 652         /* Start with generic X550EM init */
 653         ret_val = ixgbe_init_ops_X550EM(hw);
 654
 655         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
 656             hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
 657                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 658                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 659         } else {
 660                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
 661                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
 662         }
 663         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 664         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 665
 666         switch (mac->ops.get_media_type(hw)) {
 667         case ixgbe_media_type_fiber:
 668                 mac->ops.setup_fc = ixgbe_setup_fc_fiber_x550em_a;
 669                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
 670                 break;
 671         case ixgbe_media_type_backplane:
 672                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
 673                 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
 674                 break;
 675         default:
 676                 break;
 677         }
 678
 679         if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T) ||
 680                 (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)) {
 681                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
 682                 mac->ops.setup_fc = ixgbe_setup_fc_sgmii_x550em_a;
 683         }
 684
 685         return ret_val;
 686 }
 687
 688 /**
 689 *  ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
 690 *  @hw: pointer to hardware structure
 691 *
 692 *  Initialize the function pointers and for MAC type X550EM_x.
 693 *  Does not touch the hardware.
 694 **/
 695 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
 696 {
 697         struct ixgbe_mac_info *mac = &hw->mac;
 698         struct ixgbe_link_info *link = &hw->link;
 699         s32 ret_val;
 700
 701         DEBUGFUNC("ixgbe_init_ops_X550EM_x");
 702
 703         /* Start with generic X550EM init */
 704         ret_val = ixgbe_init_ops_X550EM(hw);
 705
 706         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 707         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 708         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 709         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 710         link->ops.read_link = ixgbe_read_i2c_combined_generic;
 711         link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
 712         link->ops.write_link = ixgbe_write_i2c_combined_generic;
 713         link->ops.write_link_unlocked =
 714                                       ixgbe_write_i2c_combined_generic_unlocked;
 715         link->addr = IXGBE_CS4227;
 716
 717         return ret_val;
 718 }
 719
 720 /**
 721  *  ixgbe_dmac_config_X550
 722  *  @hw: pointer to hardware structure
 723  *
 724  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 725  *  When disabling dmac, dmac enable dmac bit is cleared.
 726  **/
 727 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 728 {
 729         u32 reg, high_pri_tc;
 730
 731         DEBUGFUNC("ixgbe_dmac_config_X550");
 732
 733         /* Disable DMA coalescing before configuring */
 734         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 735         reg &= ~IXGBE_DMACR_DMAC_EN;
 736         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 737
 738         /* Disable DMA Coalescing if the watchdog timer is 0 */
 739         if (!hw->mac.dmac_config.watchdog_timer)
 740                 goto out;
 741
 742         ixgbe_dmac_config_tcs_X550(hw);
 743
 744         /* Configure DMA Coalescing Control Register */
 745         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 746
 747         /* Set the watchdog timer in units of 40.96 usec */
 748         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 749         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 750
 751         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 752         /* If fcoe is enabled, set high priority traffic class */
 753         if (hw->mac.dmac_config.fcoe_en) {
 754                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 755                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 756                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 757         }
 758         reg |= IXGBE_DMACR_EN_MNG_IND;
 759
 760         /* Enable DMA coalescing after configuration */
 761         reg |= IXGBE_DMACR_DMAC_EN;
 762         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 763
 764 out:
 765         return IXGBE_SUCCESS;
 766 }
 767
 768 /**
 769  *  ixgbe_dmac_config_tcs_X550
 770  *  @hw: pointer to hardware structure
 771  *
 772  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 773  *  be cleared before configuring.
 774  **/
 775 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 776 {
 777         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 778
 779         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 780
 781         /* Configure DMA coalescing enabled */
 782         switch (hw->mac.dmac_config.link_speed) {
 783         case IXGBE_LINK_SPEED_10_FULL:
 784         case IXGBE_LINK_SPEED_100_FULL:
 785                 pb_headroom = IXGBE_DMACRXT_100M;
 786                 break;
 787         case IXGBE_LINK_SPEED_1GB_FULL:
 788                 pb_headroom = IXGBE_DMACRXT_1G;
 789                 break;
 790         default:
 791                 pb_headroom = IXGBE_DMACRXT_10G;
 792                 break;
 793         }
 794
 795         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 796                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 797
 798         /* Set the per Rx packet buffer receive threshold */
 799         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 800                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 801                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 802
 803                 if (tc < hw->mac.dmac_config.num_tcs) {
 804                         /* Get Rx PB size */
 805                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 806                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 807                                 IXGBE_RXPBSIZE_SHIFT;
 808
 809                         /* Calculate receive buffer threshold in kilobytes */
 810                         if (rx_pb_size > pb_headroom)
 811                                 rx_pb_size = rx_pb_size - pb_headroom;
 812                         else
 813                                 rx_pb_size = 0;
 814
 815                         /* Minimum of MFS shall be set for DMCTH */
 816                         reg |= (rx_pb_size > maxframe_size_kb) ?
 817                                 rx_pb_size : maxframe_size_kb;
 818                 }
 819                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 820         }
 821         return IXGBE_SUCCESS;
 822 }
 823
 824 /**
 825  *  ixgbe_dmac_update_tcs_X550
 826  *  @hw: pointer to hardware structure
 827  *
 828  *  Disables dmac, updates per TC settings, and then enables dmac.
 829  **/
 830 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 831 {
 832         u32 reg;
 833
 834         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 835
 836         /* Disable DMA coalescing before configuring */
 837         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 838         reg &= ~IXGBE_DMACR_DMAC_EN;
 839         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 840
 841         ixgbe_dmac_config_tcs_X550(hw);
 842
 843         /* Enable DMA coalescing after configuration */
 844         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 845         reg |= IXGBE_DMACR_DMAC_EN;
 846         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 847
 848         return IXGBE_SUCCESS;
 849 }
 850
 851 /**
 852  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 853  *  @hw: pointer to hardware structure
 854  *
 855  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 856  *  ixgbe_hw struct in order to set up EEPROM access.
 857  **/
 858 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 859 {
 860         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 861         u32 eec;
 862         u16 eeprom_size;
 863
 864         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 865
 866         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 867                 eeprom->semaphore_delay = 10;
 868                 eeprom->type = ixgbe_flash;
 869
 870                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 871                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 872                                     IXGBE_EEC_SIZE_SHIFT);
 873                 eeprom->word_size = 1 << (eeprom_size +
 874                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 875
 876                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 877                           eeprom->type, eeprom->word_size);
 878         }
 879
 880         return IXGBE_SUCCESS;
 881 }
 882
 883 /**
 884  * ixgbe_enable_eee_x550 - Enable EEE support
 885  * @hw: pointer to hardware structure
 886  */
 887 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
 888 {
 889         u16 autoneg_eee_reg;
 890         u32 link_reg;
 891         s32 status;
 892
 893         if (hw->mac.type == ixgbe_mac_X550) {
 894                 /* Advertise EEE capability */
 895                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 896                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 897                                      &autoneg_eee_reg);
 898
 899                 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 900                                     IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 901                                     IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 902
 903                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 904                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 905                                       autoneg_eee_reg);
 906                 return IXGBE_SUCCESS;
 907         }
 908
 909         switch (hw->device_id) {
 910         case IXGBE_DEV_ID_X550EM_X_KR:
 911         case IXGBE_DEV_ID_X550EM_A_KR:
 912         case IXGBE_DEV_ID_X550EM_A_KR_L:
 913                 status = hw->mac.ops.read_iosf_sb_reg(hw,
 914                                      IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 915                                      IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 916                 if (status != IXGBE_SUCCESS)
 917                         return status;
 918
 919                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 920                         IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 921
 922                 /* Don't advertise FEC capability when EEE enabled. */
 923                 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 924
 925                 status = hw->mac.ops.write_iosf_sb_reg(hw,
 926                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 927                                       IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 928                 if (status != IXGBE_SUCCESS)
 929                         return status;
 930                 break;
 931         default:
 932                 break;
 933         }
 934
 935         return IXGBE_SUCCESS;
 936 }
 937
 938 /**
 939  * ixgbe_disable_eee_x550 - Disable EEE support
 940  * @hw: pointer to hardware structure
 941  */
 942 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
 943 {
 944         u16 autoneg_eee_reg;
 945         u32 link_reg;
 946         s32 status;
 947
 948         if (hw->mac.type == ixgbe_mac_X550) {
 949                 /* Disable advertised EEE capability */
 950                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 951                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 952                                      &autoneg_eee_reg);
 953
 954                 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 955                                      IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 956                                      IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 957
 958                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 959                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 960                                       autoneg_eee_reg);
 961                 return IXGBE_SUCCESS;
 962         }
 963
 964         switch (hw->device_id) {
 965         case IXGBE_DEV_ID_X550EM_X_KR:
 966         case IXGBE_DEV_ID_X550EM_A_KR:
 967         case IXGBE_DEV_ID_X550EM_A_KR_L:
 968                 status = hw->mac.ops.read_iosf_sb_reg(hw,
 969                                      IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 970                                      IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 971                 if (status != IXGBE_SUCCESS)
 972                         return status;
 973
 974                 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 975                               IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 976
 977                 /* Advertise FEC capability when EEE is disabled. */
 978                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 979
 980                 status = hw->mac.ops.write_iosf_sb_reg(hw,
 981                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 982                                       IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 983                 if (status != IXGBE_SUCCESS)
 984                         return status;
 985                 break;
 986         default:
 987                 break;
 988         }
 989
 990         return IXGBE_SUCCESS;
 991 }
 992
 993 /**
 994  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 995  *  @hw: pointer to the HW structure
 996  *  @enable_eee: boolean flag to enable EEE
 997  *
 998  *  Enable/disable EEE based on enable_eee flag.
 999  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
1000  *  are modified.
1001  *
1002  **/
1003 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
1004 {
1005         s32 status;
1006         u32 eeer;
1007
1008         DEBUGFUNC("ixgbe_setup_eee_X550");
1009
1010         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
1011         /* Enable or disable EEE per flag */
1012         if (enable_eee) {
1013                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1014
1015                 /* Not supported on first revision of X550EM_x. */
1016                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1017                     !(IXGBE_FUSES0_REV_MASK &
1018                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1019                         return IXGBE_SUCCESS;
1020                 status = ixgbe_enable_eee_x550(hw);
1021                 if (status)
1022                         return status;
1023         } else {
1024                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1025
1026                 status = ixgbe_disable_eee_x550(hw);
1027                 if (status)
1028                         return status;
1029         }
1030         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1031
1032         return IXGBE_SUCCESS;
1033 }
1034
1035 /**
1036  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1037  * @hw: pointer to hardware structure
1038  * @enable: enable or disable source address pruning
1039  * @pool: Rx pool to set source address pruning for
1040  **/
1041 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1042                                            unsigned int pool)
1043 {
1044         u64 pfflp;
1045
1046         /* max rx pool is 63 */
1047         if (pool > 63)
1048                 return;
1049
1050         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1051         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1052
1053         if (enable)
1054                 pfflp |= (1ULL << pool);
1055         else
1056                 pfflp &= ~(1ULL << pool);
1057
1058         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1059         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1060 }
1061
1062 /**
1063  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1064  *  @hw: pointer to hardware structure
1065  *  @enable: enable or disable switch for Ethertype anti-spoofing
1066  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1067  *
1068  **/
1069 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1070                 bool enable, int vf)
1071 {
1072         int vf_target_reg = vf >> 3;
1073         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1074         u32 pfvfspoof;
1075
1076         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1077
1078         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1079         if (enable)
1080                 pfvfspoof |= (1 << vf_target_shift);
1081         else
1082                 pfvfspoof &= ~(1 << vf_target_shift);
1083
1084         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1085 }
1086
1087 /**
1088  * ixgbe_iosf_wait - Wait for IOSF command completion
1089  * @hw: pointer to hardware structure
1090  * @ctrl: pointer to location to receive final IOSF control value
1091  *
1092  * Returns failing status on timeout
1093  *
1094  * Note: ctrl can be NULL if the IOSF control register value is not needed
1095  **/
1096 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1097 {
1098         u32 i, command = 0;
1099
1100         /* Check every 10 usec to see if the address cycle completed.
1101          * The SB IOSF BUSY bit will clear when the operation is
1102          * complete
1103          */
1104         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1105                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1106                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1107                         break;
1108                 usec_delay(10);
1109         }
1110         if (ctrl)
1111                 *ctrl = command;
1112         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1113                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1114                 return IXGBE_ERR_PHY;
1115         }
1116
1117         return IXGBE_SUCCESS;
1118 }
1119
1120 /**
1121  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1122  *  of the IOSF device
1123  *  @hw: pointer to hardware structure
1124  *  @reg_addr: 32 bit PHY register to write
1125  *  @device_type: 3 bit device type
1126  *  @data: Data to write to the register
1127  **/
1128 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1129                             u32 device_type, u32 data)
1130 {
1131         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1132         u32 command, error;
1133         s32 ret;
1134
1135         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1136         if (ret != IXGBE_SUCCESS)
1137                 return ret;
1138
1139         ret = ixgbe_iosf_wait(hw, NULL);
1140         if (ret != IXGBE_SUCCESS)
1141                 goto out;
1142
1143         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1144                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1145
1146         /* Write IOSF control register */
1147         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1148
1149         /* Write IOSF data register */
1150         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1151
1152         ret = ixgbe_iosf_wait(hw, &command);
1153
1154         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1155                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1156                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1157                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1158                               "Failed to write, error %x\n", error);
1159                 ret = IXGBE_ERR_PHY;
1160         }
1161
1162 out:
1163         ixgbe_release_swfw_semaphore(hw, gssr);
1164         return ret;
1165 }
1166
1167 /**
1168  *  ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1169  *  @hw: pointer to hardware structure
1170  *  @reg_addr: 32 bit PHY register to write
1171  *  @device_type: 3 bit device type
1172  *  @data: Pointer to read data from the register
1173  **/
1174 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1175                            u32 device_type, u32 *data)
1176 {
1177         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1178         u32 command, error;
1179         s32 ret;
1180
1181         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1182         if (ret != IXGBE_SUCCESS)
1183                 return ret;
1184
1185         ret = ixgbe_iosf_wait(hw, NULL);
1186         if (ret != IXGBE_SUCCESS)
1187                 goto out;
1188
1189         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1190                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1191
1192         /* Write IOSF control register */
1193         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1194
1195         ret = ixgbe_iosf_wait(hw, &command);
1196
1197         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1198                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1199                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1200                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1201                                 "Failed to read, error %x\n", error);
1202                 ret = IXGBE_ERR_PHY;
1203         }
1204
1205         if (ret == IXGBE_SUCCESS)
1206                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1207
1208 out:
1209         ixgbe_release_swfw_semaphore(hw, gssr);
1210         return ret;
1211 }
1212
1213 /**
1214  * ixgbe_get_phy_token - Get the token for shared phy access
1215  * @hw: Pointer to hardware structure
1216  */
1217
1218 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1219 {
1220         struct ixgbe_hic_phy_token_req token_cmd;
1221         s32 status;
1222
1223         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1224         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1225         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1226         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1227         token_cmd.port_number = hw->bus.lan_id;
1228         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1229         token_cmd.pad = 0;
1230         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1231                                               sizeof(token_cmd),
1232                                               IXGBE_HI_COMMAND_TIMEOUT,
1233                                               true);
1234         if (status)
1235                 return status;
1236         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1237                 return IXGBE_SUCCESS;
1238         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1239                 return IXGBE_ERR_FW_RESP_INVALID;
1240
1241         return IXGBE_ERR_TOKEN_RETRY;
1242 }
1243
1244 /**
1245  * ixgbe_put_phy_token - Put the token for shared phy access
1246  * @hw: Pointer to hardware structure
1247  */
1248
1249 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1250 {
1251         struct ixgbe_hic_phy_token_req token_cmd;
1252         s32 status;
1253
1254         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1255         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1256         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1257         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1258         token_cmd.port_number = hw->bus.lan_id;
1259         token_cmd.command_type = FW_PHY_TOKEN_REL;
1260         token_cmd.pad = 0;
1261         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1262                                               sizeof(token_cmd),
1263                                               IXGBE_HI_COMMAND_TIMEOUT,
1264                                               true);
1265         if (status)
1266                 return status;
1267         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1268                 return IXGBE_SUCCESS;
1269
1270         DEBUGOUT("Put PHY Token host interface command failed");
1271         return IXGBE_ERR_FW_RESP_INVALID;
1272 }
1273
1274 /**
1275  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1276  *  of the IOSF device
1277  *  @hw: pointer to hardware structure
1278  *  @reg_addr: 32 bit PHY register to write
1279  *  @device_type: 3 bit device type
1280  *  @data: Data to write to the register
1281  **/
1282 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1283                                   u32 device_type, u32 data)
1284 {
1285         struct ixgbe_hic_internal_phy_req write_cmd;
1286         s32 status;
1287         UNREFERENCED_1PARAMETER(device_type);
1288
1289         memset(&write_cmd, 0, sizeof(write_cmd));
1290         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1291         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1292         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1293         write_cmd.port_number = hw->bus.lan_id;
1294         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1295         write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1296         write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1297
1298         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1299                                               sizeof(write_cmd),
1300                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1301
1302         return status;
1303 }
1304
1305 /**
1306  *  ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1307  *  @hw: pointer to hardware structure
1308  *  @reg_addr: 32 bit PHY register to write
1309  *  @device_type: 3 bit device type
1310  *  @data: Pointer to read data from the register
1311  **/
1312 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1313                                  u32 device_type, u32 *data)
1314 {
1315         union {
1316                 struct ixgbe_hic_internal_phy_req cmd;
1317                 struct ixgbe_hic_internal_phy_resp rsp;
1318         } hic;
1319         s32 status;
1320         UNREFERENCED_1PARAMETER(device_type);
1321
1322         memset(&hic, 0, sizeof(hic));
1323         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1324         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1325         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1326         hic.cmd.port_number = hw->bus.lan_id;
1327         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1328         hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1329
1330         status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1331                                               sizeof(hic.cmd),
1332                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1333
1334         /* Extract the register value from the response. */
1335         *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1336
1337         return status;
1338 }
1339
1340 /**
1341  *  ixgbe_disable_mdd_X550
1342  *  @hw: pointer to hardware structure
1343  *
1344  *  Disable malicious driver detection
1345  **/
1346 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1347 {
1348         u32 reg;
1349
1350         DEBUGFUNC("ixgbe_disable_mdd_X550");
1351
1352         /* Disable MDD for TX DMA and interrupt */
1353         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1354         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1355         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1356
1357         /* Disable MDD for RX and interrupt */
1358         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1359         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1360         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1361 }
1362
1363 /**
1364  *  ixgbe_enable_mdd_X550
1365  *  @hw: pointer to hardware structure
1366  *
1367  *  Enable malicious driver detection
1368  **/
1369 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1370 {
1371         u32 reg;
1372
1373         DEBUGFUNC("ixgbe_enable_mdd_X550");
1374
1375         /* Enable MDD for TX DMA and interrupt */
1376         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1377         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1378         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1379
1380         /* Enable MDD for RX and interrupt */
1381         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1382         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1383         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1384 }
1385
1386 /**
1387  *  ixgbe_restore_mdd_vf_X550
1388  *  @hw: pointer to hardware structure
1389  *  @vf: vf index
1390  *
1391  *  Restore VF that was disabled during malicious driver detection event
1392  **/
1393 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1394 {
1395         u32 idx, reg, num_qs, start_q, bitmask;
1396
1397         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1398
1399         /* Map VF to queues */
1400         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1401         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1402         case IXGBE_MRQC_VMDQRT8TCEN:
1403                 num_qs = 8;  /* 16 VFs / pools */
1404                 bitmask = 0x000000FF;
1405                 break;
1406         case IXGBE_MRQC_VMDQRSS32EN:
1407         case IXGBE_MRQC_VMDQRT4TCEN:
1408                 num_qs = 4;  /* 32 VFs / pools */
1409                 bitmask = 0x0000000F;
1410                 break;
1411         default:            /* 64 VFs / pools */
1412                 num_qs = 2;
1413                 bitmask = 0x00000003;
1414                 break;
1415         }
1416         start_q = vf * num_qs;
1417
1418         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1419         idx = start_q / 32;
1420         reg = 0;
1421         reg |= (bitmask << (start_q % 32));
1422         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1423         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1424 }
1425
1426 /**
1427  *  ixgbe_mdd_event_X550
1428  *  @hw: pointer to hardware structure
1429  *  @vf_bitmap: vf bitmap of malicious vfs
1430  *
1431  *  Handle malicious driver detection event.
1432  **/
1433 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1434 {
1435         u32 wqbr;
1436         u32 i, j, reg, q, shift, vf, idx;
1437
1438         DEBUGFUNC("ixgbe_mdd_event_X550");
1439
1440         /* figure out pool size for mapping to vf's */
1441         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1442         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1443         case IXGBE_MRQC_VMDQRT8TCEN:
1444                 shift = 3;  /* 16 VFs / pools */
1445                 break;
1446         case IXGBE_MRQC_VMDQRSS32EN:
1447         case IXGBE_MRQC_VMDQRT4TCEN:
1448                 shift = 2;  /* 32 VFs / pools */
1449                 break;
1450         default:
1451                 shift = 1;  /* 64 VFs / pools */
1452                 break;
1453         }
1454
1455         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1456         for (i = 0; i < 4; i++) {
1457                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1458                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1459
1460                 if (!wqbr)
1461                         continue;
1462
1463                 /* Get malicious queue */
1464                 for (j = 0; j < 32 && wqbr; j++) {
1465
1466                         if (!(wqbr & (1 << j)))
1467                                 continue;
1468
1469                         /* Get queue from bitmask */
1470                         q = j + (i * 32);
1471
1472                         /* Map queue to vf */
1473                         vf = (q >> shift);
1474
1475                         /* Set vf bit in vf_bitmap */
1476                         idx = vf / 32;
1477                         vf_bitmap[idx] |= (1 << (vf % 32));
1478                         wqbr &= ~(1 << j);
1479                 }
1480         }
1481 }
1482
1483 /**
1484  *  ixgbe_get_media_type_X550em - Get media type
1485  *  @hw: pointer to hardware structure
1486  *
1487  *  Returns the media type (fiber, copper, backplane)
1488  */
1489 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1490 {
1491         enum ixgbe_media_type media_type;
1492
1493         DEBUGFUNC("ixgbe_get_media_type_X550em");
1494
1495         /* Detect if there is a copper PHY attached. */
1496         switch (hw->device_id) {
1497         case IXGBE_DEV_ID_X550EM_X_KR:
1498         case IXGBE_DEV_ID_X550EM_X_KX4:
1499         case IXGBE_DEV_ID_X550EM_A_KR:
1500         case IXGBE_DEV_ID_X550EM_A_KR_L:
1501                 media_type = ixgbe_media_type_backplane;
1502                 break;
1503         case IXGBE_DEV_ID_X550EM_X_SFP:
1504         case IXGBE_DEV_ID_X550EM_A_SFP:
1505         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1506         case IXGBE_DEV_ID_X550EM_A_QSFP:
1507         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1508                 media_type = ixgbe_media_type_fiber;
1509                 break;
1510         case IXGBE_DEV_ID_X550EM_X_1G_T:
1511         case IXGBE_DEV_ID_X550EM_X_10G_T:
1512         case IXGBE_DEV_ID_X550EM_A_10G_T:
1513                 media_type = ixgbe_media_type_copper;
1514                 break;
1515         case IXGBE_DEV_ID_X550EM_A_SGMII:
1516         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1517                 media_type = ixgbe_media_type_backplane;
1518                 hw->phy.type = ixgbe_phy_sgmii;
1519                 break;
1520         case IXGBE_DEV_ID_X550EM_A_1G_T:
1521         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1522                 media_type = ixgbe_media_type_copper;
1523                 break;
1524         default:
1525                 media_type = ixgbe_media_type_unknown;
1526                 break;
1527         }
1528         return media_type;
1529 }
1530
1531 /**
1532  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1533  *  @hw: pointer to hardware structure
1534  *  @linear: true if SFP module is linear
1535  */
1536 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1537 {
1538         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1539
1540         switch (hw->phy.sfp_type) {
1541         case ixgbe_sfp_type_not_present:
1542                 return IXGBE_ERR_SFP_NOT_PRESENT;
1543         case ixgbe_sfp_type_da_cu_core0:
1544         case ixgbe_sfp_type_da_cu_core1:
1545                 *linear = true;
1546                 break;
1547         case ixgbe_sfp_type_srlr_core0:
1548         case ixgbe_sfp_type_srlr_core1:
1549         case ixgbe_sfp_type_da_act_lmt_core0:
1550         case ixgbe_sfp_type_da_act_lmt_core1:
1551         case ixgbe_sfp_type_1g_sx_core0:
1552         case ixgbe_sfp_type_1g_sx_core1:
1553         case ixgbe_sfp_type_1g_lx_core0:
1554         case ixgbe_sfp_type_1g_lx_core1:
1555                 *linear = false;
1556                 break;
1557         case ixgbe_sfp_type_unknown:
1558         case ixgbe_sfp_type_1g_cu_core0:
1559         case ixgbe_sfp_type_1g_cu_core1:
1560         default:
1561                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1562         }
1563
1564         return IXGBE_SUCCESS;
1565 }
1566
1567 /**
1568  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1569  *  @hw: pointer to hardware structure
1570  *
1571  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1572  **/
1573 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1574 {
1575         s32 status;
1576         bool linear;
1577
1578         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1579
1580         status = ixgbe_identify_module_generic(hw);
1581
1582         if (status != IXGBE_SUCCESS)
1583                 return status;
1584
1585         /* Check if SFP module is supported */
1586         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1587
1588         return status;
1589 }
1590
1591 /**
1592  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1593  *  @hw: pointer to hardware structure
1594  */
1595 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1596 {
1597         s32 status;
1598         bool linear;
1599
1600         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1601
1602         /* Check if SFP module is supported */
1603         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1604
1605         if (status != IXGBE_SUCCESS)
1606                 return status;
1607
1608         ixgbe_init_mac_link_ops_X550em(hw);
1609         hw->phy.ops.reset = NULL;
1610
1611         return IXGBE_SUCCESS;
1612 }
1613
1614 /**
1615  * ixgbe_setup_sgmii - Set up link for sgmii
1616  * @hw: pointer to hardware structure
1617  */
1618 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1619                              bool autoneg_wait)
1620 {
1621         struct ixgbe_mac_info *mac = &hw->mac;
1622         u32 lval, sval;
1623         s32 rc;
1624
1625         rc = mac->ops.read_iosf_sb_reg(hw,
1626                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1627                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1628         if (rc)
1629                 return rc;
1630
1631         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1632         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1633         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1634         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1635         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1636         rc = mac->ops.write_iosf_sb_reg(hw,
1637                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1638                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1639         if (rc)
1640                 return rc;
1641
1642         rc = mac->ops.read_iosf_sb_reg(hw,
1643                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1644                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1645         if (rc)
1646                 return rc;
1647
1648         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1649         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1650         rc = mac->ops.write_iosf_sb_reg(hw,
1651                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1652                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1653         if (rc)
1654                 return rc;
1655
1656         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1657         rc = mac->ops.write_iosf_sb_reg(hw,
1658                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1659                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1660         if (rc)
1661                 return rc;
1662
1663         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1664 }
1665
1666  /**
1667  * ixgbe_setup_sgmii_m88 - Set up link for sgmii with Marvell PHYs
1668  * @hw: pointer to hardware structure
1669  */
1670 STATIC s32 ixgbe_setup_sgmii_m88(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1671                                  bool autoneg_wait)
1672 {
1673         struct ixgbe_mac_info *mac = &hw->mac;
1674         u32 lval, sval;
1675         s32 rc;
1676
1677         rc = mac->ops.read_iosf_sb_reg(hw,
1678                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1679                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1680         if (rc)
1681                 return rc;
1682
1683         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1684         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1685         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1686         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1687         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1688         rc = mac->ops.write_iosf_sb_reg(hw,
1689                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1690                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1691         if (rc)
1692                 return rc;
1693
1694         rc = mac->ops.read_iosf_sb_reg(hw,
1695                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1696                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1697         if (rc)
1698                 return rc;
1699
1700         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1701         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1702         rc = mac->ops.write_iosf_sb_reg(hw,
1703                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1704                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1705         if (rc)
1706                 return rc;
1707
1708         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1709         rc = mac->ops.write_iosf_sb_reg(hw,
1710                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1711                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1712         if (rc)
1713                 return rc;
1714
1715         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1716 }
1717
1718 /**
1719  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1720  *  @hw: pointer to hardware structure
1721  */
1722 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1723 {
1724         struct ixgbe_mac_info *mac = &hw->mac;
1725
1726         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1727
1728         switch (hw->mac.ops.get_media_type(hw)) {
1729         case ixgbe_media_type_fiber:
1730                 /* CS4227 does not support autoneg, so disable the laser control
1731                  * functions for SFP+ fiber
1732                  */
1733                 mac->ops.disable_tx_laser = NULL;
1734                 mac->ops.enable_tx_laser = NULL;
1735                 mac->ops.flap_tx_laser = NULL;
1736                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1737                 mac->ops.set_rate_select_speed =
1738                                         ixgbe_set_soft_rate_select_speed;
1739                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1740                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1741                         mac->ops.setup_mac_link =
1742                                 ixgbe_setup_mac_link_sfp_x550a;
1743                 else
1744                         mac->ops.setup_mac_link =
1745                                 ixgbe_setup_mac_link_sfp_x550em;
1746                 break;
1747         case ixgbe_media_type_copper:
1748                 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1749                         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1750                             hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1751                                 mac->ops.setup_link = ixgbe_setup_sgmii_m88;
1752                         } else {
1753                                 mac->ops.setup_link =
1754                                                   ixgbe_setup_mac_link_t_X550em;
1755                         }
1756                 } else {
1757                         mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1758                         mac->ops.check_link = ixgbe_check_link_t_X550em;
1759                 }
1760                 break;
1761         case ixgbe_media_type_backplane:
1762                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1763                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1764                         mac->ops.setup_link = ixgbe_setup_sgmii;
1765                 break;
1766         default:
1767                 break;
1768         }
1769 }
1770
1771 /**
1772  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1773  *  @hw: pointer to hardware structure
1774  *  @speed: pointer to link speed
1775  *  @autoneg: true when autoneg or autotry is enabled
1776  */
1777 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1778                                        ixgbe_link_speed *speed,
1779                                        bool *autoneg)
1780 {
1781         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1782
1783         /* SFP */
1784         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1785
1786                 /* CS4227 SFP must not enable auto-negotiation */
1787                 *autoneg = false;
1788
1789                 /* Check if 1G SFP module. */
1790                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1791                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1792                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1793                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1794                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1795                         return IXGBE_SUCCESS;
1796                 }
1797
1798                 /* Link capabilities are based on SFP */
1799                 if (hw->phy.multispeed_fiber)
1800                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1801                                  IXGBE_LINK_SPEED_1GB_FULL;
1802                 else
1803                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1804         } else {
1805                 switch (hw->phy.type) {
1806                 case ixgbe_phy_m88:
1807                         *speed = IXGBE_LINK_SPEED_1GB_FULL |
1808                                  IXGBE_LINK_SPEED_100_FULL |
1809                                  IXGBE_LINK_SPEED_10_FULL;
1810                         break;
1811                 case ixgbe_phy_sgmii:
1812                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1813                         break;
1814                 default:
1815                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1816                                  IXGBE_LINK_SPEED_1GB_FULL;
1817                         break;
1818                 }
1819                 *autoneg = true;
1820         }
1821
1822         return IXGBE_SUCCESS;
1823 }
1824
1825 /**
1826  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1827  * @hw: pointer to hardware structure
1828  * @lsc: pointer to boolean flag which indicates whether external Base T
1829  *       PHY interrupt is lsc
1830  *
1831  * Determime if external Base T PHY interrupt cause is high temperature
1832  * failure alarm or link status change.
1833  *
1834  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1835  * failure alarm, else return PHY access status.
1836  */
1837 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1838 {
1839         u32 status;
1840         u16 reg;
1841
1842         *lsc = false;
1843
1844         /* Vendor alarm triggered */
1845         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1846                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1847                                       &reg);
1848
1849         if (status != IXGBE_SUCCESS ||
1850             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1851                 return status;
1852
1853         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1854         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1855                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1856                                       &reg);
1857
1858         if (status != IXGBE_SUCCESS ||
1859             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1860             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1861                 return status;
1862
1863         /* Global alarm triggered */
1864         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1865                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1866                                       &reg);
1867
1868         if (status != IXGBE_SUCCESS)
1869                 return status;
1870
1871         /* If high temperature failure, then return over temp error and exit */
1872         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1873                 /* power down the PHY in case the PHY FW didn't already */
1874                 ixgbe_set_copper_phy_power(hw, false);
1875                 return IXGBE_ERR_OVERTEMP;
1876         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1877                 /*  device fault alarm triggered */
1878                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1879                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1880                                           &reg);
1881
1882                 if (status != IXGBE_SUCCESS)
1883                         return status;
1884
1885                 /* if device fault was due to high temp alarm handle and exit */
1886                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1887                         /* power down the PHY in case the PHY FW didn't */
1888                         ixgbe_set_copper_phy_power(hw, false);
1889                         return IXGBE_ERR_OVERTEMP;
1890                 }
1891         }
1892
1893         /* Vendor alarm 2 triggered */
1894         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1895                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1896
1897         if (status != IXGBE_SUCCESS ||
1898             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1899                 return status;
1900
1901         /* link connect/disconnect event occurred */
1902         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1903                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1904
1905         if (status != IXGBE_SUCCESS)
1906                 return status;
1907
1908         /* Indicate LSC */
1909         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1910                 *lsc = true;
1911
1912         return IXGBE_SUCCESS;
1913 }
1914
1915 /**
1916  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1917  * @hw: pointer to hardware structure
1918  *
1919  * Enable link status change and temperature failure alarm for the external
1920  * Base T PHY
1921  *
1922  * Returns PHY access status
1923  */
1924 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1925 {
1926         u32 status;
1927         u16 reg;
1928         bool lsc;
1929
1930         /* Clear interrupt flags */
1931         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1932
1933         /* Enable link status change alarm */
1934         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1935                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1936
1937         if (status != IXGBE_SUCCESS)
1938                 return status;
1939
1940         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1941
1942         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1943                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1944
1945         if (status != IXGBE_SUCCESS)
1946                 return status;
1947
1948         /* Enable high temperature failure and global fault alarms */
1949         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1950                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1951                                       &reg);
1952
1953         if (status != IXGBE_SUCCESS)
1954                 return status;
1955
1956         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1957                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1958
1959         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1960                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1961                                        reg);
1962
1963         if (status != IXGBE_SUCCESS)
1964                 return status;
1965
1966         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1967         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1968                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1969                                       &reg);
1970
1971         if (status != IXGBE_SUCCESS)
1972                 return status;
1973
1974         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1975                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1976
1977         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1978                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1979                                        reg);
1980
1981         if (status != IXGBE_SUCCESS)
1982                 return status;
1983
1984         /* Enable chip-wide vendor alarm */
1985         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1986                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1987                                       &reg);
1988
1989         if (status != IXGBE_SUCCESS)
1990                 return status;
1991
1992         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1993
1994         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1995                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1996                                        reg);
1997
1998         return status;
1999 }
2000
2001 /**
2002  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2003  *  @hw: pointer to hardware structure
2004  *  @speed: link speed
2005  *
2006  *  Configures the integrated KR PHY.
2007  **/
2008 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2009                                        ixgbe_link_speed speed)
2010 {
2011         s32 status;
2012         u32 reg_val;
2013
2014         status = hw->mac.ops.read_iosf_sb_reg(hw,
2015                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2016                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2017         if (status)
2018                 return status;
2019
2020         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2021         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2022                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2023
2024         /* Advertise 10G support. */
2025         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2026                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2027
2028         /* Advertise 1G support. */
2029         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2030                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2031
2032         /* Restart auto-negotiation. */
2033         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2034         status = hw->mac.ops.write_iosf_sb_reg(hw,
2035                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2036                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2037
2038         return status;
2039 }
2040
2041 /**
2042  * ixgbe_setup_m88 - setup m88 PHY
2043  * @hw: pointer to hardware structure
2044  */
2045 STATIC s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2046 {
2047         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2048         u16 reg;
2049         s32 rc;
2050
2051         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2052                 return IXGBE_SUCCESS;
2053
2054         rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2055         if (rc)
2056                 return rc;
2057
2058         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2059         if (rc)
2060                 goto out;
2061         if (reg & IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN) {
2062                 reg &= ~IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN;
2063                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2064                                           reg);
2065         }
2066
2067         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, &reg);
2068         if (rc)
2069                 goto out;
2070         if (reg & IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN) {
2071                 reg &= ~IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN;
2072                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0,
2073                                           reg);
2074         }
2075
2076         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 2);
2077         if (rc)
2078                 goto out;
2079
2080         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2081                                       &reg);
2082         if (rc)
2083                 goto out;
2084         if (reg & IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN) {
2085                 reg &= ~IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN;
2086                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2087                                           reg);
2088                 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2089                                                0);
2090                 if (rc)
2091                         goto out;
2092                 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2093                                               &reg);
2094                 if (rc)
2095                         goto out;
2096                 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2097                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2098                                           reg);
2099                 usec_delay(50);
2100         } else {
2101                 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2102                                                0);
2103                 if (rc)
2104                         goto out;
2105         }
2106
2107         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2108         if (rc)
2109                 goto out;
2110
2111         if (!(reg & IXGBE_M88E1500_COPPER_CTRL_AN_EN)) {
2112                 reg |= IXGBE_M88E1500_COPPER_CTRL_AN_EN;
2113                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2114                                           reg);
2115         }
2116
2117         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, &reg);
2118         if (rc)
2119                 goto out;
2120         reg &= ~IXGBE_M88E1500_1000T_CTRL_HALF_DUPLEX;
2121         reg &= ~IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2122         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
2123                 reg |= IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2124         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, reg);
2125
2126         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, &reg);
2127         if (rc)
2128                 goto out;
2129         reg &= ~IXGBE_M88E1500_COPPER_AN_T4;
2130         reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_FD;
2131         reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_HD;
2132         reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_FD;
2133         reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_HD;
2134
2135         /* Flow control auto negotiation configuration was moved from here to
2136          * the function ixgbe_setup_fc_sgmii_x550em_a()
2137          */
2138
2139         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
2140                 reg |= IXGBE_M88E1500_COPPER_AN_100TX_FD;
2141         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL)
2142                 reg |= IXGBE_M88E1500_COPPER_AN_10TX_FD;
2143         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, reg);
2144
2145         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2146         if (rc)
2147                 goto out;
2148         reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
2149         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2150
2151
2152         hw->mac.ops.release_swfw_sync(hw, mask);
2153         return rc;
2154
2155 out:
2156         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2157         hw->mac.ops.release_swfw_sync(hw, mask);
2158         return rc;
2159 }
2160
2161 /**
2162  * ixgbe_reset_phy_m88e1500 - Reset m88e1500 PHY
2163  * @hw: pointer to hardware structure
2164  *
2165  * The PHY token must be held when calling this function.
2166  */
2167 static s32 ixgbe_reset_phy_m88e1500(struct ixgbe_hw *hw)
2168 {
2169         u16 reg;
2170         s32 rc;
2171
2172         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2173         if (rc)
2174                 return rc;
2175
2176         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2177         if (rc)
2178                 return rc;
2179
2180         reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2181         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2182
2183         usec_delay(10);
2184
2185         return rc;
2186 }
2187
2188 /**
2189  * ixgbe_reset_phy_m88e1543 - Reset m88e1543 PHY
2190  * @hw: pointer to hardware structure
2191  *
2192  * The PHY token must be held when calling this function.
2193  */
2194 static s32 ixgbe_reset_phy_m88e1543(struct ixgbe_hw *hw)
2195 {
2196         return hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2197 }
2198
2199 /**
2200  * ixgbe_reset_phy_m88 - Reset m88 PHY
2201  * @hw: pointer to hardware structure
2202  */
2203 STATIC s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2204 {
2205         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2206         u16 reg;
2207         s32 rc;
2208
2209         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2210                 return IXGBE_SUCCESS;
2211
2212         rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2213         if (rc)
2214                 return rc;
2215
2216         switch (hw->phy.id) {
2217         case IXGBE_M88E1500_E_PHY_ID:
2218                 rc = ixgbe_reset_phy_m88e1500(hw);
2219                 break;
2220         case IXGBE_M88E1543_E_PHY_ID:
2221                 rc = ixgbe_reset_phy_m88e1543(hw);
2222                 break;
2223         default:
2224                 rc = IXGBE_ERR_PHY;
2225                 break;
2226         }
2227
2228         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2229         if (rc)
2230                 goto out;
2231
2232         reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2233               IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2234               IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2235         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2236         if (rc)
2237                 goto out;
2238
2239         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2240         if (rc)
2241                 goto out;
2242
2243         reg = IXGBE_M88E1500_GEN_CTRL_RESET |
2244               IXGBE_M88E1500_GEN_CTRL_MODE_SGMII_COPPER;
2245         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_GEN_CTRL, 0, reg);
2246         if (rc)
2247                 goto out;
2248
2249         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2250         if (rc)
2251                 goto out;
2252
2253         reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2254               IXGBE_M88E1500_FIBER_CTRL_AN_EN |
2255               IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2256               IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2257         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2258         if (rc)
2259                 goto out;
2260
2261         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2262         if (rc)
2263                 goto out;
2264
2265         reg = (IXGBE_M88E1500_MAC_CTRL_1_DWN_4X <<
2266                IXGBE_M88E1500_MAC_CTRL_1_DWN_SHIFT) |
2267               (IXGBE_M88E1500_MAC_CTRL_1_ED_TM <<
2268                IXGBE_M88E1500_MAC_CTRL_1_ED_SHIFT) |
2269               (IXGBE_M88E1500_MAC_CTRL_1_MDIX_AUTO <<
2270                IXGBE_M88E1500_MAC_CTRL_1_MDIX_SHIFT);
2271         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, reg);
2272         if (rc)
2273                 goto out;
2274
2275         reg = IXGBE_M88E1500_COPPER_CTRL_RESET |
2276               IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2277               IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2278               IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2279               IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB;
2280         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2281         if (rc)
2282                 goto out;
2283
2284         hw->mac.ops.release_swfw_sync(hw, mask);
2285
2286         /* In case of first reset set advertised speeds to default value */
2287         if (!hw->phy.autoneg_advertised)
2288                 hw->phy.autoneg_advertised = IXGBE_LINK_SPEED_1GB_FULL |
2289                                              IXGBE_LINK_SPEED_100_FULL |
2290                                              IXGBE_LINK_SPEED_10_FULL;
2291
2292         return ixgbe_setup_m88(hw);
2293
2294 out:
2295         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2296         hw->mac.ops.release_swfw_sync(hw, mask);
2297         return rc;
2298 }
2299
2300 /**
2301  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2302  *  @hw: pointer to hardware structure
2303  *
2304  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
2305  *  values.
2306  **/
2307 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2308 {
2309         /* Save NW management interface connected on board. This is used
2310          * to determine internal PHY mode.
2311          */
2312         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2313
2314         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2315          * PHY address. This register field was has only been used for X552.
2316          */
2317         if (hw->mac.type == ixgbe_mac_X550EM_a &&
2318             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2319                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2320                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2321                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2322         }
2323
2324         return IXGBE_SUCCESS;
2325 }
2326
2327 /**
2328  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2329  *  @hw: pointer to hardware structure
2330  *
2331  *  Initialize any function pointers that were not able to be
2332  *  set during init_shared_code because the PHY/SFP type was
2333  *  not known.  Perform the SFP init if necessary.
2334  */
2335 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2336 {
2337         struct ixgbe_phy_info *phy = &hw->phy;
2338         s32 ret_val;
2339
2340         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2341
2342         hw->mac.ops.set_lan_id(hw);
2343
2344         ixgbe_read_mng_if_sel_x550em(hw);
2345
2346         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2347                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2348                 ixgbe_setup_mux_ctl(hw);
2349                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2350         }
2351
2352         switch (hw->device_id) {
2353         case IXGBE_DEV_ID_X550EM_A_1G_T:
2354         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2355                 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2356                 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2357                 break;
2358         default:
2359                 break;
2360         }
2361
2362         /* Identify the PHY or SFP module */
2363         ret_val = phy->ops.identify(hw);
2364         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2365                 return ret_val;
2366
2367         /* Setup function pointers based on detected hardware */
2368         ixgbe_init_mac_link_ops_X550em(hw);
2369         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2370                 phy->ops.reset = NULL;
2371
2372         /* Set functions pointers based on phy type */
2373         switch (hw->phy.type) {
2374         case ixgbe_phy_x550em_kx4:
2375                 phy->ops.setup_link = NULL;
2376                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2377                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2378                 break;
2379         case ixgbe_phy_x550em_kr:
2380                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2381                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2382                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2383                 break;
2384         case ixgbe_phy_x550em_ext_t:
2385                 /* If internal link mode is XFI, then setup iXFI internal link,
2386                  * else setup KR now.
2387                  */
2388                 phy->ops.setup_internal_link =
2389                                               ixgbe_setup_internal_phy_t_x550em;
2390
2391                 /* setup SW LPLU only for first revision of X550EM_x */
2392                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2393                     !(IXGBE_FUSES0_REV_MASK &
2394                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2395                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2396
2397                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2398                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2399                 break;
2400         case ixgbe_phy_sgmii:
2401                 phy->ops.setup_link = NULL;
2402                 break;
2403         case ixgbe_phy_m88:
2404                 phy->ops.setup_link = ixgbe_setup_m88;
2405                 phy->ops.reset = ixgbe_reset_phy_m88;
2406                 break;
2407         default:
2408                 break;
2409         }
2410         return ret_val;
2411 }
2412
2413 /**
2414  * ixgbe_set_mdio_speed - Set MDIO clock speed
2415  *  @hw: pointer to hardware structure
2416  */
2417 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2418 {
2419         u32 hlreg0;
2420
2421         switch (hw->device_id) {
2422         case IXGBE_DEV_ID_X550EM_X_10G_T:
2423         case IXGBE_DEV_ID_X550EM_A_SGMII:
2424         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2425         case IXGBE_DEV_ID_X550EM_A_1G_T:
2426         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2427         case IXGBE_DEV_ID_X550EM_A_10G_T:
2428         case IXGBE_DEV_ID_X550EM_A_SFP:
2429         case IXGBE_DEV_ID_X550EM_A_QSFP:
2430                 /* Config MDIO clock speed before the first MDIO PHY access */
2431                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2432                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2433                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2434                 break;
2435         default:
2436                 break;
2437         }
2438 }
2439
2440 /**
2441  *  ixgbe_reset_hw_X550em - Perform hardware reset
2442  *  @hw: pointer to hardware structure
2443  *
2444  *  Resets the hardware by resetting the transmit and receive units, masks
2445  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2446  *  reset.
2447  */
2448 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2449 {
2450         ixgbe_link_speed link_speed;
2451         s32 status;
2452         u32 ctrl = 0;
2453         u32 i;
2454         bool link_up = false;
2455
2456         DEBUGFUNC("ixgbe_reset_hw_X550em");
2457
2458         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2459         status = hw->mac.ops.stop_adapter(hw);
2460         if (status != IXGBE_SUCCESS)
2461                 return status;
2462
2463         /* flush pending Tx transactions */
2464         ixgbe_clear_tx_pending(hw);
2465
2466         ixgbe_set_mdio_speed(hw);
2467
2468         /* PHY ops must be identified and initialized prior to reset */
2469         status = hw->phy.ops.init(hw);
2470
2471         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2472                 return status;
2473
2474         /* start the external PHY */
2475         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2476                 status = ixgbe_init_ext_t_x550em(hw);
2477                 if (status)
2478                         return status;
2479         }
2480
2481         /* Setup SFP module if there is one present. */
2482         if (hw->phy.sfp_setup_needed) {
2483                 status = hw->mac.ops.setup_sfp(hw);
2484                 hw->phy.sfp_setup_needed = false;
2485         }
2486
2487         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2488                 return status;
2489
2490         /* Reset PHY */
2491         if (!hw->phy.reset_disable && hw->phy.ops.reset)
2492                 hw->phy.ops.reset(hw);
2493
2494 mac_reset_top:
2495         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2496          * If link reset is used when link is up, it might reset the PHY when
2497          * mng is using it.  If link is down or the flag to force full link
2498          * reset is set, then perform link reset.
2499          */
2500         ctrl = IXGBE_CTRL_LNK_RST;
2501         if (!hw->force_full_reset) {
2502                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2503                 if (link_up)
2504                         ctrl = IXGBE_CTRL_RST;
2505         }
2506
2507         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2508         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2509         IXGBE_WRITE_FLUSH(hw);
2510
2511         /* Poll for reset bit to self-clear meaning reset is complete */
2512         for (i = 0; i < 10; i++) {
2513                 usec_delay(1);
2514                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2515                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2516                         break;
2517         }
2518
2519         if (ctrl & IXGBE_CTRL_RST_MASK) {
2520                 status = IXGBE_ERR_RESET_FAILED;
2521                 DEBUGOUT("Reset polling failed to complete.\n");
2522         }
2523
2524         msec_delay(50);
2525
2526         /* Double resets are required for recovery from certain error
2527          * conditions.  Between resets, it is necessary to stall to
2528          * allow time for any pending HW events to complete.
2529          */
2530         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2531                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2532                 goto mac_reset_top;
2533         }
2534
2535         /* Store the permanent mac address */
2536         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2537
2538         /* Store MAC address from RAR0, clear receive address registers, and
2539          * clear the multicast table.  Also reset num_rar_entries to 128,
2540          * since we modify this value when programming the SAN MAC address.
2541          */
2542         hw->mac.num_rar_entries = 128;
2543         hw->mac.ops.init_rx_addrs(hw);
2544
2545         ixgbe_set_mdio_speed(hw);
2546
2547         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2548                 ixgbe_setup_mux_ctl(hw);
2549
2550         return status;
2551 }
2552
2553 /**
2554  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2555  * @hw: pointer to hardware structure
2556  */
2557 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2558 {
2559         u32 status;
2560         u16 reg;
2561
2562         status = hw->phy.ops.read_reg(hw,
2563                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2564                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2565                                       &reg);
2566
2567         if (status != IXGBE_SUCCESS)
2568                 return status;
2569
2570         /* If PHY FW reset completed bit is set then this is the first
2571          * SW instance after a power on so the PHY FW must be un-stalled.
2572          */
2573         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2574                 status = hw->phy.ops.read_reg(hw,
2575                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2576                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2577                                         &reg);
2578
2579                 if (status != IXGBE_SUCCESS)
2580                         return status;
2581
2582                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2583
2584                 status = hw->phy.ops.write_reg(hw,
2585                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2586                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2587                                         reg);
2588
2589                 if (status != IXGBE_SUCCESS)
2590                         return status;
2591         }
2592
2593         return status;
2594 }
2595
2596 /**
2597  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2598  *  @hw: pointer to hardware structure
2599  *
2600  *  Configures the integrated KR PHY for X550EM_x.
2601  **/
2602 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2603 {
2604         if (hw->mac.type != ixgbe_mac_X550EM_x)
2605                 return IXGBE_SUCCESS;
2606
2607         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2608 }
2609
2610 /**
2611  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2612  *  @hw: pointer to hardware structure
2613  *
2614  *  Configure the external PHY and the integrated KR PHY for SFP support.
2615  **/
2616 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2617                                     ixgbe_link_speed speed,
2618                                     bool autoneg_wait_to_complete)
2619 {
2620         s32 ret_val;
2621         u16 reg_slice, reg_val;
2622         bool setup_linear = false;
2623         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2624
2625         /* Check if SFP module is supported and linear */
2626         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2627
2628         /* If no SFP module present, then return success. Return success since
2629          * there is no reason to configure CS4227 and SFP not present error is
2630          * not excepted in the setup MAC link flow.
2631          */
2632         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2633                 return IXGBE_SUCCESS;
2634
2635         if (ret_val != IXGBE_SUCCESS)
2636                 return ret_val;
2637
2638         /* Configure internal PHY for KR/KX. */
2639         ixgbe_setup_kr_speed_x550em(hw, speed);
2640
2641         /* Configure CS4227 LINE side to proper mode. */
2642         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2643                     (hw->bus.lan_id << 12);
2644         if (setup_linear)
2645                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2646         else
2647                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2648         ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2649                                           reg_val);
2650         return ret_val;
2651 }
2652
2653 /**
2654  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2655  *  @hw: pointer to hardware structure
2656  *
2657  *  Configure the the integrated PHY for SFP support.
2658  **/
2659 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2660                                    ixgbe_link_speed speed,
2661                                    bool autoneg_wait_to_complete)
2662 {
2663         s32 ret_val;
2664         u16 reg_phy_ext;
2665         bool setup_linear = false;
2666         u32 reg_slice, reg_phy_int, slice_offset;
2667
2668         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2669
2670         /* Check if SFP module is supported and linear */
2671         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2672
2673         /* If no SFP module present, then return success. Return success since
2674          * SFP not present error is not excepted in the setup MAC link flow.
2675          */
2676         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2677                 return IXGBE_SUCCESS;
2678
2679         if (ret_val != IXGBE_SUCCESS)
2680                 return ret_val;
2681
2682         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2683                 /* Configure internal PHY for native SFI */
2684                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2685                                IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2686                                IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
2687
2688                 if (ret_val != IXGBE_SUCCESS)
2689                         return ret_val;
2690
2691                 if (setup_linear) {
2692                         reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
2693                         reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;
2694                 } else {
2695                         reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;
2696                         reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
2697                 }
2698
2699                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2700                                 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2701                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2702
2703                 if (ret_val != IXGBE_SUCCESS)
2704                         return ret_val;
2705
2706                 /* Setup XFI/SFI internal link. */
2707                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2708         } else {
2709                 /* Configure internal PHY for KR/KX. */
2710                 ixgbe_setup_kr_speed_x550em(hw, speed);
2711
2712                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2713                         /* Find Address */
2714                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2715                         return IXGBE_ERR_PHY_ADDR_INVALID;
2716                 }
2717
2718                 /* Get external PHY device id */
2719                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
2720                                        IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2721
2722                 if (ret_val != IXGBE_SUCCESS)
2723                         return ret_val;
2724
2725                 /* When configuring quad port CS4223, the MAC instance is part
2726                  * of the slice offset.
2727                  */
2728                 if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
2729                         slice_offset = (hw->bus.lan_id +
2730                                         (hw->bus.instance_id << 1)) << 12;
2731                 else
2732                         slice_offset = hw->bus.lan_id << 12;
2733
2734                 /* Configure CS4227/CS4223 LINE side to proper mode. */
2735                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2736                 if (setup_linear)
2737                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2738                 else
2739                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2740                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2741                                         IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2742         }
2743         return ret_val;
2744 }
2745
2746 /**
2747  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2748  *  @hw: pointer to hardware structure
2749  *
2750  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2751  **/
2752 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2753 {
2754         struct ixgbe_mac_info *mac = &hw->mac;
2755         s32 status;
2756         u32 reg_val;
2757
2758         /* Disable training protocol FSM. */
2759         status = mac->ops.read_iosf_sb_reg(hw,
2760                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2761                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2762         if (status != IXGBE_SUCCESS)
2763                 return status;
2764         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2765         status = mac->ops.write_iosf_sb_reg(hw,
2766                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2767                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2768         if (status != IXGBE_SUCCESS)
2769                 return status;
2770
2771         /* Disable Flex from training TXFFE. */
2772         status = mac->ops.read_iosf_sb_reg(hw,
2773                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2774                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2775         if (status != IXGBE_SUCCESS)
2776                 return status;
2777         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2778         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2779         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2780         status = mac->ops.write_iosf_sb_reg(hw,
2781                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2782                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2783         if (status != IXGBE_SUCCESS)
2784                 return status;
2785         status = mac->ops.read_iosf_sb_reg(hw,
2786                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2787                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2788         if (status != IXGBE_SUCCESS)
2789                 return status;
2790         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2791         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2792         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2793         status = mac->ops.write_iosf_sb_reg(hw,
2794                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2795                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2796         if (status != IXGBE_SUCCESS)
2797                 return status;
2798
2799         /* Enable override for coefficients. */
2800         status = mac->ops.read_iosf_sb_reg(hw,
2801                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2802                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2803         if (status != IXGBE_SUCCESS)
2804                 return status;
2805         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2806         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2807         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2808         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2809         status = mac->ops.write_iosf_sb_reg(hw,
2810                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2811                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2812         return status;
2813 }
2814
2815 /**
2816  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2817  *  @hw: pointer to hardware structure
2818  *  @speed: the link speed to force
2819  *
2820  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
2821  *  internal and external PHY at a specific speed, without autonegotiation.
2822  **/
2823 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2824 {
2825         struct ixgbe_mac_info *mac = &hw->mac;
2826         s32 status;
2827         u32 reg_val;
2828
2829         /* Disable AN and force speed to 10G Serial. */
2830         status = mac->ops.read_iosf_sb_reg(hw,
2831                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2832                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2833         if (status != IXGBE_SUCCESS)
2834                 return status;
2835
2836         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2837         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2838
2839         /* Select forced link speed for internal PHY. */
2840         switch (*speed) {
2841         case IXGBE_LINK_SPEED_10GB_FULL:
2842                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2843                 break;
2844         case IXGBE_LINK_SPEED_1GB_FULL:
2845                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2846                 break;
2847         default:
2848                 /* Other link speeds are not supported by internal KR PHY. */
2849                 return IXGBE_ERR_LINK_SETUP;
2850         }
2851
2852         status = mac->ops.write_iosf_sb_reg(hw,
2853                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2854                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2855         if (status != IXGBE_SUCCESS)
2856                 return status;
2857
2858         /* Additional configuration needed for x550em_x */
2859         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2860                 status = ixgbe_setup_ixfi_x550em_x(hw);
2861                 if (status != IXGBE_SUCCESS)
2862                         return status;
2863         }
2864
2865         /* Toggle port SW reset by AN reset. */
2866         status = mac->ops.read_iosf_sb_reg(hw,
2867                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2868                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2869         if (status != IXGBE_SUCCESS)
2870                 return status;
2871         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2872         status = mac->ops.write_iosf_sb_reg(hw,
2873                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2874                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2875
2876         return status;
2877 }
2878
2879 /**
2880  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2881  * @hw: address of hardware structure
2882  * @link_up: address of boolean to indicate link status
2883  *
2884  * Returns error code if unable to get link status.
2885  */
2886 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2887 {
2888         u32 ret;
2889         u16 autoneg_status;
2890
2891         *link_up = false;
2892
2893         /* read this twice back to back to indicate current status */
2894         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2895                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2896                                    &autoneg_status);
2897         if (ret != IXGBE_SUCCESS)
2898                 return ret;
2899
2900         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2901                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2902                                    &autoneg_status);
2903         if (ret != IXGBE_SUCCESS)
2904                 return ret;
2905
2906         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2907
2908         return IXGBE_SUCCESS;
2909 }
2910
2911 /**
2912  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2913  * @hw: point to hardware structure
2914  *
2915  * Configures the link between the integrated KR PHY and the external X557 PHY
2916  * The driver will call this function when it gets a link status change
2917  * interrupt from the X557 PHY. This function configures the link speed
2918  * between the PHYs to match the link speed of the BASE-T link.
2919  *
2920  * A return of a non-zero value indicates an error, and the base driver should
2921  * not report link up.
2922  */
2923 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2924 {
2925         ixgbe_link_speed force_speed;
2926         bool link_up;
2927         u32 status;
2928         u16 speed;
2929
2930         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2931                 return IXGBE_ERR_CONFIG;
2932
2933         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2934                 /* If link is down, there is no setup necessary so return  */
2935                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2936                 if (status != IXGBE_SUCCESS)
2937                         return status;
2938
2939                 if (!link_up)
2940                         return IXGBE_SUCCESS;
2941
2942                 status = hw->phy.ops.read_reg(hw,
2943                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2944                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2945                                               &speed);
2946                 if (status != IXGBE_SUCCESS)
2947                         return status;
2948
2949                 /* If link is still down - no setup is required so return */
2950                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2951                 if (status != IXGBE_SUCCESS)
2952                         return status;
2953                 if (!link_up)
2954                         return IXGBE_SUCCESS;
2955
2956                 /* clear everything but the speed and duplex bits */
2957                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2958
2959                 switch (speed) {
2960                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2961                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2962                         break;
2963                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2964                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2965                         break;
2966                 default:
2967                         /* Internal PHY does not support anything else */
2968                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
2969                 }
2970
2971                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2972         } else {
2973                 speed = IXGBE_LINK_SPEED_10GB_FULL |
2974                         IXGBE_LINK_SPEED_1GB_FULL;
2975                 return ixgbe_setup_kr_speed_x550em(hw, speed);
2976         }
2977 }
2978
2979 /**
2980  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2981  *  @hw: pointer to hardware structure
2982  *
2983  *  Configures the integrated KR PHY to use internal loopback mode.
2984  **/
2985 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2986 {
2987         s32 status;
2988         u32 reg_val;
2989
2990         /* Disable AN and force speed to 10G Serial. */
2991         status = hw->mac.ops.read_iosf_sb_reg(hw,
2992                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2993                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2994         if (status != IXGBE_SUCCESS)
2995                 return status;
2996         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2997         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2998         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2999         status = hw->mac.ops.write_iosf_sb_reg(hw,
3000                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3001                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3002         if (status != IXGBE_SUCCESS)
3003                 return status;
3004
3005         /* Set near-end loopback clocks. */
3006         status = hw->mac.ops.read_iosf_sb_reg(hw,
3007                       IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3008                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3009         if (status != IXGBE_SUCCESS)
3010                 return status;
3011         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3012         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3013         status = hw->mac.ops.write_iosf_sb_reg(hw,
3014                        IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3015                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3016         if (status != IXGBE_SUCCESS)
3017                 return status;
3018
3019         /* Set loopback enable. */
3020         status = hw->mac.ops.read_iosf_sb_reg(hw,
3021                       IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3022                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3023         if (status != IXGBE_SUCCESS)
3024                 return status;
3025         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3026         status = hw->mac.ops.write_iosf_sb_reg(hw,
3027                        IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3028                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3029         if (status != IXGBE_SUCCESS)
3030                 return status;
3031
3032         /* Training bypass. */
3033         status = hw->mac.ops.read_iosf_sb_reg(hw,
3034                       IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3035                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3036         if (status != IXGBE_SUCCESS)
3037                 return status;
3038         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3039         status = hw->mac.ops.write_iosf_sb_reg(hw,
3040                        IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3041                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3042
3043         return status;
3044 }
3045
3046 /**
3047  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3048  *  assuming that the semaphore is already obtained.
3049  *  @hw: pointer to hardware structure
3050  *  @offset: offset of  word in the EEPROM to read
3051  *  @data: word read from the EEPROM
3052  *
3053  *  Reads a 16 bit word from the EEPROM using the hostif.
3054  **/
3055 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3056                                    u16 *data)
3057 {
3058         s32 status;
3059         struct ixgbe_hic_read_shadow_ram buffer;
3060
3061         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
3062         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3063         buffer.hdr.req.buf_lenh = 0;
3064         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3065         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3066
3067         /* convert offset from words to bytes */
3068         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3069         /* one word */
3070         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3071
3072         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3073                                               sizeof(buffer),
3074                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3075
3076         if (status)
3077                 return status;
3078
3079         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3080                                           FW_NVM_DATA_OFFSET);
3081
3082         return 0;
3083 }
3084
3085 /**
3086  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3087  *  @hw: pointer to hardware structure
3088  *  @offset: offset of  word in the EEPROM to read
3089  *  @data: word read from the EEPROM
3090  *
3091  *  Reads a 16 bit word from the EEPROM using the hostif.
3092  **/
3093 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3094                               u16 *data)
3095 {
3096         s32 status = IXGBE_SUCCESS;
3097
3098         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3099
3100         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3101             IXGBE_SUCCESS) {
3102                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
3103                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3104         } else {
3105                 status = IXGBE_ERR_SWFW_SYNC;
3106         }
3107
3108         return status;
3109 }
3110
3111 /**
3112  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3113  *  @hw: pointer to hardware structure
3114  *  @offset: offset of  word in the EEPROM to read
3115  *  @words: number of words
3116  *  @data: word(s) read from the EEPROM
3117  *
3118  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
3119  **/
3120 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3121                                      u16 offset, u16 words, u16 *data)
3122 {
3123         struct ixgbe_hic_read_shadow_ram buffer;
3124         u32 current_word = 0;
3125         u16 words_to_read;
3126         s32 status;
3127         u32 i;
3128
3129         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3130
3131         /* Take semaphore for the entire operation. */
3132         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3133         if (status) {
3134                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3135                 return status;
3136         }
3137         while (words) {
3138                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3139                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3140                 else
3141                         words_to_read = words;
3142
3143                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3144                 buffer.hdr.req.buf_lenh = 0;
3145                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3146                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3147
3148                 /* convert offset from words to bytes */
3149                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3150                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3151
3152                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3153                                                       sizeof(buffer),
3154                                                       IXGBE_HI_COMMAND_TIMEOUT,
3155                                                       false);
3156
3157                 if (status) {
3158                         DEBUGOUT("Host interface command failed\n");
3159                         goto out;
3160                 }
3161
3162                 for (i = 0; i < words_to_read; i++) {
3163                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3164                                   2 * i;
3165                         u32 value = IXGBE_READ_REG(hw, reg);
3166
3167                         data[current_word] = (u16)(value & 0xffff);
3168                         current_word++;
3169                         i++;
3170                         if (i < words_to_read) {
3171                                 value >>= 16;
3172                                 data[current_word] = (u16)(value & 0xffff);
3173                                 current_word++;
3174                         }
3175                 }
3176                 words -= words_to_read;
3177         }
3178
3179 out:
3180         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3181         return status;
3182 }
3183
3184 /**
3185  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3186  *  @hw: pointer to hardware structure
3187  *  @offset: offset of  word in the EEPROM to write
3188  *  @data: word write to the EEPROM
3189  *
3190  *  Write a 16 bit word to the EEPROM using the hostif.
3191  **/
3192 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3193                                     u16 data)
3194 {
3195         s32 status;
3196         struct ixgbe_hic_write_shadow_ram buffer;
3197
3198         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3199
3200         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3201         buffer.hdr.req.buf_lenh = 0;
3202         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3203         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3204
3205          /* one word */
3206         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3207         buffer.data = data;
3208         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3209
3210         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3211                                               sizeof(buffer),
3212                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3213
3214         return status;
3215 }
3216
3217 /**
3218  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3219  *  @hw: pointer to hardware structure
3220  *  @offset: offset of  word in the EEPROM to write
3221  *  @data: word write to the EEPROM
3222  *
3223  *  Write a 16 bit word to the EEPROM using the hostif.
3224  **/
3225 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3226                                u16 data)
3227 {
3228         s32 status = IXGBE_SUCCESS;
3229
3230         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3231
3232         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3233             IXGBE_SUCCESS) {
3234                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3235                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3236         } else {
3237                 DEBUGOUT("write ee hostif failed to get semaphore");
3238                 status = IXGBE_ERR_SWFW_SYNC;
3239         }
3240
3241         return status;
3242 }
3243
3244 /**
3245  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3246  *  @hw: pointer to hardware structure
3247  *  @offset: offset of  word in the EEPROM to write
3248  *  @words: number of words
3249  *  @data: word(s) write to the EEPROM
3250  *
3251  *  Write a 16 bit word(s) to the EEPROM using the hostif.
3252  **/
3253 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3254                                       u16 offset, u16 words, u16 *data)
3255 {
3256         s32 status = IXGBE_SUCCESS;
3257         u32 i = 0;
3258
3259         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3260
3261         /* Take semaphore for the entire operation. */
3262         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3263         if (status != IXGBE_SUCCESS) {
3264                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3265                 goto out;
3266         }
3267
3268         for (i = 0; i < words; i++) {
3269                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3270                                                          data[i]);
3271
3272                 if (status != IXGBE_SUCCESS) {
3273                         DEBUGOUT("Eeprom buffered write failed\n");
3274                         break;
3275                 }
3276         }
3277
3278         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3279 out:
3280
3281         return status;
3282 }
3283
3284 /**
3285  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3286  * @hw: pointer to hardware structure
3287  * @ptr: pointer offset in eeprom
3288  * @size: size of section pointed by ptr, if 0 first word will be used as size
3289  * @csum: address of checksum to update
3290  *
3291  * Returns error status for any failure
3292  */
3293 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3294                                    u16 size, u16 *csum, u16 *buffer,
3295                                    u32 buffer_size)
3296 {
3297         u16 buf[256];
3298         s32 status;
3299         u16 length, bufsz, i, start;
3300         u16 *local_buffer;
3301
3302         bufsz = sizeof(buf) / sizeof(buf[0]);
3303
3304         /* Read a chunk at the pointer location */
3305         if (!buffer) {
3306                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3307                 if (status) {
3308                         DEBUGOUT("Failed to read EEPROM image\n");
3309                         return status;
3310                 }
3311                 local_buffer = buf;
3312         } else {
3313                 if (buffer_size < ptr)
3314                         return  IXGBE_ERR_PARAM;
3315                 local_buffer = &buffer[ptr];
3316         }
3317
3318         if (size) {
3319                 start = 0;
3320                 length = size;
3321         } else {
3322                 start = 1;
3323                 length = local_buffer[0];
3324
3325                 /* Skip pointer section if length is invalid. */
3326                 if (length == 0xFFFF || length == 0 ||
3327                     (ptr + length) >= hw->eeprom.word_size)
3328                         return IXGBE_SUCCESS;
3329         }
3330
3331         if (buffer && ((u32)start + (u32)length > buffer_size))
3332                 return IXGBE_ERR_PARAM;
3333
3334         for (i = start; length; i++, length--) {
3335                 if (i == bufsz && !buffer) {
3336                         ptr += bufsz;
3337                         i = 0;
3338                         if (length < bufsz)
3339                                 bufsz = length;
3340
3341                         /* Read a chunk at the pointer location */
3342                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3343                                                                   bufsz, buf);
3344                         if (status) {
3345                                 DEBUGOUT("Failed to read EEPROM image\n");
3346                                 return status;
3347                         }
3348                 }
3349                 *csum += local_buffer[i];
3350         }
3351         return IXGBE_SUCCESS;
3352 }
3353
3354 /**
3355  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3356  *  @hw: pointer to hardware structure
3357  *  @buffer: pointer to buffer containing calculated checksum
3358  *  @buffer_size: size of buffer
3359  *
3360  *  Returns a negative error code on error, or the 16-bit checksum
3361  **/
3362 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3363 {
3364         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3365         u16 *local_buffer;
3366         s32 status;
3367         u16 checksum = 0;
3368         u16 pointer, i, size;
3369
3370         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3371
3372         hw->eeprom.ops.init_params(hw);
3373
3374         if (!buffer) {
3375                 /* Read pointer area */
3376                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3377                                                      IXGBE_EEPROM_LAST_WORD + 1,
3378                                                      eeprom_ptrs);
3379                 if (status) {
3380                         DEBUGOUT("Failed to read EEPROM image\n");
3381                         return status;
3382                 }
3383                 local_buffer = eeprom_ptrs;
3384         } else {
3385                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3386                         return IXGBE_ERR_PARAM;
3387                 local_buffer = buffer;
3388         }
3389
3390         /*
3391          * For X550 hardware include 0x0-0x41 in the checksum, skip the
3392          * checksum word itself
3393          */
3394         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3395                 if (i != IXGBE_EEPROM_CHECKSUM)
3396                         checksum += local_buffer[i];
3397
3398         /*
3399          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
3400          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3401          */
3402         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3403                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3404                         continue;
3405
3406                 pointer = local_buffer[i];
3407
3408                 /* Skip pointer section if the pointer is invalid. */
3409                 if (pointer == 0xFFFF || pointer == 0 ||
3410                     pointer >= hw->eeprom.word_size)
3411                         continue;
3412
3413                 switch (i) {
3414                 case IXGBE_PCIE_GENERAL_PTR:
3415                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3416                         break;
3417                 case IXGBE_PCIE_CONFIG0_PTR:
3418                 case IXGBE_PCIE_CONFIG1_PTR:
3419                         size = IXGBE_PCIE_CONFIG_SIZE;
3420                         break;
3421                 default:
3422                         size = 0;
3423                         break;
3424                 }
3425
3426                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3427                                                 buffer, buffer_size);
3428                 if (status)
3429                         return status;
3430         }
3431
3432         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3433
3434         return (s32)checksum;
3435 }
3436
3437 /**
3438  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3439  *  @hw: pointer to hardware structure
3440  *
3441  *  Returns a negative error code on error, or the 16-bit checksum
3442  **/
3443 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3444 {
3445         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3446 }
3447
3448 /**
3449  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3450  *  @hw: pointer to hardware structure
3451  *  @checksum_val: calculated checksum
3452  *
3453  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3454  *  caller does not need checksum_val, the value can be NULL.
3455  **/
3456 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3457 {
3458         s32 status;
3459         u16 checksum;
3460         u16 read_checksum = 0;
3461
3462         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3463
3464         /* Read the first word from the EEPROM. If this times out or fails, do
3465          * not continue or we could be in for a very long wait while every
3466          * EEPROM read fails
3467          */
3468         status = hw->eeprom.ops.read(hw, 0, &checksum);
3469         if (status) {
3470                 DEBUGOUT("EEPROM read failed\n");
3471                 return status;
3472         }
3473
3474         status = hw->eeprom.ops.calc_checksum(hw);
3475         if (status < 0)
3476                 return status;
3477
3478         checksum = (u16)(status & 0xffff);
3479
3480         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3481                                            &read_checksum);
3482         if (status)
3483                 return status;
3484
3485         /* Verify read checksum from EEPROM is the same as
3486          * calculated checksum
3487          */
3488         if (read_checksum != checksum) {
3489                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3490                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3491                              "Invalid EEPROM checksum");
3492         }
3493
3494         /* If the user cares, return the calculated checksum */
3495         if (checksum_val)
3496                 *checksum_val = checksum;
3497
3498         return status;
3499 }
3500
3501 /**
3502  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3503  * @hw: pointer to hardware structure
3504  *
3505  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3506  * checksum and updates the EEPROM and instructs the hardware to update
3507  * the flash.
3508  **/
3509 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3510 {
3511         s32 status;
3512         u16 checksum = 0;
3513
3514         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3515
3516         /* Read the first word from the EEPROM. If this times out or fails, do
3517          * not continue or we could be in for a very long wait while every
3518          * EEPROM read fails
3519          */
3520         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3521         if (status) {
3522                 DEBUGOUT("EEPROM read failed\n");
3523                 return status;
3524         }
3525
3526         status = ixgbe_calc_eeprom_checksum_X550(hw);
3527         if (status < 0)
3528                 return status;
3529
3530         checksum = (u16)(status & 0xffff);
3531
3532         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3533                                             checksum);
3534         if (status)
3535                 return status;
3536
3537         status = ixgbe_update_flash_X550(hw);
3538
3539         return status;
3540 }
3541
3542 /**
3543  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3544  *  @hw: pointer to hardware structure
3545  *
3546  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3547  **/
3548 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3549 {
3550         s32 status = IXGBE_SUCCESS;
3551         union ixgbe_hic_hdr2 buffer;
3552
3553         DEBUGFUNC("ixgbe_update_flash_X550");
3554
3555         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3556         buffer.req.buf_lenh = 0;
3557         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3558         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3559
3560         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3561                                               sizeof(buffer),
3562                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3563
3564         return status;
3565 }
3566
3567 /**
3568  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3569  *  @hw: pointer to hardware structure
3570  *
3571  *  Determines physical layer capabilities of the current configuration.
3572  **/
3573 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3574 {
3575         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3576         u16 ext_ability = 0;
3577
3578         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3579
3580         hw->phy.ops.identify(hw);
3581
3582         switch (hw->phy.type) {
3583         case ixgbe_phy_x550em_kr:
3584                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3585                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3586                 break;
3587         case ixgbe_phy_x550em_kx4:
3588                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3589                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3590                 break;
3591         case ixgbe_phy_x550em_ext_t:
3592                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3593                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3594                                      &ext_ability);
3595                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3596                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3597                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3598                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3599                 break;
3600         default:
3601                 break;
3602         }
3603
3604         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3605                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3606
3607         return physical_layer;
3608 }
3609
3610 /**
3611  * ixgbe_get_bus_info_x550em - Set PCI bus info
3612  * @hw: pointer to hardware structure
3613  *
3614  * Sets bus link width and speed to unknown because X550em is
3615  * not a PCI device.
3616  **/
3617 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3618 {
3619
3620         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3621
3622         hw->bus.width = ixgbe_bus_width_unknown;
3623         hw->bus.speed = ixgbe_bus_speed_unknown;
3624
3625         hw->mac.ops.set_lan_id(hw);
3626
3627         return IXGBE_SUCCESS;
3628 }
3629
3630 /**
3631  * ixgbe_disable_rx_x550 - Disable RX unit
3632  *
3633  * Enables the Rx DMA unit for x550
3634  **/
3635 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3636 {
3637         u32 rxctrl, pfdtxgswc;
3638         s32 status;
3639         struct ixgbe_hic_disable_rxen fw_cmd;
3640
3641         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3642
3643         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3644         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3645                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3646                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3647                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3648                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3649                         hw->mac.set_lben = true;
3650                 } else {
3651                         hw->mac.set_lben = false;
3652                 }
3653
3654                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3655                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3656                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3657                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3658
3659                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3660                                         sizeof(struct ixgbe_hic_disable_rxen),
3661                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3662
3663                 /* If we fail - disable RX using register write */
3664                 if (status) {
3665                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3666                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3667                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3668                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3669                         }
3670                 }
3671         }
3672 }
3673
3674 /**
3675  * ixgbe_enter_lplu_x550em - Transition to low power states
3676  *  @hw: pointer to hardware structure
3677  *
3678  * Configures Low Power Link Up on transition to low power states
3679  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3680  * X557 PHY immediately prior to entering LPLU.
3681  **/
3682 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3683 {
3684         u16 an_10g_cntl_reg, autoneg_reg, speed;
3685         s32 status;
3686         ixgbe_link_speed lcd_speed;
3687         u32 save_autoneg;
3688         bool link_up;
3689
3690         /* SW LPLU not required on later HW revisions. */
3691         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3692             (IXGBE_FUSES0_REV_MASK &
3693              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3694                 return IXGBE_SUCCESS;
3695
3696         /* If blocked by MNG FW, then don't restart AN */
3697         if (ixgbe_check_reset_blocked(hw))
3698                 return IXGBE_SUCCESS;
3699
3700         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3701         if (status != IXGBE_SUCCESS)
3702                 return status;
3703
3704         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3705
3706         if (status != IXGBE_SUCCESS)
3707                 return status;
3708
3709         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3710          * disabled, then force link down by entering low power mode.
3711          */
3712         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3713             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3714                 return ixgbe_set_copper_phy_power(hw, FALSE);
3715
3716         /* Determine LCD */
3717         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3718
3719         if (status != IXGBE_SUCCESS)
3720                 return status;
3721
3722         /* If no valid LCD link speed, then force link down and exit. */
3723         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3724                 return ixgbe_set_copper_phy_power(hw, FALSE);
3725
3726         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3727                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3728                                       &speed);
3729
3730         if (status != IXGBE_SUCCESS)
3731                 return status;
3732
3733         /* If no link now, speed is invalid so take link down */
3734         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3735         if (status != IXGBE_SUCCESS)
3736                 return ixgbe_set_copper_phy_power(hw, false);
3737
3738         /* clear everything but the speed bits */
3739         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3740
3741         /* If current speed is already LCD, then exit. */
3742         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3743              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3744             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3745              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3746                 return status;
3747
3748         /* Clear AN completed indication */
3749         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3750                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3751                                       &autoneg_reg);
3752
3753         if (status != IXGBE_SUCCESS)
3754                 return status;
3755
3756         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3757                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3758                              &an_10g_cntl_reg);
3759
3760         if (status != IXGBE_SUCCESS)
3761                 return status;
3762
3763         status = hw->phy.ops.read_reg(hw,
3764                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3765                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3766                              &autoneg_reg);
3767
3768         if (status != IXGBE_SUCCESS)
3769                 return status;
3770
3771         save_autoneg = hw->phy.autoneg_advertised;
3772
3773         /* Setup link at least common link speed */
3774         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3775
3776         /* restore autoneg from before setting lplu speed */
3777         hw->phy.autoneg_advertised = save_autoneg;
3778
3779         return status;
3780 }
3781
3782 /**
3783  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3784  *  @hw: pointer to hardware structure
3785  *  @lcd_speed: pointer to lowest common link speed
3786  *
3787  * Determine lowest common link speed with link partner.
3788  **/
3789 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3790 {
3791         u16 an_lp_status;
3792         s32 status;
3793         u16 word = hw->eeprom.ctrl_word_3;
3794
3795         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3796
3797         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3798                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3799                                       &an_lp_status);
3800
3801         if (status != IXGBE_SUCCESS)
3802                 return status;
3803
3804         /* If link partner advertised 1G, return 1G */
3805         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3806                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3807                 return status;
3808         }
3809
3810         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3811         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3812             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3813                 return status;
3814
3815         /* Link partner not capable of lower speeds, return 10G */
3816         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3817         return status;
3818 }
3819
3820 /**
3821  *  ixgbe_setup_fc_X550em - Set up flow control
3822  *  @hw: pointer to hardware structure
3823  *
3824  *  Called at init time to set up flow control.
3825  **/
3826 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3827 {
3828         s32 ret_val = IXGBE_SUCCESS;
3829         u32 pause, asm_dir, reg_val;
3830
3831         DEBUGFUNC("ixgbe_setup_fc_X550em");
3832
3833         /* Validate the requested mode */
3834         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3835                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3836                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3837                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3838                 goto out;
3839         }
3840
3841         /* 10gig parts do not have a word in the EEPROM to determine the
3842          * default flow control setting, so we explicitly set it to full.
3843          */
3844         if (hw->fc.requested_mode == ixgbe_fc_default)
3845                 hw->fc.requested_mode = ixgbe_fc_full;
3846
3847         /* Determine PAUSE and ASM_DIR bits. */
3848         switch (hw->fc.requested_mode) {
3849         case ixgbe_fc_none:
3850                 pause = 0;
3851                 asm_dir = 0;
3852                 break;
3853         case ixgbe_fc_tx_pause:
3854                 pause = 0;
3855                 asm_dir = 1;
3856                 break;
3857         case ixgbe_fc_rx_pause:
3858                 /* Rx Flow control is enabled and Tx Flow control is
3859                  * disabled by software override. Since there really
3860                  * isn't a way to advertise that we are capable of RX
3861                  * Pause ONLY, we will advertise that we support both
3862                  * symmetric and asymmetric Rx PAUSE, as such we fall
3863                  * through to the fc_full statement.  Later, we will
3864                  * disable the adapter's ability to send PAUSE frames.
3865                  */
3866         case ixgbe_fc_full:
3867                 pause = 1;
3868                 asm_dir = 1;
3869                 break;
3870         default:
3871                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3872                         "Flow control param set incorrectly\n");
3873                 ret_val = IXGBE_ERR_CONFIG;
3874                 goto out;
3875         }
3876
3877         switch (hw->device_id) {
3878         case IXGBE_DEV_ID_X550EM_X_KR:
3879         case IXGBE_DEV_ID_X550EM_A_KR:
3880         case IXGBE_DEV_ID_X550EM_A_KR_L:
3881                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3882                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3883                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3884                 if (ret_val != IXGBE_SUCCESS)
3885                         goto out;
3886                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3887                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3888                 if (pause)
3889                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3890                 if (asm_dir)
3891                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3892                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3893                                        IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3894                                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3895
3896                 /* This device does not fully support AN. */
3897                 hw->fc.disable_fc_autoneg = true;
3898                 break;
3899         default:
3900                 break;
3901         }
3902
3903 out:
3904         return ret_val;
3905 }
3906
3907 /**
3908  *  ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
3909  *  @hw: pointer to hardware structure
3910  *
3911  *  Enable flow control according to IEEE clause 37.
3912  **/
3913 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
3914 {
3915         u32 link_s1, lp_an_page_low, an_cntl_1;
3916         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
3917         ixgbe_link_speed speed;
3918         bool link_up;
3919
3920         /* AN should have completed when the cable was plugged in.
3921          * Look for reasons to bail out.  Bail out if:
3922          * - FC autoneg is disabled, or if
3923          * - link is not up.
3924          */
3925         if (hw->fc.disable_fc_autoneg) {
3926                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3927                               "Flow control autoneg is disabled");
3928                 goto out;
3929         }
3930
3931         hw->mac.ops.check_link(hw, &speed, &link_up, false);
3932         if (!link_up) {
3933                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3934                 goto out;
3935         }
3936
3937         /* Check at auto-negotiation has completed */
3938         status = hw->mac.ops.read_iosf_sb_reg(hw,
3939                                       IXGBE_KRM_LINK_S1(hw->bus.lan_id),
3940                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
3941
3942         if (status != IXGBE_SUCCESS ||
3943             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
3944                 DEBUGOUT("Auto-Negotiation did not complete\n");
3945                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
3946                 goto out;
3947         }
3948
3949         /* Read the 10g AN autoc and LP ability registers and resolve
3950          * local flow control settings accordingly
3951          */
3952         status = hw->mac.ops.read_iosf_sb_reg(hw,
3953                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3954                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
3955
3956         if (status != IXGBE_SUCCESS) {
3957                 DEBUGOUT("Auto-Negotiation did not complete\n");
3958                 goto out;
3959         }
3960
3961         status = hw->mac.ops.read_iosf_sb_reg(hw,
3962                               IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
3963                               IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
3964
3965         if (status != IXGBE_SUCCESS) {
3966                 DEBUGOUT("Auto-Negotiation did not complete\n");
3967                 goto out;
3968         }
3969
3970         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
3971                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
3972                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
3973                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
3974                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
3975
3976 out:
3977         if (status == IXGBE_SUCCESS) {
3978                 hw->fc.fc_was_autonegged = true;
3979         } else {
3980                 hw->fc.fc_was_autonegged = false;
3981                 hw->fc.current_mode = hw->fc.requested_mode;
3982         }
3983 }
3984
3985 /**
3986  *  ixgbe_fc_autoneg_fiber_x550em_a - Enable flow control IEEE clause 37
3987  *  @hw: pointer to hardware structure
3988  *
3989  *  Enable flow control according to IEEE clause 37.
3990  **/
3991 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
3992 {
3993         u32 link_s1, pcs_an_lp, pcs_an;
3994         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
3995         ixgbe_link_speed speed;
3996         bool link_up;
3997
3998         /* AN should have completed when the cable was plugged in.
3999          * Look for reasons to bail out.  Bail out if:
4000          * - FC autoneg is disabled, or if
4001          * - link is not up.
4002          */
4003         if (hw->fc.disable_fc_autoneg) {
4004                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4005                              "Flow control autoneg is disabled");
4006                 goto out;
4007         }
4008
4009         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4010         if (!link_up) {
4011                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4012                 goto out;
4013         }
4014
4015         /* Check if auto-negotiation has completed */
4016         status = hw->mac.ops.read_iosf_sb_reg(hw,
4017                                          IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4018                                          IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4019
4020         if (status != IXGBE_SUCCESS ||
4021             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4022                 DEBUGOUT("Auto-Negotiation did not complete\n");
4023                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4024                 goto out;
4025         }
4026
4027         /* Determine advertised flow control */
4028         status = hw->mac.ops.read_iosf_sb_reg(hw,
4029                                           IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4030                                           IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an);
4031
4032         if (status != IXGBE_SUCCESS) {
4033                 DEBUGOUT("Auto-Negotiation did not complete\n");
4034                 goto out;
4035         }
4036
4037         /* Determine link parter flow control */
4038         status = hw->mac.ops.read_iosf_sb_reg(hw,
4039                                   IXGBE_KRM_PCS_KX_AN_LP(hw->bus.lan_id),
4040                                   IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an_lp);
4041
4042         if (status != IXGBE_SUCCESS) {
4043                 DEBUGOUT("Auto-Negotiation did not complete\n");
4044                 goto out;
4045         }
4046
4047         status = ixgbe_negotiate_fc(hw, pcs_an, pcs_an_lp,
4048                                     IXGBE_KRM_PCS_KX_AN_SYM_PAUSE,
4049                                     IXGBE_KRM_PCS_KX_AN_ASM_PAUSE,
4050                                     IXGBE_KRM_PCS_KX_AN_LP_SYM_PAUSE,
4051                                     IXGBE_KRM_PCS_KX_AN_LP_ASM_PAUSE);
4052
4053 out:
4054         if (status == IXGBE_SUCCESS) {
4055                 hw->fc.fc_was_autonegged = true;
4056         } else {
4057                 hw->fc.fc_was_autonegged = false;
4058                 hw->fc.current_mode = hw->fc.requested_mode;
4059         }
4060 }
4061
4062 /**
4063  *  ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4064  *  @hw: pointer to hardware structure
4065  *
4066  *  Enable flow control according to IEEE clause 37.
4067  **/
4068 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4069 {
4070         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4071         u16 reg, pcs_an_lp, pcs_an;
4072         ixgbe_link_speed speed;
4073         bool link_up;
4074
4075         /* AN should have completed when the cable was plugged in.
4076          * Look for reasons to bail out.  Bail out if:
4077          * - FC autoneg is disabled, or if
4078          * - link is not up.
4079          */
4080         if (hw->fc.disable_fc_autoneg) {
4081                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4082                              "Flow control autoneg is disabled");
4083                 goto out;
4084         }
4085
4086         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4087         if (!link_up) {
4088                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4089                 goto out;
4090         }
4091
4092         /* Check if auto-negotiation has completed */
4093         status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_STATUS,
4094                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg);
4095         if (status != IXGBE_SUCCESS ||
4096             (reg & IXGBE_M88E1500_COPPER_STATUS_AN_DONE) == 0) {
4097                 DEBUGOUT("Auto-Negotiation did not complete\n");
4098                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4099                 goto out;
4100         }
4101
4102         /* Get the advertized flow control */
4103         status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4104                                         IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an);
4105         if (status != IXGBE_SUCCESS)
4106                 goto out;
4107
4108         /* Get link partner's flow control */
4109         status = hw->phy.ops.read_reg(hw,
4110                         IXGBE_M88E1500_COPPER_AN_LP_ABILITY,
4111                                         IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an_lp);
4112         if (status != IXGBE_SUCCESS)
4113                 goto out;
4114
4115         /* Negotiate the flow control */
4116         status = ixgbe_negotiate_fc(hw, (u32)pcs_an, (u32)pcs_an_lp,
4117                                     IXGBE_M88E1500_COPPER_AN_PAUSE,
4118                                     IXGBE_M88E1500_COPPER_AN_AS_PAUSE,
4119                                     IXGBE_M88E1500_COPPER_AN_LP_PAUSE,
4120                                     IXGBE_M88E1500_COPPER_AN_LP_AS_PAUSE);
4121
4122 out:
4123         if (status == IXGBE_SUCCESS) {
4124                 hw->fc.fc_was_autonegged = true;
4125         } else {
4126                 hw->fc.fc_was_autonegged = false;
4127                 hw->fc.current_mode = hw->fc.requested_mode;
4128         }
4129 }
4130
4131 /**
4132  *  ixgbe_setup_fc_sgmii_x550em_a - Set up flow control
4133  *  @hw: pointer to hardware structure
4134  *
4135  *  Called at init time to set up flow control.
4136  **/
4137 s32 ixgbe_setup_fc_sgmii_x550em_a(struct ixgbe_hw *hw)
4138 {
4139         u16 reg;
4140         s32 rc;
4141
4142         /* Validate the requested mode */
4143         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4144                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4145                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4146                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4147         }
4148
4149         if (hw->fc.requested_mode == ixgbe_fc_default)
4150                 hw->fc.requested_mode = ixgbe_fc_full;
4151
4152         /* Read contents of the Auto-Negotiation register, page 0 reg 4 */
4153         rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4154                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg);
4155         if (rc)
4156                 goto out;
4157
4158         /* Disable all the settings related to Flow control Auto-negotiation */
4159         reg &= ~IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4160         reg &= ~IXGBE_M88E1500_COPPER_AN_PAUSE;
4161
4162         /* Configure the Asymmetric and symmetric pause according to the user
4163          * requested mode.
4164          */
4165         switch (hw->fc.requested_mode) {
4166         case ixgbe_fc_full:
4167                 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4168                 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4169                 break;
4170         case ixgbe_fc_rx_pause:
4171                 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4172                 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4173                 break;
4174         case ixgbe_fc_tx_pause:
4175                 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4176                 break;
4177         default:
4178                 break;
4179         }
4180
4181         /* Write back to the Auto-Negotiation register with newly configured
4182          * fields
4183          */
4184         hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_AN,
4185                                         IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4186
4187         /* In this section of the code we restart Auto-negotiation */
4188
4189         /* Read the CONTROL register, Page 0 reg 0 */
4190         rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4191                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg);
4192         if (rc)
4193                 goto out;
4194
4195         /* Set the bit to restart Auto-Neg. The bit to enable Auto-neg is ON
4196          * by default
4197          */
4198         reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
4199
4200         /* write the new values to the register to restart Auto-Negotiation */
4201         hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4202                                         IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4203
4204 out:
4205         return rc;
4206 }
4207
4208 /**
4209  *  ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4210  *  @hw: pointer to hardware structure
4211  *
4212  *  Called at init time to set up flow control.
4213  **/
4214 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4215 {
4216         s32 status = IXGBE_SUCCESS;
4217         u32 an_cntl, link_ctrl = 0;
4218
4219         DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4220
4221         /* Validate the requested mode */
4222         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4223                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4224                       "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4225                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4226         }
4227
4228         if (hw->fc.requested_mode == ixgbe_fc_default)
4229                 hw->fc.requested_mode = ixgbe_fc_full;
4230
4231         /* Set up the 1G and 10G flow control advertisement registers so the
4232          * HW will be able to do FC autoneg once the cable is plugged in.  If
4233          * we link at 10G, the 1G advertisement is harmless and vice versa.
4234          */
4235         status = hw->mac.ops.read_iosf_sb_reg(hw,
4236                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4237                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4238
4239         if (status != IXGBE_SUCCESS) {
4240                 DEBUGOUT("Auto-Negotiation did not complete\n");
4241                 return status;
4242         }
4243
4244         /* The possible values of fc.requested_mode are:
4245          * 0: Flow control is completely disabled
4246          * 1: Rx flow control is enabled (we can receive pause frames,
4247          *    but not send pause frames).
4248          * 2: Tx flow control is enabled (we can send pause frames but
4249          *    we do not support receiving pause frames).
4250          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4251          * other: Invalid.
4252          */
4253         switch (hw->fc.requested_mode) {
4254         case ixgbe_fc_none:
4255                 /* Flow control completely disabled by software override. */
4256                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4257                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4258                 break;
4259         case ixgbe_fc_tx_pause:
4260                 /* Tx Flow control is enabled, and Rx Flow control is
4261                  * disabled by software override.
4262                  */
4263                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4264                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4265                 break;
4266         case ixgbe_fc_rx_pause:
4267                 /* Rx Flow control is enabled and Tx Flow control is
4268                  * disabled by software override. Since there really
4269                  * isn't a way to advertise that we are capable of RX
4270                  * Pause ONLY, we will advertise that we support both
4271                  * symmetric and asymmetric Rx PAUSE, as such we fall
4272                  * through to the fc_full statement.  Later, we will
4273                  * disable the adapter's ability to send PAUSE frames.
4274                  */
4275         case ixgbe_fc_full:
4276                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4277                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4278                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4279                 break;
4280         default:
4281                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4282                               "Flow control param set incorrectly\n");
4283                 return IXGBE_ERR_CONFIG;
4284         }
4285
4286         status = hw->mac.ops.write_iosf_sb_reg(hw,
4287                                        IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4288                                        IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4289
4290         /* Restart auto-negotiation. */
4291         status = hw->mac.ops.read_iosf_sb_reg(hw,
4292                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4293                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
4294
4295         if (status != IXGBE_SUCCESS) {
4296                 DEBUGOUT("Auto-Negotiation did not complete\n");
4297                 return status;
4298         }
4299
4300         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
4301         status = hw->mac.ops.write_iosf_sb_reg(hw,
4302                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4303                                        IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
4304
4305         return status;
4306 }
4307
4308 /**
4309  *  ixgbe_setup_fc_fiber_x550em_a - Set up flow control
4310  *  @hw: pointer to hardware structure
4311  *
4312  *  Called at init time to set up flow control.
4313  **/
4314 s32 ixgbe_setup_fc_fiber_x550em_a(struct ixgbe_hw *hw)
4315 {
4316         struct ixgbe_mac_info *mac = &hw->mac;
4317         s32 rc = IXGBE_SUCCESS;
4318         u32 an_cntl4, lctrl, pcs_an;
4319
4320         DEBUGFUNC("ixgbe_setup_fc_fiber_x550em_a");
4321
4322         /* Validate the requested mode */
4323         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4324                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4325                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4326                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4327         }
4328
4329         /* Enable clause 37 auto-negotiation in KRM_LINK_CTRL_1 */
4330         if (hw->fc.requested_mode == ixgbe_fc_default)
4331                 hw->fc.requested_mode = ixgbe_fc_full;
4332
4333         rc = mac->ops.read_iosf_sb_reg(hw,
4334                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4335                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lctrl);
4336         if (rc)
4337                 return rc;
4338
4339         lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
4340         lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
4341
4342         rc = mac->ops.write_iosf_sb_reg(hw,
4343                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4344                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lctrl);
4345         if (rc)
4346                 return rc;
4347
4348         /* Enable clause 37 over 73 in KRM_AN_CNTL_4 */
4349         rc = mac->ops.read_iosf_sb_reg(hw,
4350                                        IXGBE_KRM_AN_CNTL_4(hw->bus.lan_id),
4351                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl4);
4352         if (rc)
4353                 return rc;
4354
4355         an_cntl4 |= IXGBE_KRM_AN_CNTL_4_ECSR_AN37_OVER_73;
4356
4357         rc = mac->ops.write_iosf_sb_reg(hw,
4358                                         IXGBE_KRM_AN_CNTL_4(hw->bus.lan_id),
4359                                         IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl4);
4360         if (rc)
4361                 return rc;
4362
4363         rc = hw->mac.ops.read_iosf_sb_reg(hw,
4364                                           IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4365                                           IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an);
4366
4367         if (rc)
4368                 return rc;
4369
4370         /* The possible values of fc.requested_mode are:
4371          * 0: Flow control is completely disabled
4372          * 1: Rx flow control is enabled (we can receive pause frames,
4373          *    but not send pause frames).
4374          * 2: Tx flow control is enabled (we can send pause frames but
4375          *    we do not support receiving pause frames).
4376          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4377          * other: Invalid.
4378          */
4379         switch (hw->fc.requested_mode) {
4380         case ixgbe_fc_none:
4381                 /* Flow control completely disabled by software override. */
4382                 pcs_an &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4383                             IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4384                 break;
4385         case ixgbe_fc_tx_pause:
4386                 /* Tx Flow control is enabled, and Rx Flow control is
4387                  * disabled by software override.
4388                  */
4389                 pcs_an |= IXGBE_KRM_PCS_KX_AN_ASM_PAUSE;
4390                 pcs_an &= ~IXGBE_KRM_PCS_KX_AN_SYM_PAUSE;
4391                 break;
4392         case ixgbe_fc_rx_pause:
4393                 /* Rx Flow control is enabled and Tx Flow control is
4394                  * disabled by software override. Since there really
4395                  * isn't a way to advertise that we are capable of RX
4396                  * Pause ONLY, we will advertise that we support both
4397                  * symmetric and asymmetric Rx PAUSE, as such we fall
4398                  * through to the fc_full statement.  Later, we will
4399                  * disable the adapter's ability to send PAUSE frames.
4400                  */
4401         case ixgbe_fc_full:
4402                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4403                 pcs_an |= IXGBE_KRM_PCS_KX_AN_SYM_PAUSE |
4404                            IXGBE_KRM_PCS_KX_AN_ASM_PAUSE;
4405                 break;
4406         default:
4407                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4408                               "Flow control param set incorrectly\n");
4409                 return IXGBE_ERR_CONFIG;
4410         }
4411
4412         rc = hw->mac.ops.write_iosf_sb_reg(hw,
4413                                            IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4414                                            IXGBE_SB_IOSF_TARGET_KR_PHY, pcs_an);
4415
4416         /* Restart auto-negotiation. */
4417         rc = hw->mac.ops.read_iosf_sb_reg(hw,
4418                                           IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4419                                           IXGBE_SB_IOSF_TARGET_KR_PHY, &lctrl);
4420
4421         if (rc) {
4422                 DEBUGOUT("Auto-Negotiation did not complete\n");
4423                 return rc;
4424         }
4425
4426         lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
4427         rc = hw->mac.ops.write_iosf_sb_reg(hw,
4428                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4429                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lctrl);
4430
4431         return rc;
4432 }
4433
4434 /**
4435  * ixgbe_set_mux - Set mux for port 1 access with CS4227
4436  * @hw: pointer to hardware structure
4437  * @state: set mux if 1, clear if 0
4438  */
4439 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4440 {
4441         u32 esdp;
4442
4443         if (!hw->bus.lan_id)
4444                 return;
4445         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4446         if (state)
4447                 esdp |= IXGBE_ESDP_SDP1;
4448         else
4449                 esdp &= ~IXGBE_ESDP_SDP1;
4450         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4451         IXGBE_WRITE_FLUSH(hw);
4452 }
4453
4454 /**
4455  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4456  *  @hw: pointer to hardware structure
4457  *  @mask: Mask to specify which semaphore to acquire
4458  *
4459  *  Acquires the SWFW semaphore and sets the I2C MUX
4460  **/
4461 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4462 {
4463         s32 status;
4464
4465         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4466
4467         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4468         if (status)
4469                 return status;
4470
4471         if (mask & IXGBE_GSSR_I2C_MASK)
4472                 ixgbe_set_mux(hw, 1);
4473
4474         return IXGBE_SUCCESS;
4475 }
4476
4477 /**
4478  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4479  *  @hw: pointer to hardware structure
4480  *  @mask: Mask to specify which semaphore to release
4481  *
4482  *  Releases the SWFW semaphore and sets the I2C MUX
4483  **/
4484 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4485 {
4486         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4487
4488         if (mask & IXGBE_GSSR_I2C_MASK)
4489                 ixgbe_set_mux(hw, 0);
4490
4491         ixgbe_release_swfw_sync_X540(hw, mask);
4492 }
4493
4494 /**
4495  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4496  *  @hw: pointer to hardware structure
4497  *  @mask: Mask to specify which semaphore to acquire
4498  *
4499  *  Acquires the SWFW semaphore and get the shared phy token as needed
4500  */
4501 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4502 {
4503         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4504         int retries = FW_PHY_TOKEN_RETRIES;
4505         s32 status = IXGBE_SUCCESS;
4506
4507         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4508
4509         while (--retries) {
4510                 status = IXGBE_SUCCESS;
4511                 if (hmask)
4512                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4513                 if (status)
4514                         return status;
4515                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4516                         return IXGBE_SUCCESS;
4517
4518                 status = ixgbe_get_phy_token(hw);
4519                 if (status == IXGBE_SUCCESS)
4520                         return IXGBE_SUCCESS;
4521
4522                 if (hmask)
4523                         ixgbe_release_swfw_sync_X540(hw, hmask);
4524                 if (status != IXGBE_ERR_TOKEN_RETRY)
4525                         return status;
4526         }
4527
4528         return status;
4529 }
4530
4531 /**
4532  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4533  *  @hw: pointer to hardware structure
4534  *  @mask: Mask to specify which semaphore to release
4535  *
4536  *  Releases the SWFW semaphore and puts the shared phy token as needed
4537  */
4538 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4539 {
4540         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4541
4542         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4543
4544         if (mask & IXGBE_GSSR_TOKEN_SM)
4545                 ixgbe_put_phy_token(hw);
4546
4547         if (hmask)
4548                 ixgbe_release_swfw_sync_X540(hw, hmask);
4549 }
4550
4551 /**
4552  *  ixgbe_read_phy_reg_x550a  - Reads specified PHY register
4553  *  @hw: pointer to hardware structure
4554  *  @reg_addr: 32 bit address of PHY register to read
4555  *  @phy_data: Pointer to read data from PHY register
4556  *
4557  *  Reads a value from a specified PHY register using the SWFW lock and PHY
4558  *  Token. The PHY Token is needed since the MDIO is shared between to MAC
4559  *  instances.
4560  **/
4561 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4562                              u32 device_type, u16 *phy_data)
4563 {
4564         s32 status;
4565         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4566
4567         DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4568
4569         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4570                 return IXGBE_ERR_SWFW_SYNC;
4571
4572         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4573
4574         hw->mac.ops.release_swfw_sync(hw, mask);
4575
4576         return status;
4577 }
4578
4579 /**
4580  *  ixgbe_write_phy_reg_x550a - Writes specified PHY register
4581  *  @hw: pointer to hardware structure
4582  *  @reg_addr: 32 bit PHY register to write
4583  *  @device_type: 5 bit device type
4584  *  @phy_data: Data to write to the PHY register
4585  *
4586  *  Writes a value to specified PHY register using the SWFW lock and PHY Token.
4587  *  The PHY Token is needed since the MDIO is shared between to MAC instances.
4588  **/
4589 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4590                               u32 device_type, u16 phy_data)
4591 {
4592         s32 status;
4593         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4594
4595         DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4596
4597         if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4598                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4599                                                  phy_data);
4600                 hw->mac.ops.release_swfw_sync(hw, mask);
4601         } else {
4602                 status = IXGBE_ERR_SWFW_SYNC;
4603         }
4604
4605         return status;
4606 }
4607
4608 /**
4609  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4610  * @hw: pointer to hardware structure
4611  *
4612  * Handle external Base T PHY interrupt. If high temperature
4613  * failure alarm then return error, else if link status change
4614  * then setup internal/external PHY link
4615  *
4616  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4617  * failure alarm, else return PHY access status.
4618  */
4619 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4620 {
4621         bool lsc;
4622         u32 status;
4623
4624         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4625
4626         if (status != IXGBE_SUCCESS)
4627                 return status;
4628
4629         if (lsc)
4630                 return ixgbe_setup_internal_phy(hw);
4631
4632         return IXGBE_SUCCESS;
4633 }
4634
4635 /**
4636  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4637  * @hw: pointer to hardware structure
4638  * @speed: new link speed
4639  * @autoneg_wait_to_complete: true when waiting for completion is needed
4640  *
4641  * Setup internal/external PHY link speed based on link speed, then set
4642  * external PHY auto advertised link speed.
4643  *
4644  * Returns error status for any failure
4645  **/
4646 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4647                                   ixgbe_link_speed speed,
4648                                   bool autoneg_wait_to_complete)
4649 {
4650         s32 status;
4651         ixgbe_link_speed force_speed;
4652
4653         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4654
4655         /* Setup internal/external PHY link speed to iXFI (10G), unless
4656          * only 1G is auto advertised then setup KX link.
4657          */
4658         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4659                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4660         else
4661                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4662
4663         /* If internal link mode is XFI, then setup XFI internal link. */
4664         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4665                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4666
4667                 if (status != IXGBE_SUCCESS)
4668                         return status;
4669         }
4670
4671         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4672 }
4673
4674 /**
4675  * ixgbe_check_link_t_X550em - Determine link and speed status
4676  * @hw: pointer to hardware structure
4677  * @speed: pointer to link speed
4678  * @link_up: true when link is up
4679  * @link_up_wait_to_complete: bool used to wait for link up or not
4680  *
4681  * Check that both the MAC and X557 external PHY have link.
4682  **/
4683 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4684                               bool *link_up, bool link_up_wait_to_complete)
4685 {
4686         u32 status;
4687         u16 autoneg_status;
4688
4689         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4690                 return IXGBE_ERR_CONFIG;
4691
4692         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4693                                               link_up_wait_to_complete);
4694
4695         /* If check link fails or MAC link is not up, then return */
4696         if (status != IXGBE_SUCCESS || !(*link_up))
4697                 return status;
4698
4699         /* MAC link is up, so check external PHY link.
4700          * Read this twice back to back to indicate current status.
4701          */
4702         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4703                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4704                                       &autoneg_status);
4705
4706         if (status != IXGBE_SUCCESS)
4707                 return status;
4708
4709         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4710                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4711                                       &autoneg_status);
4712
4713         if (status != IXGBE_SUCCESS)
4714                 return status;
4715
4716         /* If external PHY link is not up, then indicate link not up */
4717         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4718                 *link_up = false;
4719
4720         return IXGBE_SUCCESS;
4721 }
4722
4723 /**
4724  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4725  *  @hw: pointer to hardware structure
4726  **/
4727 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4728 {
4729         s32 status;
4730
4731         status = ixgbe_reset_phy_generic(hw);
4732
4733         if (status != IXGBE_SUCCESS)
4734                 return status;
4735
4736         /* Configure Link Status Alarm and Temperature Threshold interrupts */
4737         return ixgbe_enable_lasi_ext_t_x550em(hw);
4738 }
4739
4740 /**
4741  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4742  *  @hw: pointer to hardware structure
4743  *  @led_idx: led number to turn on
4744  **/
4745 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4746 {
4747         u16 phy_data;
4748
4749         DEBUGFUNC("ixgbe_led_on_t_X550em");
4750
4751         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4752                 return IXGBE_ERR_PARAM;
4753
4754         /* To turn on the LED, set mode to ON. */
4755         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4756                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4757         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4758         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4759                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4760
4761         return IXGBE_SUCCESS;
4762 }
4763
4764 /**
4765  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4766  *  @hw: pointer to hardware structure
4767  *  @led_idx: led number to turn off
4768  **/
4769 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4770 {
4771         u16 phy_data;
4772
4773         DEBUGFUNC("ixgbe_led_off_t_X550em");
4774
4775         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4776                 return IXGBE_ERR_PARAM;
4777
4778         /* To turn on the LED, set mode to ON. */
4779         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4780                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4781         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4782         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4783                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4784
4785         return IXGBE_SUCCESS;
4786 }
4787