drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIBRTE_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void ixgbe_dev_setup_link_alarm_handler(void *param);
 233
 234 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 235                         struct rte_ether_addr *mac_addr,
 236                         uint32_t index, uint32_t pool);
 237 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 238 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 239                                            struct rte_ether_addr *mac_addr);
 240 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 241 static bool is_device_supported(struct rte_eth_dev *dev,
 242                                 struct rte_pci_driver *drv);
 243
 244 /* For Virtual Function support */
 245 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 246 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 247 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 248 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 249 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 250                                    int wait_to_complete);
 251 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 252 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 253 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 254 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 255 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 256 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 257                 struct rte_eth_stats *stats);
 258 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 259 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 260                 uint16_t vlan_id, int on);
 261 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 262                 uint16_t queue, int on);
 263 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 264 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 265 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 266 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 267                                             uint16_t queue_id);
 268 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 269                                              uint16_t queue_id);
 270 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 271                                  uint8_t queue, uint8_t msix_vector);
 272 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 273 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 274 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 277
 278 /* For Eth VMDQ APIs support */
 279 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 280                 rte_ether_addr * mac_addr, uint8_t on);
 281 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 282 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 283                 struct rte_eth_mirror_conf *mirror_conf,
 284                 uint8_t rule_id, uint8_t on);
 285 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 286                 uint8_t rule_id);
 287 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 288                                           uint16_t queue_id);
 289 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 290                                            uint16_t queue_id);
 291 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 292                                uint8_t queue, uint8_t msix_vector);
 293 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 294
 295 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 296                                 struct rte_ether_addr *mac_addr,
 297                                 uint32_t index, uint32_t pool);
 298 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 299 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 300                                              struct rte_ether_addr *mac_addr);
 301 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 302                         struct rte_eth_syn_filter *filter);
 303 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 304                         enum rte_filter_op filter_op,
 305                         void *arg);
 306 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 307                         struct ixgbe_5tuple_filter *filter);
 308 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 309                         struct ixgbe_5tuple_filter *filter);
 310 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 311                                 enum rte_filter_op filter_op,
 312                                 void *arg);
 313 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 314                         struct rte_eth_ntuple_filter *filter);
 315 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 316                                 enum rte_filter_op filter_op,
 317                                 void *arg);
 318 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 319                         struct rte_eth_ethertype_filter *filter);
 320 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 321                      enum rte_filter_type filter_type,
 322                      enum rte_filter_op filter_op,
 323                      void *arg);
 324 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 325
 326 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 327                                       struct rte_ether_addr *mc_addr_set,
 328                                       uint32_t nb_mc_addr);
 329 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 330                                    struct rte_eth_dcb_info *dcb_info);
 331
 332 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 333 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 334                             struct rte_dev_reg_info *regs);
 335 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 336 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 337                                 struct rte_dev_eeprom_info *eeprom);
 338 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 339                                 struct rte_dev_eeprom_info *eeprom);
 340
 341 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 342                                  struct rte_eth_dev_module_info *modinfo);
 343 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 344                                    struct rte_dev_eeprom_info *info);
 345
 346 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 347 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 348                                 struct rte_dev_reg_info *regs);
 349
 350 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 351 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 352 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 353                                             struct timespec *timestamp,
 354                                             uint32_t flags);
 355 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 356                                             struct timespec *timestamp);
 357 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 358 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 359                                    struct timespec *timestamp);
 360 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 361                                    const struct timespec *timestamp);
 362 static void ixgbevf_dev_interrupt_handler(void *param);
 363
 364 static int ixgbe_dev_l2_tunnel_eth_type_conf
 365         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 366 static int ixgbe_dev_l2_tunnel_offload_set
 367         (struct rte_eth_dev *dev,
 368          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 369          uint32_t mask,
 370          uint8_t en);
 371 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 372                                              enum rte_filter_op filter_op,
 373                                              void *arg);
 374
 375 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 376                                          struct rte_eth_udp_tunnel *udp_tunnel);
 377 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 380 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 381
 382 /*
 383  * Define VF Stats MACRO for Non "cleared on read" register
 384  */
 385 #define UPDATE_VF_STAT(reg, last, cur)                          \
 386 {                                                               \
 387         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 388         cur += (latest - last) & UINT_MAX;                      \
 389         last = latest;                                          \
 390 }
 391
 392 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 393 {                                                                \
 394         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 395         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 396         u64 latest = ((new_msb << 32) | new_lsb);                \
 397         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 398         last = latest;                                           \
 399 }
 400
 401 #define IXGBE_SET_HWSTRIP(h, q) do {\
 402                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 403                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 404                 (h)->bitmap[idx] |= 1 << bit;\
 405         } while (0)
 406
 407 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 408                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 409                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 410                 (h)->bitmap[idx] &= ~(1 << bit);\
 411         } while (0)
 412
 413 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 414                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 415                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 416                 (r) = (h)->bitmap[idx] >> bit & 1;\
 417         } while (0)
 418
 419 int ixgbe_logtype_init;
 420 int ixgbe_logtype_driver;
 421
 422 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
 423 int ixgbe_logtype_rx;
 424 #endif
 425 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
 426 int ixgbe_logtype_tx;
 427 #endif
 428 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
 429 int ixgbe_logtype_tx_free;
 430 #endif
 431
 432 /*
 433  * The set of PCI devices this driver supports
 434  */
 435 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 484 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 486 #endif
 487         { .vendor_id = 0, /* sentinel */ },
 488 };
 489
 490 /*
 491  * The set of PCI devices this driver supports (for 82599 VF)
 492  */
 493 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 504         { .vendor_id = 0, /* sentinel */ },
 505 };
 506
 507 static const struct rte_eth_desc_lim rx_desc_lim = {
 508         .nb_max = IXGBE_MAX_RING_DESC,
 509         .nb_min = IXGBE_MIN_RING_DESC,
 510         .nb_align = IXGBE_RXD_ALIGN,
 511 };
 512
 513 static const struct rte_eth_desc_lim tx_desc_lim = {
 514         .nb_max = IXGBE_MAX_RING_DESC,
 515         .nb_min = IXGBE_MIN_RING_DESC,
 516         .nb_align = IXGBE_TXD_ALIGN,
 517         .nb_seg_max = IXGBE_TX_MAX_SEG,
 518         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 519 };
 520
 521 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 522         .dev_configure        = ixgbe_dev_configure,
 523         .dev_start            = ixgbe_dev_start,
 524         .dev_stop             = ixgbe_dev_stop,
 525         .dev_set_link_up    = ixgbe_dev_set_link_up,
 526         .dev_set_link_down  = ixgbe_dev_set_link_down,
 527         .dev_close            = ixgbe_dev_close,
 528         .dev_reset            = ixgbe_dev_reset,
 529         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 530         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 531         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 532         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 533         .link_update          = ixgbe_dev_link_update,
 534         .stats_get            = ixgbe_dev_stats_get,
 535         .xstats_get           = ixgbe_dev_xstats_get,
 536         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 537         .stats_reset          = ixgbe_dev_stats_reset,
 538         .xstats_reset         = ixgbe_dev_xstats_reset,
 539         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 540         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 541         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 542         .fw_version_get       = ixgbe_fw_version_get,
 543         .dev_infos_get        = ixgbe_dev_info_get,
 544         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 545         .mtu_set              = ixgbe_dev_mtu_set,
 546         .vlan_filter_set      = ixgbe_vlan_filter_set,
 547         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 548         .vlan_offload_set     = ixgbe_vlan_offload_set,
 549         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 550         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 551         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 552         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 553         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 554         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 555         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 556         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 557         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 558         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 559         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 560         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 561         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 562         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 563         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 564         .dev_led_on           = ixgbe_dev_led_on,
 565         .dev_led_off          = ixgbe_dev_led_off,
 566         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 567         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 568         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 569         .mac_addr_add         = ixgbe_add_rar,
 570         .mac_addr_remove      = ixgbe_remove_rar,
 571         .mac_addr_set         = ixgbe_set_default_mac_addr,
 572         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 573         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 574         .mirror_rule_set      = ixgbe_mirror_rule_set,
 575         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 576         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 577         .reta_update          = ixgbe_dev_rss_reta_update,
 578         .reta_query           = ixgbe_dev_rss_reta_query,
 579         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 580         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 581         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 582         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 583         .rxq_info_get         = ixgbe_rxq_info_get,
 584         .txq_info_get         = ixgbe_txq_info_get,
 585         .timesync_enable      = ixgbe_timesync_enable,
 586         .timesync_disable     = ixgbe_timesync_disable,
 587         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 588         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 589         .get_reg              = ixgbe_get_regs,
 590         .get_eeprom_length    = ixgbe_get_eeprom_length,
 591         .get_eeprom           = ixgbe_get_eeprom,
 592         .set_eeprom           = ixgbe_set_eeprom,
 593         .get_module_info      = ixgbe_get_module_info,
 594         .get_module_eeprom    = ixgbe_get_module_eeprom,
 595         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 596         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 597         .timesync_read_time   = ixgbe_timesync_read_time,
 598         .timesync_write_time  = ixgbe_timesync_write_time,
 599         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 600         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 601         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 602         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 603         .tm_ops_get           = ixgbe_tm_ops_get,
 604 };
 605
 606 /*
 607  * dev_ops for virtual function, bare necessities for basic vf
 608  * operation have been implemented
 609  */
 610 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 611         .dev_configure        = ixgbevf_dev_configure,
 612         .dev_start            = ixgbevf_dev_start,
 613         .dev_stop             = ixgbevf_dev_stop,
 614         .link_update          = ixgbevf_dev_link_update,
 615         .stats_get            = ixgbevf_dev_stats_get,
 616         .xstats_get           = ixgbevf_dev_xstats_get,
 617         .stats_reset          = ixgbevf_dev_stats_reset,
 618         .xstats_reset         = ixgbevf_dev_stats_reset,
 619         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 620         .dev_close            = ixgbevf_dev_close,
 621         .dev_reset            = ixgbevf_dev_reset,
 622         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 623         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 624         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 625         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 626         .dev_infos_get        = ixgbevf_dev_info_get,
 627         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 628         .mtu_set              = ixgbevf_dev_set_mtu,
 629         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 630         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 631         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 632         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 633         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 634         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 635         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 636         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 637         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 638         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 639         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 640         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 641         .mac_addr_add         = ixgbevf_add_mac_addr,
 642         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 643         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 644         .rxq_info_get         = ixgbe_rxq_info_get,
 645         .txq_info_get         = ixgbe_txq_info_get,
 646         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 647         .get_reg              = ixgbevf_get_regs,
 648         .reta_update          = ixgbe_dev_rss_reta_update,
 649         .reta_query           = ixgbe_dev_rss_reta_query,
 650         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 651         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 652 };
 653
 654 /* store statistics names and its offset in stats structure */
 655 struct rte_ixgbe_xstats_name_off {
 656         char name[RTE_ETH_XSTATS_NAME_SIZE];
 657         unsigned offset;
 658 };
 659
 660 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 661         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 662         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 663         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 664         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 665         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 666         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 667         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 668         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 669         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 670         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 671         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 672         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 673         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 674         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 675         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 676                 prc1023)},
 677         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 678                 prc1522)},
 679         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 680         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 681         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 682         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 683         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 684         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 685         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 686         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 687         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 688         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 689         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 690         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 691         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 692         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 693         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 694         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 695         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 696                 ptc1023)},
 697         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 698                 ptc1522)},
 699         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 700         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 701         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 702         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 703
 704         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 705                 fdirustat_add)},
 706         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 707                 fdirustat_remove)},
 708         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 709                 fdirfstat_fadd)},
 710         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 711                 fdirfstat_fremove)},
 712         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 713                 fdirmatch)},
 714         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 715                 fdirmiss)},
 716
 717         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 718         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 719         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 720                 fclast)},
 721         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 722         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 723         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 724         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 725         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 726                 fcoe_noddp)},
 727         {"rx_fcoe_no_direct_data_placement_ext_buff",
 728                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 729
 730         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 731                 lxontxc)},
 732         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 733                 lxonrxc)},
 734         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 735                 lxofftxc)},
 736         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 737                 lxoffrxc)},
 738         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 739 };
 740
 741 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 742                            sizeof(rte_ixgbe_stats_strings[0]))
 743
 744 /* MACsec statistics */
 745 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 746         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 747                 out_pkts_untagged)},
 748         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 749                 out_pkts_encrypted)},
 750         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 751                 out_pkts_protected)},
 752         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 753                 out_octets_encrypted)},
 754         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 755                 out_octets_protected)},
 756         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 757                 in_pkts_untagged)},
 758         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 759                 in_pkts_badtag)},
 760         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 761                 in_pkts_nosci)},
 762         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 763                 in_pkts_unknownsci)},
 764         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 765                 in_octets_decrypted)},
 766         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 767                 in_octets_validated)},
 768         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 769                 in_pkts_unchecked)},
 770         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 771                 in_pkts_delayed)},
 772         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 773                 in_pkts_late)},
 774         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 775                 in_pkts_ok)},
 776         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 777                 in_pkts_invalid)},
 778         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 779                 in_pkts_notvalid)},
 780         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 781                 in_pkts_unusedsa)},
 782         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 783                 in_pkts_notusingsa)},
 784 };
 785
 786 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 787                            sizeof(rte_ixgbe_macsec_strings[0]))
 788
 789 /* Per-queue statistics */
 790 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 791         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 792         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 793         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 794         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 795 };
 796
 797 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 798                            sizeof(rte_ixgbe_rxq_strings[0]))
 799 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 800
 801 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 802         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 803         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 804         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 805                 pxon2offc)},
 806 };
 807
 808 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 809                            sizeof(rte_ixgbe_txq_strings[0]))
 810 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 811
 812 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 813         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 814 };
 815
 816 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 817                 sizeof(rte_ixgbevf_stats_strings[0]))
 818
 819 /*
 820  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 821  */
 822 static inline int
 823 ixgbe_is_sfp(struct ixgbe_hw *hw)
 824 {
 825         switch (hw->phy.type) {
 826         case ixgbe_phy_sfp_avago:
 827         case ixgbe_phy_sfp_ftl:
 828         case ixgbe_phy_sfp_intel:
 829         case ixgbe_phy_sfp_unknown:
 830         case ixgbe_phy_sfp_passive_tyco:
 831         case ixgbe_phy_sfp_passive_unknown:
 832                 return 1;
 833         default:
 834                 return 0;
 835         }
 836 }
 837
 838 static inline int32_t
 839 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 840 {
 841         uint32_t ctrl_ext;
 842         int32_t status;
 843
 844         status = ixgbe_reset_hw(hw);
 845
 846         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 847         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 848         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 849         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 850         IXGBE_WRITE_FLUSH(hw);
 851
 852         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 853                 status = IXGBE_SUCCESS;
 854         return status;
 855 }
 856
 857 static inline void
 858 ixgbe_enable_intr(struct rte_eth_dev *dev)
 859 {
 860         struct ixgbe_interrupt *intr =
 861                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 862         struct ixgbe_hw *hw =
 863                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 864
 865         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 866         IXGBE_WRITE_FLUSH(hw);
 867 }
 868
 869 /*
 870  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 871  */
 872 static void
 873 ixgbe_disable_intr(struct ixgbe_hw *hw)
 874 {
 875         PMD_INIT_FUNC_TRACE();
 876
 877         if (hw->mac.type == ixgbe_mac_82598EB) {
 878                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 879         } else {
 880                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 881                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 882                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 883         }
 884         IXGBE_WRITE_FLUSH(hw);
 885 }
 886
 887 /*
 888  * This function resets queue statistics mapping registers.
 889  * From Niantic datasheet, Initialization of Statistics section:
 890  * "...if software requires the queue counters, the RQSMR and TQSM registers
 891  * must be re-programmed following a device reset.
 892  */
 893 static void
 894 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 895 {
 896         uint32_t i;
 897
 898         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 899                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 900                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 901         }
 902 }
 903
 904
 905 static int
 906 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 907                                   uint16_t queue_id,
 908                                   uint8_t stat_idx,
 909                                   uint8_t is_rx)
 910 {
 911 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 912 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 913 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 914
 915         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 916         struct ixgbe_stat_mapping_registers *stat_mappings =
 917                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 918         uint32_t qsmr_mask = 0;
 919         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 920         uint32_t q_map;
 921         uint8_t n, offset;
 922
 923         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 924                 (hw->mac.type != ixgbe_mac_X540) &&
 925                 (hw->mac.type != ixgbe_mac_X550) &&
 926                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 927                 (hw->mac.type != ixgbe_mac_X550EM_a))
 928                 return -ENOSYS;
 929
 930         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 931                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 932                      queue_id, stat_idx);
 933
 934         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 935         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 936                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 937                 return -EIO;
 938         }
 939         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 940
 941         /* Now clear any previous stat_idx set */
 942         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 943         if (!is_rx)
 944                 stat_mappings->tqsm[n] &= ~clearing_mask;
 945         else
 946                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 947
 948         q_map = (uint32_t)stat_idx;
 949         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 950         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 951         if (!is_rx)
 952                 stat_mappings->tqsm[n] |= qsmr_mask;
 953         else
 954                 stat_mappings->rqsmr[n] |= qsmr_mask;
 955
 956         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 957                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 958                      queue_id, stat_idx);
 959         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 960                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 961
 962         /* Now write the mapping in the appropriate register */
 963         if (is_rx) {
 964                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 965                              stat_mappings->rqsmr[n], n);
 966                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 967         } else {
 968                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 969                              stat_mappings->tqsm[n], n);
 970                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 971         }
 972         return 0;
 973 }
 974
 975 static void
 976 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 977 {
 978         struct ixgbe_stat_mapping_registers *stat_mappings =
 979                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 980         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 981         int i;
 982
 983         /* write whatever was in stat mapping table to the NIC */
 984         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 985                 /* rx */
 986                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 987
 988                 /* tx */
 989                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 990         }
 991 }
 992
 993 static void
 994 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 995 {
 996         uint8_t i;
 997         struct ixgbe_dcb_tc_config *tc;
 998         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 999
1000         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1001         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1002         for (i = 0; i < dcb_max_tc; i++) {
1003                 tc = &dcb_config->tc_config[i];
1004                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1005                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1006                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1007                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1008                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1009                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1010                 tc->pfc = ixgbe_dcb_pfc_disabled;
1011         }
1012
1013         /* Initialize default user to priority mapping, UPx->TC0 */
1014         tc = &dcb_config->tc_config[0];
1015         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1016         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1017         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1018                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1019                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1020         }
1021         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1022         dcb_config->pfc_mode_enable = false;
1023         dcb_config->vt_mode = true;
1024         dcb_config->round_robin_enable = false;
1025         /* support all DCB capabilities in 82599 */
1026         dcb_config->support.capabilities = 0xFF;
1027
1028         /*we only support 4 Tcs for X540, X550 */
1029         if (hw->mac.type == ixgbe_mac_X540 ||
1030                 hw->mac.type == ixgbe_mac_X550 ||
1031                 hw->mac.type == ixgbe_mac_X550EM_x ||
1032                 hw->mac.type == ixgbe_mac_X550EM_a) {
1033                 dcb_config->num_tcs.pg_tcs = 4;
1034                 dcb_config->num_tcs.pfc_tcs = 4;
1035         }
1036 }
1037
1038 /*
1039  * Ensure that all locks are released before first NVM or PHY access
1040  */
1041 static void
1042 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1043 {
1044         uint16_t mask;
1045
1046         /*
1047          * Phy lock should not fail in this early stage. If this is the case,
1048          * it is due to an improper exit of the application.
1049          * So force the release of the faulty lock. Release of common lock
1050          * is done automatically by swfw_sync function.
1051          */
1052         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1053         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1054                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1055         }
1056         ixgbe_release_swfw_semaphore(hw, mask);
1057
1058         /*
1059          * These ones are more tricky since they are common to all ports; but
1060          * swfw_sync retries last long enough (1s) to be almost sure that if
1061          * lock can not be taken it is due to an improper lock of the
1062          * semaphore.
1063          */
1064         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1065         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1066                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1067         }
1068         ixgbe_release_swfw_semaphore(hw, mask);
1069 }
1070
1071 /*
1072  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1073  * It returns 0 on success.
1074  */
1075 static int
1076 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1077 {
1078         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1079         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1080         struct ixgbe_hw *hw =
1081                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1082         struct ixgbe_vfta *shadow_vfta =
1083                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1084         struct ixgbe_hwstrip *hwstrip =
1085                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1086         struct ixgbe_dcb_config *dcb_config =
1087                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1088         struct ixgbe_filter_info *filter_info =
1089                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1090         struct ixgbe_bw_conf *bw_conf =
1091                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1092         uint32_t ctrl_ext;
1093         uint16_t csum;
1094         int diag, i;
1095
1096         PMD_INIT_FUNC_TRACE();
1097
1098         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1099         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1100         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1101         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1102
1103         /*
1104          * For secondary processes, we don't initialise any further as primary
1105          * has already done this work. Only check we don't need a different
1106          * RX and TX function.
1107          */
1108         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1109                 struct ixgbe_tx_queue *txq;
1110                 /* TX queue function in primary, set by last queue initialized
1111                  * Tx queue may not initialized by primary process
1112                  */
1113                 if (eth_dev->data->tx_queues) {
1114                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1115                         ixgbe_set_tx_function(eth_dev, txq);
1116                 } else {
1117                         /* Use default TX function if we get here */
1118                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1119                                      "Using default TX function.");
1120                 }
1121
1122                 ixgbe_set_rx_function(eth_dev);
1123
1124                 return 0;
1125         }
1126
1127         rte_eth_copy_pci_info(eth_dev, pci_dev);
1128
1129         /* Vendor and Device ID need to be set before init of shared code */
1130         hw->device_id = pci_dev->id.device_id;
1131         hw->vendor_id = pci_dev->id.vendor_id;
1132         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1133         hw->allow_unsupported_sfp = 1;
1134
1135         /* Initialize the shared code (base driver) */
1136 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1137         diag = ixgbe_bypass_init_shared_code(hw);
1138 #else
1139         diag = ixgbe_init_shared_code(hw);
1140 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1141
1142         if (diag != IXGBE_SUCCESS) {
1143                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1144                 return -EIO;
1145         }
1146
1147         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1148                 PMD_INIT_LOG(ERR, "\nERROR: "
1149                         "Firmware recovery mode detected. Limiting functionality.\n"
1150                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1151                         "User Guide for details on firmware recovery mode.");
1152                 return -EIO;
1153         }
1154
1155         /* pick up the PCI bus settings for reporting later */
1156         ixgbe_get_bus_info(hw);
1157
1158         /* Unlock any pending hardware semaphore */
1159         ixgbe_swfw_lock_reset(hw);
1160
1161 #ifdef RTE_LIBRTE_SECURITY
1162         /* Initialize security_ctx only for primary process*/
1163         if (ixgbe_ipsec_ctx_create(eth_dev))
1164                 return -ENOMEM;
1165 #endif
1166
1167         /* Initialize DCB configuration*/
1168         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1169         ixgbe_dcb_init(hw, dcb_config);
1170         /* Get Hardware Flow Control setting */
1171         hw->fc.requested_mode = ixgbe_fc_full;
1172         hw->fc.current_mode = ixgbe_fc_full;
1173         hw->fc.pause_time = IXGBE_FC_PAUSE;
1174         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1175                 hw->fc.low_water[i] = IXGBE_FC_LO;
1176                 hw->fc.high_water[i] = IXGBE_FC_HI;
1177         }
1178         hw->fc.send_xon = 1;
1179
1180         /* Make sure we have a good EEPROM before we read from it */
1181         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1182         if (diag != IXGBE_SUCCESS) {
1183                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1184                 return -EIO;
1185         }
1186
1187 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1188         diag = ixgbe_bypass_init_hw(hw);
1189 #else
1190         diag = ixgbe_init_hw(hw);
1191 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1192
1193         /*
1194          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1195          * is called too soon after the kernel driver unbinding/binding occurs.
1196          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1197          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1198          * also called. See ixgbe_identify_phy_82599(). The reason for the
1199          * failure is not known, and only occuts when virtualisation features
1200          * are disabled in the bios. A delay of 100ms  was found to be enough by
1201          * trial-and-error, and is doubled to be safe.
1202          */
1203         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1204                 rte_delay_ms(200);
1205                 diag = ixgbe_init_hw(hw);
1206         }
1207
1208         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1209                 diag = IXGBE_SUCCESS;
1210
1211         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1212                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1213                              "LOM.  Please be aware there may be issues associated "
1214                              "with your hardware.");
1215                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1216                              "please contact your Intel or hardware representative "
1217                              "who provided you with this hardware.");
1218         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1219                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1220         if (diag) {
1221                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1222                 return -EIO;
1223         }
1224
1225         /* Reset the hw statistics */
1226         ixgbe_dev_stats_reset(eth_dev);
1227
1228         /* disable interrupt */
1229         ixgbe_disable_intr(hw);
1230
1231         /* reset mappings for queue statistics hw counters*/
1232         ixgbe_reset_qstat_mappings(hw);
1233
1234         /* Allocate memory for storing MAC addresses */
1235         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1236                                                hw->mac.num_rar_entries, 0);
1237         if (eth_dev->data->mac_addrs == NULL) {
1238                 PMD_INIT_LOG(ERR,
1239                              "Failed to allocate %u bytes needed to store "
1240                              "MAC addresses",
1241                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1242                 return -ENOMEM;
1243         }
1244         /* Copy the permanent MAC address */
1245         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1246                         &eth_dev->data->mac_addrs[0]);
1247
1248         /* Allocate memory for storing hash filter MAC addresses */
1249         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1250                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1251         if (eth_dev->data->hash_mac_addrs == NULL) {
1252                 PMD_INIT_LOG(ERR,
1253                              "Failed to allocate %d bytes needed to store MAC addresses",
1254                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1255                 return -ENOMEM;
1256         }
1257
1258         /* Pass the information to the rte_eth_dev_close() that it should also
1259          * release the private port resources.
1260          */
1261         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1262
1263         /* initialize the vfta */
1264         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1265
1266         /* initialize the hw strip bitmap*/
1267         memset(hwstrip, 0, sizeof(*hwstrip));
1268
1269         /* initialize PF if max_vfs not zero */
1270         ixgbe_pf_host_init(eth_dev);
1271
1272         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1273         /* let hardware know driver is loaded */
1274         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1275         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1276         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1277         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1278         IXGBE_WRITE_FLUSH(hw);
1279
1280         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1281                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1282                              (int) hw->mac.type, (int) hw->phy.type,
1283                              (int) hw->phy.sfp_type);
1284         else
1285                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1286                              (int) hw->mac.type, (int) hw->phy.type);
1287
1288         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1289                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1290                      pci_dev->id.device_id);
1291
1292         rte_intr_callback_register(intr_handle,
1293                                    ixgbe_dev_interrupt_handler, eth_dev);
1294
1295         /* enable uio/vfio intr/eventfd mapping */
1296         rte_intr_enable(intr_handle);
1297
1298         /* enable support intr */
1299         ixgbe_enable_intr(eth_dev);
1300
1301         /* initialize filter info */
1302         memset(filter_info, 0,
1303                sizeof(struct ixgbe_filter_info));
1304
1305         /* initialize 5tuple filter list */
1306         TAILQ_INIT(&filter_info->fivetuple_list);
1307
1308         /* initialize flow director filter list & hash */
1309         ixgbe_fdir_filter_init(eth_dev);
1310
1311         /* initialize l2 tunnel filter list & hash */
1312         ixgbe_l2_tn_filter_init(eth_dev);
1313
1314         /* initialize flow filter lists */
1315         ixgbe_filterlist_init();
1316
1317         /* initialize bandwidth configuration info */
1318         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1319
1320         /* initialize Traffic Manager configuration */
1321         ixgbe_tm_conf_init(eth_dev);
1322
1323         return 0;
1324 }
1325
1326 static int
1327 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1328 {
1329         PMD_INIT_FUNC_TRACE();
1330
1331         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1332                 return 0;
1333
1334         ixgbe_dev_close(eth_dev);
1335
1336         return 0;
1337 }
1338
1339 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1340 {
1341         struct ixgbe_filter_info *filter_info =
1342                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1343         struct ixgbe_5tuple_filter *p_5tuple;
1344
1345         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1346                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1347                              p_5tuple,
1348                              entries);
1349                 rte_free(p_5tuple);
1350         }
1351         memset(filter_info->fivetuple_mask, 0,
1352                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1353
1354         return 0;
1355 }
1356
1357 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1358 {
1359         struct ixgbe_hw_fdir_info *fdir_info =
1360                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1361         struct ixgbe_fdir_filter *fdir_filter;
1362
1363                 if (fdir_info->hash_map)
1364                 rte_free(fdir_info->hash_map);
1365         if (fdir_info->hash_handle)
1366                 rte_hash_free(fdir_info->hash_handle);
1367
1368         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1369                 TAILQ_REMOVE(&fdir_info->fdir_list,
1370                              fdir_filter,
1371                              entries);
1372                 rte_free(fdir_filter);
1373         }
1374
1375         return 0;
1376 }
1377
1378 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1379 {
1380         struct ixgbe_l2_tn_info *l2_tn_info =
1381                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1382         struct ixgbe_l2_tn_filter *l2_tn_filter;
1383
1384         if (l2_tn_info->hash_map)
1385                 rte_free(l2_tn_info->hash_map);
1386         if (l2_tn_info->hash_handle)
1387                 rte_hash_free(l2_tn_info->hash_handle);
1388
1389         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1390                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1391                              l2_tn_filter,
1392                              entries);
1393                 rte_free(l2_tn_filter);
1394         }
1395
1396         return 0;
1397 }
1398
1399 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1400 {
1401         struct ixgbe_hw_fdir_info *fdir_info =
1402                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1403         char fdir_hash_name[RTE_HASH_NAMESIZE];
1404         struct rte_hash_parameters fdir_hash_params = {
1405                 .name = fdir_hash_name,
1406                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1407                 .key_len = sizeof(union ixgbe_atr_input),
1408                 .hash_func = rte_hash_crc,
1409                 .hash_func_init_val = 0,
1410                 .socket_id = rte_socket_id(),
1411         };
1412
1413         TAILQ_INIT(&fdir_info->fdir_list);
1414         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1415                  "fdir_%s", eth_dev->device->name);
1416         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1417         if (!fdir_info->hash_handle) {
1418                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1419                 return -EINVAL;
1420         }
1421         fdir_info->hash_map = rte_zmalloc("ixgbe",
1422                                           sizeof(struct ixgbe_fdir_filter *) *
1423                                           IXGBE_MAX_FDIR_FILTER_NUM,
1424                                           0);
1425         if (!fdir_info->hash_map) {
1426                 PMD_INIT_LOG(ERR,
1427                              "Failed to allocate memory for fdir hash map!");
1428                 return -ENOMEM;
1429         }
1430         fdir_info->mask_added = FALSE;
1431
1432         return 0;
1433 }
1434
1435 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1436 {
1437         struct ixgbe_l2_tn_info *l2_tn_info =
1438                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1439         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1440         struct rte_hash_parameters l2_tn_hash_params = {
1441                 .name = l2_tn_hash_name,
1442                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1443                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1444                 .hash_func = rte_hash_crc,
1445                 .hash_func_init_val = 0,
1446                 .socket_id = rte_socket_id(),
1447         };
1448
1449         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1450         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1451                  "l2_tn_%s", eth_dev->device->name);
1452         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1453         if (!l2_tn_info->hash_handle) {
1454                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1455                 return -EINVAL;
1456         }
1457         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1458                                    sizeof(struct ixgbe_l2_tn_filter *) *
1459                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1460                                    0);
1461         if (!l2_tn_info->hash_map) {
1462                 PMD_INIT_LOG(ERR,
1463                         "Failed to allocate memory for L2 TN hash map!");
1464                 return -ENOMEM;
1465         }
1466         l2_tn_info->e_tag_en = FALSE;
1467         l2_tn_info->e_tag_fwd_en = FALSE;
1468         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1469
1470         return 0;
1471 }
1472 /*
1473  * Negotiate mailbox API version with the PF.
1474  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1475  * Then we try to negotiate starting with the most recent one.
1476  * If all negotiation attempts fail, then we will proceed with
1477  * the default one (ixgbe_mbox_api_10).
1478  */
1479 static void
1480 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1481 {
1482         int32_t i;
1483
1484         /* start with highest supported, proceed down */
1485         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1486                 ixgbe_mbox_api_13,
1487                 ixgbe_mbox_api_12,
1488                 ixgbe_mbox_api_11,
1489                 ixgbe_mbox_api_10,
1490         };
1491
1492         for (i = 0;
1493                         i != RTE_DIM(sup_ver) &&
1494                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1495                         i++)
1496                 ;
1497 }
1498
1499 static void
1500 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1501 {
1502         uint64_t random;
1503
1504         /* Set Organizationally Unique Identifier (OUI) prefix. */
1505         mac_addr->addr_bytes[0] = 0x00;
1506         mac_addr->addr_bytes[1] = 0x09;
1507         mac_addr->addr_bytes[2] = 0xC0;
1508         /* Force indication of locally assigned MAC address. */
1509         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1510         /* Generate the last 3 bytes of the MAC address with a random number. */
1511         random = rte_rand();
1512         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1513 }
1514
1515 static int
1516 devarg_handle_int(__rte_unused const char *key, const char *value,
1517                   void *extra_args)
1518 {
1519         uint16_t *n = extra_args;
1520
1521         if (value == NULL || extra_args == NULL)
1522                 return -EINVAL;
1523
1524         *n = (uint16_t)strtoul(value, NULL, 0);
1525         if (*n == USHRT_MAX && errno == ERANGE)
1526                 return -1;
1527
1528         return 0;
1529 }
1530
1531 static void
1532 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1533                       struct rte_devargs *devargs)
1534 {
1535         struct rte_kvargs *kvlist;
1536         uint16_t pflink_fullchk;
1537
1538         if (devargs == NULL)
1539                 return;
1540
1541         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1542         if (kvlist == NULL)
1543                 return;
1544
1545         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1546             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1547                                devarg_handle_int, &pflink_fullchk) == 0 &&
1548             pflink_fullchk == 1)
1549                 adapter->pflink_fullchk = 1;
1550
1551         rte_kvargs_free(kvlist);
1552 }
1553
1554 /*
1555  * Virtual Function device init
1556  */
1557 static int
1558 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1559 {
1560         int diag;
1561         uint32_t tc, tcs;
1562         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1563         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1564         struct ixgbe_hw *hw =
1565                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1566         struct ixgbe_vfta *shadow_vfta =
1567                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1568         struct ixgbe_hwstrip *hwstrip =
1569                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1570         struct rte_ether_addr *perm_addr =
1571                 (struct rte_ether_addr *)hw->mac.perm_addr;
1572
1573         PMD_INIT_FUNC_TRACE();
1574
1575         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1576         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1577         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1578
1579         /* for secondary processes, we don't initialise any further as primary
1580          * has already done this work. Only check we don't need a different
1581          * RX function
1582          */
1583         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1584                 struct ixgbe_tx_queue *txq;
1585                 /* TX queue function in primary, set by last queue initialized
1586                  * Tx queue may not initialized by primary process
1587                  */
1588                 if (eth_dev->data->tx_queues) {
1589                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1590                         ixgbe_set_tx_function(eth_dev, txq);
1591                 } else {
1592                         /* Use default TX function if we get here */
1593                         PMD_INIT_LOG(NOTICE,
1594                                      "No TX queues configured yet. Using default TX function.");
1595                 }
1596
1597                 ixgbe_set_rx_function(eth_dev);
1598
1599                 return 0;
1600         }
1601
1602         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1603                               pci_dev->device.devargs);
1604
1605         rte_eth_copy_pci_info(eth_dev, pci_dev);
1606
1607         hw->device_id = pci_dev->id.device_id;
1608         hw->vendor_id = pci_dev->id.vendor_id;
1609         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1610
1611         /* initialize the vfta */
1612         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1613
1614         /* initialize the hw strip bitmap*/
1615         memset(hwstrip, 0, sizeof(*hwstrip));
1616
1617         /* Initialize the shared code (base driver) */
1618         diag = ixgbe_init_shared_code(hw);
1619         if (diag != IXGBE_SUCCESS) {
1620                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1621                 return -EIO;
1622         }
1623
1624         /* init_mailbox_params */
1625         hw->mbx.ops.init_params(hw);
1626
1627         /* Reset the hw statistics */
1628         ixgbevf_dev_stats_reset(eth_dev);
1629
1630         /* Disable the interrupts for VF */
1631         ixgbevf_intr_disable(eth_dev);
1632
1633         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1634         diag = hw->mac.ops.reset_hw(hw);
1635
1636         /*
1637          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1638          * the underlying PF driver has not assigned a MAC address to the VF.
1639          * In this case, assign a random MAC address.
1640          */
1641         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1642                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1643                 /*
1644                  * This error code will be propagated to the app by
1645                  * rte_eth_dev_reset, so use a public error code rather than
1646                  * the internal-only IXGBE_ERR_RESET_FAILED
1647                  */
1648                 return -EAGAIN;
1649         }
1650
1651         /* negotiate mailbox API version to use with the PF. */
1652         ixgbevf_negotiate_api(hw);
1653
1654         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1655         ixgbevf_get_queues(hw, &tcs, &tc);
1656
1657         /* Allocate memory for storing MAC addresses */
1658         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1659                                                hw->mac.num_rar_entries, 0);
1660         if (eth_dev->data->mac_addrs == NULL) {
1661                 PMD_INIT_LOG(ERR,
1662                              "Failed to allocate %u bytes needed to store "
1663                              "MAC addresses",
1664                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1665                 return -ENOMEM;
1666         }
1667
1668         /* Pass the information to the rte_eth_dev_close() that it should also
1669          * release the private port resources.
1670          */
1671         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1672
1673         /* Generate a random MAC address, if none was assigned by PF. */
1674         if (rte_is_zero_ether_addr(perm_addr)) {
1675                 generate_random_mac_addr(perm_addr);
1676                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1677                 if (diag) {
1678                         rte_free(eth_dev->data->mac_addrs);
1679                         eth_dev->data->mac_addrs = NULL;
1680                         return diag;
1681                 }
1682                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1683                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1684                              "%02x:%02x:%02x:%02x:%02x:%02x",
1685                              perm_addr->addr_bytes[0],
1686                              perm_addr->addr_bytes[1],
1687                              perm_addr->addr_bytes[2],
1688                              perm_addr->addr_bytes[3],
1689                              perm_addr->addr_bytes[4],
1690                              perm_addr->addr_bytes[5]);
1691         }
1692
1693         /* Copy the permanent MAC address */
1694         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1695
1696         /* reset the hardware with the new settings */
1697         diag = hw->mac.ops.start_hw(hw);
1698         switch (diag) {
1699         case  0:
1700                 break;
1701
1702         default:
1703                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1704                 return -EIO;
1705         }
1706
1707         rte_intr_callback_register(intr_handle,
1708                                    ixgbevf_dev_interrupt_handler, eth_dev);
1709         rte_intr_enable(intr_handle);
1710         ixgbevf_intr_enable(eth_dev);
1711
1712         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1713                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1714                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1715
1716         return 0;
1717 }
1718
1719 /* Virtual Function device uninit */
1720
1721 static int
1722 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1723 {
1724         PMD_INIT_FUNC_TRACE();
1725
1726         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1727                 return 0;
1728
1729         ixgbevf_dev_close(eth_dev);
1730
1731         return 0;
1732 }
1733
1734 static int
1735 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1736                 struct rte_pci_device *pci_dev)
1737 {
1738         char name[RTE_ETH_NAME_MAX_LEN];
1739         struct rte_eth_dev *pf_ethdev;
1740         struct rte_eth_devargs eth_da;
1741         int i, retval;
1742
1743         if (pci_dev->device.devargs) {
1744                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1745                                 &eth_da);
1746                 if (retval)
1747                         return retval;
1748         } else
1749                 memset(&eth_da, 0, sizeof(eth_da));
1750
1751         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1752                 sizeof(struct ixgbe_adapter),
1753                 eth_dev_pci_specific_init, pci_dev,
1754                 eth_ixgbe_dev_init, NULL);
1755
1756         if (retval || eth_da.nb_representor_ports < 1)
1757                 return retval;
1758
1759         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1760         if (pf_ethdev == NULL)
1761                 return -ENODEV;
1762
1763         /* probe VF representor ports */
1764         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1765                 struct ixgbe_vf_info *vfinfo;
1766                 struct ixgbe_vf_representor representor;
1767
1768                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1769                         pf_ethdev->data->dev_private);
1770                 if (vfinfo == NULL) {
1771                         PMD_DRV_LOG(ERR,
1772                                 "no virtual functions supported by PF");
1773                         break;
1774                 }
1775
1776                 representor.vf_id = eth_da.representor_ports[i];
1777                 representor.switch_domain_id = vfinfo->switch_domain_id;
1778                 representor.pf_ethdev = pf_ethdev;
1779
1780                 /* representor port net_bdf_port */
1781                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1782                         pci_dev->device.name,
1783                         eth_da.representor_ports[i]);
1784
1785                 retval = rte_eth_dev_create(&pci_dev->device, name,
1786                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1787                         ixgbe_vf_representor_init, &representor);
1788
1789                 if (retval)
1790                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1791                                 "representor %s.", name);
1792         }
1793
1794         return 0;
1795 }
1796
1797 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1798 {
1799         struct rte_eth_dev *ethdev;
1800
1801         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1802         if (!ethdev)
1803                 return -ENODEV;
1804
1805         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1806                 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1807         else
1808                 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1809 }
1810
1811 static struct rte_pci_driver rte_ixgbe_pmd = {
1812         .id_table = pci_id_ixgbe_map,
1813         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1814         .probe = eth_ixgbe_pci_probe,
1815         .remove = eth_ixgbe_pci_remove,
1816 };
1817
1818 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1819         struct rte_pci_device *pci_dev)
1820 {
1821         return rte_eth_dev_pci_generic_probe(pci_dev,
1822                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1823 }
1824
1825 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1826 {
1827         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1828 }
1829
1830 /*
1831  * virtual function driver struct
1832  */
1833 static struct rte_pci_driver rte_ixgbevf_pmd = {
1834         .id_table = pci_id_ixgbevf_map,
1835         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1836         .probe = eth_ixgbevf_pci_probe,
1837         .remove = eth_ixgbevf_pci_remove,
1838 };
1839
1840 static int
1841 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1842 {
1843         struct ixgbe_hw *hw =
1844                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1845         struct ixgbe_vfta *shadow_vfta =
1846                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1847         uint32_t vfta;
1848         uint32_t vid_idx;
1849         uint32_t vid_bit;
1850
1851         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1852         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1853         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1854         if (on)
1855                 vfta |= vid_bit;
1856         else
1857                 vfta &= ~vid_bit;
1858         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1859
1860         /* update local VFTA copy */
1861         shadow_vfta->vfta[vid_idx] = vfta;
1862
1863         return 0;
1864 }
1865
1866 static void
1867 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1868 {
1869         if (on)
1870                 ixgbe_vlan_hw_strip_enable(dev, queue);
1871         else
1872                 ixgbe_vlan_hw_strip_disable(dev, queue);
1873 }
1874
1875 static int
1876 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1877                     enum rte_vlan_type vlan_type,
1878                     uint16_t tpid)
1879 {
1880         struct ixgbe_hw *hw =
1881                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1882         int ret = 0;
1883         uint32_t reg;
1884         uint32_t qinq;
1885
1886         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1887         qinq &= IXGBE_DMATXCTL_GDV;
1888
1889         switch (vlan_type) {
1890         case ETH_VLAN_TYPE_INNER:
1891                 if (qinq) {
1892                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1893                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1894                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1895                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1896                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1897                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1898                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1899                 } else {
1900                         ret = -ENOTSUP;
1901                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1902                                     " by single VLAN");
1903                 }
1904                 break;
1905         case ETH_VLAN_TYPE_OUTER:
1906                 if (qinq) {
1907                         /* Only the high 16-bits is valid */
1908                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1909                                         IXGBE_EXVET_VET_EXT_SHIFT);
1910                 } else {
1911                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1912                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1913                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1914                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1915                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1916                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1917                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1918                 }
1919
1920                 break;
1921         default:
1922                 ret = -EINVAL;
1923                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1924                 break;
1925         }
1926
1927         return ret;
1928 }
1929
1930 void
1931 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1932 {
1933         struct ixgbe_hw *hw =
1934                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1935         uint32_t vlnctrl;
1936
1937         PMD_INIT_FUNC_TRACE();
1938
1939         /* Filter Table Disable */
1940         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1941         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1942
1943         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1944 }
1945
1946 void
1947 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1948 {
1949         struct ixgbe_hw *hw =
1950                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1951         struct ixgbe_vfta *shadow_vfta =
1952                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1953         uint32_t vlnctrl;
1954         uint16_t i;
1955
1956         PMD_INIT_FUNC_TRACE();
1957
1958         /* Filter Table Enable */
1959         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1960         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1961         vlnctrl |= IXGBE_VLNCTRL_VFE;
1962
1963         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1964
1965         /* write whatever is in local vfta copy */
1966         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1967                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1968 }
1969
1970 static void
1971 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1972 {
1973         struct ixgbe_hwstrip *hwstrip =
1974                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1975         struct ixgbe_rx_queue *rxq;
1976
1977         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1978                 return;
1979
1980         if (on)
1981                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1982         else
1983                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1984
1985         if (queue >= dev->data->nb_rx_queues)
1986                 return;
1987
1988         rxq = dev->data->rx_queues[queue];
1989
1990         if (on) {
1991                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1992                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1993         } else {
1994                 rxq->vlan_flags = PKT_RX_VLAN;
1995                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1996         }
1997 }
1998
1999 static void
2000 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2001 {
2002         struct ixgbe_hw *hw =
2003                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2004         uint32_t ctrl;
2005
2006         PMD_INIT_FUNC_TRACE();
2007
2008         if (hw->mac.type == ixgbe_mac_82598EB) {
2009                 /* No queue level support */
2010                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2011                 return;
2012         }
2013
2014         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2015         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2016         ctrl &= ~IXGBE_RXDCTL_VME;
2017         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2018
2019         /* record those setting for HW strip per queue */
2020         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2021 }
2022
2023 static void
2024 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2025 {
2026         struct ixgbe_hw *hw =
2027                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2028         uint32_t ctrl;
2029
2030         PMD_INIT_FUNC_TRACE();
2031
2032         if (hw->mac.type == ixgbe_mac_82598EB) {
2033                 /* No queue level supported */
2034                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2035                 return;
2036         }
2037
2038         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2039         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2040         ctrl |= IXGBE_RXDCTL_VME;
2041         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2042
2043         /* record those setting for HW strip per queue */
2044         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2045 }
2046
2047 static void
2048 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2049 {
2050         struct ixgbe_hw *hw =
2051                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2052         uint32_t ctrl;
2053
2054         PMD_INIT_FUNC_TRACE();
2055
2056         /* DMATXCTRL: Geric Double VLAN Disable */
2057         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2058         ctrl &= ~IXGBE_DMATXCTL_GDV;
2059         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2060
2061         /* CTRL_EXT: Global Double VLAN Disable */
2062         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2063         ctrl &= ~IXGBE_EXTENDED_VLAN;
2064         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2065
2066 }
2067
2068 static void
2069 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2070 {
2071         struct ixgbe_hw *hw =
2072                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2073         uint32_t ctrl;
2074
2075         PMD_INIT_FUNC_TRACE();
2076
2077         /* DMATXCTRL: Geric Double VLAN Enable */
2078         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2079         ctrl |= IXGBE_DMATXCTL_GDV;
2080         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2081
2082         /* CTRL_EXT: Global Double VLAN Enable */
2083         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2084         ctrl |= IXGBE_EXTENDED_VLAN;
2085         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2086
2087         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2088         if (hw->mac.type == ixgbe_mac_X550 ||
2089             hw->mac.type == ixgbe_mac_X550EM_x ||
2090             hw->mac.type == ixgbe_mac_X550EM_a) {
2091                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2092                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2093                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2094         }
2095
2096         /*
2097          * VET EXT field in the EXVET register = 0x8100 by default
2098          * So no need to change. Same to VT field of DMATXCTL register
2099          */
2100 }
2101
2102 void
2103 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2104 {
2105         struct ixgbe_hw *hw =
2106                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2107         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2108         uint32_t ctrl;
2109         uint16_t i;
2110         struct ixgbe_rx_queue *rxq;
2111         bool on;
2112
2113         PMD_INIT_FUNC_TRACE();
2114
2115         if (hw->mac.type == ixgbe_mac_82598EB) {
2116                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2117                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2118                         ctrl |= IXGBE_VLNCTRL_VME;
2119                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2120                 } else {
2121                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2122                         ctrl &= ~IXGBE_VLNCTRL_VME;
2123                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2124                 }
2125         } else {
2126                 /*
2127                  * Other 10G NIC, the VLAN strip can be setup
2128                  * per queue in RXDCTL
2129                  */
2130                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2131                         rxq = dev->data->rx_queues[i];
2132                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2133                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2134                                 ctrl |= IXGBE_RXDCTL_VME;
2135                                 on = TRUE;
2136                         } else {
2137                                 ctrl &= ~IXGBE_RXDCTL_VME;
2138                                 on = FALSE;
2139                         }
2140                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2141
2142                         /* record those setting for HW strip per queue */
2143                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2144                 }
2145         }
2146 }
2147
2148 static void
2149 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2150 {
2151         uint16_t i;
2152         struct rte_eth_rxmode *rxmode;
2153         struct ixgbe_rx_queue *rxq;
2154
2155         if (mask & ETH_VLAN_STRIP_MASK) {
2156                 rxmode = &dev->data->dev_conf.rxmode;
2157                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2158                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2159                                 rxq = dev->data->rx_queues[i];
2160                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2161                         }
2162                 else
2163                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2164                                 rxq = dev->data->rx_queues[i];
2165                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2166                         }
2167         }
2168 }
2169
2170 static int
2171 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2172 {
2173         struct rte_eth_rxmode *rxmode;
2174         rxmode = &dev->data->dev_conf.rxmode;
2175
2176         if (mask & ETH_VLAN_STRIP_MASK) {
2177                 ixgbe_vlan_hw_strip_config(dev);
2178         }
2179
2180         if (mask & ETH_VLAN_FILTER_MASK) {
2181                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2182                         ixgbe_vlan_hw_filter_enable(dev);
2183                 else
2184                         ixgbe_vlan_hw_filter_disable(dev);
2185         }
2186
2187         if (mask & ETH_VLAN_EXTEND_MASK) {
2188                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2189                         ixgbe_vlan_hw_extend_enable(dev);
2190                 else
2191                         ixgbe_vlan_hw_extend_disable(dev);
2192         }
2193
2194         return 0;
2195 }
2196
2197 static int
2198 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2199 {
2200         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2201
2202         ixgbe_vlan_offload_config(dev, mask);
2203
2204         return 0;
2205 }
2206
2207 static void
2208 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2209 {
2210         struct ixgbe_hw *hw =
2211                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2212         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2213         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2214
2215         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2216         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2217 }
2218
2219 static int
2220 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2221 {
2222         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2223
2224         switch (nb_rx_q) {
2225         case 1:
2226         case 2:
2227                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2228                 break;
2229         case 4:
2230                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2231                 break;
2232         default:
2233                 return -EINVAL;
2234         }
2235
2236         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2237                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2238         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2239                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2240         return 0;
2241 }
2242
2243 static int
2244 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2245 {
2246         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2247         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2248         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2249         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2250
2251         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2252                 /* check multi-queue mode */
2253                 switch (dev_conf->rxmode.mq_mode) {
2254                 case ETH_MQ_RX_VMDQ_DCB:
2255                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2256                         break;
2257                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2258                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2259                         PMD_INIT_LOG(ERR, "SRIOV active,"
2260                                         " unsupported mq_mode rx %d.",
2261                                         dev_conf->rxmode.mq_mode);
2262                         return -EINVAL;
2263                 case ETH_MQ_RX_RSS:
2264                 case ETH_MQ_RX_VMDQ_RSS:
2265                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2266                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2267                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2268                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2269                                                 " invalid queue number"
2270                                                 " for VMDQ RSS, allowed"
2271                                                 " value are 1, 2 or 4.");
2272                                         return -EINVAL;
2273                                 }
2274                         break;
2275                 case ETH_MQ_RX_VMDQ_ONLY:
2276                 case ETH_MQ_RX_NONE:
2277                         /* if nothing mq mode configure, use default scheme */
2278                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2279                         break;
2280                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2281                         /* SRIOV only works in VMDq enable mode */
2282                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2283                                         " wrong mq_mode rx %d.",
2284                                         dev_conf->rxmode.mq_mode);
2285                         return -EINVAL;
2286                 }
2287
2288                 switch (dev_conf->txmode.mq_mode) {
2289                 case ETH_MQ_TX_VMDQ_DCB:
2290                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2291                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2292                         break;
2293                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2294                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2295                         break;
2296                 }
2297
2298                 /* check valid queue number */
2299                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2300                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2301                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2302                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2303                                         " must be less than or equal to %d.",
2304                                         nb_rx_q, nb_tx_q,
2305                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2306                         return -EINVAL;
2307                 }
2308         } else {
2309                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2310                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2311                                           " not supported.");
2312                         return -EINVAL;
2313                 }
2314                 /* check configuration for vmdb+dcb mode */
2315                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2316                         const struct rte_eth_vmdq_dcb_conf *conf;
2317
2318                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2319                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2320                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2321                                 return -EINVAL;
2322                         }
2323                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2324                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2325                                conf->nb_queue_pools == ETH_32_POOLS)) {
2326                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2327                                                 " nb_queue_pools must be %d or %d.",
2328                                                 ETH_16_POOLS, ETH_32_POOLS);
2329                                 return -EINVAL;
2330                         }
2331                 }
2332                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2333                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2334
2335                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2336                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2337                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2338                                 return -EINVAL;
2339                         }
2340                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2341                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2342                                conf->nb_queue_pools == ETH_32_POOLS)) {
2343                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2344                                                 " nb_queue_pools != %d and"
2345                                                 " nb_queue_pools != %d.",
2346                                                 ETH_16_POOLS, ETH_32_POOLS);
2347                                 return -EINVAL;
2348                         }
2349                 }
2350
2351                 /* For DCB mode check our configuration before we go further */
2352                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2353                         const struct rte_eth_dcb_rx_conf *conf;
2354
2355                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2356                         if (!(conf->nb_tcs == ETH_4_TCS ||
2357                                conf->nb_tcs == ETH_8_TCS)) {
2358                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2359                                                 " and nb_tcs != %d.",
2360                                                 ETH_4_TCS, ETH_8_TCS);
2361                                 return -EINVAL;
2362                         }
2363                 }
2364
2365                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2366                         const struct rte_eth_dcb_tx_conf *conf;
2367
2368                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2369                         if (!(conf->nb_tcs == ETH_4_TCS ||
2370                                conf->nb_tcs == ETH_8_TCS)) {
2371                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2372                                                 " and nb_tcs != %d.",
2373                                                 ETH_4_TCS, ETH_8_TCS);
2374                                 return -EINVAL;
2375                         }
2376                 }
2377
2378                 /*
2379                  * When DCB/VT is off, maximum number of queues changes,
2380                  * except for 82598EB, which remains constant.
2381                  */
2382                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2383                                 hw->mac.type != ixgbe_mac_82598EB) {
2384                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2385                                 PMD_INIT_LOG(ERR,
2386                                              "Neither VT nor DCB are enabled, "
2387                                              "nb_tx_q > %d.",
2388                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2389                                 return -EINVAL;
2390                         }
2391                 }
2392         }
2393         return 0;
2394 }
2395
2396 static int
2397 ixgbe_dev_configure(struct rte_eth_dev *dev)
2398 {
2399         struct ixgbe_interrupt *intr =
2400                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2401         struct ixgbe_adapter *adapter = dev->data->dev_private;
2402         int ret;
2403
2404         PMD_INIT_FUNC_TRACE();
2405         /* multipe queue mode checking */
2406         ret  = ixgbe_check_mq_mode(dev);
2407         if (ret != 0) {
2408                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2409                             ret);
2410                 return ret;
2411         }
2412
2413         /* set flag to update link status after init */
2414         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2415
2416         /*
2417          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2418          * allocation or vector Rx preconditions we will reset it.
2419          */
2420         adapter->rx_bulk_alloc_allowed = true;
2421         adapter->rx_vec_allowed = true;
2422
2423         return 0;
2424 }
2425
2426 static void
2427 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2428 {
2429         struct ixgbe_hw *hw =
2430                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2431         struct ixgbe_interrupt *intr =
2432                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2433         uint32_t gpie;
2434
2435         /* only set up it on X550EM_X */
2436         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2437                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2438                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2439                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2440                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2441                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2442         }
2443 }
2444
2445 int
2446 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2447                         uint16_t tx_rate, uint64_t q_msk)
2448 {
2449         struct ixgbe_hw *hw;
2450         struct ixgbe_vf_info *vfinfo;
2451         struct rte_eth_link link;
2452         uint8_t  nb_q_per_pool;
2453         uint32_t queue_stride;
2454         uint32_t queue_idx, idx = 0, vf_idx;
2455         uint32_t queue_end;
2456         uint16_t total_rate = 0;
2457         struct rte_pci_device *pci_dev;
2458         int ret;
2459
2460         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2461         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2462         if (ret < 0)
2463                 return ret;
2464
2465         if (vf >= pci_dev->max_vfs)
2466                 return -EINVAL;
2467
2468         if (tx_rate > link.link_speed)
2469                 return -EINVAL;
2470
2471         if (q_msk == 0)
2472                 return 0;
2473
2474         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2475         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2476         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2477         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2478         queue_idx = vf * queue_stride;
2479         queue_end = queue_idx + nb_q_per_pool - 1;
2480         if (queue_end >= hw->mac.max_tx_queues)
2481                 return -EINVAL;
2482
2483         if (vfinfo) {
2484                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2485                         if (vf_idx == vf)
2486                                 continue;
2487                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2488                                 idx++)
2489                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2490                 }
2491         } else {
2492                 return -EINVAL;
2493         }
2494
2495         /* Store tx_rate for this vf. */
2496         for (idx = 0; idx < nb_q_per_pool; idx++) {
2497                 if (((uint64_t)0x1 << idx) & q_msk) {
2498                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2499                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2500                         total_rate += tx_rate;
2501                 }
2502         }
2503
2504         if (total_rate > dev->data->dev_link.link_speed) {
2505                 /* Reset stored TX rate of the VF if it causes exceed
2506                  * link speed.
2507                  */
2508                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2509                 return -EINVAL;
2510         }
2511
2512         /* Set RTTBCNRC of each queue/pool for vf X  */
2513         for (; queue_idx <= queue_end; queue_idx++) {
2514                 if (0x1 & q_msk)
2515                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2516                 q_msk = q_msk >> 1;
2517         }
2518
2519         return 0;
2520 }
2521
2522 /*
2523  * Configure device link speed and setup link.
2524  * It returns 0 on success.
2525  */
2526 static int
2527 ixgbe_dev_start(struct rte_eth_dev *dev)
2528 {
2529         struct ixgbe_hw *hw =
2530                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2531         struct ixgbe_vf_info *vfinfo =
2532                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2533         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2534         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2535         uint32_t intr_vector = 0;
2536         int err, link_up = 0, negotiate = 0;
2537         uint32_t speed = 0;
2538         uint32_t allowed_speeds = 0;
2539         int mask = 0;
2540         int status;
2541         uint16_t vf, idx;
2542         uint32_t *link_speeds;
2543         struct ixgbe_tm_conf *tm_conf =
2544                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2545         struct ixgbe_macsec_setting *macsec_ctrl =
2546                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2547
2548         PMD_INIT_FUNC_TRACE();
2549
2550         /* IXGBE devices don't support:
2551         *    - half duplex (checked afterwards for valid speeds)
2552         *    - fixed speed: TODO implement
2553         */
2554         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2555                 PMD_INIT_LOG(ERR,
2556                 "Invalid link_speeds for port %u, fix speed not supported",
2557                                 dev->data->port_id);
2558                 return -EINVAL;
2559         }
2560
2561         /* Stop the link setup handler before resetting the HW. */
2562         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2563
2564         /* disable uio/vfio intr/eventfd mapping */
2565         rte_intr_disable(intr_handle);
2566
2567         /* stop adapter */
2568         hw->adapter_stopped = 0;
2569         ixgbe_stop_adapter(hw);
2570
2571         /* reinitialize adapter
2572          * this calls reset and start
2573          */
2574         status = ixgbe_pf_reset_hw(hw);
2575         if (status != 0)
2576                 return -1;
2577         hw->mac.ops.start_hw(hw);
2578         hw->mac.get_link_status = true;
2579
2580         /* configure PF module if SRIOV enabled */
2581         ixgbe_pf_host_configure(dev);
2582
2583         ixgbe_dev_phy_intr_setup(dev);
2584
2585         /* check and configure queue intr-vector mapping */
2586         if ((rte_intr_cap_multiple(intr_handle) ||
2587              !RTE_ETH_DEV_SRIOV(dev).active) &&
2588             dev->data->dev_conf.intr_conf.rxq != 0) {
2589                 intr_vector = dev->data->nb_rx_queues;
2590                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2591                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2592                                         IXGBE_MAX_INTR_QUEUE_NUM);
2593                         return -ENOTSUP;
2594                 }
2595                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2596                         return -1;
2597         }
2598
2599         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2600                 intr_handle->intr_vec =
2601                         rte_zmalloc("intr_vec",
2602                                     dev->data->nb_rx_queues * sizeof(int), 0);
2603                 if (intr_handle->intr_vec == NULL) {
2604                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2605                                      " intr_vec", dev->data->nb_rx_queues);
2606                         return -ENOMEM;
2607                 }
2608         }
2609
2610         /* confiugre msix for sleep until rx interrupt */
2611         ixgbe_configure_msix(dev);
2612
2613         /* initialize transmission unit */
2614         ixgbe_dev_tx_init(dev);
2615
2616         /* This can fail when allocating mbufs for descriptor rings */
2617         err = ixgbe_dev_rx_init(dev);
2618         if (err) {
2619                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2620                 goto error;
2621         }
2622
2623         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2624                 ETH_VLAN_EXTEND_MASK;
2625         err = ixgbe_vlan_offload_config(dev, mask);
2626         if (err) {
2627                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2628                 goto error;
2629         }
2630
2631         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2632                 /* Enable vlan filtering for VMDq */
2633                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2634         }
2635
2636         /* Configure DCB hw */
2637         ixgbe_configure_dcb(dev);
2638
2639         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2640                 err = ixgbe_fdir_configure(dev);
2641                 if (err)
2642                         goto error;
2643         }
2644
2645         /* Restore vf rate limit */
2646         if (vfinfo != NULL) {
2647                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2648                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2649                                 if (vfinfo[vf].tx_rate[idx] != 0)
2650                                         ixgbe_set_vf_rate_limit(
2651                                                 dev, vf,
2652                                                 vfinfo[vf].tx_rate[idx],
2653                                                 1 << idx);
2654         }
2655
2656         ixgbe_restore_statistics_mapping(dev);
2657
2658         err = ixgbe_dev_rxtx_start(dev);
2659         if (err < 0) {
2660                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2661                 goto error;
2662         }
2663
2664         /* Skip link setup if loopback mode is enabled. */
2665         if (dev->data->dev_conf.lpbk_mode != 0) {
2666                 err = ixgbe_check_supported_loopback_mode(dev);
2667                 if (err < 0) {
2668                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2669                         goto error;
2670                 } else {
2671                         goto skip_link_setup;
2672                 }
2673         }
2674
2675         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2676                 err = hw->mac.ops.setup_sfp(hw);
2677                 if (err)
2678                         goto error;
2679         }
2680
2681         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2682                 /* Turn on the copper */
2683                 ixgbe_set_phy_power(hw, true);
2684         } else {
2685                 /* Turn on the laser */
2686                 ixgbe_enable_tx_laser(hw);
2687         }
2688
2689         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2690         if (err)
2691                 goto error;
2692         dev->data->dev_link.link_status = link_up;
2693
2694         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2695         if (err)
2696                 goto error;
2697
2698         switch (hw->mac.type) {
2699         case ixgbe_mac_X550:
2700         case ixgbe_mac_X550EM_x:
2701         case ixgbe_mac_X550EM_a:
2702                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2703                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2704                         ETH_LINK_SPEED_10G;
2705                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2706                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2707                         allowed_speeds = ETH_LINK_SPEED_10M |
2708                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2709                 break;
2710         default:
2711                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2712                         ETH_LINK_SPEED_10G;
2713         }
2714
2715         link_speeds = &dev->data->dev_conf.link_speeds;
2716         if (*link_speeds & ~allowed_speeds) {
2717                 PMD_INIT_LOG(ERR, "Invalid link setting");
2718                 goto error;
2719         }
2720
2721         speed = 0x0;
2722         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2723                 switch (hw->mac.type) {
2724                 case ixgbe_mac_82598EB:
2725                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2726                         break;
2727                 case ixgbe_mac_82599EB:
2728                 case ixgbe_mac_X540:
2729                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2730                         break;
2731                 case ixgbe_mac_X550:
2732                 case ixgbe_mac_X550EM_x:
2733                 case ixgbe_mac_X550EM_a:
2734                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2735                         break;
2736                 default:
2737                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2738                 }
2739         } else {
2740                 if (*link_speeds & ETH_LINK_SPEED_10G)
2741                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2742                 if (*link_speeds & ETH_LINK_SPEED_5G)
2743                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2744                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2745                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2746                 if (*link_speeds & ETH_LINK_SPEED_1G)
2747                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2748                 if (*link_speeds & ETH_LINK_SPEED_100M)
2749                         speed |= IXGBE_LINK_SPEED_100_FULL;
2750                 if (*link_speeds & ETH_LINK_SPEED_10M)
2751                         speed |= IXGBE_LINK_SPEED_10_FULL;
2752         }
2753
2754         err = ixgbe_setup_link(hw, speed, link_up);
2755         if (err)
2756                 goto error;
2757
2758 skip_link_setup:
2759
2760         if (rte_intr_allow_others(intr_handle)) {
2761                 /* check if lsc interrupt is enabled */
2762                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2763                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2764                 else
2765                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2766                 ixgbe_dev_macsec_interrupt_setup(dev);
2767         } else {
2768                 rte_intr_callback_unregister(intr_handle,
2769                                              ixgbe_dev_interrupt_handler, dev);
2770                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2771                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2772                                      " no intr multiplex");
2773         }
2774
2775         /* check if rxq interrupt is enabled */
2776         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2777             rte_intr_dp_is_en(intr_handle))
2778                 ixgbe_dev_rxq_interrupt_setup(dev);
2779
2780         /* enable uio/vfio intr/eventfd mapping */
2781         rte_intr_enable(intr_handle);
2782
2783         /* resume enabled intr since hw reset */
2784         ixgbe_enable_intr(dev);
2785         ixgbe_l2_tunnel_conf(dev);
2786         ixgbe_filter_restore(dev);
2787
2788         if (tm_conf->root && !tm_conf->committed)
2789                 PMD_DRV_LOG(WARNING,
2790                             "please call hierarchy_commit() "
2791                             "before starting the port");
2792
2793         /*
2794          * Update link status right before return, because it may
2795          * start link configuration process in a separate thread.
2796          */
2797         ixgbe_dev_link_update(dev, 0);
2798
2799         /* setup the macsec ctrl register */
2800         ixgbe_dev_macsec_register_enable(dev, macsec_ctrl);
2801
2802         return 0;
2803
2804 error:
2805         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2806         ixgbe_dev_clear_queues(dev);
2807         return -EIO;
2808 }
2809
2810 /*
2811  * Stop device: disable rx and tx functions to allow for reconfiguring.
2812  */
2813 static void
2814 ixgbe_dev_stop(struct rte_eth_dev *dev)
2815 {
2816         struct rte_eth_link link;
2817         struct ixgbe_adapter *adapter = dev->data->dev_private;
2818         struct ixgbe_hw *hw =
2819                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2820         struct ixgbe_vf_info *vfinfo =
2821                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2822         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2823         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2824         int vf;
2825         struct ixgbe_tm_conf *tm_conf =
2826                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2827
2828         if (hw->adapter_stopped)
2829                 return;
2830
2831         PMD_INIT_FUNC_TRACE();
2832
2833         /* disable mecsec register */
2834         ixgbe_dev_macsec_register_disable(dev);
2835
2836         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2837
2838         /* disable interrupts */
2839         ixgbe_disable_intr(hw);
2840
2841         /* reset the NIC */
2842         ixgbe_pf_reset_hw(hw);
2843         hw->adapter_stopped = 0;
2844
2845         /* stop adapter */
2846         ixgbe_stop_adapter(hw);
2847
2848         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2849                 vfinfo[vf].clear_to_send = false;
2850
2851         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2852                 /* Turn off the copper */
2853                 ixgbe_set_phy_power(hw, false);
2854         } else {
2855                 /* Turn off the laser */
2856                 ixgbe_disable_tx_laser(hw);
2857         }
2858
2859         ixgbe_dev_clear_queues(dev);
2860
2861         /* Clear stored conf */
2862         dev->data->scattered_rx = 0;
2863         dev->data->lro = 0;
2864
2865         /* Clear recorded link status */
2866         memset(&link, 0, sizeof(link));
2867         rte_eth_linkstatus_set(dev, &link);
2868
2869         if (!rte_intr_allow_others(intr_handle))
2870                 /* resume to the default handler */
2871                 rte_intr_callback_register(intr_handle,
2872                                            ixgbe_dev_interrupt_handler,
2873                                            (void *)dev);
2874
2875         /* Clean datapath event and queue/vec mapping */
2876         rte_intr_efd_disable(intr_handle);
2877         if (intr_handle->intr_vec != NULL) {
2878                 rte_free(intr_handle->intr_vec);
2879                 intr_handle->intr_vec = NULL;
2880         }
2881
2882         /* reset hierarchy commit */
2883         tm_conf->committed = false;
2884
2885         adapter->rss_reta_updated = 0;
2886
2887         hw->adapter_stopped = true;
2888 }
2889
2890 /*
2891  * Set device link up: enable tx.
2892  */
2893 static int
2894 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2895 {
2896         struct ixgbe_hw *hw =
2897                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2898         if (hw->mac.type == ixgbe_mac_82599EB) {
2899 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2900                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2901                         /* Not suported in bypass mode */
2902                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2903                                      "by device id 0x%x", hw->device_id);
2904                         return -ENOTSUP;
2905                 }
2906 #endif
2907         }
2908
2909         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2910                 /* Turn on the copper */
2911                 ixgbe_set_phy_power(hw, true);
2912         } else {
2913                 /* Turn on the laser */
2914                 ixgbe_enable_tx_laser(hw);
2915         }
2916
2917         return 0;
2918 }
2919
2920 /*
2921  * Set device link down: disable tx.
2922  */
2923 static int
2924 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2925 {
2926         struct ixgbe_hw *hw =
2927                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2928         if (hw->mac.type == ixgbe_mac_82599EB) {
2929 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2930                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2931                         /* Not suported in bypass mode */
2932                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2933                                      "by device id 0x%x", hw->device_id);
2934                         return -ENOTSUP;
2935                 }
2936 #endif
2937         }
2938
2939         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2940                 /* Turn off the copper */
2941                 ixgbe_set_phy_power(hw, false);
2942         } else {
2943                 /* Turn off the laser */
2944                 ixgbe_disable_tx_laser(hw);
2945         }
2946
2947         return 0;
2948 }
2949
2950 /*
2951  * Reset and stop device.
2952  */
2953 static void
2954 ixgbe_dev_close(struct rte_eth_dev *dev)
2955 {
2956         struct ixgbe_hw *hw =
2957                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2958         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2959         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2960         int retries = 0;
2961         int ret;
2962
2963         PMD_INIT_FUNC_TRACE();
2964
2965         ixgbe_pf_reset_hw(hw);
2966
2967         ixgbe_dev_stop(dev);
2968
2969         ixgbe_dev_free_queues(dev);
2970
2971         ixgbe_disable_pcie_master(hw);
2972
2973         /* reprogram the RAR[0] in case user changed it. */
2974         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2975
2976         dev->dev_ops = NULL;
2977         dev->rx_pkt_burst = NULL;
2978         dev->tx_pkt_burst = NULL;
2979
2980         /* Unlock any pending hardware semaphore */
2981         ixgbe_swfw_lock_reset(hw);
2982
2983         /* disable uio intr before callback unregister */
2984         rte_intr_disable(intr_handle);
2985
2986         do {
2987                 ret = rte_intr_callback_unregister(intr_handle,
2988                                 ixgbe_dev_interrupt_handler, dev);
2989                 if (ret >= 0) {
2990                         break;
2991                 } else if (ret != -EAGAIN) {
2992                         PMD_INIT_LOG(ERR,
2993                                 "intr callback unregister failed: %d",
2994                                 ret);
2995                 }
2996                 rte_delay_ms(100);
2997         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
2998
2999         /* cancel the delay handler before remove dev */
3000         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3001
3002         /* uninitialize PF if max_vfs not zero */
3003         ixgbe_pf_host_uninit(dev);
3004
3005         /* remove all the fdir filters & hash */
3006         ixgbe_fdir_filter_uninit(dev);
3007
3008         /* remove all the L2 tunnel filters & hash */
3009         ixgbe_l2_tn_filter_uninit(dev);
3010
3011         /* Remove all ntuple filters of the device */
3012         ixgbe_ntuple_filter_uninit(dev);
3013
3014         /* clear all the filters list */
3015         ixgbe_filterlist_flush();
3016
3017         /* Remove all Traffic Manager configuration */
3018         ixgbe_tm_conf_uninit(dev);
3019
3020 #ifdef RTE_LIBRTE_SECURITY
3021         rte_free(dev->security_ctx);
3022 #endif
3023
3024 }
3025
3026 /*
3027  * Reset PF device.
3028  */
3029 static int
3030 ixgbe_dev_reset(struct rte_eth_dev *dev)
3031 {
3032         int ret;
3033
3034         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3035          * its VF to make them align with it. The detailed notification
3036          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3037          * To avoid unexpected behavior in VF, currently reset of PF with
3038          * SR-IOV activation is not supported. It might be supported later.
3039          */
3040         if (dev->data->sriov.active)
3041                 return -ENOTSUP;
3042
3043         ret = eth_ixgbe_dev_uninit(dev);
3044         if (ret)
3045                 return ret;
3046
3047         ret = eth_ixgbe_dev_init(dev, NULL);
3048
3049         return ret;
3050 }
3051
3052 static void
3053 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3054                            struct ixgbe_hw_stats *hw_stats,
3055                            struct ixgbe_macsec_stats *macsec_stats,
3056                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3057                            uint64_t *total_qprc, uint64_t *total_qprdc)
3058 {
3059         uint32_t bprc, lxon, lxoff, total;
3060         uint32_t delta_gprc = 0;
3061         unsigned i;
3062         /* Workaround for RX byte count not including CRC bytes when CRC
3063          * strip is enabled. CRC bytes are removed from counters when crc_strip
3064          * is disabled.
3065          */
3066         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3067                         IXGBE_HLREG0_RXCRCSTRP);
3068
3069         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3070         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3071         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3072         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3073
3074         for (i = 0; i < 8; i++) {
3075                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3076
3077                 /* global total per queue */
3078                 hw_stats->mpc[i] += mp;
3079                 /* Running comprehensive total for stats display */
3080                 *total_missed_rx += hw_stats->mpc[i];
3081                 if (hw->mac.type == ixgbe_mac_82598EB) {
3082                         hw_stats->rnbc[i] +=
3083                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3084                         hw_stats->pxonrxc[i] +=
3085                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3086                         hw_stats->pxoffrxc[i] +=
3087                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3088                 } else {
3089                         hw_stats->pxonrxc[i] +=
3090                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3091                         hw_stats->pxoffrxc[i] +=
3092                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3093                         hw_stats->pxon2offc[i] +=
3094                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3095                 }
3096                 hw_stats->pxontxc[i] +=
3097                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3098                 hw_stats->pxofftxc[i] +=
3099                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3100         }
3101         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3102                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3103                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3104                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3105
3106                 delta_gprc += delta_qprc;
3107
3108                 hw_stats->qprc[i] += delta_qprc;
3109                 hw_stats->qptc[i] += delta_qptc;
3110
3111                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3112                 hw_stats->qbrc[i] +=
3113                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3114                 if (crc_strip == 0)
3115                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3116
3117                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3118                 hw_stats->qbtc[i] +=
3119                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3120
3121                 hw_stats->qprdc[i] += delta_qprdc;
3122                 *total_qprdc += hw_stats->qprdc[i];
3123
3124                 *total_qprc += hw_stats->qprc[i];
3125                 *total_qbrc += hw_stats->qbrc[i];
3126         }
3127         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3128         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3129         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3130
3131         /*
3132          * An errata states that gprc actually counts good + missed packets:
3133          * Workaround to set gprc to summated queue packet receives
3134          */
3135         hw_stats->gprc = *total_qprc;
3136
3137         if (hw->mac.type != ixgbe_mac_82598EB) {
3138                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3139                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3140                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3141                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3142                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3143                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3144                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3145                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3146         } else {
3147                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3148                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3149                 /* 82598 only has a counter in the high register */
3150                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3151                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3152                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3153         }
3154         uint64_t old_tpr = hw_stats->tpr;
3155
3156         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3157         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3158
3159         if (crc_strip == 0)
3160                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3161
3162         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3163         hw_stats->gptc += delta_gptc;
3164         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3165         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3166
3167         /*
3168          * Workaround: mprc hardware is incorrectly counting
3169          * broadcasts, so for now we subtract those.
3170          */
3171         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3172         hw_stats->bprc += bprc;
3173         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3174         if (hw->mac.type == ixgbe_mac_82598EB)
3175                 hw_stats->mprc -= bprc;
3176
3177         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3178         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3179         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3180         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3181         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3182         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3183
3184         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3185         hw_stats->lxontxc += lxon;
3186         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3187         hw_stats->lxofftxc += lxoff;
3188         total = lxon + lxoff;
3189
3190         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3191         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3192         hw_stats->gptc -= total;
3193         hw_stats->mptc -= total;
3194         hw_stats->ptc64 -= total;
3195         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3196
3197         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3198         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3199         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3200         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3201         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3202         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3203         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3204         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3205         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3206         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3207         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3208         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3209         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3210         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3211         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3212         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3213         /* Only read FCOE on 82599 */
3214         if (hw->mac.type != ixgbe_mac_82598EB) {
3215                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3216                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3217                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3218                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3219                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3220         }
3221
3222         /* Flow Director Stats registers */
3223         if (hw->mac.type != ixgbe_mac_82598EB) {
3224                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3225                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3226                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3227                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3228                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3229                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3230                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3231                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3232                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3233                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3234         }
3235         /* MACsec Stats registers */
3236         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3237         macsec_stats->out_pkts_encrypted +=
3238                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3239         macsec_stats->out_pkts_protected +=
3240                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3241         macsec_stats->out_octets_encrypted +=
3242                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3243         macsec_stats->out_octets_protected +=
3244                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3245         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3246         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3247         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3248         macsec_stats->in_pkts_unknownsci +=
3249                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3250         macsec_stats->in_octets_decrypted +=
3251                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3252         macsec_stats->in_octets_validated +=
3253                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3254         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3255         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3256         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3257         for (i = 0; i < 2; i++) {
3258                 macsec_stats->in_pkts_ok +=
3259                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3260                 macsec_stats->in_pkts_invalid +=
3261                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3262                 macsec_stats->in_pkts_notvalid +=
3263                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3264         }
3265         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3266         macsec_stats->in_pkts_notusingsa +=
3267                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3268 }
3269
3270 /*
3271  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3272  */
3273 static int
3274 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3275 {
3276         struct ixgbe_hw *hw =
3277                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3278         struct ixgbe_hw_stats *hw_stats =
3279                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3280         struct ixgbe_macsec_stats *macsec_stats =
3281                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3282                                 dev->data->dev_private);
3283         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3284         unsigned i;
3285
3286         total_missed_rx = 0;
3287         total_qbrc = 0;
3288         total_qprc = 0;
3289         total_qprdc = 0;
3290
3291         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3292                         &total_qbrc, &total_qprc, &total_qprdc);
3293
3294         if (stats == NULL)
3295                 return -EINVAL;
3296
3297         /* Fill out the rte_eth_stats statistics structure */
3298         stats->ipackets = total_qprc;
3299         stats->ibytes = total_qbrc;
3300         stats->opackets = hw_stats->gptc;
3301         stats->obytes = hw_stats->gotc;
3302
3303         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3304                 stats->q_ipackets[i] = hw_stats->qprc[i];
3305                 stats->q_opackets[i] = hw_stats->qptc[i];
3306                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3307                 stats->q_obytes[i] = hw_stats->qbtc[i];
3308                 stats->q_errors[i] = hw_stats->qprdc[i];
3309         }
3310
3311         /* Rx Errors */
3312         stats->imissed  = total_missed_rx;
3313         stats->ierrors  = hw_stats->crcerrs +
3314                           hw_stats->mspdc +
3315                           hw_stats->rlec +
3316                           hw_stats->ruc +
3317                           hw_stats->roc +
3318                           hw_stats->illerrc +
3319                           hw_stats->errbc +
3320                           hw_stats->rfc +
3321                           hw_stats->fccrc +
3322                           hw_stats->fclast;
3323
3324         /* Tx Errors */
3325         stats->oerrors  = 0;
3326         return 0;
3327 }
3328
3329 static int
3330 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3331 {
3332         struct ixgbe_hw_stats *stats =
3333                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3334
3335         /* HW registers are cleared on read */
3336         ixgbe_dev_stats_get(dev, NULL);
3337
3338         /* Reset software totals */
3339         memset(stats, 0, sizeof(*stats));
3340
3341         return 0;
3342 }
3343
3344 /* This function calculates the number of xstats based on the current config */
3345 static unsigned
3346 ixgbe_xstats_calc_num(void) {
3347         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3348                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3349                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3350 }
3351
3352 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3353         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3354 {
3355         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3356         unsigned stat, i, count;
3357
3358         if (xstats_names != NULL) {
3359                 count = 0;
3360
3361                 /* Note: limit >= cnt_stats checked upstream
3362                  * in rte_eth_xstats_names()
3363                  */
3364
3365                 /* Extended stats from ixgbe_hw_stats */
3366                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3367                         strlcpy(xstats_names[count].name,
3368                                 rte_ixgbe_stats_strings[i].name,
3369                                 sizeof(xstats_names[count].name));
3370                         count++;
3371                 }
3372
3373                 /* MACsec Stats */
3374                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3375                         strlcpy(xstats_names[count].name,
3376                                 rte_ixgbe_macsec_strings[i].name,
3377                                 sizeof(xstats_names[count].name));
3378                         count++;
3379                 }
3380
3381                 /* RX Priority Stats */
3382                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3383                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3384                                 snprintf(xstats_names[count].name,
3385                                         sizeof(xstats_names[count].name),
3386                                         "rx_priority%u_%s", i,
3387                                         rte_ixgbe_rxq_strings[stat].name);
3388                                 count++;
3389                         }
3390                 }
3391
3392                 /* TX Priority Stats */
3393                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3394                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3395                                 snprintf(xstats_names[count].name,
3396                                         sizeof(xstats_names[count].name),
3397                                         "tx_priority%u_%s", i,
3398                                         rte_ixgbe_txq_strings[stat].name);
3399                                 count++;
3400                         }
3401                 }
3402         }
3403         return cnt_stats;
3404 }
3405
3406 static int ixgbe_dev_xstats_get_names_by_id(
3407         struct rte_eth_dev *dev,
3408         struct rte_eth_xstat_name *xstats_names,
3409         const uint64_t *ids,
3410         unsigned int limit)
3411 {
3412         if (!ids) {
3413                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3414                 unsigned int stat, i, count;
3415
3416                 if (xstats_names != NULL) {
3417                         count = 0;
3418
3419                         /* Note: limit >= cnt_stats checked upstream
3420                          * in rte_eth_xstats_names()
3421                          */
3422
3423                         /* Extended stats from ixgbe_hw_stats */
3424                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3425                                 strlcpy(xstats_names[count].name,
3426                                         rte_ixgbe_stats_strings[i].name,
3427                                         sizeof(xstats_names[count].name));
3428                                 count++;
3429                         }
3430
3431                         /* MACsec Stats */
3432                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3433                                 strlcpy(xstats_names[count].name,
3434                                         rte_ixgbe_macsec_strings[i].name,
3435                                         sizeof(xstats_names[count].name));
3436                                 count++;
3437                         }
3438
3439                         /* RX Priority Stats */
3440                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3441                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3442                                         snprintf(xstats_names[count].name,
3443                                             sizeof(xstats_names[count].name),
3444                                             "rx_priority%u_%s", i,
3445                                             rte_ixgbe_rxq_strings[stat].name);
3446                                         count++;
3447                                 }
3448                         }
3449
3450                         /* TX Priority Stats */
3451                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3452                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3453                                         snprintf(xstats_names[count].name,
3454                                             sizeof(xstats_names[count].name),
3455                                             "tx_priority%u_%s", i,
3456                                             rte_ixgbe_txq_strings[stat].name);
3457                                         count++;
3458                                 }
3459                         }
3460                 }
3461                 return cnt_stats;
3462         }
3463
3464         uint16_t i;
3465         uint16_t size = ixgbe_xstats_calc_num();
3466         struct rte_eth_xstat_name xstats_names_copy[size];
3467
3468         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3469                         size);
3470
3471         for (i = 0; i < limit; i++) {
3472                 if (ids[i] >= size) {
3473                         PMD_INIT_LOG(ERR, "id value isn't valid");
3474                         return -1;
3475                 }
3476                 strcpy(xstats_names[i].name,
3477                                 xstats_names_copy[ids[i]].name);
3478         }
3479         return limit;
3480 }
3481
3482 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3483         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3484 {
3485         unsigned i;
3486
3487         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3488                 return -ENOMEM;
3489
3490         if (xstats_names != NULL)
3491                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3492                         strlcpy(xstats_names[i].name,
3493                                 rte_ixgbevf_stats_strings[i].name,
3494                                 sizeof(xstats_names[i].name));
3495         return IXGBEVF_NB_XSTATS;
3496 }
3497
3498 static int
3499 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3500                                          unsigned n)
3501 {
3502         struct ixgbe_hw *hw =
3503                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3504         struct ixgbe_hw_stats *hw_stats =
3505                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3506         struct ixgbe_macsec_stats *macsec_stats =
3507                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3508                                 dev->data->dev_private);
3509         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3510         unsigned i, stat, count = 0;
3511
3512         count = ixgbe_xstats_calc_num();
3513
3514         if (n < count)
3515                 return count;
3516
3517         total_missed_rx = 0;
3518         total_qbrc = 0;
3519         total_qprc = 0;
3520         total_qprdc = 0;
3521
3522         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3523                         &total_qbrc, &total_qprc, &total_qprdc);
3524
3525         /* If this is a reset xstats is NULL, and we have cleared the
3526          * registers by reading them.
3527          */
3528         if (!xstats)
3529                 return 0;
3530
3531         /* Extended stats from ixgbe_hw_stats */
3532         count = 0;
3533         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3534                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3535                                 rte_ixgbe_stats_strings[i].offset);
3536                 xstats[count].id = count;
3537                 count++;
3538         }
3539
3540         /* MACsec Stats */
3541         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3542                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3543                                 rte_ixgbe_macsec_strings[i].offset);
3544                 xstats[count].id = count;
3545                 count++;
3546         }
3547
3548         /* RX Priority Stats */
3549         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3550                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3551                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3552                                         rte_ixgbe_rxq_strings[stat].offset +
3553                                         (sizeof(uint64_t) * i));
3554                         xstats[count].id = count;
3555                         count++;
3556                 }
3557         }
3558
3559         /* TX Priority Stats */
3560         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3561                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3562                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3563                                         rte_ixgbe_txq_strings[stat].offset +
3564                                         (sizeof(uint64_t) * i));
3565                         xstats[count].id = count;
3566                         count++;
3567                 }
3568         }
3569         return count;
3570 }
3571
3572 static int
3573 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3574                 uint64_t *values, unsigned int n)
3575 {
3576         if (!ids) {
3577                 struct ixgbe_hw *hw =
3578                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3579                 struct ixgbe_hw_stats *hw_stats =
3580                                 IXGBE_DEV_PRIVATE_TO_STATS(
3581                                                 dev->data->dev_private);
3582                 struct ixgbe_macsec_stats *macsec_stats =
3583                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3584                                         dev->data->dev_private);
3585                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3586                 unsigned int i, stat, count = 0;
3587
3588                 count = ixgbe_xstats_calc_num();
3589
3590                 if (!ids && n < count)
3591                         return count;
3592
3593                 total_missed_rx = 0;
3594                 total_qbrc = 0;
3595                 total_qprc = 0;
3596                 total_qprdc = 0;
3597
3598                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3599                                 &total_missed_rx, &total_qbrc, &total_qprc,
3600                                 &total_qprdc);
3601
3602                 /* If this is a reset xstats is NULL, and we have cleared the
3603                  * registers by reading them.
3604                  */
3605                 if (!ids && !values)
3606                         return 0;
3607
3608                 /* Extended stats from ixgbe_hw_stats */
3609                 count = 0;
3610                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3611                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3612                                         rte_ixgbe_stats_strings[i].offset);
3613                         count++;
3614                 }
3615
3616                 /* MACsec Stats */
3617                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3618                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3619                                         rte_ixgbe_macsec_strings[i].offset);
3620                         count++;
3621                 }
3622
3623                 /* RX Priority Stats */
3624                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3625                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3626                                 values[count] =
3627                                         *(uint64_t *)(((char *)hw_stats) +
3628                                         rte_ixgbe_rxq_strings[stat].offset +
3629                                         (sizeof(uint64_t) * i));
3630                                 count++;
3631                         }
3632                 }
3633
3634                 /* TX Priority Stats */
3635                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3636                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3637                                 values[count] =
3638                                         *(uint64_t *)(((char *)hw_stats) +
3639                                         rte_ixgbe_txq_strings[stat].offset +
3640                                         (sizeof(uint64_t) * i));
3641                                 count++;
3642                         }
3643                 }
3644                 return count;
3645         }
3646
3647         uint16_t i;
3648         uint16_t size = ixgbe_xstats_calc_num();
3649         uint64_t values_copy[size];
3650
3651         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3652
3653         for (i = 0; i < n; i++) {
3654                 if (ids[i] >= size) {
3655                         PMD_INIT_LOG(ERR, "id value isn't valid");
3656                         return -1;
3657                 }
3658                 values[i] = values_copy[ids[i]];
3659         }
3660         return n;
3661 }
3662
3663 static int
3664 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3665 {
3666         struct ixgbe_hw_stats *stats =
3667                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3668         struct ixgbe_macsec_stats *macsec_stats =
3669                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3670                                 dev->data->dev_private);
3671
3672         unsigned count = ixgbe_xstats_calc_num();
3673
3674         /* HW registers are cleared on read */
3675         ixgbe_dev_xstats_get(dev, NULL, count);
3676
3677         /* Reset software totals */
3678         memset(stats, 0, sizeof(*stats));
3679         memset(macsec_stats, 0, sizeof(*macsec_stats));
3680
3681         return 0;
3682 }
3683
3684 static void
3685 ixgbevf_update_stats(struct rte_eth_dev *dev)
3686 {
3687         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3688         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3689                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3690
3691         /* Good Rx packet, include VF loopback */
3692         UPDATE_VF_STAT(IXGBE_VFGPRC,
3693             hw_stats->last_vfgprc, hw_stats->vfgprc);
3694
3695         /* Good Rx octets, include VF loopback */
3696         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3697             hw_stats->last_vfgorc, hw_stats->vfgorc);
3698
3699         /* Good Tx packet, include VF loopback */
3700         UPDATE_VF_STAT(IXGBE_VFGPTC,
3701             hw_stats->last_vfgptc, hw_stats->vfgptc);
3702
3703         /* Good Tx octets, include VF loopback */
3704         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3705             hw_stats->last_vfgotc, hw_stats->vfgotc);
3706
3707         /* Rx Multicst Packet */
3708         UPDATE_VF_STAT(IXGBE_VFMPRC,
3709             hw_stats->last_vfmprc, hw_stats->vfmprc);
3710 }
3711
3712 static int
3713 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3714                        unsigned n)
3715 {
3716         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3717                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3718         unsigned i;
3719
3720         if (n < IXGBEVF_NB_XSTATS)
3721                 return IXGBEVF_NB_XSTATS;
3722
3723         ixgbevf_update_stats(dev);
3724
3725         if (!xstats)
3726                 return 0;
3727
3728         /* Extended stats */
3729         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3730                 xstats[i].id = i;
3731                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3732                         rte_ixgbevf_stats_strings[i].offset);
3733         }
3734
3735         return IXGBEVF_NB_XSTATS;
3736 }
3737
3738 static int
3739 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3740 {
3741         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3742                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3743
3744         ixgbevf_update_stats(dev);
3745
3746         if (stats == NULL)
3747                 return -EINVAL;
3748
3749         stats->ipackets = hw_stats->vfgprc;
3750         stats->ibytes = hw_stats->vfgorc;
3751         stats->opackets = hw_stats->vfgptc;
3752         stats->obytes = hw_stats->vfgotc;
3753         return 0;
3754 }
3755
3756 static int
3757 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3758 {
3759         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3760                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3761
3762         /* Sync HW register to the last stats */
3763         ixgbevf_dev_stats_get(dev, NULL);
3764
3765         /* reset HW current stats*/
3766         hw_stats->vfgprc = 0;
3767         hw_stats->vfgorc = 0;
3768         hw_stats->vfgptc = 0;
3769         hw_stats->vfgotc = 0;
3770
3771         return 0;
3772 }
3773
3774 static int
3775 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3776 {
3777         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3778         u16 eeprom_verh, eeprom_verl;
3779         u32 etrack_id;
3780         int ret;
3781
3782         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3783         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3784
3785         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3786         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3787
3788         ret += 1; /* add the size of '\0' */
3789         if (fw_size < (u32)ret)
3790                 return ret;
3791         else
3792                 return 0;
3793 }
3794
3795 static int
3796 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3797 {
3798         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3799         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3800         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3801
3802         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3803         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3804         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3805                 /*
3806                  * When DCB/VT is off, maximum number of queues changes,
3807                  * except for 82598EB, which remains constant.
3808                  */
3809                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3810                                 hw->mac.type != ixgbe_mac_82598EB)
3811                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3812         }
3813         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3814         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3815         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3816         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3817         dev_info->max_vfs = pci_dev->max_vfs;
3818         if (hw->mac.type == ixgbe_mac_82598EB)
3819                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3820         else
3821                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3822         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3823         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3824         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3825         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3826         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3827                                      dev_info->rx_queue_offload_capa);
3828         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3829         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3830
3831         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3832                 .rx_thresh = {
3833                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3834                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3835                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3836                 },
3837                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3838                 .rx_drop_en = 0,
3839                 .offloads = 0,
3840         };
3841
3842         dev_info->default_txconf = (struct rte_eth_txconf) {
3843                 .tx_thresh = {
3844                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3845                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3846                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3847                 },
3848                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3849                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3850                 .offloads = 0,
3851         };
3852
3853         dev_info->rx_desc_lim = rx_desc_lim;
3854         dev_info->tx_desc_lim = tx_desc_lim;
3855
3856         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3857         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3858         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3859
3860         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3861         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3862                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3863                 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3864                         ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3865
3866         if (hw->mac.type == ixgbe_mac_X540 ||
3867             hw->mac.type == ixgbe_mac_X540_vf ||
3868             hw->mac.type == ixgbe_mac_X550 ||
3869             hw->mac.type == ixgbe_mac_X550_vf) {
3870                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3871         }
3872         if (hw->mac.type == ixgbe_mac_X550) {
3873                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3874                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3875         }
3876
3877         /* Driver-preferred Rx/Tx parameters */
3878         dev_info->default_rxportconf.burst_size = 32;
3879         dev_info->default_txportconf.burst_size = 32;
3880         dev_info->default_rxportconf.nb_queues = 1;
3881         dev_info->default_txportconf.nb_queues = 1;
3882         dev_info->default_rxportconf.ring_size = 256;
3883         dev_info->default_txportconf.ring_size = 256;
3884
3885         return 0;
3886 }
3887
3888 static const uint32_t *
3889 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3890 {
3891         static const uint32_t ptypes[] = {
3892                 /* For non-vec functions,
3893                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3894                  * for vec functions,
3895                  * refers to _recv_raw_pkts_vec().
3896                  */
3897                 RTE_PTYPE_L2_ETHER,
3898                 RTE_PTYPE_L3_IPV4,
3899                 RTE_PTYPE_L3_IPV4_EXT,
3900                 RTE_PTYPE_L3_IPV6,
3901                 RTE_PTYPE_L3_IPV6_EXT,
3902                 RTE_PTYPE_L4_SCTP,
3903                 RTE_PTYPE_L4_TCP,
3904                 RTE_PTYPE_L4_UDP,
3905                 RTE_PTYPE_TUNNEL_IP,
3906                 RTE_PTYPE_INNER_L3_IPV6,
3907                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3908                 RTE_PTYPE_INNER_L4_TCP,
3909                 RTE_PTYPE_INNER_L4_UDP,
3910                 RTE_PTYPE_UNKNOWN
3911         };
3912
3913         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3914             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3915             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3916             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3917                 return ptypes;
3918
3919 #if defined(RTE_ARCH_X86) || defined(RTE_MACHINE_CPUFLAG_NEON)
3920         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3921             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3922                 return ptypes;
3923 #endif
3924         return NULL;
3925 }
3926
3927 static int
3928 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3929                      struct rte_eth_dev_info *dev_info)
3930 {
3931         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3932         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3933
3934         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3935         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3936         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3937         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3938         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3939         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3940         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3941         dev_info->max_vfs = pci_dev->max_vfs;
3942         if (hw->mac.type == ixgbe_mac_82598EB)
3943                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3944         else
3945                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3946         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3947         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3948                                      dev_info->rx_queue_offload_capa);
3949         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3950         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3951         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3952         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3953         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3954
3955         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3956                 .rx_thresh = {
3957                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3958                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3959                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3960                 },
3961                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3962                 .rx_drop_en = 0,
3963                 .offloads = 0,
3964         };
3965
3966         dev_info->default_txconf = (struct rte_eth_txconf) {
3967                 .tx_thresh = {
3968                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3969                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3970                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3971                 },
3972                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3973                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3974                 .offloads = 0,
3975         };
3976
3977         dev_info->rx_desc_lim = rx_desc_lim;
3978         dev_info->tx_desc_lim = tx_desc_lim;
3979
3980         return 0;
3981 }
3982
3983 static int
3984 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3985                    int *link_up, int wait_to_complete)
3986 {
3987         struct ixgbe_adapter *adapter = container_of(hw,
3988                                                      struct ixgbe_adapter, hw);
3989         struct ixgbe_mbx_info *mbx = &hw->mbx;
3990         struct ixgbe_mac_info *mac = &hw->mac;
3991         uint32_t links_reg, in_msg;
3992         int ret_val = 0;
3993
3994         /* If we were hit with a reset drop the link */
3995         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3996                 mac->get_link_status = true;
3997
3998         if (!mac->get_link_status)
3999                 goto out;
4000
4001         /* if link status is down no point in checking to see if pf is up */
4002         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4003         if (!(links_reg & IXGBE_LINKS_UP))
4004                 goto out;
4005
4006         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4007          * before the link status is correct
4008          */
4009         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4010                 int i;
4011
4012                 for (i = 0; i < 5; i++) {
4013                         rte_delay_us(100);
4014                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4015
4016                         if (!(links_reg & IXGBE_LINKS_UP))
4017                                 goto out;
4018                 }
4019         }
4020
4021         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4022         case IXGBE_LINKS_SPEED_10G_82599:
4023                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4024                 if (hw->mac.type >= ixgbe_mac_X550) {
4025                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4026                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4027                 }
4028                 break;
4029         case IXGBE_LINKS_SPEED_1G_82599:
4030                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4031                 break;
4032         case IXGBE_LINKS_SPEED_100_82599:
4033                 *speed = IXGBE_LINK_SPEED_100_FULL;
4034                 if (hw->mac.type == ixgbe_mac_X550) {
4035                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4036                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4037                 }
4038                 break;
4039         case IXGBE_LINKS_SPEED_10_X550EM_A:
4040                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4041                 /* Since Reserved in older MAC's */
4042                 if (hw->mac.type >= ixgbe_mac_X550)
4043                         *speed = IXGBE_LINK_SPEED_10_FULL;
4044                 break;
4045         default:
4046                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4047         }
4048
4049         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4050                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4051                         mac->get_link_status = true;
4052                 else
4053                         mac->get_link_status = false;
4054
4055                 goto out;
4056         }
4057
4058         /* if the read failed it could just be a mailbox collision, best wait
4059          * until we are called again and don't report an error
4060          */
4061         if (mbx->ops.read(hw, &in_msg, 1, 0))
4062                 goto out;
4063
4064         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4065                 /* msg is not CTS and is NACK we must have lost CTS status */
4066                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4067                         mac->get_link_status = false;
4068                 goto out;
4069         }
4070
4071         /* the pf is talking, if we timed out in the past we reinit */
4072         if (!mbx->timeout) {
4073                 ret_val = -1;
4074                 goto out;
4075         }
4076
4077         /* if we passed all the tests above then the link is up and we no
4078          * longer need to check for link
4079          */
4080         mac->get_link_status = false;
4081
4082 out:
4083         *link_up = !mac->get_link_status;
4084         return ret_val;
4085 }
4086
4087 static void
4088 ixgbe_dev_setup_link_alarm_handler(void *param)
4089 {
4090         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4091         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4092         struct ixgbe_interrupt *intr =
4093                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4094         u32 speed;
4095         bool autoneg = false;
4096
4097         speed = hw->phy.autoneg_advertised;
4098         if (!speed)
4099                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4100
4101         ixgbe_setup_link(hw, speed, true);
4102
4103         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4104 }
4105
4106 /* return 0 means link status changed, -1 means not changed */
4107 int
4108 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4109                             int wait_to_complete, int vf)
4110 {
4111         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4112         struct rte_eth_link link;
4113         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4114         struct ixgbe_interrupt *intr =
4115                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4116         int link_up;
4117         int diag;
4118         int wait = 1;
4119
4120         memset(&link, 0, sizeof(link));
4121         link.link_status = ETH_LINK_DOWN;
4122         link.link_speed = ETH_SPEED_NUM_NONE;
4123         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4124         link.link_autoneg = ETH_LINK_AUTONEG;
4125
4126         hw->mac.get_link_status = true;
4127
4128         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4129                 return rte_eth_linkstatus_set(dev, &link);
4130
4131         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4132         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4133                 wait = 0;
4134
4135         if (vf)
4136                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4137         else
4138                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4139
4140         if (diag != 0) {
4141                 link.link_speed = ETH_SPEED_NUM_100M;
4142                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4143                 return rte_eth_linkstatus_set(dev, &link);
4144         }
4145
4146         if (link_up == 0) {
4147                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4148                         intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4149                         rte_eal_alarm_set(10,
4150                                 ixgbe_dev_setup_link_alarm_handler, dev);
4151                 }
4152                 return rte_eth_linkstatus_set(dev, &link);
4153         }
4154
4155         link.link_status = ETH_LINK_UP;
4156         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4157
4158         switch (link_speed) {
4159         default:
4160         case IXGBE_LINK_SPEED_UNKNOWN:
4161                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4162                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4163                         link.link_speed = ETH_SPEED_NUM_10M;
4164                 else
4165                         link.link_speed = ETH_SPEED_NUM_100M;
4166                 break;
4167
4168         case IXGBE_LINK_SPEED_100_FULL:
4169                 link.link_speed = ETH_SPEED_NUM_100M;
4170                 break;
4171
4172         case IXGBE_LINK_SPEED_1GB_FULL:
4173                 link.link_speed = ETH_SPEED_NUM_1G;
4174                 break;
4175
4176         case IXGBE_LINK_SPEED_2_5GB_FULL:
4177                 link.link_speed = ETH_SPEED_NUM_2_5G;
4178                 break;
4179
4180         case IXGBE_LINK_SPEED_5GB_FULL:
4181                 link.link_speed = ETH_SPEED_NUM_5G;
4182                 break;
4183
4184         case IXGBE_LINK_SPEED_10GB_FULL:
4185                 link.link_speed = ETH_SPEED_NUM_10G;
4186                 break;
4187         }
4188
4189         return rte_eth_linkstatus_set(dev, &link);
4190 }
4191
4192 static int
4193 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4194 {
4195         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4196 }
4197
4198 static int
4199 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4200 {
4201         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4202 }
4203
4204 static int
4205 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4206 {
4207         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4208         uint32_t fctrl;
4209
4210         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4211         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4212         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4213
4214         return 0;
4215 }
4216
4217 static int
4218 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4219 {
4220         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4221         uint32_t fctrl;
4222
4223         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4224         fctrl &= (~IXGBE_FCTRL_UPE);
4225         if (dev->data->all_multicast == 1)
4226                 fctrl |= IXGBE_FCTRL_MPE;
4227         else
4228                 fctrl &= (~IXGBE_FCTRL_MPE);
4229         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4230
4231         return 0;
4232 }
4233
4234 static int
4235 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4236 {
4237         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4238         uint32_t fctrl;
4239
4240         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4241         fctrl |= IXGBE_FCTRL_MPE;
4242         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4243
4244         return 0;
4245 }
4246
4247 static int
4248 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4249 {
4250         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4251         uint32_t fctrl;
4252
4253         if (dev->data->promiscuous == 1)
4254                 return 0; /* must remain in all_multicast mode */
4255
4256         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4257         fctrl &= (~IXGBE_FCTRL_MPE);
4258         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4259
4260         return 0;
4261 }
4262
4263 /**
4264  * It clears the interrupt causes and enables the interrupt.
4265  * It will be called once only during nic initialized.
4266  *
4267  * @param dev
4268  *  Pointer to struct rte_eth_dev.
4269  * @param on
4270  *  Enable or Disable.
4271  *
4272  * @return
4273  *  - On success, zero.
4274  *  - On failure, a negative value.
4275  */
4276 static int
4277 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4278 {
4279         struct ixgbe_interrupt *intr =
4280                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4281
4282         ixgbe_dev_link_status_print(dev);
4283         if (on)
4284                 intr->mask |= IXGBE_EICR_LSC;
4285         else
4286                 intr->mask &= ~IXGBE_EICR_LSC;
4287
4288         return 0;
4289 }
4290
4291 /**
4292  * It clears the interrupt causes and enables the interrupt.
4293  * It will be called once only during nic initialized.
4294  *
4295  * @param dev
4296  *  Pointer to struct rte_eth_dev.
4297  *
4298  * @return
4299  *  - On success, zero.
4300  *  - On failure, a negative value.
4301  */
4302 static int
4303 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4304 {
4305         struct ixgbe_interrupt *intr =
4306                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4307
4308         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4309
4310         return 0;
4311 }
4312
4313 /**
4314  * It clears the interrupt causes and enables the interrupt.
4315  * It will be called once only during nic initialized.
4316  *
4317  * @param dev
4318  *  Pointer to struct rte_eth_dev.
4319  *
4320  * @return
4321  *  - On success, zero.
4322  *  - On failure, a negative value.
4323  */
4324 static int
4325 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4326 {
4327         struct ixgbe_interrupt *intr =
4328                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4329
4330         intr->mask |= IXGBE_EICR_LINKSEC;
4331
4332         return 0;
4333 }
4334
4335 /*
4336  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4337  *
4338  * @param dev
4339  *  Pointer to struct rte_eth_dev.
4340  *
4341  * @return
4342  *  - On success, zero.
4343  *  - On failure, a negative value.
4344  */
4345 static int
4346 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4347 {
4348         uint32_t eicr;
4349         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4350         struct ixgbe_interrupt *intr =
4351                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4352
4353         /* clear all cause mask */
4354         ixgbe_disable_intr(hw);
4355
4356         /* read-on-clear nic registers here */
4357         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4358         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4359
4360         intr->flags = 0;
4361
4362         /* set flag for async link update */
4363         if (eicr & IXGBE_EICR_LSC)
4364                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4365
4366         if (eicr & IXGBE_EICR_MAILBOX)
4367                 intr->flags |= IXGBE_FLAG_MAILBOX;
4368
4369         if (eicr & IXGBE_EICR_LINKSEC)
4370                 intr->flags |= IXGBE_FLAG_MACSEC;
4371
4372         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4373             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4374             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4375                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4376
4377         return 0;
4378 }
4379
4380 /**
4381  * It gets and then prints the link status.
4382  *
4383  * @param dev
4384  *  Pointer to struct rte_eth_dev.
4385  *
4386  * @return
4387  *  - On success, zero.
4388  *  - On failure, a negative value.
4389  */
4390 static void
4391 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4392 {
4393         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4394         struct rte_eth_link link;
4395
4396         rte_eth_linkstatus_get(dev, &link);
4397
4398         if (link.link_status) {
4399                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4400                                         (int)(dev->data->port_id),
4401                                         (unsigned)link.link_speed,
4402                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4403                                         "full-duplex" : "half-duplex");
4404         } else {
4405                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4406                                 (int)(dev->data->port_id));
4407         }
4408         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4409                                 pci_dev->addr.domain,
4410                                 pci_dev->addr.bus,
4411                                 pci_dev->addr.devid,
4412                                 pci_dev->addr.function);
4413 }
4414
4415 /*
4416  * It executes link_update after knowing an interrupt occurred.
4417  *
4418  * @param dev
4419  *  Pointer to struct rte_eth_dev.
4420  *
4421  * @return
4422  *  - On success, zero.
4423  *  - On failure, a negative value.
4424  */
4425 static int
4426 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4427 {
4428         struct ixgbe_interrupt *intr =
4429                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4430         int64_t timeout;
4431         struct ixgbe_hw *hw =
4432                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4433
4434         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4435
4436         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4437                 ixgbe_pf_mbx_process(dev);
4438                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4439         }
4440
4441         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4442                 ixgbe_handle_lasi(hw);
4443                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4444         }
4445
4446         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4447                 struct rte_eth_link link;
4448
4449                 /* get the link status before link update, for predicting later */
4450                 rte_eth_linkstatus_get(dev, &link);
4451
4452                 ixgbe_dev_link_update(dev, 0);
4453
4454                 /* likely to up */
4455                 if (!link.link_status)
4456                         /* handle it 1 sec later, wait it being stable */
4457                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4458                 /* likely to down */
4459                 else
4460                         /* handle it 4 sec later, wait it being stable */
4461                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4462
4463                 ixgbe_dev_link_status_print(dev);
4464                 if (rte_eal_alarm_set(timeout * 1000,
4465                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4466                         PMD_DRV_LOG(ERR, "Error setting alarm");
4467                 else {
4468                         /* remember original mask */
4469                         intr->mask_original = intr->mask;
4470                         /* only disable lsc interrupt */
4471                         intr->mask &= ~IXGBE_EIMS_LSC;
4472                 }
4473         }
4474
4475         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4476         ixgbe_enable_intr(dev);
4477
4478         return 0;
4479 }
4480
4481 /**
4482  * Interrupt handler which shall be registered for alarm callback for delayed
4483  * handling specific interrupt to wait for the stable nic state. As the
4484  * NIC interrupt state is not stable for ixgbe after link is just down,
4485  * it needs to wait 4 seconds to get the stable status.
4486  *
4487  * @param handle
4488  *  Pointer to interrupt handle.
4489  * @param param
4490  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4491  *
4492  * @return
4493  *  void
4494  */
4495 static void
4496 ixgbe_dev_interrupt_delayed_handler(void *param)
4497 {
4498         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4499         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4500         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4501         struct ixgbe_interrupt *intr =
4502                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4503         struct ixgbe_hw *hw =
4504                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4505         uint32_t eicr;
4506
4507         ixgbe_disable_intr(hw);
4508
4509         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4510         if (eicr & IXGBE_EICR_MAILBOX)
4511                 ixgbe_pf_mbx_process(dev);
4512
4513         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4514                 ixgbe_handle_lasi(hw);
4515                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4516         }
4517
4518         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4519                 ixgbe_dev_link_update(dev, 0);
4520                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4521                 ixgbe_dev_link_status_print(dev);
4522                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4523                                               NULL);
4524         }
4525
4526         if (intr->flags & IXGBE_FLAG_MACSEC) {
4527                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4528                                               NULL);
4529                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4530         }
4531
4532         /* restore original mask */
4533         intr->mask = intr->mask_original;
4534         intr->mask_original = 0;
4535
4536         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4537         ixgbe_enable_intr(dev);
4538         rte_intr_ack(intr_handle);
4539 }
4540
4541 /**
4542  * Interrupt handler triggered by NIC  for handling
4543  * specific interrupt.
4544  *
4545  * @param handle
4546  *  Pointer to interrupt handle.
4547  * @param param
4548  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4549  *
4550  * @return
4551  *  void
4552  */
4553 static void
4554 ixgbe_dev_interrupt_handler(void *param)
4555 {
4556         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4557
4558         ixgbe_dev_interrupt_get_status(dev);
4559         ixgbe_dev_interrupt_action(dev);
4560 }
4561
4562 static int
4563 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4564 {
4565         struct ixgbe_hw *hw;
4566
4567         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4568         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4569 }
4570
4571 static int
4572 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4573 {
4574         struct ixgbe_hw *hw;
4575
4576         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4577         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4578 }
4579
4580 static int
4581 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4582 {
4583         struct ixgbe_hw *hw;
4584         uint32_t mflcn_reg;
4585         uint32_t fccfg_reg;
4586         int rx_pause;
4587         int tx_pause;
4588
4589         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4590
4591         fc_conf->pause_time = hw->fc.pause_time;
4592         fc_conf->high_water = hw->fc.high_water[0];
4593         fc_conf->low_water = hw->fc.low_water[0];
4594         fc_conf->send_xon = hw->fc.send_xon;
4595         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4596
4597         /*
4598          * Return rx_pause status according to actual setting of
4599          * MFLCN register.
4600          */
4601         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4602         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4603                 rx_pause = 1;
4604         else
4605                 rx_pause = 0;
4606
4607         /*
4608          * Return tx_pause status according to actual setting of
4609          * FCCFG register.
4610          */
4611         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4612         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4613                 tx_pause = 1;
4614         else
4615                 tx_pause = 0;
4616
4617         if (rx_pause && tx_pause)
4618                 fc_conf->mode = RTE_FC_FULL;
4619         else if (rx_pause)
4620                 fc_conf->mode = RTE_FC_RX_PAUSE;
4621         else if (tx_pause)
4622                 fc_conf->mode = RTE_FC_TX_PAUSE;
4623         else
4624                 fc_conf->mode = RTE_FC_NONE;
4625
4626         return 0;
4627 }
4628
4629 static int
4630 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4631 {
4632         struct ixgbe_hw *hw;
4633         int err;
4634         uint32_t rx_buf_size;
4635         uint32_t max_high_water;
4636         uint32_t mflcn;
4637         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4638                 ixgbe_fc_none,
4639                 ixgbe_fc_rx_pause,
4640                 ixgbe_fc_tx_pause,
4641                 ixgbe_fc_full
4642         };
4643
4644         PMD_INIT_FUNC_TRACE();
4645
4646         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4647         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4648         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4649
4650         /*
4651          * At least reserve one Ethernet frame for watermark
4652          * high_water/low_water in kilo bytes for ixgbe
4653          */
4654         max_high_water = (rx_buf_size -
4655                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4656         if ((fc_conf->high_water > max_high_water) ||
4657                 (fc_conf->high_water < fc_conf->low_water)) {
4658                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4659                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4660                 return -EINVAL;
4661         }
4662
4663         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4664         hw->fc.pause_time     = fc_conf->pause_time;
4665         hw->fc.high_water[0]  = fc_conf->high_water;
4666         hw->fc.low_water[0]   = fc_conf->low_water;
4667         hw->fc.send_xon       = fc_conf->send_xon;
4668         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4669
4670         err = ixgbe_fc_enable(hw);
4671
4672         /* Not negotiated is not an error case */
4673         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4674
4675                 /* check if we want to forward MAC frames - driver doesn't have native
4676                  * capability to do that, so we'll write the registers ourselves */
4677
4678                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4679
4680                 /* set or clear MFLCN.PMCF bit depending on configuration */
4681                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4682                         mflcn |= IXGBE_MFLCN_PMCF;
4683                 else
4684                         mflcn &= ~IXGBE_MFLCN_PMCF;
4685
4686                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4687                 IXGBE_WRITE_FLUSH(hw);
4688
4689                 return 0;
4690         }
4691
4692         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4693         return -EIO;
4694 }
4695
4696 /**
4697  *  ixgbe_pfc_enable_generic - Enable flow control
4698  *  @hw: pointer to hardware structure
4699  *  @tc_num: traffic class number
4700  *  Enable flow control according to the current settings.
4701  */
4702 static int
4703 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4704 {
4705         int ret_val = 0;
4706         uint32_t mflcn_reg, fccfg_reg;
4707         uint32_t reg;
4708         uint32_t fcrtl, fcrth;
4709         uint8_t i;
4710         uint8_t nb_rx_en;
4711
4712         /* Validate the water mark configuration */
4713         if (!hw->fc.pause_time) {
4714                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4715                 goto out;
4716         }
4717
4718         /* Low water mark of zero causes XOFF floods */
4719         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4720                  /* High/Low water can not be 0 */
4721                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4722                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4723                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4724                         goto out;
4725                 }
4726
4727                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4728                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4729                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4730                         goto out;
4731                 }
4732         }
4733         /* Negotiate the fc mode to use */
4734         ixgbe_fc_autoneg(hw);
4735
4736         /* Disable any previous flow control settings */
4737         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4738         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4739
4740         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4741         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4742
4743         switch (hw->fc.current_mode) {
4744         case ixgbe_fc_none:
4745                 /*
4746                  * If the count of enabled RX Priority Flow control >1,
4747                  * and the TX pause can not be disabled
4748                  */
4749                 nb_rx_en = 0;
4750                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4751                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4752                         if (reg & IXGBE_FCRTH_FCEN)
4753                                 nb_rx_en++;
4754                 }
4755                 if (nb_rx_en > 1)
4756                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4757                 break;
4758         case ixgbe_fc_rx_pause:
4759                 /*
4760                  * Rx Flow control is enabled and Tx Flow control is
4761                  * disabled by software override. Since there really
4762                  * isn't a way to advertise that we are capable of RX
4763                  * Pause ONLY, we will advertise that we support both
4764                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4765                  * disable the adapter's ability to send PAUSE frames.
4766                  */
4767                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4768                 /*
4769                  * If the count of enabled RX Priority Flow control >1,
4770                  * and the TX pause can not be disabled
4771                  */
4772                 nb_rx_en = 0;
4773                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4774                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4775                         if (reg & IXGBE_FCRTH_FCEN)
4776                                 nb_rx_en++;
4777                 }
4778                 if (nb_rx_en > 1)
4779                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4780                 break;
4781         case ixgbe_fc_tx_pause:
4782                 /*
4783                  * Tx Flow control is enabled, and Rx Flow control is
4784                  * disabled by software override.
4785                  */
4786                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4787                 break;
4788         case ixgbe_fc_full:
4789                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4790                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4791                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4792                 break;
4793         default:
4794                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4795                 ret_val = IXGBE_ERR_CONFIG;
4796                 goto out;
4797         }
4798
4799         /* Set 802.3x based flow control settings. */
4800         mflcn_reg |= IXGBE_MFLCN_DPF;
4801         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4802         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4803
4804         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4805         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4806                 hw->fc.high_water[tc_num]) {
4807                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4808                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4809                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4810         } else {
4811                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4812                 /*
4813                  * In order to prevent Tx hangs when the internal Tx
4814                  * switch is enabled we must set the high water mark
4815                  * to the maximum FCRTH value.  This allows the Tx
4816                  * switch to function even under heavy Rx workloads.
4817                  */
4818                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4819         }
4820         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4821
4822         /* Configure pause time (2 TCs per register) */
4823         reg = hw->fc.pause_time * 0x00010001;
4824         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4825                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4826
4827         /* Configure flow control refresh threshold value */
4828         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4829
4830 out:
4831         return ret_val;
4832 }
4833
4834 static int
4835 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4836 {
4837         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4838         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4839
4840         if (hw->mac.type != ixgbe_mac_82598EB) {
4841                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4842         }
4843         return ret_val;
4844 }
4845
4846 static int
4847 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4848 {
4849         int err;
4850         uint32_t rx_buf_size;
4851         uint32_t max_high_water;
4852         uint8_t tc_num;
4853         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4854         struct ixgbe_hw *hw =
4855                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4856         struct ixgbe_dcb_config *dcb_config =
4857                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4858
4859         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4860                 ixgbe_fc_none,
4861                 ixgbe_fc_rx_pause,
4862                 ixgbe_fc_tx_pause,
4863                 ixgbe_fc_full
4864         };
4865
4866         PMD_INIT_FUNC_TRACE();
4867
4868         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4869         tc_num = map[pfc_conf->priority];
4870         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4871         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4872         /*
4873          * At least reserve one Ethernet frame for watermark
4874          * high_water/low_water in kilo bytes for ixgbe
4875          */
4876         max_high_water = (rx_buf_size -
4877                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4878         if ((pfc_conf->fc.high_water > max_high_water) ||
4879             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4880                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4881                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4882                 return -EINVAL;
4883         }
4884
4885         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4886         hw->fc.pause_time = pfc_conf->fc.pause_time;
4887         hw->fc.send_xon = pfc_conf->fc.send_xon;
4888         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4889         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4890
4891         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4892
4893         /* Not negotiated is not an error case */
4894         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4895                 return 0;
4896
4897         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4898         return -EIO;
4899 }
4900
4901 static int
4902 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4903                           struct rte_eth_rss_reta_entry64 *reta_conf,
4904                           uint16_t reta_size)
4905 {
4906         uint16_t i, sp_reta_size;
4907         uint8_t j, mask;
4908         uint32_t reta, r;
4909         uint16_t idx, shift;
4910         struct ixgbe_adapter *adapter = dev->data->dev_private;
4911         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4912         uint32_t reta_reg;
4913
4914         PMD_INIT_FUNC_TRACE();
4915
4916         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4917                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4918                         "NIC.");
4919                 return -ENOTSUP;
4920         }
4921
4922         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4923         if (reta_size != sp_reta_size) {
4924                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4925                         "(%d) doesn't match the number hardware can supported "
4926                         "(%d)", reta_size, sp_reta_size);
4927                 return -EINVAL;
4928         }
4929
4930         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4931                 idx = i / RTE_RETA_GROUP_SIZE;
4932                 shift = i % RTE_RETA_GROUP_SIZE;
4933                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4934                                                 IXGBE_4_BIT_MASK);
4935                 if (!mask)
4936                         continue;
4937                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4938                 if (mask == IXGBE_4_BIT_MASK)
4939                         r = 0;
4940                 else
4941                         r = IXGBE_READ_REG(hw, reta_reg);
4942                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4943                         if (mask & (0x1 << j))
4944                                 reta |= reta_conf[idx].reta[shift + j] <<
4945                                                         (CHAR_BIT * j);
4946                         else
4947                                 reta |= r & (IXGBE_8_BIT_MASK <<
4948                                                 (CHAR_BIT * j));
4949                 }
4950                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4951         }
4952         adapter->rss_reta_updated = 1;
4953
4954         return 0;
4955 }
4956
4957 static int
4958 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4959                          struct rte_eth_rss_reta_entry64 *reta_conf,
4960                          uint16_t reta_size)
4961 {
4962         uint16_t i, sp_reta_size;
4963         uint8_t j, mask;
4964         uint32_t reta;
4965         uint16_t idx, shift;
4966         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4967         uint32_t reta_reg;
4968
4969         PMD_INIT_FUNC_TRACE();
4970         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4971         if (reta_size != sp_reta_size) {
4972                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4973                         "(%d) doesn't match the number hardware can supported "
4974                         "(%d)", reta_size, sp_reta_size);
4975                 return -EINVAL;
4976         }
4977
4978         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4979                 idx = i / RTE_RETA_GROUP_SIZE;
4980                 shift = i % RTE_RETA_GROUP_SIZE;
4981                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4982                                                 IXGBE_4_BIT_MASK);
4983                 if (!mask)
4984                         continue;
4985
4986                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4987                 reta = IXGBE_READ_REG(hw, reta_reg);
4988                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4989                         if (mask & (0x1 << j))
4990                                 reta_conf[idx].reta[shift + j] =
4991                                         ((reta >> (CHAR_BIT * j)) &
4992                                                 IXGBE_8_BIT_MASK);
4993                 }
4994         }
4995
4996         return 0;
4997 }
4998
4999 static int
5000 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5001                                 uint32_t index, uint32_t pool)
5002 {
5003         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5004         uint32_t enable_addr = 1;
5005
5006         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5007                              pool, enable_addr);
5008 }
5009
5010 static void
5011 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5012 {
5013         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5014
5015         ixgbe_clear_rar(hw, index);
5016 }
5017
5018 static int
5019 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5020 {
5021         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5022
5023         ixgbe_remove_rar(dev, 0);
5024         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5025
5026         return 0;
5027 }
5028
5029 static bool
5030 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5031 {
5032         if (strcmp(dev->device->driver->name, drv->driver.name))
5033                 return false;
5034
5035         return true;
5036 }
5037
5038 bool
5039 is_ixgbe_supported(struct rte_eth_dev *dev)
5040 {
5041         return is_device_supported(dev, &rte_ixgbe_pmd);
5042 }
5043
5044 static int
5045 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5046 {
5047         uint32_t hlreg0;
5048         uint32_t maxfrs;
5049         struct ixgbe_hw *hw;
5050         struct rte_eth_dev_info dev_info;
5051         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5052         struct rte_eth_dev_data *dev_data = dev->data;
5053         int ret;
5054
5055         ret = ixgbe_dev_info_get(dev, &dev_info);
5056         if (ret != 0)
5057                 return ret;
5058
5059         /* check that mtu is within the allowed range */
5060         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5061                 return -EINVAL;
5062
5063         /* If device is started, refuse mtu that requires the support of
5064          * scattered packets when this feature has not been enabled before.
5065          */
5066         if (dev_data->dev_started && !dev_data->scattered_rx &&
5067             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5068              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5069                 PMD_INIT_LOG(ERR, "Stop port first.");
5070                 return -EINVAL;
5071         }
5072
5073         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5074         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5075
5076         /* switch to jumbo mode if needed */
5077         if (frame_size > RTE_ETHER_MAX_LEN) {
5078                 dev->data->dev_conf.rxmode.offloads |=
5079                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5080                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5081         } else {
5082                 dev->data->dev_conf.rxmode.offloads &=
5083                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5084                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5085         }
5086         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5087
5088         /* update max frame size */
5089         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5090
5091         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5092         maxfrs &= 0x0000FFFF;
5093         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5094         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5095
5096         return 0;
5097 }
5098
5099 /*
5100  * Virtual Function operations
5101  */
5102 static void
5103 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5104 {
5105         struct ixgbe_interrupt *intr =
5106                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5107         struct ixgbe_hw *hw =
5108                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5109
5110         PMD_INIT_FUNC_TRACE();
5111
5112         /* Clear interrupt mask to stop from interrupts being generated */
5113         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5114
5115         IXGBE_WRITE_FLUSH(hw);
5116
5117         /* Clear mask value. */
5118         intr->mask = 0;
5119 }
5120
5121 static void
5122 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5123 {
5124         struct ixgbe_interrupt *intr =
5125                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5126         struct ixgbe_hw *hw =
5127                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5128
5129         PMD_INIT_FUNC_TRACE();
5130
5131         /* VF enable interrupt autoclean */
5132         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5133         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5134         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5135
5136         IXGBE_WRITE_FLUSH(hw);
5137
5138         /* Save IXGBE_VTEIMS value to mask. */
5139         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5140 }
5141
5142 static int
5143 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5144 {
5145         struct rte_eth_conf *conf = &dev->data->dev_conf;
5146         struct ixgbe_adapter *adapter = dev->data->dev_private;
5147
5148         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5149                      dev->data->port_id);
5150
5151         /*
5152          * VF has no ability to enable/disable HW CRC
5153          * Keep the persistent behavior the same as Host PF
5154          */
5155 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5156         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5157                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5158                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5159         }
5160 #else
5161         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5162                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5163                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5164         }
5165 #endif
5166
5167         /*
5168          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5169          * allocation or vector Rx preconditions we will reset it.
5170          */
5171         adapter->rx_bulk_alloc_allowed = true;
5172         adapter->rx_vec_allowed = true;
5173
5174         return 0;
5175 }
5176
5177 static int
5178 ixgbevf_dev_start(struct rte_eth_dev *dev)
5179 {
5180         struct ixgbe_hw *hw =
5181                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5182         uint32_t intr_vector = 0;
5183         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5184         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5185
5186         int err, mask = 0;
5187
5188         PMD_INIT_FUNC_TRACE();
5189
5190         /* Stop the link setup handler before resetting the HW. */
5191         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5192
5193         err = hw->mac.ops.reset_hw(hw);
5194         if (err) {
5195                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5196                 return err;
5197         }
5198         hw->mac.get_link_status = true;
5199
5200         /* negotiate mailbox API version to use with the PF. */
5201         ixgbevf_negotiate_api(hw);
5202
5203         ixgbevf_dev_tx_init(dev);
5204
5205         /* This can fail when allocating mbufs for descriptor rings */
5206         err = ixgbevf_dev_rx_init(dev);
5207         if (err) {
5208                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5209                 ixgbe_dev_clear_queues(dev);
5210                 return err;
5211         }
5212
5213         /* Set vfta */
5214         ixgbevf_set_vfta_all(dev, 1);
5215
5216         /* Set HW strip */
5217         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5218                 ETH_VLAN_EXTEND_MASK;
5219         err = ixgbevf_vlan_offload_config(dev, mask);
5220         if (err) {
5221                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5222                 ixgbe_dev_clear_queues(dev);
5223                 return err;
5224         }
5225
5226         ixgbevf_dev_rxtx_start(dev);
5227
5228         /* check and configure queue intr-vector mapping */
5229         if (rte_intr_cap_multiple(intr_handle) &&
5230             dev->data->dev_conf.intr_conf.rxq) {
5231                 /* According to datasheet, only vector 0/1/2 can be used,
5232                  * now only one vector is used for Rx queue
5233                  */
5234                 intr_vector = 1;
5235                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5236                         return -1;
5237         }
5238
5239         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5240                 intr_handle->intr_vec =
5241                         rte_zmalloc("intr_vec",
5242                                     dev->data->nb_rx_queues * sizeof(int), 0);
5243                 if (intr_handle->intr_vec == NULL) {
5244                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5245                                      " intr_vec", dev->data->nb_rx_queues);
5246                         return -ENOMEM;
5247                 }
5248         }
5249         ixgbevf_configure_msix(dev);
5250
5251         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5252          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5253          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5254          * is not cleared, it will fail when following rte_intr_enable( ) tries
5255          * to map Rx queue interrupt to other VFIO vectors.
5256          * So clear uio/vfio intr/evevnfd first to avoid failure.
5257          */
5258         rte_intr_disable(intr_handle);
5259
5260         rte_intr_enable(intr_handle);
5261
5262         /* Re-enable interrupt for VF */
5263         ixgbevf_intr_enable(dev);
5264
5265         /*
5266          * Update link status right before return, because it may
5267          * start link configuration process in a separate thread.
5268          */
5269         ixgbevf_dev_link_update(dev, 0);
5270
5271         hw->adapter_stopped = false;
5272
5273         return 0;
5274 }
5275
5276 static void
5277 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5278 {
5279         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5280         struct ixgbe_adapter *adapter = dev->data->dev_private;
5281         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5282         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5283
5284         if (hw->adapter_stopped)
5285                 return;
5286
5287         PMD_INIT_FUNC_TRACE();
5288
5289         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5290
5291         ixgbevf_intr_disable(dev);
5292
5293         hw->adapter_stopped = 1;
5294         ixgbe_stop_adapter(hw);
5295
5296         /*
5297           * Clear what we set, but we still keep shadow_vfta to
5298           * restore after device starts
5299           */
5300         ixgbevf_set_vfta_all(dev, 0);
5301
5302         /* Clear stored conf */
5303         dev->data->scattered_rx = 0;
5304
5305         ixgbe_dev_clear_queues(dev);
5306
5307         /* Clean datapath event and queue/vec mapping */
5308         rte_intr_efd_disable(intr_handle);
5309         if (intr_handle->intr_vec != NULL) {
5310                 rte_free(intr_handle->intr_vec);
5311                 intr_handle->intr_vec = NULL;
5312         }
5313
5314         adapter->rss_reta_updated = 0;
5315 }
5316
5317 static void
5318 ixgbevf_dev_close(struct rte_eth_dev *dev)
5319 {
5320         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5321         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5322         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5323
5324         PMD_INIT_FUNC_TRACE();
5325
5326         ixgbe_reset_hw(hw);
5327
5328         ixgbevf_dev_stop(dev);
5329
5330         ixgbe_dev_free_queues(dev);
5331
5332         /**
5333          * Remove the VF MAC address ro ensure
5334          * that the VF traffic goes to the PF
5335          * after stop, close and detach of the VF
5336          **/
5337         ixgbevf_remove_mac_addr(dev, 0);
5338
5339         dev->dev_ops = NULL;
5340         dev->rx_pkt_burst = NULL;
5341         dev->tx_pkt_burst = NULL;
5342
5343         rte_intr_disable(intr_handle);
5344         rte_intr_callback_unregister(intr_handle,
5345                                      ixgbevf_dev_interrupt_handler, dev);
5346 }
5347
5348 /*
5349  * Reset VF device
5350  */
5351 static int
5352 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5353 {
5354         int ret;
5355
5356         ret = eth_ixgbevf_dev_uninit(dev);
5357         if (ret)
5358                 return ret;
5359
5360         ret = eth_ixgbevf_dev_init(dev);
5361
5362         return ret;
5363 }
5364
5365 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5366 {
5367         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5368         struct ixgbe_vfta *shadow_vfta =
5369                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5370         int i = 0, j = 0, vfta = 0, mask = 1;
5371
5372         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5373                 vfta = shadow_vfta->vfta[i];
5374                 if (vfta) {
5375                         mask = 1;
5376                         for (j = 0; j < 32; j++) {
5377                                 if (vfta & mask)
5378                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5379                                                        on, false);
5380                                 mask <<= 1;
5381                         }
5382                 }
5383         }
5384
5385 }
5386
5387 static int
5388 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5389 {
5390         struct ixgbe_hw *hw =
5391                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5392         struct ixgbe_vfta *shadow_vfta =
5393                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5394         uint32_t vid_idx = 0;
5395         uint32_t vid_bit = 0;
5396         int ret = 0;
5397
5398         PMD_INIT_FUNC_TRACE();
5399
5400         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5401         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5402         if (ret) {
5403                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5404                 return ret;
5405         }
5406         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5407         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5408
5409         /* Save what we set and retore it after device reset */
5410         if (on)
5411                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5412         else
5413                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5414
5415         return 0;
5416 }
5417
5418 static void
5419 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5420 {
5421         struct ixgbe_hw *hw =
5422                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5423         uint32_t ctrl;
5424
5425         PMD_INIT_FUNC_TRACE();
5426
5427         if (queue >= hw->mac.max_rx_queues)
5428                 return;
5429
5430         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5431         if (on)
5432                 ctrl |= IXGBE_RXDCTL_VME;
5433         else
5434                 ctrl &= ~IXGBE_RXDCTL_VME;
5435         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5436
5437         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5438 }
5439
5440 static int
5441 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5442 {
5443         struct ixgbe_rx_queue *rxq;
5444         uint16_t i;
5445         int on = 0;
5446
5447         /* VF function only support hw strip feature, others are not support */
5448         if (mask & ETH_VLAN_STRIP_MASK) {
5449                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5450                         rxq = dev->data->rx_queues[i];
5451                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5452                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5453                 }
5454         }
5455
5456         return 0;
5457 }
5458
5459 static int
5460 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5461 {
5462         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5463
5464         ixgbevf_vlan_offload_config(dev, mask);
5465
5466         return 0;
5467 }
5468
5469 int
5470 ixgbe_vt_check(struct ixgbe_hw *hw)
5471 {
5472         uint32_t reg_val;
5473
5474         /* if Virtualization Technology is enabled */
5475         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5476         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5477                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5478                 return -1;
5479         }
5480
5481         return 0;
5482 }
5483
5484 static uint32_t
5485 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5486 {
5487         uint32_t vector = 0;
5488
5489         switch (hw->mac.mc_filter_type) {
5490         case 0:   /* use bits [47:36] of the address */
5491                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5492                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5493                 break;
5494         case 1:   /* use bits [46:35] of the address */
5495                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5496                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5497                 break;
5498         case 2:   /* use bits [45:34] of the address */
5499                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5500                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5501                 break;
5502         case 3:   /* use bits [43:32] of the address */
5503                 vector = ((uc_addr->addr_bytes[4]) |
5504                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5505                 break;
5506         default:  /* Invalid mc_filter_type */
5507                 break;
5508         }
5509
5510         /* vector can only be 12-bits or boundary will be exceeded */
5511         vector &= 0xFFF;
5512         return vector;
5513 }
5514
5515 static int
5516 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5517                         struct rte_ether_addr *mac_addr, uint8_t on)
5518 {
5519         uint32_t vector;
5520         uint32_t uta_idx;
5521         uint32_t reg_val;
5522         uint32_t uta_shift;
5523         uint32_t rc;
5524         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5525         const uint32_t ixgbe_uta_bit_shift = 5;
5526         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5527         const uint32_t bit1 = 0x1;
5528
5529         struct ixgbe_hw *hw =
5530                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5531         struct ixgbe_uta_info *uta_info =
5532                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5533
5534         /* The UTA table only exists on 82599 hardware and newer */
5535         if (hw->mac.type < ixgbe_mac_82599EB)
5536                 return -ENOTSUP;
5537
5538         vector = ixgbe_uta_vector(hw, mac_addr);
5539         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5540         uta_shift = vector & ixgbe_uta_bit_mask;
5541
5542         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5543         if (rc == on)
5544                 return 0;
5545
5546         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5547         if (on) {
5548                 uta_info->uta_in_use++;
5549                 reg_val |= (bit1 << uta_shift);
5550                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5551         } else {
5552                 uta_info->uta_in_use--;
5553                 reg_val &= ~(bit1 << uta_shift);
5554                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5555         }
5556
5557         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5558
5559         if (uta_info->uta_in_use > 0)
5560                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5561                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5562         else
5563                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5564
5565         return 0;
5566 }
5567
5568 static int
5569 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5570 {
5571         int i;
5572         struct ixgbe_hw *hw =
5573                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5574         struct ixgbe_uta_info *uta_info =
5575                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5576
5577         /* The UTA table only exists on 82599 hardware and newer */
5578         if (hw->mac.type < ixgbe_mac_82599EB)
5579                 return -ENOTSUP;
5580
5581         if (on) {
5582                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5583                         uta_info->uta_shadow[i] = ~0;
5584                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5585                 }
5586         } else {
5587                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5588                         uta_info->uta_shadow[i] = 0;
5589                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5590                 }
5591         }
5592         return 0;
5593
5594 }
5595
5596 uint32_t
5597 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5598 {
5599         uint32_t new_val = orig_val;
5600
5601         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5602                 new_val |= IXGBE_VMOLR_AUPE;
5603         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5604                 new_val |= IXGBE_VMOLR_ROMPE;
5605         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5606                 new_val |= IXGBE_VMOLR_ROPE;
5607         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5608                 new_val |= IXGBE_VMOLR_BAM;
5609         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5610                 new_val |= IXGBE_VMOLR_MPE;
5611
5612         return new_val;
5613 }
5614
5615 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5616 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5617 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5618 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5619 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5620         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5621         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5622
5623 static int
5624 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5625                       struct rte_eth_mirror_conf *mirror_conf,
5626                       uint8_t rule_id, uint8_t on)
5627 {
5628         uint32_t mr_ctl, vlvf;
5629         uint32_t mp_lsb = 0;
5630         uint32_t mv_msb = 0;
5631         uint32_t mv_lsb = 0;
5632         uint32_t mp_msb = 0;
5633         uint8_t i = 0;
5634         int reg_index = 0;
5635         uint64_t vlan_mask = 0;
5636
5637         const uint8_t pool_mask_offset = 32;
5638         const uint8_t vlan_mask_offset = 32;
5639         const uint8_t dst_pool_offset = 8;
5640         const uint8_t rule_mr_offset  = 4;
5641         const uint8_t mirror_rule_mask = 0x0F;
5642
5643         struct ixgbe_mirror_info *mr_info =
5644                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5645         struct ixgbe_hw *hw =
5646                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5647         uint8_t mirror_type = 0;
5648
5649         if (ixgbe_vt_check(hw) < 0)
5650                 return -ENOTSUP;
5651
5652         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5653                 return -EINVAL;
5654
5655         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5656                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5657                             mirror_conf->rule_type);
5658                 return -EINVAL;
5659         }
5660
5661         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5662                 mirror_type |= IXGBE_MRCTL_VLME;
5663                 /* Check if vlan id is valid and find conresponding VLAN ID
5664                  * index in VLVF
5665                  */
5666                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5667                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5668                                 /* search vlan id related pool vlan filter
5669                                  * index
5670                                  */
5671                                 reg_index = ixgbe_find_vlvf_slot(
5672                                                 hw,
5673                                                 mirror_conf->vlan.vlan_id[i],
5674                                                 false);
5675                                 if (reg_index < 0)
5676                                         return -EINVAL;
5677                                 vlvf = IXGBE_READ_REG(hw,
5678                                                       IXGBE_VLVF(reg_index));
5679                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5680                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5681                                       mirror_conf->vlan.vlan_id[i]))
5682                                         vlan_mask |= (1ULL << reg_index);
5683                                 else
5684                                         return -EINVAL;
5685                         }
5686                 }
5687
5688                 if (on) {
5689                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5690                         mv_msb = vlan_mask >> vlan_mask_offset;
5691
5692                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5693                                                 mirror_conf->vlan.vlan_mask;
5694                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5695                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5696                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5697                                                 mirror_conf->vlan.vlan_id[i];
5698                         }
5699                 } else {
5700                         mv_lsb = 0;
5701                         mv_msb = 0;
5702                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5703                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5704                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5705                 }
5706         }
5707
5708         /**
5709          * if enable pool mirror, write related pool mask register,if disable
5710          * pool mirror, clear PFMRVM register
5711          */
5712         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5713                 mirror_type |= IXGBE_MRCTL_VPME;
5714                 if (on) {
5715                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5716                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5717                         mr_info->mr_conf[rule_id].pool_mask =
5718                                         mirror_conf->pool_mask;
5719
5720                 } else {
5721                         mp_lsb = 0;
5722                         mp_msb = 0;
5723                         mr_info->mr_conf[rule_id].pool_mask = 0;
5724                 }
5725         }
5726         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5727                 mirror_type |= IXGBE_MRCTL_UPME;
5728         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5729                 mirror_type |= IXGBE_MRCTL_DPME;
5730
5731         /* read  mirror control register and recalculate it */
5732         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5733
5734         if (on) {
5735                 mr_ctl |= mirror_type;
5736                 mr_ctl &= mirror_rule_mask;
5737                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5738         } else {
5739                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5740         }
5741
5742         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5743         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5744
5745         /* write mirrror control  register */
5746         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5747
5748         /* write pool mirrror control  register */
5749         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5750                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5751                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5752                                 mp_msb);
5753         }
5754         /* write VLAN mirrror control  register */
5755         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5756                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5757                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5758                                 mv_msb);
5759         }
5760
5761         return 0;
5762 }
5763
5764 static int
5765 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5766 {
5767         int mr_ctl = 0;
5768         uint32_t lsb_val = 0;
5769         uint32_t msb_val = 0;
5770         const uint8_t rule_mr_offset = 4;
5771
5772         struct ixgbe_hw *hw =
5773                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5774         struct ixgbe_mirror_info *mr_info =
5775                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5776
5777         if (ixgbe_vt_check(hw) < 0)
5778                 return -ENOTSUP;
5779
5780         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5781                 return -EINVAL;
5782
5783         memset(&mr_info->mr_conf[rule_id], 0,
5784                sizeof(struct rte_eth_mirror_conf));
5785
5786         /* clear PFVMCTL register */
5787         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5788
5789         /* clear pool mask register */
5790         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5791         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5792
5793         /* clear vlan mask register */
5794         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5795         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5796
5797         return 0;
5798 }
5799
5800 static int
5801 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5802 {
5803         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5804         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5805         struct ixgbe_interrupt *intr =
5806                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5807         struct ixgbe_hw *hw =
5808                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5809         uint32_t vec = IXGBE_MISC_VEC_ID;
5810
5811         if (rte_intr_allow_others(intr_handle))
5812                 vec = IXGBE_RX_VEC_START;
5813         intr->mask |= (1 << vec);
5814         RTE_SET_USED(queue_id);
5815         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5816
5817         rte_intr_ack(intr_handle);
5818
5819         return 0;
5820 }
5821
5822 static int
5823 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5824 {
5825         struct ixgbe_interrupt *intr =
5826                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5827         struct ixgbe_hw *hw =
5828                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5829         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5830         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5831         uint32_t vec = IXGBE_MISC_VEC_ID;
5832
5833         if (rte_intr_allow_others(intr_handle))
5834                 vec = IXGBE_RX_VEC_START;
5835         intr->mask &= ~(1 << vec);
5836         RTE_SET_USED(queue_id);
5837         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5838
5839         return 0;
5840 }
5841
5842 static int
5843 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5844 {
5845         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5846         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5847         uint32_t mask;
5848         struct ixgbe_hw *hw =
5849                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5850         struct ixgbe_interrupt *intr =
5851                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5852
5853         if (queue_id < 16) {
5854                 ixgbe_disable_intr(hw);
5855                 intr->mask |= (1 << queue_id);
5856                 ixgbe_enable_intr(dev);
5857         } else if (queue_id < 32) {
5858                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5859                 mask &= (1 << queue_id);
5860                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5861         } else if (queue_id < 64) {
5862                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5863                 mask &= (1 << (queue_id - 32));
5864                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5865         }
5866         rte_intr_ack(intr_handle);
5867
5868         return 0;
5869 }
5870
5871 static int
5872 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5873 {
5874         uint32_t mask;
5875         struct ixgbe_hw *hw =
5876                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5877         struct ixgbe_interrupt *intr =
5878                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5879
5880         if (queue_id < 16) {
5881                 ixgbe_disable_intr(hw);
5882                 intr->mask &= ~(1 << queue_id);
5883                 ixgbe_enable_intr(dev);
5884         } else if (queue_id < 32) {
5885                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5886                 mask &= ~(1 << queue_id);
5887                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5888         } else if (queue_id < 64) {
5889                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5890                 mask &= ~(1 << (queue_id - 32));
5891                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5892         }
5893
5894         return 0;
5895 }
5896
5897 static void
5898 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5899                      uint8_t queue, uint8_t msix_vector)
5900 {
5901         uint32_t tmp, idx;
5902
5903         if (direction == -1) {
5904                 /* other causes */
5905                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5906                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5907                 tmp &= ~0xFF;
5908                 tmp |= msix_vector;
5909                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5910         } else {
5911                 /* rx or tx cause */
5912                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5913                 idx = ((16 * (queue & 1)) + (8 * direction));
5914                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5915                 tmp &= ~(0xFF << idx);
5916                 tmp |= (msix_vector << idx);
5917                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5918         }
5919 }
5920
5921 /**
5922  * set the IVAR registers, mapping interrupt causes to vectors
5923  * @param hw
5924  *  pointer to ixgbe_hw struct
5925  * @direction
5926  *  0 for Rx, 1 for Tx, -1 for other causes
5927  * @queue
5928  *  queue to map the corresponding interrupt to
5929  * @msix_vector
5930  *  the vector to map to the corresponding queue
5931  */
5932 static void
5933 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5934                    uint8_t queue, uint8_t msix_vector)
5935 {
5936         uint32_t tmp, idx;
5937
5938         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5939         if (hw->mac.type == ixgbe_mac_82598EB) {
5940                 if (direction == -1)
5941                         direction = 0;
5942                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5943                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5944                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5945                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5946                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5947         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5948                         (hw->mac.type == ixgbe_mac_X540) ||
5949                         (hw->mac.type == ixgbe_mac_X550) ||
5950                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
5951                 if (direction == -1) {
5952                         /* other causes */
5953                         idx = ((queue & 1) * 8);
5954                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5955                         tmp &= ~(0xFF << idx);
5956                         tmp |= (msix_vector << idx);
5957                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5958                 } else {
5959                         /* rx or tx causes */
5960                         idx = ((16 * (queue & 1)) + (8 * direction));
5961                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5962                         tmp &= ~(0xFF << idx);
5963                         tmp |= (msix_vector << idx);
5964                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5965                 }
5966         }
5967 }
5968
5969 static void
5970 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5971 {
5972         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5973         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5974         struct ixgbe_hw *hw =
5975                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5976         uint32_t q_idx;
5977         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5978         uint32_t base = IXGBE_MISC_VEC_ID;
5979
5980         /* Configure VF other cause ivar */
5981         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5982
5983         /* won't configure msix register if no mapping is done
5984          * between intr vector and event fd.
5985          */
5986         if (!rte_intr_dp_is_en(intr_handle))
5987                 return;
5988
5989         if (rte_intr_allow_others(intr_handle)) {
5990                 base = IXGBE_RX_VEC_START;
5991                 vector_idx = IXGBE_RX_VEC_START;
5992         }
5993
5994         /* Configure all RX queues of VF */
5995         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5996                 /* Force all queue use vector 0,
5997                  * as IXGBE_VF_MAXMSIVECOTR = 1
5998                  */
5999                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6000                 intr_handle->intr_vec[q_idx] = vector_idx;
6001                 if (vector_idx < base + intr_handle->nb_efd - 1)
6002                         vector_idx++;
6003         }
6004
6005         /* As RX queue setting above show, all queues use the vector 0.
6006          * Set only the ITR value of IXGBE_MISC_VEC_ID.
6007          */
6008         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6009                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6010                         | IXGBE_EITR_CNT_WDIS);
6011 }
6012
6013 /**
6014  * Sets up the hardware to properly generate MSI-X interrupts
6015  * @hw
6016  *  board private structure
6017  */
6018 static void
6019 ixgbe_configure_msix(struct rte_eth_dev *dev)
6020 {
6021         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6022         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6023         struct ixgbe_hw *hw =
6024                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6025         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6026         uint32_t vec = IXGBE_MISC_VEC_ID;
6027         uint32_t mask;
6028         uint32_t gpie;
6029
6030         /* won't configure msix register if no mapping is done
6031          * between intr vector and event fd
6032          * but if misx has been enabled already, need to configure
6033          * auto clean, auto mask and throttling.
6034          */
6035         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6036         if (!rte_intr_dp_is_en(intr_handle) &&
6037             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6038                 return;
6039
6040         if (rte_intr_allow_others(intr_handle))
6041                 vec = base = IXGBE_RX_VEC_START;
6042
6043         /* setup GPIE for MSI-x mode */
6044         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6045         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6046                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6047         /* auto clearing and auto setting corresponding bits in EIMS
6048          * when MSI-X interrupt is triggered
6049          */
6050         if (hw->mac.type == ixgbe_mac_82598EB) {
6051                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6052         } else {
6053                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6054                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6055         }
6056         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6057
6058         /* Populate the IVAR table and set the ITR values to the
6059          * corresponding register.
6060          */
6061         if (rte_intr_dp_is_en(intr_handle)) {
6062                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6063                         queue_id++) {
6064                         /* by default, 1:1 mapping */
6065                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6066                         intr_handle->intr_vec[queue_id] = vec;
6067                         if (vec < base + intr_handle->nb_efd - 1)
6068                                 vec++;
6069                 }
6070
6071                 switch (hw->mac.type) {
6072                 case ixgbe_mac_82598EB:
6073                         ixgbe_set_ivar_map(hw, -1,
6074                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6075                                            IXGBE_MISC_VEC_ID);
6076                         break;
6077                 case ixgbe_mac_82599EB:
6078                 case ixgbe_mac_X540:
6079                 case ixgbe_mac_X550:
6080                 case ixgbe_mac_X550EM_x:
6081                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6082                         break;
6083                 default:
6084                         break;
6085                 }
6086         }
6087         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6088                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6089                         | IXGBE_EITR_CNT_WDIS);
6090
6091         /* set up to autoclear timer, and the vectors */
6092         mask = IXGBE_EIMS_ENABLE_MASK;
6093         mask &= ~(IXGBE_EIMS_OTHER |
6094                   IXGBE_EIMS_MAILBOX |
6095                   IXGBE_EIMS_LSC);
6096
6097         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6098 }
6099
6100 int
6101 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6102                            uint16_t queue_idx, uint16_t tx_rate)
6103 {
6104         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6105         struct rte_eth_rxmode *rxmode;
6106         uint32_t rf_dec, rf_int;
6107         uint32_t bcnrc_val;
6108         uint16_t link_speed = dev->data->dev_link.link_speed;
6109
6110         if (queue_idx >= hw->mac.max_tx_queues)
6111                 return -EINVAL;
6112
6113         if (tx_rate != 0) {
6114                 /* Calculate the rate factor values to set */
6115                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6116                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6117                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6118
6119                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6120                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6121                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6122                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6123         } else {
6124                 bcnrc_val = 0;
6125         }
6126
6127         rxmode = &dev->data->dev_conf.rxmode;
6128         /*
6129          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6130          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6131          * set as 0x4.
6132          */
6133         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6134             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6135                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6136                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6137         else
6138                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6139                         IXGBE_MMW_SIZE_DEFAULT);
6140
6141         /* Set RTTBCNRC of queue X */
6142         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6143         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6144         IXGBE_WRITE_FLUSH(hw);
6145
6146         return 0;
6147 }
6148
6149 static int
6150 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6151                      __attribute__((unused)) uint32_t index,
6152                      __attribute__((unused)) uint32_t pool)
6153 {
6154         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6155         int diag;
6156
6157         /*
6158          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6159          * operation. Trap this case to avoid exhausting the [very limited]
6160          * set of PF resources used to store VF MAC addresses.
6161          */
6162         if (memcmp(hw->mac.perm_addr, mac_addr,
6163                         sizeof(struct rte_ether_addr)) == 0)
6164                 return -1;
6165         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6166         if (diag != 0)
6167                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6168                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6169                             mac_addr->addr_bytes[0],
6170                             mac_addr->addr_bytes[1],
6171                             mac_addr->addr_bytes[2],
6172                             mac_addr->addr_bytes[3],
6173                             mac_addr->addr_bytes[4],
6174                             mac_addr->addr_bytes[5],
6175                             diag);
6176         return diag;
6177 }
6178
6179 static void
6180 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6181 {
6182         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6183         struct rte_ether_addr *perm_addr =
6184                 (struct rte_ether_addr *)hw->mac.perm_addr;
6185         struct rte_ether_addr *mac_addr;
6186         uint32_t i;
6187         int diag;
6188
6189         /*
6190          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6191          * not support the deletion of a given MAC address.
6192          * Instead, it imposes to delete all MAC addresses, then to add again
6193          * all MAC addresses with the exception of the one to be deleted.
6194          */
6195         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6196
6197         /*
6198          * Add again all MAC addresses, with the exception of the deleted one
6199          * and of the permanent MAC address.
6200          */
6201         for (i = 0, mac_addr = dev->data->mac_addrs;
6202              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6203                 /* Skip the deleted MAC address */
6204                 if (i == index)
6205                         continue;
6206                 /* Skip NULL MAC addresses */
6207                 if (rte_is_zero_ether_addr(mac_addr))
6208                         continue;
6209                 /* Skip the permanent MAC address */
6210                 if (memcmp(perm_addr, mac_addr,
6211                                 sizeof(struct rte_ether_addr)) == 0)
6212                         continue;
6213                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6214                 if (diag != 0)
6215                         PMD_DRV_LOG(ERR,
6216                                     "Adding again MAC address "
6217                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6218                                     "diag=%d",
6219                                     mac_addr->addr_bytes[0],
6220                                     mac_addr->addr_bytes[1],
6221                                     mac_addr->addr_bytes[2],
6222                                     mac_addr->addr_bytes[3],
6223                                     mac_addr->addr_bytes[4],
6224                                     mac_addr->addr_bytes[5],
6225                                     diag);
6226         }
6227 }
6228
6229 static int
6230 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6231                         struct rte_ether_addr *addr)
6232 {
6233         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6234
6235         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6236
6237         return 0;
6238 }
6239
6240 int
6241 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6242                         struct rte_eth_syn_filter *filter,
6243                         bool add)
6244 {
6245         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6246         struct ixgbe_filter_info *filter_info =
6247                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6248         uint32_t syn_info;
6249         uint32_t synqf;
6250
6251         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6252                 return -EINVAL;
6253
6254         syn_info = filter_info->syn_info;
6255
6256         if (add) {
6257                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6258                         return -EINVAL;
6259                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6260                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6261
6262                 if (filter->hig_pri)
6263                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6264                 else
6265                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6266         } else {
6267                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6268                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6269                         return -ENOENT;
6270                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6271         }
6272
6273         filter_info->syn_info = synqf;
6274         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6275         IXGBE_WRITE_FLUSH(hw);
6276         return 0;
6277 }
6278
6279 static int
6280 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6281                         struct rte_eth_syn_filter *filter)
6282 {
6283         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6284         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6285
6286         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6287                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6288                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6289                 return 0;
6290         }
6291         return -ENOENT;
6292 }
6293
6294 static int
6295 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6296                         enum rte_filter_op filter_op,
6297                         void *arg)
6298 {
6299         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6300         int ret;
6301
6302         MAC_TYPE_FILTER_SUP(hw->mac.type);
6303
6304         if (filter_op == RTE_ETH_FILTER_NOP)
6305                 return 0;
6306
6307         if (arg == NULL) {
6308                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6309                             filter_op);
6310                 return -EINVAL;
6311         }
6312
6313         switch (filter_op) {
6314         case RTE_ETH_FILTER_ADD:
6315                 ret = ixgbe_syn_filter_set(dev,
6316                                 (struct rte_eth_syn_filter *)arg,
6317                                 TRUE);
6318                 break;
6319         case RTE_ETH_FILTER_DELETE:
6320                 ret = ixgbe_syn_filter_set(dev,
6321                                 (struct rte_eth_syn_filter *)arg,
6322                                 FALSE);
6323                 break;
6324         case RTE_ETH_FILTER_GET:
6325                 ret = ixgbe_syn_filter_get(dev,
6326                                 (struct rte_eth_syn_filter *)arg);
6327                 break;
6328         default:
6329                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6330                 ret = -EINVAL;
6331                 break;
6332         }
6333
6334         return ret;
6335 }
6336
6337
6338 static inline enum ixgbe_5tuple_protocol
6339 convert_protocol_type(uint8_t protocol_value)
6340 {
6341         if (protocol_value == IPPROTO_TCP)
6342                 return IXGBE_FILTER_PROTOCOL_TCP;
6343         else if (protocol_value == IPPROTO_UDP)
6344                 return IXGBE_FILTER_PROTOCOL_UDP;
6345         else if (protocol_value == IPPROTO_SCTP)
6346                 return IXGBE_FILTER_PROTOCOL_SCTP;
6347         else
6348                 return IXGBE_FILTER_PROTOCOL_NONE;
6349 }
6350
6351 /* inject a 5-tuple filter to HW */
6352 static inline void
6353 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6354                            struct ixgbe_5tuple_filter *filter)
6355 {
6356         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6357         int i;
6358         uint32_t ftqf, sdpqf;
6359         uint32_t l34timir = 0;
6360         uint8_t mask = 0xff;
6361
6362         i = filter->index;
6363
6364         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6365                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6366         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6367
6368         ftqf = (uint32_t)(filter->filter_info.proto &
6369                 IXGBE_FTQF_PROTOCOL_MASK);
6370         ftqf |= (uint32_t)((filter->filter_info.priority &
6371                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6372         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6373                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6374         if (filter->filter_info.dst_ip_mask == 0)
6375                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6376         if (filter->filter_info.src_port_mask == 0)
6377                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6378         if (filter->filter_info.dst_port_mask == 0)
6379                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6380         if (filter->filter_info.proto_mask == 0)
6381                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6382         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6383         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6384         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6385
6386         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6387         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6388         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6389         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6390
6391         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6392         l34timir |= (uint32_t)(filter->queue <<
6393                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6394         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6395 }
6396
6397 /*
6398  * add a 5tuple filter
6399  *
6400  * @param
6401  * dev: Pointer to struct rte_eth_dev.
6402  * index: the index the filter allocates.
6403  * filter: ponter to the filter that will be added.
6404  * rx_queue: the queue id the filter assigned to.
6405  *
6406  * @return
6407  *    - On success, zero.
6408  *    - On failure, a negative value.
6409  */
6410 static int
6411 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6412                         struct ixgbe_5tuple_filter *filter)
6413 {
6414         struct ixgbe_filter_info *filter_info =
6415                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6416         int i, idx, shift;
6417
6418         /*
6419          * look for an unused 5tuple filter index,
6420          * and insert the filter to list.
6421          */
6422         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6423                 idx = i / (sizeof(uint32_t) * NBBY);
6424                 shift = i % (sizeof(uint32_t) * NBBY);
6425                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6426                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6427                         filter->index = i;
6428                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6429                                           filter,
6430                                           entries);
6431                         break;
6432                 }
6433         }
6434         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6435                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6436                 return -ENOSYS;
6437         }
6438
6439         ixgbe_inject_5tuple_filter(dev, filter);
6440
6441         return 0;
6442 }
6443
6444 /*
6445  * remove a 5tuple filter
6446  *
6447  * @param
6448  * dev: Pointer to struct rte_eth_dev.
6449  * filter: the pointer of the filter will be removed.
6450  */
6451 static void
6452 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6453                         struct ixgbe_5tuple_filter *filter)
6454 {
6455         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6456         struct ixgbe_filter_info *filter_info =
6457                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6458         uint16_t index = filter->index;
6459
6460         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6461                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6462         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6463         rte_free(filter);
6464
6465         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6466         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6467         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6468         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6469         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6470 }
6471
6472 static int
6473 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6474 {
6475         struct ixgbe_hw *hw;
6476         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6477         struct rte_eth_dev_data *dev_data = dev->data;
6478
6479         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6480
6481         if (mtu < RTE_ETHER_MIN_MTU ||
6482                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6483                 return -EINVAL;
6484
6485         /* If device is started, refuse mtu that requires the support of
6486          * scattered packets when this feature has not been enabled before.
6487          */
6488         if (dev_data->dev_started && !dev_data->scattered_rx &&
6489             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6490              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6491                 PMD_INIT_LOG(ERR, "Stop port first.");
6492                 return -EINVAL;
6493         }
6494
6495         /*
6496          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6497          * request of the version 2.0 of the mailbox API.
6498          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6499          * of the mailbox API.
6500          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6501          * prior to 3.11.33 which contains the following change:
6502          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6503          */
6504         ixgbevf_rlpml_set_vf(hw, max_frame);
6505
6506         /* update max frame size */
6507         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6508         return 0;
6509 }
6510
6511 static inline struct ixgbe_5tuple_filter *
6512 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6513                         struct ixgbe_5tuple_filter_info *key)
6514 {
6515         struct ixgbe_5tuple_filter *it;
6516
6517         TAILQ_FOREACH(it, filter_list, entries) {
6518                 if (memcmp(key, &it->filter_info,
6519                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6520                         return it;
6521                 }
6522         }
6523         return NULL;
6524 }
6525
6526 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6527 static inline int
6528 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6529                         struct ixgbe_5tuple_filter_info *filter_info)
6530 {
6531         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6532                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6533                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6534                 return -EINVAL;
6535
6536         switch (filter->dst_ip_mask) {
6537         case UINT32_MAX:
6538                 filter_info->dst_ip_mask = 0;
6539                 filter_info->dst_ip = filter->dst_ip;
6540                 break;
6541         case 0:
6542                 filter_info->dst_ip_mask = 1;
6543                 break;
6544         default:
6545                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6546                 return -EINVAL;
6547         }
6548
6549         switch (filter->src_ip_mask) {
6550         case UINT32_MAX:
6551                 filter_info->src_ip_mask = 0;
6552                 filter_info->src_ip = filter->src_ip;
6553                 break;
6554         case 0:
6555                 filter_info->src_ip_mask = 1;
6556                 break;
6557         default:
6558                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6559                 return -EINVAL;
6560         }
6561
6562         switch (filter->dst_port_mask) {
6563         case UINT16_MAX:
6564                 filter_info->dst_port_mask = 0;
6565                 filter_info->dst_port = filter->dst_port;
6566                 break;
6567         case 0:
6568                 filter_info->dst_port_mask = 1;
6569                 break;
6570         default:
6571                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6572                 return -EINVAL;
6573         }
6574
6575         switch (filter->src_port_mask) {
6576         case UINT16_MAX:
6577                 filter_info->src_port_mask = 0;
6578                 filter_info->src_port = filter->src_port;
6579                 break;
6580         case 0:
6581                 filter_info->src_port_mask = 1;
6582                 break;
6583         default:
6584                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6585                 return -EINVAL;
6586         }
6587
6588         switch (filter->proto_mask) {
6589         case UINT8_MAX:
6590                 filter_info->proto_mask = 0;
6591                 filter_info->proto =
6592                         convert_protocol_type(filter->proto);
6593                 break;
6594         case 0:
6595                 filter_info->proto_mask = 1;
6596                 break;
6597         default:
6598                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6599                 return -EINVAL;
6600         }
6601
6602         filter_info->priority = (uint8_t)filter->priority;
6603         return 0;
6604 }
6605
6606 /*
6607  * add or delete a ntuple filter
6608  *
6609  * @param
6610  * dev: Pointer to struct rte_eth_dev.
6611  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6612  * add: if true, add filter, if false, remove filter
6613  *
6614  * @return
6615  *    - On success, zero.
6616  *    - On failure, a negative value.
6617  */
6618 int
6619 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6620                         struct rte_eth_ntuple_filter *ntuple_filter,
6621                         bool add)
6622 {
6623         struct ixgbe_filter_info *filter_info =
6624                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6625         struct ixgbe_5tuple_filter_info filter_5tuple;
6626         struct ixgbe_5tuple_filter *filter;
6627         int ret;
6628
6629         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6630                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6631                 return -EINVAL;
6632         }
6633
6634         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6635         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6636         if (ret < 0)
6637                 return ret;
6638
6639         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6640                                          &filter_5tuple);
6641         if (filter != NULL && add) {
6642                 PMD_DRV_LOG(ERR, "filter exists.");
6643                 return -EEXIST;
6644         }
6645         if (filter == NULL && !add) {
6646                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6647                 return -ENOENT;
6648         }
6649
6650         if (add) {
6651                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6652                                 sizeof(struct ixgbe_5tuple_filter), 0);
6653                 if (filter == NULL)
6654                         return -ENOMEM;
6655                 rte_memcpy(&filter->filter_info,
6656                                  &filter_5tuple,
6657                                  sizeof(struct ixgbe_5tuple_filter_info));
6658                 filter->queue = ntuple_filter->queue;
6659                 ret = ixgbe_add_5tuple_filter(dev, filter);
6660                 if (ret < 0) {
6661                         rte_free(filter);
6662                         return ret;
6663                 }
6664         } else
6665                 ixgbe_remove_5tuple_filter(dev, filter);
6666
6667         return 0;
6668 }
6669
6670 /*
6671  * get a ntuple filter
6672  *
6673  * @param
6674  * dev: Pointer to struct rte_eth_dev.
6675  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6676  *
6677  * @return
6678  *    - On success, zero.
6679  *    - On failure, a negative value.
6680  */
6681 static int
6682 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6683                         struct rte_eth_ntuple_filter *ntuple_filter)
6684 {
6685         struct ixgbe_filter_info *filter_info =
6686                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6687         struct ixgbe_5tuple_filter_info filter_5tuple;
6688         struct ixgbe_5tuple_filter *filter;
6689         int ret;
6690
6691         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6692                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6693                 return -EINVAL;
6694         }
6695
6696         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6697         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6698         if (ret < 0)
6699                 return ret;
6700
6701         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6702                                          &filter_5tuple);
6703         if (filter == NULL) {
6704                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6705                 return -ENOENT;
6706         }
6707         ntuple_filter->queue = filter->queue;
6708         return 0;
6709 }
6710
6711 /*
6712  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6713  * @dev: pointer to rte_eth_dev structure
6714  * @filter_op:operation will be taken.
6715  * @arg: a pointer to specific structure corresponding to the filter_op
6716  *
6717  * @return
6718  *    - On success, zero.
6719  *    - On failure, a negative value.
6720  */
6721 static int
6722 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6723                                 enum rte_filter_op filter_op,
6724                                 void *arg)
6725 {
6726         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6727         int ret;
6728
6729         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6730
6731         if (filter_op == RTE_ETH_FILTER_NOP)
6732                 return 0;
6733
6734         if (arg == NULL) {
6735                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6736                             filter_op);
6737                 return -EINVAL;
6738         }
6739
6740         switch (filter_op) {
6741         case RTE_ETH_FILTER_ADD:
6742                 ret = ixgbe_add_del_ntuple_filter(dev,
6743                         (struct rte_eth_ntuple_filter *)arg,
6744                         TRUE);
6745                 break;
6746         case RTE_ETH_FILTER_DELETE:
6747                 ret = ixgbe_add_del_ntuple_filter(dev,
6748                         (struct rte_eth_ntuple_filter *)arg,
6749                         FALSE);
6750                 break;
6751         case RTE_ETH_FILTER_GET:
6752                 ret = ixgbe_get_ntuple_filter(dev,
6753                         (struct rte_eth_ntuple_filter *)arg);
6754                 break;
6755         default:
6756                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6757                 ret = -EINVAL;
6758                 break;
6759         }
6760         return ret;
6761 }
6762
6763 int
6764 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6765                         struct rte_eth_ethertype_filter *filter,
6766                         bool add)
6767 {
6768         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6769         struct ixgbe_filter_info *filter_info =
6770                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6771         uint32_t etqf = 0;
6772         uint32_t etqs = 0;
6773         int ret;
6774         struct ixgbe_ethertype_filter ethertype_filter;
6775
6776         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6777                 return -EINVAL;
6778
6779         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6780                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6781                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6782                         " ethertype filter.", filter->ether_type);
6783                 return -EINVAL;
6784         }
6785
6786         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6787                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6788                 return -EINVAL;
6789         }
6790         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6791                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6792                 return -EINVAL;
6793         }
6794
6795         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6796         if (ret >= 0 && add) {
6797                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6798                             filter->ether_type);
6799                 return -EEXIST;
6800         }
6801         if (ret < 0 && !add) {
6802                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6803                             filter->ether_type);
6804                 return -ENOENT;
6805         }
6806
6807         if (add) {
6808                 etqf = IXGBE_ETQF_FILTER_EN;
6809                 etqf |= (uint32_t)filter->ether_type;
6810                 etqs |= (uint32_t)((filter->queue <<
6811                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6812                                     IXGBE_ETQS_RX_QUEUE);
6813                 etqs |= IXGBE_ETQS_QUEUE_EN;
6814
6815                 ethertype_filter.ethertype = filter->ether_type;
6816                 ethertype_filter.etqf = etqf;
6817                 ethertype_filter.etqs = etqs;
6818                 ethertype_filter.conf = FALSE;
6819                 ret = ixgbe_ethertype_filter_insert(filter_info,
6820                                                     &ethertype_filter);
6821                 if (ret < 0) {
6822                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6823                         return -ENOSPC;
6824                 }
6825         } else {
6826                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6827                 if (ret < 0)
6828                         return -ENOSYS;
6829         }
6830         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6831         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6832         IXGBE_WRITE_FLUSH(hw);
6833
6834         return 0;
6835 }
6836
6837 static int
6838 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6839                         struct rte_eth_ethertype_filter *filter)
6840 {
6841         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6842         struct ixgbe_filter_info *filter_info =
6843                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6844         uint32_t etqf, etqs;
6845         int ret;
6846
6847         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6848         if (ret < 0) {
6849                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6850                             filter->ether_type);
6851                 return -ENOENT;
6852         }
6853
6854         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6855         if (etqf & IXGBE_ETQF_FILTER_EN) {
6856                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6857                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6858                 filter->flags = 0;
6859                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6860                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6861                 return 0;
6862         }
6863         return -ENOENT;
6864 }
6865
6866 /*
6867  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6868  * @dev: pointer to rte_eth_dev structure
6869  * @filter_op:operation will be taken.
6870  * @arg: a pointer to specific structure corresponding to the filter_op
6871  */
6872 static int
6873 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6874                                 enum rte_filter_op filter_op,
6875                                 void *arg)
6876 {
6877         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6878         int ret;
6879
6880         MAC_TYPE_FILTER_SUP(hw->mac.type);
6881
6882         if (filter_op == RTE_ETH_FILTER_NOP)
6883                 return 0;
6884
6885         if (arg == NULL) {
6886                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6887                             filter_op);
6888                 return -EINVAL;
6889         }
6890
6891         switch (filter_op) {
6892         case RTE_ETH_FILTER_ADD:
6893                 ret = ixgbe_add_del_ethertype_filter(dev,
6894                         (struct rte_eth_ethertype_filter *)arg,
6895                         TRUE);
6896                 break;
6897         case RTE_ETH_FILTER_DELETE:
6898                 ret = ixgbe_add_del_ethertype_filter(dev,
6899                         (struct rte_eth_ethertype_filter *)arg,
6900                         FALSE);
6901                 break;
6902         case RTE_ETH_FILTER_GET:
6903                 ret = ixgbe_get_ethertype_filter(dev,
6904                         (struct rte_eth_ethertype_filter *)arg);
6905                 break;
6906         default:
6907                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6908                 ret = -EINVAL;
6909                 break;
6910         }
6911         return ret;
6912 }
6913
6914 static int
6915 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6916                      enum rte_filter_type filter_type,
6917                      enum rte_filter_op filter_op,
6918                      void *arg)
6919 {
6920         int ret = 0;
6921
6922         switch (filter_type) {
6923         case RTE_ETH_FILTER_NTUPLE:
6924                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6925                 break;
6926         case RTE_ETH_FILTER_ETHERTYPE:
6927                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6928                 break;
6929         case RTE_ETH_FILTER_SYN:
6930                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6931                 break;
6932         case RTE_ETH_FILTER_FDIR:
6933                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6934                 break;
6935         case RTE_ETH_FILTER_L2_TUNNEL:
6936                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6937                 break;
6938         case RTE_ETH_FILTER_GENERIC:
6939                 if (filter_op != RTE_ETH_FILTER_GET)
6940                         return -EINVAL;
6941                 *(const void **)arg = &ixgbe_flow_ops;
6942                 break;
6943         default:
6944                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6945                                                         filter_type);
6946                 ret = -EINVAL;
6947                 break;
6948         }
6949
6950         return ret;
6951 }
6952
6953 static u8 *
6954 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6955                         u8 **mc_addr_ptr, u32 *vmdq)
6956 {
6957         u8 *mc_addr;
6958
6959         *vmdq = 0;
6960         mc_addr = *mc_addr_ptr;
6961         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6962         return mc_addr;
6963 }
6964
6965 static int
6966 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6967                           struct rte_ether_addr *mc_addr_set,
6968                           uint32_t nb_mc_addr)
6969 {
6970         struct ixgbe_hw *hw;
6971         u8 *mc_addr_list;
6972
6973         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6974         mc_addr_list = (u8 *)mc_addr_set;
6975         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6976                                          ixgbe_dev_addr_list_itr, TRUE);
6977 }
6978
6979 static uint64_t
6980 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6981 {
6982         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6983         uint64_t systime_cycles;
6984
6985         switch (hw->mac.type) {
6986         case ixgbe_mac_X550:
6987         case ixgbe_mac_X550EM_x:
6988         case ixgbe_mac_X550EM_a:
6989                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6990                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6991                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6992                                 * NSEC_PER_SEC;
6993                 break;
6994         default:
6995                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6996                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6997                                 << 32;
6998         }
6999
7000         return systime_cycles;
7001 }
7002
7003 static uint64_t
7004 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7005 {
7006         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7007         uint64_t rx_tstamp_cycles;
7008
7009         switch (hw->mac.type) {
7010         case ixgbe_mac_X550:
7011         case ixgbe_mac_X550EM_x:
7012         case ixgbe_mac_X550EM_a:
7013                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7014                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7015                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7016                                 * NSEC_PER_SEC;
7017                 break;
7018         default:
7019                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7020                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7021                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7022                                 << 32;
7023         }
7024
7025         return rx_tstamp_cycles;
7026 }
7027
7028 static uint64_t
7029 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7030 {
7031         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7032         uint64_t tx_tstamp_cycles;
7033
7034         switch (hw->mac.type) {
7035         case ixgbe_mac_X550:
7036         case ixgbe_mac_X550EM_x:
7037         case ixgbe_mac_X550EM_a:
7038                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7039                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7040                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7041                                 * NSEC_PER_SEC;
7042                 break;
7043         default:
7044                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7045                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7046                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7047                                 << 32;
7048         }
7049
7050         return tx_tstamp_cycles;
7051 }
7052
7053 static void
7054 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7055 {
7056         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7057         struct ixgbe_adapter *adapter = dev->data->dev_private;
7058         struct rte_eth_link link;
7059         uint32_t incval = 0;
7060         uint32_t shift = 0;
7061
7062         /* Get current link speed. */
7063         ixgbe_dev_link_update(dev, 1);
7064         rte_eth_linkstatus_get(dev, &link);
7065
7066         switch (link.link_speed) {
7067         case ETH_SPEED_NUM_100M:
7068                 incval = IXGBE_INCVAL_100;
7069                 shift = IXGBE_INCVAL_SHIFT_100;
7070                 break;
7071         case ETH_SPEED_NUM_1G:
7072                 incval = IXGBE_INCVAL_1GB;
7073                 shift = IXGBE_INCVAL_SHIFT_1GB;
7074                 break;
7075         case ETH_SPEED_NUM_10G:
7076         default:
7077                 incval = IXGBE_INCVAL_10GB;
7078                 shift = IXGBE_INCVAL_SHIFT_10GB;
7079                 break;
7080         }
7081
7082         switch (hw->mac.type) {
7083         case ixgbe_mac_X550:
7084         case ixgbe_mac_X550EM_x:
7085         case ixgbe_mac_X550EM_a:
7086                 /* Independent of link speed. */
7087                 incval = 1;
7088                 /* Cycles read will be interpreted as ns. */
7089                 shift = 0;
7090                 /* Fall-through */
7091         case ixgbe_mac_X540:
7092                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7093                 break;
7094         case ixgbe_mac_82599EB:
7095                 incval >>= IXGBE_INCVAL_SHIFT_82599;
7096                 shift -= IXGBE_INCVAL_SHIFT_82599;
7097                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7098                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7099                 break;
7100         default:
7101                 /* Not supported. */
7102                 return;
7103         }
7104
7105         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7106         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7107         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7108
7109         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7110         adapter->systime_tc.cc_shift = shift;
7111         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7112
7113         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7114         adapter->rx_tstamp_tc.cc_shift = shift;
7115         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7116
7117         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7118         adapter->tx_tstamp_tc.cc_shift = shift;
7119         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7120 }
7121
7122 static int
7123 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7124 {
7125         struct ixgbe_adapter *adapter = dev->data->dev_private;
7126
7127         adapter->systime_tc.nsec += delta;
7128         adapter->rx_tstamp_tc.nsec += delta;
7129         adapter->tx_tstamp_tc.nsec += delta;
7130
7131         return 0;
7132 }
7133
7134 static int
7135 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7136 {
7137         uint64_t ns;
7138         struct ixgbe_adapter *adapter = dev->data->dev_private;
7139
7140         ns = rte_timespec_to_ns(ts);
7141         /* Set the timecounters to a new value. */
7142         adapter->systime_tc.nsec = ns;
7143         adapter->rx_tstamp_tc.nsec = ns;
7144         adapter->tx_tstamp_tc.nsec = ns;
7145
7146         return 0;
7147 }
7148
7149 static int
7150 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7151 {
7152         uint64_t ns, systime_cycles;
7153         struct ixgbe_adapter *adapter = dev->data->dev_private;
7154
7155         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7156         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7157         *ts = rte_ns_to_timespec(ns);
7158
7159         return 0;
7160 }
7161
7162 static int
7163 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7164 {
7165         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7166         uint32_t tsync_ctl;
7167         uint32_t tsauxc;
7168
7169         /* Stop the timesync system time. */
7170         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7171         /* Reset the timesync system time value. */
7172         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7173         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7174
7175         /* Enable system time for platforms where it isn't on by default. */
7176         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7177         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7178         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7179
7180         ixgbe_start_timecounters(dev);
7181
7182         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7183         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7184                         (RTE_ETHER_TYPE_1588 |
7185                          IXGBE_ETQF_FILTER_EN |
7186                          IXGBE_ETQF_1588));
7187
7188         /* Enable timestamping of received PTP packets. */
7189         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7190         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7191         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7192
7193         /* Enable timestamping of transmitted PTP packets. */
7194         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7195         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7196         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7197
7198         IXGBE_WRITE_FLUSH(hw);
7199
7200         return 0;
7201 }
7202
7203 static int
7204 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7205 {
7206         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7207         uint32_t tsync_ctl;
7208
7209         /* Disable timestamping of transmitted PTP packets. */
7210         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7211         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7212         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7213
7214         /* Disable timestamping of received PTP packets. */
7215         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7216         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7217         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7218
7219         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7220         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7221
7222         /* Stop incrementating the System Time registers. */
7223         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7224
7225         return 0;
7226 }
7227
7228 static int
7229 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7230                                  struct timespec *timestamp,
7231                                  uint32_t flags __rte_unused)
7232 {
7233         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7234         struct ixgbe_adapter *adapter = dev->data->dev_private;
7235         uint32_t tsync_rxctl;
7236         uint64_t rx_tstamp_cycles;
7237         uint64_t ns;
7238
7239         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7240         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7241                 return -EINVAL;
7242
7243         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7244         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7245         *timestamp = rte_ns_to_timespec(ns);
7246
7247         return  0;
7248 }
7249
7250 static int
7251 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7252                                  struct timespec *timestamp)
7253 {
7254         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7255         struct ixgbe_adapter *adapter = dev->data->dev_private;
7256         uint32_t tsync_txctl;
7257         uint64_t tx_tstamp_cycles;
7258         uint64_t ns;
7259
7260         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7261         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7262                 return -EINVAL;
7263
7264         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7265         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7266         *timestamp = rte_ns_to_timespec(ns);
7267
7268         return 0;
7269 }
7270
7271 static int
7272 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7273 {
7274         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7275         int count = 0;
7276         int g_ind = 0;
7277         const struct reg_info *reg_group;
7278         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7279                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7280
7281         while ((reg_group = reg_set[g_ind++]))
7282                 count += ixgbe_regs_group_count(reg_group);
7283
7284         return count;
7285 }
7286
7287 static int
7288 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7289 {
7290         int count = 0;
7291         int g_ind = 0;
7292         const struct reg_info *reg_group;
7293
7294         while ((reg_group = ixgbevf_regs[g_ind++]))
7295                 count += ixgbe_regs_group_count(reg_group);
7296
7297         return count;
7298 }
7299
7300 static int
7301 ixgbe_get_regs(struct rte_eth_dev *dev,
7302               struct rte_dev_reg_info *regs)
7303 {
7304         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7305         uint32_t *data = regs->data;
7306         int g_ind = 0;
7307         int count = 0;
7308         const struct reg_info *reg_group;
7309         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7310                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7311
7312         if (data == NULL) {
7313                 regs->length = ixgbe_get_reg_length(dev);
7314                 regs->width = sizeof(uint32_t);
7315                 return 0;
7316         }
7317
7318         /* Support only full register dump */
7319         if ((regs->length == 0) ||
7320             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7321                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7322                         hw->device_id;
7323                 while ((reg_group = reg_set[g_ind++]))
7324                         count += ixgbe_read_regs_group(dev, &data[count],
7325                                 reg_group);
7326                 return 0;
7327         }
7328
7329         return -ENOTSUP;
7330 }
7331
7332 static int
7333 ixgbevf_get_regs(struct rte_eth_dev *dev,
7334                 struct rte_dev_reg_info *regs)
7335 {
7336         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7337         uint32_t *data = regs->data;
7338         int g_ind = 0;
7339         int count = 0;
7340         const struct reg_info *reg_group;
7341
7342         if (data == NULL) {
7343                 regs->length = ixgbevf_get_reg_length(dev);
7344                 regs->width = sizeof(uint32_t);
7345                 return 0;
7346         }
7347
7348         /* Support only full register dump */
7349         if ((regs->length == 0) ||
7350             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7351                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7352                         hw->device_id;
7353                 while ((reg_group = ixgbevf_regs[g_ind++]))
7354                         count += ixgbe_read_regs_group(dev, &data[count],
7355                                                       reg_group);
7356                 return 0;
7357         }
7358
7359         return -ENOTSUP;
7360 }
7361
7362 static int
7363 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7364 {
7365         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7366
7367         /* Return unit is byte count */
7368         return hw->eeprom.word_size * 2;
7369 }
7370
7371 static int
7372 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7373                 struct rte_dev_eeprom_info *in_eeprom)
7374 {
7375         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7376         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7377         uint16_t *data = in_eeprom->data;
7378         int first, length;
7379
7380         first = in_eeprom->offset >> 1;
7381         length = in_eeprom->length >> 1;
7382         if ((first > hw->eeprom.word_size) ||
7383             ((first + length) > hw->eeprom.word_size))
7384                 return -EINVAL;
7385
7386         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7387
7388         return eeprom->ops.read_buffer(hw, first, length, data);
7389 }
7390
7391 static int
7392 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7393                 struct rte_dev_eeprom_info *in_eeprom)
7394 {
7395         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7396         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7397         uint16_t *data = in_eeprom->data;
7398         int first, length;
7399
7400         first = in_eeprom->offset >> 1;
7401         length = in_eeprom->length >> 1;
7402         if ((first > hw->eeprom.word_size) ||
7403             ((first + length) > hw->eeprom.word_size))
7404                 return -EINVAL;
7405
7406         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7407
7408         return eeprom->ops.write_buffer(hw,  first, length, data);
7409 }
7410
7411 static int
7412 ixgbe_get_module_info(struct rte_eth_dev *dev,
7413                       struct rte_eth_dev_module_info *modinfo)
7414 {
7415         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7416         uint32_t status;
7417         uint8_t sff8472_rev, addr_mode;
7418         bool page_swap = false;
7419
7420         /* Check whether we support SFF-8472 or not */
7421         status = hw->phy.ops.read_i2c_eeprom(hw,
7422                                              IXGBE_SFF_SFF_8472_COMP,
7423                                              &sff8472_rev);
7424         if (status != 0)
7425                 return -EIO;
7426
7427         /* addressing mode is not supported */
7428         status = hw->phy.ops.read_i2c_eeprom(hw,
7429                                              IXGBE_SFF_SFF_8472_SWAP,
7430                                              &addr_mode);
7431         if (status != 0)
7432                 return -EIO;
7433
7434         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7435                 PMD_DRV_LOG(ERR,
7436                             "Address change required to access page 0xA2, "
7437                             "but not supported. Please report the module "
7438                             "type to the driver maintainers.");
7439                 page_swap = true;
7440         }
7441
7442         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7443                 /* We have a SFP, but it does not support SFF-8472 */
7444                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7445                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7446         } else {
7447                 /* We have a SFP which supports a revision of SFF-8472. */
7448                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7449                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7450         }
7451
7452         return 0;
7453 }
7454
7455 static int
7456 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7457                         struct rte_dev_eeprom_info *info)
7458 {
7459         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7460         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7461         uint8_t databyte = 0xFF;
7462         uint8_t *data = info->data;
7463         uint32_t i = 0;
7464
7465         if (info->length == 0)
7466                 return -EINVAL;
7467
7468         for (i = info->offset; i < info->offset + info->length; i++) {
7469                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7470                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7471                 else
7472                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7473
7474                 if (status != 0)
7475                         return -EIO;
7476
7477                 data[i - info->offset] = databyte;
7478         }
7479
7480         return 0;
7481 }
7482
7483 uint16_t
7484 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7485         switch (mac_type) {
7486         case ixgbe_mac_X550:
7487         case ixgbe_mac_X550EM_x:
7488         case ixgbe_mac_X550EM_a:
7489                 return ETH_RSS_RETA_SIZE_512;
7490         case ixgbe_mac_X550_vf:
7491         case ixgbe_mac_X550EM_x_vf:
7492         case ixgbe_mac_X550EM_a_vf:
7493                 return ETH_RSS_RETA_SIZE_64;
7494         case ixgbe_mac_X540_vf:
7495         case ixgbe_mac_82599_vf:
7496                 return 0;
7497         default:
7498                 return ETH_RSS_RETA_SIZE_128;
7499         }
7500 }
7501
7502 uint32_t
7503 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7504         switch (mac_type) {
7505         case ixgbe_mac_X550:
7506         case ixgbe_mac_X550EM_x:
7507         case ixgbe_mac_X550EM_a:
7508                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7509                         return IXGBE_RETA(reta_idx >> 2);
7510                 else
7511                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7512         case ixgbe_mac_X550_vf:
7513         case ixgbe_mac_X550EM_x_vf:
7514         case ixgbe_mac_X550EM_a_vf:
7515                 return IXGBE_VFRETA(reta_idx >> 2);
7516         default:
7517                 return IXGBE_RETA(reta_idx >> 2);
7518         }
7519 }
7520
7521 uint32_t
7522 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7523         switch (mac_type) {
7524         case ixgbe_mac_X550_vf:
7525         case ixgbe_mac_X550EM_x_vf:
7526         case ixgbe_mac_X550EM_a_vf:
7527                 return IXGBE_VFMRQC;
7528         default:
7529                 return IXGBE_MRQC;
7530         }
7531 }
7532
7533 uint32_t
7534 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7535         switch (mac_type) {
7536         case ixgbe_mac_X550_vf:
7537         case ixgbe_mac_X550EM_x_vf:
7538         case ixgbe_mac_X550EM_a_vf:
7539                 return IXGBE_VFRSSRK(i);
7540         default:
7541                 return IXGBE_RSSRK(i);
7542         }
7543 }
7544
7545 bool
7546 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7547         switch (mac_type) {
7548         case ixgbe_mac_82599_vf:
7549         case ixgbe_mac_X540_vf:
7550                 return 0;
7551         default:
7552                 return 1;
7553         }
7554 }
7555
7556 static int
7557 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7558                         struct rte_eth_dcb_info *dcb_info)
7559 {
7560         struct ixgbe_dcb_config *dcb_config =
7561                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7562         struct ixgbe_dcb_tc_config *tc;
7563         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7564         uint8_t nb_tcs;
7565         uint8_t i, j;
7566
7567         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7568                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7569         else
7570                 dcb_info->nb_tcs = 1;
7571
7572         tc_queue = &dcb_info->tc_queue;
7573         nb_tcs = dcb_info->nb_tcs;
7574
7575         if (dcb_config->vt_mode) { /* vt is enabled*/
7576                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7577                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7578                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7579                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7580                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7581                         for (j = 0; j < nb_tcs; j++) {
7582                                 tc_queue->tc_rxq[0][j].base = j;
7583                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7584                                 tc_queue->tc_txq[0][j].base = j;
7585                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7586                         }
7587                 } else {
7588                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7589                                 for (j = 0; j < nb_tcs; j++) {
7590                                         tc_queue->tc_rxq[i][j].base =
7591                                                 i * nb_tcs + j;
7592                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7593                                         tc_queue->tc_txq[i][j].base =
7594                                                 i * nb_tcs + j;
7595                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7596                                 }
7597                         }
7598                 }
7599         } else { /* vt is disabled*/
7600                 struct rte_eth_dcb_rx_conf *rx_conf =
7601                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7602                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7603                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7604                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7605                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7606                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7607                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7608                         }
7609                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7610                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7611                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7612                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7613                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7614                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7615                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7616                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7617                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7618                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7619                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7620                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7621                         }
7622                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7623                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7624                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7625                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7626                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7627                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7628                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7629                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7630                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7631                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7632                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7633                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7634                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7635                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7636                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7637                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7638                 }
7639         }
7640         for (i = 0; i < dcb_info->nb_tcs; i++) {
7641                 tc = &dcb_config->tc_config[i];
7642                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7643         }
7644         return 0;
7645 }
7646
7647 /* Update e-tag ether type */
7648 static int
7649 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7650                             uint16_t ether_type)
7651 {
7652         uint32_t etag_etype;
7653
7654         if (hw->mac.type != ixgbe_mac_X550 &&
7655             hw->mac.type != ixgbe_mac_X550EM_x &&
7656             hw->mac.type != ixgbe_mac_X550EM_a) {
7657                 return -ENOTSUP;
7658         }
7659
7660         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7661         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7662         etag_etype |= ether_type;
7663         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7664         IXGBE_WRITE_FLUSH(hw);
7665
7666         return 0;
7667 }
7668
7669 /* Config l2 tunnel ether type */
7670 static int
7671 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7672                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7673 {
7674         int ret = 0;
7675         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7676         struct ixgbe_l2_tn_info *l2_tn_info =
7677                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7678
7679         if (l2_tunnel == NULL)
7680                 return -EINVAL;
7681
7682         switch (l2_tunnel->l2_tunnel_type) {
7683         case RTE_L2_TUNNEL_TYPE_E_TAG:
7684                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7685                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7686                 break;
7687         default:
7688                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7689                 ret = -EINVAL;
7690                 break;
7691         }
7692
7693         return ret;
7694 }
7695
7696 /* Enable e-tag tunnel */
7697 static int
7698 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7699 {
7700         uint32_t etag_etype;
7701
7702         if (hw->mac.type != ixgbe_mac_X550 &&
7703             hw->mac.type != ixgbe_mac_X550EM_x &&
7704             hw->mac.type != ixgbe_mac_X550EM_a) {
7705                 return -ENOTSUP;
7706         }
7707
7708         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7709         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7710         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7711         IXGBE_WRITE_FLUSH(hw);
7712
7713         return 0;
7714 }
7715
7716 /* Enable l2 tunnel */
7717 static int
7718 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7719                            enum rte_eth_tunnel_type l2_tunnel_type)
7720 {
7721         int ret = 0;
7722         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7723         struct ixgbe_l2_tn_info *l2_tn_info =
7724                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7725
7726         switch (l2_tunnel_type) {
7727         case RTE_L2_TUNNEL_TYPE_E_TAG:
7728                 l2_tn_info->e_tag_en = TRUE;
7729                 ret = ixgbe_e_tag_enable(hw);
7730                 break;
7731         default:
7732                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7733                 ret = -EINVAL;
7734                 break;
7735         }
7736
7737         return ret;
7738 }
7739
7740 /* Disable e-tag tunnel */
7741 static int
7742 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7743 {
7744         uint32_t etag_etype;
7745
7746         if (hw->mac.type != ixgbe_mac_X550 &&
7747             hw->mac.type != ixgbe_mac_X550EM_x &&
7748             hw->mac.type != ixgbe_mac_X550EM_a) {
7749                 return -ENOTSUP;
7750         }
7751
7752         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7753         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7754         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7755         IXGBE_WRITE_FLUSH(hw);
7756
7757         return 0;
7758 }
7759
7760 /* Disable l2 tunnel */
7761 static int
7762 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7763                             enum rte_eth_tunnel_type l2_tunnel_type)
7764 {
7765         int ret = 0;
7766         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7767         struct ixgbe_l2_tn_info *l2_tn_info =
7768                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7769
7770         switch (l2_tunnel_type) {
7771         case RTE_L2_TUNNEL_TYPE_E_TAG:
7772                 l2_tn_info->e_tag_en = FALSE;
7773                 ret = ixgbe_e_tag_disable(hw);
7774                 break;
7775         default:
7776                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7777                 ret = -EINVAL;
7778                 break;
7779         }
7780
7781         return ret;
7782 }
7783
7784 static int
7785 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7786                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7787 {
7788         int ret = 0;
7789         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7790         uint32_t i, rar_entries;
7791         uint32_t rar_low, rar_high;
7792
7793         if (hw->mac.type != ixgbe_mac_X550 &&
7794             hw->mac.type != ixgbe_mac_X550EM_x &&
7795             hw->mac.type != ixgbe_mac_X550EM_a) {
7796                 return -ENOTSUP;
7797         }
7798
7799         rar_entries = ixgbe_get_num_rx_addrs(hw);
7800
7801         for (i = 1; i < rar_entries; i++) {
7802                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7803                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7804                 if ((rar_high & IXGBE_RAH_AV) &&
7805                     (rar_high & IXGBE_RAH_ADTYPE) &&
7806                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7807                      l2_tunnel->tunnel_id)) {
7808                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7809                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7810
7811                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7812
7813                         return ret;
7814                 }
7815         }
7816
7817         return ret;
7818 }
7819
7820 static int
7821 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7822                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7823 {
7824         int ret = 0;
7825         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7826         uint32_t i, rar_entries;
7827         uint32_t rar_low, rar_high;
7828
7829         if (hw->mac.type != ixgbe_mac_X550 &&
7830             hw->mac.type != ixgbe_mac_X550EM_x &&
7831             hw->mac.type != ixgbe_mac_X550EM_a) {
7832                 return -ENOTSUP;
7833         }
7834
7835         /* One entry for one tunnel. Try to remove potential existing entry. */
7836         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7837
7838         rar_entries = ixgbe_get_num_rx_addrs(hw);
7839
7840         for (i = 1; i < rar_entries; i++) {
7841                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7842                 if (rar_high & IXGBE_RAH_AV) {
7843                         continue;
7844                 } else {
7845                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7846                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7847                         rar_low = l2_tunnel->tunnel_id;
7848
7849                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7850                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7851
7852                         return ret;
7853                 }
7854         }
7855
7856         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7857                      " Please remove a rule before adding a new one.");
7858         return -EINVAL;
7859 }
7860
7861 static inline struct ixgbe_l2_tn_filter *
7862 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7863                           struct ixgbe_l2_tn_key *key)
7864 {
7865         int ret;
7866
7867         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7868         if (ret < 0)
7869                 return NULL;
7870
7871         return l2_tn_info->hash_map[ret];
7872 }
7873
7874 static inline int
7875 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7876                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7877 {
7878         int ret;
7879
7880         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7881                                &l2_tn_filter->key);
7882
7883         if (ret < 0) {
7884                 PMD_DRV_LOG(ERR,
7885                             "Failed to insert L2 tunnel filter"
7886                             " to hash table %d!",
7887                             ret);
7888                 return ret;
7889         }
7890
7891         l2_tn_info->hash_map[ret] = l2_tn_filter;
7892
7893         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7894
7895         return 0;
7896 }
7897
7898 static inline int
7899 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7900                           struct ixgbe_l2_tn_key *key)
7901 {
7902         int ret;
7903         struct ixgbe_l2_tn_filter *l2_tn_filter;
7904
7905         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7906
7907         if (ret < 0) {
7908                 PMD_DRV_LOG(ERR,
7909                             "No such L2 tunnel filter to delete %d!",
7910                             ret);
7911                 return ret;
7912         }
7913
7914         l2_tn_filter = l2_tn_info->hash_map[ret];
7915         l2_tn_info->hash_map[ret] = NULL;
7916
7917         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7918         rte_free(l2_tn_filter);
7919
7920         return 0;
7921 }
7922
7923 /* Add l2 tunnel filter */
7924 int
7925 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7926                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7927                                bool restore)
7928 {
7929         int ret;
7930         struct ixgbe_l2_tn_info *l2_tn_info =
7931                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7932         struct ixgbe_l2_tn_key key;
7933         struct ixgbe_l2_tn_filter *node;
7934
7935         if (!restore) {
7936                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7937                 key.tn_id = l2_tunnel->tunnel_id;
7938
7939                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7940
7941                 if (node) {
7942                         PMD_DRV_LOG(ERR,
7943                                     "The L2 tunnel filter already exists!");
7944                         return -EINVAL;
7945                 }
7946
7947                 node = rte_zmalloc("ixgbe_l2_tn",
7948                                    sizeof(struct ixgbe_l2_tn_filter),
7949                                    0);
7950                 if (!node)
7951                         return -ENOMEM;
7952
7953                 rte_memcpy(&node->key,
7954                                  &key,
7955                                  sizeof(struct ixgbe_l2_tn_key));
7956                 node->pool = l2_tunnel->pool;
7957                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7958                 if (ret < 0) {
7959                         rte_free(node);
7960                         return ret;
7961                 }
7962         }
7963
7964         switch (l2_tunnel->l2_tunnel_type) {
7965         case RTE_L2_TUNNEL_TYPE_E_TAG:
7966                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7967                 break;
7968         default:
7969                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7970                 ret = -EINVAL;
7971                 break;
7972         }
7973
7974         if ((!restore) && (ret < 0))
7975                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7976
7977         return ret;
7978 }
7979
7980 /* Delete l2 tunnel filter */
7981 int
7982 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7983                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7984 {
7985         int ret;
7986         struct ixgbe_l2_tn_info *l2_tn_info =
7987                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7988         struct ixgbe_l2_tn_key key;
7989
7990         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7991         key.tn_id = l2_tunnel->tunnel_id;
7992         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7993         if (ret < 0)
7994                 return ret;
7995
7996         switch (l2_tunnel->l2_tunnel_type) {
7997         case RTE_L2_TUNNEL_TYPE_E_TAG:
7998                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7999                 break;
8000         default:
8001                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8002                 ret = -EINVAL;
8003                 break;
8004         }
8005
8006         return ret;
8007 }
8008
8009 /**
8010  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8011  * @dev: pointer to rte_eth_dev structure
8012  * @filter_op:operation will be taken.
8013  * @arg: a pointer to specific structure corresponding to the filter_op
8014  */
8015 static int
8016 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8017                                   enum rte_filter_op filter_op,
8018                                   void *arg)
8019 {
8020         int ret;
8021
8022         if (filter_op == RTE_ETH_FILTER_NOP)
8023                 return 0;
8024
8025         if (arg == NULL) {
8026                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8027                             filter_op);
8028                 return -EINVAL;
8029         }
8030
8031         switch (filter_op) {
8032         case RTE_ETH_FILTER_ADD:
8033                 ret = ixgbe_dev_l2_tunnel_filter_add
8034                         (dev,
8035                          (struct rte_eth_l2_tunnel_conf *)arg,
8036                          FALSE);
8037                 break;
8038         case RTE_ETH_FILTER_DELETE:
8039                 ret = ixgbe_dev_l2_tunnel_filter_del
8040                         (dev,
8041                          (struct rte_eth_l2_tunnel_conf *)arg);
8042                 break;
8043         default:
8044                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8045                 ret = -EINVAL;
8046                 break;
8047         }
8048         return ret;
8049 }
8050
8051 static int
8052 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8053 {
8054         int ret = 0;
8055         uint32_t ctrl;
8056         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8057
8058         if (hw->mac.type != ixgbe_mac_X550 &&
8059             hw->mac.type != ixgbe_mac_X550EM_x &&
8060             hw->mac.type != ixgbe_mac_X550EM_a) {
8061                 return -ENOTSUP;
8062         }
8063
8064         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8065         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8066         if (en)
8067                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8068         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8069
8070         return ret;
8071 }
8072
8073 /* Enable l2 tunnel forwarding */
8074 static int
8075 ixgbe_dev_l2_tunnel_forwarding_enable
8076         (struct rte_eth_dev *dev,
8077          enum rte_eth_tunnel_type l2_tunnel_type)
8078 {
8079         struct ixgbe_l2_tn_info *l2_tn_info =
8080                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8081         int ret = 0;
8082
8083         switch (l2_tunnel_type) {
8084         case RTE_L2_TUNNEL_TYPE_E_TAG:
8085                 l2_tn_info->e_tag_fwd_en = TRUE;
8086                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8087                 break;
8088         default:
8089                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8090                 ret = -EINVAL;
8091                 break;
8092         }
8093
8094         return ret;
8095 }
8096
8097 /* Disable l2 tunnel forwarding */
8098 static int
8099 ixgbe_dev_l2_tunnel_forwarding_disable
8100         (struct rte_eth_dev *dev,
8101          enum rte_eth_tunnel_type l2_tunnel_type)
8102 {
8103         struct ixgbe_l2_tn_info *l2_tn_info =
8104                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8105         int ret = 0;
8106
8107         switch (l2_tunnel_type) {
8108         case RTE_L2_TUNNEL_TYPE_E_TAG:
8109                 l2_tn_info->e_tag_fwd_en = FALSE;
8110                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8111                 break;
8112         default:
8113                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8114                 ret = -EINVAL;
8115                 break;
8116         }
8117
8118         return ret;
8119 }
8120
8121 static int
8122 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8123                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
8124                              bool en)
8125 {
8126         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8127         int ret = 0;
8128         uint32_t vmtir, vmvir;
8129         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8130
8131         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8132                 PMD_DRV_LOG(ERR,
8133                             "VF id %u should be less than %u",
8134                             l2_tunnel->vf_id,
8135                             pci_dev->max_vfs);
8136                 return -EINVAL;
8137         }
8138
8139         if (hw->mac.type != ixgbe_mac_X550 &&
8140             hw->mac.type != ixgbe_mac_X550EM_x &&
8141             hw->mac.type != ixgbe_mac_X550EM_a) {
8142                 return -ENOTSUP;
8143         }
8144
8145         if (en)
8146                 vmtir = l2_tunnel->tunnel_id;
8147         else
8148                 vmtir = 0;
8149
8150         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8151
8152         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8153         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8154         if (en)
8155                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8156         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8157
8158         return ret;
8159 }
8160
8161 /* Enable l2 tunnel tag insertion */
8162 static int
8163 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8164                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8165 {
8166         int ret = 0;
8167
8168         switch (l2_tunnel->l2_tunnel_type) {
8169         case RTE_L2_TUNNEL_TYPE_E_TAG:
8170                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8171                 break;
8172         default:
8173                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8174                 ret = -EINVAL;
8175                 break;
8176         }
8177
8178         return ret;
8179 }
8180
8181 /* Disable l2 tunnel tag insertion */
8182 static int
8183 ixgbe_dev_l2_tunnel_insertion_disable
8184         (struct rte_eth_dev *dev,
8185          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8186 {
8187         int ret = 0;
8188
8189         switch (l2_tunnel->l2_tunnel_type) {
8190         case RTE_L2_TUNNEL_TYPE_E_TAG:
8191                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8192                 break;
8193         default:
8194                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8195                 ret = -EINVAL;
8196                 break;
8197         }
8198
8199         return ret;
8200 }
8201
8202 static int
8203 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8204                              bool en)
8205 {
8206         int ret = 0;
8207         uint32_t qde;
8208         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8209
8210         if (hw->mac.type != ixgbe_mac_X550 &&
8211             hw->mac.type != ixgbe_mac_X550EM_x &&
8212             hw->mac.type != ixgbe_mac_X550EM_a) {
8213                 return -ENOTSUP;
8214         }
8215
8216         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8217         if (en)
8218                 qde |= IXGBE_QDE_STRIP_TAG;
8219         else
8220                 qde &= ~IXGBE_QDE_STRIP_TAG;
8221         qde &= ~IXGBE_QDE_READ;
8222         qde |= IXGBE_QDE_WRITE;
8223         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8224
8225         return ret;
8226 }
8227
8228 /* Enable l2 tunnel tag stripping */
8229 static int
8230 ixgbe_dev_l2_tunnel_stripping_enable
8231         (struct rte_eth_dev *dev,
8232          enum rte_eth_tunnel_type l2_tunnel_type)
8233 {
8234         int ret = 0;
8235
8236         switch (l2_tunnel_type) {
8237         case RTE_L2_TUNNEL_TYPE_E_TAG:
8238                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8239                 break;
8240         default:
8241                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8242                 ret = -EINVAL;
8243                 break;
8244         }
8245
8246         return ret;
8247 }
8248
8249 /* Disable l2 tunnel tag stripping */
8250 static int
8251 ixgbe_dev_l2_tunnel_stripping_disable
8252         (struct rte_eth_dev *dev,
8253          enum rte_eth_tunnel_type l2_tunnel_type)
8254 {
8255         int ret = 0;
8256
8257         switch (l2_tunnel_type) {
8258         case RTE_L2_TUNNEL_TYPE_E_TAG:
8259                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8260                 break;
8261         default:
8262                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8263                 ret = -EINVAL;
8264                 break;
8265         }
8266
8267         return ret;
8268 }
8269
8270 /* Enable/disable l2 tunnel offload functions */
8271 static int
8272 ixgbe_dev_l2_tunnel_offload_set
8273         (struct rte_eth_dev *dev,
8274          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8275          uint32_t mask,
8276          uint8_t en)
8277 {
8278         int ret = 0;
8279
8280         if (l2_tunnel == NULL)
8281                 return -EINVAL;
8282
8283         ret = -EINVAL;
8284         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8285                 if (en)
8286                         ret = ixgbe_dev_l2_tunnel_enable(
8287                                 dev,
8288                                 l2_tunnel->l2_tunnel_type);
8289                 else
8290                         ret = ixgbe_dev_l2_tunnel_disable(
8291                                 dev,
8292                                 l2_tunnel->l2_tunnel_type);
8293         }
8294
8295         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8296                 if (en)
8297                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8298                                 dev,
8299                                 l2_tunnel);
8300                 else
8301                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8302                                 dev,
8303                                 l2_tunnel);
8304         }
8305
8306         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8307                 if (en)
8308                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8309                                 dev,
8310                                 l2_tunnel->l2_tunnel_type);
8311                 else
8312                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8313                                 dev,
8314                                 l2_tunnel->l2_tunnel_type);
8315         }
8316
8317         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8318                 if (en)
8319                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8320                                 dev,
8321                                 l2_tunnel->l2_tunnel_type);
8322                 else
8323                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8324                                 dev,
8325                                 l2_tunnel->l2_tunnel_type);
8326         }
8327
8328         return ret;
8329 }
8330
8331 static int
8332 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8333                         uint16_t port)
8334 {
8335         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8336         IXGBE_WRITE_FLUSH(hw);
8337
8338         return 0;
8339 }
8340
8341 /* There's only one register for VxLAN UDP port.
8342  * So, we cannot add several ports. Will update it.
8343  */
8344 static int
8345 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8346                      uint16_t port)
8347 {
8348         if (port == 0) {
8349                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8350                 return -EINVAL;
8351         }
8352
8353         return ixgbe_update_vxlan_port(hw, port);
8354 }
8355
8356 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8357  * UDP port, it must have a value.
8358  * So, will reset it to the original value 0.
8359  */
8360 static int
8361 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8362                      uint16_t port)
8363 {
8364         uint16_t cur_port;
8365
8366         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8367
8368         if (cur_port != port) {
8369                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8370                 return -EINVAL;
8371         }
8372
8373         return ixgbe_update_vxlan_port(hw, 0);
8374 }
8375
8376 /* Add UDP tunneling port */
8377 static int
8378 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8379                               struct rte_eth_udp_tunnel *udp_tunnel)
8380 {
8381         int ret = 0;
8382         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8383
8384         if (hw->mac.type != ixgbe_mac_X550 &&
8385             hw->mac.type != ixgbe_mac_X550EM_x &&
8386             hw->mac.type != ixgbe_mac_X550EM_a) {
8387                 return -ENOTSUP;
8388         }
8389
8390         if (udp_tunnel == NULL)
8391                 return -EINVAL;
8392
8393         switch (udp_tunnel->prot_type) {
8394         case RTE_TUNNEL_TYPE_VXLAN:
8395                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8396                 break;
8397
8398         case RTE_TUNNEL_TYPE_GENEVE:
8399         case RTE_TUNNEL_TYPE_TEREDO:
8400                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8401                 ret = -EINVAL;
8402                 break;
8403
8404         default:
8405                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8406                 ret = -EINVAL;
8407                 break;
8408         }
8409
8410         return ret;
8411 }
8412
8413 /* Remove UDP tunneling port */
8414 static int
8415 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8416                               struct rte_eth_udp_tunnel *udp_tunnel)
8417 {
8418         int ret = 0;
8419         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8420
8421         if (hw->mac.type != ixgbe_mac_X550 &&
8422             hw->mac.type != ixgbe_mac_X550EM_x &&
8423             hw->mac.type != ixgbe_mac_X550EM_a) {
8424                 return -ENOTSUP;
8425         }
8426
8427         if (udp_tunnel == NULL)
8428                 return -EINVAL;
8429
8430         switch (udp_tunnel->prot_type) {
8431         case RTE_TUNNEL_TYPE_VXLAN:
8432                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8433                 break;
8434         case RTE_TUNNEL_TYPE_GENEVE:
8435         case RTE_TUNNEL_TYPE_TEREDO:
8436                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8437                 ret = -EINVAL;
8438                 break;
8439         default:
8440                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8441                 ret = -EINVAL;
8442                 break;
8443         }
8444
8445         return ret;
8446 }
8447
8448 static int
8449 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8450 {
8451         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8452         int ret;
8453
8454         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8455         case IXGBE_SUCCESS:
8456                 ret = 0;
8457                 break;
8458         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8459                 ret = -ENOTSUP;
8460                 break;
8461         default:
8462                 ret = -EAGAIN;
8463                 break;
8464         }
8465
8466         return ret;
8467 }
8468
8469 static int
8470 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8471 {
8472         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8473         int ret;
8474
8475         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8476         case IXGBE_SUCCESS:
8477                 ret = 0;
8478                 break;
8479         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8480                 ret = -ENOTSUP;
8481                 break;
8482         default:
8483                 ret = -EAGAIN;
8484                 break;
8485         }
8486
8487         return ret;
8488 }
8489
8490 static int
8491 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8492 {
8493         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8494         int ret;
8495         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8496
8497         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8498         case IXGBE_SUCCESS:
8499                 ret = 0;
8500                 break;
8501         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8502                 ret = -ENOTSUP;
8503                 break;
8504         default:
8505                 ret = -EAGAIN;
8506                 break;
8507         }
8508
8509         return ret;
8510 }
8511
8512 static int
8513 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8514 {
8515         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8516         int ret;
8517
8518         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8519         case IXGBE_SUCCESS:
8520                 ret = 0;
8521                 break;
8522         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8523                 ret = -ENOTSUP;
8524                 break;
8525         default:
8526                 ret = -EAGAIN;
8527                 break;
8528         }
8529
8530         return ret;
8531 }
8532
8533 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8534 {
8535         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8536         u32 in_msg = 0;
8537
8538         /* peek the message first */
8539         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8540
8541         /* PF reset VF event */
8542         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8543                 /* dummy mbx read to ack pf */
8544                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8545                         return;
8546                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8547                                               NULL);
8548         }
8549 }
8550
8551 static int
8552 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8553 {
8554         uint32_t eicr;
8555         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8556         struct ixgbe_interrupt *intr =
8557                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8558         ixgbevf_intr_disable(dev);
8559
8560         /* read-on-clear nic registers here */
8561         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8562         intr->flags = 0;
8563
8564         /* only one misc vector supported - mailbox */
8565         eicr &= IXGBE_VTEICR_MASK;
8566         if (eicr == IXGBE_MISC_VEC_ID)
8567                 intr->flags |= IXGBE_FLAG_MAILBOX;
8568
8569         return 0;
8570 }
8571
8572 static int
8573 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8574 {
8575         struct ixgbe_interrupt *intr =
8576                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8577
8578         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8579                 ixgbevf_mbx_process(dev);
8580                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8581         }
8582
8583         ixgbevf_intr_enable(dev);
8584
8585         return 0;
8586 }
8587
8588 static void
8589 ixgbevf_dev_interrupt_handler(void *param)
8590 {
8591         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8592
8593         ixgbevf_dev_interrupt_get_status(dev);
8594         ixgbevf_dev_interrupt_action(dev);
8595 }
8596
8597 /**
8598  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8599  *  @hw: pointer to hardware structure
8600  *
8601  *  Stops the transmit data path and waits for the HW to internally empty
8602  *  the Tx security block
8603  **/
8604 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8605 {
8606 #define IXGBE_MAX_SECTX_POLL 40
8607
8608         int i;
8609         int sectxreg;
8610
8611         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8612         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8613         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8614         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8615                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8616                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8617                         break;
8618                 /* Use interrupt-safe sleep just in case */
8619                 usec_delay(1000);
8620         }
8621
8622         /* For informational purposes only */
8623         if (i >= IXGBE_MAX_SECTX_POLL)
8624                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8625                          "path fully disabled.  Continuing with init.");
8626
8627         return IXGBE_SUCCESS;
8628 }
8629
8630 /**
8631  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8632  *  @hw: pointer to hardware structure
8633  *
8634  *  Enables the transmit data path.
8635  **/
8636 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8637 {
8638         uint32_t sectxreg;
8639
8640         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8641         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8642         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8643         IXGBE_WRITE_FLUSH(hw);
8644
8645         return IXGBE_SUCCESS;
8646 }
8647
8648 /* restore n-tuple filter */
8649 static inline void
8650 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8651 {
8652         struct ixgbe_filter_info *filter_info =
8653                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8654         struct ixgbe_5tuple_filter *node;
8655
8656         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8657                 ixgbe_inject_5tuple_filter(dev, node);
8658         }
8659 }
8660
8661 /* restore ethernet type filter */
8662 static inline void
8663 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8664 {
8665         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8666         struct ixgbe_filter_info *filter_info =
8667                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8668         int i;
8669
8670         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8671                 if (filter_info->ethertype_mask & (1 << i)) {
8672                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8673                                         filter_info->ethertype_filters[i].etqf);
8674                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8675                                         filter_info->ethertype_filters[i].etqs);
8676                         IXGBE_WRITE_FLUSH(hw);
8677                 }
8678         }
8679 }
8680
8681 /* restore SYN filter */
8682 static inline void
8683 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8684 {
8685         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8686         struct ixgbe_filter_info *filter_info =
8687                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8688         uint32_t synqf;
8689
8690         synqf = filter_info->syn_info;
8691
8692         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8693                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8694                 IXGBE_WRITE_FLUSH(hw);
8695         }
8696 }
8697
8698 /* restore L2 tunnel filter */
8699 static inline void
8700 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8701 {
8702         struct ixgbe_l2_tn_info *l2_tn_info =
8703                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8704         struct ixgbe_l2_tn_filter *node;
8705         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8706
8707         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8708                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8709                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8710                 l2_tn_conf.pool           = node->pool;
8711                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8712         }
8713 }
8714
8715 /* restore rss filter */
8716 static inline void
8717 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8718 {
8719         struct ixgbe_filter_info *filter_info =
8720                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8721
8722         if (filter_info->rss_info.conf.queue_num)
8723                 ixgbe_config_rss_filter(dev,
8724                         &filter_info->rss_info, TRUE);
8725 }
8726
8727 static int
8728 ixgbe_filter_restore(struct rte_eth_dev *dev)
8729 {
8730         ixgbe_ntuple_filter_restore(dev);
8731         ixgbe_ethertype_filter_restore(dev);
8732         ixgbe_syn_filter_restore(dev);
8733         ixgbe_fdir_filter_restore(dev);
8734         ixgbe_l2_tn_filter_restore(dev);
8735         ixgbe_rss_filter_restore(dev);
8736
8737         return 0;
8738 }
8739
8740 static void
8741 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8742 {
8743         struct ixgbe_l2_tn_info *l2_tn_info =
8744                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8745         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8746
8747         if (l2_tn_info->e_tag_en)
8748                 (void)ixgbe_e_tag_enable(hw);
8749
8750         if (l2_tn_info->e_tag_fwd_en)
8751                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8752
8753         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8754 }
8755
8756 /* remove all the n-tuple filters */
8757 void
8758 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8759 {
8760         struct ixgbe_filter_info *filter_info =
8761                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8762         struct ixgbe_5tuple_filter *p_5tuple;
8763
8764         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8765                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8766 }
8767
8768 /* remove all the ether type filters */
8769 void
8770 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8771 {
8772         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8773         struct ixgbe_filter_info *filter_info =
8774                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8775         int i;
8776
8777         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8778                 if (filter_info->ethertype_mask & (1 << i) &&
8779                     !filter_info->ethertype_filters[i].conf) {
8780                         (void)ixgbe_ethertype_filter_remove(filter_info,
8781                                                             (uint8_t)i);
8782                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8783                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8784                         IXGBE_WRITE_FLUSH(hw);
8785                 }
8786         }
8787 }
8788
8789 /* remove the SYN filter */
8790 void
8791 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8792 {
8793         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8794         struct ixgbe_filter_info *filter_info =
8795                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8796
8797         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8798                 filter_info->syn_info = 0;
8799
8800                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8801                 IXGBE_WRITE_FLUSH(hw);
8802         }
8803 }
8804
8805 /* remove all the L2 tunnel filters */
8806 int
8807 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8808 {
8809         struct ixgbe_l2_tn_info *l2_tn_info =
8810                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8811         struct ixgbe_l2_tn_filter *l2_tn_filter;
8812         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8813         int ret = 0;
8814
8815         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8816                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8817                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8818                 l2_tn_conf.pool           = l2_tn_filter->pool;
8819                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8820                 if (ret < 0)
8821                         return ret;
8822         }
8823
8824         return 0;
8825 }
8826
8827 void
8828 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8829                                 struct ixgbe_macsec_setting *macsec_setting)
8830 {
8831         struct ixgbe_macsec_setting *macsec =
8832                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8833
8834         macsec->encrypt_en = macsec_setting->encrypt_en;
8835         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8836 }
8837
8838 void
8839 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8840 {
8841         struct ixgbe_macsec_setting *macsec =
8842                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8843
8844         macsec->encrypt_en = 0;
8845         macsec->replayprotect_en = 0;
8846 }
8847
8848 void
8849 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8850                                 struct ixgbe_macsec_setting *macsec_setting)
8851 {
8852         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8853         uint32_t ctrl;
8854         uint8_t en = macsec_setting->encrypt_en;
8855         uint8_t rp = macsec_setting->replayprotect_en;
8856
8857         /**
8858          * Workaround:
8859          * As no ixgbe_disable_sec_rx_path equivalent is
8860          * implemented for tx in the base code, and we are
8861          * not allowed to modify the base code in DPDK, so
8862          * just call the hand-written one directly for now.
8863          * The hardware support has been checked by
8864          * ixgbe_disable_sec_rx_path().
8865          */
8866         ixgbe_disable_sec_tx_path_generic(hw);
8867
8868         /* Enable Ethernet CRC (required by MACsec offload) */
8869         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8870         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8871         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8872
8873         /* Enable the TX and RX crypto engines */
8874         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8875         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8876         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8877
8878         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8879         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8880         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8881
8882         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8883         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8884         ctrl |= 0x3;
8885         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8886
8887         /* Enable SA lookup */
8888         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8889         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8890         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8891                      IXGBE_LSECTXCTRL_AUTH;
8892         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8893         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8894         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8895         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8896
8897         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8898         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8899         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8900         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8901         if (rp)
8902                 ctrl |= IXGBE_LSECRXCTRL_RP;
8903         else
8904                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8905         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8906
8907         /* Start the data paths */
8908         ixgbe_enable_sec_rx_path(hw);
8909         /**
8910          * Workaround:
8911          * As no ixgbe_enable_sec_rx_path equivalent is
8912          * implemented for tx in the base code, and we are
8913          * not allowed to modify the base code in DPDK, so
8914          * just call the hand-written one directly for now.
8915          */
8916         ixgbe_enable_sec_tx_path_generic(hw);
8917 }
8918
8919 void
8920 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
8921 {
8922         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8923         uint32_t ctrl;
8924
8925         /**
8926          * Workaround:
8927          * As no ixgbe_disable_sec_rx_path equivalent is
8928          * implemented for tx in the base code, and we are
8929          * not allowed to modify the base code in DPDK, so
8930          * just call the hand-written one directly for now.
8931          * The hardware support has been checked by
8932          * ixgbe_disable_sec_rx_path().
8933          */
8934         ixgbe_disable_sec_tx_path_generic(hw);
8935
8936         /* Disable the TX and RX crypto engines */
8937         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8938         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8939         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8940
8941         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8942         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8943         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8944
8945         /* Disable SA lookup */
8946         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8947         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8948         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8949         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8950
8951         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8952         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8953         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8954         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8955
8956         /* Start the data paths */
8957         ixgbe_enable_sec_rx_path(hw);
8958         /**
8959          * Workaround:
8960          * As no ixgbe_enable_sec_rx_path equivalent is
8961          * implemented for tx in the base code, and we are
8962          * not allowed to modify the base code in DPDK, so
8963          * just call the hand-written one directly for now.
8964          */
8965         ixgbe_enable_sec_tx_path_generic(hw);
8966 }
8967
8968 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8969 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8970 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8971 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8972 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8973 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8974 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
8975                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
8976
8977 RTE_INIT(ixgbe_init_log)
8978 {
8979         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8980         if (ixgbe_logtype_init >= 0)
8981                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8982         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8983         if (ixgbe_logtype_driver >= 0)
8984                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8985 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
8986         ixgbe_logtype_rx = rte_log_register("pmd.net.ixgbe.rx");
8987         if (ixgbe_logtype_rx >= 0)
8988                 rte_log_set_level(ixgbe_logtype_rx, RTE_LOG_DEBUG);
8989 #endif
8990
8991 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
8992         ixgbe_logtype_tx = rte_log_register("pmd.net.ixgbe.tx");
8993         if (ixgbe_logtype_tx >= 0)
8994                 rte_log_set_level(ixgbe_logtype_tx, RTE_LOG_DEBUG);
8995 #endif
8996
8997 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
8998         ixgbe_logtype_tx_free = rte_log_register("pmd.net.ixgbe.tx_free");
8999         if (ixgbe_logtype_tx_free >= 0)
9000                 rte_log_set_level(ixgbe_logtype_tx_free, RTE_LOG_DEBUG);
9001 #endif
9002 }