drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 #include "rte_pmd_ixgbe.h"
  76
  77 /*
  78  * High threshold controlling when to start sending XOFF frames. Must be at
  79  * least 8 bytes less than receive packet buffer size. This value is in units
  80  * of 1024 bytes.
  81  */
  82 #define IXGBE_FC_HI    0x80
  83
  84 /*
  85  * Low threshold controlling when to start sending XON frames. This value is
  86  * in units of 1024 bytes.
  87  */
  88 #define IXGBE_FC_LO    0x40
  89
  90 /* Default minimum inter-interrupt interval for EITR configuration */
  91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  92
  93 /* Timer value included in XOFF frames. */
  94 #define IXGBE_FC_PAUSE 0x680
  95
  96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  97 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  98 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  99
 100 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 101 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 102 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 103
 104 /*
 105  *  Default values for RX/TX configuration
 106  */
 107 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 108 #define IXGBE_DEFAULT_RX_PTHRESH      8
 109 #define IXGBE_DEFAULT_RX_HTHRESH      8
 110 #define IXGBE_DEFAULT_RX_WTHRESH      0
 111
 112 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 113 #define IXGBE_DEFAULT_TX_PTHRESH      32
 114 #define IXGBE_DEFAULT_TX_HTHRESH      0
 115 #define IXGBE_DEFAULT_TX_WTHRESH      0
 116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 117
 118 /* Bit shift and mask */
 119 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 120 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 121 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 122 #define IXGBE_8_BIT_MASK   UINT8_MAX
 123
 124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 125
 126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 127
 128 #define IXGBE_HKEY_MAX_INDEX 10
 129
 130 /* Additional timesync values. */
 131 #define NSEC_PER_SEC             1000000000L
 132 #define IXGBE_INCVAL_10GB        0x66666666
 133 #define IXGBE_INCVAL_1GB         0x40000000
 134 #define IXGBE_INCVAL_100         0x50000000
 135 #define IXGBE_INCVAL_SHIFT_10GB  28
 136 #define IXGBE_INCVAL_SHIFT_1GB   24
 137 #define IXGBE_INCVAL_SHIFT_100   21
 138 #define IXGBE_INCVAL_SHIFT_82599 7
 139 #define IXGBE_INCPER_SHIFT_82599 24
 140
 141 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 142
 143 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 145 #define DEFAULT_ETAG_ETYPE                     0x893f
 146 #define IXGBE_ETAG_ETYPE                       0x00005084
 147 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 148 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 149 #define IXGBE_RAH_ADTYPE                       0x40000000
 150 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 151 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 154 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 155 #define IXGBE_VTEICR_MASK                      0x07
 156
 157 enum ixgbevf_xcast_modes {
 158         IXGBEVF_XCAST_MODE_NONE = 0,
 159         IXGBEVF_XCAST_MODE_MULTI,
 160         IXGBEVF_XCAST_MODE_ALLMULTI,
 161 };
 162
 163 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 164 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 165
 166 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 167 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 168 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 169 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 171 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 172 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 177 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 178 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 179                                 int wait_to_complete);
 180 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 181                                 struct rte_eth_stats *stats);
 182 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 183                                 struct rte_eth_xstat *xstats, unsigned n);
 184 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 185                                   struct rte_eth_xstat *xstats, unsigned n);
 186 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 187 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 188 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 189         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 190 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 191         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 192 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 193                                              uint16_t queue_id,
 194                                              uint8_t stat_idx,
 195                                              uint8_t is_rx);
 196 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 197                                struct rte_eth_dev_info *dev_info);
 198 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 199 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 200                                  struct rte_eth_dev_info *dev_info);
 201 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 202
 203 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 204                 uint16_t vlan_id, int on);
 205 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 206                                enum rte_vlan_type vlan_type,
 207                                uint16_t tpid_id);
 208 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 209                 uint16_t queue, bool on);
 210 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 211                 int on);
 212 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 213 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 214 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 215 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 216 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 217
 218 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 220 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 221                                struct rte_eth_fc_conf *fc_conf);
 222 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 223                                struct rte_eth_fc_conf *fc_conf);
 224 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 225                 struct rte_eth_pfc_conf *pfc_conf);
 226 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 227                         struct rte_eth_rss_reta_entry64 *reta_conf,
 228                         uint16_t reta_size);
 229 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 230                         struct rte_eth_rss_reta_entry64 *reta_conf,
 231                         uint16_t reta_size);
 232 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 233 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 234 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 235 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 236 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 237 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 238                                       struct rte_intr_handle *handle);
 239 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 240                 void *param);
 241 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 242 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 243                 uint32_t index, uint32_t pool);
 244 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 245 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 246                                            struct ether_addr *mac_addr);
 247 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 248
 249 /* For Virtual Function support */
 250 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 251 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 252 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 253 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 254 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 255 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 256 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 257 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 258 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 259                 struct rte_eth_stats *stats);
 260 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 262                 uint16_t vlan_id, int on);
 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 264                 uint16_t queue, int on);
 265 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 266 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 267 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 268                                             uint16_t queue_id);
 269 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 270                                              uint16_t queue_id);
 271 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 272                                  uint8_t queue, uint8_t msix_vector);
 273 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 274 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 275 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 276
 277 /* For Eth VMDQ APIs support */
 278 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 279                 ether_addr * mac_addr, uint8_t on);
 280 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 281 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 282                 uint16_t rx_mask, uint8_t on);
 283 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 284 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 285 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 286                 uint64_t pool_mask, uint8_t vlan_on);
 287 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 288                 struct rte_eth_mirror_conf *mirror_conf,
 289                 uint8_t rule_id, uint8_t on);
 290 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 291                 uint8_t rule_id);
 292 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 293                                           uint16_t queue_id);
 294 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 295                                            uint16_t queue_id);
 296 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 297                                uint8_t queue, uint8_t msix_vector);
 298 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 299
 300 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 301                 uint16_t queue_idx, uint16_t tx_rate);
 302 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 303                 uint16_t tx_rate, uint64_t q_msk);
 304
 305 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 306                                  struct ether_addr *mac_addr,
 307                                  uint32_t index, uint32_t pool);
 308 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 309 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 310                                              struct ether_addr *mac_addr);
 311 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 312                         struct rte_eth_syn_filter *filter,
 313                         bool add);
 314 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 315                         struct rte_eth_syn_filter *filter);
 316 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 317                         enum rte_filter_op filter_op,
 318                         void *arg);
 319 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 320                         struct ixgbe_5tuple_filter *filter);
 321 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 322                         struct ixgbe_5tuple_filter *filter);
 323 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 324                         struct rte_eth_ntuple_filter *filter,
 325                         bool add);
 326 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 327                                 enum rte_filter_op filter_op,
 328                                 void *arg);
 329 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 330                         struct rte_eth_ntuple_filter *filter);
 331 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 332                         struct rte_eth_ethertype_filter *filter,
 333                         bool add);
 334 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 335                                 enum rte_filter_op filter_op,
 336                                 void *arg);
 337 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 338                         struct rte_eth_ethertype_filter *filter);
 339 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 340                      enum rte_filter_type filter_type,
 341                      enum rte_filter_op filter_op,
 342                      void *arg);
 343 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 344
 345 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 346                                       struct ether_addr *mc_addr_set,
 347                                       uint32_t nb_mc_addr);
 348 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 349                                    struct rte_eth_dcb_info *dcb_info);
 350
 351 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 352 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 353                             struct rte_dev_reg_info *regs);
 354 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 355 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 356                                 struct rte_dev_eeprom_info *eeprom);
 357 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 358                                 struct rte_dev_eeprom_info *eeprom);
 359
 360 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 361 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 362                                 struct rte_dev_reg_info *regs);
 363
 364 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 365 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 366 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 367                                             struct timespec *timestamp,
 368                                             uint32_t flags);
 369 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 370                                             struct timespec *timestamp);
 371 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 372 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 373                                    struct timespec *timestamp);
 374 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 375                                    const struct timespec *timestamp);
 376 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 377                                           void *param);
 378
 379 static int ixgbe_dev_l2_tunnel_eth_type_conf
 380         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 381 static int ixgbe_dev_l2_tunnel_offload_set
 382         (struct rte_eth_dev *dev,
 383          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 384          uint32_t mask,
 385          uint8_t en);
 386 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 387                                              enum rte_filter_op filter_op,
 388                                              void *arg);
 389
 390 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 391                                          struct rte_eth_udp_tunnel *udp_tunnel);
 392 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 393                                          struct rte_eth_udp_tunnel *udp_tunnel);
 394
 395 /*
 396  * Define VF Stats MACRO for Non "cleared on read" register
 397  */
 398 #define UPDATE_VF_STAT(reg, last, cur)                          \
 399 {                                                               \
 400         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 401         cur += (latest - last) & UINT_MAX;                      \
 402         last = latest;                                          \
 403 }
 404
 405 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 406 {                                                                \
 407         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 408         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 409         u64 latest = ((new_msb << 32) | new_lsb);                \
 410         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 411         last = latest;                                           \
 412 }
 413
 414 #define IXGBE_SET_HWSTRIP(h, q) do {\
 415                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 416                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 417                 (h)->bitmap[idx] |= 1 << bit;\
 418         } while (0)
 419
 420 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 421                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 422                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 423                 (h)->bitmap[idx] &= ~(1 << bit);\
 424         } while (0)
 425
 426 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 427                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 428                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 429                 (r) = (h)->bitmap[idx] >> bit & 1;\
 430         } while (0)
 431
 432 /*
 433  * The set of PCI devices this driver supports
 434  */
 435 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 489 #ifdef RTE_NIC_BYPASS
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 491 #endif
 492         { .vendor_id = 0, /* sentinel */ },
 493 };
 494
 495 /*
 496  * The set of PCI devices this driver supports (for 82599 VF)
 497  */
 498 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 504         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 505         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 506         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 507         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 508         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 509         { .vendor_id = 0, /* sentinel */ },
 510 };
 511
 512 static const struct rte_eth_desc_lim rx_desc_lim = {
 513         .nb_max = IXGBE_MAX_RING_DESC,
 514         .nb_min = IXGBE_MIN_RING_DESC,
 515         .nb_align = IXGBE_RXD_ALIGN,
 516 };
 517
 518 static const struct rte_eth_desc_lim tx_desc_lim = {
 519         .nb_max = IXGBE_MAX_RING_DESC,
 520         .nb_min = IXGBE_MIN_RING_DESC,
 521         .nb_align = IXGBE_TXD_ALIGN,
 522         .nb_seg_max = IXGBE_TX_MAX_SEG,
 523         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 524 };
 525
 526 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 527         .dev_configure        = ixgbe_dev_configure,
 528         .dev_start            = ixgbe_dev_start,
 529         .dev_stop             = ixgbe_dev_stop,
 530         .dev_set_link_up    = ixgbe_dev_set_link_up,
 531         .dev_set_link_down  = ixgbe_dev_set_link_down,
 532         .dev_close            = ixgbe_dev_close,
 533         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 534         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 535         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 536         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 537         .link_update          = ixgbe_dev_link_update,
 538         .stats_get            = ixgbe_dev_stats_get,
 539         .xstats_get           = ixgbe_dev_xstats_get,
 540         .stats_reset          = ixgbe_dev_stats_reset,
 541         .xstats_reset         = ixgbe_dev_xstats_reset,
 542         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 543         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 544         .dev_infos_get        = ixgbe_dev_info_get,
 545         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 546         .mtu_set              = ixgbe_dev_mtu_set,
 547         .vlan_filter_set      = ixgbe_vlan_filter_set,
 548         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 549         .vlan_offload_set     = ixgbe_vlan_offload_set,
 550         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 551         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 552         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 553         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 554         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 555         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 556         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 557         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 558         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 559         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 560         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 561         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 562         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 563         .dev_led_on           = ixgbe_dev_led_on,
 564         .dev_led_off          = ixgbe_dev_led_off,
 565         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 566         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 567         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 568         .mac_addr_add         = ixgbe_add_rar,
 569         .mac_addr_remove      = ixgbe_remove_rar,
 570         .mac_addr_set         = ixgbe_set_default_mac_addr,
 571         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 572         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 573         .mirror_rule_set      = ixgbe_mirror_rule_set,
 574         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 575         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 576         .set_vf_rx            = ixgbe_set_pool_rx,
 577         .set_vf_tx            = ixgbe_set_pool_tx,
 578         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 579         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 580         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 581         .reta_update          = ixgbe_dev_rss_reta_update,
 582         .reta_query           = ixgbe_dev_rss_reta_query,
 583 #ifdef RTE_NIC_BYPASS
 584         .bypass_init          = ixgbe_bypass_init,
 585         .bypass_state_set     = ixgbe_bypass_state_store,
 586         .bypass_state_show    = ixgbe_bypass_state_show,
 587         .bypass_event_set     = ixgbe_bypass_event_store,
 588         .bypass_event_show    = ixgbe_bypass_event_show,
 589         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 590         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 591         .bypass_ver_show      = ixgbe_bypass_ver_show,
 592         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 593 #endif /* RTE_NIC_BYPASS */
 594         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 595         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 596         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 597         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 598         .rxq_info_get         = ixgbe_rxq_info_get,
 599         .txq_info_get         = ixgbe_txq_info_get,
 600         .timesync_enable      = ixgbe_timesync_enable,
 601         .timesync_disable     = ixgbe_timesync_disable,
 602         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 603         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 604         .get_reg              = ixgbe_get_regs,
 605         .get_eeprom_length    = ixgbe_get_eeprom_length,
 606         .get_eeprom           = ixgbe_get_eeprom,
 607         .set_eeprom           = ixgbe_set_eeprom,
 608         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 609         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 610         .timesync_read_time   = ixgbe_timesync_read_time,
 611         .timesync_write_time  = ixgbe_timesync_write_time,
 612         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 613         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 614         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 615         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 616 };
 617
 618 /*
 619  * dev_ops for virtual function, bare necessities for basic vf
 620  * operation have been implemented
 621  */
 622 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 623         .dev_configure        = ixgbevf_dev_configure,
 624         .dev_start            = ixgbevf_dev_start,
 625         .dev_stop             = ixgbevf_dev_stop,
 626         .link_update          = ixgbe_dev_link_update,
 627         .stats_get            = ixgbevf_dev_stats_get,
 628         .xstats_get           = ixgbevf_dev_xstats_get,
 629         .stats_reset          = ixgbevf_dev_stats_reset,
 630         .xstats_reset         = ixgbevf_dev_stats_reset,
 631         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 632         .dev_close            = ixgbevf_dev_close,
 633         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 634         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 635         .dev_infos_get        = ixgbevf_dev_info_get,
 636         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 637         .mtu_set              = ixgbevf_dev_set_mtu,
 638         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 639         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 640         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 641         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 642         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 643         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 644         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 645         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 646         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 647         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 648         .mac_addr_add         = ixgbevf_add_mac_addr,
 649         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 650         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 651         .rxq_info_get         = ixgbe_rxq_info_get,
 652         .txq_info_get         = ixgbe_txq_info_get,
 653         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 654         .get_reg              = ixgbevf_get_regs,
 655         .reta_update          = ixgbe_dev_rss_reta_update,
 656         .reta_query           = ixgbe_dev_rss_reta_query,
 657         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 658         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 659 };
 660
 661 /* store statistics names and its offset in stats structure */
 662 struct rte_ixgbe_xstats_name_off {
 663         char name[RTE_ETH_XSTATS_NAME_SIZE];
 664         unsigned offset;
 665 };
 666
 667 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 668         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 669         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 670         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 671         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 672         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 673         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 674         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 675         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 676         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 677         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 678         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 679         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 680         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 681         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 682         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 683                 prc1023)},
 684         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 685                 prc1522)},
 686         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 687         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 688         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 689         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 690         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 691         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 692         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 693         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 694         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 695         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 696         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 697         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 698         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 699         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 700         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 701         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 702         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 703                 ptc1023)},
 704         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 705                 ptc1522)},
 706         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 707         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 708         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 709         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 710
 711         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 712                 fdirustat_add)},
 713         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 714                 fdirustat_remove)},
 715         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 716                 fdirfstat_fadd)},
 717         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 718                 fdirfstat_fremove)},
 719         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 720                 fdirmatch)},
 721         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 722                 fdirmiss)},
 723
 724         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 725         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 726         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 727                 fclast)},
 728         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 729         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 730         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 731         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 732         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 733                 fcoe_noddp)},
 734         {"rx_fcoe_no_direct_data_placement_ext_buff",
 735                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 736
 737         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 738                 lxontxc)},
 739         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 740                 lxonrxc)},
 741         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 742                 lxofftxc)},
 743         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 744                 lxoffrxc)},
 745         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 746 };
 747
 748 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 749                            sizeof(rte_ixgbe_stats_strings[0]))
 750
 751 /* MACsec statistics */
 752 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 753         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 754                 out_pkts_untagged)},
 755         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 756                 out_pkts_encrypted)},
 757         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 758                 out_pkts_protected)},
 759         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 760                 out_octets_encrypted)},
 761         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 762                 out_octets_protected)},
 763         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 764                 in_pkts_untagged)},
 765         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 766                 in_pkts_badtag)},
 767         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 768                 in_pkts_nosci)},
 769         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 770                 in_pkts_unknownsci)},
 771         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 772                 in_octets_decrypted)},
 773         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 774                 in_octets_validated)},
 775         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 776                 in_pkts_unchecked)},
 777         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 778                 in_pkts_delayed)},
 779         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 780                 in_pkts_late)},
 781         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 782                 in_pkts_ok)},
 783         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 784                 in_pkts_invalid)},
 785         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 786                 in_pkts_notvalid)},
 787         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 788                 in_pkts_unusedsa)},
 789         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 790                 in_pkts_notusingsa)},
 791 };
 792
 793 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 794                            sizeof(rte_ixgbe_macsec_strings[0]))
 795
 796 /* Per-queue statistics */
 797 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 798         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 799         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 800         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 801         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 802 };
 803
 804 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 805                            sizeof(rte_ixgbe_rxq_strings[0]))
 806 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 807
 808 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 809         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 810         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 811         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 812                 pxon2offc)},
 813 };
 814
 815 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 816                            sizeof(rte_ixgbe_txq_strings[0]))
 817 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 818
 819 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 820         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 821 };
 822
 823 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 824                 sizeof(rte_ixgbevf_stats_strings[0]))
 825
 826 /**
 827  * Atomically reads the link status information from global
 828  * structure rte_eth_dev.
 829  *
 830  * @param dev
 831  *   - Pointer to the structure rte_eth_dev to read from.
 832  *   - Pointer to the buffer to be saved with the link status.
 833  *
 834  * @return
 835  *   - On success, zero.
 836  *   - On failure, negative value.
 837  */
 838 static inline int
 839 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 840                                 struct rte_eth_link *link)
 841 {
 842         struct rte_eth_link *dst = link;
 843         struct rte_eth_link *src = &(dev->data->dev_link);
 844
 845         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 846                                         *(uint64_t *)src) == 0)
 847                 return -1;
 848
 849         return 0;
 850 }
 851
 852 /**
 853  * Atomically writes the link status information into global
 854  * structure rte_eth_dev.
 855  *
 856  * @param dev
 857  *   - Pointer to the structure rte_eth_dev to read from.
 858  *   - Pointer to the buffer to be saved with the link status.
 859  *
 860  * @return
 861  *   - On success, zero.
 862  *   - On failure, negative value.
 863  */
 864 static inline int
 865 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 866                                 struct rte_eth_link *link)
 867 {
 868         struct rte_eth_link *dst = &(dev->data->dev_link);
 869         struct rte_eth_link *src = link;
 870
 871         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 872                                         *(uint64_t *)src) == 0)
 873                 return -1;
 874
 875         return 0;
 876 }
 877
 878 /*
 879  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 880  */
 881 static inline int
 882 ixgbe_is_sfp(struct ixgbe_hw *hw)
 883 {
 884         switch (hw->phy.type) {
 885         case ixgbe_phy_sfp_avago:
 886         case ixgbe_phy_sfp_ftl:
 887         case ixgbe_phy_sfp_intel:
 888         case ixgbe_phy_sfp_unknown:
 889         case ixgbe_phy_sfp_passive_tyco:
 890         case ixgbe_phy_sfp_passive_unknown:
 891                 return 1;
 892         default:
 893                 return 0;
 894         }
 895 }
 896
 897 static inline int32_t
 898 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 899 {
 900         uint32_t ctrl_ext;
 901         int32_t status;
 902
 903         status = ixgbe_reset_hw(hw);
 904
 905         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 906         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 907         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 908         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 909         IXGBE_WRITE_FLUSH(hw);
 910
 911         return status;
 912 }
 913
 914 static inline void
 915 ixgbe_enable_intr(struct rte_eth_dev *dev)
 916 {
 917         struct ixgbe_interrupt *intr =
 918                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 919         struct ixgbe_hw *hw =
 920                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 921
 922         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 923         IXGBE_WRITE_FLUSH(hw);
 924 }
 925
 926 /*
 927  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 928  */
 929 static void
 930 ixgbe_disable_intr(struct ixgbe_hw *hw)
 931 {
 932         PMD_INIT_FUNC_TRACE();
 933
 934         if (hw->mac.type == ixgbe_mac_82598EB) {
 935                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 936         } else {
 937                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 938                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 939                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 940         }
 941         IXGBE_WRITE_FLUSH(hw);
 942 }
 943
 944 /*
 945  * This function resets queue statistics mapping registers.
 946  * From Niantic datasheet, Initialization of Statistics section:
 947  * "...if software requires the queue counters, the RQSMR and TQSM registers
 948  * must be re-programmed following a device reset.
 949  */
 950 static void
 951 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 952 {
 953         uint32_t i;
 954
 955         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 956                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 957                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 958         }
 959 }
 960
 961
 962 static int
 963 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 964                                   uint16_t queue_id,
 965                                   uint8_t stat_idx,
 966                                   uint8_t is_rx)
 967 {
 968 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 969 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 970 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 971
 972         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 973         struct ixgbe_stat_mapping_registers *stat_mappings =
 974                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 975         uint32_t qsmr_mask = 0;
 976         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 977         uint32_t q_map;
 978         uint8_t n, offset;
 979
 980         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 981                 (hw->mac.type != ixgbe_mac_X540) &&
 982                 (hw->mac.type != ixgbe_mac_X550) &&
 983                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 984                 (hw->mac.type != ixgbe_mac_X550EM_a))
 985                 return -ENOSYS;
 986
 987         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 988                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 989                      queue_id, stat_idx);
 990
 991         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 992         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 993                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 994                 return -EIO;
 995         }
 996         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 997
 998         /* Now clear any previous stat_idx set */
 999         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
1000         if (!is_rx)
1001                 stat_mappings->tqsm[n] &= ~clearing_mask;
1002         else
1003                 stat_mappings->rqsmr[n] &= ~clearing_mask;
1004
1005         q_map = (uint32_t)stat_idx;
1006         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
1007         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
1008         if (!is_rx)
1009                 stat_mappings->tqsm[n] |= qsmr_mask;
1010         else
1011                 stat_mappings->rqsmr[n] |= qsmr_mask;
1012
1013         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1014                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1015                      queue_id, stat_idx);
1016         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1017                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1018
1019         /* Now write the mapping in the appropriate register */
1020         if (is_rx) {
1021                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1022                              stat_mappings->rqsmr[n], n);
1023                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1024         } else {
1025                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1026                              stat_mappings->tqsm[n], n);
1027                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1028         }
1029         return 0;
1030 }
1031
1032 static void
1033 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1034 {
1035         struct ixgbe_stat_mapping_registers *stat_mappings =
1036                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1037         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1038         int i;
1039
1040         /* write whatever was in stat mapping table to the NIC */
1041         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1042                 /* rx */
1043                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1044
1045                 /* tx */
1046                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1047         }
1048 }
1049
1050 static void
1051 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1052 {
1053         uint8_t i;
1054         struct ixgbe_dcb_tc_config *tc;
1055         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1056
1057         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1058         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1059         for (i = 0; i < dcb_max_tc; i++) {
1060                 tc = &dcb_config->tc_config[i];
1061                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1062                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1063                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1064                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1065                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1066                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1067                 tc->pfc = ixgbe_dcb_pfc_disabled;
1068         }
1069
1070         /* Initialize default user to priority mapping, UPx->TC0 */
1071         tc = &dcb_config->tc_config[0];
1072         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1073         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1074         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1075                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1076                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1077         }
1078         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1079         dcb_config->pfc_mode_enable = false;
1080         dcb_config->vt_mode = true;
1081         dcb_config->round_robin_enable = false;
1082         /* support all DCB capabilities in 82599 */
1083         dcb_config->support.capabilities = 0xFF;
1084
1085         /*we only support 4 Tcs for X540, X550 */
1086         if (hw->mac.type == ixgbe_mac_X540 ||
1087                 hw->mac.type == ixgbe_mac_X550 ||
1088                 hw->mac.type == ixgbe_mac_X550EM_x ||
1089                 hw->mac.type == ixgbe_mac_X550EM_a) {
1090                 dcb_config->num_tcs.pg_tcs = 4;
1091                 dcb_config->num_tcs.pfc_tcs = 4;
1092         }
1093 }
1094
1095 /*
1096  * Ensure that all locks are released before first NVM or PHY access
1097  */
1098 static void
1099 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1100 {
1101         uint16_t mask;
1102
1103         /*
1104          * Phy lock should not fail in this early stage. If this is the case,
1105          * it is due to an improper exit of the application.
1106          * So force the release of the faulty lock. Release of common lock
1107          * is done automatically by swfw_sync function.
1108          */
1109         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1110         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1111                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1112         }
1113         ixgbe_release_swfw_semaphore(hw, mask);
1114
1115         /*
1116          * These ones are more tricky since they are common to all ports; but
1117          * swfw_sync retries last long enough (1s) to be almost sure that if
1118          * lock can not be taken it is due to an improper lock of the
1119          * semaphore.
1120          */
1121         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1122         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1123                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1124         }
1125         ixgbe_release_swfw_semaphore(hw, mask);
1126 }
1127
1128 /*
1129  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1130  * It returns 0 on success.
1131  */
1132 static int
1133 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1134 {
1135         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1136         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1137         struct ixgbe_hw *hw =
1138                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1139         struct ixgbe_vfta *shadow_vfta =
1140                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1141         struct ixgbe_hwstrip *hwstrip =
1142                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1143         struct ixgbe_dcb_config *dcb_config =
1144                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1145         struct ixgbe_filter_info *filter_info =
1146                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1147         uint32_t ctrl_ext;
1148         uint16_t csum;
1149         int diag, i;
1150
1151         PMD_INIT_FUNC_TRACE();
1152
1153         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1154         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1155         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1156         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1157
1158         /*
1159          * For secondary processes, we don't initialise any further as primary
1160          * has already done this work. Only check we don't need a different
1161          * RX and TX function.
1162          */
1163         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1164                 struct ixgbe_tx_queue *txq;
1165                 /* TX queue function in primary, set by last queue initialized
1166                  * Tx queue may not initialized by primary process
1167                  */
1168                 if (eth_dev->data->tx_queues) {
1169                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1170                         ixgbe_set_tx_function(eth_dev, txq);
1171                 } else {
1172                         /* Use default TX function if we get here */
1173                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1174                                      "Using default TX function.");
1175                 }
1176
1177                 ixgbe_set_rx_function(eth_dev);
1178
1179                 return 0;
1180         }
1181
1182         rte_eth_copy_pci_info(eth_dev, pci_dev);
1183         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1184
1185         /* Vendor and Device ID need to be set before init of shared code */
1186         hw->device_id = pci_dev->id.device_id;
1187         hw->vendor_id = pci_dev->id.vendor_id;
1188         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1189         hw->allow_unsupported_sfp = 1;
1190
1191         /* Initialize the shared code (base driver) */
1192 #ifdef RTE_NIC_BYPASS
1193         diag = ixgbe_bypass_init_shared_code(hw);
1194 #else
1195         diag = ixgbe_init_shared_code(hw);
1196 #endif /* RTE_NIC_BYPASS */
1197
1198         if (diag != IXGBE_SUCCESS) {
1199                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1200                 return -EIO;
1201         }
1202
1203         /* pick up the PCI bus settings for reporting later */
1204         ixgbe_get_bus_info(hw);
1205
1206         /* Unlock any pending hardware semaphore */
1207         ixgbe_swfw_lock_reset(hw);
1208
1209         /* Initialize DCB configuration*/
1210         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1211         ixgbe_dcb_init(hw, dcb_config);
1212         /* Get Hardware Flow Control setting */
1213         hw->fc.requested_mode = ixgbe_fc_full;
1214         hw->fc.current_mode = ixgbe_fc_full;
1215         hw->fc.pause_time = IXGBE_FC_PAUSE;
1216         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1217                 hw->fc.low_water[i] = IXGBE_FC_LO;
1218                 hw->fc.high_water[i] = IXGBE_FC_HI;
1219         }
1220         hw->fc.send_xon = 1;
1221
1222         /* Make sure we have a good EEPROM before we read from it */
1223         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1224         if (diag != IXGBE_SUCCESS) {
1225                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1226                 return -EIO;
1227         }
1228
1229 #ifdef RTE_NIC_BYPASS
1230         diag = ixgbe_bypass_init_hw(hw);
1231 #else
1232         diag = ixgbe_init_hw(hw);
1233 #endif /* RTE_NIC_BYPASS */
1234
1235         /*
1236          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1237          * is called too soon after the kernel driver unbinding/binding occurs.
1238          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1239          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1240          * also called. See ixgbe_identify_phy_82599(). The reason for the
1241          * failure is not known, and only occuts when virtualisation features
1242          * are disabled in the bios. A delay of 100ms  was found to be enough by
1243          * trial-and-error, and is doubled to be safe.
1244          */
1245         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1246                 rte_delay_ms(200);
1247                 diag = ixgbe_init_hw(hw);
1248         }
1249
1250         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1251                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1252                              "LOM.  Please be aware there may be issues associated "
1253                              "with your hardware.");
1254                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1255                              "please contact your Intel or hardware representative "
1256                              "who provided you with this hardware.");
1257         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1258                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1259         if (diag) {
1260                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1261                 return -EIO;
1262         }
1263
1264         /* Reset the hw statistics */
1265         ixgbe_dev_stats_reset(eth_dev);
1266
1267         /* disable interrupt */
1268         ixgbe_disable_intr(hw);
1269
1270         /* reset mappings for queue statistics hw counters*/
1271         ixgbe_reset_qstat_mappings(hw);
1272
1273         /* Allocate memory for storing MAC addresses */
1274         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1275                                                hw->mac.num_rar_entries, 0);
1276         if (eth_dev->data->mac_addrs == NULL) {
1277                 PMD_INIT_LOG(ERR,
1278                              "Failed to allocate %u bytes needed to store "
1279                              "MAC addresses",
1280                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1281                 return -ENOMEM;
1282         }
1283         /* Copy the permanent MAC address */
1284         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1285                         &eth_dev->data->mac_addrs[0]);
1286
1287         /* Allocate memory for storing hash filter MAC addresses */
1288         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1289                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1290         if (eth_dev->data->hash_mac_addrs == NULL) {
1291                 PMD_INIT_LOG(ERR,
1292                              "Failed to allocate %d bytes needed to store MAC addresses",
1293                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1294                 return -ENOMEM;
1295         }
1296
1297         /* initialize the vfta */
1298         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1299
1300         /* initialize the hw strip bitmap*/
1301         memset(hwstrip, 0, sizeof(*hwstrip));
1302
1303         /* initialize PF if max_vfs not zero */
1304         ixgbe_pf_host_init(eth_dev);
1305
1306         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1307         /* let hardware know driver is loaded */
1308         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1309         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1310         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1311         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1312         IXGBE_WRITE_FLUSH(hw);
1313
1314         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1315                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1316                              (int) hw->mac.type, (int) hw->phy.type,
1317                              (int) hw->phy.sfp_type);
1318         else
1319                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1320                              (int) hw->mac.type, (int) hw->phy.type);
1321
1322         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1323                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1324                      pci_dev->id.device_id);
1325
1326         rte_intr_callback_register(intr_handle,
1327                                    ixgbe_dev_interrupt_handler, eth_dev);
1328
1329         /* enable uio/vfio intr/eventfd mapping */
1330         rte_intr_enable(intr_handle);
1331
1332         /* enable support intr */
1333         ixgbe_enable_intr(eth_dev);
1334
1335         /* initialize 5tuple filter list */
1336         TAILQ_INIT(&filter_info->fivetuple_list);
1337         memset(filter_info->fivetuple_mask, 0,
1338                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1339
1340         return 0;
1341 }
1342
1343 static int
1344 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1345 {
1346         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1347         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1348         struct ixgbe_hw *hw;
1349
1350         PMD_INIT_FUNC_TRACE();
1351
1352         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1353                 return -EPERM;
1354
1355         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1356
1357         if (hw->adapter_stopped == 0)
1358                 ixgbe_dev_close(eth_dev);
1359
1360         eth_dev->dev_ops = NULL;
1361         eth_dev->rx_pkt_burst = NULL;
1362         eth_dev->tx_pkt_burst = NULL;
1363
1364         /* Unlock any pending hardware semaphore */
1365         ixgbe_swfw_lock_reset(hw);
1366
1367         /* disable uio intr before callback unregister */
1368         rte_intr_disable(intr_handle);
1369         rte_intr_callback_unregister(intr_handle,
1370                                      ixgbe_dev_interrupt_handler, eth_dev);
1371
1372         /* uninitialize PF if max_vfs not zero */
1373         ixgbe_pf_host_uninit(eth_dev);
1374
1375         rte_free(eth_dev->data->mac_addrs);
1376         eth_dev->data->mac_addrs = NULL;
1377
1378         rte_free(eth_dev->data->hash_mac_addrs);
1379         eth_dev->data->hash_mac_addrs = NULL;
1380
1381         return 0;
1382 }
1383
1384 /*
1385  * Negotiate mailbox API version with the PF.
1386  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1387  * Then we try to negotiate starting with the most recent one.
1388  * If all negotiation attempts fail, then we will proceed with
1389  * the default one (ixgbe_mbox_api_10).
1390  */
1391 static void
1392 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1393 {
1394         int32_t i;
1395
1396         /* start with highest supported, proceed down */
1397         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1398                 ixgbe_mbox_api_12,
1399                 ixgbe_mbox_api_11,
1400                 ixgbe_mbox_api_10,
1401         };
1402
1403         for (i = 0;
1404                         i != RTE_DIM(sup_ver) &&
1405                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1406                         i++)
1407                 ;
1408 }
1409
1410 static void
1411 generate_random_mac_addr(struct ether_addr *mac_addr)
1412 {
1413         uint64_t random;
1414
1415         /* Set Organizationally Unique Identifier (OUI) prefix. */
1416         mac_addr->addr_bytes[0] = 0x00;
1417         mac_addr->addr_bytes[1] = 0x09;
1418         mac_addr->addr_bytes[2] = 0xC0;
1419         /* Force indication of locally assigned MAC address. */
1420         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1421         /* Generate the last 3 bytes of the MAC address with a random number. */
1422         random = rte_rand();
1423         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1424 }
1425
1426 /*
1427  * Virtual Function device init
1428  */
1429 static int
1430 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1431 {
1432         int diag;
1433         uint32_t tc, tcs;
1434         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1435         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1436         struct ixgbe_hw *hw =
1437                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1438         struct ixgbe_vfta *shadow_vfta =
1439                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1440         struct ixgbe_hwstrip *hwstrip =
1441                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1442         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1443
1444         PMD_INIT_FUNC_TRACE();
1445
1446         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1447         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1448         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1449
1450         /* for secondary processes, we don't initialise any further as primary
1451          * has already done this work. Only check we don't need a different
1452          * RX function
1453          */
1454         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1455                 struct ixgbe_tx_queue *txq;
1456                 /* TX queue function in primary, set by last queue initialized
1457                  * Tx queue may not initialized by primary process
1458                  */
1459                 if (eth_dev->data->tx_queues) {
1460                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1461                         ixgbe_set_tx_function(eth_dev, txq);
1462                 } else {
1463                         /* Use default TX function if we get here */
1464                         PMD_INIT_LOG(NOTICE,
1465                                      "No TX queues configured yet. Using default TX function.");
1466                 }
1467
1468                 ixgbe_set_rx_function(eth_dev);
1469
1470                 return 0;
1471         }
1472
1473         rte_eth_copy_pci_info(eth_dev, pci_dev);
1474         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1475
1476         hw->device_id = pci_dev->id.device_id;
1477         hw->vendor_id = pci_dev->id.vendor_id;
1478         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1479
1480         /* initialize the vfta */
1481         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1482
1483         /* initialize the hw strip bitmap*/
1484         memset(hwstrip, 0, sizeof(*hwstrip));
1485
1486         /* Initialize the shared code (base driver) */
1487         diag = ixgbe_init_shared_code(hw);
1488         if (diag != IXGBE_SUCCESS) {
1489                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1490                 return -EIO;
1491         }
1492
1493         /* init_mailbox_params */
1494         hw->mbx.ops.init_params(hw);
1495
1496         /* Reset the hw statistics */
1497         ixgbevf_dev_stats_reset(eth_dev);
1498
1499         /* Disable the interrupts for VF */
1500         ixgbevf_intr_disable(hw);
1501
1502         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1503         diag = hw->mac.ops.reset_hw(hw);
1504
1505         /*
1506          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1507          * the underlying PF driver has not assigned a MAC address to the VF.
1508          * In this case, assign a random MAC address.
1509          */
1510         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1511                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1512                 return diag;
1513         }
1514
1515         /* negotiate mailbox API version to use with the PF. */
1516         ixgbevf_negotiate_api(hw);
1517
1518         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1519         ixgbevf_get_queues(hw, &tcs, &tc);
1520
1521         /* Allocate memory for storing MAC addresses */
1522         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1523                                                hw->mac.num_rar_entries, 0);
1524         if (eth_dev->data->mac_addrs == NULL) {
1525                 PMD_INIT_LOG(ERR,
1526                              "Failed to allocate %u bytes needed to store "
1527                              "MAC addresses",
1528                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1529                 return -ENOMEM;
1530         }
1531
1532         /* Generate a random MAC address, if none was assigned by PF. */
1533         if (is_zero_ether_addr(perm_addr)) {
1534                 generate_random_mac_addr(perm_addr);
1535                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1536                 if (diag) {
1537                         rte_free(eth_dev->data->mac_addrs);
1538                         eth_dev->data->mac_addrs = NULL;
1539                         return diag;
1540                 }
1541                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1542                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1543                              "%02x:%02x:%02x:%02x:%02x:%02x",
1544                              perm_addr->addr_bytes[0],
1545                              perm_addr->addr_bytes[1],
1546                              perm_addr->addr_bytes[2],
1547                              perm_addr->addr_bytes[3],
1548                              perm_addr->addr_bytes[4],
1549                              perm_addr->addr_bytes[5]);
1550         }
1551
1552         /* Copy the permanent MAC address */
1553         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1554
1555         /* reset the hardware with the new settings */
1556         diag = hw->mac.ops.start_hw(hw);
1557         switch (diag) {
1558         case  0:
1559                 break;
1560
1561         default:
1562                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1563                 return -EIO;
1564         }
1565
1566         rte_intr_callback_register(intr_handle,
1567                                    ixgbevf_dev_interrupt_handler, eth_dev);
1568         rte_intr_enable(intr_handle);
1569         ixgbevf_intr_enable(hw);
1570
1571         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1572                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1573                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1574
1575         return 0;
1576 }
1577
1578 /* Virtual Function device uninit */
1579
1580 static int
1581 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1582 {
1583         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1584         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1585         struct ixgbe_hw *hw;
1586
1587         PMD_INIT_FUNC_TRACE();
1588
1589         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1590                 return -EPERM;
1591
1592         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1593
1594         if (hw->adapter_stopped == 0)
1595                 ixgbevf_dev_close(eth_dev);
1596
1597         eth_dev->dev_ops = NULL;
1598         eth_dev->rx_pkt_burst = NULL;
1599         eth_dev->tx_pkt_burst = NULL;
1600
1601         /* Disable the interrupts for VF */
1602         ixgbevf_intr_disable(hw);
1603
1604         rte_free(eth_dev->data->mac_addrs);
1605         eth_dev->data->mac_addrs = NULL;
1606
1607         rte_intr_disable(intr_handle);
1608         rte_intr_callback_unregister(intr_handle,
1609                                      ixgbevf_dev_interrupt_handler, eth_dev);
1610
1611         return 0;
1612 }
1613
1614 static struct eth_driver rte_ixgbe_pmd = {
1615         .pci_drv = {
1616                 .id_table = pci_id_ixgbe_map,
1617                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1618                 .probe = rte_eth_dev_pci_probe,
1619                 .remove = rte_eth_dev_pci_remove,
1620         },
1621         .eth_dev_init = eth_ixgbe_dev_init,
1622         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1623         .dev_private_size = sizeof(struct ixgbe_adapter),
1624 };
1625
1626 /*
1627  * virtual function driver struct
1628  */
1629 static struct eth_driver rte_ixgbevf_pmd = {
1630         .pci_drv = {
1631                 .id_table = pci_id_ixgbevf_map,
1632                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1633                 .probe = rte_eth_dev_pci_probe,
1634                 .remove = rte_eth_dev_pci_remove,
1635         },
1636         .eth_dev_init = eth_ixgbevf_dev_init,
1637         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1638         .dev_private_size = sizeof(struct ixgbe_adapter),
1639 };
1640
1641 static int
1642 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1643 {
1644         struct ixgbe_hw *hw =
1645                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1646         struct ixgbe_vfta *shadow_vfta =
1647                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1648         uint32_t vfta;
1649         uint32_t vid_idx;
1650         uint32_t vid_bit;
1651
1652         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1653         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1654         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1655         if (on)
1656                 vfta |= vid_bit;
1657         else
1658                 vfta &= ~vid_bit;
1659         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1660
1661         /* update local VFTA copy */
1662         shadow_vfta->vfta[vid_idx] = vfta;
1663
1664         return 0;
1665 }
1666
1667 static void
1668 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1669 {
1670         if (on)
1671                 ixgbe_vlan_hw_strip_enable(dev, queue);
1672         else
1673                 ixgbe_vlan_hw_strip_disable(dev, queue);
1674 }
1675
1676 static int
1677 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1678                     enum rte_vlan_type vlan_type,
1679                     uint16_t tpid)
1680 {
1681         struct ixgbe_hw *hw =
1682                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1683         int ret = 0;
1684         uint32_t reg;
1685         uint32_t qinq;
1686
1687         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1688         qinq &= IXGBE_DMATXCTL_GDV;
1689
1690         switch (vlan_type) {
1691         case ETH_VLAN_TYPE_INNER:
1692                 if (qinq) {
1693                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1694                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1695                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1696                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1697                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1698                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1699                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1700                 } else {
1701                         ret = -ENOTSUP;
1702                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1703                                     " by single VLAN");
1704                 }
1705                 break;
1706         case ETH_VLAN_TYPE_OUTER:
1707                 if (qinq) {
1708                         /* Only the high 16-bits is valid */
1709                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1710                                         IXGBE_EXVET_VET_EXT_SHIFT);
1711                 } else {
1712                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1713                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1714                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1715                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1716                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1717                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1718                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1719                 }
1720
1721                 break;
1722         default:
1723                 ret = -EINVAL;
1724                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1725                 break;
1726         }
1727
1728         return ret;
1729 }
1730
1731 void
1732 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1733 {
1734         struct ixgbe_hw *hw =
1735                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1736         uint32_t vlnctrl;
1737
1738         PMD_INIT_FUNC_TRACE();
1739
1740         /* Filter Table Disable */
1741         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1742         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1743
1744         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1745 }
1746
1747 void
1748 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1749 {
1750         struct ixgbe_hw *hw =
1751                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1752         struct ixgbe_vfta *shadow_vfta =
1753                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1754         uint32_t vlnctrl;
1755         uint16_t i;
1756
1757         PMD_INIT_FUNC_TRACE();
1758
1759         /* Filter Table Enable */
1760         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1761         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1762         vlnctrl |= IXGBE_VLNCTRL_VFE;
1763
1764         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1765
1766         /* write whatever is in local vfta copy */
1767         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1768                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1769 }
1770
1771 static void
1772 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1773 {
1774         struct ixgbe_hwstrip *hwstrip =
1775                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1776         struct ixgbe_rx_queue *rxq;
1777
1778         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1779                 return;
1780
1781         if (on)
1782                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1783         else
1784                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1785
1786         if (queue >= dev->data->nb_rx_queues)
1787                 return;
1788
1789         rxq = dev->data->rx_queues[queue];
1790
1791         if (on)
1792                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1793         else
1794                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1795 }
1796
1797 static void
1798 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1799 {
1800         struct ixgbe_hw *hw =
1801                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1802         uint32_t ctrl;
1803
1804         PMD_INIT_FUNC_TRACE();
1805
1806         if (hw->mac.type == ixgbe_mac_82598EB) {
1807                 /* No queue level support */
1808                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1809                 return;
1810         }
1811
1812         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1813         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1814         ctrl &= ~IXGBE_RXDCTL_VME;
1815         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1816
1817         /* record those setting for HW strip per queue */
1818         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1819 }
1820
1821 static void
1822 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1823 {
1824         struct ixgbe_hw *hw =
1825                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1826         uint32_t ctrl;
1827
1828         PMD_INIT_FUNC_TRACE();
1829
1830         if (hw->mac.type == ixgbe_mac_82598EB) {
1831                 /* No queue level supported */
1832                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1833                 return;
1834         }
1835
1836         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1837         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1838         ctrl |= IXGBE_RXDCTL_VME;
1839         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1840
1841         /* record those setting for HW strip per queue */
1842         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1843 }
1844
1845 void
1846 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1847 {
1848         struct ixgbe_hw *hw =
1849                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1850         uint32_t ctrl;
1851         uint16_t i;
1852         struct ixgbe_rx_queue *rxq;
1853
1854         PMD_INIT_FUNC_TRACE();
1855
1856         if (hw->mac.type == ixgbe_mac_82598EB) {
1857                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1858                 ctrl &= ~IXGBE_VLNCTRL_VME;
1859                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1860         } else {
1861                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1862                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1863                         rxq = dev->data->rx_queues[i];
1864                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1865                         ctrl &= ~IXGBE_RXDCTL_VME;
1866                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1867
1868                         /* record those setting for HW strip per queue */
1869                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1870                 }
1871         }
1872 }
1873
1874 void
1875 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1876 {
1877         struct ixgbe_hw *hw =
1878                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1879         uint32_t ctrl;
1880         uint16_t i;
1881         struct ixgbe_rx_queue *rxq;
1882
1883         PMD_INIT_FUNC_TRACE();
1884
1885         if (hw->mac.type == ixgbe_mac_82598EB) {
1886                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1887                 ctrl |= IXGBE_VLNCTRL_VME;
1888                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1889         } else {
1890                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1891                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1892                         rxq = dev->data->rx_queues[i];
1893                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1894                         ctrl |= IXGBE_RXDCTL_VME;
1895                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1896
1897                         /* record those setting for HW strip per queue */
1898                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1899                 }
1900         }
1901 }
1902
1903 static void
1904 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1905 {
1906         struct ixgbe_hw *hw =
1907                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1908         uint32_t ctrl;
1909
1910         PMD_INIT_FUNC_TRACE();
1911
1912         /* DMATXCTRL: Geric Double VLAN Disable */
1913         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1914         ctrl &= ~IXGBE_DMATXCTL_GDV;
1915         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1916
1917         /* CTRL_EXT: Global Double VLAN Disable */
1918         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1919         ctrl &= ~IXGBE_EXTENDED_VLAN;
1920         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1921
1922 }
1923
1924 static void
1925 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1926 {
1927         struct ixgbe_hw *hw =
1928                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1929         uint32_t ctrl;
1930
1931         PMD_INIT_FUNC_TRACE();
1932
1933         /* DMATXCTRL: Geric Double VLAN Enable */
1934         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1935         ctrl |= IXGBE_DMATXCTL_GDV;
1936         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1937
1938         /* CTRL_EXT: Global Double VLAN Enable */
1939         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1940         ctrl |= IXGBE_EXTENDED_VLAN;
1941         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1942
1943         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1944         if (hw->mac.type == ixgbe_mac_X550 ||
1945             hw->mac.type == ixgbe_mac_X550EM_x ||
1946             hw->mac.type == ixgbe_mac_X550EM_a) {
1947                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1948                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1949                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1950         }
1951
1952         /*
1953          * VET EXT field in the EXVET register = 0x8100 by default
1954          * So no need to change. Same to VT field of DMATXCTL register
1955          */
1956 }
1957
1958 static void
1959 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1960 {
1961         if (mask & ETH_VLAN_STRIP_MASK) {
1962                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1963                         ixgbe_vlan_hw_strip_enable_all(dev);
1964                 else
1965                         ixgbe_vlan_hw_strip_disable_all(dev);
1966         }
1967
1968         if (mask & ETH_VLAN_FILTER_MASK) {
1969                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1970                         ixgbe_vlan_hw_filter_enable(dev);
1971                 else
1972                         ixgbe_vlan_hw_filter_disable(dev);
1973         }
1974
1975         if (mask & ETH_VLAN_EXTEND_MASK) {
1976                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1977                         ixgbe_vlan_hw_extend_enable(dev);
1978                 else
1979                         ixgbe_vlan_hw_extend_disable(dev);
1980         }
1981 }
1982
1983 static void
1984 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1985 {
1986         struct ixgbe_hw *hw =
1987                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1988         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1989         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1990
1991         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1992         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1993 }
1994
1995 static int
1996 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1997 {
1998         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
1999
2000         switch (nb_rx_q) {
2001         case 1:
2002         case 2:
2003                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2004                 break;
2005         case 4:
2006                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2007                 break;
2008         default:
2009                 return -EINVAL;
2010         }
2011
2012         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2013         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2014
2015         return 0;
2016 }
2017
2018 static int
2019 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2020 {
2021         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2022         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2023         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2024         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2025
2026         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2027                 /* check multi-queue mode */
2028                 switch (dev_conf->rxmode.mq_mode) {
2029                 case ETH_MQ_RX_VMDQ_DCB:
2030                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2031                         break;
2032                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2033                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2034                         PMD_INIT_LOG(ERR, "SRIOV active,"
2035                                         " unsupported mq_mode rx %d.",
2036                                         dev_conf->rxmode.mq_mode);
2037                         return -EINVAL;
2038                 case ETH_MQ_RX_RSS:
2039                 case ETH_MQ_RX_VMDQ_RSS:
2040                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2041                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2042                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2043                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2044                                                 " invalid queue number"
2045                                                 " for VMDQ RSS, allowed"
2046                                                 " value are 1, 2 or 4.");
2047                                         return -EINVAL;
2048                                 }
2049                         break;
2050                 case ETH_MQ_RX_VMDQ_ONLY:
2051                 case ETH_MQ_RX_NONE:
2052                         /* if nothing mq mode configure, use default scheme */
2053                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2054                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2055                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2056                         break;
2057                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2058                         /* SRIOV only works in VMDq enable mode */
2059                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2060                                         " wrong mq_mode rx %d.",
2061                                         dev_conf->rxmode.mq_mode);
2062                         return -EINVAL;
2063                 }
2064
2065                 switch (dev_conf->txmode.mq_mode) {
2066                 case ETH_MQ_TX_VMDQ_DCB:
2067                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2068                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2069                         break;
2070                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2071                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2072                         break;
2073                 }
2074
2075                 /* check valid queue number */
2076                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2077                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2078                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2079                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2080                                         " must be less than or equal to %d.",
2081                                         nb_rx_q, nb_tx_q,
2082                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2083                         return -EINVAL;
2084                 }
2085         } else {
2086                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2087                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2088                                           " not supported.");
2089                         return -EINVAL;
2090                 }
2091                 /* check configuration for vmdb+dcb mode */
2092                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2093                         const struct rte_eth_vmdq_dcb_conf *conf;
2094
2095                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2096                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2097                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2098                                 return -EINVAL;
2099                         }
2100                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2101                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2102                                conf->nb_queue_pools == ETH_32_POOLS)) {
2103                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2104                                                 " nb_queue_pools must be %d or %d.",
2105                                                 ETH_16_POOLS, ETH_32_POOLS);
2106                                 return -EINVAL;
2107                         }
2108                 }
2109                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2110                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2111
2112                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2113                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2114                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2115                                 return -EINVAL;
2116                         }
2117                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2118                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2119                                conf->nb_queue_pools == ETH_32_POOLS)) {
2120                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2121                                                 " nb_queue_pools != %d and"
2122                                                 " nb_queue_pools != %d.",
2123                                                 ETH_16_POOLS, ETH_32_POOLS);
2124                                 return -EINVAL;
2125                         }
2126                 }
2127
2128                 /* For DCB mode check our configuration before we go further */
2129                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2130                         const struct rte_eth_dcb_rx_conf *conf;
2131
2132                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2133                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2134                                                  IXGBE_DCB_NB_QUEUES);
2135                                 return -EINVAL;
2136                         }
2137                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2138                         if (!(conf->nb_tcs == ETH_4_TCS ||
2139                                conf->nb_tcs == ETH_8_TCS)) {
2140                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2141                                                 " and nb_tcs != %d.",
2142                                                 ETH_4_TCS, ETH_8_TCS);
2143                                 return -EINVAL;
2144                         }
2145                 }
2146
2147                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2148                         const struct rte_eth_dcb_tx_conf *conf;
2149
2150                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2151                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2152                                                  IXGBE_DCB_NB_QUEUES);
2153                                 return -EINVAL;
2154                         }
2155                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2156                         if (!(conf->nb_tcs == ETH_4_TCS ||
2157                                conf->nb_tcs == ETH_8_TCS)) {
2158                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2159                                                 " and nb_tcs != %d.",
2160                                                 ETH_4_TCS, ETH_8_TCS);
2161                                 return -EINVAL;
2162                         }
2163                 }
2164
2165                 /*
2166                  * When DCB/VT is off, maximum number of queues changes,
2167                  * except for 82598EB, which remains constant.
2168                  */
2169                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2170                                 hw->mac.type != ixgbe_mac_82598EB) {
2171                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2172                                 PMD_INIT_LOG(ERR,
2173                                              "Neither VT nor DCB are enabled, "
2174                                              "nb_tx_q > %d.",
2175                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2176                                 return -EINVAL;
2177                         }
2178                 }
2179         }
2180         return 0;
2181 }
2182
2183 static int
2184 ixgbe_dev_configure(struct rte_eth_dev *dev)
2185 {
2186         struct ixgbe_interrupt *intr =
2187                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2188         struct ixgbe_adapter *adapter =
2189                 (struct ixgbe_adapter *)dev->data->dev_private;
2190         int ret;
2191
2192         PMD_INIT_FUNC_TRACE();
2193         /* multipe queue mode checking */
2194         ret  = ixgbe_check_mq_mode(dev);
2195         if (ret != 0) {
2196                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2197                             ret);
2198                 return ret;
2199         }
2200
2201         /* set flag to update link status after init */
2202         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2203
2204         /*
2205          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2206          * allocation or vector Rx preconditions we will reset it.
2207          */
2208         adapter->rx_bulk_alloc_allowed = true;
2209         adapter->rx_vec_allowed = true;
2210
2211         return 0;
2212 }
2213
2214 static void
2215 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2216 {
2217         struct ixgbe_hw *hw =
2218                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2219         struct ixgbe_interrupt *intr =
2220                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2221         uint32_t gpie;
2222
2223         /* only set up it on X550EM_X */
2224         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2225                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2226                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2227                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2228                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2229                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2230         }
2231 }
2232
2233 /*
2234  * Configure device link speed and setup link.
2235  * It returns 0 on success.
2236  */
2237 static int
2238 ixgbe_dev_start(struct rte_eth_dev *dev)
2239 {
2240         struct ixgbe_hw *hw =
2241                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2242         struct ixgbe_vf_info *vfinfo =
2243                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2244         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2245         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2246         uint32_t intr_vector = 0;
2247         int err, link_up = 0, negotiate = 0;
2248         uint32_t speed = 0;
2249         int mask = 0;
2250         int status;
2251         uint16_t vf, idx;
2252         uint32_t *link_speeds;
2253
2254         PMD_INIT_FUNC_TRACE();
2255
2256         /* IXGBE devices don't support:
2257         *    - half duplex (checked afterwards for valid speeds)
2258         *    - fixed speed: TODO implement
2259         */
2260         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2261                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2262                              dev->data->port_id);
2263                 return -EINVAL;
2264         }
2265
2266         /* disable uio/vfio intr/eventfd mapping */
2267         rte_intr_disable(intr_handle);
2268
2269         /* stop adapter */
2270         hw->adapter_stopped = 0;
2271         ixgbe_stop_adapter(hw);
2272
2273         /* reinitialize adapter
2274          * this calls reset and start
2275          */
2276         status = ixgbe_pf_reset_hw(hw);
2277         if (status != 0)
2278                 return -1;
2279         hw->mac.ops.start_hw(hw);
2280         hw->mac.get_link_status = true;
2281
2282         /* configure PF module if SRIOV enabled */
2283         ixgbe_pf_host_configure(dev);
2284
2285         ixgbe_dev_phy_intr_setup(dev);
2286
2287         /* check and configure queue intr-vector mapping */
2288         if ((rte_intr_cap_multiple(intr_handle) ||
2289              !RTE_ETH_DEV_SRIOV(dev).active) &&
2290             dev->data->dev_conf.intr_conf.rxq != 0) {
2291                 intr_vector = dev->data->nb_rx_queues;
2292                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2293                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2294                                         IXGBE_MAX_INTR_QUEUE_NUM);
2295                         return -ENOTSUP;
2296                 }
2297                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2298                         return -1;
2299         }
2300
2301         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2302                 intr_handle->intr_vec =
2303                         rte_zmalloc("intr_vec",
2304                                     dev->data->nb_rx_queues * sizeof(int), 0);
2305                 if (intr_handle->intr_vec == NULL) {
2306                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2307                                      " intr_vec\n", dev->data->nb_rx_queues);
2308                         return -ENOMEM;
2309                 }
2310         }
2311
2312         /* confiugre msix for sleep until rx interrupt */
2313         ixgbe_configure_msix(dev);
2314
2315         /* initialize transmission unit */
2316         ixgbe_dev_tx_init(dev);
2317
2318         /* This can fail when allocating mbufs for descriptor rings */
2319         err = ixgbe_dev_rx_init(dev);
2320         if (err) {
2321                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2322                 goto error;
2323         }
2324
2325     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2326                 ETH_VLAN_EXTEND_MASK;
2327         ixgbe_vlan_offload_set(dev, mask);
2328
2329         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2330                 /* Enable vlan filtering for VMDq */
2331                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2332         }
2333
2334         /* Configure DCB hw */
2335         ixgbe_configure_dcb(dev);
2336
2337         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2338                 err = ixgbe_fdir_configure(dev);
2339                 if (err)
2340                         goto error;
2341         }
2342
2343         /* Restore vf rate limit */
2344         if (vfinfo != NULL) {
2345                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2346                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2347                                 if (vfinfo[vf].tx_rate[idx] != 0)
2348                                         ixgbe_set_vf_rate_limit(dev, vf,
2349                                                 vfinfo[vf].tx_rate[idx],
2350                                                 1 << idx);
2351         }
2352
2353         ixgbe_restore_statistics_mapping(dev);
2354
2355         err = ixgbe_dev_rxtx_start(dev);
2356         if (err < 0) {
2357                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2358                 goto error;
2359         }
2360
2361         /* Skip link setup if loopback mode is enabled for 82599. */
2362         if (hw->mac.type == ixgbe_mac_82599EB &&
2363                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2364                 goto skip_link_setup;
2365
2366         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2367                 err = hw->mac.ops.setup_sfp(hw);
2368                 if (err)
2369                         goto error;
2370         }
2371
2372         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2373                 /* Turn on the copper */
2374                 ixgbe_set_phy_power(hw, true);
2375         } else {
2376                 /* Turn on the laser */
2377                 ixgbe_enable_tx_laser(hw);
2378         }
2379
2380         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2381         if (err)
2382                 goto error;
2383         dev->data->dev_link.link_status = link_up;
2384
2385         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2386         if (err)
2387                 goto error;
2388
2389         link_speeds = &dev->data->dev_conf.link_speeds;
2390         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2391                         ETH_LINK_SPEED_10G)) {
2392                 PMD_INIT_LOG(ERR, "Invalid link setting");
2393                 goto error;
2394         }
2395
2396         speed = 0x0;
2397         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2398                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2399                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2400                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2401         } else {
2402                 if (*link_speeds & ETH_LINK_SPEED_10G)
2403                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2404                 if (*link_speeds & ETH_LINK_SPEED_1G)
2405                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2406                 if (*link_speeds & ETH_LINK_SPEED_100M)
2407                         speed |= IXGBE_LINK_SPEED_100_FULL;
2408         }
2409
2410         err = ixgbe_setup_link(hw, speed, link_up);
2411         if (err)
2412                 goto error;
2413
2414 skip_link_setup:
2415
2416         if (rte_intr_allow_others(intr_handle)) {
2417                 /* check if lsc interrupt is enabled */
2418                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2419                         ixgbe_dev_lsc_interrupt_setup(dev);
2420                 ixgbe_dev_macsec_interrupt_setup(dev);
2421         } else {
2422                 rte_intr_callback_unregister(intr_handle,
2423                                              ixgbe_dev_interrupt_handler, dev);
2424                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2425                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2426                                      " no intr multiplex\n");
2427         }
2428
2429         /* check if rxq interrupt is enabled */
2430         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2431             rte_intr_dp_is_en(intr_handle))
2432                 ixgbe_dev_rxq_interrupt_setup(dev);
2433
2434         /* enable uio/vfio intr/eventfd mapping */
2435         rte_intr_enable(intr_handle);
2436
2437         /* resume enabled intr since hw reset */
2438         ixgbe_enable_intr(dev);
2439
2440         return 0;
2441
2442 error:
2443         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2444         ixgbe_dev_clear_queues(dev);
2445         return -EIO;
2446 }
2447
2448 /*
2449  * Stop device: disable rx and tx functions to allow for reconfiguring.
2450  */
2451 static void
2452 ixgbe_dev_stop(struct rte_eth_dev *dev)
2453 {
2454         struct rte_eth_link link;
2455         struct ixgbe_hw *hw =
2456                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2457         struct ixgbe_vf_info *vfinfo =
2458                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2459         struct ixgbe_filter_info *filter_info =
2460                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2461         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2462         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2463         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2464         int vf;
2465
2466         PMD_INIT_FUNC_TRACE();
2467
2468         /* disable interrupts */
2469         ixgbe_disable_intr(hw);
2470
2471         /* reset the NIC */
2472         ixgbe_pf_reset_hw(hw);
2473         hw->adapter_stopped = 0;
2474
2475         /* stop adapter */
2476         ixgbe_stop_adapter(hw);
2477
2478         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2479                 vfinfo[vf].clear_to_send = false;
2480
2481         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2482                 /* Turn off the copper */
2483                 ixgbe_set_phy_power(hw, false);
2484         } else {
2485                 /* Turn off the laser */
2486                 ixgbe_disable_tx_laser(hw);
2487         }
2488
2489         ixgbe_dev_clear_queues(dev);
2490
2491         /* Clear stored conf */
2492         dev->data->scattered_rx = 0;
2493         dev->data->lro = 0;
2494
2495         /* Clear recorded link status */
2496         memset(&link, 0, sizeof(link));
2497         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2498
2499         /* Remove all ntuple filters of the device */
2500         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2501              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2502                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2503                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2504                              p_5tuple, entries);
2505                 rte_free(p_5tuple);
2506         }
2507         memset(filter_info->fivetuple_mask, 0,
2508                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2509
2510         if (!rte_intr_allow_others(intr_handle))
2511                 /* resume to the default handler */
2512                 rte_intr_callback_register(intr_handle,
2513                                            ixgbe_dev_interrupt_handler,
2514                                            (void *)dev);
2515
2516         /* Clean datapath event and queue/vec mapping */
2517         rte_intr_efd_disable(intr_handle);
2518         if (intr_handle->intr_vec != NULL) {
2519                 rte_free(intr_handle->intr_vec);
2520                 intr_handle->intr_vec = NULL;
2521         }
2522 }
2523
2524 /*
2525  * Set device link up: enable tx.
2526  */
2527 static int
2528 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2529 {
2530         struct ixgbe_hw *hw =
2531                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2532         if (hw->mac.type == ixgbe_mac_82599EB) {
2533 #ifdef RTE_NIC_BYPASS
2534                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2535                         /* Not suported in bypass mode */
2536                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2537                                      "by device id 0x%x", hw->device_id);
2538                         return -ENOTSUP;
2539                 }
2540 #endif
2541         }
2542
2543         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2544                 /* Turn on the copper */
2545                 ixgbe_set_phy_power(hw, true);
2546         } else {
2547                 /* Turn on the laser */
2548                 ixgbe_enable_tx_laser(hw);
2549         }
2550
2551         return 0;
2552 }
2553
2554 /*
2555  * Set device link down: disable tx.
2556  */
2557 static int
2558 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2559 {
2560         struct ixgbe_hw *hw =
2561                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2562         if (hw->mac.type == ixgbe_mac_82599EB) {
2563 #ifdef RTE_NIC_BYPASS
2564                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2565                         /* Not suported in bypass mode */
2566                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2567                                      "by device id 0x%x", hw->device_id);
2568                         return -ENOTSUP;
2569                 }
2570 #endif
2571         }
2572
2573         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2574                 /* Turn off the copper */
2575                 ixgbe_set_phy_power(hw, false);
2576         } else {
2577                 /* Turn off the laser */
2578                 ixgbe_disable_tx_laser(hw);
2579         }
2580
2581         return 0;
2582 }
2583
2584 /*
2585  * Reest and stop device.
2586  */
2587 static void
2588 ixgbe_dev_close(struct rte_eth_dev *dev)
2589 {
2590         struct ixgbe_hw *hw =
2591                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2592
2593         PMD_INIT_FUNC_TRACE();
2594
2595         ixgbe_pf_reset_hw(hw);
2596
2597         ixgbe_dev_stop(dev);
2598         hw->adapter_stopped = 1;
2599
2600         ixgbe_dev_free_queues(dev);
2601
2602         ixgbe_disable_pcie_master(hw);
2603
2604         /* reprogram the RAR[0] in case user changed it. */
2605         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2606 }
2607
2608 static void
2609 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2610                            struct ixgbe_hw_stats *hw_stats,
2611                            struct ixgbe_macsec_stats *macsec_stats,
2612                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2613                            uint64_t *total_qprc, uint64_t *total_qprdc)
2614 {
2615         uint32_t bprc, lxon, lxoff, total;
2616         uint32_t delta_gprc = 0;
2617         unsigned i;
2618         /* Workaround for RX byte count not including CRC bytes when CRC
2619 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2620          * is disabled.
2621 +        */
2622         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2623                         IXGBE_HLREG0_RXCRCSTRP);
2624
2625         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2626         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2627         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2628         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2629
2630         for (i = 0; i < 8; i++) {
2631                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2632
2633                 /* global total per queue */
2634                 hw_stats->mpc[i] += mp;
2635                 /* Running comprehensive total for stats display */
2636                 *total_missed_rx += hw_stats->mpc[i];
2637                 if (hw->mac.type == ixgbe_mac_82598EB) {
2638                         hw_stats->rnbc[i] +=
2639                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2640                         hw_stats->pxonrxc[i] +=
2641                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2642                         hw_stats->pxoffrxc[i] +=
2643                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2644                 } else {
2645                         hw_stats->pxonrxc[i] +=
2646                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2647                         hw_stats->pxoffrxc[i] +=
2648                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2649                         hw_stats->pxon2offc[i] +=
2650                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2651                 }
2652                 hw_stats->pxontxc[i] +=
2653                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2654                 hw_stats->pxofftxc[i] +=
2655                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2656         }
2657         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2658                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2659                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2660                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2661
2662                 delta_gprc += delta_qprc;
2663
2664                 hw_stats->qprc[i] += delta_qprc;
2665                 hw_stats->qptc[i] += delta_qptc;
2666
2667                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2668                 hw_stats->qbrc[i] +=
2669                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2670                 if (crc_strip == 0)
2671                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2672
2673                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2674                 hw_stats->qbtc[i] +=
2675                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2676
2677                 hw_stats->qprdc[i] += delta_qprdc;
2678                 *total_qprdc += hw_stats->qprdc[i];
2679
2680                 *total_qprc += hw_stats->qprc[i];
2681                 *total_qbrc += hw_stats->qbrc[i];
2682         }
2683         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2684         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2685         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2686
2687         /*
2688          * An errata states that gprc actually counts good + missed packets:
2689          * Workaround to set gprc to summated queue packet receives
2690          */
2691         hw_stats->gprc = *total_qprc;
2692
2693         if (hw->mac.type != ixgbe_mac_82598EB) {
2694                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2695                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2696                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2697                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2698                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2699                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2700                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2701                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2702         } else {
2703                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2704                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2705                 /* 82598 only has a counter in the high register */
2706                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2707                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2708                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2709         }
2710         uint64_t old_tpr = hw_stats->tpr;
2711
2712         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2713         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2714
2715         if (crc_strip == 0)
2716                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2717
2718         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2719         hw_stats->gptc += delta_gptc;
2720         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2721         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2722
2723         /*
2724          * Workaround: mprc hardware is incorrectly counting
2725          * broadcasts, so for now we subtract those.
2726          */
2727         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2728         hw_stats->bprc += bprc;
2729         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2730         if (hw->mac.type == ixgbe_mac_82598EB)
2731                 hw_stats->mprc -= bprc;
2732
2733         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2734         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2735         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2736         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2737         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2738         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2739
2740         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2741         hw_stats->lxontxc += lxon;
2742         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2743         hw_stats->lxofftxc += lxoff;
2744         total = lxon + lxoff;
2745
2746         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2747         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2748         hw_stats->gptc -= total;
2749         hw_stats->mptc -= total;
2750         hw_stats->ptc64 -= total;
2751         hw_stats->gotc -= total * ETHER_MIN_LEN;
2752
2753         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2754         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2755         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2756         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2757         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2758         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2759         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2760         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2761         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2762         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2763         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2764         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2765         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2766         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2767         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2768         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2769         /* Only read FCOE on 82599 */
2770         if (hw->mac.type != ixgbe_mac_82598EB) {
2771                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2772                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2773                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2774                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2775                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2776         }
2777
2778         /* Flow Director Stats registers */
2779         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2780         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2781
2782         /* MACsec Stats registers */
2783         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
2784         macsec_stats->out_pkts_encrypted +=
2785                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
2786         macsec_stats->out_pkts_protected +=
2787                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
2788         macsec_stats->out_octets_encrypted +=
2789                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
2790         macsec_stats->out_octets_protected +=
2791                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
2792         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
2793         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
2794         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
2795         macsec_stats->in_pkts_unknownsci +=
2796                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
2797         macsec_stats->in_octets_decrypted +=
2798                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
2799         macsec_stats->in_octets_validated +=
2800                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
2801         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
2802         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
2803         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
2804         for (i = 0; i < 2; i++) {
2805                 macsec_stats->in_pkts_ok +=
2806                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
2807                 macsec_stats->in_pkts_invalid +=
2808                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
2809                 macsec_stats->in_pkts_notvalid +=
2810                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
2811         }
2812         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
2813         macsec_stats->in_pkts_notusingsa +=
2814                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
2815 }
2816
2817 /*
2818  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2819  */
2820 static void
2821 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2822 {
2823         struct ixgbe_hw *hw =
2824                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2825         struct ixgbe_hw_stats *hw_stats =
2826                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2827         struct ixgbe_macsec_stats *macsec_stats =
2828                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2829                                 dev->data->dev_private);
2830         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2831         unsigned i;
2832
2833         total_missed_rx = 0;
2834         total_qbrc = 0;
2835         total_qprc = 0;
2836         total_qprdc = 0;
2837
2838         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2839                         &total_qbrc, &total_qprc, &total_qprdc);
2840
2841         if (stats == NULL)
2842                 return;
2843
2844         /* Fill out the rte_eth_stats statistics structure */
2845         stats->ipackets = total_qprc;
2846         stats->ibytes = total_qbrc;
2847         stats->opackets = hw_stats->gptc;
2848         stats->obytes = hw_stats->gotc;
2849
2850         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2851                 stats->q_ipackets[i] = hw_stats->qprc[i];
2852                 stats->q_opackets[i] = hw_stats->qptc[i];
2853                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2854                 stats->q_obytes[i] = hw_stats->qbtc[i];
2855                 stats->q_errors[i] = hw_stats->qprdc[i];
2856         }
2857
2858         /* Rx Errors */
2859         stats->imissed  = total_missed_rx;
2860         stats->ierrors  = hw_stats->crcerrs +
2861                           hw_stats->mspdc +
2862                           hw_stats->rlec +
2863                           hw_stats->ruc +
2864                           hw_stats->roc +
2865                           hw_stats->illerrc +
2866                           hw_stats->errbc +
2867                           hw_stats->rfc +
2868                           hw_stats->fccrc +
2869                           hw_stats->fclast;
2870
2871         /* Tx Errors */
2872         stats->oerrors  = 0;
2873 }
2874
2875 static void
2876 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2877 {
2878         struct ixgbe_hw_stats *stats =
2879                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2880
2881         /* HW registers are cleared on read */
2882         ixgbe_dev_stats_get(dev, NULL);
2883
2884         /* Reset software totals */
2885         memset(stats, 0, sizeof(*stats));
2886 }
2887
2888 /* This function calculates the number of xstats based on the current config */
2889 static unsigned
2890 ixgbe_xstats_calc_num(void) {
2891         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
2892                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2893                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2894 }
2895
2896 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2897         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2898 {
2899         const unsigned cnt_stats = ixgbe_xstats_calc_num();
2900         unsigned stat, i, count;
2901
2902         if (xstats_names != NULL) {
2903                 count = 0;
2904
2905                 /* Note: limit >= cnt_stats checked upstream
2906                  * in rte_eth_xstats_names()
2907                  */
2908
2909                 /* Extended stats from ixgbe_hw_stats */
2910                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2911                         snprintf(xstats_names[count].name,
2912                                 sizeof(xstats_names[count].name),
2913                                 "%s",
2914                                 rte_ixgbe_stats_strings[i].name);
2915                         count++;
2916                 }
2917
2918                 /* MACsec Stats */
2919                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
2920                         snprintf(xstats_names[count].name,
2921                                 sizeof(xstats_names[count].name),
2922                                 "%s",
2923                                 rte_ixgbe_macsec_strings[i].name);
2924                         count++;
2925                 }
2926
2927                 /* RX Priority Stats */
2928                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2929                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2930                                 snprintf(xstats_names[count].name,
2931                                         sizeof(xstats_names[count].name),
2932                                         "rx_priority%u_%s", i,
2933                                         rte_ixgbe_rxq_strings[stat].name);
2934                                 count++;
2935                         }
2936                 }
2937
2938                 /* TX Priority Stats */
2939                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2940                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2941                                 snprintf(xstats_names[count].name,
2942                                         sizeof(xstats_names[count].name),
2943                                         "tx_priority%u_%s", i,
2944                                         rte_ixgbe_txq_strings[stat].name);
2945                                 count++;
2946                         }
2947                 }
2948         }
2949         return cnt_stats;
2950 }
2951
2952 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2953         struct rte_eth_xstat_name *xstats_names, unsigned limit)
2954 {
2955         unsigned i;
2956
2957         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2958                 return -ENOMEM;
2959
2960         if (xstats_names != NULL)
2961                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2962                         snprintf(xstats_names[i].name,
2963                                 sizeof(xstats_names[i].name),
2964                                 "%s", rte_ixgbevf_stats_strings[i].name);
2965         return IXGBEVF_NB_XSTATS;
2966 }
2967
2968 static int
2969 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2970                                          unsigned n)
2971 {
2972         struct ixgbe_hw *hw =
2973                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2974         struct ixgbe_hw_stats *hw_stats =
2975                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2976         struct ixgbe_macsec_stats *macsec_stats =
2977                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2978                                 dev->data->dev_private);
2979         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2980         unsigned i, stat, count = 0;
2981
2982         count = ixgbe_xstats_calc_num();
2983
2984         if (n < count)
2985                 return count;
2986
2987         total_missed_rx = 0;
2988         total_qbrc = 0;
2989         total_qprc = 0;
2990         total_qprdc = 0;
2991
2992         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2993                         &total_qbrc, &total_qprc, &total_qprdc);
2994
2995         /* If this is a reset xstats is NULL, and we have cleared the
2996          * registers by reading them.
2997          */
2998         if (!xstats)
2999                 return 0;
3000
3001         /* Extended stats from ixgbe_hw_stats */
3002         count = 0;
3003         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3004                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3005                                 rte_ixgbe_stats_strings[i].offset);
3006                 xstats[count].id = count;
3007                 count++;
3008         }
3009
3010         /* MACsec Stats */
3011         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3012                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3013                                 rte_ixgbe_macsec_strings[i].offset);
3014                 xstats[count].id = count;
3015                 count++;
3016         }
3017
3018         /* RX Priority Stats */
3019         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3020                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3021                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3022                                         rte_ixgbe_rxq_strings[stat].offset +
3023                                         (sizeof(uint64_t) * i));
3024                         xstats[count].id = count;
3025                         count++;
3026                 }
3027         }
3028
3029         /* TX Priority Stats */
3030         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3031                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3032                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3033                                         rte_ixgbe_txq_strings[stat].offset +
3034                                         (sizeof(uint64_t) * i));
3035                         xstats[count].id = count;
3036                         count++;
3037                 }
3038         }
3039         return count;
3040 }
3041
3042 static void
3043 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3044 {
3045         struct ixgbe_hw_stats *stats =
3046                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3047         struct ixgbe_macsec_stats *macsec_stats =
3048                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3049                                 dev->data->dev_private);
3050
3051         unsigned count = ixgbe_xstats_calc_num();
3052
3053         /* HW registers are cleared on read */
3054         ixgbe_dev_xstats_get(dev, NULL, count);
3055
3056         /* Reset software totals */
3057         memset(stats, 0, sizeof(*stats));
3058         memset(macsec_stats, 0, sizeof(*macsec_stats));
3059 }
3060
3061 static void
3062 ixgbevf_update_stats(struct rte_eth_dev *dev)
3063 {
3064         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3065         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3066                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3067
3068         /* Good Rx packet, include VF loopback */
3069         UPDATE_VF_STAT(IXGBE_VFGPRC,
3070             hw_stats->last_vfgprc, hw_stats->vfgprc);
3071
3072         /* Good Rx octets, include VF loopback */
3073         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3074             hw_stats->last_vfgorc, hw_stats->vfgorc);
3075
3076         /* Good Tx packet, include VF loopback */
3077         UPDATE_VF_STAT(IXGBE_VFGPTC,
3078             hw_stats->last_vfgptc, hw_stats->vfgptc);
3079
3080         /* Good Tx octets, include VF loopback */
3081         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3082             hw_stats->last_vfgotc, hw_stats->vfgotc);
3083
3084         /* Rx Multicst Packet */
3085         UPDATE_VF_STAT(IXGBE_VFMPRC,
3086             hw_stats->last_vfmprc, hw_stats->vfmprc);
3087 }
3088
3089 static int
3090 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3091                        unsigned n)
3092 {
3093         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3094                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3095         unsigned i;
3096
3097         if (n < IXGBEVF_NB_XSTATS)
3098                 return IXGBEVF_NB_XSTATS;
3099
3100         ixgbevf_update_stats(dev);
3101
3102         if (!xstats)
3103                 return 0;
3104
3105         /* Extended stats */
3106         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3107                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3108                         rte_ixgbevf_stats_strings[i].offset);
3109         }
3110
3111         return IXGBEVF_NB_XSTATS;
3112 }
3113
3114 static void
3115 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3116 {
3117         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3118                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3119
3120         ixgbevf_update_stats(dev);
3121
3122         if (stats == NULL)
3123                 return;
3124
3125         stats->ipackets = hw_stats->vfgprc;
3126         stats->ibytes = hw_stats->vfgorc;
3127         stats->opackets = hw_stats->vfgptc;
3128         stats->obytes = hw_stats->vfgotc;
3129 }
3130
3131 static void
3132 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3133 {
3134         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3135                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3136
3137         /* Sync HW register to the last stats */
3138         ixgbevf_dev_stats_get(dev, NULL);
3139
3140         /* reset HW current stats*/
3141         hw_stats->vfgprc = 0;
3142         hw_stats->vfgorc = 0;
3143         hw_stats->vfgptc = 0;
3144         hw_stats->vfgotc = 0;
3145 }
3146
3147 static void
3148 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3149 {
3150         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3151         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3152         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3153
3154         dev_info->pci_dev = pci_dev;
3155         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3156         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3157         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3158                 /*
3159                  * When DCB/VT is off, maximum number of queues changes,
3160                  * except for 82598EB, which remains constant.
3161                  */
3162                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3163                                 hw->mac.type != ixgbe_mac_82598EB)
3164                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3165         }
3166         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3167         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3168         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3169         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3170         dev_info->max_vfs = pci_dev->max_vfs;
3171         if (hw->mac.type == ixgbe_mac_82598EB)
3172                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3173         else
3174                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3175         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3176         dev_info->rx_offload_capa =
3177                 DEV_RX_OFFLOAD_VLAN_STRIP |
3178                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3179                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3180                 DEV_RX_OFFLOAD_TCP_CKSUM;
3181
3182         /*
3183          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3184          * mode.
3185          */
3186         if ((hw->mac.type == ixgbe_mac_82599EB ||
3187              hw->mac.type == ixgbe_mac_X540) &&
3188             !RTE_ETH_DEV_SRIOV(dev).active)
3189                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3190
3191         if (hw->mac.type == ixgbe_mac_82599EB ||
3192             hw->mac.type == ixgbe_mac_X540)
3193                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3194
3195         if (hw->mac.type == ixgbe_mac_X550 ||
3196             hw->mac.type == ixgbe_mac_X550EM_x ||
3197             hw->mac.type == ixgbe_mac_X550EM_a)
3198                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3199
3200         dev_info->tx_offload_capa =
3201                 DEV_TX_OFFLOAD_VLAN_INSERT |
3202                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3203                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3204                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3205                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3206                 DEV_TX_OFFLOAD_TCP_TSO;
3207
3208         if (hw->mac.type == ixgbe_mac_82599EB ||
3209             hw->mac.type == ixgbe_mac_X540)
3210                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3211
3212         if (hw->mac.type == ixgbe_mac_X550 ||
3213             hw->mac.type == ixgbe_mac_X550EM_x ||
3214             hw->mac.type == ixgbe_mac_X550EM_a)
3215                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3216
3217         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3218                 .rx_thresh = {
3219                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3220                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3221                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3222                 },
3223                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3224                 .rx_drop_en = 0,
3225         };
3226
3227         dev_info->default_txconf = (struct rte_eth_txconf) {
3228                 .tx_thresh = {
3229                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3230                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3231                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3232                 },
3233                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3234                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3235                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3236                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3237         };
3238
3239         dev_info->rx_desc_lim = rx_desc_lim;
3240         dev_info->tx_desc_lim = tx_desc_lim;
3241
3242         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3243         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3244         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3245
3246         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3247         if (hw->mac.type == ixgbe_mac_X540 ||
3248             hw->mac.type == ixgbe_mac_X540_vf ||
3249             hw->mac.type == ixgbe_mac_X550 ||
3250             hw->mac.type == ixgbe_mac_X550_vf) {
3251                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3252         }
3253 }
3254
3255 static const uint32_t *
3256 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3257 {
3258         static const uint32_t ptypes[] = {
3259                 /* For non-vec functions,
3260                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3261                  * for vec functions,
3262                  * refers to _recv_raw_pkts_vec().
3263                  */
3264                 RTE_PTYPE_L2_ETHER,
3265                 RTE_PTYPE_L3_IPV4,
3266                 RTE_PTYPE_L3_IPV4_EXT,
3267                 RTE_PTYPE_L3_IPV6,
3268                 RTE_PTYPE_L3_IPV6_EXT,
3269                 RTE_PTYPE_L4_SCTP,
3270                 RTE_PTYPE_L4_TCP,
3271                 RTE_PTYPE_L4_UDP,
3272                 RTE_PTYPE_TUNNEL_IP,
3273                 RTE_PTYPE_INNER_L3_IPV6,
3274                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3275                 RTE_PTYPE_INNER_L4_TCP,
3276                 RTE_PTYPE_INNER_L4_UDP,
3277                 RTE_PTYPE_UNKNOWN
3278         };
3279
3280         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3281             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3282             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3283             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3284                 return ptypes;
3285         return NULL;
3286 }
3287
3288 static void
3289 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3290                      struct rte_eth_dev_info *dev_info)
3291 {
3292         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3293         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3294
3295         dev_info->pci_dev = pci_dev;
3296         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3297         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3298         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3299         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3300         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3301         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3302         dev_info->max_vfs = pci_dev->max_vfs;
3303         if (hw->mac.type == ixgbe_mac_82598EB)
3304                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3305         else
3306                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3307         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3308                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3309                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3310                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3311         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3312                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3313                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3314                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3315                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3316                                 DEV_TX_OFFLOAD_TCP_TSO;
3317
3318         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3319                 .rx_thresh = {
3320                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3321                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3322                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3323                 },
3324                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3325                 .rx_drop_en = 0,
3326         };
3327
3328         dev_info->default_txconf = (struct rte_eth_txconf) {
3329                 .tx_thresh = {
3330                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3331                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3332                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3333                 },
3334                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3335                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3336                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3337                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3338         };
3339
3340         dev_info->rx_desc_lim = rx_desc_lim;
3341         dev_info->tx_desc_lim = tx_desc_lim;
3342 }
3343
3344 /* return 0 means link status changed, -1 means not changed */
3345 static int
3346 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3347 {
3348         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3349         struct rte_eth_link link, old;
3350         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3351         int link_up;
3352         int diag;
3353
3354         link.link_status = ETH_LINK_DOWN;
3355         link.link_speed = 0;
3356         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3357         memset(&old, 0, sizeof(old));
3358         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3359
3360         hw->mac.get_link_status = true;
3361
3362         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3363         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3364                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3365         else
3366                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3367
3368         if (diag != 0) {
3369                 link.link_speed = ETH_SPEED_NUM_100M;
3370                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3371                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3372                 if (link.link_status == old.link_status)
3373                         return -1;
3374                 return 0;
3375         }
3376
3377         if (link_up == 0) {
3378                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3379                 if (link.link_status == old.link_status)
3380                         return -1;
3381                 return 0;
3382         }
3383         link.link_status = ETH_LINK_UP;
3384         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3385
3386         switch (link_speed) {
3387         default:
3388         case IXGBE_LINK_SPEED_UNKNOWN:
3389                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3390                 link.link_speed = ETH_SPEED_NUM_100M;
3391                 break;
3392
3393         case IXGBE_LINK_SPEED_100_FULL:
3394                 link.link_speed = ETH_SPEED_NUM_100M;
3395                 break;
3396
3397         case IXGBE_LINK_SPEED_1GB_FULL:
3398                 link.link_speed = ETH_SPEED_NUM_1G;
3399                 break;
3400
3401         case IXGBE_LINK_SPEED_10GB_FULL:
3402                 link.link_speed = ETH_SPEED_NUM_10G;
3403                 break;
3404         }
3405         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3406
3407         if (link.link_status == old.link_status)
3408                 return -1;
3409
3410         return 0;
3411 }
3412
3413 static void
3414 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3415 {
3416         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3417         uint32_t fctrl;
3418
3419         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3420         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3421         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3422 }
3423
3424 static void
3425 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3426 {
3427         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3428         uint32_t fctrl;
3429
3430         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3431         fctrl &= (~IXGBE_FCTRL_UPE);
3432         if (dev->data->all_multicast == 1)
3433                 fctrl |= IXGBE_FCTRL_MPE;
3434         else
3435                 fctrl &= (~IXGBE_FCTRL_MPE);
3436         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3437 }
3438
3439 static void
3440 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3441 {
3442         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3443         uint32_t fctrl;
3444
3445         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3446         fctrl |= IXGBE_FCTRL_MPE;
3447         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3448 }
3449
3450 static void
3451 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3452 {
3453         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3454         uint32_t fctrl;
3455
3456         if (dev->data->promiscuous == 1)
3457                 return; /* must remain in all_multicast mode */
3458
3459         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3460         fctrl &= (~IXGBE_FCTRL_MPE);
3461         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3462 }
3463
3464 /**
3465  * It clears the interrupt causes and enables the interrupt.
3466  * It will be called once only during nic initialized.
3467  *
3468  * @param dev
3469  *  Pointer to struct rte_eth_dev.
3470  *
3471  * @return
3472  *  - On success, zero.
3473  *  - On failure, a negative value.
3474  */
3475 static int
3476 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3477 {
3478         struct ixgbe_interrupt *intr =
3479                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3480
3481         ixgbe_dev_link_status_print(dev);
3482         intr->mask |= IXGBE_EICR_LSC;
3483
3484         return 0;
3485 }
3486
3487 /**
3488  * It clears the interrupt causes and enables the interrupt.
3489  * It will be called once only during nic initialized.
3490  *
3491  * @param dev
3492  *  Pointer to struct rte_eth_dev.
3493  *
3494  * @return
3495  *  - On success, zero.
3496  *  - On failure, a negative value.
3497  */
3498 static int
3499 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3500 {
3501         struct ixgbe_interrupt *intr =
3502                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3503
3504         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3505
3506         return 0;
3507 }
3508
3509 /**
3510  * It clears the interrupt causes and enables the interrupt.
3511  * It will be called once only during nic initialized.
3512  *
3513  * @param dev
3514  *  Pointer to struct rte_eth_dev.
3515  *
3516  * @return
3517  *  - On success, zero.
3518  *  - On failure, a negative value.
3519  */
3520 static int
3521 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3522 {
3523         struct ixgbe_interrupt *intr =
3524                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3525
3526         intr->mask |= IXGBE_EICR_LINKSEC;
3527
3528         return 0;
3529 }
3530
3531 /*
3532  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3533  *
3534  * @param dev
3535  *  Pointer to struct rte_eth_dev.
3536  *
3537  * @return
3538  *  - On success, zero.
3539  *  - On failure, a negative value.
3540  */
3541 static int
3542 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3543 {
3544         uint32_t eicr;
3545         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3546         struct ixgbe_interrupt *intr =
3547                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3548
3549         /* clear all cause mask */
3550         ixgbe_disable_intr(hw);
3551
3552         /* read-on-clear nic registers here */
3553         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3554         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3555
3556         intr->flags = 0;
3557
3558         /* set flag for async link update */
3559         if (eicr & IXGBE_EICR_LSC)
3560                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3561
3562         if (eicr & IXGBE_EICR_MAILBOX)
3563                 intr->flags |= IXGBE_FLAG_MAILBOX;
3564
3565         if (eicr & IXGBE_EICR_LINKSEC)
3566                 intr->flags |= IXGBE_FLAG_MACSEC;
3567
3568         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3569             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3570             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3571                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3572
3573         return 0;
3574 }
3575
3576 /**
3577  * It gets and then prints the link status.
3578  *
3579  * @param dev
3580  *  Pointer to struct rte_eth_dev.
3581  *
3582  * @return
3583  *  - On success, zero.
3584  *  - On failure, a negative value.
3585  */
3586 static void
3587 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3588 {
3589         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3590         struct rte_eth_link link;
3591
3592         memset(&link, 0, sizeof(link));
3593         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3594         if (link.link_status) {
3595                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3596                                         (int)(dev->data->port_id),
3597                                         (unsigned)link.link_speed,
3598                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3599                                         "full-duplex" : "half-duplex");
3600         } else {
3601                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3602                                 (int)(dev->data->port_id));
3603         }
3604         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3605                                 pci_dev->addr.domain,
3606                                 pci_dev->addr.bus,
3607                                 pci_dev->addr.devid,
3608                                 pci_dev->addr.function);
3609 }
3610
3611 /*
3612  * It executes link_update after knowing an interrupt occurred.
3613  *
3614  * @param dev
3615  *  Pointer to struct rte_eth_dev.
3616  *
3617  * @return
3618  *  - On success, zero.
3619  *  - On failure, a negative value.
3620  */
3621 static int
3622 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3623                            struct rte_intr_handle *intr_handle)
3624 {
3625         struct ixgbe_interrupt *intr =
3626                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3627         int64_t timeout;
3628         struct rte_eth_link link;
3629         int intr_enable_delay = false;
3630         struct ixgbe_hw *hw =
3631                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3632
3633         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3634
3635         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3636                 ixgbe_pf_mbx_process(dev);
3637                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3638         }
3639
3640         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3641                 ixgbe_handle_lasi(hw);
3642                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3643         }
3644
3645         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3646                 /* get the link status before link update, for predicting later */
3647                 memset(&link, 0, sizeof(link));
3648                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3649
3650                 ixgbe_dev_link_update(dev, 0);
3651
3652                 /* likely to up */
3653                 if (!link.link_status)
3654                         /* handle it 1 sec later, wait it being stable */
3655                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3656                 /* likely to down */
3657                 else
3658                         /* handle it 4 sec later, wait it being stable */
3659                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3660
3661                 ixgbe_dev_link_status_print(dev);
3662
3663                 intr_enable_delay = true;
3664         }
3665
3666         if (intr_enable_delay) {
3667                 if (rte_eal_alarm_set(timeout * 1000,
3668                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3669                         PMD_DRV_LOG(ERR, "Error setting alarm");
3670         } else {
3671                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3672                 ixgbe_enable_intr(dev);
3673                 rte_intr_enable(intr_handle);
3674         }
3675
3676
3677         return 0;
3678 }
3679
3680 /**
3681  * Interrupt handler which shall be registered for alarm callback for delayed
3682  * handling specific interrupt to wait for the stable nic state. As the
3683  * NIC interrupt state is not stable for ixgbe after link is just down,
3684  * it needs to wait 4 seconds to get the stable status.
3685  *
3686  * @param handle
3687  *  Pointer to interrupt handle.
3688  * @param param
3689  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3690  *
3691  * @return
3692  *  void
3693  */
3694 static void
3695 ixgbe_dev_interrupt_delayed_handler(void *param)
3696 {
3697         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3698         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3699         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3700         struct ixgbe_interrupt *intr =
3701                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3702         struct ixgbe_hw *hw =
3703                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3704         uint32_t eicr;
3705
3706         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3707         if (eicr & IXGBE_EICR_MAILBOX)
3708                 ixgbe_pf_mbx_process(dev);
3709
3710         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3711                 ixgbe_handle_lasi(hw);
3712                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3713         }
3714
3715         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3716                 ixgbe_dev_link_update(dev, 0);
3717                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3718                 ixgbe_dev_link_status_print(dev);
3719                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3720         }
3721
3722         if (intr->flags & IXGBE_FLAG_MACSEC) {
3723                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3724                                               NULL);
3725                 intr->flags &= ~IXGBE_FLAG_MACSEC;
3726         }
3727
3728         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3729         ixgbe_enable_intr(dev);
3730         rte_intr_enable(intr_handle);
3731 }
3732
3733 /**
3734  * Interrupt handler triggered by NIC  for handling
3735  * specific interrupt.
3736  *
3737  * @param handle
3738  *  Pointer to interrupt handle.
3739  * @param param
3740  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3741  *
3742  * @return
3743  *  void
3744  */
3745 static void
3746 ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
3747                             void *param)
3748 {
3749         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3750
3751         ixgbe_dev_interrupt_get_status(dev);
3752         ixgbe_dev_interrupt_action(dev, handle);
3753 }
3754
3755 static int
3756 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3757 {
3758         struct ixgbe_hw *hw;
3759
3760         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3761         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3762 }
3763
3764 static int
3765 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3766 {
3767         struct ixgbe_hw *hw;
3768
3769         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3770         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3771 }
3772
3773 static int
3774 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3775 {
3776         struct ixgbe_hw *hw;
3777         uint32_t mflcn_reg;
3778         uint32_t fccfg_reg;
3779         int rx_pause;
3780         int tx_pause;
3781
3782         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3783
3784         fc_conf->pause_time = hw->fc.pause_time;
3785         fc_conf->high_water = hw->fc.high_water[0];
3786         fc_conf->low_water = hw->fc.low_water[0];
3787         fc_conf->send_xon = hw->fc.send_xon;
3788         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3789
3790         /*
3791          * Return rx_pause status according to actual setting of
3792          * MFLCN register.
3793          */
3794         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3795         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3796                 rx_pause = 1;
3797         else
3798                 rx_pause = 0;
3799
3800         /*
3801          * Return tx_pause status according to actual setting of
3802          * FCCFG register.
3803          */
3804         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3805         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3806                 tx_pause = 1;
3807         else
3808                 tx_pause = 0;
3809
3810         if (rx_pause && tx_pause)
3811                 fc_conf->mode = RTE_FC_FULL;
3812         else if (rx_pause)
3813                 fc_conf->mode = RTE_FC_RX_PAUSE;
3814         else if (tx_pause)
3815                 fc_conf->mode = RTE_FC_TX_PAUSE;
3816         else
3817                 fc_conf->mode = RTE_FC_NONE;
3818
3819         return 0;
3820 }
3821
3822 static int
3823 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3824 {
3825         struct ixgbe_hw *hw;
3826         int err;
3827         uint32_t rx_buf_size;
3828         uint32_t max_high_water;
3829         uint32_t mflcn;
3830         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3831                 ixgbe_fc_none,
3832                 ixgbe_fc_rx_pause,
3833                 ixgbe_fc_tx_pause,
3834                 ixgbe_fc_full
3835         };
3836
3837         PMD_INIT_FUNC_TRACE();
3838
3839         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3840         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3841         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3842
3843         /*
3844          * At least reserve one Ethernet frame for watermark
3845          * high_water/low_water in kilo bytes for ixgbe
3846          */
3847         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3848         if ((fc_conf->high_water > max_high_water) ||
3849                 (fc_conf->high_water < fc_conf->low_water)) {
3850                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3851                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3852                 return -EINVAL;
3853         }
3854
3855         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3856         hw->fc.pause_time     = fc_conf->pause_time;
3857         hw->fc.high_water[0]  = fc_conf->high_water;
3858         hw->fc.low_water[0]   = fc_conf->low_water;
3859         hw->fc.send_xon       = fc_conf->send_xon;
3860         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3861
3862         err = ixgbe_fc_enable(hw);
3863
3864         /* Not negotiated is not an error case */
3865         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3866
3867                 /* check if we want to forward MAC frames - driver doesn't have native
3868                  * capability to do that, so we'll write the registers ourselves */
3869
3870                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3871
3872                 /* set or clear MFLCN.PMCF bit depending on configuration */
3873                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3874                         mflcn |= IXGBE_MFLCN_PMCF;
3875                 else
3876                         mflcn &= ~IXGBE_MFLCN_PMCF;
3877
3878                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3879                 IXGBE_WRITE_FLUSH(hw);
3880
3881                 return 0;
3882         }
3883
3884         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3885         return -EIO;
3886 }
3887
3888 /**
3889  *  ixgbe_pfc_enable_generic - Enable flow control
3890  *  @hw: pointer to hardware structure
3891  *  @tc_num: traffic class number
3892  *  Enable flow control according to the current settings.
3893  */
3894 static int
3895 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3896 {
3897         int ret_val = 0;
3898         uint32_t mflcn_reg, fccfg_reg;
3899         uint32_t reg;
3900         uint32_t fcrtl, fcrth;
3901         uint8_t i;
3902         uint8_t nb_rx_en;
3903
3904         /* Validate the water mark configuration */
3905         if (!hw->fc.pause_time) {
3906                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3907                 goto out;
3908         }
3909
3910         /* Low water mark of zero causes XOFF floods */
3911         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3912                  /* High/Low water can not be 0 */
3913                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3914                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3915                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3916                         goto out;
3917                 }
3918
3919                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3920                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3921                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3922                         goto out;
3923                 }
3924         }
3925         /* Negotiate the fc mode to use */
3926         ixgbe_fc_autoneg(hw);
3927
3928         /* Disable any previous flow control settings */
3929         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3930         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3931
3932         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3933         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3934
3935         switch (hw->fc.current_mode) {
3936         case ixgbe_fc_none:
3937                 /*
3938                  * If the count of enabled RX Priority Flow control >1,
3939                  * and the TX pause can not be disabled
3940                  */
3941                 nb_rx_en = 0;
3942                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3943                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3944                         if (reg & IXGBE_FCRTH_FCEN)
3945                                 nb_rx_en++;
3946                 }
3947                 if (nb_rx_en > 1)
3948                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3949                 break;
3950         case ixgbe_fc_rx_pause:
3951                 /*
3952                  * Rx Flow control is enabled and Tx Flow control is
3953                  * disabled by software override. Since there really
3954                  * isn't a way to advertise that we are capable of RX
3955                  * Pause ONLY, we will advertise that we support both
3956                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3957                  * disable the adapter's ability to send PAUSE frames.
3958                  */
3959                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3960                 /*
3961                  * If the count of enabled RX Priority Flow control >1,
3962                  * and the TX pause can not be disabled
3963                  */
3964                 nb_rx_en = 0;
3965                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3966                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3967                         if (reg & IXGBE_FCRTH_FCEN)
3968                                 nb_rx_en++;
3969                 }
3970                 if (nb_rx_en > 1)
3971                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3972                 break;
3973         case ixgbe_fc_tx_pause:
3974                 /*
3975                  * Tx Flow control is enabled, and Rx Flow control is
3976                  * disabled by software override.
3977                  */
3978                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3979                 break;
3980         case ixgbe_fc_full:
3981                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3982                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3983                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3984                 break;
3985         default:
3986                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3987                 ret_val = IXGBE_ERR_CONFIG;
3988                 goto out;
3989         }
3990
3991         /* Set 802.3x based flow control settings. */
3992         mflcn_reg |= IXGBE_MFLCN_DPF;
3993         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3994         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3995
3996         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3997         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3998                 hw->fc.high_water[tc_num]) {
3999                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4000                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4001                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4002         } else {
4003                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4004                 /*
4005                  * In order to prevent Tx hangs when the internal Tx
4006                  * switch is enabled we must set the high water mark
4007                  * to the maximum FCRTH value.  This allows the Tx
4008                  * switch to function even under heavy Rx workloads.
4009                  */
4010                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4011         }
4012         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4013
4014         /* Configure pause time (2 TCs per register) */
4015         reg = hw->fc.pause_time * 0x00010001;
4016         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4017                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4018
4019         /* Configure flow control refresh threshold value */
4020         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4021
4022 out:
4023         return ret_val;
4024 }
4025
4026 static int
4027 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4028 {
4029         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4030         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4031
4032         if (hw->mac.type != ixgbe_mac_82598EB) {
4033                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4034         }
4035         return ret_val;
4036 }
4037
4038 static int
4039 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4040 {
4041         int err;
4042         uint32_t rx_buf_size;
4043         uint32_t max_high_water;
4044         uint8_t tc_num;
4045         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4046         struct ixgbe_hw *hw =
4047                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4048         struct ixgbe_dcb_config *dcb_config =
4049                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4050
4051         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4052                 ixgbe_fc_none,
4053                 ixgbe_fc_rx_pause,
4054                 ixgbe_fc_tx_pause,
4055                 ixgbe_fc_full
4056         };
4057
4058         PMD_INIT_FUNC_TRACE();
4059
4060         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4061         tc_num = map[pfc_conf->priority];
4062         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4063         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4064         /*
4065          * At least reserve one Ethernet frame for watermark
4066          * high_water/low_water in kilo bytes for ixgbe
4067          */
4068         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4069         if ((pfc_conf->fc.high_water > max_high_water) ||
4070             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4071                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4072                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4073                 return -EINVAL;
4074         }
4075
4076         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4077         hw->fc.pause_time = pfc_conf->fc.pause_time;
4078         hw->fc.send_xon = pfc_conf->fc.send_xon;
4079         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4080         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4081
4082         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4083
4084         /* Not negotiated is not an error case */
4085         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4086                 return 0;
4087
4088         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4089         return -EIO;
4090 }
4091
4092 static int
4093 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4094                           struct rte_eth_rss_reta_entry64 *reta_conf,
4095                           uint16_t reta_size)
4096 {
4097         uint16_t i, sp_reta_size;
4098         uint8_t j, mask;
4099         uint32_t reta, r;
4100         uint16_t idx, shift;
4101         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4102         uint32_t reta_reg;
4103
4104         PMD_INIT_FUNC_TRACE();
4105
4106         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4107                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4108                         "NIC.");
4109                 return -ENOTSUP;
4110         }
4111
4112         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4113         if (reta_size != sp_reta_size) {
4114                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4115                         "(%d) doesn't match the number hardware can supported "
4116                         "(%d)\n", reta_size, sp_reta_size);
4117                 return -EINVAL;
4118         }
4119
4120         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4121                 idx = i / RTE_RETA_GROUP_SIZE;
4122                 shift = i % RTE_RETA_GROUP_SIZE;
4123                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4124                                                 IXGBE_4_BIT_MASK);
4125                 if (!mask)
4126                         continue;
4127                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4128                 if (mask == IXGBE_4_BIT_MASK)
4129                         r = 0;
4130                 else
4131                         r = IXGBE_READ_REG(hw, reta_reg);
4132                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4133                         if (mask & (0x1 << j))
4134                                 reta |= reta_conf[idx].reta[shift + j] <<
4135                                                         (CHAR_BIT * j);
4136                         else
4137                                 reta |= r & (IXGBE_8_BIT_MASK <<
4138                                                 (CHAR_BIT * j));
4139                 }
4140                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4141         }
4142
4143         return 0;
4144 }
4145
4146 static int
4147 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4148                          struct rte_eth_rss_reta_entry64 *reta_conf,
4149                          uint16_t reta_size)
4150 {
4151         uint16_t i, sp_reta_size;
4152         uint8_t j, mask;
4153         uint32_t reta;
4154         uint16_t idx, shift;
4155         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4156         uint32_t reta_reg;
4157
4158         PMD_INIT_FUNC_TRACE();
4159         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4160         if (reta_size != sp_reta_size) {
4161                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4162                         "(%d) doesn't match the number hardware can supported "
4163                         "(%d)\n", reta_size, sp_reta_size);
4164                 return -EINVAL;
4165         }
4166
4167         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4168                 idx = i / RTE_RETA_GROUP_SIZE;
4169                 shift = i % RTE_RETA_GROUP_SIZE;
4170                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4171                                                 IXGBE_4_BIT_MASK);
4172                 if (!mask)
4173                         continue;
4174
4175                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4176                 reta = IXGBE_READ_REG(hw, reta_reg);
4177                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4178                         if (mask & (0x1 << j))
4179                                 reta_conf[idx].reta[shift + j] =
4180                                         ((reta >> (CHAR_BIT * j)) &
4181                                                 IXGBE_8_BIT_MASK);
4182                 }
4183         }
4184
4185         return 0;
4186 }
4187
4188 static void
4189 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4190                                 uint32_t index, uint32_t pool)
4191 {
4192         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4193         uint32_t enable_addr = 1;
4194
4195         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4196 }
4197
4198 static void
4199 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4200 {
4201         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4202
4203         ixgbe_clear_rar(hw, index);
4204 }
4205
4206 static void
4207 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4208 {
4209         ixgbe_remove_rar(dev, 0);
4210
4211         ixgbe_add_rar(dev, addr, 0, 0);
4212 }
4213
4214 int
4215 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4216                 struct ether_addr *mac_addr)
4217 {
4218         struct ixgbe_hw *hw;
4219         struct ixgbe_vf_info *vfinfo;
4220         int rar_entry;
4221         uint8_t *new_mac = (uint8_t *)(mac_addr);
4222         struct rte_eth_dev *dev;
4223         struct rte_eth_dev_info dev_info;
4224
4225         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4226
4227         dev = &rte_eth_devices[port];
4228         rte_eth_dev_info_get(port, &dev_info);
4229
4230         if (vf >= dev_info.max_vfs)
4231                 return -EINVAL;
4232
4233         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4234         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4235         rar_entry = hw->mac.num_rar_entries - (vf + 1);
4236
4237         if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4238                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4239                                 ETHER_ADDR_LEN);
4240                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4241                                 IXGBE_RAH_AV);
4242         }
4243         return -EINVAL;
4244 }
4245
4246 static int
4247 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4248 {
4249         uint32_t hlreg0;
4250         uint32_t maxfrs;
4251         struct ixgbe_hw *hw;
4252         struct rte_eth_dev_info dev_info;
4253         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4254
4255         ixgbe_dev_info_get(dev, &dev_info);
4256
4257         /* check that mtu is within the allowed range */
4258         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4259                 return -EINVAL;
4260
4261         /* refuse mtu that requires the support of scattered packets when this
4262          * feature has not been enabled before.
4263          */
4264         if (!dev->data->scattered_rx &&
4265             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4266              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4267                 return -EINVAL;
4268
4269         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4270         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4271
4272         /* switch to jumbo mode if needed */
4273         if (frame_size > ETHER_MAX_LEN) {
4274                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4275                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4276         } else {
4277                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4278                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4279         }
4280         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4281
4282         /* update max frame size */
4283         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4284
4285         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4286         maxfrs &= 0x0000FFFF;
4287         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4288         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4289
4290         return 0;
4291 }
4292
4293 /*
4294  * Virtual Function operations
4295  */
4296 static void
4297 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4298 {
4299         PMD_INIT_FUNC_TRACE();
4300
4301         /* Clear interrupt mask to stop from interrupts being generated */
4302         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4303
4304         IXGBE_WRITE_FLUSH(hw);
4305 }
4306
4307 static void
4308 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4309 {
4310         PMD_INIT_FUNC_TRACE();
4311
4312         /* VF enable interrupt autoclean */
4313         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4314         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4315         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4316
4317         IXGBE_WRITE_FLUSH(hw);
4318 }
4319
4320 static int
4321 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4322 {
4323         struct rte_eth_conf *conf = &dev->data->dev_conf;
4324         struct ixgbe_adapter *adapter =
4325                         (struct ixgbe_adapter *)dev->data->dev_private;
4326
4327         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4328                      dev->data->port_id);
4329
4330         /*
4331          * VF has no ability to enable/disable HW CRC
4332          * Keep the persistent behavior the same as Host PF
4333          */
4334 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4335         if (!conf->rxmode.hw_strip_crc) {
4336                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4337                 conf->rxmode.hw_strip_crc = 1;
4338         }
4339 #else
4340         if (conf->rxmode.hw_strip_crc) {
4341                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4342                 conf->rxmode.hw_strip_crc = 0;
4343         }
4344 #endif
4345
4346         /*
4347          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4348          * allocation or vector Rx preconditions we will reset it.
4349          */
4350         adapter->rx_bulk_alloc_allowed = true;
4351         adapter->rx_vec_allowed = true;
4352
4353         return 0;
4354 }
4355
4356 static int
4357 ixgbevf_dev_start(struct rte_eth_dev *dev)
4358 {
4359         struct ixgbe_hw *hw =
4360                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4361         uint32_t intr_vector = 0;
4362         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4363         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4364
4365         int err, mask = 0;
4366
4367         PMD_INIT_FUNC_TRACE();
4368
4369         hw->mac.ops.reset_hw(hw);
4370         hw->mac.get_link_status = true;
4371
4372         /* negotiate mailbox API version to use with the PF. */
4373         ixgbevf_negotiate_api(hw);
4374
4375         ixgbevf_dev_tx_init(dev);
4376
4377         /* This can fail when allocating mbufs for descriptor rings */
4378         err = ixgbevf_dev_rx_init(dev);
4379         if (err) {
4380                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4381                 ixgbe_dev_clear_queues(dev);
4382                 return err;
4383         }
4384
4385         /* Set vfta */
4386         ixgbevf_set_vfta_all(dev, 1);
4387
4388         /* Set HW strip */
4389         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4390                 ETH_VLAN_EXTEND_MASK;
4391         ixgbevf_vlan_offload_set(dev, mask);
4392
4393         ixgbevf_dev_rxtx_start(dev);
4394
4395         /* check and configure queue intr-vector mapping */
4396         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4397                 intr_vector = dev->data->nb_rx_queues;
4398                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4399                         return -1;
4400         }
4401
4402         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4403                 intr_handle->intr_vec =
4404                         rte_zmalloc("intr_vec",
4405                                     dev->data->nb_rx_queues * sizeof(int), 0);
4406                 if (intr_handle->intr_vec == NULL) {
4407                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4408                                      " intr_vec\n", dev->data->nb_rx_queues);
4409                         return -ENOMEM;
4410                 }
4411         }
4412         ixgbevf_configure_msix(dev);
4413
4414         rte_intr_enable(intr_handle);
4415
4416         /* Re-enable interrupt for VF */
4417         ixgbevf_intr_enable(hw);
4418
4419         return 0;
4420 }
4421
4422 static void
4423 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4424 {
4425         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4426         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4427         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4428
4429         PMD_INIT_FUNC_TRACE();
4430
4431         ixgbevf_intr_disable(hw);
4432
4433         hw->adapter_stopped = 1;
4434         ixgbe_stop_adapter(hw);
4435
4436         /*
4437           * Clear what we set, but we still keep shadow_vfta to
4438           * restore after device starts
4439           */
4440         ixgbevf_set_vfta_all(dev, 0);
4441
4442         /* Clear stored conf */
4443         dev->data->scattered_rx = 0;
4444
4445         ixgbe_dev_clear_queues(dev);
4446
4447         /* Clean datapath event and queue/vec mapping */
4448         rte_intr_efd_disable(intr_handle);
4449         if (intr_handle->intr_vec != NULL) {
4450                 rte_free(intr_handle->intr_vec);
4451                 intr_handle->intr_vec = NULL;
4452         }
4453 }
4454
4455 static void
4456 ixgbevf_dev_close(struct rte_eth_dev *dev)
4457 {
4458         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4459
4460         PMD_INIT_FUNC_TRACE();
4461
4462         ixgbe_reset_hw(hw);
4463
4464         ixgbevf_dev_stop(dev);
4465
4466         ixgbe_dev_free_queues(dev);
4467
4468         /**
4469          * Remove the VF MAC address ro ensure
4470          * that the VF traffic goes to the PF
4471          * after stop, close and detach of the VF
4472          **/
4473         ixgbevf_remove_mac_addr(dev, 0);
4474 }
4475
4476 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4477 {
4478         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4479         struct ixgbe_vfta *shadow_vfta =
4480                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4481         int i = 0, j = 0, vfta = 0, mask = 1;
4482
4483         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4484                 vfta = shadow_vfta->vfta[i];
4485                 if (vfta) {
4486                         mask = 1;
4487                         for (j = 0; j < 32; j++) {
4488                                 if (vfta & mask)
4489                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4490                                                        on, false);
4491                                 mask <<= 1;
4492                         }
4493                 }
4494         }
4495
4496 }
4497
4498 static int
4499 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4500 {
4501         struct ixgbe_hw *hw =
4502                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4503         struct ixgbe_vfta *shadow_vfta =
4504                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4505         uint32_t vid_idx = 0;
4506         uint32_t vid_bit = 0;
4507         int ret = 0;
4508
4509         PMD_INIT_FUNC_TRACE();
4510
4511         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4512         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4513         if (ret) {
4514                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4515                 return ret;
4516         }
4517         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4518         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4519
4520         /* Save what we set and retore it after device reset */
4521         if (on)
4522                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4523         else
4524                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4525
4526         return 0;
4527 }
4528
4529 static void
4530 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4531 {
4532         struct ixgbe_hw *hw =
4533                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4534         uint32_t ctrl;
4535
4536         PMD_INIT_FUNC_TRACE();
4537
4538         if (queue >= hw->mac.max_rx_queues)
4539                 return;
4540
4541         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4542         if (on)
4543                 ctrl |= IXGBE_RXDCTL_VME;
4544         else
4545                 ctrl &= ~IXGBE_RXDCTL_VME;
4546         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4547
4548         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4549 }
4550
4551 static void
4552 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4553 {
4554         struct ixgbe_hw *hw =
4555                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4556         uint16_t i;
4557         int on = 0;
4558
4559         /* VF function only support hw strip feature, others are not support */
4560         if (mask & ETH_VLAN_STRIP_MASK) {
4561                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4562
4563                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4564                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4565         }
4566 }
4567
4568 static int
4569 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4570 {
4571         uint32_t reg_val;
4572
4573         /* we only need to do this if VMDq is enabled */
4574         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4575         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4576                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4577                 return -1;
4578         }
4579
4580         return 0;
4581 }
4582
4583 static uint32_t
4584 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4585 {
4586         uint32_t vector = 0;
4587
4588         switch (hw->mac.mc_filter_type) {
4589         case 0:   /* use bits [47:36] of the address */
4590                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4591                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4592                 break;
4593         case 1:   /* use bits [46:35] of the address */
4594                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4595                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4596                 break;
4597         case 2:   /* use bits [45:34] of the address */
4598                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4599                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4600                 break;
4601         case 3:   /* use bits [43:32] of the address */
4602                 vector = ((uc_addr->addr_bytes[4]) |
4603                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4604                 break;
4605         default:  /* Invalid mc_filter_type */
4606                 break;
4607         }
4608
4609         /* vector can only be 12-bits or boundary will be exceeded */
4610         vector &= 0xFFF;
4611         return vector;
4612 }
4613
4614 static int
4615 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4616                         uint8_t on)
4617 {
4618         uint32_t vector;
4619         uint32_t uta_idx;
4620         uint32_t reg_val;
4621         uint32_t uta_shift;
4622         uint32_t rc;
4623         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4624         const uint32_t ixgbe_uta_bit_shift = 5;
4625         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4626         const uint32_t bit1 = 0x1;
4627
4628         struct ixgbe_hw *hw =
4629                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4630         struct ixgbe_uta_info *uta_info =
4631                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4632
4633         /* The UTA table only exists on 82599 hardware and newer */
4634         if (hw->mac.type < ixgbe_mac_82599EB)
4635                 return -ENOTSUP;
4636
4637         vector = ixgbe_uta_vector(hw, mac_addr);
4638         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4639         uta_shift = vector & ixgbe_uta_bit_mask;
4640
4641         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4642         if (rc == on)
4643                 return 0;
4644
4645         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4646         if (on) {
4647                 uta_info->uta_in_use++;
4648                 reg_val |= (bit1 << uta_shift);
4649                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4650         } else {
4651                 uta_info->uta_in_use--;
4652                 reg_val &= ~(bit1 << uta_shift);
4653                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4654         }
4655
4656         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4657
4658         if (uta_info->uta_in_use > 0)
4659                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4660                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4661         else
4662                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4663
4664         return 0;
4665 }
4666
4667 static int
4668 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4669 {
4670         int i;
4671         struct ixgbe_hw *hw =
4672                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4673         struct ixgbe_uta_info *uta_info =
4674                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4675
4676         /* The UTA table only exists on 82599 hardware and newer */
4677         if (hw->mac.type < ixgbe_mac_82599EB)
4678                 return -ENOTSUP;
4679
4680         if (on) {
4681                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4682                         uta_info->uta_shadow[i] = ~0;
4683                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4684                 }
4685         } else {
4686                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4687                         uta_info->uta_shadow[i] = 0;
4688                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4689                 }
4690         }
4691         return 0;
4692
4693 }
4694
4695 uint32_t
4696 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4697 {
4698         uint32_t new_val = orig_val;
4699
4700         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4701                 new_val |= IXGBE_VMOLR_AUPE;
4702         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4703                 new_val |= IXGBE_VMOLR_ROMPE;
4704         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4705                 new_val |= IXGBE_VMOLR_ROPE;
4706         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4707                 new_val |= IXGBE_VMOLR_BAM;
4708         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4709                 new_val |= IXGBE_VMOLR_MPE;
4710
4711         return new_val;
4712 }
4713
4714 static int
4715 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4716                                uint16_t rx_mask, uint8_t on)
4717 {
4718         int val = 0;
4719
4720         struct ixgbe_hw *hw =
4721                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4722         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4723
4724         if (hw->mac.type == ixgbe_mac_82598EB) {
4725                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4726                              " on 82599 hardware and newer");
4727                 return -ENOTSUP;
4728         }
4729         if (ixgbe_vmdq_mode_check(hw) < 0)
4730                 return -ENOTSUP;
4731
4732         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4733
4734         if (on)
4735                 vmolr |= val;
4736         else
4737                 vmolr &= ~val;
4738
4739         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4740
4741         return 0;
4742 }
4743
4744 static int
4745 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4746 {
4747         uint32_t reg, addr;
4748         uint32_t val;
4749         const uint8_t bit1 = 0x1;
4750
4751         struct ixgbe_hw *hw =
4752                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4753
4754         if (ixgbe_vmdq_mode_check(hw) < 0)
4755                 return -ENOTSUP;
4756
4757         if (pool >= ETH_64_POOLS)
4758                 return -EINVAL;
4759
4760         /* for pool >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
4761         if (pool >= 32) {
4762                 addr = IXGBE_VFRE(1);
4763                 val = bit1 << (pool - 32);
4764         } else {
4765                 addr = IXGBE_VFRE(0);
4766                 val = bit1 << pool;
4767         }
4768
4769         reg = IXGBE_READ_REG(hw, addr);
4770
4771         if (on)
4772                 reg |= val;
4773         else
4774                 reg &= ~val;
4775
4776         IXGBE_WRITE_REG(hw, addr, reg);
4777
4778         return 0;
4779 }
4780
4781 static int
4782 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4783 {
4784         uint32_t reg, addr;
4785         uint32_t val;
4786         const uint8_t bit1 = 0x1;
4787
4788         struct ixgbe_hw *hw =
4789                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4790
4791         if (ixgbe_vmdq_mode_check(hw) < 0)
4792                 return -ENOTSUP;
4793
4794         if (pool >= ETH_64_POOLS)
4795                 return -EINVAL;
4796
4797         /* for pool >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
4798         if (pool >= 32) {
4799                 addr = IXGBE_VFTE(1);
4800                 val = bit1 << (pool - 32);
4801         } else {
4802                 addr = IXGBE_VFTE(0);
4803                 val = bit1 << pool;
4804         }
4805
4806         reg = IXGBE_READ_REG(hw, addr);
4807
4808         if (on)
4809                 reg |= val;
4810         else
4811                 reg &= ~val;
4812
4813         IXGBE_WRITE_REG(hw, addr, reg);
4814
4815         return 0;
4816 }
4817
4818 static int
4819 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4820                         uint64_t pool_mask, uint8_t vlan_on)
4821 {
4822         int ret = 0;
4823         uint16_t pool_idx;
4824         struct ixgbe_hw *hw =
4825                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4826
4827         if (ixgbe_vmdq_mode_check(hw) < 0)
4828                 return -ENOTSUP;
4829         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4830                 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4831                         ret = hw->mac.ops.set_vfta(hw, vlan, pool_idx,
4832                                                    vlan_on, false);
4833                         if (ret < 0)
4834                                 return ret;
4835                 }
4836         }
4837
4838         return ret;
4839 }
4840
4841 int
4842 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4843 {
4844         struct ixgbe_hw *hw;
4845         struct ixgbe_mac_info *mac;
4846         struct rte_eth_dev *dev;
4847         struct rte_eth_dev_info dev_info;
4848
4849         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4850
4851         dev = &rte_eth_devices[port];
4852         rte_eth_dev_info_get(port, &dev_info);
4853
4854         if (vf >= dev_info.max_vfs)
4855                 return -EINVAL;
4856
4857         if (on > 1)
4858                 return -EINVAL;
4859
4860         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4861         mac = &hw->mac;
4862
4863         mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4864
4865         return 0;
4866 }
4867
4868 int
4869 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4870 {
4871         struct ixgbe_hw *hw;
4872         struct ixgbe_mac_info *mac;
4873         struct rte_eth_dev *dev;
4874         struct rte_eth_dev_info dev_info;
4875
4876         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4877
4878         dev = &rte_eth_devices[port];
4879         rte_eth_dev_info_get(port, &dev_info);
4880
4881         if (vf >= dev_info.max_vfs)
4882                 return -EINVAL;
4883
4884         if (on > 1)
4885                 return -EINVAL;
4886
4887         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4888         mac = &hw->mac;
4889         mac->ops.set_mac_anti_spoofing(hw, on, vf);
4890
4891         return 0;
4892 }
4893
4894 int
4895 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4896 {
4897         struct ixgbe_hw *hw;
4898         uint32_t ctrl;
4899         struct rte_eth_dev *dev;
4900         struct rte_eth_dev_info dev_info;
4901
4902         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4903
4904         dev = &rte_eth_devices[port];
4905         rte_eth_dev_info_get(port, &dev_info);
4906
4907         if (vf >= dev_info.max_vfs)
4908                 return -EINVAL;
4909
4910         if (vlan_id > 4095)
4911                 return -EINVAL;
4912
4913         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4914         ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4915         if (vlan_id) {
4916                 ctrl = vlan_id;
4917                 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4918         } else {
4919                 ctrl = 0;
4920         }
4921
4922         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4923
4924         return 0;
4925 }
4926
4927 int
4928 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4929 {
4930         struct ixgbe_hw *hw;
4931         uint32_t ctrl;
4932         struct rte_eth_dev *dev;
4933
4934         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4935
4936         dev = &rte_eth_devices[port];
4937
4938         if (on > 1)
4939                 return -EINVAL;
4940
4941         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4942         ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4943         /* enable or disable VMDQ loopback */
4944         if (on)
4945                 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
4946         else
4947                 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4948
4949         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
4950
4951         return 0;
4952 }
4953
4954 int
4955 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
4956 {
4957         struct ixgbe_hw *hw;
4958         uint32_t reg_value;
4959         int i;
4960         int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
4961         struct rte_eth_dev *dev;
4962
4963         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4964
4965         dev = &rte_eth_devices[port];
4966
4967         if (on > 1)
4968                 return -EINVAL;
4969
4970         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4971         for (i = 0; i <= num_queues; i++) {
4972                 reg_value = IXGBE_QDE_WRITE |
4973                                 (i << IXGBE_QDE_IDX_SHIFT) |
4974                                 (on & IXGBE_QDE_ENABLE);
4975                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
4976         }
4977
4978         return 0;
4979 }
4980
4981 int
4982 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
4983 {
4984         struct ixgbe_hw *hw;
4985         uint32_t reg_value;
4986         struct rte_eth_dev *dev;
4987         struct rte_eth_dev_info dev_info;
4988
4989         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4990
4991         dev = &rte_eth_devices[port];
4992         rte_eth_dev_info_get(port, &dev_info);
4993
4994         /* only support VF's 0 to 63 */
4995         if ((vf >= dev_info.max_vfs) || (vf > 63))
4996                 return -EINVAL;
4997
4998         if (on > 1)
4999                 return -EINVAL;
5000
5001         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5002         reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
5003         if (on)
5004                 reg_value |= IXGBE_SRRCTL_DROP_EN;
5005         else
5006                 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
5007
5008         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
5009
5010         return 0;
5011 }
5012
5013 int
5014 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
5015 {
5016         struct rte_eth_dev *dev;
5017         struct rte_eth_dev_info dev_info;
5018         uint16_t queues_per_pool;
5019         uint32_t q;
5020
5021         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5022
5023         dev = &rte_eth_devices[port];
5024         rte_eth_dev_info_get(port, &dev_info);
5025
5026         if (vf >= dev_info.max_vfs)
5027                 return -EINVAL;
5028
5029         if (on > 1)
5030                 return -EINVAL;
5031
5032         RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
5033
5034         /* The PF has 128 queue pairs and in SRIOV configuration
5035          * those queues will be assigned to VF's, so RXDCTL
5036          * registers will be dealing with queues which will be
5037          * assigned to VF's.
5038          * Let's say we have SRIOV configured with 31 VF's then the
5039          * first 124 queues 0-123 will be allocated to VF's and only
5040          * the last 4 queues 123-127 will be assigned to the PF.
5041          */
5042
5043         queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
5044
5045         for (q = 0; q < queues_per_pool; q++)
5046                 (*dev->dev_ops->vlan_strip_queue_set)(dev,
5047                                 q + vf * queues_per_pool, on);
5048         return 0;
5049 }
5050
5051 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5052 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5053 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5054 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5055 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5056         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5057         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5058
5059 static int
5060 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5061                         struct rte_eth_mirror_conf *mirror_conf,
5062                         uint8_t rule_id, uint8_t on)
5063 {
5064         uint32_t mr_ctl, vlvf;
5065         uint32_t mp_lsb = 0;
5066         uint32_t mv_msb = 0;
5067         uint32_t mv_lsb = 0;
5068         uint32_t mp_msb = 0;
5069         uint8_t i = 0;
5070         int reg_index = 0;
5071         uint64_t vlan_mask = 0;
5072
5073         const uint8_t pool_mask_offset = 32;
5074         const uint8_t vlan_mask_offset = 32;
5075         const uint8_t dst_pool_offset = 8;
5076         const uint8_t rule_mr_offset  = 4;
5077         const uint8_t mirror_rule_mask = 0x0F;
5078
5079         struct ixgbe_mirror_info *mr_info =
5080                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5081         struct ixgbe_hw *hw =
5082                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5083         uint8_t mirror_type = 0;
5084
5085         if (ixgbe_vmdq_mode_check(hw) < 0)
5086                 return -ENOTSUP;
5087
5088         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5089                 return -EINVAL;
5090
5091         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5092                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5093                         mirror_conf->rule_type);
5094                 return -EINVAL;
5095         }
5096
5097         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5098                 mirror_type |= IXGBE_MRCTL_VLME;
5099                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5100                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5101                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5102                                 /* search vlan id related pool vlan filter index */
5103                                 reg_index = ixgbe_find_vlvf_slot(hw,
5104                                                  mirror_conf->vlan.vlan_id[i],
5105                                                  false);
5106                                 if (reg_index < 0)
5107                                         return -EINVAL;
5108                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5109                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5110                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5111                                       mirror_conf->vlan.vlan_id[i]))
5112                                         vlan_mask |= (1ULL << reg_index);
5113                                 else
5114                                         return -EINVAL;
5115                         }
5116                 }
5117
5118                 if (on) {
5119                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5120                         mv_msb = vlan_mask >> vlan_mask_offset;
5121
5122                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5123                                                 mirror_conf->vlan.vlan_mask;
5124                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5125                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5126                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5127                                                 mirror_conf->vlan.vlan_id[i];
5128                         }
5129                 } else {
5130                         mv_lsb = 0;
5131                         mv_msb = 0;
5132                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5133                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5134                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5135                 }
5136         }
5137
5138         /*
5139          * if enable pool mirror, write related pool mask register,if disable
5140          * pool mirror, clear PFMRVM register
5141          */
5142         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5143                 mirror_type |= IXGBE_MRCTL_VPME;
5144                 if (on) {
5145                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5146                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5147                         mr_info->mr_conf[rule_id].pool_mask =
5148                                         mirror_conf->pool_mask;
5149
5150                 } else {
5151                         mp_lsb = 0;
5152                         mp_msb = 0;
5153                         mr_info->mr_conf[rule_id].pool_mask = 0;
5154                 }
5155         }
5156         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5157                 mirror_type |= IXGBE_MRCTL_UPME;
5158         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5159                 mirror_type |= IXGBE_MRCTL_DPME;
5160
5161         /* read  mirror control register and recalculate it */
5162         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5163
5164         if (on) {
5165                 mr_ctl |= mirror_type;
5166                 mr_ctl &= mirror_rule_mask;
5167                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5168         } else
5169                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5170
5171         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5172         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5173
5174         /* write mirrror control  register */
5175         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5176
5177         /* write pool mirrror control  register */
5178         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5179                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5180                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5181                                 mp_msb);
5182         }
5183         /* write VLAN mirrror control  register */
5184         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5185                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5186                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5187                                 mv_msb);
5188         }
5189
5190         return 0;
5191 }
5192
5193 static int
5194 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5195 {
5196         int mr_ctl = 0;
5197         uint32_t lsb_val = 0;
5198         uint32_t msb_val = 0;
5199         const uint8_t rule_mr_offset = 4;
5200
5201         struct ixgbe_hw *hw =
5202                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5203         struct ixgbe_mirror_info *mr_info =
5204                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5205
5206         if (ixgbe_vmdq_mode_check(hw) < 0)
5207                 return -ENOTSUP;
5208
5209         memset(&mr_info->mr_conf[rule_id], 0,
5210                 sizeof(struct rte_eth_mirror_conf));
5211
5212         /* clear PFVMCTL register */
5213         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5214
5215         /* clear pool mask register */
5216         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5217         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5218
5219         /* clear vlan mask register */
5220         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5221         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5222
5223         return 0;
5224 }
5225
5226 static int
5227 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5228 {
5229         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5230         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5231         uint32_t mask;
5232         struct ixgbe_hw *hw =
5233                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5234
5235         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5236         mask |= (1 << IXGBE_MISC_VEC_ID);
5237         RTE_SET_USED(queue_id);
5238         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5239
5240         rte_intr_enable(intr_handle);
5241
5242         return 0;
5243 }
5244
5245 static int
5246 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5247 {
5248         uint32_t mask;
5249         struct ixgbe_hw *hw =
5250                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5251
5252         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5253         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5254         RTE_SET_USED(queue_id);
5255         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5256
5257         return 0;
5258 }
5259
5260 static int
5261 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5262 {
5263         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5264         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5265         uint32_t mask;
5266         struct ixgbe_hw *hw =
5267                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5268         struct ixgbe_interrupt *intr =
5269                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5270
5271         if (queue_id < 16) {
5272                 ixgbe_disable_intr(hw);
5273                 intr->mask |= (1 << queue_id);
5274                 ixgbe_enable_intr(dev);
5275         } else if (queue_id < 32) {
5276                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5277                 mask &= (1 << queue_id);
5278                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5279         } else if (queue_id < 64) {
5280                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5281                 mask &= (1 << (queue_id - 32));
5282                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5283         }
5284         rte_intr_enable(intr_handle);
5285
5286         return 0;
5287 }
5288
5289 static int
5290 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5291 {
5292         uint32_t mask;
5293         struct ixgbe_hw *hw =
5294                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5295         struct ixgbe_interrupt *intr =
5296                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5297
5298         if (queue_id < 16) {
5299                 ixgbe_disable_intr(hw);
5300                 intr->mask &= ~(1 << queue_id);
5301                 ixgbe_enable_intr(dev);
5302         } else if (queue_id < 32) {
5303                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5304                 mask &= ~(1 << queue_id);
5305                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5306         } else if (queue_id < 64) {
5307                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5308                 mask &= ~(1 << (queue_id - 32));
5309                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5310         }
5311
5312         return 0;
5313 }
5314
5315 static void
5316 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5317                      uint8_t queue, uint8_t msix_vector)
5318 {
5319         uint32_t tmp, idx;
5320
5321         if (direction == -1) {
5322                 /* other causes */
5323                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5324                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5325                 tmp &= ~0xFF;
5326                 tmp |= msix_vector;
5327                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5328         } else {
5329                 /* rx or tx cause */
5330                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5331                 idx = ((16 * (queue & 1)) + (8 * direction));
5332                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5333                 tmp &= ~(0xFF << idx);
5334                 tmp |= (msix_vector << idx);
5335                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5336         }
5337 }
5338
5339 /**
5340  * set the IVAR registers, mapping interrupt causes to vectors
5341  * @param hw
5342  *  pointer to ixgbe_hw struct
5343  * @direction
5344  *  0 for Rx, 1 for Tx, -1 for other causes
5345  * @queue
5346  *  queue to map the corresponding interrupt to
5347  * @msix_vector
5348  *  the vector to map to the corresponding queue
5349  */
5350 static void
5351 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5352                    uint8_t queue, uint8_t msix_vector)
5353 {
5354         uint32_t tmp, idx;
5355
5356         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5357         if (hw->mac.type == ixgbe_mac_82598EB) {
5358                 if (direction == -1)
5359                         direction = 0;
5360                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5361                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5362                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5363                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5364                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5365         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5366                         (hw->mac.type == ixgbe_mac_X540)) {
5367                 if (direction == -1) {
5368                         /* other causes */
5369                         idx = ((queue & 1) * 8);
5370                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5371                         tmp &= ~(0xFF << idx);
5372                         tmp |= (msix_vector << idx);
5373                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5374                 } else {
5375                         /* rx or tx causes */
5376                         idx = ((16 * (queue & 1)) + (8 * direction));
5377                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5378                         tmp &= ~(0xFF << idx);
5379                         tmp |= (msix_vector << idx);
5380                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5381                 }
5382         }
5383 }
5384
5385 static void
5386 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5387 {
5388         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5389         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5390         struct ixgbe_hw *hw =
5391                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5392         uint32_t q_idx;
5393         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5394
5395         /* Configure VF other cause ivar */
5396         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5397
5398         /* won't configure msix register if no mapping is done
5399          * between intr vector and event fd.
5400          */
5401         if (!rte_intr_dp_is_en(intr_handle))
5402                 return;
5403
5404         /* Configure all RX queues of VF */
5405         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5406                 /* Force all queue use vector 0,
5407                  * as IXGBE_VF_MAXMSIVECOTR = 1
5408                  */
5409                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5410                 intr_handle->intr_vec[q_idx] = vector_idx;
5411         }
5412 }
5413
5414 /**
5415  * Sets up the hardware to properly generate MSI-X interrupts
5416  * @hw
5417  *  board private structure
5418  */
5419 static void
5420 ixgbe_configure_msix(struct rte_eth_dev *dev)
5421 {
5422         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5423         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5424         struct ixgbe_hw *hw =
5425                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5426         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5427         uint32_t vec = IXGBE_MISC_VEC_ID;
5428         uint32_t mask;
5429         uint32_t gpie;
5430
5431         /* won't configure msix register if no mapping is done
5432          * between intr vector and event fd
5433          */
5434         if (!rte_intr_dp_is_en(intr_handle))
5435                 return;
5436
5437         if (rte_intr_allow_others(intr_handle))
5438                 vec = base = IXGBE_RX_VEC_START;
5439
5440         /* setup GPIE for MSI-x mode */
5441         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5442         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5443                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5444         /* auto clearing and auto setting corresponding bits in EIMS
5445          * when MSI-X interrupt is triggered
5446          */
5447         if (hw->mac.type == ixgbe_mac_82598EB) {
5448                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5449         } else {
5450                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5451                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5452         }
5453         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5454
5455         /* Populate the IVAR table and set the ITR values to the
5456          * corresponding register.
5457          */
5458         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5459              queue_id++) {
5460                 /* by default, 1:1 mapping */
5461                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5462                 intr_handle->intr_vec[queue_id] = vec;
5463                 if (vec < base + intr_handle->nb_efd - 1)
5464                         vec++;
5465         }
5466
5467         switch (hw->mac.type) {
5468         case ixgbe_mac_82598EB:
5469                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5470                                    IXGBE_MISC_VEC_ID);
5471                 break;
5472         case ixgbe_mac_82599EB:
5473         case ixgbe_mac_X540:
5474                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5475                 break;
5476         default:
5477                 break;
5478         }
5479         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5480                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5481
5482         /* set up to autoclear timer, and the vectors */
5483         mask = IXGBE_EIMS_ENABLE_MASK;
5484         mask &= ~(IXGBE_EIMS_OTHER |
5485                   IXGBE_EIMS_MAILBOX |
5486                   IXGBE_EIMS_LSC);
5487
5488         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5489 }
5490
5491 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5492         uint16_t queue_idx, uint16_t tx_rate)
5493 {
5494         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5495         uint32_t rf_dec, rf_int;
5496         uint32_t bcnrc_val;
5497         uint16_t link_speed = dev->data->dev_link.link_speed;
5498
5499         if (queue_idx >= hw->mac.max_tx_queues)
5500                 return -EINVAL;
5501
5502         if (tx_rate != 0) {
5503                 /* Calculate the rate factor values to set */
5504                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5505                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5506                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5507
5508                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5509                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5510                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5511                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5512         } else {
5513                 bcnrc_val = 0;
5514         }
5515
5516         /*
5517          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5518          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5519          * set as 0x4.
5520          */
5521         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5522                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5523                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5524                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5525                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5526         else
5527                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5528                         IXGBE_MMW_SIZE_DEFAULT);
5529
5530         /* Set RTTBCNRC of queue X */
5531         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5532         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5533         IXGBE_WRITE_FLUSH(hw);
5534
5535         return 0;
5536 }
5537
5538 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
5539         uint16_t tx_rate, uint64_t q_msk)
5540 {
5541         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5542         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5543         struct ixgbe_vf_info *vfinfo =
5544                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5545         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5546         uint32_t queue_stride =
5547                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5548         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
5549         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
5550         uint16_t total_rate = 0;
5551
5552         if (queue_end >= hw->mac.max_tx_queues)
5553                 return -EINVAL;
5554
5555         if (vfinfo != NULL) {
5556                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5557                         if (vf_idx == vf)
5558                                 continue;
5559                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5560                                 idx++)
5561                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5562                 }
5563         } else
5564                 return -EINVAL;
5565
5566         /* Store tx_rate for this vf. */
5567         for (idx = 0; idx < nb_q_per_pool; idx++) {
5568                 if (((uint64_t)0x1 << idx) & q_msk) {
5569                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5570                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5571                         total_rate += tx_rate;
5572                 }
5573         }
5574
5575         if (total_rate > dev->data->dev_link.link_speed) {
5576                 /*
5577                  * Reset stored TX rate of the VF if it causes exceed
5578                  * link speed.
5579                  */
5580                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5581                 return -EINVAL;
5582         }
5583
5584         /* Set RTTBCNRC of each queue/pool for vf X  */
5585         for (; queue_idx <= queue_end; queue_idx++) {
5586                 if (0x1 & q_msk)
5587                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5588                 q_msk = q_msk >> 1;
5589         }
5590
5591         return 0;
5592 }
5593
5594 static void
5595 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5596                      __attribute__((unused)) uint32_t index,
5597                      __attribute__((unused)) uint32_t pool)
5598 {
5599         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5600         int diag;
5601
5602         /*
5603          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5604          * operation. Trap this case to avoid exhausting the [very limited]
5605          * set of PF resources used to store VF MAC addresses.
5606          */
5607         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5608                 return;
5609         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5610         if (diag == 0)
5611                 return;
5612         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5613 }
5614
5615 static void
5616 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5617 {
5618         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5619         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5620         struct ether_addr *mac_addr;
5621         uint32_t i;
5622         int diag;
5623
5624         /*
5625          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5626          * not support the deletion of a given MAC address.
5627          * Instead, it imposes to delete all MAC addresses, then to add again
5628          * all MAC addresses with the exception of the one to be deleted.
5629          */
5630         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5631
5632         /*
5633          * Add again all MAC addresses, with the exception of the deleted one
5634          * and of the permanent MAC address.
5635          */
5636         for (i = 0, mac_addr = dev->data->mac_addrs;
5637              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5638                 /* Skip the deleted MAC address */
5639                 if (i == index)
5640                         continue;
5641                 /* Skip NULL MAC addresses */
5642                 if (is_zero_ether_addr(mac_addr))
5643                         continue;
5644                 /* Skip the permanent MAC address */
5645                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5646                         continue;
5647                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5648                 if (diag != 0)
5649                         PMD_DRV_LOG(ERR,
5650                                     "Adding again MAC address "
5651                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5652                                     "diag=%d",
5653                                     mac_addr->addr_bytes[0],
5654                                     mac_addr->addr_bytes[1],
5655                                     mac_addr->addr_bytes[2],
5656                                     mac_addr->addr_bytes[3],
5657                                     mac_addr->addr_bytes[4],
5658                                     mac_addr->addr_bytes[5],
5659                                     diag);
5660         }
5661 }
5662
5663 static void
5664 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5665 {
5666         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5667
5668         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5669 }
5670
5671 #define MAC_TYPE_FILTER_SUP(type)    do {\
5672         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5673                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5674                 (type) != ixgbe_mac_X550EM_a)\
5675                 return -ENOTSUP;\
5676 } while (0)
5677
5678 static int
5679 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5680                         struct rte_eth_syn_filter *filter,
5681                         bool add)
5682 {
5683         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5684         uint32_t synqf;
5685
5686         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5687                 return -EINVAL;
5688
5689         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5690
5691         if (add) {
5692                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5693                         return -EINVAL;
5694                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5695                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5696
5697                 if (filter->hig_pri)
5698                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5699                 else
5700                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5701         } else {
5702                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5703                         return -ENOENT;
5704                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5705         }
5706         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5707         IXGBE_WRITE_FLUSH(hw);
5708         return 0;
5709 }
5710
5711 static int
5712 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5713                         struct rte_eth_syn_filter *filter)
5714 {
5715         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5716         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5717
5718         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5719                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5720                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5721                 return 0;
5722         }
5723         return -ENOENT;
5724 }
5725
5726 static int
5727 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5728                         enum rte_filter_op filter_op,
5729                         void *arg)
5730 {
5731         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5732         int ret;
5733
5734         MAC_TYPE_FILTER_SUP(hw->mac.type);
5735
5736         if (filter_op == RTE_ETH_FILTER_NOP)
5737                 return 0;
5738
5739         if (arg == NULL) {
5740                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5741                             filter_op);
5742                 return -EINVAL;
5743         }
5744
5745         switch (filter_op) {
5746         case RTE_ETH_FILTER_ADD:
5747                 ret = ixgbe_syn_filter_set(dev,
5748                                 (struct rte_eth_syn_filter *)arg,
5749                                 TRUE);
5750                 break;
5751         case RTE_ETH_FILTER_DELETE:
5752                 ret = ixgbe_syn_filter_set(dev,
5753                                 (struct rte_eth_syn_filter *)arg,
5754                                 FALSE);
5755                 break;
5756         case RTE_ETH_FILTER_GET:
5757                 ret = ixgbe_syn_filter_get(dev,
5758                                 (struct rte_eth_syn_filter *)arg);
5759                 break;
5760         default:
5761                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5762                 ret = -EINVAL;
5763                 break;
5764         }
5765
5766         return ret;
5767 }
5768
5769
5770 static inline enum ixgbe_5tuple_protocol
5771 convert_protocol_type(uint8_t protocol_value)
5772 {
5773         if (protocol_value == IPPROTO_TCP)
5774                 return IXGBE_FILTER_PROTOCOL_TCP;
5775         else if (protocol_value == IPPROTO_UDP)
5776                 return IXGBE_FILTER_PROTOCOL_UDP;
5777         else if (protocol_value == IPPROTO_SCTP)
5778                 return IXGBE_FILTER_PROTOCOL_SCTP;
5779         else
5780                 return IXGBE_FILTER_PROTOCOL_NONE;
5781 }
5782
5783 /*
5784  * add a 5tuple filter
5785  *
5786  * @param
5787  * dev: Pointer to struct rte_eth_dev.
5788  * index: the index the filter allocates.
5789  * filter: ponter to the filter that will be added.
5790  * rx_queue: the queue id the filter assigned to.
5791  *
5792  * @return
5793  *    - On success, zero.
5794  *    - On failure, a negative value.
5795  */
5796 static int
5797 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5798                         struct ixgbe_5tuple_filter *filter)
5799 {
5800         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5801         struct ixgbe_filter_info *filter_info =
5802                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5803         int i, idx, shift;
5804         uint32_t ftqf, sdpqf;
5805         uint32_t l34timir = 0;
5806         uint8_t mask = 0xff;
5807
5808         /*
5809          * look for an unused 5tuple filter index,
5810          * and insert the filter to list.
5811          */
5812         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5813                 idx = i / (sizeof(uint32_t) * NBBY);
5814                 shift = i % (sizeof(uint32_t) * NBBY);
5815                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5816                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5817                         filter->index = i;
5818                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5819                                           filter,
5820                                           entries);
5821                         break;
5822                 }
5823         }
5824         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5825                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5826                 return -ENOSYS;
5827         }
5828
5829         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5830                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5831         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5832
5833         ftqf = (uint32_t)(filter->filter_info.proto &
5834                 IXGBE_FTQF_PROTOCOL_MASK);
5835         ftqf |= (uint32_t)((filter->filter_info.priority &
5836                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5837         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5838                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5839         if (filter->filter_info.dst_ip_mask == 0)
5840                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5841         if (filter->filter_info.src_port_mask == 0)
5842                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5843         if (filter->filter_info.dst_port_mask == 0)
5844                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5845         if (filter->filter_info.proto_mask == 0)
5846                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5847         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5848         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5849         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5850
5851         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5852         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5853         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5854         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5855
5856         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5857         l34timir |= (uint32_t)(filter->queue <<
5858                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5859         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5860         return 0;
5861 }
5862
5863 /*
5864  * remove a 5tuple filter
5865  *
5866  * @param
5867  * dev: Pointer to struct rte_eth_dev.
5868  * filter: the pointer of the filter will be removed.
5869  */
5870 static void
5871 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5872                         struct ixgbe_5tuple_filter *filter)
5873 {
5874         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5875         struct ixgbe_filter_info *filter_info =
5876                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5877         uint16_t index = filter->index;
5878
5879         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5880                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5881         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5882         rte_free(filter);
5883
5884         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5885         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5886         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5887         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5888         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5889 }
5890
5891 static int
5892 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5893 {
5894         struct ixgbe_hw *hw;
5895         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5896
5897         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5898
5899         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5900                 return -EINVAL;
5901
5902         /* refuse mtu that requires the support of scattered packets when this
5903          * feature has not been enabled before.
5904          */
5905         if (!dev->data->scattered_rx &&
5906             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5907              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5908                 return -EINVAL;
5909
5910         /*
5911          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5912          * request of the version 2.0 of the mailbox API.
5913          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5914          * of the mailbox API.
5915          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5916          * prior to 3.11.33 which contains the following change:
5917          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5918          */
5919         ixgbevf_rlpml_set_vf(hw, max_frame);
5920
5921         /* update max frame size */
5922         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5923         return 0;
5924 }
5925
5926 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5927         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5928                 return -ENOTSUP;\
5929 } while (0)
5930
5931 static inline struct ixgbe_5tuple_filter *
5932 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5933                         struct ixgbe_5tuple_filter_info *key)
5934 {
5935         struct ixgbe_5tuple_filter *it;
5936
5937         TAILQ_FOREACH(it, filter_list, entries) {
5938                 if (memcmp(key, &it->filter_info,
5939                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5940                         return it;
5941                 }
5942         }
5943         return NULL;
5944 }
5945
5946 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5947 static inline int
5948 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5949                         struct ixgbe_5tuple_filter_info *filter_info)
5950 {
5951         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5952                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5953                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5954                 return -EINVAL;
5955
5956         switch (filter->dst_ip_mask) {
5957         case UINT32_MAX:
5958                 filter_info->dst_ip_mask = 0;
5959                 filter_info->dst_ip = filter->dst_ip;
5960                 break;
5961         case 0:
5962                 filter_info->dst_ip_mask = 1;
5963                 break;
5964         default:
5965                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5966                 return -EINVAL;
5967         }
5968
5969         switch (filter->src_ip_mask) {
5970         case UINT32_MAX:
5971                 filter_info->src_ip_mask = 0;
5972                 filter_info->src_ip = filter->src_ip;
5973                 break;
5974         case 0:
5975                 filter_info->src_ip_mask = 1;
5976                 break;
5977         default:
5978                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5979                 return -EINVAL;
5980         }
5981
5982         switch (filter->dst_port_mask) {
5983         case UINT16_MAX:
5984                 filter_info->dst_port_mask = 0;
5985                 filter_info->dst_port = filter->dst_port;
5986                 break;
5987         case 0:
5988                 filter_info->dst_port_mask = 1;
5989                 break;
5990         default:
5991                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5992                 return -EINVAL;
5993         }
5994
5995         switch (filter->src_port_mask) {
5996         case UINT16_MAX:
5997                 filter_info->src_port_mask = 0;
5998                 filter_info->src_port = filter->src_port;
5999                 break;
6000         case 0:
6001                 filter_info->src_port_mask = 1;
6002                 break;
6003         default:
6004                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6005                 return -EINVAL;
6006         }
6007
6008         switch (filter->proto_mask) {
6009         case UINT8_MAX:
6010                 filter_info->proto_mask = 0;
6011                 filter_info->proto =
6012                         convert_protocol_type(filter->proto);
6013                 break;
6014         case 0:
6015                 filter_info->proto_mask = 1;
6016                 break;
6017         default:
6018                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6019                 return -EINVAL;
6020         }
6021
6022         filter_info->priority = (uint8_t)filter->priority;
6023         return 0;
6024 }
6025
6026 /*
6027  * add or delete a ntuple filter
6028  *
6029  * @param
6030  * dev: Pointer to struct rte_eth_dev.
6031  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6032  * add: if true, add filter, if false, remove filter
6033  *
6034  * @return
6035  *    - On success, zero.
6036  *    - On failure, a negative value.
6037  */
6038 static int
6039 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6040                         struct rte_eth_ntuple_filter *ntuple_filter,
6041                         bool add)
6042 {
6043         struct ixgbe_filter_info *filter_info =
6044                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6045         struct ixgbe_5tuple_filter_info filter_5tuple;
6046         struct ixgbe_5tuple_filter *filter;
6047         int ret;
6048
6049         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6050                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6051                 return -EINVAL;
6052         }
6053
6054         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6055         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6056         if (ret < 0)
6057                 return ret;
6058
6059         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6060                                          &filter_5tuple);
6061         if (filter != NULL && add) {
6062                 PMD_DRV_LOG(ERR, "filter exists.");
6063                 return -EEXIST;
6064         }
6065         if (filter == NULL && !add) {
6066                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6067                 return -ENOENT;
6068         }
6069
6070         if (add) {
6071                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6072                                 sizeof(struct ixgbe_5tuple_filter), 0);
6073                 if (filter == NULL)
6074                         return -ENOMEM;
6075                 (void)rte_memcpy(&filter->filter_info,
6076                                  &filter_5tuple,
6077                                  sizeof(struct ixgbe_5tuple_filter_info));
6078                 filter->queue = ntuple_filter->queue;
6079                 ret = ixgbe_add_5tuple_filter(dev, filter);
6080                 if (ret < 0) {
6081                         rte_free(filter);
6082                         return ret;
6083                 }
6084         } else
6085                 ixgbe_remove_5tuple_filter(dev, filter);
6086
6087         return 0;
6088 }
6089
6090 /*
6091  * get a ntuple filter
6092  *
6093  * @param
6094  * dev: Pointer to struct rte_eth_dev.
6095  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6096  *
6097  * @return
6098  *    - On success, zero.
6099  *    - On failure, a negative value.
6100  */
6101 static int
6102 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6103                         struct rte_eth_ntuple_filter *ntuple_filter)
6104 {
6105         struct ixgbe_filter_info *filter_info =
6106                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6107         struct ixgbe_5tuple_filter_info filter_5tuple;
6108         struct ixgbe_5tuple_filter *filter;
6109         int ret;
6110
6111         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6112                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6113                 return -EINVAL;
6114         }
6115
6116         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6117         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6118         if (ret < 0)
6119                 return ret;
6120
6121         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6122                                          &filter_5tuple);
6123         if (filter == NULL) {
6124                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6125                 return -ENOENT;
6126         }
6127         ntuple_filter->queue = filter->queue;
6128         return 0;
6129 }
6130
6131 /*
6132  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6133  * @dev: pointer to rte_eth_dev structure
6134  * @filter_op:operation will be taken.
6135  * @arg: a pointer to specific structure corresponding to the filter_op
6136  *
6137  * @return
6138  *    - On success, zero.
6139  *    - On failure, a negative value.
6140  */
6141 static int
6142 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6143                                 enum rte_filter_op filter_op,
6144                                 void *arg)
6145 {
6146         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6147         int ret;
6148
6149         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6150
6151         if (filter_op == RTE_ETH_FILTER_NOP)
6152                 return 0;
6153
6154         if (arg == NULL) {
6155                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6156                             filter_op);
6157                 return -EINVAL;
6158         }
6159
6160         switch (filter_op) {
6161         case RTE_ETH_FILTER_ADD:
6162                 ret = ixgbe_add_del_ntuple_filter(dev,
6163                         (struct rte_eth_ntuple_filter *)arg,
6164                         TRUE);
6165                 break;
6166         case RTE_ETH_FILTER_DELETE:
6167                 ret = ixgbe_add_del_ntuple_filter(dev,
6168                         (struct rte_eth_ntuple_filter *)arg,
6169                         FALSE);
6170                 break;
6171         case RTE_ETH_FILTER_GET:
6172                 ret = ixgbe_get_ntuple_filter(dev,
6173                         (struct rte_eth_ntuple_filter *)arg);
6174                 break;
6175         default:
6176                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6177                 ret = -EINVAL;
6178                 break;
6179         }
6180         return ret;
6181 }
6182
6183 static inline int
6184 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
6185                         uint16_t ethertype)
6186 {
6187         int i;
6188
6189         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6190                 if (filter_info->ethertype_filters[i] == ethertype &&
6191                     (filter_info->ethertype_mask & (1 << i)))
6192                         return i;
6193         }
6194         return -1;
6195 }
6196
6197 static inline int
6198 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
6199                         uint16_t ethertype)
6200 {
6201         int i;
6202
6203         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6204                 if (!(filter_info->ethertype_mask & (1 << i))) {
6205                         filter_info->ethertype_mask |= 1 << i;
6206                         filter_info->ethertype_filters[i] = ethertype;
6207                         return i;
6208                 }
6209         }
6210         return -1;
6211 }
6212
6213 static inline int
6214 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
6215                         uint8_t idx)
6216 {
6217         if (idx >= IXGBE_MAX_ETQF_FILTERS)
6218                 return -1;
6219         filter_info->ethertype_mask &= ~(1 << idx);
6220         filter_info->ethertype_filters[idx] = 0;
6221         return idx;
6222 }
6223
6224 static int
6225 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6226                         struct rte_eth_ethertype_filter *filter,
6227                         bool add)
6228 {
6229         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6230         struct ixgbe_filter_info *filter_info =
6231                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6232         uint32_t etqf = 0;
6233         uint32_t etqs = 0;
6234         int ret;
6235
6236         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6237                 return -EINVAL;
6238
6239         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6240                 filter->ether_type == ETHER_TYPE_IPv6) {
6241                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6242                         " ethertype filter.", filter->ether_type);
6243                 return -EINVAL;
6244         }
6245
6246         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6247                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6248                 return -EINVAL;
6249         }
6250         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6251                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6252                 return -EINVAL;
6253         }
6254
6255         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6256         if (ret >= 0 && add) {
6257                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6258                             filter->ether_type);
6259                 return -EEXIST;
6260         }
6261         if (ret < 0 && !add) {
6262                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6263                             filter->ether_type);
6264                 return -ENOENT;
6265         }
6266
6267         if (add) {
6268                 ret = ixgbe_ethertype_filter_insert(filter_info,
6269                         filter->ether_type);
6270                 if (ret < 0) {
6271                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6272                         return -ENOSYS;
6273                 }
6274                 etqf = IXGBE_ETQF_FILTER_EN;
6275                 etqf |= (uint32_t)filter->ether_type;
6276                 etqs |= (uint32_t)((filter->queue <<
6277                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6278                                     IXGBE_ETQS_RX_QUEUE);
6279                 etqs |= IXGBE_ETQS_QUEUE_EN;
6280         } else {
6281                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6282                 if (ret < 0)
6283                         return -ENOSYS;
6284         }
6285         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6286         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6287         IXGBE_WRITE_FLUSH(hw);
6288
6289         return 0;
6290 }
6291
6292 static int
6293 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6294                         struct rte_eth_ethertype_filter *filter)
6295 {
6296         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6297         struct ixgbe_filter_info *filter_info =
6298                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6299         uint32_t etqf, etqs;
6300         int ret;
6301
6302         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6303         if (ret < 0) {
6304                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6305                             filter->ether_type);
6306                 return -ENOENT;
6307         }
6308
6309         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6310         if (etqf & IXGBE_ETQF_FILTER_EN) {
6311                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6312                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6313                 filter->flags = 0;
6314                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6315                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6316                 return 0;
6317         }
6318         return -ENOENT;
6319 }
6320
6321 /*
6322  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6323  * @dev: pointer to rte_eth_dev structure
6324  * @filter_op:operation will be taken.
6325  * @arg: a pointer to specific structure corresponding to the filter_op
6326  */
6327 static int
6328 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6329                                 enum rte_filter_op filter_op,
6330                                 void *arg)
6331 {
6332         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6333         int ret;
6334
6335         MAC_TYPE_FILTER_SUP(hw->mac.type);
6336
6337         if (filter_op == RTE_ETH_FILTER_NOP)
6338                 return 0;
6339
6340         if (arg == NULL) {
6341                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6342                             filter_op);
6343                 return -EINVAL;
6344         }
6345
6346         switch (filter_op) {
6347         case RTE_ETH_FILTER_ADD:
6348                 ret = ixgbe_add_del_ethertype_filter(dev,
6349                         (struct rte_eth_ethertype_filter *)arg,
6350                         TRUE);
6351                 break;
6352         case RTE_ETH_FILTER_DELETE:
6353                 ret = ixgbe_add_del_ethertype_filter(dev,
6354                         (struct rte_eth_ethertype_filter *)arg,
6355                         FALSE);
6356                 break;
6357         case RTE_ETH_FILTER_GET:
6358                 ret = ixgbe_get_ethertype_filter(dev,
6359                         (struct rte_eth_ethertype_filter *)arg);
6360                 break;
6361         default:
6362                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6363                 ret = -EINVAL;
6364                 break;
6365         }
6366         return ret;
6367 }
6368
6369 static int
6370 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6371                      enum rte_filter_type filter_type,
6372                      enum rte_filter_op filter_op,
6373                      void *arg)
6374 {
6375         int ret = -EINVAL;
6376
6377         switch (filter_type) {
6378         case RTE_ETH_FILTER_NTUPLE:
6379                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6380                 break;
6381         case RTE_ETH_FILTER_ETHERTYPE:
6382                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6383                 break;
6384         case RTE_ETH_FILTER_SYN:
6385                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6386                 break;
6387         case RTE_ETH_FILTER_FDIR:
6388                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6389                 break;
6390         case RTE_ETH_FILTER_L2_TUNNEL:
6391                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6392                 break;
6393         default:
6394                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6395                                                         filter_type);
6396                 break;
6397         }
6398
6399         return ret;
6400 }
6401
6402 static u8 *
6403 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6404                         u8 **mc_addr_ptr, u32 *vmdq)
6405 {
6406         u8 *mc_addr;
6407
6408         *vmdq = 0;
6409         mc_addr = *mc_addr_ptr;
6410         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6411         return mc_addr;
6412 }
6413
6414 static int
6415 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6416                           struct ether_addr *mc_addr_set,
6417                           uint32_t nb_mc_addr)
6418 {
6419         struct ixgbe_hw *hw;
6420         u8 *mc_addr_list;
6421
6422         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6423         mc_addr_list = (u8 *)mc_addr_set;
6424         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6425                                          ixgbe_dev_addr_list_itr, TRUE);
6426 }
6427
6428 static uint64_t
6429 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6430 {
6431         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6432         uint64_t systime_cycles;
6433
6434         switch (hw->mac.type) {
6435         case ixgbe_mac_X550:
6436         case ixgbe_mac_X550EM_x:
6437         case ixgbe_mac_X550EM_a:
6438                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6439                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6440                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6441                                 * NSEC_PER_SEC;
6442                 break;
6443         default:
6444                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6445                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6446                                 << 32;
6447         }
6448
6449         return systime_cycles;
6450 }
6451
6452 static uint64_t
6453 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6454 {
6455         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6456         uint64_t rx_tstamp_cycles;
6457
6458         switch (hw->mac.type) {
6459         case ixgbe_mac_X550:
6460         case ixgbe_mac_X550EM_x:
6461         case ixgbe_mac_X550EM_a:
6462                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6463                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6464                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6465                                 * NSEC_PER_SEC;
6466                 break;
6467         default:
6468                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6469                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6470                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6471                                 << 32;
6472         }
6473
6474         return rx_tstamp_cycles;
6475 }
6476
6477 static uint64_t
6478 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6479 {
6480         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6481         uint64_t tx_tstamp_cycles;
6482
6483         switch (hw->mac.type) {
6484         case ixgbe_mac_X550:
6485         case ixgbe_mac_X550EM_x:
6486         case ixgbe_mac_X550EM_a:
6487                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6488                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6489                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6490                                 * NSEC_PER_SEC;
6491                 break;
6492         default:
6493                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6494                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6495                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6496                                 << 32;
6497         }
6498
6499         return tx_tstamp_cycles;
6500 }
6501
6502 static void
6503 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6504 {
6505         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6506         struct ixgbe_adapter *adapter =
6507                 (struct ixgbe_adapter *)dev->data->dev_private;
6508         struct rte_eth_link link;
6509         uint32_t incval = 0;
6510         uint32_t shift = 0;
6511
6512         /* Get current link speed. */
6513         memset(&link, 0, sizeof(link));
6514         ixgbe_dev_link_update(dev, 1);
6515         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6516
6517         switch (link.link_speed) {
6518         case ETH_SPEED_NUM_100M:
6519                 incval = IXGBE_INCVAL_100;
6520                 shift = IXGBE_INCVAL_SHIFT_100;
6521                 break;
6522         case ETH_SPEED_NUM_1G:
6523                 incval = IXGBE_INCVAL_1GB;
6524                 shift = IXGBE_INCVAL_SHIFT_1GB;
6525                 break;
6526         case ETH_SPEED_NUM_10G:
6527         default:
6528                 incval = IXGBE_INCVAL_10GB;
6529                 shift = IXGBE_INCVAL_SHIFT_10GB;
6530                 break;
6531         }
6532
6533         switch (hw->mac.type) {
6534         case ixgbe_mac_X550:
6535         case ixgbe_mac_X550EM_x:
6536         case ixgbe_mac_X550EM_a:
6537                 /* Independent of link speed. */
6538                 incval = 1;
6539                 /* Cycles read will be interpreted as ns. */
6540                 shift = 0;
6541                 /* Fall-through */
6542         case ixgbe_mac_X540:
6543                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6544                 break;
6545         case ixgbe_mac_82599EB:
6546                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6547                 shift -= IXGBE_INCVAL_SHIFT_82599;
6548                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6549                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6550                 break;
6551         default:
6552                 /* Not supported. */
6553                 return;
6554         }
6555
6556         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6557         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6558         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6559
6560         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6561         adapter->systime_tc.cc_shift = shift;
6562         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6563
6564         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6565         adapter->rx_tstamp_tc.cc_shift = shift;
6566         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6567
6568         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6569         adapter->tx_tstamp_tc.cc_shift = shift;
6570         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6571 }
6572
6573 static int
6574 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6575 {
6576         struct ixgbe_adapter *adapter =
6577                         (struct ixgbe_adapter *)dev->data->dev_private;
6578
6579         adapter->systime_tc.nsec += delta;
6580         adapter->rx_tstamp_tc.nsec += delta;
6581         adapter->tx_tstamp_tc.nsec += delta;
6582
6583         return 0;
6584 }
6585
6586 static int
6587 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6588 {
6589         uint64_t ns;
6590         struct ixgbe_adapter *adapter =
6591                         (struct ixgbe_adapter *)dev->data->dev_private;
6592
6593         ns = rte_timespec_to_ns(ts);
6594         /* Set the timecounters to a new value. */
6595         adapter->systime_tc.nsec = ns;
6596         adapter->rx_tstamp_tc.nsec = ns;
6597         adapter->tx_tstamp_tc.nsec = ns;
6598
6599         return 0;
6600 }
6601
6602 static int
6603 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6604 {
6605         uint64_t ns, systime_cycles;
6606         struct ixgbe_adapter *adapter =
6607                         (struct ixgbe_adapter *)dev->data->dev_private;
6608
6609         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6610         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6611         *ts = rte_ns_to_timespec(ns);
6612
6613         return 0;
6614 }
6615
6616 static int
6617 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6618 {
6619         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6620         uint32_t tsync_ctl;
6621         uint32_t tsauxc;
6622
6623         /* Stop the timesync system time. */
6624         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6625         /* Reset the timesync system time value. */
6626         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6627         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6628
6629         /* Enable system time for platforms where it isn't on by default. */
6630         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6631         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6632         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6633
6634         ixgbe_start_timecounters(dev);
6635
6636         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6637         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6638                         (ETHER_TYPE_1588 |
6639                          IXGBE_ETQF_FILTER_EN |
6640                          IXGBE_ETQF_1588));
6641
6642         /* Enable timestamping of received PTP packets. */
6643         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6644         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6645         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6646
6647         /* Enable timestamping of transmitted PTP packets. */
6648         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6649         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6650         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6651
6652         IXGBE_WRITE_FLUSH(hw);
6653
6654         return 0;
6655 }
6656
6657 static int
6658 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6659 {
6660         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6661         uint32_t tsync_ctl;
6662
6663         /* Disable timestamping of transmitted PTP packets. */
6664         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6665         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6666         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6667
6668         /* Disable timestamping of received PTP packets. */
6669         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6670         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6671         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6672
6673         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6674         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6675
6676         /* Stop incrementating the System Time registers. */
6677         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6678
6679         return 0;
6680 }
6681
6682 static int
6683 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6684                                  struct timespec *timestamp,
6685                                  uint32_t flags __rte_unused)
6686 {
6687         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6688         struct ixgbe_adapter *adapter =
6689                 (struct ixgbe_adapter *)dev->data->dev_private;
6690         uint32_t tsync_rxctl;
6691         uint64_t rx_tstamp_cycles;
6692         uint64_t ns;
6693
6694         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6695         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6696                 return -EINVAL;
6697
6698         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6699         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6700         *timestamp = rte_ns_to_timespec(ns);
6701
6702         return  0;
6703 }
6704
6705 static int
6706 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6707                                  struct timespec *timestamp)
6708 {
6709         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6710         struct ixgbe_adapter *adapter =
6711                 (struct ixgbe_adapter *)dev->data->dev_private;
6712         uint32_t tsync_txctl;
6713         uint64_t tx_tstamp_cycles;
6714         uint64_t ns;
6715
6716         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6717         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6718                 return -EINVAL;
6719
6720         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6721         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6722         *timestamp = rte_ns_to_timespec(ns);
6723
6724         return 0;
6725 }
6726
6727 static int
6728 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6729 {
6730         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6731         int count = 0;
6732         int g_ind = 0;
6733         const struct reg_info *reg_group;
6734         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6735                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6736
6737         while ((reg_group = reg_set[g_ind++]))
6738                 count += ixgbe_regs_group_count(reg_group);
6739
6740         return count;
6741 }
6742
6743 static int
6744 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6745 {
6746         int count = 0;
6747         int g_ind = 0;
6748         const struct reg_info *reg_group;
6749
6750         while ((reg_group = ixgbevf_regs[g_ind++]))
6751                 count += ixgbe_regs_group_count(reg_group);
6752
6753         return count;
6754 }
6755
6756 static int
6757 ixgbe_get_regs(struct rte_eth_dev *dev,
6758               struct rte_dev_reg_info *regs)
6759 {
6760         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6761         uint32_t *data = regs->data;
6762         int g_ind = 0;
6763         int count = 0;
6764         const struct reg_info *reg_group;
6765         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6766                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6767
6768         if (data == NULL) {
6769                 regs->length = ixgbe_get_reg_length(dev);
6770                 regs->width = sizeof(uint32_t);
6771                 return 0;
6772         }
6773
6774         /* Support only full register dump */
6775         if ((regs->length == 0) ||
6776             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6777                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6778                         hw->device_id;
6779                 while ((reg_group = reg_set[g_ind++]))
6780                         count += ixgbe_read_regs_group(dev, &data[count],
6781                                 reg_group);
6782                 return 0;
6783         }
6784
6785         return -ENOTSUP;
6786 }
6787
6788 static int
6789 ixgbevf_get_regs(struct rte_eth_dev *dev,
6790                 struct rte_dev_reg_info *regs)
6791 {
6792         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6793         uint32_t *data = regs->data;
6794         int g_ind = 0;
6795         int count = 0;
6796         const struct reg_info *reg_group;
6797
6798         if (data == NULL) {
6799                 regs->length = ixgbevf_get_reg_length(dev);
6800                 regs->width = sizeof(uint32_t);
6801                 return 0;
6802         }
6803
6804         /* Support only full register dump */
6805         if ((regs->length == 0) ||
6806             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6807                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6808                         hw->device_id;
6809                 while ((reg_group = ixgbevf_regs[g_ind++]))
6810                         count += ixgbe_read_regs_group(dev, &data[count],
6811                                                       reg_group);
6812                 return 0;
6813         }
6814
6815         return -ENOTSUP;
6816 }
6817
6818 static int
6819 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6820 {
6821         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6822
6823         /* Return unit is byte count */
6824         return hw->eeprom.word_size * 2;
6825 }
6826
6827 static int
6828 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6829                 struct rte_dev_eeprom_info *in_eeprom)
6830 {
6831         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6832         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6833         uint16_t *data = in_eeprom->data;
6834         int first, length;
6835
6836         first = in_eeprom->offset >> 1;
6837         length = in_eeprom->length >> 1;
6838         if ((first > hw->eeprom.word_size) ||
6839             ((first + length) > hw->eeprom.word_size))
6840                 return -EINVAL;
6841
6842         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6843
6844         return eeprom->ops.read_buffer(hw, first, length, data);
6845 }
6846
6847 static int
6848 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6849                 struct rte_dev_eeprom_info *in_eeprom)
6850 {
6851         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6852         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6853         uint16_t *data = in_eeprom->data;
6854         int first, length;
6855
6856         first = in_eeprom->offset >> 1;
6857         length = in_eeprom->length >> 1;
6858         if ((first > hw->eeprom.word_size) ||
6859             ((first + length) > hw->eeprom.word_size))
6860                 return -EINVAL;
6861
6862         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6863
6864         return eeprom->ops.write_buffer(hw,  first, length, data);
6865 }
6866
6867 uint16_t
6868 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6869         switch (mac_type) {
6870         case ixgbe_mac_X550:
6871         case ixgbe_mac_X550EM_x:
6872         case ixgbe_mac_X550EM_a:
6873                 return ETH_RSS_RETA_SIZE_512;
6874         case ixgbe_mac_X550_vf:
6875         case ixgbe_mac_X550EM_x_vf:
6876         case ixgbe_mac_X550EM_a_vf:
6877                 return ETH_RSS_RETA_SIZE_64;
6878         default:
6879                 return ETH_RSS_RETA_SIZE_128;
6880         }
6881 }
6882
6883 uint32_t
6884 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6885         switch (mac_type) {
6886         case ixgbe_mac_X550:
6887         case ixgbe_mac_X550EM_x:
6888         case ixgbe_mac_X550EM_a:
6889                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6890                         return IXGBE_RETA(reta_idx >> 2);
6891                 else
6892                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6893         case ixgbe_mac_X550_vf:
6894         case ixgbe_mac_X550EM_x_vf:
6895         case ixgbe_mac_X550EM_a_vf:
6896                 return IXGBE_VFRETA(reta_idx >> 2);
6897         default:
6898                 return IXGBE_RETA(reta_idx >> 2);
6899         }
6900 }
6901
6902 uint32_t
6903 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6904         switch (mac_type) {
6905         case ixgbe_mac_X550_vf:
6906         case ixgbe_mac_X550EM_x_vf:
6907         case ixgbe_mac_X550EM_a_vf:
6908                 return IXGBE_VFMRQC;
6909         default:
6910                 return IXGBE_MRQC;
6911         }
6912 }
6913
6914 uint32_t
6915 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6916         switch (mac_type) {
6917         case ixgbe_mac_X550_vf:
6918         case ixgbe_mac_X550EM_x_vf:
6919         case ixgbe_mac_X550EM_a_vf:
6920                 return IXGBE_VFRSSRK(i);
6921         default:
6922                 return IXGBE_RSSRK(i);
6923         }
6924 }
6925
6926 bool
6927 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6928         switch (mac_type) {
6929         case ixgbe_mac_82599_vf:
6930         case ixgbe_mac_X540_vf:
6931                 return 0;
6932         default:
6933                 return 1;
6934         }
6935 }
6936
6937 static int
6938 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6939                         struct rte_eth_dcb_info *dcb_info)
6940 {
6941         struct ixgbe_dcb_config *dcb_config =
6942                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6943         struct ixgbe_dcb_tc_config *tc;
6944         uint8_t i, j;
6945
6946         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6947                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6948         else
6949                 dcb_info->nb_tcs = 1;
6950
6951         if (dcb_config->vt_mode) { /* vt is enabled*/
6952                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6953                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6954                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6955                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6956                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6957                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6958                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6959                                                 i * dcb_info->nb_tcs + j;
6960                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6961                                 dcb_info->tc_queue.tc_txq[i][j].base =
6962                                                 i * dcb_info->nb_tcs + j;
6963                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6964                         }
6965                 }
6966         } else { /* vt is disabled*/
6967                 struct rte_eth_dcb_rx_conf *rx_conf =
6968                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6969                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6970                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6971                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6972                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6973                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6974                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6975                         }
6976                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6977                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6978                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6979                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6980                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6981                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6982                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6983                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6984                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6985                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6986                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6987                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6988                         }
6989                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6990                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6991                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6992                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6993                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6994                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6995                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6996                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6997                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6998                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6999                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7000                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7001                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7002                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7003                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7004                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7005                 }
7006         }
7007         for (i = 0; i < dcb_info->nb_tcs; i++) {
7008                 tc = &dcb_config->tc_config[i];
7009                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7010         }
7011         return 0;
7012 }
7013
7014 /* Update e-tag ether type */
7015 static int
7016 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7017                             uint16_t ether_type)
7018 {
7019         uint32_t etag_etype;
7020
7021         if (hw->mac.type != ixgbe_mac_X550 &&
7022             hw->mac.type != ixgbe_mac_X550EM_x &&
7023             hw->mac.type != ixgbe_mac_X550EM_a) {
7024                 return -ENOTSUP;
7025         }
7026
7027         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7028         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7029         etag_etype |= ether_type;
7030         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7031         IXGBE_WRITE_FLUSH(hw);
7032
7033         return 0;
7034 }
7035
7036 /* Config l2 tunnel ether type */
7037 static int
7038 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7039                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7040 {
7041         int ret = 0;
7042         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7043
7044         if (l2_tunnel == NULL)
7045                 return -EINVAL;
7046
7047         switch (l2_tunnel->l2_tunnel_type) {
7048         case RTE_L2_TUNNEL_TYPE_E_TAG:
7049                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7050                 break;
7051         default:
7052                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7053                 ret = -EINVAL;
7054                 break;
7055         }
7056
7057         return ret;
7058 }
7059
7060 /* Enable e-tag tunnel */
7061 static int
7062 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7063 {
7064         uint32_t etag_etype;
7065
7066         if (hw->mac.type != ixgbe_mac_X550 &&
7067             hw->mac.type != ixgbe_mac_X550EM_x &&
7068             hw->mac.type != ixgbe_mac_X550EM_a) {
7069                 return -ENOTSUP;
7070         }
7071
7072         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7073         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7074         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7075         IXGBE_WRITE_FLUSH(hw);
7076
7077         return 0;
7078 }
7079
7080 /* Enable l2 tunnel */
7081 static int
7082 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7083                            enum rte_eth_tunnel_type l2_tunnel_type)
7084 {
7085         int ret = 0;
7086         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7087
7088         switch (l2_tunnel_type) {
7089         case RTE_L2_TUNNEL_TYPE_E_TAG:
7090                 ret = ixgbe_e_tag_enable(hw);
7091                 break;
7092         default:
7093                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7094                 ret = -EINVAL;
7095                 break;
7096         }
7097
7098         return ret;
7099 }
7100
7101 /* Disable e-tag tunnel */
7102 static int
7103 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7104 {
7105         uint32_t etag_etype;
7106
7107         if (hw->mac.type != ixgbe_mac_X550 &&
7108             hw->mac.type != ixgbe_mac_X550EM_x &&
7109             hw->mac.type != ixgbe_mac_X550EM_a) {
7110                 return -ENOTSUP;
7111         }
7112
7113         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7114         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7115         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7116         IXGBE_WRITE_FLUSH(hw);
7117
7118         return 0;
7119 }
7120
7121 /* Disable l2 tunnel */
7122 static int
7123 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7124                             enum rte_eth_tunnel_type l2_tunnel_type)
7125 {
7126         int ret = 0;
7127         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7128
7129         switch (l2_tunnel_type) {
7130         case RTE_L2_TUNNEL_TYPE_E_TAG:
7131                 ret = ixgbe_e_tag_disable(hw);
7132                 break;
7133         default:
7134                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7135                 ret = -EINVAL;
7136                 break;
7137         }
7138
7139         return ret;
7140 }
7141
7142 static int
7143 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7144                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7145 {
7146         int ret = 0;
7147         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7148         uint32_t i, rar_entries;
7149         uint32_t rar_low, rar_high;
7150
7151         if (hw->mac.type != ixgbe_mac_X550 &&
7152             hw->mac.type != ixgbe_mac_X550EM_x &&
7153             hw->mac.type != ixgbe_mac_X550EM_a) {
7154                 return -ENOTSUP;
7155         }
7156
7157         rar_entries = ixgbe_get_num_rx_addrs(hw);
7158
7159         for (i = 1; i < rar_entries; i++) {
7160                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7161                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7162                 if ((rar_high & IXGBE_RAH_AV) &&
7163                     (rar_high & IXGBE_RAH_ADTYPE) &&
7164                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7165                      l2_tunnel->tunnel_id)) {
7166                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7167                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7168
7169                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7170
7171                         return ret;
7172                 }
7173         }
7174
7175         return ret;
7176 }
7177
7178 static int
7179 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7180                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7181 {
7182         int ret = 0;
7183         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7184         uint32_t i, rar_entries;
7185         uint32_t rar_low, rar_high;
7186
7187         if (hw->mac.type != ixgbe_mac_X550 &&
7188             hw->mac.type != ixgbe_mac_X550EM_x &&
7189             hw->mac.type != ixgbe_mac_X550EM_a) {
7190                 return -ENOTSUP;
7191         }
7192
7193         /* One entry for one tunnel. Try to remove potential existing entry. */
7194         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7195
7196         rar_entries = ixgbe_get_num_rx_addrs(hw);
7197
7198         for (i = 1; i < rar_entries; i++) {
7199                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7200                 if (rar_high & IXGBE_RAH_AV) {
7201                         continue;
7202                 } else {
7203                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7204                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7205                         rar_low = l2_tunnel->tunnel_id;
7206
7207                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7208                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7209
7210                         return ret;
7211                 }
7212         }
7213
7214         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7215                      " Please remove a rule before adding a new one.");
7216         return -EINVAL;
7217 }
7218
7219 /* Add l2 tunnel filter */
7220 static int
7221 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7222                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7223 {
7224         int ret = 0;
7225
7226         switch (l2_tunnel->l2_tunnel_type) {
7227         case RTE_L2_TUNNEL_TYPE_E_TAG:
7228                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7229                 break;
7230         default:
7231                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7232                 ret = -EINVAL;
7233                 break;
7234         }
7235
7236         return ret;
7237 }
7238
7239 /* Delete l2 tunnel filter */
7240 static int
7241 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7242                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7243 {
7244         int ret = 0;
7245
7246         switch (l2_tunnel->l2_tunnel_type) {
7247         case RTE_L2_TUNNEL_TYPE_E_TAG:
7248                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7249                 break;
7250         default:
7251                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7252                 ret = -EINVAL;
7253                 break;
7254         }
7255
7256         return ret;
7257 }
7258
7259 /**
7260  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7261  * @dev: pointer to rte_eth_dev structure
7262  * @filter_op:operation will be taken.
7263  * @arg: a pointer to specific structure corresponding to the filter_op
7264  */
7265 static int
7266 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7267                                   enum rte_filter_op filter_op,
7268                                   void *arg)
7269 {
7270         int ret = 0;
7271
7272         if (filter_op == RTE_ETH_FILTER_NOP)
7273                 return 0;
7274
7275         if (arg == NULL) {
7276                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7277                             filter_op);
7278                 return -EINVAL;
7279         }
7280
7281         switch (filter_op) {
7282         case RTE_ETH_FILTER_ADD:
7283                 ret = ixgbe_dev_l2_tunnel_filter_add
7284                         (dev,
7285                          (struct rte_eth_l2_tunnel_conf *)arg);
7286                 break;
7287         case RTE_ETH_FILTER_DELETE:
7288                 ret = ixgbe_dev_l2_tunnel_filter_del
7289                         (dev,
7290                          (struct rte_eth_l2_tunnel_conf *)arg);
7291                 break;
7292         default:
7293                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7294                 ret = -EINVAL;
7295                 break;
7296         }
7297         return ret;
7298 }
7299
7300 static int
7301 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7302 {
7303         int ret = 0;
7304         uint32_t ctrl;
7305         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7306
7307         if (hw->mac.type != ixgbe_mac_X550 &&
7308             hw->mac.type != ixgbe_mac_X550EM_x &&
7309             hw->mac.type != ixgbe_mac_X550EM_a) {
7310                 return -ENOTSUP;
7311         }
7312
7313         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7314         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7315         if (en)
7316                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7317         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7318
7319         return ret;
7320 }
7321
7322 /* Enable l2 tunnel forwarding */
7323 static int
7324 ixgbe_dev_l2_tunnel_forwarding_enable
7325         (struct rte_eth_dev *dev,
7326          enum rte_eth_tunnel_type l2_tunnel_type)
7327 {
7328         int ret = 0;
7329
7330         switch (l2_tunnel_type) {
7331         case RTE_L2_TUNNEL_TYPE_E_TAG:
7332                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7333                 break;
7334         default:
7335                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7336                 ret = -EINVAL;
7337                 break;
7338         }
7339
7340         return ret;
7341 }
7342
7343 /* Disable l2 tunnel forwarding */
7344 static int
7345 ixgbe_dev_l2_tunnel_forwarding_disable
7346         (struct rte_eth_dev *dev,
7347          enum rte_eth_tunnel_type l2_tunnel_type)
7348 {
7349         int ret = 0;
7350
7351         switch (l2_tunnel_type) {
7352         case RTE_L2_TUNNEL_TYPE_E_TAG:
7353                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7354                 break;
7355         default:
7356                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7357                 ret = -EINVAL;
7358                 break;
7359         }
7360
7361         return ret;
7362 }
7363
7364 static int
7365 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7366                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7367                              bool en)
7368 {
7369         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7370         int ret = 0;
7371         uint32_t vmtir, vmvir;
7372         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7373
7374         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7375                 PMD_DRV_LOG(ERR,
7376                             "VF id %u should be less than %u",
7377                             l2_tunnel->vf_id,
7378                             pci_dev->max_vfs);
7379                 return -EINVAL;
7380         }
7381
7382         if (hw->mac.type != ixgbe_mac_X550 &&
7383             hw->mac.type != ixgbe_mac_X550EM_x &&
7384             hw->mac.type != ixgbe_mac_X550EM_a) {
7385                 return -ENOTSUP;
7386         }
7387
7388         if (en)
7389                 vmtir = l2_tunnel->tunnel_id;
7390         else
7391                 vmtir = 0;
7392
7393         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7394
7395         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7396         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7397         if (en)
7398                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7399         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7400
7401         return ret;
7402 }
7403
7404 /* Enable l2 tunnel tag insertion */
7405 static int
7406 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7407                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7408 {
7409         int ret = 0;
7410
7411         switch (l2_tunnel->l2_tunnel_type) {
7412         case RTE_L2_TUNNEL_TYPE_E_TAG:
7413                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7414                 break;
7415         default:
7416                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7417                 ret = -EINVAL;
7418                 break;
7419         }
7420
7421         return ret;
7422 }
7423
7424 /* Disable l2 tunnel tag insertion */
7425 static int
7426 ixgbe_dev_l2_tunnel_insertion_disable
7427         (struct rte_eth_dev *dev,
7428          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7429 {
7430         int ret = 0;
7431
7432         switch (l2_tunnel->l2_tunnel_type) {
7433         case RTE_L2_TUNNEL_TYPE_E_TAG:
7434                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7435                 break;
7436         default:
7437                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7438                 ret = -EINVAL;
7439                 break;
7440         }
7441
7442         return ret;
7443 }
7444
7445 static int
7446 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7447                              bool en)
7448 {
7449         int ret = 0;
7450         uint32_t qde;
7451         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7452
7453         if (hw->mac.type != ixgbe_mac_X550 &&
7454             hw->mac.type != ixgbe_mac_X550EM_x &&
7455             hw->mac.type != ixgbe_mac_X550EM_a) {
7456                 return -ENOTSUP;
7457         }
7458
7459         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7460         if (en)
7461                 qde |= IXGBE_QDE_STRIP_TAG;
7462         else
7463                 qde &= ~IXGBE_QDE_STRIP_TAG;
7464         qde &= ~IXGBE_QDE_READ;
7465         qde |= IXGBE_QDE_WRITE;
7466         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7467
7468         return ret;
7469 }
7470
7471 /* Enable l2 tunnel tag stripping */
7472 static int
7473 ixgbe_dev_l2_tunnel_stripping_enable
7474         (struct rte_eth_dev *dev,
7475          enum rte_eth_tunnel_type l2_tunnel_type)
7476 {
7477         int ret = 0;
7478
7479         switch (l2_tunnel_type) {
7480         case RTE_L2_TUNNEL_TYPE_E_TAG:
7481                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7482                 break;
7483         default:
7484                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7485                 ret = -EINVAL;
7486                 break;
7487         }
7488
7489         return ret;
7490 }
7491
7492 /* Disable l2 tunnel tag stripping */
7493 static int
7494 ixgbe_dev_l2_tunnel_stripping_disable
7495         (struct rte_eth_dev *dev,
7496          enum rte_eth_tunnel_type l2_tunnel_type)
7497 {
7498         int ret = 0;
7499
7500         switch (l2_tunnel_type) {
7501         case RTE_L2_TUNNEL_TYPE_E_TAG:
7502                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7503                 break;
7504         default:
7505                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7506                 ret = -EINVAL;
7507                 break;
7508         }
7509
7510         return ret;
7511 }
7512
7513 /* Enable/disable l2 tunnel offload functions */
7514 static int
7515 ixgbe_dev_l2_tunnel_offload_set
7516         (struct rte_eth_dev *dev,
7517          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7518          uint32_t mask,
7519          uint8_t en)
7520 {
7521         int ret = 0;
7522
7523         if (l2_tunnel == NULL)
7524                 return -EINVAL;
7525
7526         ret = -EINVAL;
7527         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7528                 if (en)
7529                         ret = ixgbe_dev_l2_tunnel_enable(
7530                                 dev,
7531                                 l2_tunnel->l2_tunnel_type);
7532                 else
7533                         ret = ixgbe_dev_l2_tunnel_disable(
7534                                 dev,
7535                                 l2_tunnel->l2_tunnel_type);
7536         }
7537
7538         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7539                 if (en)
7540                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7541                                 dev,
7542                                 l2_tunnel);
7543                 else
7544                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7545                                 dev,
7546                                 l2_tunnel);
7547         }
7548
7549         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7550                 if (en)
7551                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7552                                 dev,
7553                                 l2_tunnel->l2_tunnel_type);
7554                 else
7555                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7556                                 dev,
7557                                 l2_tunnel->l2_tunnel_type);
7558         }
7559
7560         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7561                 if (en)
7562                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7563                                 dev,
7564                                 l2_tunnel->l2_tunnel_type);
7565                 else
7566                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7567                                 dev,
7568                                 l2_tunnel->l2_tunnel_type);
7569         }
7570
7571         return ret;
7572 }
7573
7574 static int
7575 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7576                         uint16_t port)
7577 {
7578         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7579         IXGBE_WRITE_FLUSH(hw);
7580
7581         return 0;
7582 }
7583
7584 /* There's only one register for VxLAN UDP port.
7585  * So, we cannot add several ports. Will update it.
7586  */
7587 static int
7588 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7589                      uint16_t port)
7590 {
7591         if (port == 0) {
7592                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7593                 return -EINVAL;
7594         }
7595
7596         return ixgbe_update_vxlan_port(hw, port);
7597 }
7598
7599 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7600  * UDP port, it must have a value.
7601  * So, will reset it to the original value 0.
7602  */
7603 static int
7604 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7605                      uint16_t port)
7606 {
7607         uint16_t cur_port;
7608
7609         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7610
7611         if (cur_port != port) {
7612                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7613                 return -EINVAL;
7614         }
7615
7616         return ixgbe_update_vxlan_port(hw, 0);
7617 }
7618
7619 /* Add UDP tunneling port */
7620 static int
7621 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7622                               struct rte_eth_udp_tunnel *udp_tunnel)
7623 {
7624         int ret = 0;
7625         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7626
7627         if (hw->mac.type != ixgbe_mac_X550 &&
7628             hw->mac.type != ixgbe_mac_X550EM_x &&
7629             hw->mac.type != ixgbe_mac_X550EM_a) {
7630                 return -ENOTSUP;
7631         }
7632
7633         if (udp_tunnel == NULL)
7634                 return -EINVAL;
7635
7636         switch (udp_tunnel->prot_type) {
7637         case RTE_TUNNEL_TYPE_VXLAN:
7638                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7639                 break;
7640
7641         case RTE_TUNNEL_TYPE_GENEVE:
7642         case RTE_TUNNEL_TYPE_TEREDO:
7643                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7644                 ret = -EINVAL;
7645                 break;
7646
7647         default:
7648                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7649                 ret = -EINVAL;
7650                 break;
7651         }
7652
7653         return ret;
7654 }
7655
7656 /* Remove UDP tunneling port */
7657 static int
7658 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7659                               struct rte_eth_udp_tunnel *udp_tunnel)
7660 {
7661         int ret = 0;
7662         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7663
7664         if (hw->mac.type != ixgbe_mac_X550 &&
7665             hw->mac.type != ixgbe_mac_X550EM_x &&
7666             hw->mac.type != ixgbe_mac_X550EM_a) {
7667                 return -ENOTSUP;
7668         }
7669
7670         if (udp_tunnel == NULL)
7671                 return -EINVAL;
7672
7673         switch (udp_tunnel->prot_type) {
7674         case RTE_TUNNEL_TYPE_VXLAN:
7675                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7676                 break;
7677         case RTE_TUNNEL_TYPE_GENEVE:
7678         case RTE_TUNNEL_TYPE_TEREDO:
7679                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7680                 ret = -EINVAL;
7681                 break;
7682         default:
7683                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7684                 ret = -EINVAL;
7685                 break;
7686         }
7687
7688         return ret;
7689 }
7690
7691 static void
7692 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7693 {
7694         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7695
7696         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7697 }
7698
7699 static void
7700 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7701 {
7702         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7703
7704         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7705 }
7706
7707 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7708 {
7709         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7710         u32 in_msg = 0;
7711
7712         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7713                 return;
7714
7715         /* PF reset VF event */
7716         if (in_msg == IXGBE_PF_CONTROL_MSG)
7717                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
7718 }
7719
7720 static int
7721 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7722 {
7723         uint32_t eicr;
7724         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7725         struct ixgbe_interrupt *intr =
7726                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7727         ixgbevf_intr_disable(hw);
7728
7729         /* read-on-clear nic registers here */
7730         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7731         intr->flags = 0;
7732
7733         /* only one misc vector supported - mailbox */
7734         eicr &= IXGBE_VTEICR_MASK;
7735         if (eicr == IXGBE_MISC_VEC_ID)
7736                 intr->flags |= IXGBE_FLAG_MAILBOX;
7737
7738         return 0;
7739 }
7740
7741 static int
7742 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7743 {
7744         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7745         struct ixgbe_interrupt *intr =
7746                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7747
7748         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7749                 ixgbevf_mbx_process(dev);
7750                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7751         }
7752
7753         ixgbevf_intr_enable(hw);
7754
7755         return 0;
7756 }
7757
7758 static void
7759 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
7760                               void *param)
7761 {
7762         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7763
7764         ixgbevf_dev_interrupt_get_status(dev);
7765         ixgbevf_dev_interrupt_action(dev);
7766 }
7767
7768 /**
7769  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
7770  *  @hw: pointer to hardware structure
7771  *
7772  *  Stops the transmit data path and waits for the HW to internally empty
7773  *  the Tx security block
7774  **/
7775 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
7776 {
7777 #define IXGBE_MAX_SECTX_POLL 40
7778
7779         int i;
7780         int sectxreg;
7781
7782         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7783         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
7784         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7785         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
7786                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
7787                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
7788                         break;
7789                 /* Use interrupt-safe sleep just in case */
7790                 usec_delay(1000);
7791         }
7792
7793         /* For informational purposes only */
7794         if (i >= IXGBE_MAX_SECTX_POLL)
7795                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
7796                          "path fully disabled.  Continuing with init.\n");
7797
7798         return IXGBE_SUCCESS;
7799 }
7800
7801 /**
7802  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
7803  *  @hw: pointer to hardware structure
7804  *
7805  *  Enables the transmit data path.
7806  **/
7807 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
7808 {
7809         uint32_t sectxreg;
7810
7811         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7812         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
7813         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7814         IXGBE_WRITE_FLUSH(hw);
7815
7816         return IXGBE_SUCCESS;
7817 }
7818
7819 int
7820 rte_pmd_ixgbe_macsec_enable(uint8_t port, uint8_t en, uint8_t rp)
7821 {
7822         struct ixgbe_hw *hw;
7823         struct rte_eth_dev *dev;
7824         uint32_t ctrl;
7825
7826         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
7827
7828         dev = &rte_eth_devices[port];
7829         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7830
7831         /* Stop the data paths */
7832         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
7833                 return -ENOTSUP;
7834         /*
7835          * Workaround:
7836          * As no ixgbe_disable_sec_rx_path equivalent is
7837          * implemented for tx in the base code, and we are
7838          * not allowed to modify the base code in DPDK, so
7839          * just call the hand-written one directly for now.
7840          * The hardware support has been checked by
7841          * ixgbe_disable_sec_rx_path().
7842          */
7843         ixgbe_disable_sec_tx_path_generic(hw);
7844
7845         /* Enable Ethernet CRC (required by MACsec offload) */
7846         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
7847         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
7848         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
7849
7850         /* Enable the TX and RX crypto engines */
7851         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7852         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
7853         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
7854
7855         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
7856         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
7857         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
7858
7859         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
7860         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
7861         ctrl |= 0x3;
7862         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
7863
7864         /* Enable SA lookup */
7865         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
7866         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
7867         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
7868                      IXGBE_LSECTXCTRL_AUTH;
7869         ctrl |= IXGBE_LSECTXCTRL_AISCI;
7870         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
7871         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
7872         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
7873
7874         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
7875         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
7876         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
7877         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
7878         if (rp)
7879                 ctrl |= IXGBE_LSECRXCTRL_RP;
7880         else
7881                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
7882         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
7883
7884         /* Start the data paths */
7885         ixgbe_enable_sec_rx_path(hw);
7886         /*
7887          * Workaround:
7888          * As no ixgbe_enable_sec_rx_path equivalent is
7889          * implemented for tx in the base code, and we are
7890          * not allowed to modify the base code in DPDK, so
7891          * just call the hand-written one directly for now.
7892          */
7893         ixgbe_enable_sec_tx_path_generic(hw);
7894
7895         return 0;
7896 }
7897
7898 int
7899 rte_pmd_ixgbe_macsec_disable(uint8_t port)
7900 {
7901         struct ixgbe_hw *hw;
7902         struct rte_eth_dev *dev;
7903         uint32_t ctrl;
7904
7905         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
7906
7907         dev = &rte_eth_devices[port];
7908         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7909
7910         /* Stop the data paths */
7911         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
7912                 return -ENOTSUP;
7913         /*
7914          * Workaround:
7915          * As no ixgbe_disable_sec_rx_path equivalent is
7916          * implemented for tx in the base code, and we are
7917          * not allowed to modify the base code in DPDK, so
7918          * just call the hand-written one directly for now.
7919          * The hardware support has been checked by
7920          * ixgbe_disable_sec_rx_path().
7921          */
7922         ixgbe_disable_sec_tx_path_generic(hw);
7923
7924         /* Disable the TX and RX crypto engines */
7925         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7926         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
7927         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
7928
7929         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
7930         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
7931         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
7932
7933         /* Disable SA lookup */
7934         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
7935         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
7936         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
7937         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
7938
7939         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
7940         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
7941         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
7942         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
7943
7944         /* Start the data paths */
7945         ixgbe_enable_sec_rx_path(hw);
7946         /*
7947          * Workaround:
7948          * As no ixgbe_enable_sec_rx_path equivalent is
7949          * implemented for tx in the base code, and we are
7950          * not allowed to modify the base code in DPDK, so
7951          * just call the hand-written one directly for now.
7952          */
7953         ixgbe_enable_sec_tx_path_generic(hw);
7954
7955         return 0;
7956 }
7957
7958 int
7959 rte_pmd_ixgbe_macsec_config_txsc(uint8_t port, uint8_t *mac)
7960 {
7961         struct ixgbe_hw *hw;
7962         struct rte_eth_dev *dev;
7963         uint32_t ctrl;
7964
7965         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
7966
7967         dev = &rte_eth_devices[port];
7968         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7969
7970         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
7971         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl);
7972
7973         ctrl = mac[4] | (mac[5] << 8);
7974         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl);
7975
7976         return 0;
7977 }
7978
7979 int
7980 rte_pmd_ixgbe_macsec_config_rxsc(uint8_t port, uint8_t *mac, uint16_t pi)
7981 {
7982         struct ixgbe_hw *hw;
7983         struct rte_eth_dev *dev;
7984         uint32_t ctrl;
7985
7986         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
7987
7988         dev = &rte_eth_devices[port];
7989         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7990
7991         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
7992         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl);
7993
7994         pi = rte_cpu_to_be_16(pi);
7995         ctrl = mac[4] | (mac[5] << 8) | (pi << 16);
7996         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl);
7997
7998         return 0;
7999 }
8000
8001 int
8002 rte_pmd_ixgbe_macsec_select_txsa(uint8_t port, uint8_t idx, uint8_t an,
8003                                  uint32_t pn, uint8_t *key)
8004 {
8005         struct ixgbe_hw *hw;
8006         struct rte_eth_dev *dev;
8007         uint32_t ctrl, i;
8008
8009         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8010
8011         dev = &rte_eth_devices[port];
8012         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8013
8014         if (idx != 0 && idx != 1)
8015                 return -EINVAL;
8016
8017         if (an >= 4)
8018                 return -EINVAL;
8019
8020         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8021
8022         /* Set the PN and key */
8023         pn = rte_cpu_to_be_32(pn);
8024         if (idx == 0) {
8025                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn);
8026
8027                 for (i = 0; i < 4; i++) {
8028                         ctrl = (key[i * 4 + 0] <<  0) |
8029                                (key[i * 4 + 1] <<  8) |
8030                                (key[i * 4 + 2] << 16) |
8031                                (key[i * 4 + 3] << 24);
8032                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl);
8033                 }
8034         } else {
8035                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn);
8036
8037                 for (i = 0; i < 4; i++) {
8038                         ctrl = (key[i * 4 + 0] <<  0) |
8039                                (key[i * 4 + 1] <<  8) |
8040                                (key[i * 4 + 2] << 16) |
8041                                (key[i * 4 + 3] << 24);
8042                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl);
8043                 }
8044         }
8045
8046         /* Set AN and select the SA */
8047         ctrl = (an << idx * 2) | (idx << 4);
8048         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl);
8049
8050         return 0;
8051 }
8052
8053 int
8054 rte_pmd_ixgbe_macsec_select_rxsa(uint8_t port, uint8_t idx, uint8_t an,
8055                                  uint32_t pn, uint8_t *key)
8056 {
8057         struct ixgbe_hw *hw;
8058         struct rte_eth_dev *dev;
8059         uint32_t ctrl, i;
8060
8061         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8062
8063         dev = &rte_eth_devices[port];
8064         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8065
8066         if (idx != 0 && idx != 1)
8067                 return -EINVAL;
8068
8069         if (an >= 4)
8070                 return -EINVAL;
8071
8072         /* Set the PN */
8073         pn = rte_cpu_to_be_32(pn);
8074         IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn);
8075
8076         /* Set the key */
8077         for (i = 0; i < 4; i++) {
8078                 ctrl = (key[i * 4 + 0] <<  0) |
8079                        (key[i * 4 + 1] <<  8) |
8080                        (key[i * 4 + 2] << 16) |
8081                        (key[i * 4 + 3] << 24);
8082                 IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl);
8083         }
8084
8085         /* Set the AN and validate the SA */
8086         ctrl = an | (1 << 2);
8087         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl);
8088
8089         return 0;
8090 }
8091
8092 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
8093 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8094 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8095 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
8096 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8097 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");