drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_eal.h>
  26 #include <rte_alarm.h>
  27 #include <rte_ether.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_malloc.h>
  31 #include <rte_random.h>
  32 #include <rte_dev.h>
  33 #include <rte_hash_crc.h>
  34 #ifdef RTE_LIBRTE_SECURITY
  35 #include <rte_security_driver.h>
  36 #endif
  37
  38 #include "ixgbe_logs.h"
  39 #include "base/ixgbe_api.h"
  40 #include "base/ixgbe_vf.h"
  41 #include "base/ixgbe_common.h"
  42 #include "ixgbe_ethdev.h"
  43 #include "ixgbe_bypass.h"
  44 #include "ixgbe_rxtx.h"
  45 #include "base/ixgbe_type.h"
  46 #include "base/ixgbe_phy.h"
  47 #include "ixgbe_regs.h"
  48
  49 /*
  50  * High threshold controlling when to start sending XOFF frames. Must be at
  51  * least 8 bytes less than receive packet buffer size. This value is in units
  52  * of 1024 bytes.
  53  */
  54 #define IXGBE_FC_HI    0x80
  55
  56 /*
  57  * Low threshold controlling when to start sending XON frames. This value is
  58  * in units of 1024 bytes.
  59  */
  60 #define IXGBE_FC_LO    0x40
  61
  62 /* Default minimum inter-interrupt interval for EITR configuration */
  63 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  64
  65 /* Timer value included in XOFF frames. */
  66 #define IXGBE_FC_PAUSE 0x680
  67
  68 /*Default value of Max Rx Queue*/
  69 #define IXGBE_MAX_RX_QUEUE_NUM 128
  70
  71 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  72 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  73 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  74
  75 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  76 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  77 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  78
  79 /*
  80  *  Default values for RX/TX configuration
  81  */
  82 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  83 #define IXGBE_DEFAULT_RX_PTHRESH      8
  84 #define IXGBE_DEFAULT_RX_HTHRESH      8
  85 #define IXGBE_DEFAULT_RX_WTHRESH      0
  86
  87 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  88 #define IXGBE_DEFAULT_TX_PTHRESH      32
  89 #define IXGBE_DEFAULT_TX_HTHRESH      0
  90 #define IXGBE_DEFAULT_TX_WTHRESH      0
  91 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  92
  93 /* Bit shift and mask */
  94 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  95 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  96 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  97 #define IXGBE_8_BIT_MASK   UINT8_MAX
  98
  99 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 100
 101 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 102
 103 #define IXGBE_HKEY_MAX_INDEX 10
 104
 105 /* Additional timesync values. */
 106 #define NSEC_PER_SEC             1000000000L
 107 #define IXGBE_INCVAL_10GB        0x66666666
 108 #define IXGBE_INCVAL_1GB         0x40000000
 109 #define IXGBE_INCVAL_100         0x50000000
 110 #define IXGBE_INCVAL_SHIFT_10GB  28
 111 #define IXGBE_INCVAL_SHIFT_1GB   24
 112 #define IXGBE_INCVAL_SHIFT_100   21
 113 #define IXGBE_INCVAL_SHIFT_82599 7
 114 #define IXGBE_INCPER_SHIFT_82599 24
 115
 116 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 117
 118 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 119 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 120 #define DEFAULT_ETAG_ETYPE                     0x893f
 121 #define IXGBE_ETAG_ETYPE                       0x00005084
 122 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 123 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 124 #define IXGBE_RAH_ADTYPE                       0x40000000
 125 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 126 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 127 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 128 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 129 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 130 #define IXGBE_VTEICR_MASK                      0x07
 131
 132 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 133 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 134
 135 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 136 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 137 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 138 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 139 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 143 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 145 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 148 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 149 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 151 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 152 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 154                                 int wait_to_complete);
 155 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 156                                 struct rte_eth_stats *stats);
 157 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 158                                 struct rte_eth_xstat *xstats, unsigned n);
 159 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 160                                   struct rte_eth_xstat *xstats, unsigned n);
 161 static int
 162 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 163                 uint64_t *values, unsigned int n);
 164 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 165 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 166 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 167         struct rte_eth_xstat_name *xstats_names,
 168         unsigned int size);
 169 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 171 static int ixgbe_dev_xstats_get_names_by_id(
 172         struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names,
 174         const uint64_t *ids,
 175         unsigned int limit);
 176 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 177                                              uint16_t queue_id,
 178                                              uint8_t stat_idx,
 179                                              uint8_t is_rx);
 180 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 181                                  size_t fw_size);
 182 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 183                                struct rte_eth_dev_info *dev_info);
 184 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 185 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 186                                  struct rte_eth_dev_info *dev_info);
 187 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 188
 189 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 190                 uint16_t vlan_id, int on);
 191 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 192                                enum rte_vlan_type vlan_type,
 193                                uint16_t tpid_id);
 194 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 195                 uint16_t queue, bool on);
 196 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 197                 int on);
 198 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 199 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 200 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 201 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 202 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 203
 204 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 205 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 206 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 207                                struct rte_eth_fc_conf *fc_conf);
 208 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 209                                struct rte_eth_fc_conf *fc_conf);
 210 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 211                 struct rte_eth_pfc_conf *pfc_conf);
 212 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 213                         struct rte_eth_rss_reta_entry64 *reta_conf,
 214                         uint16_t reta_size);
 215 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 216                         struct rte_eth_rss_reta_entry64 *reta_conf,
 217                         uint16_t reta_size);
 218 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 220 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 221 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 222 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 223 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 224                                       struct rte_intr_handle *handle);
 225 static void ixgbe_dev_interrupt_handler(void *param);
 226 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 227 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 228                          uint32_t index, uint32_t pool);
 229 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 230 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 231                                            struct ether_addr *mac_addr);
 232 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 233 static bool is_device_supported(struct rte_eth_dev *dev,
 234                                 struct rte_pci_driver *drv);
 235
 236 /* For Virtual Function support */
 237 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 238 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 239 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 240 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 241 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 242                                    int wait_to_complete);
 243 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 244 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 245 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 246 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 247 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 248 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 249                 struct rte_eth_stats *stats);
 250 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 251 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 252                 uint16_t vlan_id, int on);
 253 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 254                 uint16_t queue, int on);
 255 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 256 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 257 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 258                                             uint16_t queue_id);
 259 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 260                                              uint16_t queue_id);
 261 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 262                                  uint8_t queue, uint8_t msix_vector);
 263 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 264 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 265 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 266
 267 /* For Eth VMDQ APIs support */
 268 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 269                 ether_addr * mac_addr, uint8_t on);
 270 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 271 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 272                 struct rte_eth_mirror_conf *mirror_conf,
 273                 uint8_t rule_id, uint8_t on);
 274 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 275                 uint8_t rule_id);
 276 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 277                                           uint16_t queue_id);
 278 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 279                                            uint16_t queue_id);
 280 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 281                                uint8_t queue, uint8_t msix_vector);
 282 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 283
 284 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 285                                 struct ether_addr *mac_addr,
 286                                 uint32_t index, uint32_t pool);
 287 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 288 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 289                                              struct ether_addr *mac_addr);
 290 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 291                         struct rte_eth_syn_filter *filter);
 292 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 293                         enum rte_filter_op filter_op,
 294                         void *arg);
 295 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 296                         struct ixgbe_5tuple_filter *filter);
 297 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 298                         struct ixgbe_5tuple_filter *filter);
 299 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 300                                 enum rte_filter_op filter_op,
 301                                 void *arg);
 302 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 303                         struct rte_eth_ntuple_filter *filter);
 304 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 305                                 enum rte_filter_op filter_op,
 306                                 void *arg);
 307 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 308                         struct rte_eth_ethertype_filter *filter);
 309 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 310                      enum rte_filter_type filter_type,
 311                      enum rte_filter_op filter_op,
 312                      void *arg);
 313 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 314
 315 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 316                                       struct ether_addr *mc_addr_set,
 317                                       uint32_t nb_mc_addr);
 318 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 319                                    struct rte_eth_dcb_info *dcb_info);
 320
 321 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 322 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 323                             struct rte_dev_reg_info *regs);
 324 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 325 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 326                                 struct rte_dev_eeprom_info *eeprom);
 327 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 328                                 struct rte_dev_eeprom_info *eeprom);
 329
 330 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 331 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 332                                 struct rte_dev_reg_info *regs);
 333
 334 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 335 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 336 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 337                                             struct timespec *timestamp,
 338                                             uint32_t flags);
 339 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 340                                             struct timespec *timestamp);
 341 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 342 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 343                                    struct timespec *timestamp);
 344 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 345                                    const struct timespec *timestamp);
 346 static void ixgbevf_dev_interrupt_handler(void *param);
 347
 348 static int ixgbe_dev_l2_tunnel_eth_type_conf
 349         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 350 static int ixgbe_dev_l2_tunnel_offload_set
 351         (struct rte_eth_dev *dev,
 352          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 353          uint32_t mask,
 354          uint8_t en);
 355 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 356                                              enum rte_filter_op filter_op,
 357                                              void *arg);
 358
 359 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 360                                          struct rte_eth_udp_tunnel *udp_tunnel);
 361 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 362                                          struct rte_eth_udp_tunnel *udp_tunnel);
 363 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 364 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 365
 366 /*
 367  * Define VF Stats MACRO for Non "cleared on read" register
 368  */
 369 #define UPDATE_VF_STAT(reg, last, cur)                          \
 370 {                                                               \
 371         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 372         cur += (latest - last) & UINT_MAX;                      \
 373         last = latest;                                          \
 374 }
 375
 376 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 377 {                                                                \
 378         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 379         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 380         u64 latest = ((new_msb << 32) | new_lsb);                \
 381         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 382         last = latest;                                           \
 383 }
 384
 385 #define IXGBE_SET_HWSTRIP(h, q) do {\
 386                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 387                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 388                 (h)->bitmap[idx] |= 1 << bit;\
 389         } while (0)
 390
 391 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 392                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 393                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 394                 (h)->bitmap[idx] &= ~(1 << bit);\
 395         } while (0)
 396
 397 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 398                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 399                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 400                 (r) = (h)->bitmap[idx] >> bit & 1;\
 401         } while (0)
 402
 403 int ixgbe_logtype_init;
 404 int ixgbe_logtype_driver;
 405
 406 /*
 407  * The set of PCI devices this driver supports
 408  */
 409 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 410         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 411         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 458 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 460 #endif
 461         { .vendor_id = 0, /* sentinel */ },
 462 };
 463
 464 /*
 465  * The set of PCI devices this driver supports (for 82599 VF)
 466  */
 467 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 478         { .vendor_id = 0, /* sentinel */ },
 479 };
 480
 481 static const struct rte_eth_desc_lim rx_desc_lim = {
 482         .nb_max = IXGBE_MAX_RING_DESC,
 483         .nb_min = IXGBE_MIN_RING_DESC,
 484         .nb_align = IXGBE_RXD_ALIGN,
 485 };
 486
 487 static const struct rte_eth_desc_lim tx_desc_lim = {
 488         .nb_max = IXGBE_MAX_RING_DESC,
 489         .nb_min = IXGBE_MIN_RING_DESC,
 490         .nb_align = IXGBE_TXD_ALIGN,
 491         .nb_seg_max = IXGBE_TX_MAX_SEG,
 492         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 493 };
 494
 495 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 496         .dev_configure        = ixgbe_dev_configure,
 497         .dev_start            = ixgbe_dev_start,
 498         .dev_stop             = ixgbe_dev_stop,
 499         .dev_set_link_up    = ixgbe_dev_set_link_up,
 500         .dev_set_link_down  = ixgbe_dev_set_link_down,
 501         .dev_close            = ixgbe_dev_close,
 502         .dev_reset            = ixgbe_dev_reset,
 503         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 504         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 505         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 506         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 507         .link_update          = ixgbe_dev_link_update,
 508         .stats_get            = ixgbe_dev_stats_get,
 509         .xstats_get           = ixgbe_dev_xstats_get,
 510         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 511         .stats_reset          = ixgbe_dev_stats_reset,
 512         .xstats_reset         = ixgbe_dev_xstats_reset,
 513         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 514         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 515         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 516         .fw_version_get       = ixgbe_fw_version_get,
 517         .dev_infos_get        = ixgbe_dev_info_get,
 518         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 519         .mtu_set              = ixgbe_dev_mtu_set,
 520         .vlan_filter_set      = ixgbe_vlan_filter_set,
 521         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 522         .vlan_offload_set     = ixgbe_vlan_offload_set,
 523         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 524         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 525         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 526         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 527         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 528         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 529         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 530         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 531         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 532         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 533         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 534         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 535         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 536         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 537         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 538         .dev_led_on           = ixgbe_dev_led_on,
 539         .dev_led_off          = ixgbe_dev_led_off,
 540         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 541         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 542         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 543         .mac_addr_add         = ixgbe_add_rar,
 544         .mac_addr_remove      = ixgbe_remove_rar,
 545         .mac_addr_set         = ixgbe_set_default_mac_addr,
 546         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 547         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 548         .mirror_rule_set      = ixgbe_mirror_rule_set,
 549         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 550         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 551         .reta_update          = ixgbe_dev_rss_reta_update,
 552         .reta_query           = ixgbe_dev_rss_reta_query,
 553         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 554         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 555         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 556         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 557         .rxq_info_get         = ixgbe_rxq_info_get,
 558         .txq_info_get         = ixgbe_txq_info_get,
 559         .timesync_enable      = ixgbe_timesync_enable,
 560         .timesync_disable     = ixgbe_timesync_disable,
 561         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 562         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 563         .get_reg              = ixgbe_get_regs,
 564         .get_eeprom_length    = ixgbe_get_eeprom_length,
 565         .get_eeprom           = ixgbe_get_eeprom,
 566         .set_eeprom           = ixgbe_set_eeprom,
 567         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 568         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 569         .timesync_read_time   = ixgbe_timesync_read_time,
 570         .timesync_write_time  = ixgbe_timesync_write_time,
 571         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 572         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 573         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 574         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 575         .tm_ops_get           = ixgbe_tm_ops_get,
 576 };
 577
 578 /*
 579  * dev_ops for virtual function, bare necessities for basic vf
 580  * operation have been implemented
 581  */
 582 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 583         .dev_configure        = ixgbevf_dev_configure,
 584         .dev_start            = ixgbevf_dev_start,
 585         .dev_stop             = ixgbevf_dev_stop,
 586         .link_update          = ixgbevf_dev_link_update,
 587         .stats_get            = ixgbevf_dev_stats_get,
 588         .xstats_get           = ixgbevf_dev_xstats_get,
 589         .stats_reset          = ixgbevf_dev_stats_reset,
 590         .xstats_reset         = ixgbevf_dev_stats_reset,
 591         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 592         .dev_close            = ixgbevf_dev_close,
 593         .dev_reset            = ixgbevf_dev_reset,
 594         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 595         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 596         .dev_infos_get        = ixgbevf_dev_info_get,
 597         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 598         .mtu_set              = ixgbevf_dev_set_mtu,
 599         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 600         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 601         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 602         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 603         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 604         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 605         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 606         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 607         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 608         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 609         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 610         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 611         .mac_addr_add         = ixgbevf_add_mac_addr,
 612         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 613         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 614         .rxq_info_get         = ixgbe_rxq_info_get,
 615         .txq_info_get         = ixgbe_txq_info_get,
 616         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 617         .get_reg              = ixgbevf_get_regs,
 618         .reta_update          = ixgbe_dev_rss_reta_update,
 619         .reta_query           = ixgbe_dev_rss_reta_query,
 620         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 621         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 622 };
 623
 624 /* store statistics names and its offset in stats structure */
 625 struct rte_ixgbe_xstats_name_off {
 626         char name[RTE_ETH_XSTATS_NAME_SIZE];
 627         unsigned offset;
 628 };
 629
 630 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 631         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 632         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 633         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 634         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 635         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 636         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 637         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 638         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 639         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 640         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 641         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 642         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 643         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 644         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 645         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 646                 prc1023)},
 647         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 648                 prc1522)},
 649         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 650         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 651         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 652         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 653         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 654         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 655         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 656         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 657         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 658         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 659         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 660         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 661         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 662         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 663         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 664         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 665         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 666                 ptc1023)},
 667         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 668                 ptc1522)},
 669         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 670         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 671         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 672         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 673
 674         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 675                 fdirustat_add)},
 676         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 677                 fdirustat_remove)},
 678         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 679                 fdirfstat_fadd)},
 680         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 681                 fdirfstat_fremove)},
 682         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 683                 fdirmatch)},
 684         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 685                 fdirmiss)},
 686
 687         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 688         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 689         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 690                 fclast)},
 691         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 692         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 693         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 694         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 695         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 696                 fcoe_noddp)},
 697         {"rx_fcoe_no_direct_data_placement_ext_buff",
 698                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 699
 700         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 701                 lxontxc)},
 702         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 703                 lxonrxc)},
 704         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 705                 lxofftxc)},
 706         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 707                 lxoffrxc)},
 708         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 709 };
 710
 711 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 712                            sizeof(rte_ixgbe_stats_strings[0]))
 713
 714 /* MACsec statistics */
 715 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 716         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 717                 out_pkts_untagged)},
 718         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 719                 out_pkts_encrypted)},
 720         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 721                 out_pkts_protected)},
 722         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 723                 out_octets_encrypted)},
 724         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 725                 out_octets_protected)},
 726         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 727                 in_pkts_untagged)},
 728         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 729                 in_pkts_badtag)},
 730         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 731                 in_pkts_nosci)},
 732         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 733                 in_pkts_unknownsci)},
 734         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 735                 in_octets_decrypted)},
 736         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 737                 in_octets_validated)},
 738         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 739                 in_pkts_unchecked)},
 740         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 741                 in_pkts_delayed)},
 742         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 743                 in_pkts_late)},
 744         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 745                 in_pkts_ok)},
 746         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 747                 in_pkts_invalid)},
 748         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 749                 in_pkts_notvalid)},
 750         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_unusedsa)},
 752         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_notusingsa)},
 754 };
 755
 756 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 757                            sizeof(rte_ixgbe_macsec_strings[0]))
 758
 759 /* Per-queue statistics */
 760 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 761         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 762         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 763         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 764         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 765 };
 766
 767 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 768                            sizeof(rte_ixgbe_rxq_strings[0]))
 769 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 770
 771 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 772         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 773         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 774         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 775                 pxon2offc)},
 776 };
 777
 778 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 779                            sizeof(rte_ixgbe_txq_strings[0]))
 780 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 781
 782 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 783         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 784 };
 785
 786 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 787                 sizeof(rte_ixgbevf_stats_strings[0]))
 788
 789 /*
 790  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 791  */
 792 static inline int
 793 ixgbe_is_sfp(struct ixgbe_hw *hw)
 794 {
 795         switch (hw->phy.type) {
 796         case ixgbe_phy_sfp_avago:
 797         case ixgbe_phy_sfp_ftl:
 798         case ixgbe_phy_sfp_intel:
 799         case ixgbe_phy_sfp_unknown:
 800         case ixgbe_phy_sfp_passive_tyco:
 801         case ixgbe_phy_sfp_passive_unknown:
 802                 return 1;
 803         default:
 804                 return 0;
 805         }
 806 }
 807
 808 static inline int32_t
 809 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 810 {
 811         uint32_t ctrl_ext;
 812         int32_t status;
 813
 814         status = ixgbe_reset_hw(hw);
 815
 816         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 817         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 818         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 819         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 820         IXGBE_WRITE_FLUSH(hw);
 821
 822         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 823                 status = IXGBE_SUCCESS;
 824         return status;
 825 }
 826
 827 static inline void
 828 ixgbe_enable_intr(struct rte_eth_dev *dev)
 829 {
 830         struct ixgbe_interrupt *intr =
 831                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 832         struct ixgbe_hw *hw =
 833                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 834
 835         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 836         IXGBE_WRITE_FLUSH(hw);
 837 }
 838
 839 /*
 840  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 841  */
 842 static void
 843 ixgbe_disable_intr(struct ixgbe_hw *hw)
 844 {
 845         PMD_INIT_FUNC_TRACE();
 846
 847         if (hw->mac.type == ixgbe_mac_82598EB) {
 848                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 849         } else {
 850                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 851                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 852                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 853         }
 854         IXGBE_WRITE_FLUSH(hw);
 855 }
 856
 857 /*
 858  * This function resets queue statistics mapping registers.
 859  * From Niantic datasheet, Initialization of Statistics section:
 860  * "...if software requires the queue counters, the RQSMR and TQSM registers
 861  * must be re-programmed following a device reset.
 862  */
 863 static void
 864 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 865 {
 866         uint32_t i;
 867
 868         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 869                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 870                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 871         }
 872 }
 873
 874
 875 static int
 876 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 877                                   uint16_t queue_id,
 878                                   uint8_t stat_idx,
 879                                   uint8_t is_rx)
 880 {
 881 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 882 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 883 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 884
 885         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 886         struct ixgbe_stat_mapping_registers *stat_mappings =
 887                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 888         uint32_t qsmr_mask = 0;
 889         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 890         uint32_t q_map;
 891         uint8_t n, offset;
 892
 893         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 894                 (hw->mac.type != ixgbe_mac_X540) &&
 895                 (hw->mac.type != ixgbe_mac_X550) &&
 896                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 897                 (hw->mac.type != ixgbe_mac_X550EM_a))
 898                 return -ENOSYS;
 899
 900         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 901                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 902                      queue_id, stat_idx);
 903
 904         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 905         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 906                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 907                 return -EIO;
 908         }
 909         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 910
 911         /* Now clear any previous stat_idx set */
 912         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 913         if (!is_rx)
 914                 stat_mappings->tqsm[n] &= ~clearing_mask;
 915         else
 916                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 917
 918         q_map = (uint32_t)stat_idx;
 919         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 920         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 921         if (!is_rx)
 922                 stat_mappings->tqsm[n] |= qsmr_mask;
 923         else
 924                 stat_mappings->rqsmr[n] |= qsmr_mask;
 925
 926         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 927                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 928                      queue_id, stat_idx);
 929         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 930                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 931
 932         /* Now write the mapping in the appropriate register */
 933         if (is_rx) {
 934                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 935                              stat_mappings->rqsmr[n], n);
 936                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 937         } else {
 938                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 939                              stat_mappings->tqsm[n], n);
 940                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 941         }
 942         return 0;
 943 }
 944
 945 static void
 946 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 947 {
 948         struct ixgbe_stat_mapping_registers *stat_mappings =
 949                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 950         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 951         int i;
 952
 953         /* write whatever was in stat mapping table to the NIC */
 954         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 955                 /* rx */
 956                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 957
 958                 /* tx */
 959                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 960         }
 961 }
 962
 963 static void
 964 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 965 {
 966         uint8_t i;
 967         struct ixgbe_dcb_tc_config *tc;
 968         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 969
 970         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 971         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 972         for (i = 0; i < dcb_max_tc; i++) {
 973                 tc = &dcb_config->tc_config[i];
 974                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 975                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 976                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 977                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 978                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 979                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 980                 tc->pfc = ixgbe_dcb_pfc_disabled;
 981         }
 982
 983         /* Initialize default user to priority mapping, UPx->TC0 */
 984         tc = &dcb_config->tc_config[0];
 985         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 986         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 987         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 988                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 989                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 990         }
 991         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 992         dcb_config->pfc_mode_enable = false;
 993         dcb_config->vt_mode = true;
 994         dcb_config->round_robin_enable = false;
 995         /* support all DCB capabilities in 82599 */
 996         dcb_config->support.capabilities = 0xFF;
 997
 998         /*we only support 4 Tcs for X540, X550 */
 999         if (hw->mac.type == ixgbe_mac_X540 ||
1000                 hw->mac.type == ixgbe_mac_X550 ||
1001                 hw->mac.type == ixgbe_mac_X550EM_x ||
1002                 hw->mac.type == ixgbe_mac_X550EM_a) {
1003                 dcb_config->num_tcs.pg_tcs = 4;
1004                 dcb_config->num_tcs.pfc_tcs = 4;
1005         }
1006 }
1007
1008 /*
1009  * Ensure that all locks are released before first NVM or PHY access
1010  */
1011 static void
1012 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1013 {
1014         uint16_t mask;
1015
1016         /*
1017          * Phy lock should not fail in this early stage. If this is the case,
1018          * it is due to an improper exit of the application.
1019          * So force the release of the faulty lock. Release of common lock
1020          * is done automatically by swfw_sync function.
1021          */
1022         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1023         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1024                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1025         }
1026         ixgbe_release_swfw_semaphore(hw, mask);
1027
1028         /*
1029          * These ones are more tricky since they are common to all ports; but
1030          * swfw_sync retries last long enough (1s) to be almost sure that if
1031          * lock can not be taken it is due to an improper lock of the
1032          * semaphore.
1033          */
1034         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1035         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1036                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1037         }
1038         ixgbe_release_swfw_semaphore(hw, mask);
1039 }
1040
1041 /*
1042  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1043  * It returns 0 on success.
1044  */
1045 static int
1046 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1047 {
1048         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1049         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1050         struct ixgbe_hw *hw =
1051                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1052         struct ixgbe_vfta *shadow_vfta =
1053                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1054         struct ixgbe_hwstrip *hwstrip =
1055                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1056         struct ixgbe_dcb_config *dcb_config =
1057                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1058         struct ixgbe_filter_info *filter_info =
1059                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1060         struct ixgbe_bw_conf *bw_conf =
1061                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1062         uint32_t ctrl_ext;
1063         uint16_t csum;
1064         int diag, i;
1065
1066         PMD_INIT_FUNC_TRACE();
1067
1068         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1069         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1070         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1071         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1072
1073         /*
1074          * For secondary processes, we don't initialise any further as primary
1075          * has already done this work. Only check we don't need a different
1076          * RX and TX function.
1077          */
1078         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1079                 struct ixgbe_tx_queue *txq;
1080                 /* TX queue function in primary, set by last queue initialized
1081                  * Tx queue may not initialized by primary process
1082                  */
1083                 if (eth_dev->data->tx_queues) {
1084                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1085                         ixgbe_set_tx_function(eth_dev, txq);
1086                 } else {
1087                         /* Use default TX function if we get here */
1088                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1089                                      "Using default TX function.");
1090                 }
1091
1092                 ixgbe_set_rx_function(eth_dev);
1093
1094                 return 0;
1095         }
1096
1097         rte_eth_copy_pci_info(eth_dev, pci_dev);
1098
1099         /* Vendor and Device ID need to be set before init of shared code */
1100         hw->device_id = pci_dev->id.device_id;
1101         hw->vendor_id = pci_dev->id.vendor_id;
1102         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1103         hw->allow_unsupported_sfp = 1;
1104
1105         /* Initialize the shared code (base driver) */
1106 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1107         diag = ixgbe_bypass_init_shared_code(hw);
1108 #else
1109         diag = ixgbe_init_shared_code(hw);
1110 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1111
1112         if (diag != IXGBE_SUCCESS) {
1113                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1114                 return -EIO;
1115         }
1116
1117         /* pick up the PCI bus settings for reporting later */
1118         ixgbe_get_bus_info(hw);
1119
1120         /* Unlock any pending hardware semaphore */
1121         ixgbe_swfw_lock_reset(hw);
1122
1123 #ifdef RTE_LIBRTE_SECURITY
1124         /* Initialize security_ctx only for primary process*/
1125         if (ixgbe_ipsec_ctx_create(eth_dev))
1126                 return -ENOMEM;
1127 #endif
1128
1129         /* Initialize DCB configuration*/
1130         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1131         ixgbe_dcb_init(hw, dcb_config);
1132         /* Get Hardware Flow Control setting */
1133         hw->fc.requested_mode = ixgbe_fc_full;
1134         hw->fc.current_mode = ixgbe_fc_full;
1135         hw->fc.pause_time = IXGBE_FC_PAUSE;
1136         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1137                 hw->fc.low_water[i] = IXGBE_FC_LO;
1138                 hw->fc.high_water[i] = IXGBE_FC_HI;
1139         }
1140         hw->fc.send_xon = 1;
1141
1142         /* Make sure we have a good EEPROM before we read from it */
1143         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1144         if (diag != IXGBE_SUCCESS) {
1145                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1146                 return -EIO;
1147         }
1148
1149 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1150         diag = ixgbe_bypass_init_hw(hw);
1151 #else
1152         diag = ixgbe_init_hw(hw);
1153 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1154
1155         /*
1156          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1157          * is called too soon after the kernel driver unbinding/binding occurs.
1158          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1159          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1160          * also called. See ixgbe_identify_phy_82599(). The reason for the
1161          * failure is not known, and only occuts when virtualisation features
1162          * are disabled in the bios. A delay of 100ms  was found to be enough by
1163          * trial-and-error, and is doubled to be safe.
1164          */
1165         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1166                 rte_delay_ms(200);
1167                 diag = ixgbe_init_hw(hw);
1168         }
1169
1170         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1171                 diag = IXGBE_SUCCESS;
1172
1173         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1174                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1175                              "LOM.  Please be aware there may be issues associated "
1176                              "with your hardware.");
1177                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1178                              "please contact your Intel or hardware representative "
1179                              "who provided you with this hardware.");
1180         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1181                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1182         if (diag) {
1183                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1184                 return -EIO;
1185         }
1186
1187         /* Reset the hw statistics */
1188         ixgbe_dev_stats_reset(eth_dev);
1189
1190         /* disable interrupt */
1191         ixgbe_disable_intr(hw);
1192
1193         /* reset mappings for queue statistics hw counters*/
1194         ixgbe_reset_qstat_mappings(hw);
1195
1196         /* Allocate memory for storing MAC addresses */
1197         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1198                                                hw->mac.num_rar_entries, 0);
1199         if (eth_dev->data->mac_addrs == NULL) {
1200                 PMD_INIT_LOG(ERR,
1201                              "Failed to allocate %u bytes needed to store "
1202                              "MAC addresses",
1203                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1204                 return -ENOMEM;
1205         }
1206         /* Copy the permanent MAC address */
1207         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1208                         &eth_dev->data->mac_addrs[0]);
1209
1210         /* Allocate memory for storing hash filter MAC addresses */
1211         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1212                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1213         if (eth_dev->data->hash_mac_addrs == NULL) {
1214                 PMD_INIT_LOG(ERR,
1215                              "Failed to allocate %d bytes needed to store MAC addresses",
1216                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1217                 return -ENOMEM;
1218         }
1219
1220         /* initialize the vfta */
1221         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1222
1223         /* initialize the hw strip bitmap*/
1224         memset(hwstrip, 0, sizeof(*hwstrip));
1225
1226         /* initialize PF if max_vfs not zero */
1227         ixgbe_pf_host_init(eth_dev);
1228
1229         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1230         /* let hardware know driver is loaded */
1231         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1232         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1233         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1234         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1235         IXGBE_WRITE_FLUSH(hw);
1236
1237         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1238                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1239                              (int) hw->mac.type, (int) hw->phy.type,
1240                              (int) hw->phy.sfp_type);
1241         else
1242                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1243                              (int) hw->mac.type, (int) hw->phy.type);
1244
1245         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1246                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1247                      pci_dev->id.device_id);
1248
1249         rte_intr_callback_register(intr_handle,
1250                                    ixgbe_dev_interrupt_handler, eth_dev);
1251
1252         /* enable uio/vfio intr/eventfd mapping */
1253         rte_intr_enable(intr_handle);
1254
1255         /* enable support intr */
1256         ixgbe_enable_intr(eth_dev);
1257
1258         /* initialize filter info */
1259         memset(filter_info, 0,
1260                sizeof(struct ixgbe_filter_info));
1261
1262         /* initialize 5tuple filter list */
1263         TAILQ_INIT(&filter_info->fivetuple_list);
1264
1265         /* initialize flow director filter list & hash */
1266         ixgbe_fdir_filter_init(eth_dev);
1267
1268         /* initialize l2 tunnel filter list & hash */
1269         ixgbe_l2_tn_filter_init(eth_dev);
1270
1271         /* initialize flow filter lists */
1272         ixgbe_filterlist_init();
1273
1274         /* initialize bandwidth configuration info */
1275         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1276
1277         /* initialize Traffic Manager configuration */
1278         ixgbe_tm_conf_init(eth_dev);
1279
1280         return 0;
1281 }
1282
1283 static int
1284 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1285 {
1286         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1287         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1288         struct ixgbe_hw *hw;
1289         int retries = 0;
1290         int ret;
1291
1292         PMD_INIT_FUNC_TRACE();
1293
1294         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1295                 return -EPERM;
1296
1297         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1298
1299         if (hw->adapter_stopped == 0)
1300                 ixgbe_dev_close(eth_dev);
1301
1302         eth_dev->dev_ops = NULL;
1303         eth_dev->rx_pkt_burst = NULL;
1304         eth_dev->tx_pkt_burst = NULL;
1305
1306         /* Unlock any pending hardware semaphore */
1307         ixgbe_swfw_lock_reset(hw);
1308
1309         /* disable uio intr before callback unregister */
1310         rte_intr_disable(intr_handle);
1311
1312         do {
1313                 ret = rte_intr_callback_unregister(intr_handle,
1314                                 ixgbe_dev_interrupt_handler, eth_dev);
1315                 if (ret >= 0) {
1316                         break;
1317                 } else if (ret != -EAGAIN) {
1318                         PMD_INIT_LOG(ERR,
1319                                 "intr callback unregister failed: %d",
1320                                 ret);
1321                         return ret;
1322                 }
1323                 rte_delay_ms(100);
1324         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1325
1326         /* uninitialize PF if max_vfs not zero */
1327         ixgbe_pf_host_uninit(eth_dev);
1328
1329         rte_free(eth_dev->data->mac_addrs);
1330         eth_dev->data->mac_addrs = NULL;
1331
1332         rte_free(eth_dev->data->hash_mac_addrs);
1333         eth_dev->data->hash_mac_addrs = NULL;
1334
1335         /* remove all the fdir filters & hash */
1336         ixgbe_fdir_filter_uninit(eth_dev);
1337
1338         /* remove all the L2 tunnel filters & hash */
1339         ixgbe_l2_tn_filter_uninit(eth_dev);
1340
1341         /* Remove all ntuple filters of the device */
1342         ixgbe_ntuple_filter_uninit(eth_dev);
1343
1344         /* clear all the filters list */
1345         ixgbe_filterlist_flush();
1346
1347         /* Remove all Traffic Manager configuration */
1348         ixgbe_tm_conf_uninit(eth_dev);
1349
1350 #ifdef RTE_LIBRTE_SECURITY
1351         rte_free(eth_dev->security_ctx);
1352 #endif
1353
1354         return 0;
1355 }
1356
1357 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1358 {
1359         struct ixgbe_filter_info *filter_info =
1360                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1361         struct ixgbe_5tuple_filter *p_5tuple;
1362
1363         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1364                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1365                              p_5tuple,
1366                              entries);
1367                 rte_free(p_5tuple);
1368         }
1369         memset(filter_info->fivetuple_mask, 0,
1370                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1371
1372         return 0;
1373 }
1374
1375 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1376 {
1377         struct ixgbe_hw_fdir_info *fdir_info =
1378                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1379         struct ixgbe_fdir_filter *fdir_filter;
1380
1381                 if (fdir_info->hash_map)
1382                 rte_free(fdir_info->hash_map);
1383         if (fdir_info->hash_handle)
1384                 rte_hash_free(fdir_info->hash_handle);
1385
1386         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1387                 TAILQ_REMOVE(&fdir_info->fdir_list,
1388                              fdir_filter,
1389                              entries);
1390                 rte_free(fdir_filter);
1391         }
1392
1393         return 0;
1394 }
1395
1396 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1397 {
1398         struct ixgbe_l2_tn_info *l2_tn_info =
1399                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1400         struct ixgbe_l2_tn_filter *l2_tn_filter;
1401
1402         if (l2_tn_info->hash_map)
1403                 rte_free(l2_tn_info->hash_map);
1404         if (l2_tn_info->hash_handle)
1405                 rte_hash_free(l2_tn_info->hash_handle);
1406
1407         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1408                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1409                              l2_tn_filter,
1410                              entries);
1411                 rte_free(l2_tn_filter);
1412         }
1413
1414         return 0;
1415 }
1416
1417 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1418 {
1419         struct ixgbe_hw_fdir_info *fdir_info =
1420                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1421         char fdir_hash_name[RTE_HASH_NAMESIZE];
1422         struct rte_hash_parameters fdir_hash_params = {
1423                 .name = fdir_hash_name,
1424                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1425                 .key_len = sizeof(union ixgbe_atr_input),
1426                 .hash_func = rte_hash_crc,
1427                 .hash_func_init_val = 0,
1428                 .socket_id = rte_socket_id(),
1429         };
1430
1431         TAILQ_INIT(&fdir_info->fdir_list);
1432         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1433                  "fdir_%s", eth_dev->device->name);
1434         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1435         if (!fdir_info->hash_handle) {
1436                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1437                 return -EINVAL;
1438         }
1439         fdir_info->hash_map = rte_zmalloc("ixgbe",
1440                                           sizeof(struct ixgbe_fdir_filter *) *
1441                                           IXGBE_MAX_FDIR_FILTER_NUM,
1442                                           0);
1443         if (!fdir_info->hash_map) {
1444                 PMD_INIT_LOG(ERR,
1445                              "Failed to allocate memory for fdir hash map!");
1446                 return -ENOMEM;
1447         }
1448         fdir_info->mask_added = FALSE;
1449
1450         return 0;
1451 }
1452
1453 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1454 {
1455         struct ixgbe_l2_tn_info *l2_tn_info =
1456                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1457         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1458         struct rte_hash_parameters l2_tn_hash_params = {
1459                 .name = l2_tn_hash_name,
1460                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1461                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1462                 .hash_func = rte_hash_crc,
1463                 .hash_func_init_val = 0,
1464                 .socket_id = rte_socket_id(),
1465         };
1466
1467         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1468         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1469                  "l2_tn_%s", eth_dev->device->name);
1470         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1471         if (!l2_tn_info->hash_handle) {
1472                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1473                 return -EINVAL;
1474         }
1475         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1476                                    sizeof(struct ixgbe_l2_tn_filter *) *
1477                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1478                                    0);
1479         if (!l2_tn_info->hash_map) {
1480                 PMD_INIT_LOG(ERR,
1481                         "Failed to allocate memory for L2 TN hash map!");
1482                 return -ENOMEM;
1483         }
1484         l2_tn_info->e_tag_en = FALSE;
1485         l2_tn_info->e_tag_fwd_en = FALSE;
1486         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1487
1488         return 0;
1489 }
1490 /*
1491  * Negotiate mailbox API version with the PF.
1492  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1493  * Then we try to negotiate starting with the most recent one.
1494  * If all negotiation attempts fail, then we will proceed with
1495  * the default one (ixgbe_mbox_api_10).
1496  */
1497 static void
1498 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1499 {
1500         int32_t i;
1501
1502         /* start with highest supported, proceed down */
1503         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1504                 ixgbe_mbox_api_12,
1505                 ixgbe_mbox_api_11,
1506                 ixgbe_mbox_api_10,
1507         };
1508
1509         for (i = 0;
1510                         i != RTE_DIM(sup_ver) &&
1511                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1512                         i++)
1513                 ;
1514 }
1515
1516 static void
1517 generate_random_mac_addr(struct ether_addr *mac_addr)
1518 {
1519         uint64_t random;
1520
1521         /* Set Organizationally Unique Identifier (OUI) prefix. */
1522         mac_addr->addr_bytes[0] = 0x00;
1523         mac_addr->addr_bytes[1] = 0x09;
1524         mac_addr->addr_bytes[2] = 0xC0;
1525         /* Force indication of locally assigned MAC address. */
1526         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1527         /* Generate the last 3 bytes of the MAC address with a random number. */
1528         random = rte_rand();
1529         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1530 }
1531
1532 /*
1533  * Virtual Function device init
1534  */
1535 static int
1536 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1537 {
1538         int diag;
1539         uint32_t tc, tcs;
1540         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1541         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1542         struct ixgbe_hw *hw =
1543                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1544         struct ixgbe_vfta *shadow_vfta =
1545                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1546         struct ixgbe_hwstrip *hwstrip =
1547                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1548         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1549
1550         PMD_INIT_FUNC_TRACE();
1551
1552         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1553         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1554         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1555
1556         /* for secondary processes, we don't initialise any further as primary
1557          * has already done this work. Only check we don't need a different
1558          * RX function
1559          */
1560         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1561                 struct ixgbe_tx_queue *txq;
1562                 /* TX queue function in primary, set by last queue initialized
1563                  * Tx queue may not initialized by primary process
1564                  */
1565                 if (eth_dev->data->tx_queues) {
1566                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1567                         ixgbe_set_tx_function(eth_dev, txq);
1568                 } else {
1569                         /* Use default TX function if we get here */
1570                         PMD_INIT_LOG(NOTICE,
1571                                      "No TX queues configured yet. Using default TX function.");
1572                 }
1573
1574                 ixgbe_set_rx_function(eth_dev);
1575
1576                 return 0;
1577         }
1578
1579         rte_eth_copy_pci_info(eth_dev, pci_dev);
1580
1581         hw->device_id = pci_dev->id.device_id;
1582         hw->vendor_id = pci_dev->id.vendor_id;
1583         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1584
1585         /* initialize the vfta */
1586         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1587
1588         /* initialize the hw strip bitmap*/
1589         memset(hwstrip, 0, sizeof(*hwstrip));
1590
1591         /* Initialize the shared code (base driver) */
1592         diag = ixgbe_init_shared_code(hw);
1593         if (diag != IXGBE_SUCCESS) {
1594                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1595                 return -EIO;
1596         }
1597
1598         /* init_mailbox_params */
1599         hw->mbx.ops.init_params(hw);
1600
1601         /* Reset the hw statistics */
1602         ixgbevf_dev_stats_reset(eth_dev);
1603
1604         /* Disable the interrupts for VF */
1605         ixgbevf_intr_disable(hw);
1606
1607         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1608         diag = hw->mac.ops.reset_hw(hw);
1609
1610         /*
1611          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1612          * the underlying PF driver has not assigned a MAC address to the VF.
1613          * In this case, assign a random MAC address.
1614          */
1615         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1616                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1617                 return diag;
1618         }
1619
1620         /* negotiate mailbox API version to use with the PF. */
1621         ixgbevf_negotiate_api(hw);
1622
1623         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1624         ixgbevf_get_queues(hw, &tcs, &tc);
1625
1626         /* Allocate memory for storing MAC addresses */
1627         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1628                                                hw->mac.num_rar_entries, 0);
1629         if (eth_dev->data->mac_addrs == NULL) {
1630                 PMD_INIT_LOG(ERR,
1631                              "Failed to allocate %u bytes needed to store "
1632                              "MAC addresses",
1633                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1634                 return -ENOMEM;
1635         }
1636
1637         /* Generate a random MAC address, if none was assigned by PF. */
1638         if (is_zero_ether_addr(perm_addr)) {
1639                 generate_random_mac_addr(perm_addr);
1640                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1641                 if (diag) {
1642                         rte_free(eth_dev->data->mac_addrs);
1643                         eth_dev->data->mac_addrs = NULL;
1644                         return diag;
1645                 }
1646                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1647                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1648                              "%02x:%02x:%02x:%02x:%02x:%02x",
1649                              perm_addr->addr_bytes[0],
1650                              perm_addr->addr_bytes[1],
1651                              perm_addr->addr_bytes[2],
1652                              perm_addr->addr_bytes[3],
1653                              perm_addr->addr_bytes[4],
1654                              perm_addr->addr_bytes[5]);
1655         }
1656
1657         /* Copy the permanent MAC address */
1658         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1659
1660         /* reset the hardware with the new settings */
1661         diag = hw->mac.ops.start_hw(hw);
1662         switch (diag) {
1663         case  0:
1664                 break;
1665
1666         default:
1667                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1668                 return -EIO;
1669         }
1670
1671         rte_intr_callback_register(intr_handle,
1672                                    ixgbevf_dev_interrupt_handler, eth_dev);
1673         rte_intr_enable(intr_handle);
1674         ixgbevf_intr_enable(hw);
1675
1676         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1677                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1678                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1679
1680         return 0;
1681 }
1682
1683 /* Virtual Function device uninit */
1684
1685 static int
1686 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1687 {
1688         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1689         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1690         struct ixgbe_hw *hw;
1691
1692         PMD_INIT_FUNC_TRACE();
1693
1694         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1695                 return -EPERM;
1696
1697         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1698
1699         if (hw->adapter_stopped == 0)
1700                 ixgbevf_dev_close(eth_dev);
1701
1702         eth_dev->dev_ops = NULL;
1703         eth_dev->rx_pkt_burst = NULL;
1704         eth_dev->tx_pkt_burst = NULL;
1705
1706         /* Disable the interrupts for VF */
1707         ixgbevf_intr_disable(hw);
1708
1709         rte_free(eth_dev->data->mac_addrs);
1710         eth_dev->data->mac_addrs = NULL;
1711
1712         rte_intr_disable(intr_handle);
1713         rte_intr_callback_unregister(intr_handle,
1714                                      ixgbevf_dev_interrupt_handler, eth_dev);
1715
1716         return 0;
1717 }
1718
1719 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1720         struct rte_pci_device *pci_dev)
1721 {
1722         return rte_eth_dev_pci_generic_probe(pci_dev,
1723                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1724 }
1725
1726 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1727 {
1728         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1729 }
1730
1731 static struct rte_pci_driver rte_ixgbe_pmd = {
1732         .id_table = pci_id_ixgbe_map,
1733         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1734                      RTE_PCI_DRV_IOVA_AS_VA,
1735         .probe = eth_ixgbe_pci_probe,
1736         .remove = eth_ixgbe_pci_remove,
1737 };
1738
1739 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1740         struct rte_pci_device *pci_dev)
1741 {
1742         return rte_eth_dev_pci_generic_probe(pci_dev,
1743                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1744 }
1745
1746 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1747 {
1748         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1749 }
1750
1751 /*
1752  * virtual function driver struct
1753  */
1754 static struct rte_pci_driver rte_ixgbevf_pmd = {
1755         .id_table = pci_id_ixgbevf_map,
1756         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1757         .probe = eth_ixgbevf_pci_probe,
1758         .remove = eth_ixgbevf_pci_remove,
1759 };
1760
1761 static int
1762 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1763 {
1764         struct ixgbe_hw *hw =
1765                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1766         struct ixgbe_vfta *shadow_vfta =
1767                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1768         uint32_t vfta;
1769         uint32_t vid_idx;
1770         uint32_t vid_bit;
1771
1772         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1773         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1774         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1775         if (on)
1776                 vfta |= vid_bit;
1777         else
1778                 vfta &= ~vid_bit;
1779         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1780
1781         /* update local VFTA copy */
1782         shadow_vfta->vfta[vid_idx] = vfta;
1783
1784         return 0;
1785 }
1786
1787 static void
1788 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1789 {
1790         if (on)
1791                 ixgbe_vlan_hw_strip_enable(dev, queue);
1792         else
1793                 ixgbe_vlan_hw_strip_disable(dev, queue);
1794 }
1795
1796 static int
1797 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1798                     enum rte_vlan_type vlan_type,
1799                     uint16_t tpid)
1800 {
1801         struct ixgbe_hw *hw =
1802                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1803         int ret = 0;
1804         uint32_t reg;
1805         uint32_t qinq;
1806
1807         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1808         qinq &= IXGBE_DMATXCTL_GDV;
1809
1810         switch (vlan_type) {
1811         case ETH_VLAN_TYPE_INNER:
1812                 if (qinq) {
1813                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1814                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1815                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1816                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1817                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1818                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1819                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1820                 } else {
1821                         ret = -ENOTSUP;
1822                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1823                                     " by single VLAN");
1824                 }
1825                 break;
1826         case ETH_VLAN_TYPE_OUTER:
1827                 if (qinq) {
1828                         /* Only the high 16-bits is valid */
1829                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1830                                         IXGBE_EXVET_VET_EXT_SHIFT);
1831                 } else {
1832                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1833                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1834                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1835                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1836                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1837                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1838                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1839                 }
1840
1841                 break;
1842         default:
1843                 ret = -EINVAL;
1844                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1845                 break;
1846         }
1847
1848         return ret;
1849 }
1850
1851 void
1852 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1853 {
1854         struct ixgbe_hw *hw =
1855                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1856         uint32_t vlnctrl;
1857
1858         PMD_INIT_FUNC_TRACE();
1859
1860         /* Filter Table Disable */
1861         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1862         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1863
1864         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1865 }
1866
1867 void
1868 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1869 {
1870         struct ixgbe_hw *hw =
1871                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872         struct ixgbe_vfta *shadow_vfta =
1873                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1874         uint32_t vlnctrl;
1875         uint16_t i;
1876
1877         PMD_INIT_FUNC_TRACE();
1878
1879         /* Filter Table Enable */
1880         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1881         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1882         vlnctrl |= IXGBE_VLNCTRL_VFE;
1883
1884         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1885
1886         /* write whatever is in local vfta copy */
1887         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1888                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1889 }
1890
1891 static void
1892 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1893 {
1894         struct ixgbe_hwstrip *hwstrip =
1895                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1896         struct ixgbe_rx_queue *rxq;
1897
1898         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1899                 return;
1900
1901         if (on)
1902                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1903         else
1904                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1905
1906         if (queue >= dev->data->nb_rx_queues)
1907                 return;
1908
1909         rxq = dev->data->rx_queues[queue];
1910
1911         if (on)
1912                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1913         else
1914                 rxq->vlan_flags = PKT_RX_VLAN;
1915 }
1916
1917 static void
1918 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1919 {
1920         struct ixgbe_hw *hw =
1921                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         uint32_t ctrl;
1923
1924         PMD_INIT_FUNC_TRACE();
1925
1926         if (hw->mac.type == ixgbe_mac_82598EB) {
1927                 /* No queue level support */
1928                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1929                 return;
1930         }
1931
1932         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1933         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1934         ctrl &= ~IXGBE_RXDCTL_VME;
1935         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1936
1937         /* record those setting for HW strip per queue */
1938         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1939 }
1940
1941 static void
1942 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1943 {
1944         struct ixgbe_hw *hw =
1945                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1946         uint32_t ctrl;
1947
1948         PMD_INIT_FUNC_TRACE();
1949
1950         if (hw->mac.type == ixgbe_mac_82598EB) {
1951                 /* No queue level supported */
1952                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1953                 return;
1954         }
1955
1956         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1957         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1958         ctrl |= IXGBE_RXDCTL_VME;
1959         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1960
1961         /* record those setting for HW strip per queue */
1962         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1963 }
1964
1965 static void
1966 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1967 {
1968         struct ixgbe_hw *hw =
1969                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1970         uint32_t ctrl;
1971
1972         PMD_INIT_FUNC_TRACE();
1973
1974         /* DMATXCTRL: Geric Double VLAN Disable */
1975         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1976         ctrl &= ~IXGBE_DMATXCTL_GDV;
1977         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1978
1979         /* CTRL_EXT: Global Double VLAN Disable */
1980         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1981         ctrl &= ~IXGBE_EXTENDED_VLAN;
1982         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1983
1984 }
1985
1986 static void
1987 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1988 {
1989         struct ixgbe_hw *hw =
1990                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1991         uint32_t ctrl;
1992
1993         PMD_INIT_FUNC_TRACE();
1994
1995         /* DMATXCTRL: Geric Double VLAN Enable */
1996         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1997         ctrl |= IXGBE_DMATXCTL_GDV;
1998         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1999
2000         /* CTRL_EXT: Global Double VLAN Enable */
2001         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2002         ctrl |= IXGBE_EXTENDED_VLAN;
2003         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2004
2005         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2006         if (hw->mac.type == ixgbe_mac_X550 ||
2007             hw->mac.type == ixgbe_mac_X550EM_x ||
2008             hw->mac.type == ixgbe_mac_X550EM_a) {
2009                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2010                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2011                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2012         }
2013
2014         /*
2015          * VET EXT field in the EXVET register = 0x8100 by default
2016          * So no need to change. Same to VT field of DMATXCTL register
2017          */
2018 }
2019
2020 void
2021 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2022 {
2023         struct ixgbe_hw *hw =
2024                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2025         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2026         uint32_t ctrl;
2027         uint16_t i;
2028         struct ixgbe_rx_queue *rxq;
2029         bool on;
2030
2031         PMD_INIT_FUNC_TRACE();
2032
2033         if (hw->mac.type == ixgbe_mac_82598EB) {
2034                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2035                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2036                         ctrl |= IXGBE_VLNCTRL_VME;
2037                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2038                 } else {
2039                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2040                         ctrl &= ~IXGBE_VLNCTRL_VME;
2041                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2042                 }
2043         } else {
2044                 /*
2045                  * Other 10G NIC, the VLAN strip can be setup
2046                  * per queue in RXDCTL
2047                  */
2048                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2049                         rxq = dev->data->rx_queues[i];
2050                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2051                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2052                                 ctrl |= IXGBE_RXDCTL_VME;
2053                                 on = TRUE;
2054                         } else {
2055                                 ctrl &= ~IXGBE_RXDCTL_VME;
2056                                 on = FALSE;
2057                         }
2058                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2059
2060                         /* record those setting for HW strip per queue */
2061                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2062                 }
2063         }
2064 }
2065
2066 static int
2067 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2068 {
2069         struct rte_eth_rxmode *rxmode;
2070         rxmode = &dev->data->dev_conf.rxmode;
2071
2072         if (mask & ETH_VLAN_STRIP_MASK) {
2073                 ixgbe_vlan_hw_strip_config(dev);
2074         }
2075
2076         if (mask & ETH_VLAN_FILTER_MASK) {
2077                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2078                         ixgbe_vlan_hw_filter_enable(dev);
2079                 else
2080                         ixgbe_vlan_hw_filter_disable(dev);
2081         }
2082
2083         if (mask & ETH_VLAN_EXTEND_MASK) {
2084                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2085                         ixgbe_vlan_hw_extend_enable(dev);
2086                 else
2087                         ixgbe_vlan_hw_extend_disable(dev);
2088         }
2089
2090         return 0;
2091 }
2092
2093 static void
2094 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2095 {
2096         struct ixgbe_hw *hw =
2097                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2098         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2099         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2100
2101         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2102         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2103 }
2104
2105 static int
2106 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2107 {
2108         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2109
2110         switch (nb_rx_q) {
2111         case 1:
2112         case 2:
2113                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2114                 break;
2115         case 4:
2116                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2117                 break;
2118         default:
2119                 return -EINVAL;
2120         }
2121
2122         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2123                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2124         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2125                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2126         return 0;
2127 }
2128
2129 static int
2130 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2131 {
2132         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2133         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2134         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2135         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2136
2137         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2138                 /* check multi-queue mode */
2139                 switch (dev_conf->rxmode.mq_mode) {
2140                 case ETH_MQ_RX_VMDQ_DCB:
2141                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2142                         break;
2143                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2144                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2145                         PMD_INIT_LOG(ERR, "SRIOV active,"
2146                                         " unsupported mq_mode rx %d.",
2147                                         dev_conf->rxmode.mq_mode);
2148                         return -EINVAL;
2149                 case ETH_MQ_RX_RSS:
2150                 case ETH_MQ_RX_VMDQ_RSS:
2151                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2152                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2153                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2154                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2155                                                 " invalid queue number"
2156                                                 " for VMDQ RSS, allowed"
2157                                                 " value are 1, 2 or 4.");
2158                                         return -EINVAL;
2159                                 }
2160                         break;
2161                 case ETH_MQ_RX_VMDQ_ONLY:
2162                 case ETH_MQ_RX_NONE:
2163                         /* if nothing mq mode configure, use default scheme */
2164                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2165                         break;
2166                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2167                         /* SRIOV only works in VMDq enable mode */
2168                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2169                                         " wrong mq_mode rx %d.",
2170                                         dev_conf->rxmode.mq_mode);
2171                         return -EINVAL;
2172                 }
2173
2174                 switch (dev_conf->txmode.mq_mode) {
2175                 case ETH_MQ_TX_VMDQ_DCB:
2176                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2177                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2178                         break;
2179                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2180                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2181                         break;
2182                 }
2183
2184                 /* check valid queue number */
2185                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2186                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2187                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2188                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2189                                         " must be less than or equal to %d.",
2190                                         nb_rx_q, nb_tx_q,
2191                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2192                         return -EINVAL;
2193                 }
2194         } else {
2195                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2196                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2197                                           " not supported.");
2198                         return -EINVAL;
2199                 }
2200                 /* check configuration for vmdb+dcb mode */
2201                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2202                         const struct rte_eth_vmdq_dcb_conf *conf;
2203
2204                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2205                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2206                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2207                                 return -EINVAL;
2208                         }
2209                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2210                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2211                                conf->nb_queue_pools == ETH_32_POOLS)) {
2212                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2213                                                 " nb_queue_pools must be %d or %d.",
2214                                                 ETH_16_POOLS, ETH_32_POOLS);
2215                                 return -EINVAL;
2216                         }
2217                 }
2218                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2219                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2220
2221                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2222                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2223                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2224                                 return -EINVAL;
2225                         }
2226                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2227                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2228                                conf->nb_queue_pools == ETH_32_POOLS)) {
2229                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2230                                                 " nb_queue_pools != %d and"
2231                                                 " nb_queue_pools != %d.",
2232                                                 ETH_16_POOLS, ETH_32_POOLS);
2233                                 return -EINVAL;
2234                         }
2235                 }
2236
2237                 /* For DCB mode check our configuration before we go further */
2238                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2239                         const struct rte_eth_dcb_rx_conf *conf;
2240
2241                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2242                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2243                                                  IXGBE_DCB_NB_QUEUES);
2244                                 return -EINVAL;
2245                         }
2246                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2247                         if (!(conf->nb_tcs == ETH_4_TCS ||
2248                                conf->nb_tcs == ETH_8_TCS)) {
2249                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2250                                                 " and nb_tcs != %d.",
2251                                                 ETH_4_TCS, ETH_8_TCS);
2252                                 return -EINVAL;
2253                         }
2254                 }
2255
2256                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2257                         const struct rte_eth_dcb_tx_conf *conf;
2258
2259                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2260                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2261                                                  IXGBE_DCB_NB_QUEUES);
2262                                 return -EINVAL;
2263                         }
2264                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2265                         if (!(conf->nb_tcs == ETH_4_TCS ||
2266                                conf->nb_tcs == ETH_8_TCS)) {
2267                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2268                                                 " and nb_tcs != %d.",
2269                                                 ETH_4_TCS, ETH_8_TCS);
2270                                 return -EINVAL;
2271                         }
2272                 }
2273
2274                 /*
2275                  * When DCB/VT is off, maximum number of queues changes,
2276                  * except for 82598EB, which remains constant.
2277                  */
2278                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2279                                 hw->mac.type != ixgbe_mac_82598EB) {
2280                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2281                                 PMD_INIT_LOG(ERR,
2282                                              "Neither VT nor DCB are enabled, "
2283                                              "nb_tx_q > %d.",
2284                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2285                                 return -EINVAL;
2286                         }
2287                 }
2288         }
2289         return 0;
2290 }
2291
2292 static int
2293 ixgbe_dev_configure(struct rte_eth_dev *dev)
2294 {
2295         struct ixgbe_interrupt *intr =
2296                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2297         struct ixgbe_adapter *adapter =
2298                 (struct ixgbe_adapter *)dev->data->dev_private;
2299         struct rte_eth_dev_info dev_info;
2300         uint64_t rx_offloads;
2301         uint64_t tx_offloads;
2302         int ret;
2303
2304         PMD_INIT_FUNC_TRACE();
2305         /* multipe queue mode checking */
2306         ret  = ixgbe_check_mq_mode(dev);
2307         if (ret != 0) {
2308                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2309                             ret);
2310                 return ret;
2311         }
2312
2313         ixgbe_dev_info_get(dev, &dev_info);
2314         rx_offloads = dev->data->dev_conf.rxmode.offloads;
2315         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
2316                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
2317                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2318                             rx_offloads, dev_info.rx_offload_capa);
2319                 return -ENOTSUP;
2320         }
2321         tx_offloads = dev->data->dev_conf.txmode.offloads;
2322         if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
2323                 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
2324                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2325                             tx_offloads, dev_info.tx_offload_capa);
2326                 return -ENOTSUP;
2327         }
2328
2329         /* set flag to update link status after init */
2330         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2331
2332         /*
2333          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2334          * allocation or vector Rx preconditions we will reset it.
2335          */
2336         adapter->rx_bulk_alloc_allowed = true;
2337         adapter->rx_vec_allowed = true;
2338
2339         return 0;
2340 }
2341
2342 static void
2343 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2344 {
2345         struct ixgbe_hw *hw =
2346                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2347         struct ixgbe_interrupt *intr =
2348                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2349         uint32_t gpie;
2350
2351         /* only set up it on X550EM_X */
2352         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2353                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2354                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2355                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2356                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2357                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2358         }
2359 }
2360
2361 int
2362 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2363                         uint16_t tx_rate, uint64_t q_msk)
2364 {
2365         struct ixgbe_hw *hw;
2366         struct ixgbe_vf_info *vfinfo;
2367         struct rte_eth_link link;
2368         uint8_t  nb_q_per_pool;
2369         uint32_t queue_stride;
2370         uint32_t queue_idx, idx = 0, vf_idx;
2371         uint32_t queue_end;
2372         uint16_t total_rate = 0;
2373         struct rte_pci_device *pci_dev;
2374
2375         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2376         rte_eth_link_get_nowait(dev->data->port_id, &link);
2377
2378         if (vf >= pci_dev->max_vfs)
2379                 return -EINVAL;
2380
2381         if (tx_rate > link.link_speed)
2382                 return -EINVAL;
2383
2384         if (q_msk == 0)
2385                 return 0;
2386
2387         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2388         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2389         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2390         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2391         queue_idx = vf * queue_stride;
2392         queue_end = queue_idx + nb_q_per_pool - 1;
2393         if (queue_end >= hw->mac.max_tx_queues)
2394                 return -EINVAL;
2395
2396         if (vfinfo) {
2397                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2398                         if (vf_idx == vf)
2399                                 continue;
2400                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2401                                 idx++)
2402                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2403                 }
2404         } else {
2405                 return -EINVAL;
2406         }
2407
2408         /* Store tx_rate for this vf. */
2409         for (idx = 0; idx < nb_q_per_pool; idx++) {
2410                 if (((uint64_t)0x1 << idx) & q_msk) {
2411                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2412                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2413                         total_rate += tx_rate;
2414                 }
2415         }
2416
2417         if (total_rate > dev->data->dev_link.link_speed) {
2418                 /* Reset stored TX rate of the VF if it causes exceed
2419                  * link speed.
2420                  */
2421                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2422                 return -EINVAL;
2423         }
2424
2425         /* Set RTTBCNRC of each queue/pool for vf X  */
2426         for (; queue_idx <= queue_end; queue_idx++) {
2427                 if (0x1 & q_msk)
2428                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2429                 q_msk = q_msk >> 1;
2430         }
2431
2432         return 0;
2433 }
2434
2435 /*
2436  * Configure device link speed and setup link.
2437  * It returns 0 on success.
2438  */
2439 static int
2440 ixgbe_dev_start(struct rte_eth_dev *dev)
2441 {
2442         struct ixgbe_hw *hw =
2443                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2444         struct ixgbe_vf_info *vfinfo =
2445                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2446         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2447         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2448         uint32_t intr_vector = 0;
2449         int err, link_up = 0, negotiate = 0;
2450         uint32_t speed = 0;
2451         int mask = 0;
2452         int status;
2453         uint16_t vf, idx;
2454         uint32_t *link_speeds;
2455         struct ixgbe_tm_conf *tm_conf =
2456                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2457
2458         PMD_INIT_FUNC_TRACE();
2459
2460         /* IXGBE devices don't support:
2461         *    - half duplex (checked afterwards for valid speeds)
2462         *    - fixed speed: TODO implement
2463         */
2464         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2465                 PMD_INIT_LOG(ERR,
2466                 "Invalid link_speeds for port %u, fix speed not supported",
2467                                 dev->data->port_id);
2468                 return -EINVAL;
2469         }
2470
2471         /* disable uio/vfio intr/eventfd mapping */
2472         rte_intr_disable(intr_handle);
2473
2474         /* stop adapter */
2475         hw->adapter_stopped = 0;
2476         ixgbe_stop_adapter(hw);
2477
2478         /* reinitialize adapter
2479          * this calls reset and start
2480          */
2481         status = ixgbe_pf_reset_hw(hw);
2482         if (status != 0)
2483                 return -1;
2484         hw->mac.ops.start_hw(hw);
2485         hw->mac.get_link_status = true;
2486
2487         /* configure PF module if SRIOV enabled */
2488         ixgbe_pf_host_configure(dev);
2489
2490         ixgbe_dev_phy_intr_setup(dev);
2491
2492         /* check and configure queue intr-vector mapping */
2493         if ((rte_intr_cap_multiple(intr_handle) ||
2494              !RTE_ETH_DEV_SRIOV(dev).active) &&
2495             dev->data->dev_conf.intr_conf.rxq != 0) {
2496                 intr_vector = dev->data->nb_rx_queues;
2497                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2498                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2499                                         IXGBE_MAX_INTR_QUEUE_NUM);
2500                         return -ENOTSUP;
2501                 }
2502                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2503                         return -1;
2504         }
2505
2506         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2507                 intr_handle->intr_vec =
2508                         rte_zmalloc("intr_vec",
2509                                     dev->data->nb_rx_queues * sizeof(int), 0);
2510                 if (intr_handle->intr_vec == NULL) {
2511                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2512                                      " intr_vec", dev->data->nb_rx_queues);
2513                         return -ENOMEM;
2514                 }
2515         }
2516
2517         /* confiugre msix for sleep until rx interrupt */
2518         ixgbe_configure_msix(dev);
2519
2520         /* initialize transmission unit */
2521         ixgbe_dev_tx_init(dev);
2522
2523         /* This can fail when allocating mbufs for descriptor rings */
2524         err = ixgbe_dev_rx_init(dev);
2525         if (err) {
2526                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2527                 goto error;
2528         }
2529
2530         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2531                 ETH_VLAN_EXTEND_MASK;
2532         err = ixgbe_vlan_offload_set(dev, mask);
2533         if (err) {
2534                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2535                 goto error;
2536         }
2537
2538         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2539                 /* Enable vlan filtering for VMDq */
2540                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2541         }
2542
2543         /* Configure DCB hw */
2544         ixgbe_configure_dcb(dev);
2545
2546         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2547                 err = ixgbe_fdir_configure(dev);
2548                 if (err)
2549                         goto error;
2550         }
2551
2552         /* Restore vf rate limit */
2553         if (vfinfo != NULL) {
2554                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2555                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2556                                 if (vfinfo[vf].tx_rate[idx] != 0)
2557                                         ixgbe_set_vf_rate_limit(
2558                                                 dev, vf,
2559                                                 vfinfo[vf].tx_rate[idx],
2560                                                 1 << idx);
2561         }
2562
2563         ixgbe_restore_statistics_mapping(dev);
2564
2565         err = ixgbe_dev_rxtx_start(dev);
2566         if (err < 0) {
2567                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2568                 goto error;
2569         }
2570
2571         /* Skip link setup if loopback mode is enabled for 82599. */
2572         if (hw->mac.type == ixgbe_mac_82599EB &&
2573                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2574                 goto skip_link_setup;
2575
2576         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2577                 err = hw->mac.ops.setup_sfp(hw);
2578                 if (err)
2579                         goto error;
2580         }
2581
2582         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2583                 /* Turn on the copper */
2584                 ixgbe_set_phy_power(hw, true);
2585         } else {
2586                 /* Turn on the laser */
2587                 ixgbe_enable_tx_laser(hw);
2588         }
2589
2590         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2591         if (err)
2592                 goto error;
2593         dev->data->dev_link.link_status = link_up;
2594
2595         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2596         if (err)
2597                 goto error;
2598
2599         link_speeds = &dev->data->dev_conf.link_speeds;
2600         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2601                         ETH_LINK_SPEED_10G)) {
2602                 PMD_INIT_LOG(ERR, "Invalid link setting");
2603                 goto error;
2604         }
2605
2606         speed = 0x0;
2607         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2608                 switch (hw->mac.type) {
2609                 case ixgbe_mac_82598EB:
2610                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2611                         break;
2612                 case ixgbe_mac_82599EB:
2613                 case ixgbe_mac_X540:
2614                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2615                         break;
2616                 case ixgbe_mac_X550:
2617                 case ixgbe_mac_X550EM_x:
2618                 case ixgbe_mac_X550EM_a:
2619                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2620                         break;
2621                 default:
2622                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2623                 }
2624         } else {
2625                 if (*link_speeds & ETH_LINK_SPEED_10G)
2626                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2627                 if (*link_speeds & ETH_LINK_SPEED_1G)
2628                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2629                 if (*link_speeds & ETH_LINK_SPEED_100M)
2630                         speed |= IXGBE_LINK_SPEED_100_FULL;
2631         }
2632
2633         err = ixgbe_setup_link(hw, speed, link_up);
2634         if (err)
2635                 goto error;
2636
2637         ixgbe_dev_link_update(dev, 0);
2638
2639 skip_link_setup:
2640
2641         if (rte_intr_allow_others(intr_handle)) {
2642                 /* check if lsc interrupt is enabled */
2643                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2644                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2645                 else
2646                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2647                 ixgbe_dev_macsec_interrupt_setup(dev);
2648         } else {
2649                 rte_intr_callback_unregister(intr_handle,
2650                                              ixgbe_dev_interrupt_handler, dev);
2651                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2652                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2653                                      " no intr multiplex");
2654         }
2655
2656         /* check if rxq interrupt is enabled */
2657         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2658             rte_intr_dp_is_en(intr_handle))
2659                 ixgbe_dev_rxq_interrupt_setup(dev);
2660
2661         /* enable uio/vfio intr/eventfd mapping */
2662         rte_intr_enable(intr_handle);
2663
2664         /* resume enabled intr since hw reset */
2665         ixgbe_enable_intr(dev);
2666         ixgbe_l2_tunnel_conf(dev);
2667         ixgbe_filter_restore(dev);
2668
2669         if (tm_conf->root && !tm_conf->committed)
2670                 PMD_DRV_LOG(WARNING,
2671                             "please call hierarchy_commit() "
2672                             "before starting the port");
2673
2674         return 0;
2675
2676 error:
2677         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2678         ixgbe_dev_clear_queues(dev);
2679         return -EIO;
2680 }
2681
2682 /*
2683  * Stop device: disable rx and tx functions to allow for reconfiguring.
2684  */
2685 static void
2686 ixgbe_dev_stop(struct rte_eth_dev *dev)
2687 {
2688         struct rte_eth_link link;
2689         struct ixgbe_hw *hw =
2690                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2691         struct ixgbe_vf_info *vfinfo =
2692                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2693         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2694         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2695         int vf;
2696         struct ixgbe_tm_conf *tm_conf =
2697                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2698
2699         PMD_INIT_FUNC_TRACE();
2700
2701         /* disable interrupts */
2702         ixgbe_disable_intr(hw);
2703
2704         /* reset the NIC */
2705         ixgbe_pf_reset_hw(hw);
2706         hw->adapter_stopped = 0;
2707
2708         /* stop adapter */
2709         ixgbe_stop_adapter(hw);
2710
2711         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2712                 vfinfo[vf].clear_to_send = false;
2713
2714         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2715                 /* Turn off the copper */
2716                 ixgbe_set_phy_power(hw, false);
2717         } else {
2718                 /* Turn off the laser */
2719                 ixgbe_disable_tx_laser(hw);
2720         }
2721
2722         ixgbe_dev_clear_queues(dev);
2723
2724         /* Clear stored conf */
2725         dev->data->scattered_rx = 0;
2726         dev->data->lro = 0;
2727
2728         /* Clear recorded link status */
2729         memset(&link, 0, sizeof(link));
2730         rte_eth_linkstatus_set(dev, &link);
2731
2732         if (!rte_intr_allow_others(intr_handle))
2733                 /* resume to the default handler */
2734                 rte_intr_callback_register(intr_handle,
2735                                            ixgbe_dev_interrupt_handler,
2736                                            (void *)dev);
2737
2738         /* Clean datapath event and queue/vec mapping */
2739         rte_intr_efd_disable(intr_handle);
2740         if (intr_handle->intr_vec != NULL) {
2741                 rte_free(intr_handle->intr_vec);
2742                 intr_handle->intr_vec = NULL;
2743         }
2744
2745         /* reset hierarchy commit */
2746         tm_conf->committed = false;
2747 }
2748
2749 /*
2750  * Set device link up: enable tx.
2751  */
2752 static int
2753 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2754 {
2755         struct ixgbe_hw *hw =
2756                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2757         if (hw->mac.type == ixgbe_mac_82599EB) {
2758 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2759                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2760                         /* Not suported in bypass mode */
2761                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2762                                      "by device id 0x%x", hw->device_id);
2763                         return -ENOTSUP;
2764                 }
2765 #endif
2766         }
2767
2768         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2769                 /* Turn on the copper */
2770                 ixgbe_set_phy_power(hw, true);
2771         } else {
2772                 /* Turn on the laser */
2773                 ixgbe_enable_tx_laser(hw);
2774         }
2775
2776         return 0;
2777 }
2778
2779 /*
2780  * Set device link down: disable tx.
2781  */
2782 static int
2783 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2784 {
2785         struct ixgbe_hw *hw =
2786                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2787         if (hw->mac.type == ixgbe_mac_82599EB) {
2788 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2789                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2790                         /* Not suported in bypass mode */
2791                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2792                                      "by device id 0x%x", hw->device_id);
2793                         return -ENOTSUP;
2794                 }
2795 #endif
2796         }
2797
2798         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2799                 /* Turn off the copper */
2800                 ixgbe_set_phy_power(hw, false);
2801         } else {
2802                 /* Turn off the laser */
2803                 ixgbe_disable_tx_laser(hw);
2804         }
2805
2806         return 0;
2807 }
2808
2809 /*
2810  * Reset and stop device.
2811  */
2812 static void
2813 ixgbe_dev_close(struct rte_eth_dev *dev)
2814 {
2815         struct ixgbe_hw *hw =
2816                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2817
2818         PMD_INIT_FUNC_TRACE();
2819
2820         ixgbe_pf_reset_hw(hw);
2821
2822         ixgbe_dev_stop(dev);
2823         hw->adapter_stopped = 1;
2824
2825         ixgbe_dev_free_queues(dev);
2826
2827         ixgbe_disable_pcie_master(hw);
2828
2829         /* reprogram the RAR[0] in case user changed it. */
2830         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2831 }
2832
2833 /*
2834  * Reset PF device.
2835  */
2836 static int
2837 ixgbe_dev_reset(struct rte_eth_dev *dev)
2838 {
2839         int ret;
2840
2841         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2842          * its VF to make them align with it. The detailed notification
2843          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2844          * To avoid unexpected behavior in VF, currently reset of PF with
2845          * SR-IOV activation is not supported. It might be supported later.
2846          */
2847         if (dev->data->sriov.active)
2848                 return -ENOTSUP;
2849
2850         ret = eth_ixgbe_dev_uninit(dev);
2851         if (ret)
2852                 return ret;
2853
2854         ret = eth_ixgbe_dev_init(dev);
2855
2856         return ret;
2857 }
2858
2859 static void
2860 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2861                            struct ixgbe_hw_stats *hw_stats,
2862                            struct ixgbe_macsec_stats *macsec_stats,
2863                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2864                            uint64_t *total_qprc, uint64_t *total_qprdc)
2865 {
2866         uint32_t bprc, lxon, lxoff, total;
2867         uint32_t delta_gprc = 0;
2868         unsigned i;
2869         /* Workaround for RX byte count not including CRC bytes when CRC
2870          * strip is enabled. CRC bytes are removed from counters when crc_strip
2871          * is disabled.
2872          */
2873         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2874                         IXGBE_HLREG0_RXCRCSTRP);
2875
2876         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2877         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2878         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2879         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2880
2881         for (i = 0; i < 8; i++) {
2882                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2883
2884                 /* global total per queue */
2885                 hw_stats->mpc[i] += mp;
2886                 /* Running comprehensive total for stats display */
2887                 *total_missed_rx += hw_stats->mpc[i];
2888                 if (hw->mac.type == ixgbe_mac_82598EB) {
2889                         hw_stats->rnbc[i] +=
2890                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2891                         hw_stats->pxonrxc[i] +=
2892                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2893                         hw_stats->pxoffrxc[i] +=
2894                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2895                 } else {
2896                         hw_stats->pxonrxc[i] +=
2897                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2898                         hw_stats->pxoffrxc[i] +=
2899                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2900                         hw_stats->pxon2offc[i] +=
2901                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2902                 }
2903                 hw_stats->pxontxc[i] +=
2904                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2905                 hw_stats->pxofftxc[i] +=
2906                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2907         }
2908         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2909                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2910                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2911                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2912
2913                 delta_gprc += delta_qprc;
2914
2915                 hw_stats->qprc[i] += delta_qprc;
2916                 hw_stats->qptc[i] += delta_qptc;
2917
2918                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2919                 hw_stats->qbrc[i] +=
2920                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2921                 if (crc_strip == 0)
2922                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2923
2924                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2925                 hw_stats->qbtc[i] +=
2926                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2927
2928                 hw_stats->qprdc[i] += delta_qprdc;
2929                 *total_qprdc += hw_stats->qprdc[i];
2930
2931                 *total_qprc += hw_stats->qprc[i];
2932                 *total_qbrc += hw_stats->qbrc[i];
2933         }
2934         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2935         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2936         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2937
2938         /*
2939          * An errata states that gprc actually counts good + missed packets:
2940          * Workaround to set gprc to summated queue packet receives
2941          */
2942         hw_stats->gprc = *total_qprc;
2943
2944         if (hw->mac.type != ixgbe_mac_82598EB) {
2945                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2946                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2947                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2948                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2949                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2950                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2951                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2952                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2953         } else {
2954                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2955                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2956                 /* 82598 only has a counter in the high register */
2957                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2958                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2959                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2960         }
2961         uint64_t old_tpr = hw_stats->tpr;
2962
2963         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2964         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2965
2966         if (crc_strip == 0)
2967                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2968
2969         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2970         hw_stats->gptc += delta_gptc;
2971         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2972         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2973
2974         /*
2975          * Workaround: mprc hardware is incorrectly counting
2976          * broadcasts, so for now we subtract those.
2977          */
2978         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2979         hw_stats->bprc += bprc;
2980         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2981         if (hw->mac.type == ixgbe_mac_82598EB)
2982                 hw_stats->mprc -= bprc;
2983
2984         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2985         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2986         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2987         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2988         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2989         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2990
2991         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2992         hw_stats->lxontxc += lxon;
2993         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2994         hw_stats->lxofftxc += lxoff;
2995         total = lxon + lxoff;
2996
2997         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2998         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2999         hw_stats->gptc -= total;
3000         hw_stats->mptc -= total;
3001         hw_stats->ptc64 -= total;
3002         hw_stats->gotc -= total * ETHER_MIN_LEN;
3003
3004         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3005         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3006         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3007         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3008         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3009         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3010         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3011         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3012         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3013         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3014         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3015         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3016         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3017         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3018         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3019         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3020         /* Only read FCOE on 82599 */
3021         if (hw->mac.type != ixgbe_mac_82598EB) {
3022                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3023                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3024                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3025                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3026                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3027         }
3028
3029         /* Flow Director Stats registers */
3030         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3031         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3032
3033         /* MACsec Stats registers */
3034         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3035         macsec_stats->out_pkts_encrypted +=
3036                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3037         macsec_stats->out_pkts_protected +=
3038                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3039         macsec_stats->out_octets_encrypted +=
3040                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3041         macsec_stats->out_octets_protected +=
3042                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3043         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3044         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3045         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3046         macsec_stats->in_pkts_unknownsci +=
3047                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3048         macsec_stats->in_octets_decrypted +=
3049                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3050         macsec_stats->in_octets_validated +=
3051                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3052         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3053         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3054         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3055         for (i = 0; i < 2; i++) {
3056                 macsec_stats->in_pkts_ok +=
3057                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3058                 macsec_stats->in_pkts_invalid +=
3059                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3060                 macsec_stats->in_pkts_notvalid +=
3061                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3062         }
3063         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3064         macsec_stats->in_pkts_notusingsa +=
3065                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3066 }
3067
3068 /*
3069  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3070  */
3071 static int
3072 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3073 {
3074         struct ixgbe_hw *hw =
3075                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3076         struct ixgbe_hw_stats *hw_stats =
3077                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3078         struct ixgbe_macsec_stats *macsec_stats =
3079                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3080                                 dev->data->dev_private);
3081         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3082         unsigned i;
3083
3084         total_missed_rx = 0;
3085         total_qbrc = 0;
3086         total_qprc = 0;
3087         total_qprdc = 0;
3088
3089         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3090                         &total_qbrc, &total_qprc, &total_qprdc);
3091
3092         if (stats == NULL)
3093                 return -EINVAL;
3094
3095         /* Fill out the rte_eth_stats statistics structure */
3096         stats->ipackets = total_qprc;
3097         stats->ibytes = total_qbrc;
3098         stats->opackets = hw_stats->gptc;
3099         stats->obytes = hw_stats->gotc;
3100
3101         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3102                 stats->q_ipackets[i] = hw_stats->qprc[i];
3103                 stats->q_opackets[i] = hw_stats->qptc[i];
3104                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3105                 stats->q_obytes[i] = hw_stats->qbtc[i];
3106                 stats->q_errors[i] = hw_stats->qprdc[i];
3107         }
3108
3109         /* Rx Errors */
3110         stats->imissed  = total_missed_rx;
3111         stats->ierrors  = hw_stats->crcerrs +
3112                           hw_stats->mspdc +
3113                           hw_stats->rlec +
3114                           hw_stats->ruc +
3115                           hw_stats->roc +
3116                           hw_stats->illerrc +
3117                           hw_stats->errbc +
3118                           hw_stats->rfc +
3119                           hw_stats->fccrc +
3120                           hw_stats->fclast;
3121
3122         /* Tx Errors */
3123         stats->oerrors  = 0;
3124         return 0;
3125 }
3126
3127 static void
3128 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3129 {
3130         struct ixgbe_hw_stats *stats =
3131                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3132
3133         /* HW registers are cleared on read */
3134         ixgbe_dev_stats_get(dev, NULL);
3135
3136         /* Reset software totals */
3137         memset(stats, 0, sizeof(*stats));
3138 }
3139
3140 /* This function calculates the number of xstats based on the current config */
3141 static unsigned
3142 ixgbe_xstats_calc_num(void) {
3143         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3144                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3145                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3146 }
3147
3148 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3149         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3150 {
3151         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3152         unsigned stat, i, count;
3153
3154         if (xstats_names != NULL) {
3155                 count = 0;
3156
3157                 /* Note: limit >= cnt_stats checked upstream
3158                  * in rte_eth_xstats_names()
3159                  */
3160
3161                 /* Extended stats from ixgbe_hw_stats */
3162                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3163                         snprintf(xstats_names[count].name,
3164                                 sizeof(xstats_names[count].name),
3165                                 "%s",
3166                                 rte_ixgbe_stats_strings[i].name);
3167                         count++;
3168                 }
3169
3170                 /* MACsec Stats */
3171                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3172                         snprintf(xstats_names[count].name,
3173                                 sizeof(xstats_names[count].name),
3174                                 "%s",
3175                                 rte_ixgbe_macsec_strings[i].name);
3176                         count++;
3177                 }
3178
3179                 /* RX Priority Stats */
3180                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3181                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3182                                 snprintf(xstats_names[count].name,
3183                                         sizeof(xstats_names[count].name),
3184                                         "rx_priority%u_%s", i,
3185                                         rte_ixgbe_rxq_strings[stat].name);
3186                                 count++;
3187                         }
3188                 }
3189
3190                 /* TX Priority Stats */
3191                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3192                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3193                                 snprintf(xstats_names[count].name,
3194                                         sizeof(xstats_names[count].name),
3195                                         "tx_priority%u_%s", i,
3196                                         rte_ixgbe_txq_strings[stat].name);
3197                                 count++;
3198                         }
3199                 }
3200         }
3201         return cnt_stats;
3202 }
3203
3204 static int ixgbe_dev_xstats_get_names_by_id(
3205         struct rte_eth_dev *dev,
3206         struct rte_eth_xstat_name *xstats_names,
3207         const uint64_t *ids,
3208         unsigned int limit)
3209 {
3210         if (!ids) {
3211                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3212                 unsigned int stat, i, count;
3213
3214                 if (xstats_names != NULL) {
3215                         count = 0;
3216
3217                         /* Note: limit >= cnt_stats checked upstream
3218                          * in rte_eth_xstats_names()
3219                          */
3220
3221                         /* Extended stats from ixgbe_hw_stats */
3222                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3223                                 snprintf(xstats_names[count].name,
3224                                         sizeof(xstats_names[count].name),
3225                                         "%s",
3226                                         rte_ixgbe_stats_strings[i].name);
3227                                 count++;
3228                         }
3229
3230                         /* MACsec Stats */
3231                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3232                                 snprintf(xstats_names[count].name,
3233                                         sizeof(xstats_names[count].name),
3234                                         "%s",
3235                                         rte_ixgbe_macsec_strings[i].name);
3236                                 count++;
3237                         }
3238
3239                         /* RX Priority Stats */
3240                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3241                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3242                                         snprintf(xstats_names[count].name,
3243                                             sizeof(xstats_names[count].name),
3244                                             "rx_priority%u_%s", i,
3245                                             rte_ixgbe_rxq_strings[stat].name);
3246                                         count++;
3247                                 }
3248                         }
3249
3250                         /* TX Priority Stats */
3251                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3252                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3253                                         snprintf(xstats_names[count].name,
3254                                             sizeof(xstats_names[count].name),
3255                                             "tx_priority%u_%s", i,
3256                                             rte_ixgbe_txq_strings[stat].name);
3257                                         count++;
3258                                 }
3259                         }
3260                 }
3261                 return cnt_stats;
3262         }
3263
3264         uint16_t i;
3265         uint16_t size = ixgbe_xstats_calc_num();
3266         struct rte_eth_xstat_name xstats_names_copy[size];
3267
3268         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3269                         size);
3270
3271         for (i = 0; i < limit; i++) {
3272                 if (ids[i] >= size) {
3273                         PMD_INIT_LOG(ERR, "id value isn't valid");
3274                         return -1;
3275                 }
3276                 strcpy(xstats_names[i].name,
3277                                 xstats_names_copy[ids[i]].name);
3278         }
3279         return limit;
3280 }
3281
3282 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3283         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3284 {
3285         unsigned i;
3286
3287         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3288                 return -ENOMEM;
3289
3290         if (xstats_names != NULL)
3291                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3292                         snprintf(xstats_names[i].name,
3293                                 sizeof(xstats_names[i].name),
3294                                 "%s", rte_ixgbevf_stats_strings[i].name);
3295         return IXGBEVF_NB_XSTATS;
3296 }
3297
3298 static int
3299 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3300                                          unsigned n)
3301 {
3302         struct ixgbe_hw *hw =
3303                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3304         struct ixgbe_hw_stats *hw_stats =
3305                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3306         struct ixgbe_macsec_stats *macsec_stats =
3307                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3308                                 dev->data->dev_private);
3309         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3310         unsigned i, stat, count = 0;
3311
3312         count = ixgbe_xstats_calc_num();
3313
3314         if (n < count)
3315                 return count;
3316
3317         total_missed_rx = 0;
3318         total_qbrc = 0;
3319         total_qprc = 0;
3320         total_qprdc = 0;
3321
3322         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3323                         &total_qbrc, &total_qprc, &total_qprdc);
3324
3325         /* If this is a reset xstats is NULL, and we have cleared the
3326          * registers by reading them.
3327          */
3328         if (!xstats)
3329                 return 0;
3330
3331         /* Extended stats from ixgbe_hw_stats */
3332         count = 0;
3333         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3334                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3335                                 rte_ixgbe_stats_strings[i].offset);
3336                 xstats[count].id = count;
3337                 count++;
3338         }
3339
3340         /* MACsec Stats */
3341         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3342                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3343                                 rte_ixgbe_macsec_strings[i].offset);
3344                 xstats[count].id = count;
3345                 count++;
3346         }
3347
3348         /* RX Priority Stats */
3349         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3350                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3351                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3352                                         rte_ixgbe_rxq_strings[stat].offset +
3353                                         (sizeof(uint64_t) * i));
3354                         xstats[count].id = count;
3355                         count++;
3356                 }
3357         }
3358
3359         /* TX Priority Stats */
3360         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3361                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3362                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3363                                         rte_ixgbe_txq_strings[stat].offset +
3364                                         (sizeof(uint64_t) * i));
3365                         xstats[count].id = count;
3366                         count++;
3367                 }
3368         }
3369         return count;
3370 }
3371
3372 static int
3373 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3374                 uint64_t *values, unsigned int n)
3375 {
3376         if (!ids) {
3377                 struct ixgbe_hw *hw =
3378                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3379                 struct ixgbe_hw_stats *hw_stats =
3380                                 IXGBE_DEV_PRIVATE_TO_STATS(
3381                                                 dev->data->dev_private);
3382                 struct ixgbe_macsec_stats *macsec_stats =
3383                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3384                                         dev->data->dev_private);
3385                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3386                 unsigned int i, stat, count = 0;
3387
3388                 count = ixgbe_xstats_calc_num();
3389
3390                 if (!ids && n < count)
3391                         return count;
3392
3393                 total_missed_rx = 0;
3394                 total_qbrc = 0;
3395                 total_qprc = 0;
3396                 total_qprdc = 0;
3397
3398                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3399                                 &total_missed_rx, &total_qbrc, &total_qprc,
3400                                 &total_qprdc);
3401
3402                 /* If this is a reset xstats is NULL, and we have cleared the
3403                  * registers by reading them.
3404                  */
3405                 if (!ids && !values)
3406                         return 0;
3407
3408                 /* Extended stats from ixgbe_hw_stats */
3409                 count = 0;
3410                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3411                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3412                                         rte_ixgbe_stats_strings[i].offset);
3413                         count++;
3414                 }
3415
3416                 /* MACsec Stats */
3417                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3418                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3419                                         rte_ixgbe_macsec_strings[i].offset);
3420                         count++;
3421                 }
3422
3423                 /* RX Priority Stats */
3424                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3425                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3426                                 values[count] =
3427                                         *(uint64_t *)(((char *)hw_stats) +
3428                                         rte_ixgbe_rxq_strings[stat].offset +
3429                                         (sizeof(uint64_t) * i));
3430                                 count++;
3431                         }
3432                 }
3433
3434                 /* TX Priority Stats */
3435                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3436                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3437                                 values[count] =
3438                                         *(uint64_t *)(((char *)hw_stats) +
3439                                         rte_ixgbe_txq_strings[stat].offset +
3440                                         (sizeof(uint64_t) * i));
3441                                 count++;
3442                         }
3443                 }
3444                 return count;
3445         }
3446
3447         uint16_t i;
3448         uint16_t size = ixgbe_xstats_calc_num();
3449         uint64_t values_copy[size];
3450
3451         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3452
3453         for (i = 0; i < n; i++) {
3454                 if (ids[i] >= size) {
3455                         PMD_INIT_LOG(ERR, "id value isn't valid");
3456                         return -1;
3457                 }
3458                 values[i] = values_copy[ids[i]];
3459         }
3460         return n;
3461 }
3462
3463 static void
3464 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3465 {
3466         struct ixgbe_hw_stats *stats =
3467                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3468         struct ixgbe_macsec_stats *macsec_stats =
3469                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3470                                 dev->data->dev_private);
3471
3472         unsigned count = ixgbe_xstats_calc_num();
3473
3474         /* HW registers are cleared on read */
3475         ixgbe_dev_xstats_get(dev, NULL, count);
3476
3477         /* Reset software totals */
3478         memset(stats, 0, sizeof(*stats));
3479         memset(macsec_stats, 0, sizeof(*macsec_stats));
3480 }
3481
3482 static void
3483 ixgbevf_update_stats(struct rte_eth_dev *dev)
3484 {
3485         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3486         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3487                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3488
3489         /* Good Rx packet, include VF loopback */
3490         UPDATE_VF_STAT(IXGBE_VFGPRC,
3491             hw_stats->last_vfgprc, hw_stats->vfgprc);
3492
3493         /* Good Rx octets, include VF loopback */
3494         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3495             hw_stats->last_vfgorc, hw_stats->vfgorc);
3496
3497         /* Good Tx packet, include VF loopback */
3498         UPDATE_VF_STAT(IXGBE_VFGPTC,
3499             hw_stats->last_vfgptc, hw_stats->vfgptc);
3500
3501         /* Good Tx octets, include VF loopback */
3502         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3503             hw_stats->last_vfgotc, hw_stats->vfgotc);
3504
3505         /* Rx Multicst Packet */
3506         UPDATE_VF_STAT(IXGBE_VFMPRC,
3507             hw_stats->last_vfmprc, hw_stats->vfmprc);
3508 }
3509
3510 static int
3511 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3512                        unsigned n)
3513 {
3514         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3515                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3516         unsigned i;
3517
3518         if (n < IXGBEVF_NB_XSTATS)
3519                 return IXGBEVF_NB_XSTATS;
3520
3521         ixgbevf_update_stats(dev);
3522
3523         if (!xstats)
3524                 return 0;
3525
3526         /* Extended stats */
3527         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3528                 xstats[i].id = i;
3529                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3530                         rte_ixgbevf_stats_strings[i].offset);
3531         }
3532
3533         return IXGBEVF_NB_XSTATS;
3534 }
3535
3536 static int
3537 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3538 {
3539         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3540                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3541
3542         ixgbevf_update_stats(dev);
3543
3544         if (stats == NULL)
3545                 return -EINVAL;
3546
3547         stats->ipackets = hw_stats->vfgprc;
3548         stats->ibytes = hw_stats->vfgorc;
3549         stats->opackets = hw_stats->vfgptc;
3550         stats->obytes = hw_stats->vfgotc;
3551         return 0;
3552 }
3553
3554 static void
3555 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3556 {
3557         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3558                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3559
3560         /* Sync HW register to the last stats */
3561         ixgbevf_dev_stats_get(dev, NULL);
3562
3563         /* reset HW current stats*/
3564         hw_stats->vfgprc = 0;
3565         hw_stats->vfgorc = 0;
3566         hw_stats->vfgptc = 0;
3567         hw_stats->vfgotc = 0;
3568 }
3569
3570 static int
3571 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3572 {
3573         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3574         u16 eeprom_verh, eeprom_verl;
3575         u32 etrack_id;
3576         int ret;
3577
3578         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3579         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3580
3581         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3582         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3583
3584         ret += 1; /* add the size of '\0' */
3585         if (fw_size < (u32)ret)
3586                 return ret;
3587         else
3588                 return 0;
3589 }
3590
3591 static void
3592 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3593 {
3594         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3595         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3596         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3597
3598         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3599         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3600         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3601                 /*
3602                  * When DCB/VT is off, maximum number of queues changes,
3603                  * except for 82598EB, which remains constant.
3604                  */
3605                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3606                                 hw->mac.type != ixgbe_mac_82598EB)
3607                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3608         }
3609         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3610         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3611         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3612         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3613         dev_info->max_vfs = pci_dev->max_vfs;
3614         if (hw->mac.type == ixgbe_mac_82598EB)
3615                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3616         else
3617                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3618         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3619         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3620         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3621                                      dev_info->rx_queue_offload_capa);
3622         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3623         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3624
3625         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3626                 .rx_thresh = {
3627                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3628                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3629                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3630                 },
3631                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3632                 .rx_drop_en = 0,
3633                 .offloads = 0,
3634         };
3635
3636         dev_info->default_txconf = (struct rte_eth_txconf) {
3637                 .tx_thresh = {
3638                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3639                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3640                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3641                 },
3642                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3643                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3644                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3645                              ETH_TXQ_FLAGS_NOOFFLOADS |
3646                              ETH_TXQ_FLAGS_IGNORE,
3647                 .offloads = 0,
3648         };
3649
3650         dev_info->rx_desc_lim = rx_desc_lim;
3651         dev_info->tx_desc_lim = tx_desc_lim;
3652
3653         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3654         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3655         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3656
3657         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3658         if (hw->mac.type == ixgbe_mac_X540 ||
3659             hw->mac.type == ixgbe_mac_X540_vf ||
3660             hw->mac.type == ixgbe_mac_X550 ||
3661             hw->mac.type == ixgbe_mac_X550_vf) {
3662                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3663         }
3664         if (hw->mac.type == ixgbe_mac_X550) {
3665                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3666                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3667         }
3668 }
3669
3670 static const uint32_t *
3671 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3672 {
3673         static const uint32_t ptypes[] = {
3674                 /* For non-vec functions,
3675                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3676                  * for vec functions,
3677                  * refers to _recv_raw_pkts_vec().
3678                  */
3679                 RTE_PTYPE_L2_ETHER,
3680                 RTE_PTYPE_L3_IPV4,
3681                 RTE_PTYPE_L3_IPV4_EXT,
3682                 RTE_PTYPE_L3_IPV6,
3683                 RTE_PTYPE_L3_IPV6_EXT,
3684                 RTE_PTYPE_L4_SCTP,
3685                 RTE_PTYPE_L4_TCP,
3686                 RTE_PTYPE_L4_UDP,
3687                 RTE_PTYPE_TUNNEL_IP,
3688                 RTE_PTYPE_INNER_L3_IPV6,
3689                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3690                 RTE_PTYPE_INNER_L4_TCP,
3691                 RTE_PTYPE_INNER_L4_UDP,
3692                 RTE_PTYPE_UNKNOWN
3693         };
3694
3695         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3696             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3697             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3698             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3699                 return ptypes;
3700
3701 #if defined(RTE_ARCH_X86)
3702         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3703             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3704                 return ptypes;
3705 #endif
3706         return NULL;
3707 }
3708
3709 static void
3710 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3711                      struct rte_eth_dev_info *dev_info)
3712 {
3713         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3714         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3715
3716         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3717         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3718         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3719         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3720         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3721         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3722         dev_info->max_vfs = pci_dev->max_vfs;
3723         if (hw->mac.type == ixgbe_mac_82598EB)
3724                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3725         else
3726                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3727         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3728         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3729                                      dev_info->rx_queue_offload_capa);
3730         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3731         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3732
3733         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3734                 .rx_thresh = {
3735                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3736                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3737                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3738                 },
3739                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3740                 .rx_drop_en = 0,
3741                 .offloads = 0,
3742         };
3743
3744         dev_info->default_txconf = (struct rte_eth_txconf) {
3745                 .tx_thresh = {
3746                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3747                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3748                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3749                 },
3750                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3751                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3752                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3753                              ETH_TXQ_FLAGS_NOOFFLOADS |
3754                              ETH_TXQ_FLAGS_IGNORE,
3755                 .offloads = 0,
3756         };
3757
3758         dev_info->rx_desc_lim = rx_desc_lim;
3759         dev_info->tx_desc_lim = tx_desc_lim;
3760 }
3761
3762 static int
3763 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3764                    int *link_up, int wait_to_complete)
3765 {
3766         /**
3767          * for a quick link status checking, wait_to_compelet == 0,
3768          * skip PF link status checking
3769          */
3770         bool no_pflink_check = wait_to_complete == 0;
3771         struct ixgbe_mbx_info *mbx = &hw->mbx;
3772         struct ixgbe_mac_info *mac = &hw->mac;
3773         uint32_t links_reg, in_msg;
3774         int ret_val = 0;
3775
3776         /* If we were hit with a reset drop the link */
3777         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3778                 mac->get_link_status = true;
3779
3780         if (!mac->get_link_status)
3781                 goto out;
3782
3783         /* if link status is down no point in checking to see if pf is up */
3784         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3785         if (!(links_reg & IXGBE_LINKS_UP))
3786                 goto out;
3787
3788         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3789          * before the link status is correct
3790          */
3791         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3792                 int i;
3793
3794                 for (i = 0; i < 5; i++) {
3795                         rte_delay_us(100);
3796                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3797
3798                         if (!(links_reg & IXGBE_LINKS_UP))
3799                                 goto out;
3800                 }
3801         }
3802
3803         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3804         case IXGBE_LINKS_SPEED_10G_82599:
3805                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3806                 if (hw->mac.type >= ixgbe_mac_X550) {
3807                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3808                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3809                 }
3810                 break;
3811         case IXGBE_LINKS_SPEED_1G_82599:
3812                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3813                 break;
3814         case IXGBE_LINKS_SPEED_100_82599:
3815                 *speed = IXGBE_LINK_SPEED_100_FULL;
3816                 if (hw->mac.type == ixgbe_mac_X550) {
3817                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3818                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3819                 }
3820                 break;
3821         case IXGBE_LINKS_SPEED_10_X550EM_A:
3822                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3823                 /* Since Reserved in older MAC's */
3824                 if (hw->mac.type >= ixgbe_mac_X550)
3825                         *speed = IXGBE_LINK_SPEED_10_FULL;
3826                 break;
3827         default:
3828                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3829         }
3830
3831         if (no_pflink_check) {
3832                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3833                         mac->get_link_status = true;
3834                 else
3835                         mac->get_link_status = false;
3836
3837                 goto out;
3838         }
3839         /* if the read failed it could just be a mailbox collision, best wait
3840          * until we are called again and don't report an error
3841          */
3842         if (mbx->ops.read(hw, &in_msg, 1, 0))
3843                 goto out;
3844
3845         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3846                 /* msg is not CTS and is NACK we must have lost CTS status */
3847                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3848                         ret_val = -1;
3849                 goto out;
3850         }
3851
3852         /* the pf is talking, if we timed out in the past we reinit */
3853         if (!mbx->timeout) {
3854                 ret_val = -1;
3855                 goto out;
3856         }
3857
3858         /* if we passed all the tests above then the link is up and we no
3859          * longer need to check for link
3860          */
3861         mac->get_link_status = false;
3862
3863 out:
3864         *link_up = !mac->get_link_status;
3865         return ret_val;
3866 }
3867
3868 /* return 0 means link status changed, -1 means not changed */
3869 static int
3870 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3871                             int wait_to_complete, int vf)
3872 {
3873         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3874         struct rte_eth_link link;
3875         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3876         struct ixgbe_interrupt *intr =
3877                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3878         int link_up;
3879         int diag;
3880         u32 speed = 0;
3881         int wait = 1;
3882         bool autoneg = false;
3883
3884         memset(&link, 0, sizeof(link));
3885         link.link_status = ETH_LINK_DOWN;
3886         link.link_speed = 0;
3887         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3888         link.link_autoneg = ETH_LINK_AUTONEG;
3889
3890         hw->mac.get_link_status = true;
3891
3892         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3893                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3894                 speed = hw->phy.autoneg_advertised;
3895                 if (!speed)
3896                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3897                 ixgbe_setup_link(hw, speed, true);
3898         }
3899
3900         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3901         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3902                 wait = 0;
3903
3904         if (vf)
3905                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3906         else
3907                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3908
3909         if (diag != 0) {
3910                 link.link_speed = ETH_SPEED_NUM_100M;
3911                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3912                 return rte_eth_linkstatus_set(dev, &link);
3913         }
3914
3915         if (link_up == 0) {
3916                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3917                 return rte_eth_linkstatus_set(dev, &link);
3918         }
3919
3920         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3921         link.link_status = ETH_LINK_UP;
3922         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3923
3924         switch (link_speed) {
3925         default:
3926         case IXGBE_LINK_SPEED_UNKNOWN:
3927                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3928                 link.link_speed = ETH_SPEED_NUM_100M;
3929                 break;
3930
3931         case IXGBE_LINK_SPEED_100_FULL:
3932                 link.link_speed = ETH_SPEED_NUM_100M;
3933                 break;
3934
3935         case IXGBE_LINK_SPEED_1GB_FULL:
3936                 link.link_speed = ETH_SPEED_NUM_1G;
3937                 break;
3938
3939         case IXGBE_LINK_SPEED_2_5GB_FULL:
3940                 link.link_speed = ETH_SPEED_NUM_2_5G;
3941                 break;
3942
3943         case IXGBE_LINK_SPEED_5GB_FULL:
3944                 link.link_speed = ETH_SPEED_NUM_5G;
3945                 break;
3946
3947         case IXGBE_LINK_SPEED_10GB_FULL:
3948                 link.link_speed = ETH_SPEED_NUM_10G;
3949                 break;
3950         }
3951
3952         return rte_eth_linkstatus_set(dev, &link);
3953 }
3954
3955 static int
3956 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3957 {
3958         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
3959 }
3960
3961 static int
3962 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3963 {
3964         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
3965 }
3966
3967 static void
3968 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3969 {
3970         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3971         uint32_t fctrl;
3972
3973         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3974         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3975         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3976 }
3977
3978 static void
3979 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3980 {
3981         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3982         uint32_t fctrl;
3983
3984         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3985         fctrl &= (~IXGBE_FCTRL_UPE);
3986         if (dev->data->all_multicast == 1)
3987                 fctrl |= IXGBE_FCTRL_MPE;
3988         else
3989                 fctrl &= (~IXGBE_FCTRL_MPE);
3990         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3991 }
3992
3993 static void
3994 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3995 {
3996         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3997         uint32_t fctrl;
3998
3999         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4000         fctrl |= IXGBE_FCTRL_MPE;
4001         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4002 }
4003
4004 static void
4005 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4006 {
4007         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4008         uint32_t fctrl;
4009
4010         if (dev->data->promiscuous == 1)
4011                 return; /* must remain in all_multicast mode */
4012
4013         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4014         fctrl &= (~IXGBE_FCTRL_MPE);
4015         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4016 }
4017
4018 /**
4019  * It clears the interrupt causes and enables the interrupt.
4020  * It will be called once only during nic initialized.
4021  *
4022  * @param dev
4023  *  Pointer to struct rte_eth_dev.
4024  * @param on
4025  *  Enable or Disable.
4026  *
4027  * @return
4028  *  - On success, zero.
4029  *  - On failure, a negative value.
4030  */
4031 static int
4032 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4033 {
4034         struct ixgbe_interrupt *intr =
4035                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4036
4037         ixgbe_dev_link_status_print(dev);
4038         if (on)
4039                 intr->mask |= IXGBE_EICR_LSC;
4040         else
4041                 intr->mask &= ~IXGBE_EICR_LSC;
4042
4043         return 0;
4044 }
4045
4046 /**
4047  * It clears the interrupt causes and enables the interrupt.
4048  * It will be called once only during nic initialized.
4049  *
4050  * @param dev
4051  *  Pointer to struct rte_eth_dev.
4052  *
4053  * @return
4054  *  - On success, zero.
4055  *  - On failure, a negative value.
4056  */
4057 static int
4058 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4059 {
4060         struct ixgbe_interrupt *intr =
4061                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4062
4063         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4064
4065         return 0;
4066 }
4067
4068 /**
4069  * It clears the interrupt causes and enables the interrupt.
4070  * It will be called once only during nic initialized.
4071  *
4072  * @param dev
4073  *  Pointer to struct rte_eth_dev.
4074  *
4075  * @return
4076  *  - On success, zero.
4077  *  - On failure, a negative value.
4078  */
4079 static int
4080 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4081 {
4082         struct ixgbe_interrupt *intr =
4083                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4084
4085         intr->mask |= IXGBE_EICR_LINKSEC;
4086
4087         return 0;
4088 }
4089
4090 /*
4091  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4092  *
4093  * @param dev
4094  *  Pointer to struct rte_eth_dev.
4095  *
4096  * @return
4097  *  - On success, zero.
4098  *  - On failure, a negative value.
4099  */
4100 static int
4101 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4102 {
4103         uint32_t eicr;
4104         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4105         struct ixgbe_interrupt *intr =
4106                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4107
4108         /* clear all cause mask */
4109         ixgbe_disable_intr(hw);
4110
4111         /* read-on-clear nic registers here */
4112         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4113         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4114
4115         intr->flags = 0;
4116
4117         /* set flag for async link update */
4118         if (eicr & IXGBE_EICR_LSC)
4119                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4120
4121         if (eicr & IXGBE_EICR_MAILBOX)
4122                 intr->flags |= IXGBE_FLAG_MAILBOX;
4123
4124         if (eicr & IXGBE_EICR_LINKSEC)
4125                 intr->flags |= IXGBE_FLAG_MACSEC;
4126
4127         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4128             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4129             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4130                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4131
4132         return 0;
4133 }
4134
4135 /**
4136  * It gets and then prints the link status.
4137  *
4138  * @param dev
4139  *  Pointer to struct rte_eth_dev.
4140  *
4141  * @return
4142  *  - On success, zero.
4143  *  - On failure, a negative value.
4144  */
4145 static void
4146 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4147 {
4148         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4149         struct rte_eth_link link;
4150
4151         rte_eth_linkstatus_get(dev, &link);
4152
4153         if (link.link_status) {
4154                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4155                                         (int)(dev->data->port_id),
4156                                         (unsigned)link.link_speed,
4157                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4158                                         "full-duplex" : "half-duplex");
4159         } else {
4160                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4161                                 (int)(dev->data->port_id));
4162         }
4163         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4164                                 pci_dev->addr.domain,
4165                                 pci_dev->addr.bus,
4166                                 pci_dev->addr.devid,
4167                                 pci_dev->addr.function);
4168 }
4169
4170 /*
4171  * It executes link_update after knowing an interrupt occurred.
4172  *
4173  * @param dev
4174  *  Pointer to struct rte_eth_dev.
4175  *
4176  * @return
4177  *  - On success, zero.
4178  *  - On failure, a negative value.
4179  */
4180 static int
4181 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4182                            struct rte_intr_handle *intr_handle)
4183 {
4184         struct ixgbe_interrupt *intr =
4185                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4186         int64_t timeout;
4187         struct ixgbe_hw *hw =
4188                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4189
4190         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4191
4192         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4193                 ixgbe_pf_mbx_process(dev);
4194                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4195         }
4196
4197         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4198                 ixgbe_handle_lasi(hw);
4199                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4200         }
4201
4202         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4203                 struct rte_eth_link link;
4204
4205                 /* get the link status before link update, for predicting later */
4206                 rte_eth_linkstatus_get(dev, &link);
4207
4208                 ixgbe_dev_link_update(dev, 0);
4209
4210                 /* likely to up */
4211                 if (!link.link_status)
4212                         /* handle it 1 sec later, wait it being stable */
4213                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4214                 /* likely to down */
4215                 else
4216                         /* handle it 4 sec later, wait it being stable */
4217                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4218
4219                 ixgbe_dev_link_status_print(dev);
4220                 if (rte_eal_alarm_set(timeout * 1000,
4221                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4222                         PMD_DRV_LOG(ERR, "Error setting alarm");
4223                 else {
4224                         /* remember original mask */
4225                         intr->mask_original = intr->mask;
4226                         /* only disable lsc interrupt */
4227                         intr->mask &= ~IXGBE_EIMS_LSC;
4228                 }
4229         }
4230
4231         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4232         ixgbe_enable_intr(dev);
4233         rte_intr_enable(intr_handle);
4234
4235         return 0;
4236 }
4237
4238 /**
4239  * Interrupt handler which shall be registered for alarm callback for delayed
4240  * handling specific interrupt to wait for the stable nic state. As the
4241  * NIC interrupt state is not stable for ixgbe after link is just down,
4242  * it needs to wait 4 seconds to get the stable status.
4243  *
4244  * @param handle
4245  *  Pointer to interrupt handle.
4246  * @param param
4247  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4248  *
4249  * @return
4250  *  void
4251  */
4252 static void
4253 ixgbe_dev_interrupt_delayed_handler(void *param)
4254 {
4255         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4256         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4257         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4258         struct ixgbe_interrupt *intr =
4259                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4260         struct ixgbe_hw *hw =
4261                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4262         uint32_t eicr;
4263
4264         ixgbe_disable_intr(hw);
4265
4266         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4267         if (eicr & IXGBE_EICR_MAILBOX)
4268                 ixgbe_pf_mbx_process(dev);
4269
4270         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4271                 ixgbe_handle_lasi(hw);
4272                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4273         }
4274
4275         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4276                 ixgbe_dev_link_update(dev, 0);
4277                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4278                 ixgbe_dev_link_status_print(dev);
4279                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4280                                               NULL);
4281         }
4282
4283         if (intr->flags & IXGBE_FLAG_MACSEC) {
4284                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4285                                               NULL);
4286                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4287         }
4288
4289         /* restore original mask */
4290         intr->mask = intr->mask_original;
4291         intr->mask_original = 0;
4292
4293         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4294         ixgbe_enable_intr(dev);
4295         rte_intr_enable(intr_handle);
4296 }
4297
4298 /**
4299  * Interrupt handler triggered by NIC  for handling
4300  * specific interrupt.
4301  *
4302  * @param handle
4303  *  Pointer to interrupt handle.
4304  * @param param
4305  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4306  *
4307  * @return
4308  *  void
4309  */
4310 static void
4311 ixgbe_dev_interrupt_handler(void *param)
4312 {
4313         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4314
4315         ixgbe_dev_interrupt_get_status(dev);
4316         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4317 }
4318
4319 static int
4320 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4321 {
4322         struct ixgbe_hw *hw;
4323
4324         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4325         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4326 }
4327
4328 static int
4329 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4330 {
4331         struct ixgbe_hw *hw;
4332
4333         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4334         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4335 }
4336
4337 static int
4338 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4339 {
4340         struct ixgbe_hw *hw;
4341         uint32_t mflcn_reg;
4342         uint32_t fccfg_reg;
4343         int rx_pause;
4344         int tx_pause;
4345
4346         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4347
4348         fc_conf->pause_time = hw->fc.pause_time;
4349         fc_conf->high_water = hw->fc.high_water[0];
4350         fc_conf->low_water = hw->fc.low_water[0];
4351         fc_conf->send_xon = hw->fc.send_xon;
4352         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4353
4354         /*
4355          * Return rx_pause status according to actual setting of
4356          * MFLCN register.
4357          */
4358         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4359         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4360                 rx_pause = 1;
4361         else
4362                 rx_pause = 0;
4363
4364         /*
4365          * Return tx_pause status according to actual setting of
4366          * FCCFG register.
4367          */
4368         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4369         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4370                 tx_pause = 1;
4371         else
4372                 tx_pause = 0;
4373
4374         if (rx_pause && tx_pause)
4375                 fc_conf->mode = RTE_FC_FULL;
4376         else if (rx_pause)
4377                 fc_conf->mode = RTE_FC_RX_PAUSE;
4378         else if (tx_pause)
4379                 fc_conf->mode = RTE_FC_TX_PAUSE;
4380         else
4381                 fc_conf->mode = RTE_FC_NONE;
4382
4383         return 0;
4384 }
4385
4386 static int
4387 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4388 {
4389         struct ixgbe_hw *hw;
4390         int err;
4391         uint32_t rx_buf_size;
4392         uint32_t max_high_water;
4393         uint32_t mflcn;
4394         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4395                 ixgbe_fc_none,
4396                 ixgbe_fc_rx_pause,
4397                 ixgbe_fc_tx_pause,
4398                 ixgbe_fc_full
4399         };
4400
4401         PMD_INIT_FUNC_TRACE();
4402
4403         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4404         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4405         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4406
4407         /*
4408          * At least reserve one Ethernet frame for watermark
4409          * high_water/low_water in kilo bytes for ixgbe
4410          */
4411         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4412         if ((fc_conf->high_water > max_high_water) ||
4413                 (fc_conf->high_water < fc_conf->low_water)) {
4414                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4415                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4416                 return -EINVAL;
4417         }
4418
4419         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4420         hw->fc.pause_time     = fc_conf->pause_time;
4421         hw->fc.high_water[0]  = fc_conf->high_water;
4422         hw->fc.low_water[0]   = fc_conf->low_water;
4423         hw->fc.send_xon       = fc_conf->send_xon;
4424         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4425
4426         err = ixgbe_fc_enable(hw);
4427
4428         /* Not negotiated is not an error case */
4429         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4430
4431                 /* check if we want to forward MAC frames - driver doesn't have native
4432                  * capability to do that, so we'll write the registers ourselves */
4433
4434                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4435
4436                 /* set or clear MFLCN.PMCF bit depending on configuration */
4437                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4438                         mflcn |= IXGBE_MFLCN_PMCF;
4439                 else
4440                         mflcn &= ~IXGBE_MFLCN_PMCF;
4441
4442                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4443                 IXGBE_WRITE_FLUSH(hw);
4444
4445                 return 0;
4446         }
4447
4448         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4449         return -EIO;
4450 }
4451
4452 /**
4453  *  ixgbe_pfc_enable_generic - Enable flow control
4454  *  @hw: pointer to hardware structure
4455  *  @tc_num: traffic class number
4456  *  Enable flow control according to the current settings.
4457  */
4458 static int
4459 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4460 {
4461         int ret_val = 0;
4462         uint32_t mflcn_reg, fccfg_reg;
4463         uint32_t reg;
4464         uint32_t fcrtl, fcrth;
4465         uint8_t i;
4466         uint8_t nb_rx_en;
4467
4468         /* Validate the water mark configuration */
4469         if (!hw->fc.pause_time) {
4470                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4471                 goto out;
4472         }
4473
4474         /* Low water mark of zero causes XOFF floods */
4475         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4476                  /* High/Low water can not be 0 */
4477                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4478                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4479                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4480                         goto out;
4481                 }
4482
4483                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4484                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4485                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4486                         goto out;
4487                 }
4488         }
4489         /* Negotiate the fc mode to use */
4490         ixgbe_fc_autoneg(hw);
4491
4492         /* Disable any previous flow control settings */
4493         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4494         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4495
4496         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4497         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4498
4499         switch (hw->fc.current_mode) {
4500         case ixgbe_fc_none:
4501                 /*
4502                  * If the count of enabled RX Priority Flow control >1,
4503                  * and the TX pause can not be disabled
4504                  */
4505                 nb_rx_en = 0;
4506                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4507                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4508                         if (reg & IXGBE_FCRTH_FCEN)
4509                                 nb_rx_en++;
4510                 }
4511                 if (nb_rx_en > 1)
4512                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4513                 break;
4514         case ixgbe_fc_rx_pause:
4515                 /*
4516                  * Rx Flow control is enabled and Tx Flow control is
4517                  * disabled by software override. Since there really
4518                  * isn't a way to advertise that we are capable of RX
4519                  * Pause ONLY, we will advertise that we support both
4520                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4521                  * disable the adapter's ability to send PAUSE frames.
4522                  */
4523                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4524                 /*
4525                  * If the count of enabled RX Priority Flow control >1,
4526                  * and the TX pause can not be disabled
4527                  */
4528                 nb_rx_en = 0;
4529                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4530                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4531                         if (reg & IXGBE_FCRTH_FCEN)
4532                                 nb_rx_en++;
4533                 }
4534                 if (nb_rx_en > 1)
4535                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4536                 break;
4537         case ixgbe_fc_tx_pause:
4538                 /*
4539                  * Tx Flow control is enabled, and Rx Flow control is
4540                  * disabled by software override.
4541                  */
4542                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4543                 break;
4544         case ixgbe_fc_full:
4545                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4546                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4547                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4548                 break;
4549         default:
4550                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4551                 ret_val = IXGBE_ERR_CONFIG;
4552                 goto out;
4553         }
4554
4555         /* Set 802.3x based flow control settings. */
4556         mflcn_reg |= IXGBE_MFLCN_DPF;
4557         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4558         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4559
4560         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4561         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4562                 hw->fc.high_water[tc_num]) {
4563                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4564                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4565                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4566         } else {
4567                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4568                 /*
4569                  * In order to prevent Tx hangs when the internal Tx
4570                  * switch is enabled we must set the high water mark
4571                  * to the maximum FCRTH value.  This allows the Tx
4572                  * switch to function even under heavy Rx workloads.
4573                  */
4574                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4575         }
4576         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4577
4578         /* Configure pause time (2 TCs per register) */
4579         reg = hw->fc.pause_time * 0x00010001;
4580         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4581                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4582
4583         /* Configure flow control refresh threshold value */
4584         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4585
4586 out:
4587         return ret_val;
4588 }
4589
4590 static int
4591 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4592 {
4593         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4594         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4595
4596         if (hw->mac.type != ixgbe_mac_82598EB) {
4597                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4598         }
4599         return ret_val;
4600 }
4601
4602 static int
4603 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4604 {
4605         int err;
4606         uint32_t rx_buf_size;
4607         uint32_t max_high_water;
4608         uint8_t tc_num;
4609         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4610         struct ixgbe_hw *hw =
4611                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4612         struct ixgbe_dcb_config *dcb_config =
4613                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4614
4615         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4616                 ixgbe_fc_none,
4617                 ixgbe_fc_rx_pause,
4618                 ixgbe_fc_tx_pause,
4619                 ixgbe_fc_full
4620         };
4621
4622         PMD_INIT_FUNC_TRACE();
4623
4624         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4625         tc_num = map[pfc_conf->priority];
4626         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4627         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4628         /*
4629          * At least reserve one Ethernet frame for watermark
4630          * high_water/low_water in kilo bytes for ixgbe
4631          */
4632         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4633         if ((pfc_conf->fc.high_water > max_high_water) ||
4634             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4635                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4636                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4637                 return -EINVAL;
4638         }
4639
4640         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4641         hw->fc.pause_time = pfc_conf->fc.pause_time;
4642         hw->fc.send_xon = pfc_conf->fc.send_xon;
4643         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4644         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4645
4646         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4647
4648         /* Not negotiated is not an error case */
4649         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4650                 return 0;
4651
4652         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4653         return -EIO;
4654 }
4655
4656 static int
4657 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4658                           struct rte_eth_rss_reta_entry64 *reta_conf,
4659                           uint16_t reta_size)
4660 {
4661         uint16_t i, sp_reta_size;
4662         uint8_t j, mask;
4663         uint32_t reta, r;
4664         uint16_t idx, shift;
4665         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4666         uint32_t reta_reg;
4667
4668         PMD_INIT_FUNC_TRACE();
4669
4670         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4671                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4672                         "NIC.");
4673                 return -ENOTSUP;
4674         }
4675
4676         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4677         if (reta_size != sp_reta_size) {
4678                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4679                         "(%d) doesn't match the number hardware can supported "
4680                         "(%d)", reta_size, sp_reta_size);
4681                 return -EINVAL;
4682         }
4683
4684         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4685                 idx = i / RTE_RETA_GROUP_SIZE;
4686                 shift = i % RTE_RETA_GROUP_SIZE;
4687                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4688                                                 IXGBE_4_BIT_MASK);
4689                 if (!mask)
4690                         continue;
4691                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4692                 if (mask == IXGBE_4_BIT_MASK)
4693                         r = 0;
4694                 else
4695                         r = IXGBE_READ_REG(hw, reta_reg);
4696                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4697                         if (mask & (0x1 << j))
4698                                 reta |= reta_conf[idx].reta[shift + j] <<
4699                                                         (CHAR_BIT * j);
4700                         else
4701                                 reta |= r & (IXGBE_8_BIT_MASK <<
4702                                                 (CHAR_BIT * j));
4703                 }
4704                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4705         }
4706
4707         return 0;
4708 }
4709
4710 static int
4711 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4712                          struct rte_eth_rss_reta_entry64 *reta_conf,
4713                          uint16_t reta_size)
4714 {
4715         uint16_t i, sp_reta_size;
4716         uint8_t j, mask;
4717         uint32_t reta;
4718         uint16_t idx, shift;
4719         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4720         uint32_t reta_reg;
4721
4722         PMD_INIT_FUNC_TRACE();
4723         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4724         if (reta_size != sp_reta_size) {
4725                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4726                         "(%d) doesn't match the number hardware can supported "
4727                         "(%d)", reta_size, sp_reta_size);
4728                 return -EINVAL;
4729         }
4730
4731         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4732                 idx = i / RTE_RETA_GROUP_SIZE;
4733                 shift = i % RTE_RETA_GROUP_SIZE;
4734                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4735                                                 IXGBE_4_BIT_MASK);
4736                 if (!mask)
4737                         continue;
4738
4739                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4740                 reta = IXGBE_READ_REG(hw, reta_reg);
4741                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4742                         if (mask & (0x1 << j))
4743                                 reta_conf[idx].reta[shift + j] =
4744                                         ((reta >> (CHAR_BIT * j)) &
4745                                                 IXGBE_8_BIT_MASK);
4746                 }
4747         }
4748
4749         return 0;
4750 }
4751
4752 static int
4753 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4754                                 uint32_t index, uint32_t pool)
4755 {
4756         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4757         uint32_t enable_addr = 1;
4758
4759         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4760                              pool, enable_addr);
4761 }
4762
4763 static void
4764 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4765 {
4766         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4767
4768         ixgbe_clear_rar(hw, index);
4769 }
4770
4771 static void
4772 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4773 {
4774         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4775
4776         ixgbe_remove_rar(dev, 0);
4777
4778         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4779 }
4780
4781 static bool
4782 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4783 {
4784         if (strcmp(dev->device->driver->name, drv->driver.name))
4785                 return false;
4786
4787         return true;
4788 }
4789
4790 bool
4791 is_ixgbe_supported(struct rte_eth_dev *dev)
4792 {
4793         return is_device_supported(dev, &rte_ixgbe_pmd);
4794 }
4795
4796 static int
4797 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4798 {
4799         uint32_t hlreg0;
4800         uint32_t maxfrs;
4801         struct ixgbe_hw *hw;
4802         struct rte_eth_dev_info dev_info;
4803         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4804         struct rte_eth_dev_data *dev_data = dev->data;
4805
4806         ixgbe_dev_info_get(dev, &dev_info);
4807
4808         /* check that mtu is within the allowed range */
4809         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4810                 return -EINVAL;
4811
4812         /* If device is started, refuse mtu that requires the support of
4813          * scattered packets when this feature has not been enabled before.
4814          */
4815         if (dev_data->dev_started && !dev_data->scattered_rx &&
4816             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4817              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4818                 PMD_INIT_LOG(ERR, "Stop port first.");
4819                 return -EINVAL;
4820         }
4821
4822         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4823         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4824
4825         /* switch to jumbo mode if needed */
4826         if (frame_size > ETHER_MAX_LEN) {
4827                 dev->data->dev_conf.rxmode.offloads |=
4828                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4829                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4830         } else {
4831                 dev->data->dev_conf.rxmode.offloads &=
4832                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4833                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4834         }
4835         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4836
4837         /* update max frame size */
4838         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4839
4840         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4841         maxfrs &= 0x0000FFFF;
4842         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4843         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4844
4845         return 0;
4846 }
4847
4848 /*
4849  * Virtual Function operations
4850  */
4851 static void
4852 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4853 {
4854         PMD_INIT_FUNC_TRACE();
4855
4856         /* Clear interrupt mask to stop from interrupts being generated */
4857         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4858
4859         IXGBE_WRITE_FLUSH(hw);
4860 }
4861
4862 static void
4863 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4864 {
4865         PMD_INIT_FUNC_TRACE();
4866
4867         /* VF enable interrupt autoclean */
4868         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4869         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4870         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4871
4872         IXGBE_WRITE_FLUSH(hw);
4873 }
4874
4875 static int
4876 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4877 {
4878         struct rte_eth_conf *conf = &dev->data->dev_conf;
4879         struct ixgbe_adapter *adapter =
4880                         (struct ixgbe_adapter *)dev->data->dev_private;
4881         struct rte_eth_dev_info dev_info;
4882         uint64_t rx_offloads;
4883         uint64_t tx_offloads;
4884
4885         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4886                      dev->data->port_id);
4887
4888         ixgbevf_dev_info_get(dev, &dev_info);
4889         rx_offloads = dev->data->dev_conf.rxmode.offloads;
4890         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
4891                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
4892                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4893                             rx_offloads, dev_info.rx_offload_capa);
4894                 return -ENOTSUP;
4895         }
4896         tx_offloads = dev->data->dev_conf.txmode.offloads;
4897         if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
4898                 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
4899                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4900                             tx_offloads, dev_info.tx_offload_capa);
4901                 return -ENOTSUP;
4902         }
4903
4904         /*
4905          * VF has no ability to enable/disable HW CRC
4906          * Keep the persistent behavior the same as Host PF
4907          */
4908 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4909         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
4910                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4911                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
4912         }
4913 #else
4914         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
4915                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4916                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_CRC_STRIP;
4917         }
4918 #endif
4919
4920         /*
4921          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4922          * allocation or vector Rx preconditions we will reset it.
4923          */
4924         adapter->rx_bulk_alloc_allowed = true;
4925         adapter->rx_vec_allowed = true;
4926
4927         return 0;
4928 }
4929
4930 static int
4931 ixgbevf_dev_start(struct rte_eth_dev *dev)
4932 {
4933         struct ixgbe_hw *hw =
4934                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4935         uint32_t intr_vector = 0;
4936         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4937         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4938
4939         int err, mask = 0;
4940
4941         PMD_INIT_FUNC_TRACE();
4942
4943         err = hw->mac.ops.reset_hw(hw);
4944         if (err) {
4945                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
4946                 return err;
4947         }
4948         hw->mac.get_link_status = true;
4949
4950         /* negotiate mailbox API version to use with the PF. */
4951         ixgbevf_negotiate_api(hw);
4952
4953         ixgbevf_dev_tx_init(dev);
4954
4955         /* This can fail when allocating mbufs for descriptor rings */
4956         err = ixgbevf_dev_rx_init(dev);
4957         if (err) {
4958                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4959                 ixgbe_dev_clear_queues(dev);
4960                 return err;
4961         }
4962
4963         /* Set vfta */
4964         ixgbevf_set_vfta_all(dev, 1);
4965
4966         /* Set HW strip */
4967         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4968                 ETH_VLAN_EXTEND_MASK;
4969         err = ixgbevf_vlan_offload_set(dev, mask);
4970         if (err) {
4971                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
4972                 ixgbe_dev_clear_queues(dev);
4973                 return err;
4974         }
4975
4976         ixgbevf_dev_rxtx_start(dev);
4977
4978         ixgbevf_dev_link_update(dev, 0);
4979
4980         /* check and configure queue intr-vector mapping */
4981         if (rte_intr_cap_multiple(intr_handle) &&
4982             dev->data->dev_conf.intr_conf.rxq) {
4983                 /* According to datasheet, only vector 0/1/2 can be used,
4984                  * now only one vector is used for Rx queue
4985                  */
4986                 intr_vector = 1;
4987                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4988                         return -1;
4989         }
4990
4991         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4992                 intr_handle->intr_vec =
4993                         rte_zmalloc("intr_vec",
4994                                     dev->data->nb_rx_queues * sizeof(int), 0);
4995                 if (intr_handle->intr_vec == NULL) {
4996                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4997                                      " intr_vec", dev->data->nb_rx_queues);
4998                         return -ENOMEM;
4999                 }
5000         }
5001         ixgbevf_configure_msix(dev);
5002
5003         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5004          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5005          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5006          * is not cleared, it will fail when following rte_intr_enable( ) tries
5007          * to map Rx queue interrupt to other VFIO vectors.
5008          * So clear uio/vfio intr/evevnfd first to avoid failure.
5009          */
5010         rte_intr_disable(intr_handle);
5011
5012         rte_intr_enable(intr_handle);
5013
5014         /* Re-enable interrupt for VF */
5015         ixgbevf_intr_enable(hw);
5016
5017         return 0;
5018 }
5019
5020 static void
5021 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5022 {
5023         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5024         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5025         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5026
5027         PMD_INIT_FUNC_TRACE();
5028
5029         ixgbevf_intr_disable(hw);
5030
5031         hw->adapter_stopped = 1;
5032         ixgbe_stop_adapter(hw);
5033
5034         /*
5035           * Clear what we set, but we still keep shadow_vfta to
5036           * restore after device starts
5037           */
5038         ixgbevf_set_vfta_all(dev, 0);
5039
5040         /* Clear stored conf */
5041         dev->data->scattered_rx = 0;
5042
5043         ixgbe_dev_clear_queues(dev);
5044
5045         /* Clean datapath event and queue/vec mapping */
5046         rte_intr_efd_disable(intr_handle);
5047         if (intr_handle->intr_vec != NULL) {
5048                 rte_free(intr_handle->intr_vec);
5049                 intr_handle->intr_vec = NULL;
5050         }
5051 }
5052
5053 static void
5054 ixgbevf_dev_close(struct rte_eth_dev *dev)
5055 {
5056         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5057
5058         PMD_INIT_FUNC_TRACE();
5059
5060         ixgbe_reset_hw(hw);
5061
5062         ixgbevf_dev_stop(dev);
5063
5064         ixgbe_dev_free_queues(dev);
5065
5066         /**
5067          * Remove the VF MAC address ro ensure
5068          * that the VF traffic goes to the PF
5069          * after stop, close and detach of the VF
5070          **/
5071         ixgbevf_remove_mac_addr(dev, 0);
5072 }
5073
5074 /*
5075  * Reset VF device
5076  */
5077 static int
5078 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5079 {
5080         int ret;
5081
5082         ret = eth_ixgbevf_dev_uninit(dev);
5083         if (ret)
5084                 return ret;
5085
5086         ret = eth_ixgbevf_dev_init(dev);
5087
5088         return ret;
5089 }
5090
5091 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5092 {
5093         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5094         struct ixgbe_vfta *shadow_vfta =
5095                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5096         int i = 0, j = 0, vfta = 0, mask = 1;
5097
5098         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5099                 vfta = shadow_vfta->vfta[i];
5100                 if (vfta) {
5101                         mask = 1;
5102                         for (j = 0; j < 32; j++) {
5103                                 if (vfta & mask)
5104                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5105                                                        on, false);
5106                                 mask <<= 1;
5107                         }
5108                 }
5109         }
5110
5111 }
5112
5113 static int
5114 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5115 {
5116         struct ixgbe_hw *hw =
5117                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5118         struct ixgbe_vfta *shadow_vfta =
5119                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5120         uint32_t vid_idx = 0;
5121         uint32_t vid_bit = 0;
5122         int ret = 0;
5123
5124         PMD_INIT_FUNC_TRACE();
5125
5126         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5127         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5128         if (ret) {
5129                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5130                 return ret;
5131         }
5132         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5133         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5134
5135         /* Save what we set and retore it after device reset */
5136         if (on)
5137                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5138         else
5139                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5140
5141         return 0;
5142 }
5143
5144 static void
5145 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5146 {
5147         struct ixgbe_hw *hw =
5148                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5149         uint32_t ctrl;
5150
5151         PMD_INIT_FUNC_TRACE();
5152
5153         if (queue >= hw->mac.max_rx_queues)
5154                 return;
5155
5156         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5157         if (on)
5158                 ctrl |= IXGBE_RXDCTL_VME;
5159         else
5160                 ctrl &= ~IXGBE_RXDCTL_VME;
5161         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5162
5163         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5164 }
5165
5166 static int
5167 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5168 {
5169         struct ixgbe_hw *hw =
5170                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5171         struct ixgbe_rx_queue *rxq;
5172         uint16_t i;
5173         int on = 0;
5174
5175         /* VF function only support hw strip feature, others are not support */
5176         if (mask & ETH_VLAN_STRIP_MASK) {
5177                 for (i = 0; i < hw->mac.max_rx_queues; i++) {
5178                         rxq = dev->data->rx_queues[i];
5179                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5180                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5181                 }
5182         }
5183
5184         return 0;
5185 }
5186
5187 int
5188 ixgbe_vt_check(struct ixgbe_hw *hw)
5189 {
5190         uint32_t reg_val;
5191
5192         /* if Virtualization Technology is enabled */
5193         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5194         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5195                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5196                 return -1;
5197         }
5198
5199         return 0;
5200 }
5201
5202 static uint32_t
5203 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5204 {
5205         uint32_t vector = 0;
5206
5207         switch (hw->mac.mc_filter_type) {
5208         case 0:   /* use bits [47:36] of the address */
5209                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5210                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5211                 break;
5212         case 1:   /* use bits [46:35] of the address */
5213                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5214                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5215                 break;
5216         case 2:   /* use bits [45:34] of the address */
5217                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5218                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5219                 break;
5220         case 3:   /* use bits [43:32] of the address */
5221                 vector = ((uc_addr->addr_bytes[4]) |
5222                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5223                 break;
5224         default:  /* Invalid mc_filter_type */
5225                 break;
5226         }
5227
5228         /* vector can only be 12-bits or boundary will be exceeded */
5229         vector &= 0xFFF;
5230         return vector;
5231 }
5232
5233 static int
5234 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5235                         uint8_t on)
5236 {
5237         uint32_t vector;
5238         uint32_t uta_idx;
5239         uint32_t reg_val;
5240         uint32_t uta_shift;
5241         uint32_t rc;
5242         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5243         const uint32_t ixgbe_uta_bit_shift = 5;
5244         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5245         const uint32_t bit1 = 0x1;
5246
5247         struct ixgbe_hw *hw =
5248                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5249         struct ixgbe_uta_info *uta_info =
5250                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5251
5252         /* The UTA table only exists on 82599 hardware and newer */
5253         if (hw->mac.type < ixgbe_mac_82599EB)
5254                 return -ENOTSUP;
5255
5256         vector = ixgbe_uta_vector(hw, mac_addr);
5257         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5258         uta_shift = vector & ixgbe_uta_bit_mask;
5259
5260         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5261         if (rc == on)
5262                 return 0;
5263
5264         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5265         if (on) {
5266                 uta_info->uta_in_use++;
5267                 reg_val |= (bit1 << uta_shift);
5268                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5269         } else {
5270                 uta_info->uta_in_use--;
5271                 reg_val &= ~(bit1 << uta_shift);
5272                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5273         }
5274
5275         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5276
5277         if (uta_info->uta_in_use > 0)
5278                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5279                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5280         else
5281                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5282
5283         return 0;
5284 }
5285
5286 static int
5287 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5288 {
5289         int i;
5290         struct ixgbe_hw *hw =
5291                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5292         struct ixgbe_uta_info *uta_info =
5293                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5294
5295         /* The UTA table only exists on 82599 hardware and newer */
5296         if (hw->mac.type < ixgbe_mac_82599EB)
5297                 return -ENOTSUP;
5298
5299         if (on) {
5300                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5301                         uta_info->uta_shadow[i] = ~0;
5302                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5303                 }
5304         } else {
5305                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5306                         uta_info->uta_shadow[i] = 0;
5307                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5308                 }
5309         }
5310         return 0;
5311
5312 }
5313
5314 uint32_t
5315 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5316 {
5317         uint32_t new_val = orig_val;
5318
5319         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5320                 new_val |= IXGBE_VMOLR_AUPE;
5321         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5322                 new_val |= IXGBE_VMOLR_ROMPE;
5323         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5324                 new_val |= IXGBE_VMOLR_ROPE;
5325         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5326                 new_val |= IXGBE_VMOLR_BAM;
5327         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5328                 new_val |= IXGBE_VMOLR_MPE;
5329
5330         return new_val;
5331 }
5332
5333 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5334 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5335 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5336 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5337 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5338         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5339         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5340
5341 static int
5342 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5343                       struct rte_eth_mirror_conf *mirror_conf,
5344                       uint8_t rule_id, uint8_t on)
5345 {
5346         uint32_t mr_ctl, vlvf;
5347         uint32_t mp_lsb = 0;
5348         uint32_t mv_msb = 0;
5349         uint32_t mv_lsb = 0;
5350         uint32_t mp_msb = 0;
5351         uint8_t i = 0;
5352         int reg_index = 0;
5353         uint64_t vlan_mask = 0;
5354
5355         const uint8_t pool_mask_offset = 32;
5356         const uint8_t vlan_mask_offset = 32;
5357         const uint8_t dst_pool_offset = 8;
5358         const uint8_t rule_mr_offset  = 4;
5359         const uint8_t mirror_rule_mask = 0x0F;
5360
5361         struct ixgbe_mirror_info *mr_info =
5362                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5363         struct ixgbe_hw *hw =
5364                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5365         uint8_t mirror_type = 0;
5366
5367         if (ixgbe_vt_check(hw) < 0)
5368                 return -ENOTSUP;
5369
5370         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5371                 return -EINVAL;
5372
5373         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5374                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5375                             mirror_conf->rule_type);
5376                 return -EINVAL;
5377         }
5378
5379         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5380                 mirror_type |= IXGBE_MRCTL_VLME;
5381                 /* Check if vlan id is valid and find conresponding VLAN ID
5382                  * index in VLVF
5383                  */
5384                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5385                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5386                                 /* search vlan id related pool vlan filter
5387                                  * index
5388                                  */
5389                                 reg_index = ixgbe_find_vlvf_slot(
5390                                                 hw,
5391                                                 mirror_conf->vlan.vlan_id[i],
5392                                                 false);
5393                                 if (reg_index < 0)
5394                                         return -EINVAL;
5395                                 vlvf = IXGBE_READ_REG(hw,
5396                                                       IXGBE_VLVF(reg_index));
5397                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5398                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5399                                       mirror_conf->vlan.vlan_id[i]))
5400                                         vlan_mask |= (1ULL << reg_index);
5401                                 else
5402                                         return -EINVAL;
5403                         }
5404                 }
5405
5406                 if (on) {
5407                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5408                         mv_msb = vlan_mask >> vlan_mask_offset;
5409
5410                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5411                                                 mirror_conf->vlan.vlan_mask;
5412                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5413                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5414                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5415                                                 mirror_conf->vlan.vlan_id[i];
5416                         }
5417                 } else {
5418                         mv_lsb = 0;
5419                         mv_msb = 0;
5420                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5421                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5422                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5423                 }
5424         }
5425
5426         /**
5427          * if enable pool mirror, write related pool mask register,if disable
5428          * pool mirror, clear PFMRVM register
5429          */
5430         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5431                 mirror_type |= IXGBE_MRCTL_VPME;
5432                 if (on) {
5433                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5434                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5435                         mr_info->mr_conf[rule_id].pool_mask =
5436                                         mirror_conf->pool_mask;
5437
5438                 } else {
5439                         mp_lsb = 0;
5440                         mp_msb = 0;
5441                         mr_info->mr_conf[rule_id].pool_mask = 0;
5442                 }
5443         }
5444         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5445                 mirror_type |= IXGBE_MRCTL_UPME;
5446         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5447                 mirror_type |= IXGBE_MRCTL_DPME;
5448
5449         /* read  mirror control register and recalculate it */
5450         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5451
5452         if (on) {
5453                 mr_ctl |= mirror_type;
5454                 mr_ctl &= mirror_rule_mask;
5455                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5456         } else {
5457                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5458         }
5459
5460         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5461         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5462
5463         /* write mirrror control  register */
5464         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5465
5466         /* write pool mirrror control  register */
5467         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5468                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5469                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5470                                 mp_msb);
5471         }
5472         /* write VLAN mirrror control  register */
5473         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5474                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5475                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5476                                 mv_msb);
5477         }
5478
5479         return 0;
5480 }
5481
5482 static int
5483 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5484 {
5485         int mr_ctl = 0;
5486         uint32_t lsb_val = 0;
5487         uint32_t msb_val = 0;
5488         const uint8_t rule_mr_offset = 4;
5489
5490         struct ixgbe_hw *hw =
5491                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5492         struct ixgbe_mirror_info *mr_info =
5493                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5494
5495         if (ixgbe_vt_check(hw) < 0)
5496                 return -ENOTSUP;
5497
5498         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5499                 return -EINVAL;
5500
5501         memset(&mr_info->mr_conf[rule_id], 0,
5502                sizeof(struct rte_eth_mirror_conf));
5503
5504         /* clear PFVMCTL register */
5505         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5506
5507         /* clear pool mask register */
5508         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5509         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5510
5511         /* clear vlan mask register */
5512         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5513         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5514
5515         return 0;
5516 }
5517
5518 static int
5519 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5520 {
5521         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5522         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5523         uint32_t mask;
5524         struct ixgbe_hw *hw =
5525                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5526         uint32_t vec = IXGBE_MISC_VEC_ID;
5527
5528         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5529         if (rte_intr_allow_others(intr_handle))
5530                 vec = IXGBE_RX_VEC_START;
5531         mask |= (1 << vec);
5532         RTE_SET_USED(queue_id);
5533         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5534
5535         rte_intr_enable(intr_handle);
5536
5537         return 0;
5538 }
5539
5540 static int
5541 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5542 {
5543         uint32_t mask;
5544         struct ixgbe_hw *hw =
5545                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5546         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5547         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5548         uint32_t vec = IXGBE_MISC_VEC_ID;
5549
5550         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5551         if (rte_intr_allow_others(intr_handle))
5552                 vec = IXGBE_RX_VEC_START;
5553         mask &= ~(1 << vec);
5554         RTE_SET_USED(queue_id);
5555         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5556
5557         return 0;
5558 }
5559
5560 static int
5561 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5562 {
5563         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5564         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5565         uint32_t mask;
5566         struct ixgbe_hw *hw =
5567                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5568         struct ixgbe_interrupt *intr =
5569                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5570
5571         if (queue_id < 16) {
5572                 ixgbe_disable_intr(hw);
5573                 intr->mask |= (1 << queue_id);
5574                 ixgbe_enable_intr(dev);
5575         } else if (queue_id < 32) {
5576                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5577                 mask &= (1 << queue_id);
5578                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5579         } else if (queue_id < 64) {
5580                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5581                 mask &= (1 << (queue_id - 32));
5582                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5583         }
5584         rte_intr_enable(intr_handle);
5585
5586         return 0;
5587 }
5588
5589 static int
5590 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5591 {
5592         uint32_t mask;
5593         struct ixgbe_hw *hw =
5594                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5595         struct ixgbe_interrupt *intr =
5596                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5597
5598         if (queue_id < 16) {
5599                 ixgbe_disable_intr(hw);
5600                 intr->mask &= ~(1 << queue_id);
5601                 ixgbe_enable_intr(dev);
5602         } else if (queue_id < 32) {
5603                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5604                 mask &= ~(1 << queue_id);
5605                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5606         } else if (queue_id < 64) {
5607                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5608                 mask &= ~(1 << (queue_id - 32));
5609                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5610         }
5611
5612         return 0;
5613 }
5614
5615 static void
5616 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5617                      uint8_t queue, uint8_t msix_vector)
5618 {
5619         uint32_t tmp, idx;
5620
5621         if (direction == -1) {
5622                 /* other causes */
5623                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5624                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5625                 tmp &= ~0xFF;
5626                 tmp |= msix_vector;
5627                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5628         } else {
5629                 /* rx or tx cause */
5630                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5631                 idx = ((16 * (queue & 1)) + (8 * direction));
5632                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5633                 tmp &= ~(0xFF << idx);
5634                 tmp |= (msix_vector << idx);
5635                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5636         }
5637 }
5638
5639 /**
5640  * set the IVAR registers, mapping interrupt causes to vectors
5641  * @param hw
5642  *  pointer to ixgbe_hw struct
5643  * @direction
5644  *  0 for Rx, 1 for Tx, -1 for other causes
5645  * @queue
5646  *  queue to map the corresponding interrupt to
5647  * @msix_vector
5648  *  the vector to map to the corresponding queue
5649  */
5650 static void
5651 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5652                    uint8_t queue, uint8_t msix_vector)
5653 {
5654         uint32_t tmp, idx;
5655
5656         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5657         if (hw->mac.type == ixgbe_mac_82598EB) {
5658                 if (direction == -1)
5659                         direction = 0;
5660                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5661                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5662                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5663                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5664                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5665         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5666                         (hw->mac.type == ixgbe_mac_X540) ||
5667                         (hw->mac.type == ixgbe_mac_X550)) {
5668                 if (direction == -1) {
5669                         /* other causes */
5670                         idx = ((queue & 1) * 8);
5671                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5672                         tmp &= ~(0xFF << idx);
5673                         tmp |= (msix_vector << idx);
5674                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5675                 } else {
5676                         /* rx or tx causes */
5677                         idx = ((16 * (queue & 1)) + (8 * direction));
5678                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5679                         tmp &= ~(0xFF << idx);
5680                         tmp |= (msix_vector << idx);
5681                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5682                 }
5683         }
5684 }
5685
5686 static void
5687 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5688 {
5689         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5690         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5691         struct ixgbe_hw *hw =
5692                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5693         uint32_t q_idx;
5694         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5695         uint32_t base = IXGBE_MISC_VEC_ID;
5696
5697         /* Configure VF other cause ivar */
5698         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5699
5700         /* won't configure msix register if no mapping is done
5701          * between intr vector and event fd.
5702          */
5703         if (!rte_intr_dp_is_en(intr_handle))
5704                 return;
5705
5706         if (rte_intr_allow_others(intr_handle)) {
5707                 base = IXGBE_RX_VEC_START;
5708                 vector_idx = IXGBE_RX_VEC_START;
5709         }
5710
5711         /* Configure all RX queues of VF */
5712         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5713                 /* Force all queue use vector 0,
5714                  * as IXGBE_VF_MAXMSIVECOTR = 1
5715                  */
5716                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5717                 intr_handle->intr_vec[q_idx] = vector_idx;
5718                 if (vector_idx < base + intr_handle->nb_efd - 1)
5719                         vector_idx++;
5720         }
5721 }
5722
5723 /**
5724  * Sets up the hardware to properly generate MSI-X interrupts
5725  * @hw
5726  *  board private structure
5727  */
5728 static void
5729 ixgbe_configure_msix(struct rte_eth_dev *dev)
5730 {
5731         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5732         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5733         struct ixgbe_hw *hw =
5734                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5735         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5736         uint32_t vec = IXGBE_MISC_VEC_ID;
5737         uint32_t mask;
5738         uint32_t gpie;
5739
5740         /* won't configure msix register if no mapping is done
5741          * between intr vector and event fd
5742          */
5743         if (!rte_intr_dp_is_en(intr_handle))
5744                 return;
5745
5746         if (rte_intr_allow_others(intr_handle))
5747                 vec = base = IXGBE_RX_VEC_START;
5748
5749         /* setup GPIE for MSI-x mode */
5750         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5751         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5752                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5753         /* auto clearing and auto setting corresponding bits in EIMS
5754          * when MSI-X interrupt is triggered
5755          */
5756         if (hw->mac.type == ixgbe_mac_82598EB) {
5757                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5758         } else {
5759                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5760                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5761         }
5762         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5763
5764         /* Populate the IVAR table and set the ITR values to the
5765          * corresponding register.
5766          */
5767         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5768              queue_id++) {
5769                 /* by default, 1:1 mapping */
5770                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5771                 intr_handle->intr_vec[queue_id] = vec;
5772                 if (vec < base + intr_handle->nb_efd - 1)
5773                         vec++;
5774         }
5775
5776         switch (hw->mac.type) {
5777         case ixgbe_mac_82598EB:
5778                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5779                                    IXGBE_MISC_VEC_ID);
5780                 break;
5781         case ixgbe_mac_82599EB:
5782         case ixgbe_mac_X540:
5783         case ixgbe_mac_X550:
5784                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5785                 break;
5786         default:
5787                 break;
5788         }
5789         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5790                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5791
5792         /* set up to autoclear timer, and the vectors */
5793         mask = IXGBE_EIMS_ENABLE_MASK;
5794         mask &= ~(IXGBE_EIMS_OTHER |
5795                   IXGBE_EIMS_MAILBOX |
5796                   IXGBE_EIMS_LSC);
5797
5798         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5799 }
5800
5801 int
5802 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5803                            uint16_t queue_idx, uint16_t tx_rate)
5804 {
5805         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5806         struct rte_eth_rxmode *rxmode;
5807         uint32_t rf_dec, rf_int;
5808         uint32_t bcnrc_val;
5809         uint16_t link_speed = dev->data->dev_link.link_speed;
5810
5811         if (queue_idx >= hw->mac.max_tx_queues)
5812                 return -EINVAL;
5813
5814         if (tx_rate != 0) {
5815                 /* Calculate the rate factor values to set */
5816                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5817                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5818                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5819
5820                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5821                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5822                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5823                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5824         } else {
5825                 bcnrc_val = 0;
5826         }
5827
5828         rxmode = &dev->data->dev_conf.rxmode;
5829         /*
5830          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5831          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5832          * set as 0x4.
5833          */
5834         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
5835             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
5836                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5837                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5838         else
5839                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5840                         IXGBE_MMW_SIZE_DEFAULT);
5841
5842         /* Set RTTBCNRC of queue X */
5843         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5844         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5845         IXGBE_WRITE_FLUSH(hw);
5846
5847         return 0;
5848 }
5849
5850 static int
5851 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5852                      __attribute__((unused)) uint32_t index,
5853                      __attribute__((unused)) uint32_t pool)
5854 {
5855         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5856         int diag;
5857
5858         /*
5859          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5860          * operation. Trap this case to avoid exhausting the [very limited]
5861          * set of PF resources used to store VF MAC addresses.
5862          */
5863         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5864                 return -1;
5865         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5866         if (diag != 0)
5867                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5868                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5869                             mac_addr->addr_bytes[0],
5870                             mac_addr->addr_bytes[1],
5871                             mac_addr->addr_bytes[2],
5872                             mac_addr->addr_bytes[3],
5873                             mac_addr->addr_bytes[4],
5874                             mac_addr->addr_bytes[5],
5875                             diag);
5876         return diag;
5877 }
5878
5879 static void
5880 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5881 {
5882         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5883         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5884         struct ether_addr *mac_addr;
5885         uint32_t i;
5886         int diag;
5887
5888         /*
5889          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5890          * not support the deletion of a given MAC address.
5891          * Instead, it imposes to delete all MAC addresses, then to add again
5892          * all MAC addresses with the exception of the one to be deleted.
5893          */
5894         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5895
5896         /*
5897          * Add again all MAC addresses, with the exception of the deleted one
5898          * and of the permanent MAC address.
5899          */
5900         for (i = 0, mac_addr = dev->data->mac_addrs;
5901              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5902                 /* Skip the deleted MAC address */
5903                 if (i == index)
5904                         continue;
5905                 /* Skip NULL MAC addresses */
5906                 if (is_zero_ether_addr(mac_addr))
5907                         continue;
5908                 /* Skip the permanent MAC address */
5909                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5910                         continue;
5911                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5912                 if (diag != 0)
5913                         PMD_DRV_LOG(ERR,
5914                                     "Adding again MAC address "
5915                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5916                                     "diag=%d",
5917                                     mac_addr->addr_bytes[0],
5918                                     mac_addr->addr_bytes[1],
5919                                     mac_addr->addr_bytes[2],
5920                                     mac_addr->addr_bytes[3],
5921                                     mac_addr->addr_bytes[4],
5922                                     mac_addr->addr_bytes[5],
5923                                     diag);
5924         }
5925 }
5926
5927 static void
5928 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5929 {
5930         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5931
5932         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5933 }
5934
5935 int
5936 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5937                         struct rte_eth_syn_filter *filter,
5938                         bool add)
5939 {
5940         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5941         struct ixgbe_filter_info *filter_info =
5942                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5943         uint32_t syn_info;
5944         uint32_t synqf;
5945
5946         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5947                 return -EINVAL;
5948
5949         syn_info = filter_info->syn_info;
5950
5951         if (add) {
5952                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5953                         return -EINVAL;
5954                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5955                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5956
5957                 if (filter->hig_pri)
5958                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5959                 else
5960                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5961         } else {
5962                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5963                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5964                         return -ENOENT;
5965                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5966         }
5967
5968         filter_info->syn_info = synqf;
5969         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5970         IXGBE_WRITE_FLUSH(hw);
5971         return 0;
5972 }
5973
5974 static int
5975 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5976                         struct rte_eth_syn_filter *filter)
5977 {
5978         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5979         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5980
5981         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5982                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5983                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5984                 return 0;
5985         }
5986         return -ENOENT;
5987 }
5988
5989 static int
5990 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5991                         enum rte_filter_op filter_op,
5992                         void *arg)
5993 {
5994         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5995         int ret;
5996
5997         MAC_TYPE_FILTER_SUP(hw->mac.type);
5998
5999         if (filter_op == RTE_ETH_FILTER_NOP)
6000                 return 0;
6001
6002         if (arg == NULL) {
6003                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6004                             filter_op);
6005                 return -EINVAL;
6006         }
6007
6008         switch (filter_op) {
6009         case RTE_ETH_FILTER_ADD:
6010                 ret = ixgbe_syn_filter_set(dev,
6011                                 (struct rte_eth_syn_filter *)arg,
6012                                 TRUE);
6013                 break;
6014         case RTE_ETH_FILTER_DELETE:
6015                 ret = ixgbe_syn_filter_set(dev,
6016                                 (struct rte_eth_syn_filter *)arg,
6017                                 FALSE);
6018                 break;
6019         case RTE_ETH_FILTER_GET:
6020                 ret = ixgbe_syn_filter_get(dev,
6021                                 (struct rte_eth_syn_filter *)arg);
6022                 break;
6023         default:
6024                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6025                 ret = -EINVAL;
6026                 break;
6027         }
6028
6029         return ret;
6030 }
6031
6032
6033 static inline enum ixgbe_5tuple_protocol
6034 convert_protocol_type(uint8_t protocol_value)
6035 {
6036         if (protocol_value == IPPROTO_TCP)
6037                 return IXGBE_FILTER_PROTOCOL_TCP;
6038         else if (protocol_value == IPPROTO_UDP)
6039                 return IXGBE_FILTER_PROTOCOL_UDP;
6040         else if (protocol_value == IPPROTO_SCTP)
6041                 return IXGBE_FILTER_PROTOCOL_SCTP;
6042         else
6043                 return IXGBE_FILTER_PROTOCOL_NONE;
6044 }
6045
6046 /* inject a 5-tuple filter to HW */
6047 static inline void
6048 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6049                            struct ixgbe_5tuple_filter *filter)
6050 {
6051         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6052         int i;
6053         uint32_t ftqf, sdpqf;
6054         uint32_t l34timir = 0;
6055         uint8_t mask = 0xff;
6056
6057         i = filter->index;
6058
6059         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6060                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6061         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6062
6063         ftqf = (uint32_t)(filter->filter_info.proto &
6064                 IXGBE_FTQF_PROTOCOL_MASK);
6065         ftqf |= (uint32_t)((filter->filter_info.priority &
6066                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6067         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6068                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6069         if (filter->filter_info.dst_ip_mask == 0)
6070                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6071         if (filter->filter_info.src_port_mask == 0)
6072                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6073         if (filter->filter_info.dst_port_mask == 0)
6074                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6075         if (filter->filter_info.proto_mask == 0)
6076                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6077         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6078         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6079         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6080
6081         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6082         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6083         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6084         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6085
6086         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6087         l34timir |= (uint32_t)(filter->queue <<
6088                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6089         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6090 }
6091
6092 /*
6093  * add a 5tuple filter
6094  *
6095  * @param
6096  * dev: Pointer to struct rte_eth_dev.
6097  * index: the index the filter allocates.
6098  * filter: ponter to the filter that will be added.
6099  * rx_queue: the queue id the filter assigned to.
6100  *
6101  * @return
6102  *    - On success, zero.
6103  *    - On failure, a negative value.
6104  */
6105 static int
6106 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6107                         struct ixgbe_5tuple_filter *filter)
6108 {
6109         struct ixgbe_filter_info *filter_info =
6110                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6111         int i, idx, shift;
6112
6113         /*
6114          * look for an unused 5tuple filter index,
6115          * and insert the filter to list.
6116          */
6117         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6118                 idx = i / (sizeof(uint32_t) * NBBY);
6119                 shift = i % (sizeof(uint32_t) * NBBY);
6120                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6121                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6122                         filter->index = i;
6123                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6124                                           filter,
6125                                           entries);
6126                         break;
6127                 }
6128         }
6129         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6130                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6131                 return -ENOSYS;
6132         }
6133
6134         ixgbe_inject_5tuple_filter(dev, filter);
6135
6136         return 0;
6137 }
6138
6139 /*
6140  * remove a 5tuple filter
6141  *
6142  * @param
6143  * dev: Pointer to struct rte_eth_dev.
6144  * filter: the pointer of the filter will be removed.
6145  */
6146 static void
6147 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6148                         struct ixgbe_5tuple_filter *filter)
6149 {
6150         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6151         struct ixgbe_filter_info *filter_info =
6152                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6153         uint16_t index = filter->index;
6154
6155         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6156                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6157         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6158         rte_free(filter);
6159
6160         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6161         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6162         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6163         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6164         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6165 }
6166
6167 static int
6168 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6169 {
6170         struct ixgbe_hw *hw;
6171         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6172         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6173
6174         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6175
6176         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6177                 return -EINVAL;
6178
6179         /* refuse mtu that requires the support of scattered packets when this
6180          * feature has not been enabled before.
6181          */
6182         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6183             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6184              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6185                 return -EINVAL;
6186
6187         /*
6188          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6189          * request of the version 2.0 of the mailbox API.
6190          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6191          * of the mailbox API.
6192          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6193          * prior to 3.11.33 which contains the following change:
6194          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6195          */
6196         ixgbevf_rlpml_set_vf(hw, max_frame);
6197
6198         /* update max frame size */
6199         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6200         return 0;
6201 }
6202
6203 static inline struct ixgbe_5tuple_filter *
6204 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6205                         struct ixgbe_5tuple_filter_info *key)
6206 {
6207         struct ixgbe_5tuple_filter *it;
6208
6209         TAILQ_FOREACH(it, filter_list, entries) {
6210                 if (memcmp(key, &it->filter_info,
6211                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6212                         return it;
6213                 }
6214         }
6215         return NULL;
6216 }
6217
6218 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6219 static inline int
6220 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6221                         struct ixgbe_5tuple_filter_info *filter_info)
6222 {
6223         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6224                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6225                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6226                 return -EINVAL;
6227
6228         switch (filter->dst_ip_mask) {
6229         case UINT32_MAX:
6230                 filter_info->dst_ip_mask = 0;
6231                 filter_info->dst_ip = filter->dst_ip;
6232                 break;
6233         case 0:
6234                 filter_info->dst_ip_mask = 1;
6235                 break;
6236         default:
6237                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6238                 return -EINVAL;
6239         }
6240
6241         switch (filter->src_ip_mask) {
6242         case UINT32_MAX:
6243                 filter_info->src_ip_mask = 0;
6244                 filter_info->src_ip = filter->src_ip;
6245                 break;
6246         case 0:
6247                 filter_info->src_ip_mask = 1;
6248                 break;
6249         default:
6250                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6251                 return -EINVAL;
6252         }
6253
6254         switch (filter->dst_port_mask) {
6255         case UINT16_MAX:
6256                 filter_info->dst_port_mask = 0;
6257                 filter_info->dst_port = filter->dst_port;
6258                 break;
6259         case 0:
6260                 filter_info->dst_port_mask = 1;
6261                 break;
6262         default:
6263                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6264                 return -EINVAL;
6265         }
6266
6267         switch (filter->src_port_mask) {
6268         case UINT16_MAX:
6269                 filter_info->src_port_mask = 0;
6270                 filter_info->src_port = filter->src_port;
6271                 break;
6272         case 0:
6273                 filter_info->src_port_mask = 1;
6274                 break;
6275         default:
6276                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6277                 return -EINVAL;
6278         }
6279
6280         switch (filter->proto_mask) {
6281         case UINT8_MAX:
6282                 filter_info->proto_mask = 0;
6283                 filter_info->proto =
6284                         convert_protocol_type(filter->proto);
6285                 break;
6286         case 0:
6287                 filter_info->proto_mask = 1;
6288                 break;
6289         default:
6290                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6291                 return -EINVAL;
6292         }
6293
6294         filter_info->priority = (uint8_t)filter->priority;
6295         return 0;
6296 }
6297
6298 /*
6299  * add or delete a ntuple filter
6300  *
6301  * @param
6302  * dev: Pointer to struct rte_eth_dev.
6303  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6304  * add: if true, add filter, if false, remove filter
6305  *
6306  * @return
6307  *    - On success, zero.
6308  *    - On failure, a negative value.
6309  */
6310 int
6311 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6312                         struct rte_eth_ntuple_filter *ntuple_filter,
6313                         bool add)
6314 {
6315         struct ixgbe_filter_info *filter_info =
6316                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6317         struct ixgbe_5tuple_filter_info filter_5tuple;
6318         struct ixgbe_5tuple_filter *filter;
6319         int ret;
6320
6321         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6322                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6323                 return -EINVAL;
6324         }
6325
6326         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6327         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6328         if (ret < 0)
6329                 return ret;
6330
6331         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6332                                          &filter_5tuple);
6333         if (filter != NULL && add) {
6334                 PMD_DRV_LOG(ERR, "filter exists.");
6335                 return -EEXIST;
6336         }
6337         if (filter == NULL && !add) {
6338                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6339                 return -ENOENT;
6340         }
6341
6342         if (add) {
6343                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6344                                 sizeof(struct ixgbe_5tuple_filter), 0);
6345                 if (filter == NULL)
6346                         return -ENOMEM;
6347                 rte_memcpy(&filter->filter_info,
6348                                  &filter_5tuple,
6349                                  sizeof(struct ixgbe_5tuple_filter_info));
6350                 filter->queue = ntuple_filter->queue;
6351                 ret = ixgbe_add_5tuple_filter(dev, filter);
6352                 if (ret < 0) {
6353                         rte_free(filter);
6354                         return ret;
6355                 }
6356         } else
6357                 ixgbe_remove_5tuple_filter(dev, filter);
6358
6359         return 0;
6360 }
6361
6362 /*
6363  * get a ntuple filter
6364  *
6365  * @param
6366  * dev: Pointer to struct rte_eth_dev.
6367  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6368  *
6369  * @return
6370  *    - On success, zero.
6371  *    - On failure, a negative value.
6372  */
6373 static int
6374 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6375                         struct rte_eth_ntuple_filter *ntuple_filter)
6376 {
6377         struct ixgbe_filter_info *filter_info =
6378                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6379         struct ixgbe_5tuple_filter_info filter_5tuple;
6380         struct ixgbe_5tuple_filter *filter;
6381         int ret;
6382
6383         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6384                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6385                 return -EINVAL;
6386         }
6387
6388         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6389         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6390         if (ret < 0)
6391                 return ret;
6392
6393         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6394                                          &filter_5tuple);
6395         if (filter == NULL) {
6396                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6397                 return -ENOENT;
6398         }
6399         ntuple_filter->queue = filter->queue;
6400         return 0;
6401 }
6402
6403 /*
6404  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6405  * @dev: pointer to rte_eth_dev structure
6406  * @filter_op:operation will be taken.
6407  * @arg: a pointer to specific structure corresponding to the filter_op
6408  *
6409  * @return
6410  *    - On success, zero.
6411  *    - On failure, a negative value.
6412  */
6413 static int
6414 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6415                                 enum rte_filter_op filter_op,
6416                                 void *arg)
6417 {
6418         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6419         int ret;
6420
6421         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6422
6423         if (filter_op == RTE_ETH_FILTER_NOP)
6424                 return 0;
6425
6426         if (arg == NULL) {
6427                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6428                             filter_op);
6429                 return -EINVAL;
6430         }
6431
6432         switch (filter_op) {
6433         case RTE_ETH_FILTER_ADD:
6434                 ret = ixgbe_add_del_ntuple_filter(dev,
6435                         (struct rte_eth_ntuple_filter *)arg,
6436                         TRUE);
6437                 break;
6438         case RTE_ETH_FILTER_DELETE:
6439                 ret = ixgbe_add_del_ntuple_filter(dev,
6440                         (struct rte_eth_ntuple_filter *)arg,
6441                         FALSE);
6442                 break;
6443         case RTE_ETH_FILTER_GET:
6444                 ret = ixgbe_get_ntuple_filter(dev,
6445                         (struct rte_eth_ntuple_filter *)arg);
6446                 break;
6447         default:
6448                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6449                 ret = -EINVAL;
6450                 break;
6451         }
6452         return ret;
6453 }
6454
6455 int
6456 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6457                         struct rte_eth_ethertype_filter *filter,
6458                         bool add)
6459 {
6460         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6461         struct ixgbe_filter_info *filter_info =
6462                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6463         uint32_t etqf = 0;
6464         uint32_t etqs = 0;
6465         int ret;
6466         struct ixgbe_ethertype_filter ethertype_filter;
6467
6468         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6469                 return -EINVAL;
6470
6471         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6472                 filter->ether_type == ETHER_TYPE_IPv6) {
6473                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6474                         " ethertype filter.", filter->ether_type);
6475                 return -EINVAL;
6476         }
6477
6478         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6479                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6480                 return -EINVAL;
6481         }
6482         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6483                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6484                 return -EINVAL;
6485         }
6486
6487         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6488         if (ret >= 0 && add) {
6489                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6490                             filter->ether_type);
6491                 return -EEXIST;
6492         }
6493         if (ret < 0 && !add) {
6494                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6495                             filter->ether_type);
6496                 return -ENOENT;
6497         }
6498
6499         if (add) {
6500                 etqf = IXGBE_ETQF_FILTER_EN;
6501                 etqf |= (uint32_t)filter->ether_type;
6502                 etqs |= (uint32_t)((filter->queue <<
6503                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6504                                     IXGBE_ETQS_RX_QUEUE);
6505                 etqs |= IXGBE_ETQS_QUEUE_EN;
6506
6507                 ethertype_filter.ethertype = filter->ether_type;
6508                 ethertype_filter.etqf = etqf;
6509                 ethertype_filter.etqs = etqs;
6510                 ethertype_filter.conf = FALSE;
6511                 ret = ixgbe_ethertype_filter_insert(filter_info,
6512                                                     &ethertype_filter);
6513                 if (ret < 0) {
6514                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6515                         return -ENOSPC;
6516                 }
6517         } else {
6518                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6519                 if (ret < 0)
6520                         return -ENOSYS;
6521         }
6522         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6523         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6524         IXGBE_WRITE_FLUSH(hw);
6525
6526         return 0;
6527 }
6528
6529 static int
6530 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6531                         struct rte_eth_ethertype_filter *filter)
6532 {
6533         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6534         struct ixgbe_filter_info *filter_info =
6535                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6536         uint32_t etqf, etqs;
6537         int ret;
6538
6539         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6540         if (ret < 0) {
6541                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6542                             filter->ether_type);
6543                 return -ENOENT;
6544         }
6545
6546         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6547         if (etqf & IXGBE_ETQF_FILTER_EN) {
6548                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6549                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6550                 filter->flags = 0;
6551                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6552                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6553                 return 0;
6554         }
6555         return -ENOENT;
6556 }
6557
6558 /*
6559  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6560  * @dev: pointer to rte_eth_dev structure
6561  * @filter_op:operation will be taken.
6562  * @arg: a pointer to specific structure corresponding to the filter_op
6563  */
6564 static int
6565 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6566                                 enum rte_filter_op filter_op,
6567                                 void *arg)
6568 {
6569         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6570         int ret;
6571
6572         MAC_TYPE_FILTER_SUP(hw->mac.type);
6573
6574         if (filter_op == RTE_ETH_FILTER_NOP)
6575                 return 0;
6576
6577         if (arg == NULL) {
6578                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6579                             filter_op);
6580                 return -EINVAL;
6581         }
6582
6583         switch (filter_op) {
6584         case RTE_ETH_FILTER_ADD:
6585                 ret = ixgbe_add_del_ethertype_filter(dev,
6586                         (struct rte_eth_ethertype_filter *)arg,
6587                         TRUE);
6588                 break;
6589         case RTE_ETH_FILTER_DELETE:
6590                 ret = ixgbe_add_del_ethertype_filter(dev,
6591                         (struct rte_eth_ethertype_filter *)arg,
6592                         FALSE);
6593                 break;
6594         case RTE_ETH_FILTER_GET:
6595                 ret = ixgbe_get_ethertype_filter(dev,
6596                         (struct rte_eth_ethertype_filter *)arg);
6597                 break;
6598         default:
6599                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6600                 ret = -EINVAL;
6601                 break;
6602         }
6603         return ret;
6604 }
6605
6606 static int
6607 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6608                      enum rte_filter_type filter_type,
6609                      enum rte_filter_op filter_op,
6610                      void *arg)
6611 {
6612         int ret = 0;
6613
6614         switch (filter_type) {
6615         case RTE_ETH_FILTER_NTUPLE:
6616                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6617                 break;
6618         case RTE_ETH_FILTER_ETHERTYPE:
6619                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6620                 break;
6621         case RTE_ETH_FILTER_SYN:
6622                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6623                 break;
6624         case RTE_ETH_FILTER_FDIR:
6625                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6626                 break;
6627         case RTE_ETH_FILTER_L2_TUNNEL:
6628                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6629                 break;
6630         case RTE_ETH_FILTER_GENERIC:
6631                 if (filter_op != RTE_ETH_FILTER_GET)
6632                         return -EINVAL;
6633                 *(const void **)arg = &ixgbe_flow_ops;
6634                 break;
6635         default:
6636                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6637                                                         filter_type);
6638                 ret = -EINVAL;
6639                 break;
6640         }
6641
6642         return ret;
6643 }
6644
6645 static u8 *
6646 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6647                         u8 **mc_addr_ptr, u32 *vmdq)
6648 {
6649         u8 *mc_addr;
6650
6651         *vmdq = 0;
6652         mc_addr = *mc_addr_ptr;
6653         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6654         return mc_addr;
6655 }
6656
6657 static int
6658 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6659                           struct ether_addr *mc_addr_set,
6660                           uint32_t nb_mc_addr)
6661 {
6662         struct ixgbe_hw *hw;
6663         u8 *mc_addr_list;
6664
6665         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6666         mc_addr_list = (u8 *)mc_addr_set;
6667         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6668                                          ixgbe_dev_addr_list_itr, TRUE);
6669 }
6670
6671 static uint64_t
6672 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6673 {
6674         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6675         uint64_t systime_cycles;
6676
6677         switch (hw->mac.type) {
6678         case ixgbe_mac_X550:
6679         case ixgbe_mac_X550EM_x:
6680         case ixgbe_mac_X550EM_a:
6681                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6682                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6683                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6684                                 * NSEC_PER_SEC;
6685                 break;
6686         default:
6687                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6688                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6689                                 << 32;
6690         }
6691
6692         return systime_cycles;
6693 }
6694
6695 static uint64_t
6696 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6697 {
6698         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6699         uint64_t rx_tstamp_cycles;
6700
6701         switch (hw->mac.type) {
6702         case ixgbe_mac_X550:
6703         case ixgbe_mac_X550EM_x:
6704         case ixgbe_mac_X550EM_a:
6705                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6706                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6707                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6708                                 * NSEC_PER_SEC;
6709                 break;
6710         default:
6711                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6712                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6713                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6714                                 << 32;
6715         }
6716
6717         return rx_tstamp_cycles;
6718 }
6719
6720 static uint64_t
6721 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6722 {
6723         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6724         uint64_t tx_tstamp_cycles;
6725
6726         switch (hw->mac.type) {
6727         case ixgbe_mac_X550:
6728         case ixgbe_mac_X550EM_x:
6729         case ixgbe_mac_X550EM_a:
6730                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6731                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6732                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6733                                 * NSEC_PER_SEC;
6734                 break;
6735         default:
6736                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6737                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6738                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6739                                 << 32;
6740         }
6741
6742         return tx_tstamp_cycles;
6743 }
6744
6745 static void
6746 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6747 {
6748         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6749         struct ixgbe_adapter *adapter =
6750                 (struct ixgbe_adapter *)dev->data->dev_private;
6751         struct rte_eth_link link;
6752         uint32_t incval = 0;
6753         uint32_t shift = 0;
6754
6755         /* Get current link speed. */
6756         ixgbe_dev_link_update(dev, 1);
6757         rte_eth_linkstatus_get(dev, &link);
6758
6759         switch (link.link_speed) {
6760         case ETH_SPEED_NUM_100M:
6761                 incval = IXGBE_INCVAL_100;
6762                 shift = IXGBE_INCVAL_SHIFT_100;
6763                 break;
6764         case ETH_SPEED_NUM_1G:
6765                 incval = IXGBE_INCVAL_1GB;
6766                 shift = IXGBE_INCVAL_SHIFT_1GB;
6767                 break;
6768         case ETH_SPEED_NUM_10G:
6769         default:
6770                 incval = IXGBE_INCVAL_10GB;
6771                 shift = IXGBE_INCVAL_SHIFT_10GB;
6772                 break;
6773         }
6774
6775         switch (hw->mac.type) {
6776         case ixgbe_mac_X550:
6777         case ixgbe_mac_X550EM_x:
6778         case ixgbe_mac_X550EM_a:
6779                 /* Independent of link speed. */
6780                 incval = 1;
6781                 /* Cycles read will be interpreted as ns. */
6782                 shift = 0;
6783                 /* Fall-through */
6784         case ixgbe_mac_X540:
6785                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6786                 break;
6787         case ixgbe_mac_82599EB:
6788                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6789                 shift -= IXGBE_INCVAL_SHIFT_82599;
6790                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6791                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6792                 break;
6793         default:
6794                 /* Not supported. */
6795                 return;
6796         }
6797
6798         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6799         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6800         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6801
6802         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6803         adapter->systime_tc.cc_shift = shift;
6804         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6805
6806         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6807         adapter->rx_tstamp_tc.cc_shift = shift;
6808         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6809
6810         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6811         adapter->tx_tstamp_tc.cc_shift = shift;
6812         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6813 }
6814
6815 static int
6816 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6817 {
6818         struct ixgbe_adapter *adapter =
6819                         (struct ixgbe_adapter *)dev->data->dev_private;
6820
6821         adapter->systime_tc.nsec += delta;
6822         adapter->rx_tstamp_tc.nsec += delta;
6823         adapter->tx_tstamp_tc.nsec += delta;
6824
6825         return 0;
6826 }
6827
6828 static int
6829 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6830 {
6831         uint64_t ns;
6832         struct ixgbe_adapter *adapter =
6833                         (struct ixgbe_adapter *)dev->data->dev_private;
6834
6835         ns = rte_timespec_to_ns(ts);
6836         /* Set the timecounters to a new value. */
6837         adapter->systime_tc.nsec = ns;
6838         adapter->rx_tstamp_tc.nsec = ns;
6839         adapter->tx_tstamp_tc.nsec = ns;
6840
6841         return 0;
6842 }
6843
6844 static int
6845 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6846 {
6847         uint64_t ns, systime_cycles;
6848         struct ixgbe_adapter *adapter =
6849                         (struct ixgbe_adapter *)dev->data->dev_private;
6850
6851         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6852         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6853         *ts = rte_ns_to_timespec(ns);
6854
6855         return 0;
6856 }
6857
6858 static int
6859 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6860 {
6861         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6862         uint32_t tsync_ctl;
6863         uint32_t tsauxc;
6864
6865         /* Stop the timesync system time. */
6866         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6867         /* Reset the timesync system time value. */
6868         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6869         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6870
6871         /* Enable system time for platforms where it isn't on by default. */
6872         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6873         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6874         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6875
6876         ixgbe_start_timecounters(dev);
6877
6878         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6879         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6880                         (ETHER_TYPE_1588 |
6881                          IXGBE_ETQF_FILTER_EN |
6882                          IXGBE_ETQF_1588));
6883
6884         /* Enable timestamping of received PTP packets. */
6885         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6886         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6887         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6888
6889         /* Enable timestamping of transmitted PTP packets. */
6890         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6891         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6892         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6893
6894         IXGBE_WRITE_FLUSH(hw);
6895
6896         return 0;
6897 }
6898
6899 static int
6900 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6901 {
6902         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6903         uint32_t tsync_ctl;
6904
6905         /* Disable timestamping of transmitted PTP packets. */
6906         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6907         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6908         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6909
6910         /* Disable timestamping of received PTP packets. */
6911         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6912         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6913         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6914
6915         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6916         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6917
6918         /* Stop incrementating the System Time registers. */
6919         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6920
6921         return 0;
6922 }
6923
6924 static int
6925 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6926                                  struct timespec *timestamp,
6927                                  uint32_t flags __rte_unused)
6928 {
6929         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6930         struct ixgbe_adapter *adapter =
6931                 (struct ixgbe_adapter *)dev->data->dev_private;
6932         uint32_t tsync_rxctl;
6933         uint64_t rx_tstamp_cycles;
6934         uint64_t ns;
6935
6936         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6937         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6938                 return -EINVAL;
6939
6940         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6941         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6942         *timestamp = rte_ns_to_timespec(ns);
6943
6944         return  0;
6945 }
6946
6947 static int
6948 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6949                                  struct timespec *timestamp)
6950 {
6951         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6952         struct ixgbe_adapter *adapter =
6953                 (struct ixgbe_adapter *)dev->data->dev_private;
6954         uint32_t tsync_txctl;
6955         uint64_t tx_tstamp_cycles;
6956         uint64_t ns;
6957
6958         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6959         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6960                 return -EINVAL;
6961
6962         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6963         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6964         *timestamp = rte_ns_to_timespec(ns);
6965
6966         return 0;
6967 }
6968
6969 static int
6970 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6971 {
6972         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6973         int count = 0;
6974         int g_ind = 0;
6975         const struct reg_info *reg_group;
6976         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6977                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6978
6979         while ((reg_group = reg_set[g_ind++]))
6980                 count += ixgbe_regs_group_count(reg_group);
6981
6982         return count;
6983 }
6984
6985 static int
6986 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6987 {
6988         int count = 0;
6989         int g_ind = 0;
6990         const struct reg_info *reg_group;
6991
6992         while ((reg_group = ixgbevf_regs[g_ind++]))
6993                 count += ixgbe_regs_group_count(reg_group);
6994
6995         return count;
6996 }
6997
6998 static int
6999 ixgbe_get_regs(struct rte_eth_dev *dev,
7000               struct rte_dev_reg_info *regs)
7001 {
7002         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7003         uint32_t *data = regs->data;
7004         int g_ind = 0;
7005         int count = 0;
7006         const struct reg_info *reg_group;
7007         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7008                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7009
7010         if (data == NULL) {
7011                 regs->length = ixgbe_get_reg_length(dev);
7012                 regs->width = sizeof(uint32_t);
7013                 return 0;
7014         }
7015
7016         /* Support only full register dump */
7017         if ((regs->length == 0) ||
7018             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7019                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7020                         hw->device_id;
7021                 while ((reg_group = reg_set[g_ind++]))
7022                         count += ixgbe_read_regs_group(dev, &data[count],
7023                                 reg_group);
7024                 return 0;
7025         }
7026
7027         return -ENOTSUP;
7028 }
7029
7030 static int
7031 ixgbevf_get_regs(struct rte_eth_dev *dev,
7032                 struct rte_dev_reg_info *regs)
7033 {
7034         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7035         uint32_t *data = regs->data;
7036         int g_ind = 0;
7037         int count = 0;
7038         const struct reg_info *reg_group;
7039
7040         if (data == NULL) {
7041                 regs->length = ixgbevf_get_reg_length(dev);
7042                 regs->width = sizeof(uint32_t);
7043                 return 0;
7044         }
7045
7046         /* Support only full register dump */
7047         if ((regs->length == 0) ||
7048             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7049                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7050                         hw->device_id;
7051                 while ((reg_group = ixgbevf_regs[g_ind++]))
7052                         count += ixgbe_read_regs_group(dev, &data[count],
7053                                                       reg_group);
7054                 return 0;
7055         }
7056
7057         return -ENOTSUP;
7058 }
7059
7060 static int
7061 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7062 {
7063         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7064
7065         /* Return unit is byte count */
7066         return hw->eeprom.word_size * 2;
7067 }
7068
7069 static int
7070 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7071                 struct rte_dev_eeprom_info *in_eeprom)
7072 {
7073         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7074         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7075         uint16_t *data = in_eeprom->data;
7076         int first, length;
7077
7078         first = in_eeprom->offset >> 1;
7079         length = in_eeprom->length >> 1;
7080         if ((first > hw->eeprom.word_size) ||
7081             ((first + length) > hw->eeprom.word_size))
7082                 return -EINVAL;
7083
7084         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7085
7086         return eeprom->ops.read_buffer(hw, first, length, data);
7087 }
7088
7089 static int
7090 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7091                 struct rte_dev_eeprom_info *in_eeprom)
7092 {
7093         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7094         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7095         uint16_t *data = in_eeprom->data;
7096         int first, length;
7097
7098         first = in_eeprom->offset >> 1;
7099         length = in_eeprom->length >> 1;
7100         if ((first > hw->eeprom.word_size) ||
7101             ((first + length) > hw->eeprom.word_size))
7102                 return -EINVAL;
7103
7104         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7105
7106         return eeprom->ops.write_buffer(hw,  first, length, data);
7107 }
7108
7109 uint16_t
7110 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7111         switch (mac_type) {
7112         case ixgbe_mac_X550:
7113         case ixgbe_mac_X550EM_x:
7114         case ixgbe_mac_X550EM_a:
7115                 return ETH_RSS_RETA_SIZE_512;
7116         case ixgbe_mac_X550_vf:
7117         case ixgbe_mac_X550EM_x_vf:
7118         case ixgbe_mac_X550EM_a_vf:
7119                 return ETH_RSS_RETA_SIZE_64;
7120         default:
7121                 return ETH_RSS_RETA_SIZE_128;
7122         }
7123 }
7124
7125 uint32_t
7126 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7127         switch (mac_type) {
7128         case ixgbe_mac_X550:
7129         case ixgbe_mac_X550EM_x:
7130         case ixgbe_mac_X550EM_a:
7131                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7132                         return IXGBE_RETA(reta_idx >> 2);
7133                 else
7134                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7135         case ixgbe_mac_X550_vf:
7136         case ixgbe_mac_X550EM_x_vf:
7137         case ixgbe_mac_X550EM_a_vf:
7138                 return IXGBE_VFRETA(reta_idx >> 2);
7139         default:
7140                 return IXGBE_RETA(reta_idx >> 2);
7141         }
7142 }
7143
7144 uint32_t
7145 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7146         switch (mac_type) {
7147         case ixgbe_mac_X550_vf:
7148         case ixgbe_mac_X550EM_x_vf:
7149         case ixgbe_mac_X550EM_a_vf:
7150                 return IXGBE_VFMRQC;
7151         default:
7152                 return IXGBE_MRQC;
7153         }
7154 }
7155
7156 uint32_t
7157 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7158         switch (mac_type) {
7159         case ixgbe_mac_X550_vf:
7160         case ixgbe_mac_X550EM_x_vf:
7161         case ixgbe_mac_X550EM_a_vf:
7162                 return IXGBE_VFRSSRK(i);
7163         default:
7164                 return IXGBE_RSSRK(i);
7165         }
7166 }
7167
7168 bool
7169 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7170         switch (mac_type) {
7171         case ixgbe_mac_82599_vf:
7172         case ixgbe_mac_X540_vf:
7173                 return 0;
7174         default:
7175                 return 1;
7176         }
7177 }
7178
7179 static int
7180 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7181                         struct rte_eth_dcb_info *dcb_info)
7182 {
7183         struct ixgbe_dcb_config *dcb_config =
7184                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7185         struct ixgbe_dcb_tc_config *tc;
7186         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7187         uint8_t nb_tcs;
7188         uint8_t i, j;
7189
7190         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7191                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7192         else
7193                 dcb_info->nb_tcs = 1;
7194
7195         tc_queue = &dcb_info->tc_queue;
7196         nb_tcs = dcb_info->nb_tcs;
7197
7198         if (dcb_config->vt_mode) { /* vt is enabled*/
7199                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7200                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7201                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7202                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7203                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7204                         for (j = 0; j < nb_tcs; j++) {
7205                                 tc_queue->tc_rxq[0][j].base = j;
7206                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7207                                 tc_queue->tc_txq[0][j].base = j;
7208                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7209                         }
7210                 } else {
7211                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7212                                 for (j = 0; j < nb_tcs; j++) {
7213                                         tc_queue->tc_rxq[i][j].base =
7214                                                 i * nb_tcs + j;
7215                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7216                                         tc_queue->tc_txq[i][j].base =
7217                                                 i * nb_tcs + j;
7218                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7219                                 }
7220                         }
7221                 }
7222         } else { /* vt is disabled*/
7223                 struct rte_eth_dcb_rx_conf *rx_conf =
7224                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7225                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7226                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7227                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7228                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7229                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7230                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7231                         }
7232                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7233                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7234                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7235                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7236                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7237                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7238                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7239                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7240                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7241                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7242                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7243                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7244                         }
7245                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7246                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7247                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7248                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7249                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7250                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7251                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7252                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7253                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7254                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7255                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7256                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7257                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7258                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7259                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7260                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7261                 }
7262         }
7263         for (i = 0; i < dcb_info->nb_tcs; i++) {
7264                 tc = &dcb_config->tc_config[i];
7265                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7266         }
7267         return 0;
7268 }
7269
7270 /* Update e-tag ether type */
7271 static int
7272 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7273                             uint16_t ether_type)
7274 {
7275         uint32_t etag_etype;
7276
7277         if (hw->mac.type != ixgbe_mac_X550 &&
7278             hw->mac.type != ixgbe_mac_X550EM_x &&
7279             hw->mac.type != ixgbe_mac_X550EM_a) {
7280                 return -ENOTSUP;
7281         }
7282
7283         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7284         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7285         etag_etype |= ether_type;
7286         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7287         IXGBE_WRITE_FLUSH(hw);
7288
7289         return 0;
7290 }
7291
7292 /* Config l2 tunnel ether type */
7293 static int
7294 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7295                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7296 {
7297         int ret = 0;
7298         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7299         struct ixgbe_l2_tn_info *l2_tn_info =
7300                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7301
7302         if (l2_tunnel == NULL)
7303                 return -EINVAL;
7304
7305         switch (l2_tunnel->l2_tunnel_type) {
7306         case RTE_L2_TUNNEL_TYPE_E_TAG:
7307                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7308                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7309                 break;
7310         default:
7311                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7312                 ret = -EINVAL;
7313                 break;
7314         }
7315
7316         return ret;
7317 }
7318
7319 /* Enable e-tag tunnel */
7320 static int
7321 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7322 {
7323         uint32_t etag_etype;
7324
7325         if (hw->mac.type != ixgbe_mac_X550 &&
7326             hw->mac.type != ixgbe_mac_X550EM_x &&
7327             hw->mac.type != ixgbe_mac_X550EM_a) {
7328                 return -ENOTSUP;
7329         }
7330
7331         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7332         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7333         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7334         IXGBE_WRITE_FLUSH(hw);
7335
7336         return 0;
7337 }
7338
7339 /* Enable l2 tunnel */
7340 static int
7341 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7342                            enum rte_eth_tunnel_type l2_tunnel_type)
7343 {
7344         int ret = 0;
7345         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7346         struct ixgbe_l2_tn_info *l2_tn_info =
7347                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7348
7349         switch (l2_tunnel_type) {
7350         case RTE_L2_TUNNEL_TYPE_E_TAG:
7351                 l2_tn_info->e_tag_en = TRUE;
7352                 ret = ixgbe_e_tag_enable(hw);
7353                 break;
7354         default:
7355                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7356                 ret = -EINVAL;
7357                 break;
7358         }
7359
7360         return ret;
7361 }
7362
7363 /* Disable e-tag tunnel */
7364 static int
7365 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7366 {
7367         uint32_t etag_etype;
7368
7369         if (hw->mac.type != ixgbe_mac_X550 &&
7370             hw->mac.type != ixgbe_mac_X550EM_x &&
7371             hw->mac.type != ixgbe_mac_X550EM_a) {
7372                 return -ENOTSUP;
7373         }
7374
7375         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7376         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7377         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7378         IXGBE_WRITE_FLUSH(hw);
7379
7380         return 0;
7381 }
7382
7383 /* Disable l2 tunnel */
7384 static int
7385 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7386                             enum rte_eth_tunnel_type l2_tunnel_type)
7387 {
7388         int ret = 0;
7389         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7390         struct ixgbe_l2_tn_info *l2_tn_info =
7391                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7392
7393         switch (l2_tunnel_type) {
7394         case RTE_L2_TUNNEL_TYPE_E_TAG:
7395                 l2_tn_info->e_tag_en = FALSE;
7396                 ret = ixgbe_e_tag_disable(hw);
7397                 break;
7398         default:
7399                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7400                 ret = -EINVAL;
7401                 break;
7402         }
7403
7404         return ret;
7405 }
7406
7407 static int
7408 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7409                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7410 {
7411         int ret = 0;
7412         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7413         uint32_t i, rar_entries;
7414         uint32_t rar_low, rar_high;
7415
7416         if (hw->mac.type != ixgbe_mac_X550 &&
7417             hw->mac.type != ixgbe_mac_X550EM_x &&
7418             hw->mac.type != ixgbe_mac_X550EM_a) {
7419                 return -ENOTSUP;
7420         }
7421
7422         rar_entries = ixgbe_get_num_rx_addrs(hw);
7423
7424         for (i = 1; i < rar_entries; i++) {
7425                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7426                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7427                 if ((rar_high & IXGBE_RAH_AV) &&
7428                     (rar_high & IXGBE_RAH_ADTYPE) &&
7429                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7430                      l2_tunnel->tunnel_id)) {
7431                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7432                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7433
7434                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7435
7436                         return ret;
7437                 }
7438         }
7439
7440         return ret;
7441 }
7442
7443 static int
7444 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7445                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7446 {
7447         int ret = 0;
7448         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7449         uint32_t i, rar_entries;
7450         uint32_t rar_low, rar_high;
7451
7452         if (hw->mac.type != ixgbe_mac_X550 &&
7453             hw->mac.type != ixgbe_mac_X550EM_x &&
7454             hw->mac.type != ixgbe_mac_X550EM_a) {
7455                 return -ENOTSUP;
7456         }
7457
7458         /* One entry for one tunnel. Try to remove potential existing entry. */
7459         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7460
7461         rar_entries = ixgbe_get_num_rx_addrs(hw);
7462
7463         for (i = 1; i < rar_entries; i++) {
7464                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7465                 if (rar_high & IXGBE_RAH_AV) {
7466                         continue;
7467                 } else {
7468                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7469                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7470                         rar_low = l2_tunnel->tunnel_id;
7471
7472                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7473                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7474
7475                         return ret;
7476                 }
7477         }
7478
7479         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7480                      " Please remove a rule before adding a new one.");
7481         return -EINVAL;
7482 }
7483
7484 static inline struct ixgbe_l2_tn_filter *
7485 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7486                           struct ixgbe_l2_tn_key *key)
7487 {
7488         int ret;
7489
7490         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7491         if (ret < 0)
7492                 return NULL;
7493
7494         return l2_tn_info->hash_map[ret];
7495 }
7496
7497 static inline int
7498 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7499                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7500 {
7501         int ret;
7502
7503         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7504                                &l2_tn_filter->key);
7505
7506         if (ret < 0) {
7507                 PMD_DRV_LOG(ERR,
7508                             "Failed to insert L2 tunnel filter"
7509                             " to hash table %d!",
7510                             ret);
7511                 return ret;
7512         }
7513
7514         l2_tn_info->hash_map[ret] = l2_tn_filter;
7515
7516         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7517
7518         return 0;
7519 }
7520
7521 static inline int
7522 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7523                           struct ixgbe_l2_tn_key *key)
7524 {
7525         int ret;
7526         struct ixgbe_l2_tn_filter *l2_tn_filter;
7527
7528         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7529
7530         if (ret < 0) {
7531                 PMD_DRV_LOG(ERR,
7532                             "No such L2 tunnel filter to delete %d!",
7533                             ret);
7534                 return ret;
7535         }
7536
7537         l2_tn_filter = l2_tn_info->hash_map[ret];
7538         l2_tn_info->hash_map[ret] = NULL;
7539
7540         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7541         rte_free(l2_tn_filter);
7542
7543         return 0;
7544 }
7545
7546 /* Add l2 tunnel filter */
7547 int
7548 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7549                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7550                                bool restore)
7551 {
7552         int ret;
7553         struct ixgbe_l2_tn_info *l2_tn_info =
7554                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7555         struct ixgbe_l2_tn_key key;
7556         struct ixgbe_l2_tn_filter *node;
7557
7558         if (!restore) {
7559                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7560                 key.tn_id = l2_tunnel->tunnel_id;
7561
7562                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7563
7564                 if (node) {
7565                         PMD_DRV_LOG(ERR,
7566                                     "The L2 tunnel filter already exists!");
7567                         return -EINVAL;
7568                 }
7569
7570                 node = rte_zmalloc("ixgbe_l2_tn",
7571                                    sizeof(struct ixgbe_l2_tn_filter),
7572                                    0);
7573                 if (!node)
7574                         return -ENOMEM;
7575
7576                 rte_memcpy(&node->key,
7577                                  &key,
7578                                  sizeof(struct ixgbe_l2_tn_key));
7579                 node->pool = l2_tunnel->pool;
7580                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7581                 if (ret < 0) {
7582                         rte_free(node);
7583                         return ret;
7584                 }
7585         }
7586
7587         switch (l2_tunnel->l2_tunnel_type) {
7588         case RTE_L2_TUNNEL_TYPE_E_TAG:
7589                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7590                 break;
7591         default:
7592                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7593                 ret = -EINVAL;
7594                 break;
7595         }
7596
7597         if ((!restore) && (ret < 0))
7598                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7599
7600         return ret;
7601 }
7602
7603 /* Delete l2 tunnel filter */
7604 int
7605 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7606                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7607 {
7608         int ret;
7609         struct ixgbe_l2_tn_info *l2_tn_info =
7610                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7611         struct ixgbe_l2_tn_key key;
7612
7613         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7614         key.tn_id = l2_tunnel->tunnel_id;
7615         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7616         if (ret < 0)
7617                 return ret;
7618
7619         switch (l2_tunnel->l2_tunnel_type) {
7620         case RTE_L2_TUNNEL_TYPE_E_TAG:
7621                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7622                 break;
7623         default:
7624                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7625                 ret = -EINVAL;
7626                 break;
7627         }
7628
7629         return ret;
7630 }
7631
7632 /**
7633  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7634  * @dev: pointer to rte_eth_dev structure
7635  * @filter_op:operation will be taken.
7636  * @arg: a pointer to specific structure corresponding to the filter_op
7637  */
7638 static int
7639 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7640                                   enum rte_filter_op filter_op,
7641                                   void *arg)
7642 {
7643         int ret;
7644
7645         if (filter_op == RTE_ETH_FILTER_NOP)
7646                 return 0;
7647
7648         if (arg == NULL) {
7649                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7650                             filter_op);
7651                 return -EINVAL;
7652         }
7653
7654         switch (filter_op) {
7655         case RTE_ETH_FILTER_ADD:
7656                 ret = ixgbe_dev_l2_tunnel_filter_add
7657                         (dev,
7658                          (struct rte_eth_l2_tunnel_conf *)arg,
7659                          FALSE);
7660                 break;
7661         case RTE_ETH_FILTER_DELETE:
7662                 ret = ixgbe_dev_l2_tunnel_filter_del
7663                         (dev,
7664                          (struct rte_eth_l2_tunnel_conf *)arg);
7665                 break;
7666         default:
7667                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7668                 ret = -EINVAL;
7669                 break;
7670         }
7671         return ret;
7672 }
7673
7674 static int
7675 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7676 {
7677         int ret = 0;
7678         uint32_t ctrl;
7679         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7680
7681         if (hw->mac.type != ixgbe_mac_X550 &&
7682             hw->mac.type != ixgbe_mac_X550EM_x &&
7683             hw->mac.type != ixgbe_mac_X550EM_a) {
7684                 return -ENOTSUP;
7685         }
7686
7687         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7688         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7689         if (en)
7690                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7691         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7692
7693         return ret;
7694 }
7695
7696 /* Enable l2 tunnel forwarding */
7697 static int
7698 ixgbe_dev_l2_tunnel_forwarding_enable
7699         (struct rte_eth_dev *dev,
7700          enum rte_eth_tunnel_type l2_tunnel_type)
7701 {
7702         struct ixgbe_l2_tn_info *l2_tn_info =
7703                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7704         int ret = 0;
7705
7706         switch (l2_tunnel_type) {
7707         case RTE_L2_TUNNEL_TYPE_E_TAG:
7708                 l2_tn_info->e_tag_fwd_en = TRUE;
7709                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7710                 break;
7711         default:
7712                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7713                 ret = -EINVAL;
7714                 break;
7715         }
7716
7717         return ret;
7718 }
7719
7720 /* Disable l2 tunnel forwarding */
7721 static int
7722 ixgbe_dev_l2_tunnel_forwarding_disable
7723         (struct rte_eth_dev *dev,
7724          enum rte_eth_tunnel_type l2_tunnel_type)
7725 {
7726         struct ixgbe_l2_tn_info *l2_tn_info =
7727                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7728         int ret = 0;
7729
7730         switch (l2_tunnel_type) {
7731         case RTE_L2_TUNNEL_TYPE_E_TAG:
7732                 l2_tn_info->e_tag_fwd_en = FALSE;
7733                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7734                 break;
7735         default:
7736                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7737                 ret = -EINVAL;
7738                 break;
7739         }
7740
7741         return ret;
7742 }
7743
7744 static int
7745 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7746                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7747                              bool en)
7748 {
7749         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7750         int ret = 0;
7751         uint32_t vmtir, vmvir;
7752         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7753
7754         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7755                 PMD_DRV_LOG(ERR,
7756                             "VF id %u should be less than %u",
7757                             l2_tunnel->vf_id,
7758                             pci_dev->max_vfs);
7759                 return -EINVAL;
7760         }
7761
7762         if (hw->mac.type != ixgbe_mac_X550 &&
7763             hw->mac.type != ixgbe_mac_X550EM_x &&
7764             hw->mac.type != ixgbe_mac_X550EM_a) {
7765                 return -ENOTSUP;
7766         }
7767
7768         if (en)
7769                 vmtir = l2_tunnel->tunnel_id;
7770         else
7771                 vmtir = 0;
7772
7773         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7774
7775         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7776         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7777         if (en)
7778                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7779         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7780
7781         return ret;
7782 }
7783
7784 /* Enable l2 tunnel tag insertion */
7785 static int
7786 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7787                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7788 {
7789         int ret = 0;
7790
7791         switch (l2_tunnel->l2_tunnel_type) {
7792         case RTE_L2_TUNNEL_TYPE_E_TAG:
7793                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7794                 break;
7795         default:
7796                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7797                 ret = -EINVAL;
7798                 break;
7799         }
7800
7801         return ret;
7802 }
7803
7804 /* Disable l2 tunnel tag insertion */
7805 static int
7806 ixgbe_dev_l2_tunnel_insertion_disable
7807         (struct rte_eth_dev *dev,
7808          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7809 {
7810         int ret = 0;
7811
7812         switch (l2_tunnel->l2_tunnel_type) {
7813         case RTE_L2_TUNNEL_TYPE_E_TAG:
7814                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7815                 break;
7816         default:
7817                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7818                 ret = -EINVAL;
7819                 break;
7820         }
7821
7822         return ret;
7823 }
7824
7825 static int
7826 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7827                              bool en)
7828 {
7829         int ret = 0;
7830         uint32_t qde;
7831         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7832
7833         if (hw->mac.type != ixgbe_mac_X550 &&
7834             hw->mac.type != ixgbe_mac_X550EM_x &&
7835             hw->mac.type != ixgbe_mac_X550EM_a) {
7836                 return -ENOTSUP;
7837         }
7838
7839         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7840         if (en)
7841                 qde |= IXGBE_QDE_STRIP_TAG;
7842         else
7843                 qde &= ~IXGBE_QDE_STRIP_TAG;
7844         qde &= ~IXGBE_QDE_READ;
7845         qde |= IXGBE_QDE_WRITE;
7846         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7847
7848         return ret;
7849 }
7850
7851 /* Enable l2 tunnel tag stripping */
7852 static int
7853 ixgbe_dev_l2_tunnel_stripping_enable
7854         (struct rte_eth_dev *dev,
7855          enum rte_eth_tunnel_type l2_tunnel_type)
7856 {
7857         int ret = 0;
7858
7859         switch (l2_tunnel_type) {
7860         case RTE_L2_TUNNEL_TYPE_E_TAG:
7861                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7862                 break;
7863         default:
7864                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7865                 ret = -EINVAL;
7866                 break;
7867         }
7868
7869         return ret;
7870 }
7871
7872 /* Disable l2 tunnel tag stripping */
7873 static int
7874 ixgbe_dev_l2_tunnel_stripping_disable
7875         (struct rte_eth_dev *dev,
7876          enum rte_eth_tunnel_type l2_tunnel_type)
7877 {
7878         int ret = 0;
7879
7880         switch (l2_tunnel_type) {
7881         case RTE_L2_TUNNEL_TYPE_E_TAG:
7882                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7883                 break;
7884         default:
7885                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7886                 ret = -EINVAL;
7887                 break;
7888         }
7889
7890         return ret;
7891 }
7892
7893 /* Enable/disable l2 tunnel offload functions */
7894 static int
7895 ixgbe_dev_l2_tunnel_offload_set
7896         (struct rte_eth_dev *dev,
7897          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7898          uint32_t mask,
7899          uint8_t en)
7900 {
7901         int ret = 0;
7902
7903         if (l2_tunnel == NULL)
7904                 return -EINVAL;
7905
7906         ret = -EINVAL;
7907         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7908                 if (en)
7909                         ret = ixgbe_dev_l2_tunnel_enable(
7910                                 dev,
7911                                 l2_tunnel->l2_tunnel_type);
7912                 else
7913                         ret = ixgbe_dev_l2_tunnel_disable(
7914                                 dev,
7915                                 l2_tunnel->l2_tunnel_type);
7916         }
7917
7918         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7919                 if (en)
7920                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7921                                 dev,
7922                                 l2_tunnel);
7923                 else
7924                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7925                                 dev,
7926                                 l2_tunnel);
7927         }
7928
7929         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7930                 if (en)
7931                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7932                                 dev,
7933                                 l2_tunnel->l2_tunnel_type);
7934                 else
7935                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7936                                 dev,
7937                                 l2_tunnel->l2_tunnel_type);
7938         }
7939
7940         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7941                 if (en)
7942                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7943                                 dev,
7944                                 l2_tunnel->l2_tunnel_type);
7945                 else
7946                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7947                                 dev,
7948                                 l2_tunnel->l2_tunnel_type);
7949         }
7950
7951         return ret;
7952 }
7953
7954 static int
7955 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7956                         uint16_t port)
7957 {
7958         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7959         IXGBE_WRITE_FLUSH(hw);
7960
7961         return 0;
7962 }
7963
7964 /* There's only one register for VxLAN UDP port.
7965  * So, we cannot add several ports. Will update it.
7966  */
7967 static int
7968 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7969                      uint16_t port)
7970 {
7971         if (port == 0) {
7972                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7973                 return -EINVAL;
7974         }
7975
7976         return ixgbe_update_vxlan_port(hw, port);
7977 }
7978
7979 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7980  * UDP port, it must have a value.
7981  * So, will reset it to the original value 0.
7982  */
7983 static int
7984 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7985                      uint16_t port)
7986 {
7987         uint16_t cur_port;
7988
7989         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7990
7991         if (cur_port != port) {
7992                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7993                 return -EINVAL;
7994         }
7995
7996         return ixgbe_update_vxlan_port(hw, 0);
7997 }
7998
7999 /* Add UDP tunneling port */
8000 static int
8001 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8002                               struct rte_eth_udp_tunnel *udp_tunnel)
8003 {
8004         int ret = 0;
8005         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8006
8007         if (hw->mac.type != ixgbe_mac_X550 &&
8008             hw->mac.type != ixgbe_mac_X550EM_x &&
8009             hw->mac.type != ixgbe_mac_X550EM_a) {
8010                 return -ENOTSUP;
8011         }
8012
8013         if (udp_tunnel == NULL)
8014                 return -EINVAL;
8015
8016         switch (udp_tunnel->prot_type) {
8017         case RTE_TUNNEL_TYPE_VXLAN:
8018                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8019                 break;
8020
8021         case RTE_TUNNEL_TYPE_GENEVE:
8022         case RTE_TUNNEL_TYPE_TEREDO:
8023                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8024                 ret = -EINVAL;
8025                 break;
8026
8027         default:
8028                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8029                 ret = -EINVAL;
8030                 break;
8031         }
8032
8033         return ret;
8034 }
8035
8036 /* Remove UDP tunneling port */
8037 static int
8038 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8039                               struct rte_eth_udp_tunnel *udp_tunnel)
8040 {
8041         int ret = 0;
8042         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8043
8044         if (hw->mac.type != ixgbe_mac_X550 &&
8045             hw->mac.type != ixgbe_mac_X550EM_x &&
8046             hw->mac.type != ixgbe_mac_X550EM_a) {
8047                 return -ENOTSUP;
8048         }
8049
8050         if (udp_tunnel == NULL)
8051                 return -EINVAL;
8052
8053         switch (udp_tunnel->prot_type) {
8054         case RTE_TUNNEL_TYPE_VXLAN:
8055                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8056                 break;
8057         case RTE_TUNNEL_TYPE_GENEVE:
8058         case RTE_TUNNEL_TYPE_TEREDO:
8059                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8060                 ret = -EINVAL;
8061                 break;
8062         default:
8063                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8064                 ret = -EINVAL;
8065                 break;
8066         }
8067
8068         return ret;
8069 }
8070
8071 static void
8072 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8073 {
8074         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8075
8076         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8077 }
8078
8079 static void
8080 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8081 {
8082         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8083
8084         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8085 }
8086
8087 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8088 {
8089         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8090         u32 in_msg = 0;
8091
8092         /* peek the message first */
8093         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8094
8095         /* PF reset VF event */
8096         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8097                 /* dummy mbx read to ack pf */
8098                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8099                         return;
8100                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8101                                               NULL);
8102         }
8103 }
8104
8105 static int
8106 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8107 {
8108         uint32_t eicr;
8109         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8110         struct ixgbe_interrupt *intr =
8111                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8112         ixgbevf_intr_disable(hw);
8113
8114         /* read-on-clear nic registers here */
8115         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8116         intr->flags = 0;
8117
8118         /* only one misc vector supported - mailbox */
8119         eicr &= IXGBE_VTEICR_MASK;
8120         if (eicr == IXGBE_MISC_VEC_ID)
8121                 intr->flags |= IXGBE_FLAG_MAILBOX;
8122
8123         return 0;
8124 }
8125
8126 static int
8127 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8128 {
8129         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8130         struct ixgbe_interrupt *intr =
8131                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8132
8133         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8134                 ixgbevf_mbx_process(dev);
8135                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8136         }
8137
8138         ixgbevf_intr_enable(hw);
8139
8140         return 0;
8141 }
8142
8143 static void
8144 ixgbevf_dev_interrupt_handler(void *param)
8145 {
8146         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8147
8148         ixgbevf_dev_interrupt_get_status(dev);
8149         ixgbevf_dev_interrupt_action(dev);
8150 }
8151
8152 /**
8153  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8154  *  @hw: pointer to hardware structure
8155  *
8156  *  Stops the transmit data path and waits for the HW to internally empty
8157  *  the Tx security block
8158  **/
8159 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8160 {
8161 #define IXGBE_MAX_SECTX_POLL 40
8162
8163         int i;
8164         int sectxreg;
8165
8166         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8167         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8168         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8169         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8170                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8171                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8172                         break;
8173                 /* Use interrupt-safe sleep just in case */
8174                 usec_delay(1000);
8175         }
8176
8177         /* For informational purposes only */
8178         if (i >= IXGBE_MAX_SECTX_POLL)
8179                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8180                          "path fully disabled.  Continuing with init.");
8181
8182         return IXGBE_SUCCESS;
8183 }
8184
8185 /**
8186  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8187  *  @hw: pointer to hardware structure
8188  *
8189  *  Enables the transmit data path.
8190  **/
8191 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8192 {
8193         uint32_t sectxreg;
8194
8195         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8196         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8197         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8198         IXGBE_WRITE_FLUSH(hw);
8199
8200         return IXGBE_SUCCESS;
8201 }
8202
8203 /* restore n-tuple filter */
8204 static inline void
8205 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8206 {
8207         struct ixgbe_filter_info *filter_info =
8208                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8209         struct ixgbe_5tuple_filter *node;
8210
8211         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8212                 ixgbe_inject_5tuple_filter(dev, node);
8213         }
8214 }
8215
8216 /* restore ethernet type filter */
8217 static inline void
8218 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8219 {
8220         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8221         struct ixgbe_filter_info *filter_info =
8222                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8223         int i;
8224
8225         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8226                 if (filter_info->ethertype_mask & (1 << i)) {
8227                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8228                                         filter_info->ethertype_filters[i].etqf);
8229                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8230                                         filter_info->ethertype_filters[i].etqs);
8231                         IXGBE_WRITE_FLUSH(hw);
8232                 }
8233         }
8234 }
8235
8236 /* restore SYN filter */
8237 static inline void
8238 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8239 {
8240         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8241         struct ixgbe_filter_info *filter_info =
8242                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8243         uint32_t synqf;
8244
8245         synqf = filter_info->syn_info;
8246
8247         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8248                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8249                 IXGBE_WRITE_FLUSH(hw);
8250         }
8251 }
8252
8253 /* restore L2 tunnel filter */
8254 static inline void
8255 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8256 {
8257         struct ixgbe_l2_tn_info *l2_tn_info =
8258                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8259         struct ixgbe_l2_tn_filter *node;
8260         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8261
8262         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8263                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8264                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8265                 l2_tn_conf.pool           = node->pool;
8266                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8267         }
8268 }
8269
8270 /* restore rss filter */
8271 static inline void
8272 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8273 {
8274         struct ixgbe_filter_info *filter_info =
8275                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8276
8277         if (filter_info->rss_info.num)
8278                 ixgbe_config_rss_filter(dev,
8279                         &filter_info->rss_info, TRUE);
8280 }
8281
8282 static int
8283 ixgbe_filter_restore(struct rte_eth_dev *dev)
8284 {
8285         ixgbe_ntuple_filter_restore(dev);
8286         ixgbe_ethertype_filter_restore(dev);
8287         ixgbe_syn_filter_restore(dev);
8288         ixgbe_fdir_filter_restore(dev);
8289         ixgbe_l2_tn_filter_restore(dev);
8290         ixgbe_rss_filter_restore(dev);
8291
8292         return 0;
8293 }
8294
8295 static void
8296 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8297 {
8298         struct ixgbe_l2_tn_info *l2_tn_info =
8299                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8300         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8301
8302         if (l2_tn_info->e_tag_en)
8303                 (void)ixgbe_e_tag_enable(hw);
8304
8305         if (l2_tn_info->e_tag_fwd_en)
8306                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8307
8308         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8309 }
8310
8311 /* remove all the n-tuple filters */
8312 void
8313 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8314 {
8315         struct ixgbe_filter_info *filter_info =
8316                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8317         struct ixgbe_5tuple_filter *p_5tuple;
8318
8319         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8320                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8321 }
8322
8323 /* remove all the ether type filters */
8324 void
8325 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8326 {
8327         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8328         struct ixgbe_filter_info *filter_info =
8329                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8330         int i;
8331
8332         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8333                 if (filter_info->ethertype_mask & (1 << i) &&
8334                     !filter_info->ethertype_filters[i].conf) {
8335                         (void)ixgbe_ethertype_filter_remove(filter_info,
8336                                                             (uint8_t)i);
8337                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8338                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8339                         IXGBE_WRITE_FLUSH(hw);
8340                 }
8341         }
8342 }
8343
8344 /* remove the SYN filter */
8345 void
8346 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8347 {
8348         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8349         struct ixgbe_filter_info *filter_info =
8350                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8351
8352         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8353                 filter_info->syn_info = 0;
8354
8355                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8356                 IXGBE_WRITE_FLUSH(hw);
8357         }
8358 }
8359
8360 /* remove all the L2 tunnel filters */
8361 int
8362 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8363 {
8364         struct ixgbe_l2_tn_info *l2_tn_info =
8365                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8366         struct ixgbe_l2_tn_filter *l2_tn_filter;
8367         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8368         int ret = 0;
8369
8370         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8371                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8372                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8373                 l2_tn_conf.pool           = l2_tn_filter->pool;
8374                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8375                 if (ret < 0)
8376                         return ret;
8377         }
8378
8379         return 0;
8380 }
8381
8382 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8383 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8384 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8385 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8386 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8387 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8388
8389 RTE_INIT(ixgbe_init_log);
8390 static void
8391 ixgbe_init_log(void)
8392 {
8393         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8394         if (ixgbe_logtype_init >= 0)
8395                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8396         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8397         if (ixgbe_logtype_driver >= 0)
8398                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8399 }