drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63 #include <rte_hash_crc.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "base/ixgbe_api.h"
  67 #include "base/ixgbe_vf.h"
  68 #include "base/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71 #include "ixgbe_rxtx.h"
  72 #include "base/ixgbe_type.h"
  73 #include "base/ixgbe_phy.h"
  74 #include "ixgbe_regs.h"
  75
  76 #include "rte_pmd_ixgbe.h"
  77
  78 /*
  79  * High threshold controlling when to start sending XOFF frames. Must be at
  80  * least 8 bytes less than receive packet buffer size. This value is in units
  81  * of 1024 bytes.
  82  */
  83 #define IXGBE_FC_HI    0x80
  84
  85 /*
  86  * Low threshold controlling when to start sending XON frames. This value is
  87  * in units of 1024 bytes.
  88  */
  89 #define IXGBE_FC_LO    0x40
  90
  91 /* Default minimum inter-interrupt interval for EITR configuration */
  92 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  93
  94 /* Timer value included in XOFF frames. */
  95 #define IXGBE_FC_PAUSE 0x680
  96
  97 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  98 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  99 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
 100
 101 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 102 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 103 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 104
 105 /*
 106  *  Default values for RX/TX configuration
 107  */
 108 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 109 #define IXGBE_DEFAULT_RX_PTHRESH      8
 110 #define IXGBE_DEFAULT_RX_HTHRESH      8
 111 #define IXGBE_DEFAULT_RX_WTHRESH      0
 112
 113 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 114 #define IXGBE_DEFAULT_TX_PTHRESH      32
 115 #define IXGBE_DEFAULT_TX_HTHRESH      0
 116 #define IXGBE_DEFAULT_TX_WTHRESH      0
 117 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 118
 119 /* Bit shift and mask */
 120 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 121 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 122 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 123 #define IXGBE_8_BIT_MASK   UINT8_MAX
 124
 125 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 126
 127 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 128
 129 #define IXGBE_HKEY_MAX_INDEX 10
 130
 131 /* Additional timesync values. */
 132 #define NSEC_PER_SEC             1000000000L
 133 #define IXGBE_INCVAL_10GB        0x66666666
 134 #define IXGBE_INCVAL_1GB         0x40000000
 135 #define IXGBE_INCVAL_100         0x50000000
 136 #define IXGBE_INCVAL_SHIFT_10GB  28
 137 #define IXGBE_INCVAL_SHIFT_1GB   24
 138 #define IXGBE_INCVAL_SHIFT_100   21
 139 #define IXGBE_INCVAL_SHIFT_82599 7
 140 #define IXGBE_INCPER_SHIFT_82599 24
 141
 142 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 143
 144 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 145 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 146 #define DEFAULT_ETAG_ETYPE                     0x893f
 147 #define IXGBE_ETAG_ETYPE                       0x00005084
 148 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 149 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 150 #define IXGBE_RAH_ADTYPE                       0x40000000
 151 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 152 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 153 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 154 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 155 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 156 #define IXGBE_VTEICR_MASK                      0x07
 157
 158 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 159 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 160
 161 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 162 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 163 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 164 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 165 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 166 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 167 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 168 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 169 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 171 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 172 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 177 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 178 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 179                                 int wait_to_complete);
 180 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 181                                 struct rte_eth_stats *stats);
 182 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 183                                 struct rte_eth_xstat *xstats, unsigned n);
 184 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 185                                   struct rte_eth_xstat *xstats, unsigned n);
 186 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 187 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 188 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 189         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 190 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 191         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 192 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 193                                              uint16_t queue_id,
 194                                              uint8_t stat_idx,
 195                                              uint8_t is_rx);
 196 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 197                                  size_t fw_size);
 198 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 199                                struct rte_eth_dev_info *dev_info);
 200 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 201 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 202                                  struct rte_eth_dev_info *dev_info);
 203 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 204
 205 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 206                 uint16_t vlan_id, int on);
 207 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 208                                enum rte_vlan_type vlan_type,
 209                                uint16_t tpid_id);
 210 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 211                 uint16_t queue, bool on);
 212 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 213                 int on);
 214 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 215 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 216 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 217 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 218 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 219
 220 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 221 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 222 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 223                                struct rte_eth_fc_conf *fc_conf);
 224 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 225                                struct rte_eth_fc_conf *fc_conf);
 226 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 227                 struct rte_eth_pfc_conf *pfc_conf);
 228 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 229                         struct rte_eth_rss_reta_entry64 *reta_conf,
 230                         uint16_t reta_size);
 231 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 232                         struct rte_eth_rss_reta_entry64 *reta_conf,
 233                         uint16_t reta_size);
 234 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 235 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 236 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 237 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 238 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 239 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 240                                       struct rte_intr_handle *handle);
 241 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 242                 void *param);
 243 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 244 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 245                 uint32_t index, uint32_t pool);
 246 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 247 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 248                                            struct ether_addr *mac_addr);
 249 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 250 static bool is_device_supported(struct rte_eth_dev *dev,
 251                                 struct eth_driver *drv);
 252
 253 /* For Virtual Function support */
 254 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 255 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 256 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 257 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 258 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 259 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 260 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 261 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 262 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 263                 struct rte_eth_stats *stats);
 264 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 265 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 266                 uint16_t vlan_id, int on);
 267 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 268                 uint16_t queue, int on);
 269 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 270 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 271 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 272                                             uint16_t queue_id);
 273 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 274                                              uint16_t queue_id);
 275 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 276                                  uint8_t queue, uint8_t msix_vector);
 277 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 278 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 279 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 280
 281 /* For Eth VMDQ APIs support */
 282 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 283                 ether_addr * mac_addr, uint8_t on);
 284 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 285 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 286                 struct rte_eth_mirror_conf *mirror_conf,
 287                 uint8_t rule_id, uint8_t on);
 288 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 289                 uint8_t rule_id);
 290 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 291                                           uint16_t queue_id);
 292 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 293                                            uint16_t queue_id);
 294 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 295                                uint8_t queue, uint8_t msix_vector);
 296 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 297
 298 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 299                 uint16_t queue_idx, uint16_t tx_rate);
 300
 301 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 302                                  struct ether_addr *mac_addr,
 303                                  uint32_t index, uint32_t pool);
 304 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 305 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 306                                              struct ether_addr *mac_addr);
 307 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 308                         struct rte_eth_syn_filter *filter);
 309 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 310                         enum rte_filter_op filter_op,
 311                         void *arg);
 312 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 313                         struct ixgbe_5tuple_filter *filter);
 314 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 315                         struct ixgbe_5tuple_filter *filter);
 316 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 317                                 enum rte_filter_op filter_op,
 318                                 void *arg);
 319 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 320                         struct rte_eth_ntuple_filter *filter);
 321 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 322                                 enum rte_filter_op filter_op,
 323                                 void *arg);
 324 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 325                         struct rte_eth_ethertype_filter *filter);
 326 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 327                      enum rte_filter_type filter_type,
 328                      enum rte_filter_op filter_op,
 329                      void *arg);
 330 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 331
 332 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 333                                       struct ether_addr *mc_addr_set,
 334                                       uint32_t nb_mc_addr);
 335 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 336                                    struct rte_eth_dcb_info *dcb_info);
 337
 338 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 339 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 340                             struct rte_dev_reg_info *regs);
 341 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 342 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 343                                 struct rte_dev_eeprom_info *eeprom);
 344 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 345                                 struct rte_dev_eeprom_info *eeprom);
 346
 347 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 348 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 349                                 struct rte_dev_reg_info *regs);
 350
 351 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 352 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 354                                             struct timespec *timestamp,
 355                                             uint32_t flags);
 356 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 357                                             struct timespec *timestamp);
 358 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 359 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 360                                    struct timespec *timestamp);
 361 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 362                                    const struct timespec *timestamp);
 363 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 364                                           void *param);
 365
 366 static int ixgbe_dev_l2_tunnel_eth_type_conf
 367         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 368 static int ixgbe_dev_l2_tunnel_offload_set
 369         (struct rte_eth_dev *dev,
 370          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 371          uint32_t mask,
 372          uint8_t en);
 373 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 374                                              enum rte_filter_op filter_op,
 375                                              void *arg);
 376
 377 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 380                                          struct rte_eth_udp_tunnel *udp_tunnel);
 381 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 382 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 383
 384 /*
 385  * Define VF Stats MACRO for Non "cleared on read" register
 386  */
 387 #define UPDATE_VF_STAT(reg, last, cur)                          \
 388 {                                                               \
 389         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 390         cur += (latest - last) & UINT_MAX;                      \
 391         last = latest;                                          \
 392 }
 393
 394 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 395 {                                                                \
 396         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 397         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 398         u64 latest = ((new_msb << 32) | new_lsb);                \
 399         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 400         last = latest;                                           \
 401 }
 402
 403 #define IXGBE_SET_HWSTRIP(h, q) do {\
 404                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 405                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 406                 (h)->bitmap[idx] |= 1 << bit;\
 407         } while (0)
 408
 409 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 410                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 411                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 412                 (h)->bitmap[idx] &= ~(1 << bit);\
 413         } while (0)
 414
 415 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 416                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 417                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 418                 (r) = (h)->bitmap[idx] >> bit & 1;\
 419         } while (0)
 420
 421 /*
 422  * The set of PCI devices this driver supports
 423  */
 424 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 478 #ifdef RTE_NIC_BYPASS
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 480 #endif
 481         { .vendor_id = 0, /* sentinel */ },
 482 };
 483
 484 /*
 485  * The set of PCI devices this driver supports (for 82599 VF)
 486  */
 487 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 492         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 498         { .vendor_id = 0, /* sentinel */ },
 499 };
 500
 501 static const struct rte_eth_desc_lim rx_desc_lim = {
 502         .nb_max = IXGBE_MAX_RING_DESC,
 503         .nb_min = IXGBE_MIN_RING_DESC,
 504         .nb_align = IXGBE_RXD_ALIGN,
 505 };
 506
 507 static const struct rte_eth_desc_lim tx_desc_lim = {
 508         .nb_max = IXGBE_MAX_RING_DESC,
 509         .nb_min = IXGBE_MIN_RING_DESC,
 510         .nb_align = IXGBE_TXD_ALIGN,
 511         .nb_seg_max = IXGBE_TX_MAX_SEG,
 512         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 513 };
 514
 515 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 516         .dev_configure        = ixgbe_dev_configure,
 517         .dev_start            = ixgbe_dev_start,
 518         .dev_stop             = ixgbe_dev_stop,
 519         .dev_set_link_up    = ixgbe_dev_set_link_up,
 520         .dev_set_link_down  = ixgbe_dev_set_link_down,
 521         .dev_close            = ixgbe_dev_close,
 522         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 523         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 524         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 525         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 526         .link_update          = ixgbe_dev_link_update,
 527         .stats_get            = ixgbe_dev_stats_get,
 528         .xstats_get           = ixgbe_dev_xstats_get,
 529         .stats_reset          = ixgbe_dev_stats_reset,
 530         .xstats_reset         = ixgbe_dev_xstats_reset,
 531         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 532         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 533         .fw_version_get       = ixgbe_fw_version_get,
 534         .dev_infos_get        = ixgbe_dev_info_get,
 535         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 536         .mtu_set              = ixgbe_dev_mtu_set,
 537         .vlan_filter_set      = ixgbe_vlan_filter_set,
 538         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 539         .vlan_offload_set     = ixgbe_vlan_offload_set,
 540         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 541         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 542         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 543         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 544         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 545         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 546         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 547         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 548         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 549         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 550         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 551         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 552         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 553         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 554         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 555         .dev_led_on           = ixgbe_dev_led_on,
 556         .dev_led_off          = ixgbe_dev_led_off,
 557         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 558         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 559         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 560         .mac_addr_add         = ixgbe_add_rar,
 561         .mac_addr_remove      = ixgbe_remove_rar,
 562         .mac_addr_set         = ixgbe_set_default_mac_addr,
 563         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 564         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 565         .mirror_rule_set      = ixgbe_mirror_rule_set,
 566         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 567         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 568         .reta_update          = ixgbe_dev_rss_reta_update,
 569         .reta_query           = ixgbe_dev_rss_reta_query,
 570 #ifdef RTE_NIC_BYPASS
 571         .bypass_init          = ixgbe_bypass_init,
 572         .bypass_state_set     = ixgbe_bypass_state_store,
 573         .bypass_state_show    = ixgbe_bypass_state_show,
 574         .bypass_event_set     = ixgbe_bypass_event_store,
 575         .bypass_event_show    = ixgbe_bypass_event_show,
 576         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 577         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 578         .bypass_ver_show      = ixgbe_bypass_ver_show,
 579         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 580 #endif /* RTE_NIC_BYPASS */
 581         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 582         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 583         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 584         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 585         .rxq_info_get         = ixgbe_rxq_info_get,
 586         .txq_info_get         = ixgbe_txq_info_get,
 587         .timesync_enable      = ixgbe_timesync_enable,
 588         .timesync_disable     = ixgbe_timesync_disable,
 589         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 590         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 591         .get_reg              = ixgbe_get_regs,
 592         .get_eeprom_length    = ixgbe_get_eeprom_length,
 593         .get_eeprom           = ixgbe_get_eeprom,
 594         .set_eeprom           = ixgbe_set_eeprom,
 595         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 596         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 597         .timesync_read_time   = ixgbe_timesync_read_time,
 598         .timesync_write_time  = ixgbe_timesync_write_time,
 599         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 600         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 601         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 602         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 603 };
 604
 605 /*
 606  * dev_ops for virtual function, bare necessities for basic vf
 607  * operation have been implemented
 608  */
 609 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 610         .dev_configure        = ixgbevf_dev_configure,
 611         .dev_start            = ixgbevf_dev_start,
 612         .dev_stop             = ixgbevf_dev_stop,
 613         .link_update          = ixgbe_dev_link_update,
 614         .stats_get            = ixgbevf_dev_stats_get,
 615         .xstats_get           = ixgbevf_dev_xstats_get,
 616         .stats_reset          = ixgbevf_dev_stats_reset,
 617         .xstats_reset         = ixgbevf_dev_stats_reset,
 618         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 619         .dev_close            = ixgbevf_dev_close,
 620         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 621         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 622         .dev_infos_get        = ixgbevf_dev_info_get,
 623         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 624         .mtu_set              = ixgbevf_dev_set_mtu,
 625         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 626         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 627         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 628         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 629         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 630         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 631         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 632         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 633         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 634         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 635         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 636         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 637         .mac_addr_add         = ixgbevf_add_mac_addr,
 638         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 639         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 640         .rxq_info_get         = ixgbe_rxq_info_get,
 641         .txq_info_get         = ixgbe_txq_info_get,
 642         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 643         .get_reg              = ixgbevf_get_regs,
 644         .reta_update          = ixgbe_dev_rss_reta_update,
 645         .reta_query           = ixgbe_dev_rss_reta_query,
 646         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 647         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 648 };
 649
 650 /* store statistics names and its offset in stats structure */
 651 struct rte_ixgbe_xstats_name_off {
 652         char name[RTE_ETH_XSTATS_NAME_SIZE];
 653         unsigned offset;
 654 };
 655
 656 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 657         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 658         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 659         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 660         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 661         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 662         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 663         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 664         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 665         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 666         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 667         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 668         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 669         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 670         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 671         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 672                 prc1023)},
 673         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 674                 prc1522)},
 675         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 676         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 677         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 678         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 679         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 680         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 681         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 682         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 683         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 684         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 685         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 686         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 687         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 688         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 689         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 690         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 691         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 692                 ptc1023)},
 693         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 694                 ptc1522)},
 695         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 696         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 697         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 698         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 699
 700         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 701                 fdirustat_add)},
 702         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 703                 fdirustat_remove)},
 704         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 705                 fdirfstat_fadd)},
 706         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 707                 fdirfstat_fremove)},
 708         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 709                 fdirmatch)},
 710         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 711                 fdirmiss)},
 712
 713         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 714         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 715         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 716                 fclast)},
 717         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 718         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 719         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 720         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 721         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 722                 fcoe_noddp)},
 723         {"rx_fcoe_no_direct_data_placement_ext_buff",
 724                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 725
 726         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 727                 lxontxc)},
 728         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 729                 lxonrxc)},
 730         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 731                 lxofftxc)},
 732         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 733                 lxoffrxc)},
 734         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 735 };
 736
 737 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 738                            sizeof(rte_ixgbe_stats_strings[0]))
 739
 740 /* MACsec statistics */
 741 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 742         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 743                 out_pkts_untagged)},
 744         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 745                 out_pkts_encrypted)},
 746         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 747                 out_pkts_protected)},
 748         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 749                 out_octets_encrypted)},
 750         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 751                 out_octets_protected)},
 752         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_untagged)},
 754         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 755                 in_pkts_badtag)},
 756         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 757                 in_pkts_nosci)},
 758         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 759                 in_pkts_unknownsci)},
 760         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 761                 in_octets_decrypted)},
 762         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 763                 in_octets_validated)},
 764         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 765                 in_pkts_unchecked)},
 766         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 767                 in_pkts_delayed)},
 768         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 769                 in_pkts_late)},
 770         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 771                 in_pkts_ok)},
 772         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 773                 in_pkts_invalid)},
 774         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 775                 in_pkts_notvalid)},
 776         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 777                 in_pkts_unusedsa)},
 778         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 779                 in_pkts_notusingsa)},
 780 };
 781
 782 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 783                            sizeof(rte_ixgbe_macsec_strings[0]))
 784
 785 /* Per-queue statistics */
 786 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 787         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 788         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 789         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 790         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 791 };
 792
 793 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 794                            sizeof(rte_ixgbe_rxq_strings[0]))
 795 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 796
 797 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 798         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 799         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 800         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 801                 pxon2offc)},
 802 };
 803
 804 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 805                            sizeof(rte_ixgbe_txq_strings[0]))
 806 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 807
 808 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 809         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 810 };
 811
 812 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 813                 sizeof(rte_ixgbevf_stats_strings[0]))
 814
 815 /**
 816  * Atomically reads the link status information from global
 817  * structure rte_eth_dev.
 818  *
 819  * @param dev
 820  *   - Pointer to the structure rte_eth_dev to read from.
 821  *   - Pointer to the buffer to be saved with the link status.
 822  *
 823  * @return
 824  *   - On success, zero.
 825  *   - On failure, negative value.
 826  */
 827 static inline int
 828 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 829                                 struct rte_eth_link *link)
 830 {
 831         struct rte_eth_link *dst = link;
 832         struct rte_eth_link *src = &(dev->data->dev_link);
 833
 834         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 835                                         *(uint64_t *)src) == 0)
 836                 return -1;
 837
 838         return 0;
 839 }
 840
 841 /**
 842  * Atomically writes the link status information into global
 843  * structure rte_eth_dev.
 844  *
 845  * @param dev
 846  *   - Pointer to the structure rte_eth_dev to read from.
 847  *   - Pointer to the buffer to be saved with the link status.
 848  *
 849  * @return
 850  *   - On success, zero.
 851  *   - On failure, negative value.
 852  */
 853 static inline int
 854 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 855                                 struct rte_eth_link *link)
 856 {
 857         struct rte_eth_link *dst = &(dev->data->dev_link);
 858         struct rte_eth_link *src = link;
 859
 860         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 861                                         *(uint64_t *)src) == 0)
 862                 return -1;
 863
 864         return 0;
 865 }
 866
 867 /*
 868  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 869  */
 870 static inline int
 871 ixgbe_is_sfp(struct ixgbe_hw *hw)
 872 {
 873         switch (hw->phy.type) {
 874         case ixgbe_phy_sfp_avago:
 875         case ixgbe_phy_sfp_ftl:
 876         case ixgbe_phy_sfp_intel:
 877         case ixgbe_phy_sfp_unknown:
 878         case ixgbe_phy_sfp_passive_tyco:
 879         case ixgbe_phy_sfp_passive_unknown:
 880                 return 1;
 881         default:
 882                 return 0;
 883         }
 884 }
 885
 886 static inline int32_t
 887 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 888 {
 889         uint32_t ctrl_ext;
 890         int32_t status;
 891
 892         status = ixgbe_reset_hw(hw);
 893
 894         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 895         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 896         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 897         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 898         IXGBE_WRITE_FLUSH(hw);
 899
 900         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 901                 status = IXGBE_SUCCESS;
 902         return status;
 903 }
 904
 905 static inline void
 906 ixgbe_enable_intr(struct rte_eth_dev *dev)
 907 {
 908         struct ixgbe_interrupt *intr =
 909                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 910         struct ixgbe_hw *hw =
 911                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 912
 913         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 914         IXGBE_WRITE_FLUSH(hw);
 915 }
 916
 917 /*
 918  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 919  */
 920 static void
 921 ixgbe_disable_intr(struct ixgbe_hw *hw)
 922 {
 923         PMD_INIT_FUNC_TRACE();
 924
 925         if (hw->mac.type == ixgbe_mac_82598EB) {
 926                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 927         } else {
 928                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 929                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 930                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 931         }
 932         IXGBE_WRITE_FLUSH(hw);
 933 }
 934
 935 /*
 936  * This function resets queue statistics mapping registers.
 937  * From Niantic datasheet, Initialization of Statistics section:
 938  * "...if software requires the queue counters, the RQSMR and TQSM registers
 939  * must be re-programmed following a device reset.
 940  */
 941 static void
 942 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 943 {
 944         uint32_t i;
 945
 946         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 947                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 948                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 949         }
 950 }
 951
 952
 953 static int
 954 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 955                                   uint16_t queue_id,
 956                                   uint8_t stat_idx,
 957                                   uint8_t is_rx)
 958 {
 959 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 960 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 961 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 962
 963         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 964         struct ixgbe_stat_mapping_registers *stat_mappings =
 965                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 966         uint32_t qsmr_mask = 0;
 967         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 968         uint32_t q_map;
 969         uint8_t n, offset;
 970
 971         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 972                 (hw->mac.type != ixgbe_mac_X540) &&
 973                 (hw->mac.type != ixgbe_mac_X550) &&
 974                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 975                 (hw->mac.type != ixgbe_mac_X550EM_a))
 976                 return -ENOSYS;
 977
 978         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 979                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 980                      queue_id, stat_idx);
 981
 982         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 983         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 984                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 985                 return -EIO;
 986         }
 987         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 988
 989         /* Now clear any previous stat_idx set */
 990         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 991         if (!is_rx)
 992                 stat_mappings->tqsm[n] &= ~clearing_mask;
 993         else
 994                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 995
 996         q_map = (uint32_t)stat_idx;
 997         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 998         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 999         if (!is_rx)
1000                 stat_mappings->tqsm[n] |= qsmr_mask;
1001         else
1002                 stat_mappings->rqsmr[n] |= qsmr_mask;
1003
1004         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1005                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1006                      queue_id, stat_idx);
1007         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1008                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1009
1010         /* Now write the mapping in the appropriate register */
1011         if (is_rx) {
1012                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1013                              stat_mappings->rqsmr[n], n);
1014                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1015         } else {
1016                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1017                              stat_mappings->tqsm[n], n);
1018                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1019         }
1020         return 0;
1021 }
1022
1023 static void
1024 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1025 {
1026         struct ixgbe_stat_mapping_registers *stat_mappings =
1027                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1028         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1029         int i;
1030
1031         /* write whatever was in stat mapping table to the NIC */
1032         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1033                 /* rx */
1034                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1035
1036                 /* tx */
1037                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1038         }
1039 }
1040
1041 static void
1042 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1043 {
1044         uint8_t i;
1045         struct ixgbe_dcb_tc_config *tc;
1046         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1047
1048         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1049         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1050         for (i = 0; i < dcb_max_tc; i++) {
1051                 tc = &dcb_config->tc_config[i];
1052                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1053                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1054                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1055                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1056                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1057                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1058                 tc->pfc = ixgbe_dcb_pfc_disabled;
1059         }
1060
1061         /* Initialize default user to priority mapping, UPx->TC0 */
1062         tc = &dcb_config->tc_config[0];
1063         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1064         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1065         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1066                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1067                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1068         }
1069         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1070         dcb_config->pfc_mode_enable = false;
1071         dcb_config->vt_mode = true;
1072         dcb_config->round_robin_enable = false;
1073         /* support all DCB capabilities in 82599 */
1074         dcb_config->support.capabilities = 0xFF;
1075
1076         /*we only support 4 Tcs for X540, X550 */
1077         if (hw->mac.type == ixgbe_mac_X540 ||
1078                 hw->mac.type == ixgbe_mac_X550 ||
1079                 hw->mac.type == ixgbe_mac_X550EM_x ||
1080                 hw->mac.type == ixgbe_mac_X550EM_a) {
1081                 dcb_config->num_tcs.pg_tcs = 4;
1082                 dcb_config->num_tcs.pfc_tcs = 4;
1083         }
1084 }
1085
1086 /*
1087  * Ensure that all locks are released before first NVM or PHY access
1088  */
1089 static void
1090 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1091 {
1092         uint16_t mask;
1093
1094         /*
1095          * Phy lock should not fail in this early stage. If this is the case,
1096          * it is due to an improper exit of the application.
1097          * So force the release of the faulty lock. Release of common lock
1098          * is done automatically by swfw_sync function.
1099          */
1100         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1101         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1102                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1103         }
1104         ixgbe_release_swfw_semaphore(hw, mask);
1105
1106         /*
1107          * These ones are more tricky since they are common to all ports; but
1108          * swfw_sync retries last long enough (1s) to be almost sure that if
1109          * lock can not be taken it is due to an improper lock of the
1110          * semaphore.
1111          */
1112         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1113         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1114                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1115         }
1116         ixgbe_release_swfw_semaphore(hw, mask);
1117 }
1118
1119 /*
1120  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1121  * It returns 0 on success.
1122  */
1123 static int
1124 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1125 {
1126         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1127         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1128         struct ixgbe_hw *hw =
1129                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1130         struct ixgbe_vfta *shadow_vfta =
1131                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1132         struct ixgbe_hwstrip *hwstrip =
1133                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1134         struct ixgbe_dcb_config *dcb_config =
1135                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1136         struct ixgbe_filter_info *filter_info =
1137                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1138         uint32_t ctrl_ext;
1139         uint16_t csum;
1140         int diag, i;
1141
1142         PMD_INIT_FUNC_TRACE();
1143
1144         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1145         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1146         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1147         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1148
1149         /*
1150          * For secondary processes, we don't initialise any further as primary
1151          * has already done this work. Only check we don't need a different
1152          * RX and TX function.
1153          */
1154         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1155                 struct ixgbe_tx_queue *txq;
1156                 /* TX queue function in primary, set by last queue initialized
1157                  * Tx queue may not initialized by primary process
1158                  */
1159                 if (eth_dev->data->tx_queues) {
1160                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1161                         ixgbe_set_tx_function(eth_dev, txq);
1162                 } else {
1163                         /* Use default TX function if we get here */
1164                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1165                                      "Using default TX function.");
1166                 }
1167
1168                 ixgbe_set_rx_function(eth_dev);
1169
1170                 return 0;
1171         }
1172
1173         rte_eth_copy_pci_info(eth_dev, pci_dev);
1174         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1175
1176         /* Vendor and Device ID need to be set before init of shared code */
1177         hw->device_id = pci_dev->id.device_id;
1178         hw->vendor_id = pci_dev->id.vendor_id;
1179         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1180         hw->allow_unsupported_sfp = 1;
1181
1182         /* Initialize the shared code (base driver) */
1183 #ifdef RTE_NIC_BYPASS
1184         diag = ixgbe_bypass_init_shared_code(hw);
1185 #else
1186         diag = ixgbe_init_shared_code(hw);
1187 #endif /* RTE_NIC_BYPASS */
1188
1189         if (diag != IXGBE_SUCCESS) {
1190                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1191                 return -EIO;
1192         }
1193
1194         /* pick up the PCI bus settings for reporting later */
1195         ixgbe_get_bus_info(hw);
1196
1197         /* Unlock any pending hardware semaphore */
1198         ixgbe_swfw_lock_reset(hw);
1199
1200         /* Initialize DCB configuration*/
1201         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1202         ixgbe_dcb_init(hw, dcb_config);
1203         /* Get Hardware Flow Control setting */
1204         hw->fc.requested_mode = ixgbe_fc_full;
1205         hw->fc.current_mode = ixgbe_fc_full;
1206         hw->fc.pause_time = IXGBE_FC_PAUSE;
1207         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1208                 hw->fc.low_water[i] = IXGBE_FC_LO;
1209                 hw->fc.high_water[i] = IXGBE_FC_HI;
1210         }
1211         hw->fc.send_xon = 1;
1212
1213         /* Make sure we have a good EEPROM before we read from it */
1214         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1215         if (diag != IXGBE_SUCCESS) {
1216                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1217                 return -EIO;
1218         }
1219
1220 #ifdef RTE_NIC_BYPASS
1221         diag = ixgbe_bypass_init_hw(hw);
1222 #else
1223         diag = ixgbe_init_hw(hw);
1224 #endif /* RTE_NIC_BYPASS */
1225
1226         /*
1227          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1228          * is called too soon after the kernel driver unbinding/binding occurs.
1229          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1230          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1231          * also called. See ixgbe_identify_phy_82599(). The reason for the
1232          * failure is not known, and only occuts when virtualisation features
1233          * are disabled in the bios. A delay of 100ms  was found to be enough by
1234          * trial-and-error, and is doubled to be safe.
1235          */
1236         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1237                 rte_delay_ms(200);
1238                 diag = ixgbe_init_hw(hw);
1239         }
1240
1241         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1242                 diag = IXGBE_SUCCESS;
1243
1244         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1245                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1246                              "LOM.  Please be aware there may be issues associated "
1247                              "with your hardware.");
1248                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1249                              "please contact your Intel or hardware representative "
1250                              "who provided you with this hardware.");
1251         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1252                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1253         if (diag) {
1254                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1255                 return -EIO;
1256         }
1257
1258         /* Reset the hw statistics */
1259         ixgbe_dev_stats_reset(eth_dev);
1260
1261         /* disable interrupt */
1262         ixgbe_disable_intr(hw);
1263
1264         /* reset mappings for queue statistics hw counters*/
1265         ixgbe_reset_qstat_mappings(hw);
1266
1267         /* Allocate memory for storing MAC addresses */
1268         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1269                                                hw->mac.num_rar_entries, 0);
1270         if (eth_dev->data->mac_addrs == NULL) {
1271                 PMD_INIT_LOG(ERR,
1272                              "Failed to allocate %u bytes needed to store "
1273                              "MAC addresses",
1274                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1275                 return -ENOMEM;
1276         }
1277         /* Copy the permanent MAC address */
1278         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1279                         &eth_dev->data->mac_addrs[0]);
1280
1281         /* Allocate memory for storing hash filter MAC addresses */
1282         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1283                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1284         if (eth_dev->data->hash_mac_addrs == NULL) {
1285                 PMD_INIT_LOG(ERR,
1286                              "Failed to allocate %d bytes needed to store MAC addresses",
1287                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1288                 return -ENOMEM;
1289         }
1290
1291         /* initialize the vfta */
1292         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1293
1294         /* initialize the hw strip bitmap*/
1295         memset(hwstrip, 0, sizeof(*hwstrip));
1296
1297         /* initialize PF if max_vfs not zero */
1298         ixgbe_pf_host_init(eth_dev);
1299
1300         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1301         /* let hardware know driver is loaded */
1302         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1303         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1304         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1305         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1306         IXGBE_WRITE_FLUSH(hw);
1307
1308         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1309                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1310                              (int) hw->mac.type, (int) hw->phy.type,
1311                              (int) hw->phy.sfp_type);
1312         else
1313                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1314                              (int) hw->mac.type, (int) hw->phy.type);
1315
1316         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1317                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1318                      pci_dev->id.device_id);
1319
1320         rte_intr_callback_register(intr_handle,
1321                                    ixgbe_dev_interrupt_handler, eth_dev);
1322
1323         /* enable uio/vfio intr/eventfd mapping */
1324         rte_intr_enable(intr_handle);
1325
1326         /* enable support intr */
1327         ixgbe_enable_intr(eth_dev);
1328
1329         /* initialize filter info */
1330         memset(filter_info, 0,
1331                sizeof(struct ixgbe_filter_info));
1332
1333         /* initialize 5tuple filter list */
1334         TAILQ_INIT(&filter_info->fivetuple_list);
1335
1336         /* initialize flow director filter list & hash */
1337         ixgbe_fdir_filter_init(eth_dev);
1338
1339         /* initialize l2 tunnel filter list & hash */
1340         ixgbe_l2_tn_filter_init(eth_dev);
1341
1342         TAILQ_INIT(&filter_ntuple_list);
1343         TAILQ_INIT(&filter_ethertype_list);
1344         TAILQ_INIT(&filter_syn_list);
1345         TAILQ_INIT(&filter_fdir_list);
1346         TAILQ_INIT(&filter_l2_tunnel_list);
1347         TAILQ_INIT(&ixgbe_flow_list);
1348
1349         return 0;
1350 }
1351
1352 static int
1353 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1354 {
1355         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1356         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1357         struct ixgbe_hw *hw;
1358
1359         PMD_INIT_FUNC_TRACE();
1360
1361         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1362                 return -EPERM;
1363
1364         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1365
1366         if (hw->adapter_stopped == 0)
1367                 ixgbe_dev_close(eth_dev);
1368
1369         eth_dev->dev_ops = NULL;
1370         eth_dev->rx_pkt_burst = NULL;
1371         eth_dev->tx_pkt_burst = NULL;
1372
1373         /* Unlock any pending hardware semaphore */
1374         ixgbe_swfw_lock_reset(hw);
1375
1376         /* disable uio intr before callback unregister */
1377         rte_intr_disable(intr_handle);
1378         rte_intr_callback_unregister(intr_handle,
1379                                      ixgbe_dev_interrupt_handler, eth_dev);
1380
1381         /* uninitialize PF if max_vfs not zero */
1382         ixgbe_pf_host_uninit(eth_dev);
1383
1384         rte_free(eth_dev->data->mac_addrs);
1385         eth_dev->data->mac_addrs = NULL;
1386
1387         rte_free(eth_dev->data->hash_mac_addrs);
1388         eth_dev->data->hash_mac_addrs = NULL;
1389
1390         /* remove all the fdir filters & hash */
1391         ixgbe_fdir_filter_uninit(eth_dev);
1392
1393         /* remove all the L2 tunnel filters & hash */
1394         ixgbe_l2_tn_filter_uninit(eth_dev);
1395
1396         /* Remove all ntuple filters of the device */
1397         ixgbe_ntuple_filter_uninit(eth_dev);
1398
1399         /* clear all the filters list */
1400         ixgbe_filterlist_flush();
1401
1402         return 0;
1403 }
1404
1405 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1406 {
1407         struct ixgbe_filter_info *filter_info =
1408                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1409         struct ixgbe_5tuple_filter *p_5tuple;
1410
1411         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1412                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1413                              p_5tuple,
1414                              entries);
1415                 rte_free(p_5tuple);
1416         }
1417         memset(filter_info->fivetuple_mask, 0,
1418                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1419
1420         return 0;
1421 }
1422
1423 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1424 {
1425         struct ixgbe_hw_fdir_info *fdir_info =
1426                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1427         struct ixgbe_fdir_filter *fdir_filter;
1428
1429                 if (fdir_info->hash_map)
1430                 rte_free(fdir_info->hash_map);
1431         if (fdir_info->hash_handle)
1432                 rte_hash_free(fdir_info->hash_handle);
1433
1434         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1435                 TAILQ_REMOVE(&fdir_info->fdir_list,
1436                              fdir_filter,
1437                              entries);
1438                 rte_free(fdir_filter);
1439         }
1440
1441         return 0;
1442 }
1443
1444 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1445 {
1446         struct ixgbe_l2_tn_info *l2_tn_info =
1447                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1448         struct ixgbe_l2_tn_filter *l2_tn_filter;
1449
1450         if (l2_tn_info->hash_map)
1451                 rte_free(l2_tn_info->hash_map);
1452         if (l2_tn_info->hash_handle)
1453                 rte_hash_free(l2_tn_info->hash_handle);
1454
1455         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1456                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1457                              l2_tn_filter,
1458                              entries);
1459                 rte_free(l2_tn_filter);
1460         }
1461
1462         return 0;
1463 }
1464
1465 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1466 {
1467         struct ixgbe_hw_fdir_info *fdir_info =
1468                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1469         char fdir_hash_name[RTE_HASH_NAMESIZE];
1470         struct rte_hash_parameters fdir_hash_params = {
1471                 .name = fdir_hash_name,
1472                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1473                 .key_len = sizeof(union ixgbe_atr_input),
1474                 .hash_func = rte_hash_crc,
1475                 .hash_func_init_val = 0,
1476                 .socket_id = rte_socket_id(),
1477         };
1478
1479         TAILQ_INIT(&fdir_info->fdir_list);
1480         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1481                  "fdir_%s", eth_dev->data->name);
1482         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1483         if (!fdir_info->hash_handle) {
1484                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1485                 return -EINVAL;
1486         }
1487         fdir_info->hash_map = rte_zmalloc("ixgbe",
1488                                           sizeof(struct ixgbe_fdir_filter *) *
1489                                           IXGBE_MAX_FDIR_FILTER_NUM,
1490                                           0);
1491         if (!fdir_info->hash_map) {
1492                 PMD_INIT_LOG(ERR,
1493                              "Failed to allocate memory for fdir hash map!");
1494                 return -ENOMEM;
1495         }
1496         fdir_info->mask_added = FALSE;
1497
1498         return 0;
1499 }
1500
1501 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1502 {
1503         struct ixgbe_l2_tn_info *l2_tn_info =
1504                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1505         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1506         struct rte_hash_parameters l2_tn_hash_params = {
1507                 .name = l2_tn_hash_name,
1508                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1509                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1510                 .hash_func = rte_hash_crc,
1511                 .hash_func_init_val = 0,
1512                 .socket_id = rte_socket_id(),
1513         };
1514
1515         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1516         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1517                  "l2_tn_%s", eth_dev->data->name);
1518         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1519         if (!l2_tn_info->hash_handle) {
1520                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1521                 return -EINVAL;
1522         }
1523         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1524                                    sizeof(struct ixgbe_l2_tn_filter *) *
1525                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1526                                    0);
1527         if (!l2_tn_info->hash_map) {
1528                 PMD_INIT_LOG(ERR,
1529                         "Failed to allocate memory for L2 TN hash map!");
1530                 return -ENOMEM;
1531         }
1532         l2_tn_info->e_tag_en = FALSE;
1533         l2_tn_info->e_tag_fwd_en = FALSE;
1534         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1535
1536         return 0;
1537 }
1538 /*
1539  * Negotiate mailbox API version with the PF.
1540  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1541  * Then we try to negotiate starting with the most recent one.
1542  * If all negotiation attempts fail, then we will proceed with
1543  * the default one (ixgbe_mbox_api_10).
1544  */
1545 static void
1546 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1547 {
1548         int32_t i;
1549
1550         /* start with highest supported, proceed down */
1551         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1552                 ixgbe_mbox_api_12,
1553                 ixgbe_mbox_api_11,
1554                 ixgbe_mbox_api_10,
1555         };
1556
1557         for (i = 0;
1558                         i != RTE_DIM(sup_ver) &&
1559                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1560                         i++)
1561                 ;
1562 }
1563
1564 static void
1565 generate_random_mac_addr(struct ether_addr *mac_addr)
1566 {
1567         uint64_t random;
1568
1569         /* Set Organizationally Unique Identifier (OUI) prefix. */
1570         mac_addr->addr_bytes[0] = 0x00;
1571         mac_addr->addr_bytes[1] = 0x09;
1572         mac_addr->addr_bytes[2] = 0xC0;
1573         /* Force indication of locally assigned MAC address. */
1574         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1575         /* Generate the last 3 bytes of the MAC address with a random number. */
1576         random = rte_rand();
1577         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1578 }
1579
1580 /*
1581  * Virtual Function device init
1582  */
1583 static int
1584 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1585 {
1586         int diag;
1587         uint32_t tc, tcs;
1588         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1589         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1590         struct ixgbe_hw *hw =
1591                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1592         struct ixgbe_vfta *shadow_vfta =
1593                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1594         struct ixgbe_hwstrip *hwstrip =
1595                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1596         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1597
1598         PMD_INIT_FUNC_TRACE();
1599
1600         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1601         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1602         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1603
1604         /* for secondary processes, we don't initialise any further as primary
1605          * has already done this work. Only check we don't need a different
1606          * RX function
1607          */
1608         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1609                 struct ixgbe_tx_queue *txq;
1610                 /* TX queue function in primary, set by last queue initialized
1611                  * Tx queue may not initialized by primary process
1612                  */
1613                 if (eth_dev->data->tx_queues) {
1614                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1615                         ixgbe_set_tx_function(eth_dev, txq);
1616                 } else {
1617                         /* Use default TX function if we get here */
1618                         PMD_INIT_LOG(NOTICE,
1619                                      "No TX queues configured yet. Using default TX function.");
1620                 }
1621
1622                 ixgbe_set_rx_function(eth_dev);
1623
1624                 return 0;
1625         }
1626
1627         rte_eth_copy_pci_info(eth_dev, pci_dev);
1628         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1629
1630         hw->device_id = pci_dev->id.device_id;
1631         hw->vendor_id = pci_dev->id.vendor_id;
1632         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1633
1634         /* initialize the vfta */
1635         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1636
1637         /* initialize the hw strip bitmap*/
1638         memset(hwstrip, 0, sizeof(*hwstrip));
1639
1640         /* Initialize the shared code (base driver) */
1641         diag = ixgbe_init_shared_code(hw);
1642         if (diag != IXGBE_SUCCESS) {
1643                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1644                 return -EIO;
1645         }
1646
1647         /* init_mailbox_params */
1648         hw->mbx.ops.init_params(hw);
1649
1650         /* Reset the hw statistics */
1651         ixgbevf_dev_stats_reset(eth_dev);
1652
1653         /* Disable the interrupts for VF */
1654         ixgbevf_intr_disable(hw);
1655
1656         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1657         diag = hw->mac.ops.reset_hw(hw);
1658
1659         /*
1660          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1661          * the underlying PF driver has not assigned a MAC address to the VF.
1662          * In this case, assign a random MAC address.
1663          */
1664         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1665                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1666                 return diag;
1667         }
1668
1669         /* negotiate mailbox API version to use with the PF. */
1670         ixgbevf_negotiate_api(hw);
1671
1672         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1673         ixgbevf_get_queues(hw, &tcs, &tc);
1674
1675         /* Allocate memory for storing MAC addresses */
1676         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1677                                                hw->mac.num_rar_entries, 0);
1678         if (eth_dev->data->mac_addrs == NULL) {
1679                 PMD_INIT_LOG(ERR,
1680                              "Failed to allocate %u bytes needed to store "
1681                              "MAC addresses",
1682                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1683                 return -ENOMEM;
1684         }
1685
1686         /* Generate a random MAC address, if none was assigned by PF. */
1687         if (is_zero_ether_addr(perm_addr)) {
1688                 generate_random_mac_addr(perm_addr);
1689                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1690                 if (diag) {
1691                         rte_free(eth_dev->data->mac_addrs);
1692                         eth_dev->data->mac_addrs = NULL;
1693                         return diag;
1694                 }
1695                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1696                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1697                              "%02x:%02x:%02x:%02x:%02x:%02x",
1698                              perm_addr->addr_bytes[0],
1699                              perm_addr->addr_bytes[1],
1700                              perm_addr->addr_bytes[2],
1701                              perm_addr->addr_bytes[3],
1702                              perm_addr->addr_bytes[4],
1703                              perm_addr->addr_bytes[5]);
1704         }
1705
1706         /* Copy the permanent MAC address */
1707         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1708
1709         /* reset the hardware with the new settings */
1710         diag = hw->mac.ops.start_hw(hw);
1711         switch (diag) {
1712         case  0:
1713                 break;
1714
1715         default:
1716                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1717                 return -EIO;
1718         }
1719
1720         rte_intr_callback_register(intr_handle,
1721                                    ixgbevf_dev_interrupt_handler, eth_dev);
1722         rte_intr_enable(intr_handle);
1723         ixgbevf_intr_enable(hw);
1724
1725         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1726                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1727                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1728
1729         return 0;
1730 }
1731
1732 /* Virtual Function device uninit */
1733
1734 static int
1735 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1736 {
1737         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1738         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1739         struct ixgbe_hw *hw;
1740
1741         PMD_INIT_FUNC_TRACE();
1742
1743         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1744                 return -EPERM;
1745
1746         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1747
1748         if (hw->adapter_stopped == 0)
1749                 ixgbevf_dev_close(eth_dev);
1750
1751         eth_dev->dev_ops = NULL;
1752         eth_dev->rx_pkt_burst = NULL;
1753         eth_dev->tx_pkt_burst = NULL;
1754
1755         /* Disable the interrupts for VF */
1756         ixgbevf_intr_disable(hw);
1757
1758         rte_free(eth_dev->data->mac_addrs);
1759         eth_dev->data->mac_addrs = NULL;
1760
1761         rte_intr_disable(intr_handle);
1762         rte_intr_callback_unregister(intr_handle,
1763                                      ixgbevf_dev_interrupt_handler, eth_dev);
1764
1765         return 0;
1766 }
1767
1768 static struct eth_driver rte_ixgbe_pmd = {
1769         .pci_drv = {
1770                 .id_table = pci_id_ixgbe_map,
1771                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1772                 .probe = rte_eth_dev_pci_probe,
1773                 .remove = rte_eth_dev_pci_remove,
1774         },
1775         .eth_dev_init = eth_ixgbe_dev_init,
1776         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1777         .dev_private_size = sizeof(struct ixgbe_adapter),
1778 };
1779
1780 /*
1781  * virtual function driver struct
1782  */
1783 static struct eth_driver rte_ixgbevf_pmd = {
1784         .pci_drv = {
1785                 .id_table = pci_id_ixgbevf_map,
1786                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1787                 .probe = rte_eth_dev_pci_probe,
1788                 .remove = rte_eth_dev_pci_remove,
1789         },
1790         .eth_dev_init = eth_ixgbevf_dev_init,
1791         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1792         .dev_private_size = sizeof(struct ixgbe_adapter),
1793 };
1794
1795 static int
1796 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1797 {
1798         struct ixgbe_hw *hw =
1799                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1800         struct ixgbe_vfta *shadow_vfta =
1801                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1802         uint32_t vfta;
1803         uint32_t vid_idx;
1804         uint32_t vid_bit;
1805
1806         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1807         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1808         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1809         if (on)
1810                 vfta |= vid_bit;
1811         else
1812                 vfta &= ~vid_bit;
1813         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1814
1815         /* update local VFTA copy */
1816         shadow_vfta->vfta[vid_idx] = vfta;
1817
1818         return 0;
1819 }
1820
1821 static void
1822 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1823 {
1824         if (on)
1825                 ixgbe_vlan_hw_strip_enable(dev, queue);
1826         else
1827                 ixgbe_vlan_hw_strip_disable(dev, queue);
1828 }
1829
1830 static int
1831 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1832                     enum rte_vlan_type vlan_type,
1833                     uint16_t tpid)
1834 {
1835         struct ixgbe_hw *hw =
1836                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1837         int ret = 0;
1838         uint32_t reg;
1839         uint32_t qinq;
1840
1841         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1842         qinq &= IXGBE_DMATXCTL_GDV;
1843
1844         switch (vlan_type) {
1845         case ETH_VLAN_TYPE_INNER:
1846                 if (qinq) {
1847                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1848                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1849                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1850                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1851                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1852                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1853                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1854                 } else {
1855                         ret = -ENOTSUP;
1856                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1857                                     " by single VLAN");
1858                 }
1859                 break;
1860         case ETH_VLAN_TYPE_OUTER:
1861                 if (qinq) {
1862                         /* Only the high 16-bits is valid */
1863                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1864                                         IXGBE_EXVET_VET_EXT_SHIFT);
1865                 } else {
1866                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1867                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1868                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1869                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1870                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1871                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1872                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1873                 }
1874
1875                 break;
1876         default:
1877                 ret = -EINVAL;
1878                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1879                 break;
1880         }
1881
1882         return ret;
1883 }
1884
1885 void
1886 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1887 {
1888         struct ixgbe_hw *hw =
1889                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1890         uint32_t vlnctrl;
1891
1892         PMD_INIT_FUNC_TRACE();
1893
1894         /* Filter Table Disable */
1895         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1896         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1897
1898         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1899 }
1900
1901 void
1902 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1903 {
1904         struct ixgbe_hw *hw =
1905                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1906         struct ixgbe_vfta *shadow_vfta =
1907                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1908         uint32_t vlnctrl;
1909         uint16_t i;
1910
1911         PMD_INIT_FUNC_TRACE();
1912
1913         /* Filter Table Enable */
1914         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1915         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1916         vlnctrl |= IXGBE_VLNCTRL_VFE;
1917
1918         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1919
1920         /* write whatever is in local vfta copy */
1921         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1922                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1923 }
1924
1925 static void
1926 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1927 {
1928         struct ixgbe_hwstrip *hwstrip =
1929                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1930         struct ixgbe_rx_queue *rxq;
1931
1932         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1933                 return;
1934
1935         if (on)
1936                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1937         else
1938                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1939
1940         if (queue >= dev->data->nb_rx_queues)
1941                 return;
1942
1943         rxq = dev->data->rx_queues[queue];
1944
1945         if (on)
1946                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1947         else
1948                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1949 }
1950
1951 static void
1952 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1953 {
1954         struct ixgbe_hw *hw =
1955                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1956         uint32_t ctrl;
1957
1958         PMD_INIT_FUNC_TRACE();
1959
1960         if (hw->mac.type == ixgbe_mac_82598EB) {
1961                 /* No queue level support */
1962                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1963                 return;
1964         }
1965
1966         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1967         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1968         ctrl &= ~IXGBE_RXDCTL_VME;
1969         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1970
1971         /* record those setting for HW strip per queue */
1972         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1973 }
1974
1975 static void
1976 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1977 {
1978         struct ixgbe_hw *hw =
1979                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1980         uint32_t ctrl;
1981
1982         PMD_INIT_FUNC_TRACE();
1983
1984         if (hw->mac.type == ixgbe_mac_82598EB) {
1985                 /* No queue level supported */
1986                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1987                 return;
1988         }
1989
1990         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1991         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1992         ctrl |= IXGBE_RXDCTL_VME;
1993         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1994
1995         /* record those setting for HW strip per queue */
1996         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1997 }
1998
1999 void
2000 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2001 {
2002         struct ixgbe_hw *hw =
2003                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2004         uint32_t ctrl;
2005         uint16_t i;
2006         struct ixgbe_rx_queue *rxq;
2007
2008         PMD_INIT_FUNC_TRACE();
2009
2010         if (hw->mac.type == ixgbe_mac_82598EB) {
2011                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2012                 ctrl &= ~IXGBE_VLNCTRL_VME;
2013                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2014         } else {
2015                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2016                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2017                         rxq = dev->data->rx_queues[i];
2018                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2019                         ctrl &= ~IXGBE_RXDCTL_VME;
2020                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2021
2022                         /* record those setting for HW strip per queue */
2023                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2024                 }
2025         }
2026 }
2027
2028 void
2029 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2030 {
2031         struct ixgbe_hw *hw =
2032                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2033         uint32_t ctrl;
2034         uint16_t i;
2035         struct ixgbe_rx_queue *rxq;
2036
2037         PMD_INIT_FUNC_TRACE();
2038
2039         if (hw->mac.type == ixgbe_mac_82598EB) {
2040                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2041                 ctrl |= IXGBE_VLNCTRL_VME;
2042                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2043         } else {
2044                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2045                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2046                         rxq = dev->data->rx_queues[i];
2047                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2048                         ctrl |= IXGBE_RXDCTL_VME;
2049                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2050
2051                         /* record those setting for HW strip per queue */
2052                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2053                 }
2054         }
2055 }
2056
2057 static void
2058 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2059 {
2060         struct ixgbe_hw *hw =
2061                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2062         uint32_t ctrl;
2063
2064         PMD_INIT_FUNC_TRACE();
2065
2066         /* DMATXCTRL: Geric Double VLAN Disable */
2067         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2068         ctrl &= ~IXGBE_DMATXCTL_GDV;
2069         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2070
2071         /* CTRL_EXT: Global Double VLAN Disable */
2072         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2073         ctrl &= ~IXGBE_EXTENDED_VLAN;
2074         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2075
2076 }
2077
2078 static void
2079 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2080 {
2081         struct ixgbe_hw *hw =
2082                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2083         uint32_t ctrl;
2084
2085         PMD_INIT_FUNC_TRACE();
2086
2087         /* DMATXCTRL: Geric Double VLAN Enable */
2088         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2089         ctrl |= IXGBE_DMATXCTL_GDV;
2090         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2091
2092         /* CTRL_EXT: Global Double VLAN Enable */
2093         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2094         ctrl |= IXGBE_EXTENDED_VLAN;
2095         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2096
2097         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2098         if (hw->mac.type == ixgbe_mac_X550 ||
2099             hw->mac.type == ixgbe_mac_X550EM_x ||
2100             hw->mac.type == ixgbe_mac_X550EM_a) {
2101                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2102                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2103                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2104         }
2105
2106         /*
2107          * VET EXT field in the EXVET register = 0x8100 by default
2108          * So no need to change. Same to VT field of DMATXCTL register
2109          */
2110 }
2111
2112 static void
2113 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2114 {
2115         if (mask & ETH_VLAN_STRIP_MASK) {
2116                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2117                         ixgbe_vlan_hw_strip_enable_all(dev);
2118                 else
2119                         ixgbe_vlan_hw_strip_disable_all(dev);
2120         }
2121
2122         if (mask & ETH_VLAN_FILTER_MASK) {
2123                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2124                         ixgbe_vlan_hw_filter_enable(dev);
2125                 else
2126                         ixgbe_vlan_hw_filter_disable(dev);
2127         }
2128
2129         if (mask & ETH_VLAN_EXTEND_MASK) {
2130                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2131                         ixgbe_vlan_hw_extend_enable(dev);
2132                 else
2133                         ixgbe_vlan_hw_extend_disable(dev);
2134         }
2135 }
2136
2137 static void
2138 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2139 {
2140         struct ixgbe_hw *hw =
2141                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2142         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2143         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2144
2145         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2146         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2147 }
2148
2149 static int
2150 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2151 {
2152         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2153
2154         switch (nb_rx_q) {
2155         case 1:
2156         case 2:
2157                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2158                 break;
2159         case 4:
2160                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2161                 break;
2162         default:
2163                 return -EINVAL;
2164         }
2165
2166         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2167         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2168
2169         return 0;
2170 }
2171
2172 static int
2173 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2174 {
2175         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2176         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2177         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2178         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2179
2180         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2181                 /* check multi-queue mode */
2182                 switch (dev_conf->rxmode.mq_mode) {
2183                 case ETH_MQ_RX_VMDQ_DCB:
2184                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2185                         break;
2186                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2187                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2188                         PMD_INIT_LOG(ERR, "SRIOV active,"
2189                                         " unsupported mq_mode rx %d.",
2190                                         dev_conf->rxmode.mq_mode);
2191                         return -EINVAL;
2192                 case ETH_MQ_RX_RSS:
2193                 case ETH_MQ_RX_VMDQ_RSS:
2194                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2195                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2196                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2197                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2198                                                 " invalid queue number"
2199                                                 " for VMDQ RSS, allowed"
2200                                                 " value are 1, 2 or 4.");
2201                                         return -EINVAL;
2202                                 }
2203                         break;
2204                 case ETH_MQ_RX_VMDQ_ONLY:
2205                 case ETH_MQ_RX_NONE:
2206                         /* if nothing mq mode configure, use default scheme */
2207                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2208                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2209                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2210                         break;
2211                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2212                         /* SRIOV only works in VMDq enable mode */
2213                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2214                                         " wrong mq_mode rx %d.",
2215                                         dev_conf->rxmode.mq_mode);
2216                         return -EINVAL;
2217                 }
2218
2219                 switch (dev_conf->txmode.mq_mode) {
2220                 case ETH_MQ_TX_VMDQ_DCB:
2221                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2222                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2223                         break;
2224                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2225                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2226                         break;
2227                 }
2228
2229                 /* check valid queue number */
2230                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2231                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2232                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2233                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2234                                         " must be less than or equal to %d.",
2235                                         nb_rx_q, nb_tx_q,
2236                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2237                         return -EINVAL;
2238                 }
2239         } else {
2240                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2241                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2242                                           " not supported.");
2243                         return -EINVAL;
2244                 }
2245                 /* check configuration for vmdb+dcb mode */
2246                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2247                         const struct rte_eth_vmdq_dcb_conf *conf;
2248
2249                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2250                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2251                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2252                                 return -EINVAL;
2253                         }
2254                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2255                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2256                                conf->nb_queue_pools == ETH_32_POOLS)) {
2257                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2258                                                 " nb_queue_pools must be %d or %d.",
2259                                                 ETH_16_POOLS, ETH_32_POOLS);
2260                                 return -EINVAL;
2261                         }
2262                 }
2263                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2264                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2265
2266                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2267                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2268                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2269                                 return -EINVAL;
2270                         }
2271                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2272                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2273                                conf->nb_queue_pools == ETH_32_POOLS)) {
2274                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2275                                                 " nb_queue_pools != %d and"
2276                                                 " nb_queue_pools != %d.",
2277                                                 ETH_16_POOLS, ETH_32_POOLS);
2278                                 return -EINVAL;
2279                         }
2280                 }
2281
2282                 /* For DCB mode check our configuration before we go further */
2283                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2284                         const struct rte_eth_dcb_rx_conf *conf;
2285
2286                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2287                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2288                                                  IXGBE_DCB_NB_QUEUES);
2289                                 return -EINVAL;
2290                         }
2291                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2292                         if (!(conf->nb_tcs == ETH_4_TCS ||
2293                                conf->nb_tcs == ETH_8_TCS)) {
2294                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2295                                                 " and nb_tcs != %d.",
2296                                                 ETH_4_TCS, ETH_8_TCS);
2297                                 return -EINVAL;
2298                         }
2299                 }
2300
2301                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2302                         const struct rte_eth_dcb_tx_conf *conf;
2303
2304                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2305                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2306                                                  IXGBE_DCB_NB_QUEUES);
2307                                 return -EINVAL;
2308                         }
2309                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2310                         if (!(conf->nb_tcs == ETH_4_TCS ||
2311                                conf->nb_tcs == ETH_8_TCS)) {
2312                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2313                                                 " and nb_tcs != %d.",
2314                                                 ETH_4_TCS, ETH_8_TCS);
2315                                 return -EINVAL;
2316                         }
2317                 }
2318
2319                 /*
2320                  * When DCB/VT is off, maximum number of queues changes,
2321                  * except for 82598EB, which remains constant.
2322                  */
2323                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2324                                 hw->mac.type != ixgbe_mac_82598EB) {
2325                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2326                                 PMD_INIT_LOG(ERR,
2327                                              "Neither VT nor DCB are enabled, "
2328                                              "nb_tx_q > %d.",
2329                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2330                                 return -EINVAL;
2331                         }
2332                 }
2333         }
2334         return 0;
2335 }
2336
2337 static int
2338 ixgbe_dev_configure(struct rte_eth_dev *dev)
2339 {
2340         struct ixgbe_interrupt *intr =
2341                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2342         struct ixgbe_adapter *adapter =
2343                 (struct ixgbe_adapter *)dev->data->dev_private;
2344         int ret;
2345
2346         PMD_INIT_FUNC_TRACE();
2347         /* multipe queue mode checking */
2348         ret  = ixgbe_check_mq_mode(dev);
2349         if (ret != 0) {
2350                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2351                             ret);
2352                 return ret;
2353         }
2354
2355         /* set flag to update link status after init */
2356         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2357
2358         /*
2359          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2360          * allocation or vector Rx preconditions we will reset it.
2361          */
2362         adapter->rx_bulk_alloc_allowed = true;
2363         adapter->rx_vec_allowed = true;
2364
2365         return 0;
2366 }
2367
2368 static void
2369 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2370 {
2371         struct ixgbe_hw *hw =
2372                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2373         struct ixgbe_interrupt *intr =
2374                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2375         uint32_t gpie;
2376
2377         /* only set up it on X550EM_X */
2378         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2379                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2380                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2381                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2382                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2383                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2384         }
2385 }
2386
2387 /*
2388  * Configure device link speed and setup link.
2389  * It returns 0 on success.
2390  */
2391 static int
2392 ixgbe_dev_start(struct rte_eth_dev *dev)
2393 {
2394         struct ixgbe_hw *hw =
2395                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2396         struct ixgbe_vf_info *vfinfo =
2397                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2398         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2399         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2400         uint32_t intr_vector = 0;
2401         int err, link_up = 0, negotiate = 0;
2402         uint32_t speed = 0;
2403         int mask = 0;
2404         int status;
2405         uint16_t vf, idx;
2406         uint32_t *link_speeds;
2407
2408         PMD_INIT_FUNC_TRACE();
2409
2410         /* IXGBE devices don't support:
2411         *    - half duplex (checked afterwards for valid speeds)
2412         *    - fixed speed: TODO implement
2413         */
2414         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2415                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2416                              dev->data->port_id);
2417                 return -EINVAL;
2418         }
2419
2420         /* disable uio/vfio intr/eventfd mapping */
2421         rte_intr_disable(intr_handle);
2422
2423         /* stop adapter */
2424         hw->adapter_stopped = 0;
2425         ixgbe_stop_adapter(hw);
2426
2427         /* reinitialize adapter
2428          * this calls reset and start
2429          */
2430         status = ixgbe_pf_reset_hw(hw);
2431         if (status != 0)
2432                 return -1;
2433         hw->mac.ops.start_hw(hw);
2434         hw->mac.get_link_status = true;
2435
2436         /* configure PF module if SRIOV enabled */
2437         ixgbe_pf_host_configure(dev);
2438
2439         ixgbe_dev_phy_intr_setup(dev);
2440
2441         /* check and configure queue intr-vector mapping */
2442         if ((rte_intr_cap_multiple(intr_handle) ||
2443              !RTE_ETH_DEV_SRIOV(dev).active) &&
2444             dev->data->dev_conf.intr_conf.rxq != 0) {
2445                 intr_vector = dev->data->nb_rx_queues;
2446                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2447                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2448                                         IXGBE_MAX_INTR_QUEUE_NUM);
2449                         return -ENOTSUP;
2450                 }
2451                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2452                         return -1;
2453         }
2454
2455         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2456                 intr_handle->intr_vec =
2457                         rte_zmalloc("intr_vec",
2458                                     dev->data->nb_rx_queues * sizeof(int), 0);
2459                 if (intr_handle->intr_vec == NULL) {
2460                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2461                                      " intr_vec", dev->data->nb_rx_queues);
2462                         return -ENOMEM;
2463                 }
2464         }
2465
2466         /* confiugre msix for sleep until rx interrupt */
2467         ixgbe_configure_msix(dev);
2468
2469         /* initialize transmission unit */
2470         ixgbe_dev_tx_init(dev);
2471
2472         /* This can fail when allocating mbufs for descriptor rings */
2473         err = ixgbe_dev_rx_init(dev);
2474         if (err) {
2475                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2476                 goto error;
2477         }
2478
2479     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2480                 ETH_VLAN_EXTEND_MASK;
2481         ixgbe_vlan_offload_set(dev, mask);
2482
2483         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2484                 /* Enable vlan filtering for VMDq */
2485                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2486         }
2487
2488         /* Configure DCB hw */
2489         ixgbe_configure_dcb(dev);
2490
2491         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2492                 err = ixgbe_fdir_configure(dev);
2493                 if (err)
2494                         goto error;
2495         }
2496
2497         /* Restore vf rate limit */
2498         if (vfinfo != NULL) {
2499                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2500                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2501                                 if (vfinfo[vf].tx_rate[idx] != 0)
2502                                         rte_pmd_ixgbe_set_vf_rate_limit(
2503                                                 dev->data->port_id, vf,
2504                                                 vfinfo[vf].tx_rate[idx],
2505                                                 1 << idx);
2506         }
2507
2508         ixgbe_restore_statistics_mapping(dev);
2509
2510         err = ixgbe_dev_rxtx_start(dev);
2511         if (err < 0) {
2512                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2513                 goto error;
2514         }
2515
2516         /* Skip link setup if loopback mode is enabled for 82599. */
2517         if (hw->mac.type == ixgbe_mac_82599EB &&
2518                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2519                 goto skip_link_setup;
2520
2521         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2522                 err = hw->mac.ops.setup_sfp(hw);
2523                 if (err)
2524                         goto error;
2525         }
2526
2527         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2528                 /* Turn on the copper */
2529                 ixgbe_set_phy_power(hw, true);
2530         } else {
2531                 /* Turn on the laser */
2532                 ixgbe_enable_tx_laser(hw);
2533         }
2534
2535         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2536         if (err)
2537                 goto error;
2538         dev->data->dev_link.link_status = link_up;
2539
2540         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2541         if (err)
2542                 goto error;
2543
2544         link_speeds = &dev->data->dev_conf.link_speeds;
2545         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2546                         ETH_LINK_SPEED_10G)) {
2547                 PMD_INIT_LOG(ERR, "Invalid link setting");
2548                 goto error;
2549         }
2550
2551         speed = 0x0;
2552         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2553                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2554                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2555                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2556         } else {
2557                 if (*link_speeds & ETH_LINK_SPEED_10G)
2558                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2559                 if (*link_speeds & ETH_LINK_SPEED_1G)
2560                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2561                 if (*link_speeds & ETH_LINK_SPEED_100M)
2562                         speed |= IXGBE_LINK_SPEED_100_FULL;
2563         }
2564
2565         err = ixgbe_setup_link(hw, speed, link_up);
2566         if (err)
2567                 goto error;
2568
2569 skip_link_setup:
2570
2571         if (rte_intr_allow_others(intr_handle)) {
2572                 /* check if lsc interrupt is enabled */
2573                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2574                         ixgbe_dev_lsc_interrupt_setup(dev);
2575                 ixgbe_dev_macsec_interrupt_setup(dev);
2576         } else {
2577                 rte_intr_callback_unregister(intr_handle,
2578                                              ixgbe_dev_interrupt_handler, dev);
2579                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2580                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2581                                      " no intr multiplex");
2582         }
2583
2584         /* check if rxq interrupt is enabled */
2585         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2586             rte_intr_dp_is_en(intr_handle))
2587                 ixgbe_dev_rxq_interrupt_setup(dev);
2588
2589         /* enable uio/vfio intr/eventfd mapping */
2590         rte_intr_enable(intr_handle);
2591
2592         /* resume enabled intr since hw reset */
2593         ixgbe_enable_intr(dev);
2594         ixgbe_l2_tunnel_conf(dev);
2595         ixgbe_filter_restore(dev);
2596
2597         return 0;
2598
2599 error:
2600         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2601         ixgbe_dev_clear_queues(dev);
2602         return -EIO;
2603 }
2604
2605 /*
2606  * Stop device: disable rx and tx functions to allow for reconfiguring.
2607  */
2608 static void
2609 ixgbe_dev_stop(struct rte_eth_dev *dev)
2610 {
2611         struct rte_eth_link link;
2612         struct ixgbe_hw *hw =
2613                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2614         struct ixgbe_vf_info *vfinfo =
2615                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2616         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2617         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2618         int vf;
2619
2620         PMD_INIT_FUNC_TRACE();
2621
2622         /* disable interrupts */
2623         ixgbe_disable_intr(hw);
2624
2625         /* reset the NIC */
2626         ixgbe_pf_reset_hw(hw);
2627         hw->adapter_stopped = 0;
2628
2629         /* stop adapter */
2630         ixgbe_stop_adapter(hw);
2631
2632         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2633                 vfinfo[vf].clear_to_send = false;
2634
2635         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2636                 /* Turn off the copper */
2637                 ixgbe_set_phy_power(hw, false);
2638         } else {
2639                 /* Turn off the laser */
2640                 ixgbe_disable_tx_laser(hw);
2641         }
2642
2643         ixgbe_dev_clear_queues(dev);
2644
2645         /* Clear stored conf */
2646         dev->data->scattered_rx = 0;
2647         dev->data->lro = 0;
2648
2649         /* Clear recorded link status */
2650         memset(&link, 0, sizeof(link));
2651         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2652
2653         if (!rte_intr_allow_others(intr_handle))
2654                 /* resume to the default handler */
2655                 rte_intr_callback_register(intr_handle,
2656                                            ixgbe_dev_interrupt_handler,
2657                                            (void *)dev);
2658
2659         /* Clean datapath event and queue/vec mapping */
2660         rte_intr_efd_disable(intr_handle);
2661         if (intr_handle->intr_vec != NULL) {
2662                 rte_free(intr_handle->intr_vec);
2663                 intr_handle->intr_vec = NULL;
2664         }
2665 }
2666
2667 /*
2668  * Set device link up: enable tx.
2669  */
2670 static int
2671 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2672 {
2673         struct ixgbe_hw *hw =
2674                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2675         if (hw->mac.type == ixgbe_mac_82599EB) {
2676 #ifdef RTE_NIC_BYPASS
2677                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2678                         /* Not suported in bypass mode */
2679                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2680                                      "by device id 0x%x", hw->device_id);
2681                         return -ENOTSUP;
2682                 }
2683 #endif
2684         }
2685
2686         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2687                 /* Turn on the copper */
2688                 ixgbe_set_phy_power(hw, true);
2689         } else {
2690                 /* Turn on the laser */
2691                 ixgbe_enable_tx_laser(hw);
2692         }
2693
2694         return 0;
2695 }
2696
2697 /*
2698  * Set device link down: disable tx.
2699  */
2700 static int
2701 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2702 {
2703         struct ixgbe_hw *hw =
2704                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2705         if (hw->mac.type == ixgbe_mac_82599EB) {
2706 #ifdef RTE_NIC_BYPASS
2707                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2708                         /* Not suported in bypass mode */
2709                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2710                                      "by device id 0x%x", hw->device_id);
2711                         return -ENOTSUP;
2712                 }
2713 #endif
2714         }
2715
2716         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2717                 /* Turn off the copper */
2718                 ixgbe_set_phy_power(hw, false);
2719         } else {
2720                 /* Turn off the laser */
2721                 ixgbe_disable_tx_laser(hw);
2722         }
2723
2724         return 0;
2725 }
2726
2727 /*
2728  * Reest and stop device.
2729  */
2730 static void
2731 ixgbe_dev_close(struct rte_eth_dev *dev)
2732 {
2733         struct ixgbe_hw *hw =
2734                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2735
2736         PMD_INIT_FUNC_TRACE();
2737
2738         ixgbe_pf_reset_hw(hw);
2739
2740         ixgbe_dev_stop(dev);
2741         hw->adapter_stopped = 1;
2742
2743         ixgbe_dev_free_queues(dev);
2744
2745         ixgbe_disable_pcie_master(hw);
2746
2747         /* reprogram the RAR[0] in case user changed it. */
2748         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2749 }
2750
2751 static void
2752 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2753                            struct ixgbe_hw_stats *hw_stats,
2754                            struct ixgbe_macsec_stats *macsec_stats,
2755                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2756                            uint64_t *total_qprc, uint64_t *total_qprdc)
2757 {
2758         uint32_t bprc, lxon, lxoff, total;
2759         uint32_t delta_gprc = 0;
2760         unsigned i;
2761         /* Workaround for RX byte count not including CRC bytes when CRC
2762          * strip is enabled. CRC bytes are removed from counters when crc_strip
2763          * is disabled.
2764          */
2765         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2766                         IXGBE_HLREG0_RXCRCSTRP);
2767
2768         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2769         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2770         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2771         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2772
2773         for (i = 0; i < 8; i++) {
2774                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2775
2776                 /* global total per queue */
2777                 hw_stats->mpc[i] += mp;
2778                 /* Running comprehensive total for stats display */
2779                 *total_missed_rx += hw_stats->mpc[i];
2780                 if (hw->mac.type == ixgbe_mac_82598EB) {
2781                         hw_stats->rnbc[i] +=
2782                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2783                         hw_stats->pxonrxc[i] +=
2784                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2785                         hw_stats->pxoffrxc[i] +=
2786                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2787                 } else {
2788                         hw_stats->pxonrxc[i] +=
2789                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2790                         hw_stats->pxoffrxc[i] +=
2791                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2792                         hw_stats->pxon2offc[i] +=
2793                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2794                 }
2795                 hw_stats->pxontxc[i] +=
2796                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2797                 hw_stats->pxofftxc[i] +=
2798                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2799         }
2800         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2801                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2802                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2803                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2804
2805                 delta_gprc += delta_qprc;
2806
2807                 hw_stats->qprc[i] += delta_qprc;
2808                 hw_stats->qptc[i] += delta_qptc;
2809
2810                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2811                 hw_stats->qbrc[i] +=
2812                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2813                 if (crc_strip == 0)
2814                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2815
2816                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2817                 hw_stats->qbtc[i] +=
2818                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2819
2820                 hw_stats->qprdc[i] += delta_qprdc;
2821                 *total_qprdc += hw_stats->qprdc[i];
2822
2823                 *total_qprc += hw_stats->qprc[i];
2824                 *total_qbrc += hw_stats->qbrc[i];
2825         }
2826         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2827         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2828         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2829
2830         /*
2831          * An errata states that gprc actually counts good + missed packets:
2832          * Workaround to set gprc to summated queue packet receives
2833          */
2834         hw_stats->gprc = *total_qprc;
2835
2836         if (hw->mac.type != ixgbe_mac_82598EB) {
2837                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2838                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2839                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2840                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2841                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2842                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2843                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2844                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2845         } else {
2846                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2847                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2848                 /* 82598 only has a counter in the high register */
2849                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2850                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2851                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2852         }
2853         uint64_t old_tpr = hw_stats->tpr;
2854
2855         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2856         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2857
2858         if (crc_strip == 0)
2859                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2860
2861         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2862         hw_stats->gptc += delta_gptc;
2863         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2864         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2865
2866         /*
2867          * Workaround: mprc hardware is incorrectly counting
2868          * broadcasts, so for now we subtract those.
2869          */
2870         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2871         hw_stats->bprc += bprc;
2872         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2873         if (hw->mac.type == ixgbe_mac_82598EB)
2874                 hw_stats->mprc -= bprc;
2875
2876         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2877         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2878         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2879         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2880         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2881         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2882
2883         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2884         hw_stats->lxontxc += lxon;
2885         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2886         hw_stats->lxofftxc += lxoff;
2887         total = lxon + lxoff;
2888
2889         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2890         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2891         hw_stats->gptc -= total;
2892         hw_stats->mptc -= total;
2893         hw_stats->ptc64 -= total;
2894         hw_stats->gotc -= total * ETHER_MIN_LEN;
2895
2896         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2897         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2898         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2899         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2900         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2901         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2902         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2903         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2904         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2905         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2906         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2907         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2908         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2909         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2910         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2911         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2912         /* Only read FCOE on 82599 */
2913         if (hw->mac.type != ixgbe_mac_82598EB) {
2914                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2915                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2916                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2917                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2918                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2919         }
2920
2921         /* Flow Director Stats registers */
2922         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2923         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2924
2925         /* MACsec Stats registers */
2926         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
2927         macsec_stats->out_pkts_encrypted +=
2928                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
2929         macsec_stats->out_pkts_protected +=
2930                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
2931         macsec_stats->out_octets_encrypted +=
2932                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
2933         macsec_stats->out_octets_protected +=
2934                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
2935         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
2936         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
2937         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
2938         macsec_stats->in_pkts_unknownsci +=
2939                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
2940         macsec_stats->in_octets_decrypted +=
2941                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
2942         macsec_stats->in_octets_validated +=
2943                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
2944         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
2945         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
2946         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
2947         for (i = 0; i < 2; i++) {
2948                 macsec_stats->in_pkts_ok +=
2949                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
2950                 macsec_stats->in_pkts_invalid +=
2951                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
2952                 macsec_stats->in_pkts_notvalid +=
2953                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
2954         }
2955         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
2956         macsec_stats->in_pkts_notusingsa +=
2957                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
2958 }
2959
2960 /*
2961  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2962  */
2963 static void
2964 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2965 {
2966         struct ixgbe_hw *hw =
2967                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2968         struct ixgbe_hw_stats *hw_stats =
2969                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2970         struct ixgbe_macsec_stats *macsec_stats =
2971                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2972                                 dev->data->dev_private);
2973         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2974         unsigned i;
2975
2976         total_missed_rx = 0;
2977         total_qbrc = 0;
2978         total_qprc = 0;
2979         total_qprdc = 0;
2980
2981         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2982                         &total_qbrc, &total_qprc, &total_qprdc);
2983
2984         if (stats == NULL)
2985                 return;
2986
2987         /* Fill out the rte_eth_stats statistics structure */
2988         stats->ipackets = total_qprc;
2989         stats->ibytes = total_qbrc;
2990         stats->opackets = hw_stats->gptc;
2991         stats->obytes = hw_stats->gotc;
2992
2993         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2994                 stats->q_ipackets[i] = hw_stats->qprc[i];
2995                 stats->q_opackets[i] = hw_stats->qptc[i];
2996                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2997                 stats->q_obytes[i] = hw_stats->qbtc[i];
2998                 stats->q_errors[i] = hw_stats->qprdc[i];
2999         }
3000
3001         /* Rx Errors */
3002         stats->imissed  = total_missed_rx;
3003         stats->ierrors  = hw_stats->crcerrs +
3004                           hw_stats->mspdc +
3005                           hw_stats->rlec +
3006                           hw_stats->ruc +
3007                           hw_stats->roc +
3008                           hw_stats->illerrc +
3009                           hw_stats->errbc +
3010                           hw_stats->rfc +
3011                           hw_stats->fccrc +
3012                           hw_stats->fclast;
3013
3014         /* Tx Errors */
3015         stats->oerrors  = 0;
3016 }
3017
3018 static void
3019 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3020 {
3021         struct ixgbe_hw_stats *stats =
3022                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3023
3024         /* HW registers are cleared on read */
3025         ixgbe_dev_stats_get(dev, NULL);
3026
3027         /* Reset software totals */
3028         memset(stats, 0, sizeof(*stats));
3029 }
3030
3031 /* This function calculates the number of xstats based on the current config */
3032 static unsigned
3033 ixgbe_xstats_calc_num(void) {
3034         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3035                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3036                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3037 }
3038
3039 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3040         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
3041 {
3042         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3043         unsigned stat, i, count;
3044
3045         if (xstats_names != NULL) {
3046                 count = 0;
3047
3048                 /* Note: limit >= cnt_stats checked upstream
3049                  * in rte_eth_xstats_names()
3050                  */
3051
3052                 /* Extended stats from ixgbe_hw_stats */
3053                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3054                         snprintf(xstats_names[count].name,
3055                                 sizeof(xstats_names[count].name),
3056                                 "%s",
3057                                 rte_ixgbe_stats_strings[i].name);
3058                         count++;
3059                 }
3060
3061                 /* MACsec Stats */
3062                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3063                         snprintf(xstats_names[count].name,
3064                                 sizeof(xstats_names[count].name),
3065                                 "%s",
3066                                 rte_ixgbe_macsec_strings[i].name);
3067                         count++;
3068                 }
3069
3070                 /* RX Priority Stats */
3071                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3072                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3073                                 snprintf(xstats_names[count].name,
3074                                         sizeof(xstats_names[count].name),
3075                                         "rx_priority%u_%s", i,
3076                                         rte_ixgbe_rxq_strings[stat].name);
3077                                 count++;
3078                         }
3079                 }
3080
3081                 /* TX Priority Stats */
3082                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3083                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3084                                 snprintf(xstats_names[count].name,
3085                                         sizeof(xstats_names[count].name),
3086                                         "tx_priority%u_%s", i,
3087                                         rte_ixgbe_txq_strings[stat].name);
3088                                 count++;
3089                         }
3090                 }
3091         }
3092         return cnt_stats;
3093 }
3094
3095 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3096         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3097 {
3098         unsigned i;
3099
3100         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3101                 return -ENOMEM;
3102
3103         if (xstats_names != NULL)
3104                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3105                         snprintf(xstats_names[i].name,
3106                                 sizeof(xstats_names[i].name),
3107                                 "%s", rte_ixgbevf_stats_strings[i].name);
3108         return IXGBEVF_NB_XSTATS;
3109 }
3110
3111 static int
3112 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3113                                          unsigned n)
3114 {
3115         struct ixgbe_hw *hw =
3116                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3117         struct ixgbe_hw_stats *hw_stats =
3118                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3119         struct ixgbe_macsec_stats *macsec_stats =
3120                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3121                                 dev->data->dev_private);
3122         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3123         unsigned i, stat, count = 0;
3124
3125         count = ixgbe_xstats_calc_num();
3126
3127         if (n < count)
3128                 return count;
3129
3130         total_missed_rx = 0;
3131         total_qbrc = 0;
3132         total_qprc = 0;
3133         total_qprdc = 0;
3134
3135         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3136                         &total_qbrc, &total_qprc, &total_qprdc);
3137
3138         /* If this is a reset xstats is NULL, and we have cleared the
3139          * registers by reading them.
3140          */
3141         if (!xstats)
3142                 return 0;
3143
3144         /* Extended stats from ixgbe_hw_stats */
3145         count = 0;
3146         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3147                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3148                                 rte_ixgbe_stats_strings[i].offset);
3149                 xstats[count].id = count;
3150                 count++;
3151         }
3152
3153         /* MACsec Stats */
3154         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3155                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3156                                 rte_ixgbe_macsec_strings[i].offset);
3157                 xstats[count].id = count;
3158                 count++;
3159         }
3160
3161         /* RX Priority Stats */
3162         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3163                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3164                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3165                                         rte_ixgbe_rxq_strings[stat].offset +
3166                                         (sizeof(uint64_t) * i));
3167                         xstats[count].id = count;
3168                         count++;
3169                 }
3170         }
3171
3172         /* TX Priority Stats */
3173         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3174                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3175                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3176                                         rte_ixgbe_txq_strings[stat].offset +
3177                                         (sizeof(uint64_t) * i));
3178                         xstats[count].id = count;
3179                         count++;
3180                 }
3181         }
3182         return count;
3183 }
3184
3185 static void
3186 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3187 {
3188         struct ixgbe_hw_stats *stats =
3189                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3190         struct ixgbe_macsec_stats *macsec_stats =
3191                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3192                                 dev->data->dev_private);
3193
3194         unsigned count = ixgbe_xstats_calc_num();
3195
3196         /* HW registers are cleared on read */
3197         ixgbe_dev_xstats_get(dev, NULL, count);
3198
3199         /* Reset software totals */
3200         memset(stats, 0, sizeof(*stats));
3201         memset(macsec_stats, 0, sizeof(*macsec_stats));
3202 }
3203
3204 static void
3205 ixgbevf_update_stats(struct rte_eth_dev *dev)
3206 {
3207         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3208         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3209                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3210
3211         /* Good Rx packet, include VF loopback */
3212         UPDATE_VF_STAT(IXGBE_VFGPRC,
3213             hw_stats->last_vfgprc, hw_stats->vfgprc);
3214
3215         /* Good Rx octets, include VF loopback */
3216         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3217             hw_stats->last_vfgorc, hw_stats->vfgorc);
3218
3219         /* Good Tx packet, include VF loopback */
3220         UPDATE_VF_STAT(IXGBE_VFGPTC,
3221             hw_stats->last_vfgptc, hw_stats->vfgptc);
3222
3223         /* Good Tx octets, include VF loopback */
3224         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3225             hw_stats->last_vfgotc, hw_stats->vfgotc);
3226
3227         /* Rx Multicst Packet */
3228         UPDATE_VF_STAT(IXGBE_VFMPRC,
3229             hw_stats->last_vfmprc, hw_stats->vfmprc);
3230 }
3231
3232 static int
3233 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3234                        unsigned n)
3235 {
3236         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3237                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3238         unsigned i;
3239
3240         if (n < IXGBEVF_NB_XSTATS)
3241                 return IXGBEVF_NB_XSTATS;
3242
3243         ixgbevf_update_stats(dev);
3244
3245         if (!xstats)
3246                 return 0;
3247
3248         /* Extended stats */
3249         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3250                 xstats[i].id = i;
3251                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3252                         rte_ixgbevf_stats_strings[i].offset);
3253         }
3254
3255         return IXGBEVF_NB_XSTATS;
3256 }
3257
3258 static void
3259 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3260 {
3261         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3262                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3263
3264         ixgbevf_update_stats(dev);
3265
3266         if (stats == NULL)
3267                 return;
3268
3269         stats->ipackets = hw_stats->vfgprc;
3270         stats->ibytes = hw_stats->vfgorc;
3271         stats->opackets = hw_stats->vfgptc;
3272         stats->obytes = hw_stats->vfgotc;
3273 }
3274
3275 static void
3276 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3277 {
3278         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3279                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3280
3281         /* Sync HW register to the last stats */
3282         ixgbevf_dev_stats_get(dev, NULL);
3283
3284         /* reset HW current stats*/
3285         hw_stats->vfgprc = 0;
3286         hw_stats->vfgorc = 0;
3287         hw_stats->vfgptc = 0;
3288         hw_stats->vfgotc = 0;
3289 }
3290
3291 static int
3292 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3293 {
3294         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3295         u16 eeprom_verh, eeprom_verl;
3296         u32 etrack_id;
3297         int ret;
3298
3299         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3300         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3301
3302         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3303         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3304
3305         ret += 1; /* add the size of '\0' */
3306         if (fw_size < (u32)ret)
3307                 return ret;
3308         else
3309                 return 0;
3310 }
3311
3312 static void
3313 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3314 {
3315         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3316         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3317         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3318
3319         dev_info->pci_dev = pci_dev;
3320         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3321         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3322         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3323                 /*
3324                  * When DCB/VT is off, maximum number of queues changes,
3325                  * except for 82598EB, which remains constant.
3326                  */
3327                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3328                                 hw->mac.type != ixgbe_mac_82598EB)
3329                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3330         }
3331         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3332         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3333         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3334         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3335         dev_info->max_vfs = pci_dev->max_vfs;
3336         if (hw->mac.type == ixgbe_mac_82598EB)
3337                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3338         else
3339                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3340         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3341         dev_info->rx_offload_capa =
3342                 DEV_RX_OFFLOAD_VLAN_STRIP |
3343                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3344                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3345                 DEV_RX_OFFLOAD_TCP_CKSUM;
3346
3347         /*
3348          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3349          * mode.
3350          */
3351         if ((hw->mac.type == ixgbe_mac_82599EB ||
3352              hw->mac.type == ixgbe_mac_X540) &&
3353             !RTE_ETH_DEV_SRIOV(dev).active)
3354                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3355
3356         if (hw->mac.type == ixgbe_mac_82599EB ||
3357             hw->mac.type == ixgbe_mac_X540)
3358                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3359
3360         if (hw->mac.type == ixgbe_mac_X550 ||
3361             hw->mac.type == ixgbe_mac_X550EM_x ||
3362             hw->mac.type == ixgbe_mac_X550EM_a)
3363                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3364
3365         dev_info->tx_offload_capa =
3366                 DEV_TX_OFFLOAD_VLAN_INSERT |
3367                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3368                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3369                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3370                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3371                 DEV_TX_OFFLOAD_TCP_TSO;
3372
3373         if (hw->mac.type == ixgbe_mac_82599EB ||
3374             hw->mac.type == ixgbe_mac_X540)
3375                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3376
3377         if (hw->mac.type == ixgbe_mac_X550 ||
3378             hw->mac.type == ixgbe_mac_X550EM_x ||
3379             hw->mac.type == ixgbe_mac_X550EM_a)
3380                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3381
3382         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3383                 .rx_thresh = {
3384                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3385                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3386                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3387                 },
3388                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3389                 .rx_drop_en = 0,
3390         };
3391
3392         dev_info->default_txconf = (struct rte_eth_txconf) {
3393                 .tx_thresh = {
3394                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3395                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3396                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3397                 },
3398                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3399                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3400                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3401                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3402         };
3403
3404         dev_info->rx_desc_lim = rx_desc_lim;
3405         dev_info->tx_desc_lim = tx_desc_lim;
3406
3407         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3408         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3409         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3410
3411         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3412         if (hw->mac.type == ixgbe_mac_X540 ||
3413             hw->mac.type == ixgbe_mac_X540_vf ||
3414             hw->mac.type == ixgbe_mac_X550 ||
3415             hw->mac.type == ixgbe_mac_X550_vf) {
3416                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3417         }
3418 }
3419
3420 static const uint32_t *
3421 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3422 {
3423         static const uint32_t ptypes[] = {
3424                 /* For non-vec functions,
3425                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3426                  * for vec functions,
3427                  * refers to _recv_raw_pkts_vec().
3428                  */
3429                 RTE_PTYPE_L2_ETHER,
3430                 RTE_PTYPE_L3_IPV4,
3431                 RTE_PTYPE_L3_IPV4_EXT,
3432                 RTE_PTYPE_L3_IPV6,
3433                 RTE_PTYPE_L3_IPV6_EXT,
3434                 RTE_PTYPE_L4_SCTP,
3435                 RTE_PTYPE_L4_TCP,
3436                 RTE_PTYPE_L4_UDP,
3437                 RTE_PTYPE_TUNNEL_IP,
3438                 RTE_PTYPE_INNER_L3_IPV6,
3439                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3440                 RTE_PTYPE_INNER_L4_TCP,
3441                 RTE_PTYPE_INNER_L4_UDP,
3442                 RTE_PTYPE_UNKNOWN
3443         };
3444
3445         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3446             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3447             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3448             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3449                 return ptypes;
3450         return NULL;
3451 }
3452
3453 static void
3454 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3455                      struct rte_eth_dev_info *dev_info)
3456 {
3457         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3458         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3459
3460         dev_info->pci_dev = pci_dev;
3461         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3462         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3463         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3464         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3465         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3466         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3467         dev_info->max_vfs = pci_dev->max_vfs;
3468         if (hw->mac.type == ixgbe_mac_82598EB)
3469                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3470         else
3471                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3472         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3473                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3474                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3475                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3476         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3477                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3478                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3479                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3480                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3481                                 DEV_TX_OFFLOAD_TCP_TSO;
3482
3483         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3484                 .rx_thresh = {
3485                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3486                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3487                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3488                 },
3489                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3490                 .rx_drop_en = 0,
3491         };
3492
3493         dev_info->default_txconf = (struct rte_eth_txconf) {
3494                 .tx_thresh = {
3495                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3496                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3497                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3498                 },
3499                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3500                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3501                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3502                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3503         };
3504
3505         dev_info->rx_desc_lim = rx_desc_lim;
3506         dev_info->tx_desc_lim = tx_desc_lim;
3507 }
3508
3509 /* return 0 means link status changed, -1 means not changed */
3510 static int
3511 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3512 {
3513         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3514         struct rte_eth_link link, old;
3515         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3516         int link_up;
3517         int diag;
3518
3519         link.link_status = ETH_LINK_DOWN;
3520         link.link_speed = 0;
3521         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3522         memset(&old, 0, sizeof(old));
3523         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3524
3525         hw->mac.get_link_status = true;
3526
3527         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3528         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3529                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3530         else
3531                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3532
3533         if (diag != 0) {
3534                 link.link_speed = ETH_SPEED_NUM_100M;
3535                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3536                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3537                 if (link.link_status == old.link_status)
3538                         return -1;
3539                 return 0;
3540         }
3541
3542         if (link_up == 0) {
3543                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3544                 if (link.link_status == old.link_status)
3545                         return -1;
3546                 return 0;
3547         }
3548         link.link_status = ETH_LINK_UP;
3549         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3550
3551         switch (link_speed) {
3552         default:
3553         case IXGBE_LINK_SPEED_UNKNOWN:
3554                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3555                 link.link_speed = ETH_SPEED_NUM_100M;
3556                 break;
3557
3558         case IXGBE_LINK_SPEED_100_FULL:
3559                 link.link_speed = ETH_SPEED_NUM_100M;
3560                 break;
3561
3562         case IXGBE_LINK_SPEED_1GB_FULL:
3563                 link.link_speed = ETH_SPEED_NUM_1G;
3564                 break;
3565
3566         case IXGBE_LINK_SPEED_10GB_FULL:
3567                 link.link_speed = ETH_SPEED_NUM_10G;
3568                 break;
3569         }
3570         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3571
3572         if (link.link_status == old.link_status)
3573                 return -1;
3574
3575         return 0;
3576 }
3577
3578 static void
3579 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3580 {
3581         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3582         uint32_t fctrl;
3583
3584         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3585         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3586         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3587 }
3588
3589 static void
3590 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3591 {
3592         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3593         uint32_t fctrl;
3594
3595         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3596         fctrl &= (~IXGBE_FCTRL_UPE);
3597         if (dev->data->all_multicast == 1)
3598                 fctrl |= IXGBE_FCTRL_MPE;
3599         else
3600                 fctrl &= (~IXGBE_FCTRL_MPE);
3601         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3602 }
3603
3604 static void
3605 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3606 {
3607         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3608         uint32_t fctrl;
3609
3610         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3611         fctrl |= IXGBE_FCTRL_MPE;
3612         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3613 }
3614
3615 static void
3616 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3617 {
3618         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3619         uint32_t fctrl;
3620
3621         if (dev->data->promiscuous == 1)
3622                 return; /* must remain in all_multicast mode */
3623
3624         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3625         fctrl &= (~IXGBE_FCTRL_MPE);
3626         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3627 }
3628
3629 /**
3630  * It clears the interrupt causes and enables the interrupt.
3631  * It will be called once only during nic initialized.
3632  *
3633  * @param dev
3634  *  Pointer to struct rte_eth_dev.
3635  *
3636  * @return
3637  *  - On success, zero.
3638  *  - On failure, a negative value.
3639  */
3640 static int
3641 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3642 {
3643         struct ixgbe_interrupt *intr =
3644                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3645
3646         ixgbe_dev_link_status_print(dev);
3647         intr->mask |= IXGBE_EICR_LSC;
3648
3649         return 0;
3650 }
3651
3652 /**
3653  * It clears the interrupt causes and enables the interrupt.
3654  * It will be called once only during nic initialized.
3655  *
3656  * @param dev
3657  *  Pointer to struct rte_eth_dev.
3658  *
3659  * @return
3660  *  - On success, zero.
3661  *  - On failure, a negative value.
3662  */
3663 static int
3664 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3665 {
3666         struct ixgbe_interrupt *intr =
3667                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3668
3669         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3670
3671         return 0;
3672 }
3673
3674 /**
3675  * It clears the interrupt causes and enables the interrupt.
3676  * It will be called once only during nic initialized.
3677  *
3678  * @param dev
3679  *  Pointer to struct rte_eth_dev.
3680  *
3681  * @return
3682  *  - On success, zero.
3683  *  - On failure, a negative value.
3684  */
3685 static int
3686 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3687 {
3688         struct ixgbe_interrupt *intr =
3689                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3690
3691         intr->mask |= IXGBE_EICR_LINKSEC;
3692
3693         return 0;
3694 }
3695
3696 /*
3697  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3698  *
3699  * @param dev
3700  *  Pointer to struct rte_eth_dev.
3701  *
3702  * @return
3703  *  - On success, zero.
3704  *  - On failure, a negative value.
3705  */
3706 static int
3707 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3708 {
3709         uint32_t eicr;
3710         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3711         struct ixgbe_interrupt *intr =
3712                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3713
3714         /* clear all cause mask */
3715         ixgbe_disable_intr(hw);
3716
3717         /* read-on-clear nic registers here */
3718         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3719         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3720
3721         intr->flags = 0;
3722
3723         /* set flag for async link update */
3724         if (eicr & IXGBE_EICR_LSC)
3725                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3726
3727         if (eicr & IXGBE_EICR_MAILBOX)
3728                 intr->flags |= IXGBE_FLAG_MAILBOX;
3729
3730         if (eicr & IXGBE_EICR_LINKSEC)
3731                 intr->flags |= IXGBE_FLAG_MACSEC;
3732
3733         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3734             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3735             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3736                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3737
3738         return 0;
3739 }
3740
3741 /**
3742  * It gets and then prints the link status.
3743  *
3744  * @param dev
3745  *  Pointer to struct rte_eth_dev.
3746  *
3747  * @return
3748  *  - On success, zero.
3749  *  - On failure, a negative value.
3750  */
3751 static void
3752 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3753 {
3754         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3755         struct rte_eth_link link;
3756
3757         memset(&link, 0, sizeof(link));
3758         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3759         if (link.link_status) {
3760                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3761                                         (int)(dev->data->port_id),
3762                                         (unsigned)link.link_speed,
3763                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3764                                         "full-duplex" : "half-duplex");
3765         } else {
3766                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3767                                 (int)(dev->data->port_id));
3768         }
3769         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3770                                 pci_dev->addr.domain,
3771                                 pci_dev->addr.bus,
3772                                 pci_dev->addr.devid,
3773                                 pci_dev->addr.function);
3774 }
3775
3776 /*
3777  * It executes link_update after knowing an interrupt occurred.
3778  *
3779  * @param dev
3780  *  Pointer to struct rte_eth_dev.
3781  *
3782  * @return
3783  *  - On success, zero.
3784  *  - On failure, a negative value.
3785  */
3786 static int
3787 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3788                            struct rte_intr_handle *intr_handle)
3789 {
3790         struct ixgbe_interrupt *intr =
3791                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3792         int64_t timeout;
3793         struct rte_eth_link link;
3794         struct ixgbe_hw *hw =
3795                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3796
3797         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3798
3799         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3800                 ixgbe_pf_mbx_process(dev);
3801                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3802         }
3803
3804         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3805                 ixgbe_handle_lasi(hw);
3806                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3807         }
3808
3809         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3810                 /* get the link status before link update, for predicting later */
3811                 memset(&link, 0, sizeof(link));
3812                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3813
3814                 ixgbe_dev_link_update(dev, 0);
3815
3816                 /* likely to up */
3817                 if (!link.link_status)
3818                         /* handle it 1 sec later, wait it being stable */
3819                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3820                 /* likely to down */
3821                 else
3822                         /* handle it 4 sec later, wait it being stable */
3823                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3824
3825                 ixgbe_dev_link_status_print(dev);
3826                 intr->mask_original = intr->mask;
3827                 /* only disable lsc interrupt */
3828                 intr->mask &= ~IXGBE_EIMS_LSC;
3829                 if (rte_eal_alarm_set(timeout * 1000,
3830                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3831                         PMD_DRV_LOG(ERR, "Error setting alarm");
3832                 else
3833                         intr->mask = intr->mask_original;
3834         }
3835
3836         PMD_DRV_LOG(DEBUG, "enable intr immediately");
3837         ixgbe_enable_intr(dev);
3838         rte_intr_enable(intr_handle);
3839
3840         return 0;
3841 }
3842
3843 /**
3844  * Interrupt handler which shall be registered for alarm callback for delayed
3845  * handling specific interrupt to wait for the stable nic state. As the
3846  * NIC interrupt state is not stable for ixgbe after link is just down,
3847  * it needs to wait 4 seconds to get the stable status.
3848  *
3849  * @param handle
3850  *  Pointer to interrupt handle.
3851  * @param param
3852  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3853  *
3854  * @return
3855  *  void
3856  */
3857 static void
3858 ixgbe_dev_interrupt_delayed_handler(void *param)
3859 {
3860         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3861         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3862         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3863         struct ixgbe_interrupt *intr =
3864                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3865         struct ixgbe_hw *hw =
3866                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3867         uint32_t eicr;
3868
3869         ixgbe_disable_intr(hw);
3870
3871         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3872         if (eicr & IXGBE_EICR_MAILBOX)
3873                 ixgbe_pf_mbx_process(dev);
3874
3875         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3876                 ixgbe_handle_lasi(hw);
3877                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3878         }
3879
3880         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3881                 ixgbe_dev_link_update(dev, 0);
3882                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3883                 ixgbe_dev_link_status_print(dev);
3884                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3885         }
3886
3887         if (intr->flags & IXGBE_FLAG_MACSEC) {
3888                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3889                                               NULL);
3890                 intr->flags &= ~IXGBE_FLAG_MACSEC;
3891         }
3892
3893         /* restore original mask */
3894         intr->mask = intr->mask_original;
3895         intr->mask_original = 0;
3896
3897         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3898         ixgbe_enable_intr(dev);
3899         rte_intr_enable(intr_handle);
3900 }
3901
3902 /**
3903  * Interrupt handler triggered by NIC  for handling
3904  * specific interrupt.
3905  *
3906  * @param handle
3907  *  Pointer to interrupt handle.
3908  * @param param
3909  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3910  *
3911  * @return
3912  *  void
3913  */
3914 static void
3915 ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
3916                             void *param)
3917 {
3918         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3919
3920         ixgbe_dev_interrupt_get_status(dev);
3921         ixgbe_dev_interrupt_action(dev, handle);
3922 }
3923
3924 static int
3925 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3926 {
3927         struct ixgbe_hw *hw;
3928
3929         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3930         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3931 }
3932
3933 static int
3934 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3935 {
3936         struct ixgbe_hw *hw;
3937
3938         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3939         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3940 }
3941
3942 static int
3943 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3944 {
3945         struct ixgbe_hw *hw;
3946         uint32_t mflcn_reg;
3947         uint32_t fccfg_reg;
3948         int rx_pause;
3949         int tx_pause;
3950
3951         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3952
3953         fc_conf->pause_time = hw->fc.pause_time;
3954         fc_conf->high_water = hw->fc.high_water[0];
3955         fc_conf->low_water = hw->fc.low_water[0];
3956         fc_conf->send_xon = hw->fc.send_xon;
3957         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3958
3959         /*
3960          * Return rx_pause status according to actual setting of
3961          * MFLCN register.
3962          */
3963         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3964         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3965                 rx_pause = 1;
3966         else
3967                 rx_pause = 0;
3968
3969         /*
3970          * Return tx_pause status according to actual setting of
3971          * FCCFG register.
3972          */
3973         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3974         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3975                 tx_pause = 1;
3976         else
3977                 tx_pause = 0;
3978
3979         if (rx_pause && tx_pause)
3980                 fc_conf->mode = RTE_FC_FULL;
3981         else if (rx_pause)
3982                 fc_conf->mode = RTE_FC_RX_PAUSE;
3983         else if (tx_pause)
3984                 fc_conf->mode = RTE_FC_TX_PAUSE;
3985         else
3986                 fc_conf->mode = RTE_FC_NONE;
3987
3988         return 0;
3989 }
3990
3991 static int
3992 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3993 {
3994         struct ixgbe_hw *hw;
3995         int err;
3996         uint32_t rx_buf_size;
3997         uint32_t max_high_water;
3998         uint32_t mflcn;
3999         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4000                 ixgbe_fc_none,
4001                 ixgbe_fc_rx_pause,
4002                 ixgbe_fc_tx_pause,
4003                 ixgbe_fc_full
4004         };
4005
4006         PMD_INIT_FUNC_TRACE();
4007
4008         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4009         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4010         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4011
4012         /*
4013          * At least reserve one Ethernet frame for watermark
4014          * high_water/low_water in kilo bytes for ixgbe
4015          */
4016         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4017         if ((fc_conf->high_water > max_high_water) ||
4018                 (fc_conf->high_water < fc_conf->low_water)) {
4019                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4020                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4021                 return -EINVAL;
4022         }
4023
4024         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4025         hw->fc.pause_time     = fc_conf->pause_time;
4026         hw->fc.high_water[0]  = fc_conf->high_water;
4027         hw->fc.low_water[0]   = fc_conf->low_water;
4028         hw->fc.send_xon       = fc_conf->send_xon;
4029         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4030
4031         err = ixgbe_fc_enable(hw);
4032
4033         /* Not negotiated is not an error case */
4034         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4035
4036                 /* check if we want to forward MAC frames - driver doesn't have native
4037                  * capability to do that, so we'll write the registers ourselves */
4038
4039                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4040
4041                 /* set or clear MFLCN.PMCF bit depending on configuration */
4042                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4043                         mflcn |= IXGBE_MFLCN_PMCF;
4044                 else
4045                         mflcn &= ~IXGBE_MFLCN_PMCF;
4046
4047                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4048                 IXGBE_WRITE_FLUSH(hw);
4049
4050                 return 0;
4051         }
4052
4053         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4054         return -EIO;
4055 }
4056
4057 /**
4058  *  ixgbe_pfc_enable_generic - Enable flow control
4059  *  @hw: pointer to hardware structure
4060  *  @tc_num: traffic class number
4061  *  Enable flow control according to the current settings.
4062  */
4063 static int
4064 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4065 {
4066         int ret_val = 0;
4067         uint32_t mflcn_reg, fccfg_reg;
4068         uint32_t reg;
4069         uint32_t fcrtl, fcrth;
4070         uint8_t i;
4071         uint8_t nb_rx_en;
4072
4073         /* Validate the water mark configuration */
4074         if (!hw->fc.pause_time) {
4075                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4076                 goto out;
4077         }
4078
4079         /* Low water mark of zero causes XOFF floods */
4080         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4081                  /* High/Low water can not be 0 */
4082                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4083                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4084                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4085                         goto out;
4086                 }
4087
4088                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4089                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4090                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4091                         goto out;
4092                 }
4093         }
4094         /* Negotiate the fc mode to use */
4095         ixgbe_fc_autoneg(hw);
4096
4097         /* Disable any previous flow control settings */
4098         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4099         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4100
4101         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4102         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4103
4104         switch (hw->fc.current_mode) {
4105         case ixgbe_fc_none:
4106                 /*
4107                  * If the count of enabled RX Priority Flow control >1,
4108                  * and the TX pause can not be disabled
4109                  */
4110                 nb_rx_en = 0;
4111                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4112                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4113                         if (reg & IXGBE_FCRTH_FCEN)
4114                                 nb_rx_en++;
4115                 }
4116                 if (nb_rx_en > 1)
4117                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4118                 break;
4119         case ixgbe_fc_rx_pause:
4120                 /*
4121                  * Rx Flow control is enabled and Tx Flow control is
4122                  * disabled by software override. Since there really
4123                  * isn't a way to advertise that we are capable of RX
4124                  * Pause ONLY, we will advertise that we support both
4125                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4126                  * disable the adapter's ability to send PAUSE frames.
4127                  */
4128                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4129                 /*
4130                  * If the count of enabled RX Priority Flow control >1,
4131                  * and the TX pause can not be disabled
4132                  */
4133                 nb_rx_en = 0;
4134                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4135                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4136                         if (reg & IXGBE_FCRTH_FCEN)
4137                                 nb_rx_en++;
4138                 }
4139                 if (nb_rx_en > 1)
4140                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4141                 break;
4142         case ixgbe_fc_tx_pause:
4143                 /*
4144                  * Tx Flow control is enabled, and Rx Flow control is
4145                  * disabled by software override.
4146                  */
4147                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4148                 break;
4149         case ixgbe_fc_full:
4150                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4151                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4152                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4153                 break;
4154         default:
4155                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4156                 ret_val = IXGBE_ERR_CONFIG;
4157                 goto out;
4158         }
4159
4160         /* Set 802.3x based flow control settings. */
4161         mflcn_reg |= IXGBE_MFLCN_DPF;
4162         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4163         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4164
4165         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4166         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4167                 hw->fc.high_water[tc_num]) {
4168                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4169                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4170                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4171         } else {
4172                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4173                 /*
4174                  * In order to prevent Tx hangs when the internal Tx
4175                  * switch is enabled we must set the high water mark
4176                  * to the maximum FCRTH value.  This allows the Tx
4177                  * switch to function even under heavy Rx workloads.
4178                  */
4179                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4180         }
4181         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4182
4183         /* Configure pause time (2 TCs per register) */
4184         reg = hw->fc.pause_time * 0x00010001;
4185         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4186                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4187
4188         /* Configure flow control refresh threshold value */
4189         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4190
4191 out:
4192         return ret_val;
4193 }
4194
4195 static int
4196 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4197 {
4198         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4199         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4200
4201         if (hw->mac.type != ixgbe_mac_82598EB) {
4202                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4203         }
4204         return ret_val;
4205 }
4206
4207 static int
4208 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4209 {
4210         int err;
4211         uint32_t rx_buf_size;
4212         uint32_t max_high_water;
4213         uint8_t tc_num;
4214         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4215         struct ixgbe_hw *hw =
4216                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4217         struct ixgbe_dcb_config *dcb_config =
4218                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4219
4220         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4221                 ixgbe_fc_none,
4222                 ixgbe_fc_rx_pause,
4223                 ixgbe_fc_tx_pause,
4224                 ixgbe_fc_full
4225         };
4226
4227         PMD_INIT_FUNC_TRACE();
4228
4229         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4230         tc_num = map[pfc_conf->priority];
4231         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4232         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4233         /*
4234          * At least reserve one Ethernet frame for watermark
4235          * high_water/low_water in kilo bytes for ixgbe
4236          */
4237         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4238         if ((pfc_conf->fc.high_water > max_high_water) ||
4239             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4240                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4241                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4242                 return -EINVAL;
4243         }
4244
4245         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4246         hw->fc.pause_time = pfc_conf->fc.pause_time;
4247         hw->fc.send_xon = pfc_conf->fc.send_xon;
4248         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4249         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4250
4251         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4252
4253         /* Not negotiated is not an error case */
4254         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4255                 return 0;
4256
4257         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4258         return -EIO;
4259 }
4260
4261 static int
4262 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4263                           struct rte_eth_rss_reta_entry64 *reta_conf,
4264                           uint16_t reta_size)
4265 {
4266         uint16_t i, sp_reta_size;
4267         uint8_t j, mask;
4268         uint32_t reta, r;
4269         uint16_t idx, shift;
4270         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4271         uint32_t reta_reg;
4272
4273         PMD_INIT_FUNC_TRACE();
4274
4275         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4276                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4277                         "NIC.");
4278                 return -ENOTSUP;
4279         }
4280
4281         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4282         if (reta_size != sp_reta_size) {
4283                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4284                         "(%d) doesn't match the number hardware can supported "
4285                         "(%d)", reta_size, sp_reta_size);
4286                 return -EINVAL;
4287         }
4288
4289         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4290                 idx = i / RTE_RETA_GROUP_SIZE;
4291                 shift = i % RTE_RETA_GROUP_SIZE;
4292                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4293                                                 IXGBE_4_BIT_MASK);
4294                 if (!mask)
4295                         continue;
4296                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4297                 if (mask == IXGBE_4_BIT_MASK)
4298                         r = 0;
4299                 else
4300                         r = IXGBE_READ_REG(hw, reta_reg);
4301                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4302                         if (mask & (0x1 << j))
4303                                 reta |= reta_conf[idx].reta[shift + j] <<
4304                                                         (CHAR_BIT * j);
4305                         else
4306                                 reta |= r & (IXGBE_8_BIT_MASK <<
4307                                                 (CHAR_BIT * j));
4308                 }
4309                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4310         }
4311
4312         return 0;
4313 }
4314
4315 static int
4316 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4317                          struct rte_eth_rss_reta_entry64 *reta_conf,
4318                          uint16_t reta_size)
4319 {
4320         uint16_t i, sp_reta_size;
4321         uint8_t j, mask;
4322         uint32_t reta;
4323         uint16_t idx, shift;
4324         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4325         uint32_t reta_reg;
4326
4327         PMD_INIT_FUNC_TRACE();
4328         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4329         if (reta_size != sp_reta_size) {
4330                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4331                         "(%d) doesn't match the number hardware can supported "
4332                         "(%d)", reta_size, sp_reta_size);
4333                 return -EINVAL;
4334         }
4335
4336         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4337                 idx = i / RTE_RETA_GROUP_SIZE;
4338                 shift = i % RTE_RETA_GROUP_SIZE;
4339                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4340                                                 IXGBE_4_BIT_MASK);
4341                 if (!mask)
4342                         continue;
4343
4344                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4345                 reta = IXGBE_READ_REG(hw, reta_reg);
4346                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4347                         if (mask & (0x1 << j))
4348                                 reta_conf[idx].reta[shift + j] =
4349                                         ((reta >> (CHAR_BIT * j)) &
4350                                                 IXGBE_8_BIT_MASK);
4351                 }
4352         }
4353
4354         return 0;
4355 }
4356
4357 static void
4358 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4359                                 uint32_t index, uint32_t pool)
4360 {
4361         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4362         uint32_t enable_addr = 1;
4363
4364         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4365 }
4366
4367 static void
4368 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4369 {
4370         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4371
4372         ixgbe_clear_rar(hw, index);
4373 }
4374
4375 static void
4376 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4377 {
4378         ixgbe_remove_rar(dev, 0);
4379
4380         ixgbe_add_rar(dev, addr, 0, 0);
4381 }
4382
4383 static bool
4384 is_device_supported(struct rte_eth_dev *dev, struct eth_driver *drv)
4385 {
4386         if (strcmp(dev->driver->pci_drv.driver.name,
4387                    drv->pci_drv.driver.name))
4388                 return false;
4389
4390         return true;
4391 }
4392
4393 int
4394 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4395                 struct ether_addr *mac_addr)
4396 {
4397         struct ixgbe_hw *hw;
4398         struct ixgbe_vf_info *vfinfo;
4399         int rar_entry;
4400         uint8_t *new_mac = (uint8_t *)(mac_addr);
4401         struct rte_eth_dev *dev;
4402         struct rte_pci_device *pci_dev;
4403
4404         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4405
4406         dev = &rte_eth_devices[port];
4407         pci_dev = IXGBE_DEV_TO_PCI(dev);
4408
4409         if (!is_device_supported(dev, &rte_ixgbe_pmd))
4410                 return -ENOTSUP;
4411
4412         if (vf >= pci_dev->max_vfs)
4413                 return -EINVAL;
4414
4415         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4416         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4417         rar_entry = hw->mac.num_rar_entries - (vf + 1);
4418
4419         if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4420                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4421                                 ETHER_ADDR_LEN);
4422                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4423                                 IXGBE_RAH_AV);
4424         }
4425         return -EINVAL;
4426 }
4427
4428 static int
4429 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4430 {
4431         uint32_t hlreg0;
4432         uint32_t maxfrs;
4433         struct ixgbe_hw *hw;
4434         struct rte_eth_dev_info dev_info;
4435         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4436
4437         ixgbe_dev_info_get(dev, &dev_info);
4438
4439         /* check that mtu is within the allowed range */
4440         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4441                 return -EINVAL;
4442
4443         /* refuse mtu that requires the support of scattered packets when this
4444          * feature has not been enabled before.
4445          */
4446         if (!dev->data->scattered_rx &&
4447             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4448              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4449                 return -EINVAL;
4450
4451         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4452         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4453
4454         /* switch to jumbo mode if needed */
4455         if (frame_size > ETHER_MAX_LEN) {
4456                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4457                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4458         } else {
4459                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4460                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4461         }
4462         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4463
4464         /* update max frame size */
4465         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4466
4467         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4468         maxfrs &= 0x0000FFFF;
4469         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4470         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4471
4472         return 0;
4473 }
4474
4475 /*
4476  * Virtual Function operations
4477  */
4478 static void
4479 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4480 {
4481         PMD_INIT_FUNC_TRACE();
4482
4483         /* Clear interrupt mask to stop from interrupts being generated */
4484         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4485
4486         IXGBE_WRITE_FLUSH(hw);
4487 }
4488
4489 static void
4490 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4491 {
4492         PMD_INIT_FUNC_TRACE();
4493
4494         /* VF enable interrupt autoclean */
4495         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4496         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4497         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4498
4499         IXGBE_WRITE_FLUSH(hw);
4500 }
4501
4502 static int
4503 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4504 {
4505         struct rte_eth_conf *conf = &dev->data->dev_conf;
4506         struct ixgbe_adapter *adapter =
4507                         (struct ixgbe_adapter *)dev->data->dev_private;
4508
4509         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4510                      dev->data->port_id);
4511
4512         /*
4513          * VF has no ability to enable/disable HW CRC
4514          * Keep the persistent behavior the same as Host PF
4515          */
4516 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4517         if (!conf->rxmode.hw_strip_crc) {
4518                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4519                 conf->rxmode.hw_strip_crc = 1;
4520         }
4521 #else
4522         if (conf->rxmode.hw_strip_crc) {
4523                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4524                 conf->rxmode.hw_strip_crc = 0;
4525         }
4526 #endif
4527
4528         /*
4529          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4530          * allocation or vector Rx preconditions we will reset it.
4531          */
4532         adapter->rx_bulk_alloc_allowed = true;
4533         adapter->rx_vec_allowed = true;
4534
4535         return 0;
4536 }
4537
4538 static int
4539 ixgbevf_dev_start(struct rte_eth_dev *dev)
4540 {
4541         struct ixgbe_hw *hw =
4542                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4543         uint32_t intr_vector = 0;
4544         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4545         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4546
4547         int err, mask = 0;
4548
4549         PMD_INIT_FUNC_TRACE();
4550
4551         hw->mac.ops.reset_hw(hw);
4552         hw->mac.get_link_status = true;
4553
4554         /* negotiate mailbox API version to use with the PF. */
4555         ixgbevf_negotiate_api(hw);
4556
4557         ixgbevf_dev_tx_init(dev);
4558
4559         /* This can fail when allocating mbufs for descriptor rings */
4560         err = ixgbevf_dev_rx_init(dev);
4561         if (err) {
4562                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4563                 ixgbe_dev_clear_queues(dev);
4564                 return err;
4565         }
4566
4567         /* Set vfta */
4568         ixgbevf_set_vfta_all(dev, 1);
4569
4570         /* Set HW strip */
4571         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4572                 ETH_VLAN_EXTEND_MASK;
4573         ixgbevf_vlan_offload_set(dev, mask);
4574
4575         ixgbevf_dev_rxtx_start(dev);
4576
4577         /* check and configure queue intr-vector mapping */
4578         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4579                 intr_vector = dev->data->nb_rx_queues;
4580                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4581                         return -1;
4582         }
4583
4584         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4585                 intr_handle->intr_vec =
4586                         rte_zmalloc("intr_vec",
4587                                     dev->data->nb_rx_queues * sizeof(int), 0);
4588                 if (intr_handle->intr_vec == NULL) {
4589                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4590                                      " intr_vec", dev->data->nb_rx_queues);
4591                         return -ENOMEM;
4592                 }
4593         }
4594         ixgbevf_configure_msix(dev);
4595
4596         rte_intr_enable(intr_handle);
4597
4598         /* Re-enable interrupt for VF */
4599         ixgbevf_intr_enable(hw);
4600
4601         return 0;
4602 }
4603
4604 static void
4605 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4606 {
4607         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4608         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4609         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4610
4611         PMD_INIT_FUNC_TRACE();
4612
4613         ixgbevf_intr_disable(hw);
4614
4615         hw->adapter_stopped = 1;
4616         ixgbe_stop_adapter(hw);
4617
4618         /*
4619           * Clear what we set, but we still keep shadow_vfta to
4620           * restore after device starts
4621           */
4622         ixgbevf_set_vfta_all(dev, 0);
4623
4624         /* Clear stored conf */
4625         dev->data->scattered_rx = 0;
4626
4627         ixgbe_dev_clear_queues(dev);
4628
4629         /* Clean datapath event and queue/vec mapping */
4630         rte_intr_efd_disable(intr_handle);
4631         if (intr_handle->intr_vec != NULL) {
4632                 rte_free(intr_handle->intr_vec);
4633                 intr_handle->intr_vec = NULL;
4634         }
4635 }
4636
4637 static void
4638 ixgbevf_dev_close(struct rte_eth_dev *dev)
4639 {
4640         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4641
4642         PMD_INIT_FUNC_TRACE();
4643
4644         ixgbe_reset_hw(hw);
4645
4646         ixgbevf_dev_stop(dev);
4647
4648         ixgbe_dev_free_queues(dev);
4649
4650         /**
4651          * Remove the VF MAC address ro ensure
4652          * that the VF traffic goes to the PF
4653          * after stop, close and detach of the VF
4654          **/
4655         ixgbevf_remove_mac_addr(dev, 0);
4656 }
4657
4658 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4659 {
4660         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4661         struct ixgbe_vfta *shadow_vfta =
4662                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4663         int i = 0, j = 0, vfta = 0, mask = 1;
4664
4665         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4666                 vfta = shadow_vfta->vfta[i];
4667                 if (vfta) {
4668                         mask = 1;
4669                         for (j = 0; j < 32; j++) {
4670                                 if (vfta & mask)
4671                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4672                                                        on, false);
4673                                 mask <<= 1;
4674                         }
4675                 }
4676         }
4677
4678 }
4679
4680 static int
4681 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4682 {
4683         struct ixgbe_hw *hw =
4684                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4685         struct ixgbe_vfta *shadow_vfta =
4686                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4687         uint32_t vid_idx = 0;
4688         uint32_t vid_bit = 0;
4689         int ret = 0;
4690
4691         PMD_INIT_FUNC_TRACE();
4692
4693         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4694         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4695         if (ret) {
4696                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4697                 return ret;
4698         }
4699         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4700         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4701
4702         /* Save what we set and retore it after device reset */
4703         if (on)
4704                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4705         else
4706                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4707
4708         return 0;
4709 }
4710
4711 static void
4712 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4713 {
4714         struct ixgbe_hw *hw =
4715                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4716         uint32_t ctrl;
4717
4718         PMD_INIT_FUNC_TRACE();
4719
4720         if (queue >= hw->mac.max_rx_queues)
4721                 return;
4722
4723         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4724         if (on)
4725                 ctrl |= IXGBE_RXDCTL_VME;
4726         else
4727                 ctrl &= ~IXGBE_RXDCTL_VME;
4728         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4729
4730         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4731 }
4732
4733 static void
4734 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4735 {
4736         struct ixgbe_hw *hw =
4737                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4738         uint16_t i;
4739         int on = 0;
4740
4741         /* VF function only support hw strip feature, others are not support */
4742         if (mask & ETH_VLAN_STRIP_MASK) {
4743                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4744
4745                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4746                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4747         }
4748 }
4749
4750 static int
4751 ixgbe_vt_check(struct ixgbe_hw *hw)
4752 {
4753         uint32_t reg_val;
4754
4755         /* if Virtualization Technology is enabled */
4756         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4757         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4758                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
4759                 return -1;
4760         }
4761
4762         return 0;
4763 }
4764
4765 static uint32_t
4766 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4767 {
4768         uint32_t vector = 0;
4769
4770         switch (hw->mac.mc_filter_type) {
4771         case 0:   /* use bits [47:36] of the address */
4772                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4773                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4774                 break;
4775         case 1:   /* use bits [46:35] of the address */
4776                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4777                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4778                 break;
4779         case 2:   /* use bits [45:34] of the address */
4780                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4781                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4782                 break;
4783         case 3:   /* use bits [43:32] of the address */
4784                 vector = ((uc_addr->addr_bytes[4]) |
4785                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4786                 break;
4787         default:  /* Invalid mc_filter_type */
4788                 break;
4789         }
4790
4791         /* vector can only be 12-bits or boundary will be exceeded */
4792         vector &= 0xFFF;
4793         return vector;
4794 }
4795
4796 static int
4797 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4798                         uint8_t on)
4799 {
4800         uint32_t vector;
4801         uint32_t uta_idx;
4802         uint32_t reg_val;
4803         uint32_t uta_shift;
4804         uint32_t rc;
4805         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4806         const uint32_t ixgbe_uta_bit_shift = 5;
4807         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4808         const uint32_t bit1 = 0x1;
4809
4810         struct ixgbe_hw *hw =
4811                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4812         struct ixgbe_uta_info *uta_info =
4813                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4814
4815         /* The UTA table only exists on 82599 hardware and newer */
4816         if (hw->mac.type < ixgbe_mac_82599EB)
4817                 return -ENOTSUP;
4818
4819         vector = ixgbe_uta_vector(hw, mac_addr);
4820         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4821         uta_shift = vector & ixgbe_uta_bit_mask;
4822
4823         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4824         if (rc == on)
4825                 return 0;
4826
4827         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4828         if (on) {
4829                 uta_info->uta_in_use++;
4830                 reg_val |= (bit1 << uta_shift);
4831                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4832         } else {
4833                 uta_info->uta_in_use--;
4834                 reg_val &= ~(bit1 << uta_shift);
4835                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4836         }
4837
4838         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4839
4840         if (uta_info->uta_in_use > 0)
4841                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4842                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4843         else
4844                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4845
4846         return 0;
4847 }
4848
4849 static int
4850 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4851 {
4852         int i;
4853         struct ixgbe_hw *hw =
4854                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4855         struct ixgbe_uta_info *uta_info =
4856                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4857
4858         /* The UTA table only exists on 82599 hardware and newer */
4859         if (hw->mac.type < ixgbe_mac_82599EB)
4860                 return -ENOTSUP;
4861
4862         if (on) {
4863                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4864                         uta_info->uta_shadow[i] = ~0;
4865                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4866                 }
4867         } else {
4868                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4869                         uta_info->uta_shadow[i] = 0;
4870                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4871                 }
4872         }
4873         return 0;
4874
4875 }
4876
4877 uint32_t
4878 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4879 {
4880         uint32_t new_val = orig_val;
4881
4882         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4883                 new_val |= IXGBE_VMOLR_AUPE;
4884         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4885                 new_val |= IXGBE_VMOLR_ROMPE;
4886         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4887                 new_val |= IXGBE_VMOLR_ROPE;
4888         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4889                 new_val |= IXGBE_VMOLR_BAM;
4890         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4891                 new_val |= IXGBE_VMOLR_MPE;
4892
4893         return new_val;
4894 }
4895
4896 int
4897 rte_pmd_ixgbe_ping_vf(uint8_t port, uint16_t vf)
4898 {
4899         struct ixgbe_hw *hw;
4900         struct ixgbe_vf_info *vfinfo;
4901         struct rte_eth_dev *dev;
4902         struct rte_pci_device *pci_dev;
4903         uint32_t ctrl;
4904
4905         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4906
4907         dev = &rte_eth_devices[port];
4908         pci_dev = IXGBE_DEV_TO_PCI(dev);
4909
4910         if (!is_device_supported(dev, &rte_ixgbe_pmd))
4911                 return -ENOTSUP;
4912
4913         if (vf >= pci_dev->max_vfs)
4914                 return -EINVAL;
4915
4916         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4917         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4918
4919         ctrl = IXGBE_PF_CONTROL_MSG;
4920         if (vfinfo[vf].clear_to_send)
4921                 ctrl |= IXGBE_VT_MSGTYPE_CTS;
4922
4923         ixgbe_write_mbx(hw, &ctrl, 1, vf);
4924
4925         return 0;
4926 }
4927
4928 int
4929 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4930 {
4931         struct ixgbe_hw *hw;
4932         struct ixgbe_mac_info *mac;
4933         struct rte_eth_dev *dev;
4934         struct rte_pci_device *pci_dev;
4935
4936         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4937
4938         dev = &rte_eth_devices[port];
4939         pci_dev = IXGBE_DEV_TO_PCI(dev);
4940
4941         if (!is_device_supported(dev, &rte_ixgbe_pmd))
4942                 return -ENOTSUP;
4943
4944         if (vf >= pci_dev->max_vfs)
4945                 return -EINVAL;
4946
4947         if (on > 1)
4948                 return -EINVAL;
4949
4950         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4951         mac = &hw->mac;
4952
4953         mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4954
4955         return 0;
4956 }
4957
4958 int
4959 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4960 {
4961         struct ixgbe_hw *hw;
4962         struct ixgbe_mac_info *mac;
4963         struct rte_eth_dev *dev;
4964         struct rte_pci_device *pci_dev;
4965
4966         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4967
4968         dev = &rte_eth_devices[port];
4969         pci_dev = IXGBE_DEV_TO_PCI(dev);
4970
4971         if (!is_device_supported(dev, &rte_ixgbe_pmd))
4972                 return -ENOTSUP;
4973
4974         if (vf >= pci_dev->max_vfs)
4975                 return -EINVAL;
4976
4977         if (on > 1)
4978                 return -EINVAL;
4979
4980         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4981         mac = &hw->mac;
4982         mac->ops.set_mac_anti_spoofing(hw, on, vf);
4983
4984         return 0;
4985 }
4986
4987 int
4988 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4989 {
4990         struct ixgbe_hw *hw;
4991         uint32_t ctrl;
4992         struct rte_eth_dev *dev;
4993         struct rte_pci_device *pci_dev;
4994
4995         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4996
4997         dev = &rte_eth_devices[port];
4998         pci_dev = IXGBE_DEV_TO_PCI(dev);
4999
5000         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5001                 return -ENOTSUP;
5002
5003         if (vf >= pci_dev->max_vfs)
5004                 return -EINVAL;
5005
5006         if (vlan_id > ETHER_MAX_VLAN_ID)
5007                 return -EINVAL;
5008
5009         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5010         ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
5011         if (vlan_id) {
5012                 ctrl = vlan_id;
5013                 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
5014         } else {
5015                 ctrl = 0;
5016         }
5017
5018         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
5019
5020         return 0;
5021 }
5022
5023 int
5024 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
5025 {
5026         struct ixgbe_hw *hw;
5027         uint32_t ctrl;
5028         struct rte_eth_dev *dev;
5029
5030         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5031
5032         dev = &rte_eth_devices[port];
5033
5034         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5035                 return -ENOTSUP;
5036
5037         if (on > 1)
5038                 return -EINVAL;
5039
5040         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5041         ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5042         /* enable or disable VMDQ loopback */
5043         if (on)
5044                 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
5045         else
5046                 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
5047
5048         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
5049
5050         return 0;
5051 }
5052
5053 int
5054 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
5055 {
5056         struct ixgbe_hw *hw;
5057         uint32_t reg_value;
5058         int i;
5059         int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
5060         struct rte_eth_dev *dev;
5061
5062         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5063
5064         dev = &rte_eth_devices[port];
5065
5066         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5067                 return -ENOTSUP;
5068
5069         if (on > 1)
5070                 return -EINVAL;
5071
5072         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5073         for (i = 0; i <= num_queues; i++) {
5074                 reg_value = IXGBE_QDE_WRITE |
5075                                 (i << IXGBE_QDE_IDX_SHIFT) |
5076                                 (on & IXGBE_QDE_ENABLE);
5077                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
5078         }
5079
5080         return 0;
5081 }
5082
5083 int
5084 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
5085 {
5086         struct ixgbe_hw *hw;
5087         uint32_t reg_value;
5088         struct rte_eth_dev *dev;
5089         struct rte_pci_device *pci_dev;
5090
5091         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5092
5093         dev = &rte_eth_devices[port];
5094         pci_dev = IXGBE_DEV_TO_PCI(dev);
5095
5096         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5097                 return -ENOTSUP;
5098
5099         /* only support VF's 0 to 63 */
5100         if ((vf >= pci_dev->max_vfs) || (vf > 63))
5101                 return -EINVAL;
5102
5103         if (on > 1)
5104                 return -EINVAL;
5105
5106         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5107         reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
5108         if (on)
5109                 reg_value |= IXGBE_SRRCTL_DROP_EN;
5110         else
5111                 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
5112
5113         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
5114
5115         return 0;
5116 }
5117
5118 int
5119 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
5120 {
5121         struct rte_eth_dev *dev;
5122         struct rte_pci_device *pci_dev;
5123         struct ixgbe_hw *hw;
5124         uint16_t queues_per_pool;
5125         uint32_t q;
5126
5127         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5128
5129         dev = &rte_eth_devices[port];
5130         pci_dev = IXGBE_DEV_TO_PCI(dev);
5131         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5132
5133         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5134                 return -ENOTSUP;
5135
5136         if (vf >= pci_dev->max_vfs)
5137                 return -EINVAL;
5138
5139         if (on > 1)
5140                 return -EINVAL;
5141
5142         RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
5143
5144         /* The PF has 128 queue pairs and in SRIOV configuration
5145          * those queues will be assigned to VF's, so RXDCTL
5146          * registers will be dealing with queues which will be
5147          * assigned to VF's.
5148          * Let's say we have SRIOV configured with 31 VF's then the
5149          * first 124 queues 0-123 will be allocated to VF's and only
5150          * the last 4 queues 123-127 will be assigned to the PF.
5151          */
5152         if (hw->mac.type == ixgbe_mac_82598EB)
5153                 queues_per_pool = (uint16_t)hw->mac.max_rx_queues /
5154                                   ETH_16_POOLS;
5155         else
5156                 queues_per_pool = (uint16_t)hw->mac.max_rx_queues /
5157                                   ETH_64_POOLS;
5158
5159         for (q = 0; q < queues_per_pool; q++)
5160                 (*dev->dev_ops->vlan_strip_queue_set)(dev,
5161                                 q + vf * queues_per_pool, on);
5162         return 0;
5163 }
5164
5165 int
5166 rte_pmd_ixgbe_set_vf_rxmode(uint8_t port, uint16_t vf, uint16_t rx_mask, uint8_t on)
5167 {
5168         int val = 0;
5169         struct rte_eth_dev *dev;
5170         struct rte_pci_device *pci_dev;
5171         struct ixgbe_hw *hw;
5172         uint32_t vmolr;
5173
5174         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5175
5176         dev = &rte_eth_devices[port];
5177         pci_dev = IXGBE_DEV_TO_PCI(dev);
5178
5179         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5180                 return -ENOTSUP;
5181
5182         if (vf >= pci_dev->max_vfs)
5183                 return -EINVAL;
5184
5185         if (on > 1)
5186                 return -EINVAL;
5187
5188         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5189         vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
5190
5191         if (hw->mac.type == ixgbe_mac_82598EB) {
5192                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
5193                              " on 82599 hardware and newer");
5194                 return -ENOTSUP;
5195         }
5196         if (ixgbe_vt_check(hw) < 0)
5197                 return -ENOTSUP;
5198
5199         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
5200
5201         if (on)
5202                 vmolr |= val;
5203         else
5204                 vmolr &= ~val;
5205
5206         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
5207
5208         return 0;
5209 }
5210
5211 int
5212 rte_pmd_ixgbe_set_vf_rx(uint8_t port, uint16_t vf, uint8_t on)
5213 {
5214         struct rte_eth_dev *dev;
5215         struct rte_pci_device *pci_dev;
5216         uint32_t reg, addr;
5217         uint32_t val;
5218         const uint8_t bit1 = 0x1;
5219         struct ixgbe_hw *hw;
5220
5221         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5222
5223         dev = &rte_eth_devices[port];
5224         pci_dev = IXGBE_DEV_TO_PCI(dev);
5225
5226         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5227                 return -ENOTSUP;
5228
5229         if (vf >= pci_dev->max_vfs)
5230                 return -EINVAL;
5231
5232         if (on > 1)
5233                 return -EINVAL;
5234
5235         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5236
5237         if (ixgbe_vt_check(hw) < 0)
5238                 return -ENOTSUP;
5239
5240         /* for vf >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
5241         if (vf >= 32) {
5242                 addr = IXGBE_VFRE(1);
5243                 val = bit1 << (vf - 32);
5244         } else {
5245                 addr = IXGBE_VFRE(0);
5246                 val = bit1 << vf;
5247         }
5248
5249         reg = IXGBE_READ_REG(hw, addr);
5250
5251         if (on)
5252                 reg |= val;
5253         else
5254                 reg &= ~val;
5255
5256         IXGBE_WRITE_REG(hw, addr, reg);
5257
5258         return 0;
5259 }
5260
5261 int
5262 rte_pmd_ixgbe_set_vf_tx(uint8_t port, uint16_t vf, uint8_t on)
5263 {
5264         struct rte_eth_dev *dev;
5265         struct rte_pci_device *pci_dev;
5266         uint32_t reg, addr;
5267         uint32_t val;
5268         const uint8_t bit1 = 0x1;
5269
5270         struct ixgbe_hw *hw;
5271
5272         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5273
5274         dev = &rte_eth_devices[port];
5275         pci_dev = IXGBE_DEV_TO_PCI(dev);
5276
5277         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5278                 return -ENOTSUP;
5279
5280         if (vf >= pci_dev->max_vfs)
5281                 return -EINVAL;
5282
5283         if (on > 1)
5284                 return -EINVAL;
5285
5286         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5287         if (ixgbe_vt_check(hw) < 0)
5288                 return -ENOTSUP;
5289
5290         /* for vf >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
5291         if (vf >= 32) {
5292                 addr = IXGBE_VFTE(1);
5293                 val = bit1 << (vf - 32);
5294         } else {
5295                 addr = IXGBE_VFTE(0);
5296                 val = bit1 << vf;
5297         }
5298
5299         reg = IXGBE_READ_REG(hw, addr);
5300
5301         if (on)
5302                 reg |= val;
5303         else
5304                 reg &= ~val;
5305
5306         IXGBE_WRITE_REG(hw, addr, reg);
5307
5308         return 0;
5309 }
5310
5311 int
5312 rte_pmd_ixgbe_set_vf_vlan_filter(uint8_t port, uint16_t vlan,
5313                         uint64_t vf_mask, uint8_t vlan_on)
5314 {
5315         struct rte_eth_dev *dev;
5316         int ret = 0;
5317         uint16_t vf_idx;
5318         struct ixgbe_hw *hw;
5319
5320         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5321
5322         dev = &rte_eth_devices[port];
5323
5324         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5325                 return -ENOTSUP;
5326
5327         if ((vlan > ETHER_MAX_VLAN_ID) || (vf_mask == 0))
5328                 return -EINVAL;
5329
5330         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5331         if (ixgbe_vt_check(hw) < 0)
5332                 return -ENOTSUP;
5333
5334         for (vf_idx = 0; vf_idx < 64; vf_idx++) {
5335                 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
5336                         ret = hw->mac.ops.set_vfta(hw, vlan, vf_idx,
5337                                                    vlan_on, false);
5338                         if (ret < 0)
5339                                 return ret;
5340                 }
5341         }
5342
5343         return ret;
5344 }
5345
5346 int rte_pmd_ixgbe_set_vf_rate_limit(uint8_t port, uint16_t vf,
5347         uint16_t tx_rate, uint64_t q_msk)
5348 {
5349         struct rte_eth_dev *dev;
5350         struct ixgbe_hw *hw;
5351         struct ixgbe_vf_info *vfinfo;
5352         struct rte_eth_link link;
5353         uint8_t  nb_q_per_pool;
5354         uint32_t queue_stride;
5355         uint32_t queue_idx, idx = 0, vf_idx;
5356         uint32_t queue_end;
5357         uint16_t total_rate = 0;
5358         struct rte_pci_device *pci_dev;
5359
5360         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5361
5362         dev = &rte_eth_devices[port];
5363         pci_dev = IXGBE_DEV_TO_PCI(dev);
5364         rte_eth_link_get_nowait(port, &link);
5365
5366         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5367                 return -ENOTSUP;
5368
5369         if (vf >= pci_dev->max_vfs)
5370                 return -EINVAL;
5371
5372         if (tx_rate > link.link_speed)
5373                 return -EINVAL;
5374
5375         if (q_msk == 0)
5376                 return 0;
5377
5378         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5379         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5380         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5381         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5382         queue_idx = vf * queue_stride;
5383         queue_end = queue_idx + nb_q_per_pool - 1;
5384         if (queue_end >= hw->mac.max_tx_queues)
5385                 return -EINVAL;
5386
5387         if (vfinfo) {
5388                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5389                         if (vf_idx == vf)
5390                                 continue;
5391                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5392                                 idx++)
5393                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5394                 }
5395         } else {
5396                 return -EINVAL;
5397         }
5398
5399         /* Store tx_rate for this vf. */
5400         for (idx = 0; idx < nb_q_per_pool; idx++) {
5401                 if (((uint64_t)0x1 << idx) & q_msk) {
5402                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5403                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5404                         total_rate += tx_rate;
5405                 }
5406         }
5407
5408         if (total_rate > dev->data->dev_link.link_speed) {
5409                 /* Reset stored TX rate of the VF if it causes exceed
5410                  * link speed.
5411                  */
5412                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5413                 return -EINVAL;
5414         }
5415
5416         /* Set RTTBCNRC of each queue/pool for vf X  */
5417         for (; queue_idx <= queue_end; queue_idx++) {
5418                 if (0x1 & q_msk)
5419                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5420                 q_msk = q_msk >> 1;
5421         }
5422
5423         return 0;
5424 }
5425
5426 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5427 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5428 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5429 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5430 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5431         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5432         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5433
5434 static int
5435 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5436                         struct rte_eth_mirror_conf *mirror_conf,
5437                         uint8_t rule_id, uint8_t on)
5438 {
5439         uint32_t mr_ctl, vlvf;
5440         uint32_t mp_lsb = 0;
5441         uint32_t mv_msb = 0;
5442         uint32_t mv_lsb = 0;
5443         uint32_t mp_msb = 0;
5444         uint8_t i = 0;
5445         int reg_index = 0;
5446         uint64_t vlan_mask = 0;
5447
5448         const uint8_t pool_mask_offset = 32;
5449         const uint8_t vlan_mask_offset = 32;
5450         const uint8_t dst_pool_offset = 8;
5451         const uint8_t rule_mr_offset  = 4;
5452         const uint8_t mirror_rule_mask = 0x0F;
5453
5454         struct ixgbe_mirror_info *mr_info =
5455                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5456         struct ixgbe_hw *hw =
5457                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5458         uint8_t mirror_type = 0;
5459
5460         if (ixgbe_vt_check(hw) < 0)
5461                 return -ENOTSUP;
5462
5463         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5464                 return -EINVAL;
5465
5466         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5467                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5468                         mirror_conf->rule_type);
5469                 return -EINVAL;
5470         }
5471
5472         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5473                 mirror_type |= IXGBE_MRCTL_VLME;
5474                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5475                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5476                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5477                                 /* search vlan id related pool vlan filter index */
5478                                 reg_index = ixgbe_find_vlvf_slot(hw,
5479                                                  mirror_conf->vlan.vlan_id[i],
5480                                                  false);
5481                                 if (reg_index < 0)
5482                                         return -EINVAL;
5483                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5484                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5485                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5486                                       mirror_conf->vlan.vlan_id[i]))
5487                                         vlan_mask |= (1ULL << reg_index);
5488                                 else
5489                                         return -EINVAL;
5490                         }
5491                 }
5492
5493                 if (on) {
5494                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5495                         mv_msb = vlan_mask >> vlan_mask_offset;
5496
5497                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5498                                                 mirror_conf->vlan.vlan_mask;
5499                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5500                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5501                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5502                                                 mirror_conf->vlan.vlan_id[i];
5503                         }
5504                 } else {
5505                         mv_lsb = 0;
5506                         mv_msb = 0;
5507                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5508                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5509                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5510                 }
5511         }
5512
5513         /*
5514          * if enable pool mirror, write related pool mask register,if disable
5515          * pool mirror, clear PFMRVM register
5516          */
5517         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5518                 mirror_type |= IXGBE_MRCTL_VPME;
5519                 if (on) {
5520                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5521                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5522                         mr_info->mr_conf[rule_id].pool_mask =
5523                                         mirror_conf->pool_mask;
5524
5525                 } else {
5526                         mp_lsb = 0;
5527                         mp_msb = 0;
5528                         mr_info->mr_conf[rule_id].pool_mask = 0;
5529                 }
5530         }
5531         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5532                 mirror_type |= IXGBE_MRCTL_UPME;
5533         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5534                 mirror_type |= IXGBE_MRCTL_DPME;
5535
5536         /* read  mirror control register and recalculate it */
5537         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5538
5539         if (on) {
5540                 mr_ctl |= mirror_type;
5541                 mr_ctl &= mirror_rule_mask;
5542                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5543         } else
5544                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5545
5546         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5547         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5548
5549         /* write mirrror control  register */
5550         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5551
5552         /* write pool mirrror control  register */
5553         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5554                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5555                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5556                                 mp_msb);
5557         }
5558         /* write VLAN mirrror control  register */
5559         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5560                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5561                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5562                                 mv_msb);
5563         }
5564
5565         return 0;
5566 }
5567
5568 static int
5569 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5570 {
5571         int mr_ctl = 0;
5572         uint32_t lsb_val = 0;
5573         uint32_t msb_val = 0;
5574         const uint8_t rule_mr_offset = 4;
5575
5576         struct ixgbe_hw *hw =
5577                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5578         struct ixgbe_mirror_info *mr_info =
5579                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5580
5581         if (ixgbe_vt_check(hw) < 0)
5582                 return -ENOTSUP;
5583
5584         memset(&mr_info->mr_conf[rule_id], 0,
5585                 sizeof(struct rte_eth_mirror_conf));
5586
5587         /* clear PFVMCTL register */
5588         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5589
5590         /* clear pool mask register */
5591         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5592         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5593
5594         /* clear vlan mask register */
5595         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5596         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5597
5598         return 0;
5599 }
5600
5601 static int
5602 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5603 {
5604         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5605         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5606         uint32_t mask;
5607         struct ixgbe_hw *hw =
5608                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5609
5610         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5611         mask |= (1 << IXGBE_MISC_VEC_ID);
5612         RTE_SET_USED(queue_id);
5613         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5614
5615         rte_intr_enable(intr_handle);
5616
5617         return 0;
5618 }
5619
5620 static int
5621 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5622 {
5623         uint32_t mask;
5624         struct ixgbe_hw *hw =
5625                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5626
5627         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5628         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5629         RTE_SET_USED(queue_id);
5630         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5631
5632         return 0;
5633 }
5634
5635 static int
5636 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5637 {
5638         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5639         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5640         uint32_t mask;
5641         struct ixgbe_hw *hw =
5642                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5643         struct ixgbe_interrupt *intr =
5644                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5645
5646         if (queue_id < 16) {
5647                 ixgbe_disable_intr(hw);
5648                 intr->mask |= (1 << queue_id);
5649                 ixgbe_enable_intr(dev);
5650         } else if (queue_id < 32) {
5651                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5652                 mask &= (1 << queue_id);
5653                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5654         } else if (queue_id < 64) {
5655                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5656                 mask &= (1 << (queue_id - 32));
5657                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5658         }
5659         rte_intr_enable(intr_handle);
5660
5661         return 0;
5662 }
5663
5664 static int
5665 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5666 {
5667         uint32_t mask;
5668         struct ixgbe_hw *hw =
5669                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5670         struct ixgbe_interrupt *intr =
5671                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5672
5673         if (queue_id < 16) {
5674                 ixgbe_disable_intr(hw);
5675                 intr->mask &= ~(1 << queue_id);
5676                 ixgbe_enable_intr(dev);
5677         } else if (queue_id < 32) {
5678                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5679                 mask &= ~(1 << queue_id);
5680                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5681         } else if (queue_id < 64) {
5682                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5683                 mask &= ~(1 << (queue_id - 32));
5684                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5685         }
5686
5687         return 0;
5688 }
5689
5690 static void
5691 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5692                      uint8_t queue, uint8_t msix_vector)
5693 {
5694         uint32_t tmp, idx;
5695
5696         if (direction == -1) {
5697                 /* other causes */
5698                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5699                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5700                 tmp &= ~0xFF;
5701                 tmp |= msix_vector;
5702                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5703         } else {
5704                 /* rx or tx cause */
5705                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5706                 idx = ((16 * (queue & 1)) + (8 * direction));
5707                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5708                 tmp &= ~(0xFF << idx);
5709                 tmp |= (msix_vector << idx);
5710                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5711         }
5712 }
5713
5714 /**
5715  * set the IVAR registers, mapping interrupt causes to vectors
5716  * @param hw
5717  *  pointer to ixgbe_hw struct
5718  * @direction
5719  *  0 for Rx, 1 for Tx, -1 for other causes
5720  * @queue
5721  *  queue to map the corresponding interrupt to
5722  * @msix_vector
5723  *  the vector to map to the corresponding queue
5724  */
5725 static void
5726 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5727                    uint8_t queue, uint8_t msix_vector)
5728 {
5729         uint32_t tmp, idx;
5730
5731         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5732         if (hw->mac.type == ixgbe_mac_82598EB) {
5733                 if (direction == -1)
5734                         direction = 0;
5735                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5736                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5737                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5738                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5739                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5740         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5741                         (hw->mac.type == ixgbe_mac_X540)) {
5742                 if (direction == -1) {
5743                         /* other causes */
5744                         idx = ((queue & 1) * 8);
5745                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5746                         tmp &= ~(0xFF << idx);
5747                         tmp |= (msix_vector << idx);
5748                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5749                 } else {
5750                         /* rx or tx causes */
5751                         idx = ((16 * (queue & 1)) + (8 * direction));
5752                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5753                         tmp &= ~(0xFF << idx);
5754                         tmp |= (msix_vector << idx);
5755                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5756                 }
5757         }
5758 }
5759
5760 static void
5761 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5762 {
5763         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5764         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5765         struct ixgbe_hw *hw =
5766                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5767         uint32_t q_idx;
5768         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5769
5770         /* Configure VF other cause ivar */
5771         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5772
5773         /* won't configure msix register if no mapping is done
5774          * between intr vector and event fd.
5775          */
5776         if (!rte_intr_dp_is_en(intr_handle))
5777                 return;
5778
5779         /* Configure all RX queues of VF */
5780         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5781                 /* Force all queue use vector 0,
5782                  * as IXGBE_VF_MAXMSIVECOTR = 1
5783                  */
5784                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5785                 intr_handle->intr_vec[q_idx] = vector_idx;
5786         }
5787 }
5788
5789 /**
5790  * Sets up the hardware to properly generate MSI-X interrupts
5791  * @hw
5792  *  board private structure
5793  */
5794 static void
5795 ixgbe_configure_msix(struct rte_eth_dev *dev)
5796 {
5797         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5798         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5799         struct ixgbe_hw *hw =
5800                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5801         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5802         uint32_t vec = IXGBE_MISC_VEC_ID;
5803         uint32_t mask;
5804         uint32_t gpie;
5805
5806         /* won't configure msix register if no mapping is done
5807          * between intr vector and event fd
5808          */
5809         if (!rte_intr_dp_is_en(intr_handle))
5810                 return;
5811
5812         if (rte_intr_allow_others(intr_handle))
5813                 vec = base = IXGBE_RX_VEC_START;
5814
5815         /* setup GPIE for MSI-x mode */
5816         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5817         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5818                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5819         /* auto clearing and auto setting corresponding bits in EIMS
5820          * when MSI-X interrupt is triggered
5821          */
5822         if (hw->mac.type == ixgbe_mac_82598EB) {
5823                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5824         } else {
5825                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5826                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5827         }
5828         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5829
5830         /* Populate the IVAR table and set the ITR values to the
5831          * corresponding register.
5832          */
5833         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5834              queue_id++) {
5835                 /* by default, 1:1 mapping */
5836                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5837                 intr_handle->intr_vec[queue_id] = vec;
5838                 if (vec < base + intr_handle->nb_efd - 1)
5839                         vec++;
5840         }
5841
5842         switch (hw->mac.type) {
5843         case ixgbe_mac_82598EB:
5844                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5845                                    IXGBE_MISC_VEC_ID);
5846                 break;
5847         case ixgbe_mac_82599EB:
5848         case ixgbe_mac_X540:
5849                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5850                 break;
5851         default:
5852                 break;
5853         }
5854         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5855                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5856
5857         /* set up to autoclear timer, and the vectors */
5858         mask = IXGBE_EIMS_ENABLE_MASK;
5859         mask &= ~(IXGBE_EIMS_OTHER |
5860                   IXGBE_EIMS_MAILBOX |
5861                   IXGBE_EIMS_LSC);
5862
5863         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5864 }
5865
5866 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5867         uint16_t queue_idx, uint16_t tx_rate)
5868 {
5869         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5870         uint32_t rf_dec, rf_int;
5871         uint32_t bcnrc_val;
5872         uint16_t link_speed = dev->data->dev_link.link_speed;
5873
5874         if (queue_idx >= hw->mac.max_tx_queues)
5875                 return -EINVAL;
5876
5877         if (tx_rate != 0) {
5878                 /* Calculate the rate factor values to set */
5879                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5880                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5881                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5882
5883                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5884                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5885                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5886                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5887         } else {
5888                 bcnrc_val = 0;
5889         }
5890
5891         /*
5892          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5893          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5894          * set as 0x4.
5895          */
5896         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5897                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5898                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5899                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5900                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5901         else
5902                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5903                         IXGBE_MMW_SIZE_DEFAULT);
5904
5905         /* Set RTTBCNRC of queue X */
5906         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5907         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5908         IXGBE_WRITE_FLUSH(hw);
5909
5910         return 0;
5911 }
5912
5913 static void
5914 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5915                      __attribute__((unused)) uint32_t index,
5916                      __attribute__((unused)) uint32_t pool)
5917 {
5918         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5919         int diag;
5920
5921         /*
5922          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5923          * operation. Trap this case to avoid exhausting the [very limited]
5924          * set of PF resources used to store VF MAC addresses.
5925          */
5926         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5927                 return;
5928         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5929         if (diag == 0)
5930                 return;
5931         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5932 }
5933
5934 static void
5935 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5936 {
5937         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5938         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5939         struct ether_addr *mac_addr;
5940         uint32_t i;
5941         int diag;
5942
5943         /*
5944          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5945          * not support the deletion of a given MAC address.
5946          * Instead, it imposes to delete all MAC addresses, then to add again
5947          * all MAC addresses with the exception of the one to be deleted.
5948          */
5949         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5950
5951         /*
5952          * Add again all MAC addresses, with the exception of the deleted one
5953          * and of the permanent MAC address.
5954          */
5955         for (i = 0, mac_addr = dev->data->mac_addrs;
5956              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5957                 /* Skip the deleted MAC address */
5958                 if (i == index)
5959                         continue;
5960                 /* Skip NULL MAC addresses */
5961                 if (is_zero_ether_addr(mac_addr))
5962                         continue;
5963                 /* Skip the permanent MAC address */
5964                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5965                         continue;
5966                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5967                 if (diag != 0)
5968                         PMD_DRV_LOG(ERR,
5969                                     "Adding again MAC address "
5970                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5971                                     "diag=%d",
5972                                     mac_addr->addr_bytes[0],
5973                                     mac_addr->addr_bytes[1],
5974                                     mac_addr->addr_bytes[2],
5975                                     mac_addr->addr_bytes[3],
5976                                     mac_addr->addr_bytes[4],
5977                                     mac_addr->addr_bytes[5],
5978                                     diag);
5979         }
5980 }
5981
5982 static void
5983 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5984 {
5985         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5986
5987         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5988 }
5989
5990 int
5991 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5992                         struct rte_eth_syn_filter *filter,
5993                         bool add)
5994 {
5995         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5996         struct ixgbe_filter_info *filter_info =
5997                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5998         uint32_t syn_info;
5999         uint32_t synqf;
6000
6001         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6002                 return -EINVAL;
6003
6004         syn_info = filter_info->syn_info;
6005
6006         if (add) {
6007                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6008                         return -EINVAL;
6009                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6010                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6011
6012                 if (filter->hig_pri)
6013                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6014                 else
6015                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6016         } else {
6017                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6018                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6019                         return -ENOENT;
6020                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6021         }
6022
6023         filter_info->syn_info = synqf;
6024         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6025         IXGBE_WRITE_FLUSH(hw);
6026         return 0;
6027 }
6028
6029 static int
6030 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6031                         struct rte_eth_syn_filter *filter)
6032 {
6033         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6034         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6035
6036         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6037                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6038                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6039                 return 0;
6040         }
6041         return -ENOENT;
6042 }
6043
6044 static int
6045 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6046                         enum rte_filter_op filter_op,
6047                         void *arg)
6048 {
6049         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6050         int ret;
6051
6052         MAC_TYPE_FILTER_SUP(hw->mac.type);
6053
6054         if (filter_op == RTE_ETH_FILTER_NOP)
6055                 return 0;
6056
6057         if (arg == NULL) {
6058                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6059                             filter_op);
6060                 return -EINVAL;
6061         }
6062
6063         switch (filter_op) {
6064         case RTE_ETH_FILTER_ADD:
6065                 ret = ixgbe_syn_filter_set(dev,
6066                                 (struct rte_eth_syn_filter *)arg,
6067                                 TRUE);
6068                 break;
6069         case RTE_ETH_FILTER_DELETE:
6070                 ret = ixgbe_syn_filter_set(dev,
6071                                 (struct rte_eth_syn_filter *)arg,
6072                                 FALSE);
6073                 break;
6074         case RTE_ETH_FILTER_GET:
6075                 ret = ixgbe_syn_filter_get(dev,
6076                                 (struct rte_eth_syn_filter *)arg);
6077                 break;
6078         default:
6079                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6080                 ret = -EINVAL;
6081                 break;
6082         }
6083
6084         return ret;
6085 }
6086
6087
6088 static inline enum ixgbe_5tuple_protocol
6089 convert_protocol_type(uint8_t protocol_value)
6090 {
6091         if (protocol_value == IPPROTO_TCP)
6092                 return IXGBE_FILTER_PROTOCOL_TCP;
6093         else if (protocol_value == IPPROTO_UDP)
6094                 return IXGBE_FILTER_PROTOCOL_UDP;
6095         else if (protocol_value == IPPROTO_SCTP)
6096                 return IXGBE_FILTER_PROTOCOL_SCTP;
6097         else
6098                 return IXGBE_FILTER_PROTOCOL_NONE;
6099 }
6100
6101 /* inject a 5-tuple filter to HW */
6102 static inline void
6103 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6104                            struct ixgbe_5tuple_filter *filter)
6105 {
6106         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6107         int i;
6108         uint32_t ftqf, sdpqf;
6109         uint32_t l34timir = 0;
6110         uint8_t mask = 0xff;
6111
6112         i = filter->index;
6113
6114         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6115                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6116         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6117
6118         ftqf = (uint32_t)(filter->filter_info.proto &
6119                 IXGBE_FTQF_PROTOCOL_MASK);
6120         ftqf |= (uint32_t)((filter->filter_info.priority &
6121                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6122         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6123                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6124         if (filter->filter_info.dst_ip_mask == 0)
6125                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6126         if (filter->filter_info.src_port_mask == 0)
6127                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6128         if (filter->filter_info.dst_port_mask == 0)
6129                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6130         if (filter->filter_info.proto_mask == 0)
6131                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6132         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6133         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6134         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6135
6136         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6137         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6138         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6139         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6140
6141         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6142         l34timir |= (uint32_t)(filter->queue <<
6143                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6144         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6145 }
6146
6147 /*
6148  * add a 5tuple filter
6149  *
6150  * @param
6151  * dev: Pointer to struct rte_eth_dev.
6152  * index: the index the filter allocates.
6153  * filter: ponter to the filter that will be added.
6154  * rx_queue: the queue id the filter assigned to.
6155  *
6156  * @return
6157  *    - On success, zero.
6158  *    - On failure, a negative value.
6159  */
6160 static int
6161 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6162                         struct ixgbe_5tuple_filter *filter)
6163 {
6164         struct ixgbe_filter_info *filter_info =
6165                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6166         int i, idx, shift;
6167
6168         /*
6169          * look for an unused 5tuple filter index,
6170          * and insert the filter to list.
6171          */
6172         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6173                 idx = i / (sizeof(uint32_t) * NBBY);
6174                 shift = i % (sizeof(uint32_t) * NBBY);
6175                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6176                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6177                         filter->index = i;
6178                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6179                                           filter,
6180                                           entries);
6181                         break;
6182                 }
6183         }
6184         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6185                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6186                 return -ENOSYS;
6187         }
6188
6189         ixgbe_inject_5tuple_filter(dev, filter);
6190
6191         return 0;
6192 }
6193
6194 /*
6195  * remove a 5tuple filter
6196  *
6197  * @param
6198  * dev: Pointer to struct rte_eth_dev.
6199  * filter: the pointer of the filter will be removed.
6200  */
6201 static void
6202 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6203                         struct ixgbe_5tuple_filter *filter)
6204 {
6205         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6206         struct ixgbe_filter_info *filter_info =
6207                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6208         uint16_t index = filter->index;
6209
6210         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6211                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6212         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6213         rte_free(filter);
6214
6215         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6216         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6217         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6218         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6219         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6220 }
6221
6222 static int
6223 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6224 {
6225         struct ixgbe_hw *hw;
6226         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6227
6228         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6229
6230         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6231                 return -EINVAL;
6232
6233         /* refuse mtu that requires the support of scattered packets when this
6234          * feature has not been enabled before.
6235          */
6236         if (!dev->data->scattered_rx &&
6237             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6238              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6239                 return -EINVAL;
6240
6241         /*
6242          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6243          * request of the version 2.0 of the mailbox API.
6244          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6245          * of the mailbox API.
6246          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6247          * prior to 3.11.33 which contains the following change:
6248          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6249          */
6250         ixgbevf_rlpml_set_vf(hw, max_frame);
6251
6252         /* update max frame size */
6253         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6254         return 0;
6255 }
6256
6257 static inline struct ixgbe_5tuple_filter *
6258 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6259                         struct ixgbe_5tuple_filter_info *key)
6260 {
6261         struct ixgbe_5tuple_filter *it;
6262
6263         TAILQ_FOREACH(it, filter_list, entries) {
6264                 if (memcmp(key, &it->filter_info,
6265                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6266                         return it;
6267                 }
6268         }
6269         return NULL;
6270 }
6271
6272 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6273 static inline int
6274 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6275                         struct ixgbe_5tuple_filter_info *filter_info)
6276 {
6277         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6278                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6279                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6280                 return -EINVAL;
6281
6282         switch (filter->dst_ip_mask) {
6283         case UINT32_MAX:
6284                 filter_info->dst_ip_mask = 0;
6285                 filter_info->dst_ip = filter->dst_ip;
6286                 break;
6287         case 0:
6288                 filter_info->dst_ip_mask = 1;
6289                 break;
6290         default:
6291                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6292                 return -EINVAL;
6293         }
6294
6295         switch (filter->src_ip_mask) {
6296         case UINT32_MAX:
6297                 filter_info->src_ip_mask = 0;
6298                 filter_info->src_ip = filter->src_ip;
6299                 break;
6300         case 0:
6301                 filter_info->src_ip_mask = 1;
6302                 break;
6303         default:
6304                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6305                 return -EINVAL;
6306         }
6307
6308         switch (filter->dst_port_mask) {
6309         case UINT16_MAX:
6310                 filter_info->dst_port_mask = 0;
6311                 filter_info->dst_port = filter->dst_port;
6312                 break;
6313         case 0:
6314                 filter_info->dst_port_mask = 1;
6315                 break;
6316         default:
6317                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6318                 return -EINVAL;
6319         }
6320
6321         switch (filter->src_port_mask) {
6322         case UINT16_MAX:
6323                 filter_info->src_port_mask = 0;
6324                 filter_info->src_port = filter->src_port;
6325                 break;
6326         case 0:
6327                 filter_info->src_port_mask = 1;
6328                 break;
6329         default:
6330                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6331                 return -EINVAL;
6332         }
6333
6334         switch (filter->proto_mask) {
6335         case UINT8_MAX:
6336                 filter_info->proto_mask = 0;
6337                 filter_info->proto =
6338                         convert_protocol_type(filter->proto);
6339                 break;
6340         case 0:
6341                 filter_info->proto_mask = 1;
6342                 break;
6343         default:
6344                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6345                 return -EINVAL;
6346         }
6347
6348         filter_info->priority = (uint8_t)filter->priority;
6349         return 0;
6350 }
6351
6352 /*
6353  * add or delete a ntuple filter
6354  *
6355  * @param
6356  * dev: Pointer to struct rte_eth_dev.
6357  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6358  * add: if true, add filter, if false, remove filter
6359  *
6360  * @return
6361  *    - On success, zero.
6362  *    - On failure, a negative value.
6363  */
6364 int
6365 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6366                         struct rte_eth_ntuple_filter *ntuple_filter,
6367                         bool add)
6368 {
6369         struct ixgbe_filter_info *filter_info =
6370                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6371         struct ixgbe_5tuple_filter_info filter_5tuple;
6372         struct ixgbe_5tuple_filter *filter;
6373         int ret;
6374
6375         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6376                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6377                 return -EINVAL;
6378         }
6379
6380         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6381         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6382         if (ret < 0)
6383                 return ret;
6384
6385         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6386                                          &filter_5tuple);
6387         if (filter != NULL && add) {
6388                 PMD_DRV_LOG(ERR, "filter exists.");
6389                 return -EEXIST;
6390         }
6391         if (filter == NULL && !add) {
6392                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6393                 return -ENOENT;
6394         }
6395
6396         if (add) {
6397                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6398                                 sizeof(struct ixgbe_5tuple_filter), 0);
6399                 if (filter == NULL)
6400                         return -ENOMEM;
6401                 (void)rte_memcpy(&filter->filter_info,
6402                                  &filter_5tuple,
6403                                  sizeof(struct ixgbe_5tuple_filter_info));
6404                 filter->queue = ntuple_filter->queue;
6405                 ret = ixgbe_add_5tuple_filter(dev, filter);
6406                 if (ret < 0) {
6407                         rte_free(filter);
6408                         return ret;
6409                 }
6410         } else
6411                 ixgbe_remove_5tuple_filter(dev, filter);
6412
6413         return 0;
6414 }
6415
6416 /*
6417  * get a ntuple filter
6418  *
6419  * @param
6420  * dev: Pointer to struct rte_eth_dev.
6421  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6422  *
6423  * @return
6424  *    - On success, zero.
6425  *    - On failure, a negative value.
6426  */
6427 static int
6428 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6429                         struct rte_eth_ntuple_filter *ntuple_filter)
6430 {
6431         struct ixgbe_filter_info *filter_info =
6432                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6433         struct ixgbe_5tuple_filter_info filter_5tuple;
6434         struct ixgbe_5tuple_filter *filter;
6435         int ret;
6436
6437         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6438                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6439                 return -EINVAL;
6440         }
6441
6442         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6443         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6444         if (ret < 0)
6445                 return ret;
6446
6447         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6448                                          &filter_5tuple);
6449         if (filter == NULL) {
6450                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6451                 return -ENOENT;
6452         }
6453         ntuple_filter->queue = filter->queue;
6454         return 0;
6455 }
6456
6457 /*
6458  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6459  * @dev: pointer to rte_eth_dev structure
6460  * @filter_op:operation will be taken.
6461  * @arg: a pointer to specific structure corresponding to the filter_op
6462  *
6463  * @return
6464  *    - On success, zero.
6465  *    - On failure, a negative value.
6466  */
6467 static int
6468 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6469                                 enum rte_filter_op filter_op,
6470                                 void *arg)
6471 {
6472         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6473         int ret;
6474
6475         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6476
6477         if (filter_op == RTE_ETH_FILTER_NOP)
6478                 return 0;
6479
6480         if (arg == NULL) {
6481                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6482                             filter_op);
6483                 return -EINVAL;
6484         }
6485
6486         switch (filter_op) {
6487         case RTE_ETH_FILTER_ADD:
6488                 ret = ixgbe_add_del_ntuple_filter(dev,
6489                         (struct rte_eth_ntuple_filter *)arg,
6490                         TRUE);
6491                 break;
6492         case RTE_ETH_FILTER_DELETE:
6493                 ret = ixgbe_add_del_ntuple_filter(dev,
6494                         (struct rte_eth_ntuple_filter *)arg,
6495                         FALSE);
6496                 break;
6497         case RTE_ETH_FILTER_GET:
6498                 ret = ixgbe_get_ntuple_filter(dev,
6499                         (struct rte_eth_ntuple_filter *)arg);
6500                 break;
6501         default:
6502                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6503                 ret = -EINVAL;
6504                 break;
6505         }
6506         return ret;
6507 }
6508
6509 int
6510 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6511                         struct rte_eth_ethertype_filter *filter,
6512                         bool add)
6513 {
6514         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6515         struct ixgbe_filter_info *filter_info =
6516                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6517         uint32_t etqf = 0;
6518         uint32_t etqs = 0;
6519         int ret;
6520         struct ixgbe_ethertype_filter ethertype_filter;
6521
6522         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6523                 return -EINVAL;
6524
6525         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6526                 filter->ether_type == ETHER_TYPE_IPv6) {
6527                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6528                         " ethertype filter.", filter->ether_type);
6529                 return -EINVAL;
6530         }
6531
6532         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6533                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6534                 return -EINVAL;
6535         }
6536         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6537                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6538                 return -EINVAL;
6539         }
6540
6541         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6542         if (ret >= 0 && add) {
6543                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6544                             filter->ether_type);
6545                 return -EEXIST;
6546         }
6547         if (ret < 0 && !add) {
6548                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6549                             filter->ether_type);
6550                 return -ENOENT;
6551         }
6552
6553         if (add) {
6554                 etqf = IXGBE_ETQF_FILTER_EN;
6555                 etqf |= (uint32_t)filter->ether_type;
6556                 etqs |= (uint32_t)((filter->queue <<
6557                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6558                                     IXGBE_ETQS_RX_QUEUE);
6559                 etqs |= IXGBE_ETQS_QUEUE_EN;
6560
6561                 ethertype_filter.ethertype = filter->ether_type;
6562                 ethertype_filter.etqf = etqf;
6563                 ethertype_filter.etqs = etqs;
6564                 ethertype_filter.conf = FALSE;
6565                 ret = ixgbe_ethertype_filter_insert(filter_info,
6566                                                     &ethertype_filter);
6567                 if (ret < 0) {
6568                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6569                         return -ENOSPC;
6570                 }
6571         } else {
6572                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6573                 if (ret < 0)
6574                         return -ENOSYS;
6575         }
6576         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6577         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6578         IXGBE_WRITE_FLUSH(hw);
6579
6580         return 0;
6581 }
6582
6583 static int
6584 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6585                         struct rte_eth_ethertype_filter *filter)
6586 {
6587         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6588         struct ixgbe_filter_info *filter_info =
6589                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6590         uint32_t etqf, etqs;
6591         int ret;
6592
6593         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6594         if (ret < 0) {
6595                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6596                             filter->ether_type);
6597                 return -ENOENT;
6598         }
6599
6600         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6601         if (etqf & IXGBE_ETQF_FILTER_EN) {
6602                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6603                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6604                 filter->flags = 0;
6605                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6606                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6607                 return 0;
6608         }
6609         return -ENOENT;
6610 }
6611
6612 /*
6613  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6614  * @dev: pointer to rte_eth_dev structure
6615  * @filter_op:operation will be taken.
6616  * @arg: a pointer to specific structure corresponding to the filter_op
6617  */
6618 static int
6619 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6620                                 enum rte_filter_op filter_op,
6621                                 void *arg)
6622 {
6623         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6624         int ret;
6625
6626         MAC_TYPE_FILTER_SUP(hw->mac.type);
6627
6628         if (filter_op == RTE_ETH_FILTER_NOP)
6629                 return 0;
6630
6631         if (arg == NULL) {
6632                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6633                             filter_op);
6634                 return -EINVAL;
6635         }
6636
6637         switch (filter_op) {
6638         case RTE_ETH_FILTER_ADD:
6639                 ret = ixgbe_add_del_ethertype_filter(dev,
6640                         (struct rte_eth_ethertype_filter *)arg,
6641                         TRUE);
6642                 break;
6643         case RTE_ETH_FILTER_DELETE:
6644                 ret = ixgbe_add_del_ethertype_filter(dev,
6645                         (struct rte_eth_ethertype_filter *)arg,
6646                         FALSE);
6647                 break;
6648         case RTE_ETH_FILTER_GET:
6649                 ret = ixgbe_get_ethertype_filter(dev,
6650                         (struct rte_eth_ethertype_filter *)arg);
6651                 break;
6652         default:
6653                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6654                 ret = -EINVAL;
6655                 break;
6656         }
6657         return ret;
6658 }
6659
6660 static int
6661 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6662                      enum rte_filter_type filter_type,
6663                      enum rte_filter_op filter_op,
6664                      void *arg)
6665 {
6666         int ret = 0;
6667
6668         switch (filter_type) {
6669         case RTE_ETH_FILTER_NTUPLE:
6670                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6671                 break;
6672         case RTE_ETH_FILTER_ETHERTYPE:
6673                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6674                 break;
6675         case RTE_ETH_FILTER_SYN:
6676                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6677                 break;
6678         case RTE_ETH_FILTER_FDIR:
6679                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6680                 break;
6681         case RTE_ETH_FILTER_L2_TUNNEL:
6682                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6683                 break;
6684         case RTE_ETH_FILTER_GENERIC:
6685                 if (filter_op != RTE_ETH_FILTER_GET)
6686                         return -EINVAL;
6687                 *(const void **)arg = &ixgbe_flow_ops;
6688                 break;
6689         default:
6690                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6691                                                         filter_type);
6692                 ret = -EINVAL;
6693                 break;
6694         }
6695
6696         return ret;
6697 }
6698
6699 static u8 *
6700 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6701                         u8 **mc_addr_ptr, u32 *vmdq)
6702 {
6703         u8 *mc_addr;
6704
6705         *vmdq = 0;
6706         mc_addr = *mc_addr_ptr;
6707         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6708         return mc_addr;
6709 }
6710
6711 static int
6712 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6713                           struct ether_addr *mc_addr_set,
6714                           uint32_t nb_mc_addr)
6715 {
6716         struct ixgbe_hw *hw;
6717         u8 *mc_addr_list;
6718
6719         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6720         mc_addr_list = (u8 *)mc_addr_set;
6721         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6722                                          ixgbe_dev_addr_list_itr, TRUE);
6723 }
6724
6725 static uint64_t
6726 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6727 {
6728         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6729         uint64_t systime_cycles;
6730
6731         switch (hw->mac.type) {
6732         case ixgbe_mac_X550:
6733         case ixgbe_mac_X550EM_x:
6734         case ixgbe_mac_X550EM_a:
6735                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6736                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6737                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6738                                 * NSEC_PER_SEC;
6739                 break;
6740         default:
6741                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6742                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6743                                 << 32;
6744         }
6745
6746         return systime_cycles;
6747 }
6748
6749 static uint64_t
6750 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6751 {
6752         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6753         uint64_t rx_tstamp_cycles;
6754
6755         switch (hw->mac.type) {
6756         case ixgbe_mac_X550:
6757         case ixgbe_mac_X550EM_x:
6758         case ixgbe_mac_X550EM_a:
6759                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6760                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6761                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6762                                 * NSEC_PER_SEC;
6763                 break;
6764         default:
6765                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6766                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6767                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6768                                 << 32;
6769         }
6770
6771         return rx_tstamp_cycles;
6772 }
6773
6774 static uint64_t
6775 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6776 {
6777         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6778         uint64_t tx_tstamp_cycles;
6779
6780         switch (hw->mac.type) {
6781         case ixgbe_mac_X550:
6782         case ixgbe_mac_X550EM_x:
6783         case ixgbe_mac_X550EM_a:
6784                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6785                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6786                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6787                                 * NSEC_PER_SEC;
6788                 break;
6789         default:
6790                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6791                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6792                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6793                                 << 32;
6794         }
6795
6796         return tx_tstamp_cycles;
6797 }
6798
6799 static void
6800 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6801 {
6802         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6803         struct ixgbe_adapter *adapter =
6804                 (struct ixgbe_adapter *)dev->data->dev_private;
6805         struct rte_eth_link link;
6806         uint32_t incval = 0;
6807         uint32_t shift = 0;
6808
6809         /* Get current link speed. */
6810         memset(&link, 0, sizeof(link));
6811         ixgbe_dev_link_update(dev, 1);
6812         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6813
6814         switch (link.link_speed) {
6815         case ETH_SPEED_NUM_100M:
6816                 incval = IXGBE_INCVAL_100;
6817                 shift = IXGBE_INCVAL_SHIFT_100;
6818                 break;
6819         case ETH_SPEED_NUM_1G:
6820                 incval = IXGBE_INCVAL_1GB;
6821                 shift = IXGBE_INCVAL_SHIFT_1GB;
6822                 break;
6823         case ETH_SPEED_NUM_10G:
6824         default:
6825                 incval = IXGBE_INCVAL_10GB;
6826                 shift = IXGBE_INCVAL_SHIFT_10GB;
6827                 break;
6828         }
6829
6830         switch (hw->mac.type) {
6831         case ixgbe_mac_X550:
6832         case ixgbe_mac_X550EM_x:
6833         case ixgbe_mac_X550EM_a:
6834                 /* Independent of link speed. */
6835                 incval = 1;
6836                 /* Cycles read will be interpreted as ns. */
6837                 shift = 0;
6838                 /* Fall-through */
6839         case ixgbe_mac_X540:
6840                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6841                 break;
6842         case ixgbe_mac_82599EB:
6843                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6844                 shift -= IXGBE_INCVAL_SHIFT_82599;
6845                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6846                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6847                 break;
6848         default:
6849                 /* Not supported. */
6850                 return;
6851         }
6852
6853         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6854         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6855         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6856
6857         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6858         adapter->systime_tc.cc_shift = shift;
6859         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6860
6861         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6862         adapter->rx_tstamp_tc.cc_shift = shift;
6863         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6864
6865         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6866         adapter->tx_tstamp_tc.cc_shift = shift;
6867         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6868 }
6869
6870 static int
6871 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6872 {
6873         struct ixgbe_adapter *adapter =
6874                         (struct ixgbe_adapter *)dev->data->dev_private;
6875
6876         adapter->systime_tc.nsec += delta;
6877         adapter->rx_tstamp_tc.nsec += delta;
6878         adapter->tx_tstamp_tc.nsec += delta;
6879
6880         return 0;
6881 }
6882
6883 static int
6884 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6885 {
6886         uint64_t ns;
6887         struct ixgbe_adapter *adapter =
6888                         (struct ixgbe_adapter *)dev->data->dev_private;
6889
6890         ns = rte_timespec_to_ns(ts);
6891         /* Set the timecounters to a new value. */
6892         adapter->systime_tc.nsec = ns;
6893         adapter->rx_tstamp_tc.nsec = ns;
6894         adapter->tx_tstamp_tc.nsec = ns;
6895
6896         return 0;
6897 }
6898
6899 static int
6900 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6901 {
6902         uint64_t ns, systime_cycles;
6903         struct ixgbe_adapter *adapter =
6904                         (struct ixgbe_adapter *)dev->data->dev_private;
6905
6906         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6907         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6908         *ts = rte_ns_to_timespec(ns);
6909
6910         return 0;
6911 }
6912
6913 static int
6914 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6915 {
6916         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6917         uint32_t tsync_ctl;
6918         uint32_t tsauxc;
6919
6920         /* Stop the timesync system time. */
6921         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6922         /* Reset the timesync system time value. */
6923         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6924         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6925
6926         /* Enable system time for platforms where it isn't on by default. */
6927         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6928         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6929         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6930
6931         ixgbe_start_timecounters(dev);
6932
6933         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6934         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6935                         (ETHER_TYPE_1588 |
6936                          IXGBE_ETQF_FILTER_EN |
6937                          IXGBE_ETQF_1588));
6938
6939         /* Enable timestamping of received PTP packets. */
6940         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6941         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6942         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6943
6944         /* Enable timestamping of transmitted PTP packets. */
6945         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6946         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6947         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6948
6949         IXGBE_WRITE_FLUSH(hw);
6950
6951         return 0;
6952 }
6953
6954 static int
6955 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6956 {
6957         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6958         uint32_t tsync_ctl;
6959
6960         /* Disable timestamping of transmitted PTP packets. */
6961         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6962         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6963         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6964
6965         /* Disable timestamping of received PTP packets. */
6966         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6967         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6968         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6969
6970         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6971         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6972
6973         /* Stop incrementating the System Time registers. */
6974         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6975
6976         return 0;
6977 }
6978
6979 static int
6980 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6981                                  struct timespec *timestamp,
6982                                  uint32_t flags __rte_unused)
6983 {
6984         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6985         struct ixgbe_adapter *adapter =
6986                 (struct ixgbe_adapter *)dev->data->dev_private;
6987         uint32_t tsync_rxctl;
6988         uint64_t rx_tstamp_cycles;
6989         uint64_t ns;
6990
6991         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6992         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6993                 return -EINVAL;
6994
6995         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6996         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6997         *timestamp = rte_ns_to_timespec(ns);
6998
6999         return  0;
7000 }
7001
7002 static int
7003 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7004                                  struct timespec *timestamp)
7005 {
7006         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7007         struct ixgbe_adapter *adapter =
7008                 (struct ixgbe_adapter *)dev->data->dev_private;
7009         uint32_t tsync_txctl;
7010         uint64_t tx_tstamp_cycles;
7011         uint64_t ns;
7012
7013         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7014         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7015                 return -EINVAL;
7016
7017         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7018         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7019         *timestamp = rte_ns_to_timespec(ns);
7020
7021         return 0;
7022 }
7023
7024 static int
7025 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7026 {
7027         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7028         int count = 0;
7029         int g_ind = 0;
7030         const struct reg_info *reg_group;
7031         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7032                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7033
7034         while ((reg_group = reg_set[g_ind++]))
7035                 count += ixgbe_regs_group_count(reg_group);
7036
7037         return count;
7038 }
7039
7040 static int
7041 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7042 {
7043         int count = 0;
7044         int g_ind = 0;
7045         const struct reg_info *reg_group;
7046
7047         while ((reg_group = ixgbevf_regs[g_ind++]))
7048                 count += ixgbe_regs_group_count(reg_group);
7049
7050         return count;
7051 }
7052
7053 static int
7054 ixgbe_get_regs(struct rte_eth_dev *dev,
7055               struct rte_dev_reg_info *regs)
7056 {
7057         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7058         uint32_t *data = regs->data;
7059         int g_ind = 0;
7060         int count = 0;
7061         const struct reg_info *reg_group;
7062         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7063                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7064
7065         if (data == NULL) {
7066                 regs->length = ixgbe_get_reg_length(dev);
7067                 regs->width = sizeof(uint32_t);
7068                 return 0;
7069         }
7070
7071         /* Support only full register dump */
7072         if ((regs->length == 0) ||
7073             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7074                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7075                         hw->device_id;
7076                 while ((reg_group = reg_set[g_ind++]))
7077                         count += ixgbe_read_regs_group(dev, &data[count],
7078                                 reg_group);
7079                 return 0;
7080         }
7081
7082         return -ENOTSUP;
7083 }
7084
7085 static int
7086 ixgbevf_get_regs(struct rte_eth_dev *dev,
7087                 struct rte_dev_reg_info *regs)
7088 {
7089         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7090         uint32_t *data = regs->data;
7091         int g_ind = 0;
7092         int count = 0;
7093         const struct reg_info *reg_group;
7094
7095         if (data == NULL) {
7096                 regs->length = ixgbevf_get_reg_length(dev);
7097                 regs->width = sizeof(uint32_t);
7098                 return 0;
7099         }
7100
7101         /* Support only full register dump */
7102         if ((regs->length == 0) ||
7103             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7104                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7105                         hw->device_id;
7106                 while ((reg_group = ixgbevf_regs[g_ind++]))
7107                         count += ixgbe_read_regs_group(dev, &data[count],
7108                                                       reg_group);
7109                 return 0;
7110         }
7111
7112         return -ENOTSUP;
7113 }
7114
7115 static int
7116 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7117 {
7118         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7119
7120         /* Return unit is byte count */
7121         return hw->eeprom.word_size * 2;
7122 }
7123
7124 static int
7125 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7126                 struct rte_dev_eeprom_info *in_eeprom)
7127 {
7128         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7129         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7130         uint16_t *data = in_eeprom->data;
7131         int first, length;
7132
7133         first = in_eeprom->offset >> 1;
7134         length = in_eeprom->length >> 1;
7135         if ((first > hw->eeprom.word_size) ||
7136             ((first + length) > hw->eeprom.word_size))
7137                 return -EINVAL;
7138
7139         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7140
7141         return eeprom->ops.read_buffer(hw, first, length, data);
7142 }
7143
7144 static int
7145 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7146                 struct rte_dev_eeprom_info *in_eeprom)
7147 {
7148         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7149         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7150         uint16_t *data = in_eeprom->data;
7151         int first, length;
7152
7153         first = in_eeprom->offset >> 1;
7154         length = in_eeprom->length >> 1;
7155         if ((first > hw->eeprom.word_size) ||
7156             ((first + length) > hw->eeprom.word_size))
7157                 return -EINVAL;
7158
7159         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7160
7161         return eeprom->ops.write_buffer(hw,  first, length, data);
7162 }
7163
7164 uint16_t
7165 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7166         switch (mac_type) {
7167         case ixgbe_mac_X550:
7168         case ixgbe_mac_X550EM_x:
7169         case ixgbe_mac_X550EM_a:
7170                 return ETH_RSS_RETA_SIZE_512;
7171         case ixgbe_mac_X550_vf:
7172         case ixgbe_mac_X550EM_x_vf:
7173         case ixgbe_mac_X550EM_a_vf:
7174                 return ETH_RSS_RETA_SIZE_64;
7175         default:
7176                 return ETH_RSS_RETA_SIZE_128;
7177         }
7178 }
7179
7180 uint32_t
7181 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7182         switch (mac_type) {
7183         case ixgbe_mac_X550:
7184         case ixgbe_mac_X550EM_x:
7185         case ixgbe_mac_X550EM_a:
7186                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7187                         return IXGBE_RETA(reta_idx >> 2);
7188                 else
7189                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7190         case ixgbe_mac_X550_vf:
7191         case ixgbe_mac_X550EM_x_vf:
7192         case ixgbe_mac_X550EM_a_vf:
7193                 return IXGBE_VFRETA(reta_idx >> 2);
7194         default:
7195                 return IXGBE_RETA(reta_idx >> 2);
7196         }
7197 }
7198
7199 uint32_t
7200 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7201         switch (mac_type) {
7202         case ixgbe_mac_X550_vf:
7203         case ixgbe_mac_X550EM_x_vf:
7204         case ixgbe_mac_X550EM_a_vf:
7205                 return IXGBE_VFMRQC;
7206         default:
7207                 return IXGBE_MRQC;
7208         }
7209 }
7210
7211 uint32_t
7212 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7213         switch (mac_type) {
7214         case ixgbe_mac_X550_vf:
7215         case ixgbe_mac_X550EM_x_vf:
7216         case ixgbe_mac_X550EM_a_vf:
7217                 return IXGBE_VFRSSRK(i);
7218         default:
7219                 return IXGBE_RSSRK(i);
7220         }
7221 }
7222
7223 bool
7224 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7225         switch (mac_type) {
7226         case ixgbe_mac_82599_vf:
7227         case ixgbe_mac_X540_vf:
7228                 return 0;
7229         default:
7230                 return 1;
7231         }
7232 }
7233
7234 static int
7235 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7236                         struct rte_eth_dcb_info *dcb_info)
7237 {
7238         struct ixgbe_dcb_config *dcb_config =
7239                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7240         struct ixgbe_dcb_tc_config *tc;
7241         uint8_t i, j;
7242
7243         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7244                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7245         else
7246                 dcb_info->nb_tcs = 1;
7247
7248         if (dcb_config->vt_mode) { /* vt is enabled*/
7249                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7250                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7251                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7252                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7253                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7254                         for (j = 0; j < dcb_info->nb_tcs; j++) {
7255                                 dcb_info->tc_queue.tc_rxq[i][j].base =
7256                                                 i * dcb_info->nb_tcs + j;
7257                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7258                                 dcb_info->tc_queue.tc_txq[i][j].base =
7259                                                 i * dcb_info->nb_tcs + j;
7260                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7261                         }
7262                 }
7263         } else { /* vt is disabled*/
7264                 struct rte_eth_dcb_rx_conf *rx_conf =
7265                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7266                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7267                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7268                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7269                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7270                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7271                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7272                         }
7273                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7274                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7275                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7276                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7277                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7278                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7279                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7280                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7281                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7282                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7283                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7284                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7285                         }
7286                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7287                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7288                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7289                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7290                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7291                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7292                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7293                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7294                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7295                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7296                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7297                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7298                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7299                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7300                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7301                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7302                 }
7303         }
7304         for (i = 0; i < dcb_info->nb_tcs; i++) {
7305                 tc = &dcb_config->tc_config[i];
7306                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7307         }
7308         return 0;
7309 }
7310
7311 /* Update e-tag ether type */
7312 static int
7313 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7314                             uint16_t ether_type)
7315 {
7316         uint32_t etag_etype;
7317
7318         if (hw->mac.type != ixgbe_mac_X550 &&
7319             hw->mac.type != ixgbe_mac_X550EM_x &&
7320             hw->mac.type != ixgbe_mac_X550EM_a) {
7321                 return -ENOTSUP;
7322         }
7323
7324         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7325         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7326         etag_etype |= ether_type;
7327         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7328         IXGBE_WRITE_FLUSH(hw);
7329
7330         return 0;
7331 }
7332
7333 /* Config l2 tunnel ether type */
7334 static int
7335 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7336                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7337 {
7338         int ret = 0;
7339         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7340         struct ixgbe_l2_tn_info *l2_tn_info =
7341                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7342
7343         if (l2_tunnel == NULL)
7344                 return -EINVAL;
7345
7346         switch (l2_tunnel->l2_tunnel_type) {
7347         case RTE_L2_TUNNEL_TYPE_E_TAG:
7348                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7349                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7350                 break;
7351         default:
7352                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7353                 ret = -EINVAL;
7354                 break;
7355         }
7356
7357         return ret;
7358 }
7359
7360 /* Enable e-tag tunnel */
7361 static int
7362 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7363 {
7364         uint32_t etag_etype;
7365
7366         if (hw->mac.type != ixgbe_mac_X550 &&
7367             hw->mac.type != ixgbe_mac_X550EM_x &&
7368             hw->mac.type != ixgbe_mac_X550EM_a) {
7369                 return -ENOTSUP;
7370         }
7371
7372         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7373         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7374         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7375         IXGBE_WRITE_FLUSH(hw);
7376
7377         return 0;
7378 }
7379
7380 /* Enable l2 tunnel */
7381 static int
7382 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7383                            enum rte_eth_tunnel_type l2_tunnel_type)
7384 {
7385         int ret = 0;
7386         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7387         struct ixgbe_l2_tn_info *l2_tn_info =
7388                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7389
7390         switch (l2_tunnel_type) {
7391         case RTE_L2_TUNNEL_TYPE_E_TAG:
7392                 l2_tn_info->e_tag_en = TRUE;
7393                 ret = ixgbe_e_tag_enable(hw);
7394                 break;
7395         default:
7396                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7397                 ret = -EINVAL;
7398                 break;
7399         }
7400
7401         return ret;
7402 }
7403
7404 /* Disable e-tag tunnel */
7405 static int
7406 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7407 {
7408         uint32_t etag_etype;
7409
7410         if (hw->mac.type != ixgbe_mac_X550 &&
7411             hw->mac.type != ixgbe_mac_X550EM_x &&
7412             hw->mac.type != ixgbe_mac_X550EM_a) {
7413                 return -ENOTSUP;
7414         }
7415
7416         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7417         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7418         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7419         IXGBE_WRITE_FLUSH(hw);
7420
7421         return 0;
7422 }
7423
7424 /* Disable l2 tunnel */
7425 static int
7426 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7427                             enum rte_eth_tunnel_type l2_tunnel_type)
7428 {
7429         int ret = 0;
7430         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7431         struct ixgbe_l2_tn_info *l2_tn_info =
7432                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7433
7434         switch (l2_tunnel_type) {
7435         case RTE_L2_TUNNEL_TYPE_E_TAG:
7436                 l2_tn_info->e_tag_en = FALSE;
7437                 ret = ixgbe_e_tag_disable(hw);
7438                 break;
7439         default:
7440                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7441                 ret = -EINVAL;
7442                 break;
7443         }
7444
7445         return ret;
7446 }
7447
7448 static int
7449 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7450                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7451 {
7452         int ret = 0;
7453         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7454         uint32_t i, rar_entries;
7455         uint32_t rar_low, rar_high;
7456
7457         if (hw->mac.type != ixgbe_mac_X550 &&
7458             hw->mac.type != ixgbe_mac_X550EM_x &&
7459             hw->mac.type != ixgbe_mac_X550EM_a) {
7460                 return -ENOTSUP;
7461         }
7462
7463         rar_entries = ixgbe_get_num_rx_addrs(hw);
7464
7465         for (i = 1; i < rar_entries; i++) {
7466                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7467                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7468                 if ((rar_high & IXGBE_RAH_AV) &&
7469                     (rar_high & IXGBE_RAH_ADTYPE) &&
7470                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7471                      l2_tunnel->tunnel_id)) {
7472                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7473                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7474
7475                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7476
7477                         return ret;
7478                 }
7479         }
7480
7481         return ret;
7482 }
7483
7484 static int
7485 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7486                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7487 {
7488         int ret = 0;
7489         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7490         uint32_t i, rar_entries;
7491         uint32_t rar_low, rar_high;
7492
7493         if (hw->mac.type != ixgbe_mac_X550 &&
7494             hw->mac.type != ixgbe_mac_X550EM_x &&
7495             hw->mac.type != ixgbe_mac_X550EM_a) {
7496                 return -ENOTSUP;
7497         }
7498
7499         /* One entry for one tunnel. Try to remove potential existing entry. */
7500         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7501
7502         rar_entries = ixgbe_get_num_rx_addrs(hw);
7503
7504         for (i = 1; i < rar_entries; i++) {
7505                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7506                 if (rar_high & IXGBE_RAH_AV) {
7507                         continue;
7508                 } else {
7509                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7510                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7511                         rar_low = l2_tunnel->tunnel_id;
7512
7513                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7514                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7515
7516                         return ret;
7517                 }
7518         }
7519
7520         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7521                      " Please remove a rule before adding a new one.");
7522         return -EINVAL;
7523 }
7524
7525 static inline struct ixgbe_l2_tn_filter *
7526 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7527                           struct ixgbe_l2_tn_key *key)
7528 {
7529         int ret;
7530
7531         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7532         if (ret < 0)
7533                 return NULL;
7534
7535         return l2_tn_info->hash_map[ret];
7536 }
7537
7538 static inline int
7539 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7540                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7541 {
7542         int ret;
7543
7544         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7545                                &l2_tn_filter->key);
7546
7547         if (ret < 0) {
7548                 PMD_DRV_LOG(ERR,
7549                             "Failed to insert L2 tunnel filter"
7550                             " to hash table %d!",
7551                             ret);
7552                 return ret;
7553         }
7554
7555         l2_tn_info->hash_map[ret] = l2_tn_filter;
7556
7557         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7558
7559         return 0;
7560 }
7561
7562 static inline int
7563 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7564                           struct ixgbe_l2_tn_key *key)
7565 {
7566         int ret;
7567         struct ixgbe_l2_tn_filter *l2_tn_filter;
7568
7569         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7570
7571         if (ret < 0) {
7572                 PMD_DRV_LOG(ERR,
7573                             "No such L2 tunnel filter to delete %d!",
7574                             ret);
7575                 return ret;
7576         }
7577
7578         l2_tn_filter = l2_tn_info->hash_map[ret];
7579         l2_tn_info->hash_map[ret] = NULL;
7580
7581         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7582         rte_free(l2_tn_filter);
7583
7584         return 0;
7585 }
7586
7587 /* Add l2 tunnel filter */
7588 int
7589 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7590                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7591                                bool restore)
7592 {
7593         int ret;
7594         struct ixgbe_l2_tn_info *l2_tn_info =
7595                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7596         struct ixgbe_l2_tn_key key;
7597         struct ixgbe_l2_tn_filter *node;
7598
7599         if (!restore) {
7600                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7601                 key.tn_id = l2_tunnel->tunnel_id;
7602
7603                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7604
7605                 if (node) {
7606                         PMD_DRV_LOG(ERR,
7607                                     "The L2 tunnel filter already exists!");
7608                         return -EINVAL;
7609                 }
7610
7611                 node = rte_zmalloc("ixgbe_l2_tn",
7612                                    sizeof(struct ixgbe_l2_tn_filter),
7613                                    0);
7614                 if (!node)
7615                         return -ENOMEM;
7616
7617                 (void)rte_memcpy(&node->key,
7618                                  &key,
7619                                  sizeof(struct ixgbe_l2_tn_key));
7620                 node->pool = l2_tunnel->pool;
7621                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7622                 if (ret < 0) {
7623                         rte_free(node);
7624                         return ret;
7625                 }
7626         }
7627
7628         switch (l2_tunnel->l2_tunnel_type) {
7629         case RTE_L2_TUNNEL_TYPE_E_TAG:
7630                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7631                 break;
7632         default:
7633                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7634                 ret = -EINVAL;
7635                 break;
7636         }
7637
7638         if ((!restore) && (ret < 0))
7639                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7640
7641         return ret;
7642 }
7643
7644 /* Delete l2 tunnel filter */
7645 int
7646 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7647                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7648 {
7649         int ret;
7650         struct ixgbe_l2_tn_info *l2_tn_info =
7651                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7652         struct ixgbe_l2_tn_key key;
7653
7654         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7655         key.tn_id = l2_tunnel->tunnel_id;
7656         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7657         if (ret < 0)
7658                 return ret;
7659
7660         switch (l2_tunnel->l2_tunnel_type) {
7661         case RTE_L2_TUNNEL_TYPE_E_TAG:
7662                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7663                 break;
7664         default:
7665                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7666                 ret = -EINVAL;
7667                 break;
7668         }
7669
7670         return ret;
7671 }
7672
7673 /**
7674  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7675  * @dev: pointer to rte_eth_dev structure
7676  * @filter_op:operation will be taken.
7677  * @arg: a pointer to specific structure corresponding to the filter_op
7678  */
7679 static int
7680 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7681                                   enum rte_filter_op filter_op,
7682                                   void *arg)
7683 {
7684         int ret;
7685
7686         if (filter_op == RTE_ETH_FILTER_NOP)
7687                 return 0;
7688
7689         if (arg == NULL) {
7690                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7691                             filter_op);
7692                 return -EINVAL;
7693         }
7694
7695         switch (filter_op) {
7696         case RTE_ETH_FILTER_ADD:
7697                 ret = ixgbe_dev_l2_tunnel_filter_add
7698                         (dev,
7699                          (struct rte_eth_l2_tunnel_conf *)arg,
7700                          FALSE);
7701                 break;
7702         case RTE_ETH_FILTER_DELETE:
7703                 ret = ixgbe_dev_l2_tunnel_filter_del
7704                         (dev,
7705                          (struct rte_eth_l2_tunnel_conf *)arg);
7706                 break;
7707         default:
7708                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7709                 ret = -EINVAL;
7710                 break;
7711         }
7712         return ret;
7713 }
7714
7715 static int
7716 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7717 {
7718         int ret = 0;
7719         uint32_t ctrl;
7720         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7721
7722         if (hw->mac.type != ixgbe_mac_X550 &&
7723             hw->mac.type != ixgbe_mac_X550EM_x &&
7724             hw->mac.type != ixgbe_mac_X550EM_a) {
7725                 return -ENOTSUP;
7726         }
7727
7728         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7729         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7730         if (en)
7731                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7732         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7733
7734         return ret;
7735 }
7736
7737 /* Enable l2 tunnel forwarding */
7738 static int
7739 ixgbe_dev_l2_tunnel_forwarding_enable
7740         (struct rte_eth_dev *dev,
7741          enum rte_eth_tunnel_type l2_tunnel_type)
7742 {
7743         struct ixgbe_l2_tn_info *l2_tn_info =
7744                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7745         int ret = 0;
7746
7747         switch (l2_tunnel_type) {
7748         case RTE_L2_TUNNEL_TYPE_E_TAG:
7749                 l2_tn_info->e_tag_fwd_en = TRUE;
7750                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7751                 break;
7752         default:
7753                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7754                 ret = -EINVAL;
7755                 break;
7756         }
7757
7758         return ret;
7759 }
7760
7761 /* Disable l2 tunnel forwarding */
7762 static int
7763 ixgbe_dev_l2_tunnel_forwarding_disable
7764         (struct rte_eth_dev *dev,
7765          enum rte_eth_tunnel_type l2_tunnel_type)
7766 {
7767         struct ixgbe_l2_tn_info *l2_tn_info =
7768                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7769         int ret = 0;
7770
7771         switch (l2_tunnel_type) {
7772         case RTE_L2_TUNNEL_TYPE_E_TAG:
7773                 l2_tn_info->e_tag_fwd_en = FALSE;
7774                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7775                 break;
7776         default:
7777                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7778                 ret = -EINVAL;
7779                 break;
7780         }
7781
7782         return ret;
7783 }
7784
7785 static int
7786 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7787                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7788                              bool en)
7789 {
7790         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7791         int ret = 0;
7792         uint32_t vmtir, vmvir;
7793         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7794
7795         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7796                 PMD_DRV_LOG(ERR,
7797                             "VF id %u should be less than %u",
7798                             l2_tunnel->vf_id,
7799                             pci_dev->max_vfs);
7800                 return -EINVAL;
7801         }
7802
7803         if (hw->mac.type != ixgbe_mac_X550 &&
7804             hw->mac.type != ixgbe_mac_X550EM_x &&
7805             hw->mac.type != ixgbe_mac_X550EM_a) {
7806                 return -ENOTSUP;
7807         }
7808
7809         if (en)
7810                 vmtir = l2_tunnel->tunnel_id;
7811         else
7812                 vmtir = 0;
7813
7814         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7815
7816         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7817         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7818         if (en)
7819                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7820         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7821
7822         return ret;
7823 }
7824
7825 /* Enable l2 tunnel tag insertion */
7826 static int
7827 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7828                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7829 {
7830         int ret = 0;
7831
7832         switch (l2_tunnel->l2_tunnel_type) {
7833         case RTE_L2_TUNNEL_TYPE_E_TAG:
7834                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7835                 break;
7836         default:
7837                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7838                 ret = -EINVAL;
7839                 break;
7840         }
7841
7842         return ret;
7843 }
7844
7845 /* Disable l2 tunnel tag insertion */
7846 static int
7847 ixgbe_dev_l2_tunnel_insertion_disable
7848         (struct rte_eth_dev *dev,
7849          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7850 {
7851         int ret = 0;
7852
7853         switch (l2_tunnel->l2_tunnel_type) {
7854         case RTE_L2_TUNNEL_TYPE_E_TAG:
7855                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7856                 break;
7857         default:
7858                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7859                 ret = -EINVAL;
7860                 break;
7861         }
7862
7863         return ret;
7864 }
7865
7866 static int
7867 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7868                              bool en)
7869 {
7870         int ret = 0;
7871         uint32_t qde;
7872         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7873
7874         if (hw->mac.type != ixgbe_mac_X550 &&
7875             hw->mac.type != ixgbe_mac_X550EM_x &&
7876             hw->mac.type != ixgbe_mac_X550EM_a) {
7877                 return -ENOTSUP;
7878         }
7879
7880         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7881         if (en)
7882                 qde |= IXGBE_QDE_STRIP_TAG;
7883         else
7884                 qde &= ~IXGBE_QDE_STRIP_TAG;
7885         qde &= ~IXGBE_QDE_READ;
7886         qde |= IXGBE_QDE_WRITE;
7887         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7888
7889         return ret;
7890 }
7891
7892 /* Enable l2 tunnel tag stripping */
7893 static int
7894 ixgbe_dev_l2_tunnel_stripping_enable
7895         (struct rte_eth_dev *dev,
7896          enum rte_eth_tunnel_type l2_tunnel_type)
7897 {
7898         int ret = 0;
7899
7900         switch (l2_tunnel_type) {
7901         case RTE_L2_TUNNEL_TYPE_E_TAG:
7902                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7903                 break;
7904         default:
7905                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7906                 ret = -EINVAL;
7907                 break;
7908         }
7909
7910         return ret;
7911 }
7912
7913 /* Disable l2 tunnel tag stripping */
7914 static int
7915 ixgbe_dev_l2_tunnel_stripping_disable
7916         (struct rte_eth_dev *dev,
7917          enum rte_eth_tunnel_type l2_tunnel_type)
7918 {
7919         int ret = 0;
7920
7921         switch (l2_tunnel_type) {
7922         case RTE_L2_TUNNEL_TYPE_E_TAG:
7923                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7924                 break;
7925         default:
7926                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7927                 ret = -EINVAL;
7928                 break;
7929         }
7930
7931         return ret;
7932 }
7933
7934 /* Enable/disable l2 tunnel offload functions */
7935 static int
7936 ixgbe_dev_l2_tunnel_offload_set
7937         (struct rte_eth_dev *dev,
7938          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7939          uint32_t mask,
7940          uint8_t en)
7941 {
7942         int ret = 0;
7943
7944         if (l2_tunnel == NULL)
7945                 return -EINVAL;
7946
7947         ret = -EINVAL;
7948         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7949                 if (en)
7950                         ret = ixgbe_dev_l2_tunnel_enable(
7951                                 dev,
7952                                 l2_tunnel->l2_tunnel_type);
7953                 else
7954                         ret = ixgbe_dev_l2_tunnel_disable(
7955                                 dev,
7956                                 l2_tunnel->l2_tunnel_type);
7957         }
7958
7959         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7960                 if (en)
7961                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7962                                 dev,
7963                                 l2_tunnel);
7964                 else
7965                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7966                                 dev,
7967                                 l2_tunnel);
7968         }
7969
7970         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7971                 if (en)
7972                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7973                                 dev,
7974                                 l2_tunnel->l2_tunnel_type);
7975                 else
7976                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7977                                 dev,
7978                                 l2_tunnel->l2_tunnel_type);
7979         }
7980
7981         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7982                 if (en)
7983                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7984                                 dev,
7985                                 l2_tunnel->l2_tunnel_type);
7986                 else
7987                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7988                                 dev,
7989                                 l2_tunnel->l2_tunnel_type);
7990         }
7991
7992         return ret;
7993 }
7994
7995 static int
7996 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7997                         uint16_t port)
7998 {
7999         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8000         IXGBE_WRITE_FLUSH(hw);
8001
8002         return 0;
8003 }
8004
8005 /* There's only one register for VxLAN UDP port.
8006  * So, we cannot add several ports. Will update it.
8007  */
8008 static int
8009 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8010                      uint16_t port)
8011 {
8012         if (port == 0) {
8013                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8014                 return -EINVAL;
8015         }
8016
8017         return ixgbe_update_vxlan_port(hw, port);
8018 }
8019
8020 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8021  * UDP port, it must have a value.
8022  * So, will reset it to the original value 0.
8023  */
8024 static int
8025 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8026                      uint16_t port)
8027 {
8028         uint16_t cur_port;
8029
8030         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8031
8032         if (cur_port != port) {
8033                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8034                 return -EINVAL;
8035         }
8036
8037         return ixgbe_update_vxlan_port(hw, 0);
8038 }
8039
8040 /* Add UDP tunneling port */
8041 static int
8042 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8043                               struct rte_eth_udp_tunnel *udp_tunnel)
8044 {
8045         int ret = 0;
8046         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8047
8048         if (hw->mac.type != ixgbe_mac_X550 &&
8049             hw->mac.type != ixgbe_mac_X550EM_x &&
8050             hw->mac.type != ixgbe_mac_X550EM_a) {
8051                 return -ENOTSUP;
8052         }
8053
8054         if (udp_tunnel == NULL)
8055                 return -EINVAL;
8056
8057         switch (udp_tunnel->prot_type) {
8058         case RTE_TUNNEL_TYPE_VXLAN:
8059                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8060                 break;
8061
8062         case RTE_TUNNEL_TYPE_GENEVE:
8063         case RTE_TUNNEL_TYPE_TEREDO:
8064                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8065                 ret = -EINVAL;
8066                 break;
8067
8068         default:
8069                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8070                 ret = -EINVAL;
8071                 break;
8072         }
8073
8074         return ret;
8075 }
8076
8077 /* Remove UDP tunneling port */
8078 static int
8079 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8080                               struct rte_eth_udp_tunnel *udp_tunnel)
8081 {
8082         int ret = 0;
8083         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8084
8085         if (hw->mac.type != ixgbe_mac_X550 &&
8086             hw->mac.type != ixgbe_mac_X550EM_x &&
8087             hw->mac.type != ixgbe_mac_X550EM_a) {
8088                 return -ENOTSUP;
8089         }
8090
8091         if (udp_tunnel == NULL)
8092                 return -EINVAL;
8093
8094         switch (udp_tunnel->prot_type) {
8095         case RTE_TUNNEL_TYPE_VXLAN:
8096                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8097                 break;
8098         case RTE_TUNNEL_TYPE_GENEVE:
8099         case RTE_TUNNEL_TYPE_TEREDO:
8100                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8101                 ret = -EINVAL;
8102                 break;
8103         default:
8104                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8105                 ret = -EINVAL;
8106                 break;
8107         }
8108
8109         return ret;
8110 }
8111
8112 static void
8113 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8114 {
8115         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8116
8117         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8118 }
8119
8120 static void
8121 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8122 {
8123         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8124
8125         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
8126 }
8127
8128 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8129 {
8130         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8131         u32 in_msg = 0;
8132
8133         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8134                 return;
8135
8136         /* PF reset VF event */
8137         if (in_msg == IXGBE_PF_CONTROL_MSG)
8138                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
8139 }
8140
8141 static int
8142 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8143 {
8144         uint32_t eicr;
8145         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8146         struct ixgbe_interrupt *intr =
8147                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8148         ixgbevf_intr_disable(hw);
8149
8150         /* read-on-clear nic registers here */
8151         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8152         intr->flags = 0;
8153
8154         /* only one misc vector supported - mailbox */
8155         eicr &= IXGBE_VTEICR_MASK;
8156         if (eicr == IXGBE_MISC_VEC_ID)
8157                 intr->flags |= IXGBE_FLAG_MAILBOX;
8158
8159         return 0;
8160 }
8161
8162 static int
8163 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8164 {
8165         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8166         struct ixgbe_interrupt *intr =
8167                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8168
8169         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8170                 ixgbevf_mbx_process(dev);
8171                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8172         }
8173
8174         ixgbevf_intr_enable(hw);
8175
8176         return 0;
8177 }
8178
8179 static void
8180 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
8181                               void *param)
8182 {
8183         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8184
8185         ixgbevf_dev_interrupt_get_status(dev);
8186         ixgbevf_dev_interrupt_action(dev);
8187 }
8188
8189 /**
8190  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8191  *  @hw: pointer to hardware structure
8192  *
8193  *  Stops the transmit data path and waits for the HW to internally empty
8194  *  the Tx security block
8195  **/
8196 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8197 {
8198 #define IXGBE_MAX_SECTX_POLL 40
8199
8200         int i;
8201         int sectxreg;
8202
8203         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8204         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8205         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8206         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8207                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8208                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8209                         break;
8210                 /* Use interrupt-safe sleep just in case */
8211                 usec_delay(1000);
8212         }
8213
8214         /* For informational purposes only */
8215         if (i >= IXGBE_MAX_SECTX_POLL)
8216                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8217                          "path fully disabled.  Continuing with init.");
8218
8219         return IXGBE_SUCCESS;
8220 }
8221
8222 /**
8223  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8224  *  @hw: pointer to hardware structure
8225  *
8226  *  Enables the transmit data path.
8227  **/
8228 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8229 {
8230         uint32_t sectxreg;
8231
8232         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8233         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8234         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8235         IXGBE_WRITE_FLUSH(hw);
8236
8237         return IXGBE_SUCCESS;
8238 }
8239
8240 int
8241 rte_pmd_ixgbe_macsec_enable(uint8_t port, uint8_t en, uint8_t rp)
8242 {
8243         struct ixgbe_hw *hw;
8244         struct rte_eth_dev *dev;
8245         uint32_t ctrl;
8246
8247         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8248
8249         dev = &rte_eth_devices[port];
8250
8251         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8252                 return -ENOTSUP;
8253
8254         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8255
8256         /* Stop the data paths */
8257         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8258                 return -ENOTSUP;
8259         /*
8260          * Workaround:
8261          * As no ixgbe_disable_sec_rx_path equivalent is
8262          * implemented for tx in the base code, and we are
8263          * not allowed to modify the base code in DPDK, so
8264          * just call the hand-written one directly for now.
8265          * The hardware support has been checked by
8266          * ixgbe_disable_sec_rx_path().
8267          */
8268         ixgbe_disable_sec_tx_path_generic(hw);
8269
8270         /* Enable Ethernet CRC (required by MACsec offload) */
8271         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8272         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8273         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8274
8275         /* Enable the TX and RX crypto engines */
8276         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8277         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8278         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8279
8280         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8281         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8282         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8283
8284         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8285         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8286         ctrl |= 0x3;
8287         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8288
8289         /* Enable SA lookup */
8290         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8291         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8292         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8293                      IXGBE_LSECTXCTRL_AUTH;
8294         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8295         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8296         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8297         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8298
8299         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8300         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8301         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8302         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8303         if (rp)
8304                 ctrl |= IXGBE_LSECRXCTRL_RP;
8305         else
8306                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8307         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8308
8309         /* Start the data paths */
8310         ixgbe_enable_sec_rx_path(hw);
8311         /*
8312          * Workaround:
8313          * As no ixgbe_enable_sec_rx_path equivalent is
8314          * implemented for tx in the base code, and we are
8315          * not allowed to modify the base code in DPDK, so
8316          * just call the hand-written one directly for now.
8317          */
8318         ixgbe_enable_sec_tx_path_generic(hw);
8319
8320         return 0;
8321 }
8322
8323 int
8324 rte_pmd_ixgbe_macsec_disable(uint8_t port)
8325 {
8326         struct ixgbe_hw *hw;
8327         struct rte_eth_dev *dev;
8328         uint32_t ctrl;
8329
8330         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8331
8332         dev = &rte_eth_devices[port];
8333
8334         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8335                 return -ENOTSUP;
8336
8337         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8338
8339         /* Stop the data paths */
8340         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8341                 return -ENOTSUP;
8342         /*
8343          * Workaround:
8344          * As no ixgbe_disable_sec_rx_path equivalent is
8345          * implemented for tx in the base code, and we are
8346          * not allowed to modify the base code in DPDK, so
8347          * just call the hand-written one directly for now.
8348          * The hardware support has been checked by
8349          * ixgbe_disable_sec_rx_path().
8350          */
8351         ixgbe_disable_sec_tx_path_generic(hw);
8352
8353         /* Disable the TX and RX crypto engines */
8354         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8355         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8356         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8357
8358         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8359         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8360         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8361
8362         /* Disable SA lookup */
8363         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8364         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8365         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8366         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8367
8368         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8369         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8370         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8371         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8372
8373         /* Start the data paths */
8374         ixgbe_enable_sec_rx_path(hw);
8375         /*
8376          * Workaround:
8377          * As no ixgbe_enable_sec_rx_path equivalent is
8378          * implemented for tx in the base code, and we are
8379          * not allowed to modify the base code in DPDK, so
8380          * just call the hand-written one directly for now.
8381          */
8382         ixgbe_enable_sec_tx_path_generic(hw);
8383
8384         return 0;
8385 }
8386
8387 int
8388 rte_pmd_ixgbe_macsec_config_txsc(uint8_t port, uint8_t *mac)
8389 {
8390         struct ixgbe_hw *hw;
8391         struct rte_eth_dev *dev;
8392         uint32_t ctrl;
8393
8394         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8395
8396         dev = &rte_eth_devices[port];
8397
8398         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8399                 return -ENOTSUP;
8400
8401         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8402
8403         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8404         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl);
8405
8406         ctrl = mac[4] | (mac[5] << 8);
8407         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl);
8408
8409         return 0;
8410 }
8411
8412 int
8413 rte_pmd_ixgbe_macsec_config_rxsc(uint8_t port, uint8_t *mac, uint16_t pi)
8414 {
8415         struct ixgbe_hw *hw;
8416         struct rte_eth_dev *dev;
8417         uint32_t ctrl;
8418
8419         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8420
8421         dev = &rte_eth_devices[port];
8422
8423         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8424                 return -ENOTSUP;
8425
8426         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8427
8428         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8429         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl);
8430
8431         pi = rte_cpu_to_be_16(pi);
8432         ctrl = mac[4] | (mac[5] << 8) | (pi << 16);
8433         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl);
8434
8435         return 0;
8436 }
8437
8438 int
8439 rte_pmd_ixgbe_macsec_select_txsa(uint8_t port, uint8_t idx, uint8_t an,
8440                                  uint32_t pn, uint8_t *key)
8441 {
8442         struct ixgbe_hw *hw;
8443         struct rte_eth_dev *dev;
8444         uint32_t ctrl, i;
8445
8446         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8447
8448         dev = &rte_eth_devices[port];
8449
8450         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8451                 return -ENOTSUP;
8452
8453         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8454
8455         if (idx != 0 && idx != 1)
8456                 return -EINVAL;
8457
8458         if (an >= 4)
8459                 return -EINVAL;
8460
8461         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8462
8463         /* Set the PN and key */
8464         pn = rte_cpu_to_be_32(pn);
8465         if (idx == 0) {
8466                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn);
8467
8468                 for (i = 0; i < 4; i++) {
8469                         ctrl = (key[i * 4 + 0] <<  0) |
8470                                (key[i * 4 + 1] <<  8) |
8471                                (key[i * 4 + 2] << 16) |
8472                                (key[i * 4 + 3] << 24);
8473                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl);
8474                 }
8475         } else {
8476                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn);
8477
8478                 for (i = 0; i < 4; i++) {
8479                         ctrl = (key[i * 4 + 0] <<  0) |
8480                                (key[i * 4 + 1] <<  8) |
8481                                (key[i * 4 + 2] << 16) |
8482                                (key[i * 4 + 3] << 24);
8483                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl);
8484                 }
8485         }
8486
8487         /* Set AN and select the SA */
8488         ctrl = (an << idx * 2) | (idx << 4);
8489         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl);
8490
8491         return 0;
8492 }
8493
8494 int
8495 rte_pmd_ixgbe_macsec_select_rxsa(uint8_t port, uint8_t idx, uint8_t an,
8496                                  uint32_t pn, uint8_t *key)
8497 {
8498         struct ixgbe_hw *hw;
8499         struct rte_eth_dev *dev;
8500         uint32_t ctrl, i;
8501
8502         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8503
8504         dev = &rte_eth_devices[port];
8505
8506         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8507                 return -ENOTSUP;
8508
8509         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8510
8511         if (idx != 0 && idx != 1)
8512                 return -EINVAL;
8513
8514         if (an >= 4)
8515                 return -EINVAL;
8516
8517         /* Set the PN */
8518         pn = rte_cpu_to_be_32(pn);
8519         IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn);
8520
8521         /* Set the key */
8522         for (i = 0; i < 4; i++) {
8523                 ctrl = (key[i * 4 + 0] <<  0) |
8524                        (key[i * 4 + 1] <<  8) |
8525                        (key[i * 4 + 2] << 16) |
8526                        (key[i * 4 + 3] << 24);
8527                 IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl);
8528         }
8529
8530         /* Set the AN and validate the SA */
8531         ctrl = an | (1 << 2);
8532         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl);
8533
8534         return 0;
8535 }
8536
8537 /* restore n-tuple filter */
8538 static inline void
8539 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8540 {
8541         struct ixgbe_filter_info *filter_info =
8542                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8543         struct ixgbe_5tuple_filter *node;
8544
8545         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8546                 ixgbe_inject_5tuple_filter(dev, node);
8547         }
8548 }
8549
8550 /* restore ethernet type filter */
8551 static inline void
8552 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8553 {
8554         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8555         struct ixgbe_filter_info *filter_info =
8556                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8557         int i;
8558
8559         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8560                 if (filter_info->ethertype_mask & (1 << i)) {
8561                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8562                                         filter_info->ethertype_filters[i].etqf);
8563                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8564                                         filter_info->ethertype_filters[i].etqs);
8565                         IXGBE_WRITE_FLUSH(hw);
8566                 }
8567         }
8568 }
8569
8570 /* restore SYN filter */
8571 static inline void
8572 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8573 {
8574         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8575         struct ixgbe_filter_info *filter_info =
8576                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8577         uint32_t synqf;
8578
8579         synqf = filter_info->syn_info;
8580
8581         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8582                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8583                 IXGBE_WRITE_FLUSH(hw);
8584         }
8585 }
8586
8587 /* restore L2 tunnel filter */
8588 static inline void
8589 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8590 {
8591         struct ixgbe_l2_tn_info *l2_tn_info =
8592                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8593         struct ixgbe_l2_tn_filter *node;
8594         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8595
8596         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8597                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8598                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8599                 l2_tn_conf.pool           = node->pool;
8600                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8601         }
8602 }
8603
8604 static int
8605 ixgbe_filter_restore(struct rte_eth_dev *dev)
8606 {
8607         ixgbe_ntuple_filter_restore(dev);
8608         ixgbe_ethertype_filter_restore(dev);
8609         ixgbe_syn_filter_restore(dev);
8610         ixgbe_fdir_filter_restore(dev);
8611         ixgbe_l2_tn_filter_restore(dev);
8612
8613         return 0;
8614 }
8615
8616 static void
8617 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8618 {
8619         struct ixgbe_l2_tn_info *l2_tn_info =
8620                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8621         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8622
8623         if (l2_tn_info->e_tag_en)
8624                 (void)ixgbe_e_tag_enable(hw);
8625
8626         if (l2_tn_info->e_tag_fwd_en)
8627                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8628
8629         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8630 }
8631
8632 /* remove all the n-tuple filters */
8633 void
8634 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8635 {
8636         struct ixgbe_filter_info *filter_info =
8637                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8638         struct ixgbe_5tuple_filter *p_5tuple;
8639
8640         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8641                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8642 }
8643
8644 /* remove all the ether type filters */
8645 void
8646 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8647 {
8648         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8649         struct ixgbe_filter_info *filter_info =
8650                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8651         int i;
8652
8653         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8654                 if (filter_info->ethertype_mask & (1 << i) &&
8655                     !filter_info->ethertype_filters[i].conf) {
8656                         (void)ixgbe_ethertype_filter_remove(filter_info,
8657                                                             (uint8_t)i);
8658                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8659                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8660                         IXGBE_WRITE_FLUSH(hw);
8661                 }
8662         }
8663 }
8664
8665 /* remove the SYN filter */
8666 void
8667 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8668 {
8669         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8670         struct ixgbe_filter_info *filter_info =
8671                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8672
8673         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8674                 filter_info->syn_info = 0;
8675
8676                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8677                 IXGBE_WRITE_FLUSH(hw);
8678         }
8679 }
8680
8681 /* remove all the L2 tunnel filters */
8682 int
8683 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8684 {
8685         struct ixgbe_l2_tn_info *l2_tn_info =
8686                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8687         struct ixgbe_l2_tn_filter *l2_tn_filter;
8688         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8689         int ret = 0;
8690
8691         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8692                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8693                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8694                 l2_tn_conf.pool           = l2_tn_filter->pool;
8695                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8696                 if (ret < 0)
8697                         return ret;
8698         }
8699
8700         return 0;
8701 }
8702
8703 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
8704 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8705 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8706 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
8707 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8708 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");