drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIBRTE_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
 233 static void ixgbe_dev_cancel_link_thread(struct rte_eth_dev *dev);
 234
 235 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 236                         struct rte_ether_addr *mac_addr,
 237                         uint32_t index, uint32_t pool);
 238 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 239 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 240                                            struct rte_ether_addr *mac_addr);
 241 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 242 static bool is_device_supported(struct rte_eth_dev *dev,
 243                                 struct rte_pci_driver *drv);
 244
 245 /* For Virtual Function support */
 246 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 247 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 248 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 249 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 250 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 251                                    int wait_to_complete);
 252 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 253 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 254 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 255 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 256 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 257 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 258                 struct rte_eth_stats *stats);
 259 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 260 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 261                 uint16_t vlan_id, int on);
 262 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 263                 uint16_t queue, int on);
 264 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 265 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 266 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 267 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 268                                             uint16_t queue_id);
 269 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 270                                              uint16_t queue_id);
 271 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 272                                  uint8_t queue, uint8_t msix_vector);
 273 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 274 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 277 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 278
 279 /* For Eth VMDQ APIs support */
 280 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 281                 rte_ether_addr * mac_addr, uint8_t on);
 282 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 283 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 284                 struct rte_eth_mirror_conf *mirror_conf,
 285                 uint8_t rule_id, uint8_t on);
 286 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 287                 uint8_t rule_id);
 288 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 289                                           uint16_t queue_id);
 290 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 291                                            uint16_t queue_id);
 292 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 293                                uint8_t queue, uint8_t msix_vector);
 294 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 295
 296 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 297                                 struct rte_ether_addr *mac_addr,
 298                                 uint32_t index, uint32_t pool);
 299 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 300 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 301                                              struct rte_ether_addr *mac_addr);
 302 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 303                         struct rte_eth_syn_filter *filter);
 304 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 305                         enum rte_filter_op filter_op,
 306                         void *arg);
 307 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 308                         struct ixgbe_5tuple_filter *filter);
 309 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 310                         struct ixgbe_5tuple_filter *filter);
 311 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 312                                 enum rte_filter_op filter_op,
 313                                 void *arg);
 314 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 315                         struct rte_eth_ntuple_filter *filter);
 316 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 317                                 enum rte_filter_op filter_op,
 318                                 void *arg);
 319 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 320                         struct rte_eth_ethertype_filter *filter);
 321 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 322                      enum rte_filter_type filter_type,
 323                      enum rte_filter_op filter_op,
 324                      void *arg);
 325 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 326
 327 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 328                                       struct rte_ether_addr *mc_addr_set,
 329                                       uint32_t nb_mc_addr);
 330 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 331                                    struct rte_eth_dcb_info *dcb_info);
 332
 333 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 334 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 335                             struct rte_dev_reg_info *regs);
 336 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 337 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 338                                 struct rte_dev_eeprom_info *eeprom);
 339 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 340                                 struct rte_dev_eeprom_info *eeprom);
 341
 342 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 343                                  struct rte_eth_dev_module_info *modinfo);
 344 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 345                                    struct rte_dev_eeprom_info *info);
 346
 347 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 348 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 349                                 struct rte_dev_reg_info *regs);
 350
 351 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 352 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 354                                             struct timespec *timestamp,
 355                                             uint32_t flags);
 356 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 357                                             struct timespec *timestamp);
 358 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 359 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 360                                    struct timespec *timestamp);
 361 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 362                                    const struct timespec *timestamp);
 363 static void ixgbevf_dev_interrupt_handler(void *param);
 364
 365 static int ixgbe_dev_l2_tunnel_eth_type_conf
 366         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 367 static int ixgbe_dev_l2_tunnel_offload_set
 368         (struct rte_eth_dev *dev,
 369          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 370          uint32_t mask,
 371          uint8_t en);
 372 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 373                                              enum rte_filter_op filter_op,
 374                                              void *arg);
 375
 376 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 377                                          struct rte_eth_udp_tunnel *udp_tunnel);
 378 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 379                                          struct rte_eth_udp_tunnel *udp_tunnel);
 380 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 381 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 382 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
 383
 384 /*
 385  * Define VF Stats MACRO for Non "cleared on read" register
 386  */
 387 #define UPDATE_VF_STAT(reg, last, cur)                          \
 388 {                                                               \
 389         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 390         cur += (latest - last) & UINT_MAX;                      \
 391         last = latest;                                          \
 392 }
 393
 394 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 395 {                                                                \
 396         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 397         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 398         u64 latest = ((new_msb << 32) | new_lsb);                \
 399         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 400         last = latest;                                           \
 401 }
 402
 403 #define IXGBE_SET_HWSTRIP(h, q) do {\
 404                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 405                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 406                 (h)->bitmap[idx] |= 1 << bit;\
 407         } while (0)
 408
 409 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 410                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 411                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 412                 (h)->bitmap[idx] &= ~(1 << bit);\
 413         } while (0)
 414
 415 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 416                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 417                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 418                 (r) = (h)->bitmap[idx] >> bit & 1;\
 419         } while (0)
 420
 421 int ixgbe_logtype_init;
 422 int ixgbe_logtype_driver;
 423
 424 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
 425 int ixgbe_logtype_rx;
 426 #endif
 427 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
 428 int ixgbe_logtype_tx;
 429 #endif
 430 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
 431 int ixgbe_logtype_tx_free;
 432 #endif
 433
 434 /*
 435  * The set of PCI devices this driver supports
 436  */
 437 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 486 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 488 #endif
 489         { .vendor_id = 0, /* sentinel */ },
 490 };
 491
 492 /*
 493  * The set of PCI devices this driver supports (for 82599 VF)
 494  */
 495 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 504         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 505         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 506         { .vendor_id = 0, /* sentinel */ },
 507 };
 508
 509 static const struct rte_eth_desc_lim rx_desc_lim = {
 510         .nb_max = IXGBE_MAX_RING_DESC,
 511         .nb_min = IXGBE_MIN_RING_DESC,
 512         .nb_align = IXGBE_RXD_ALIGN,
 513 };
 514
 515 static const struct rte_eth_desc_lim tx_desc_lim = {
 516         .nb_max = IXGBE_MAX_RING_DESC,
 517         .nb_min = IXGBE_MIN_RING_DESC,
 518         .nb_align = IXGBE_TXD_ALIGN,
 519         .nb_seg_max = IXGBE_TX_MAX_SEG,
 520         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 521 };
 522
 523 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 524         .dev_configure        = ixgbe_dev_configure,
 525         .dev_start            = ixgbe_dev_start,
 526         .dev_stop             = ixgbe_dev_stop,
 527         .dev_set_link_up    = ixgbe_dev_set_link_up,
 528         .dev_set_link_down  = ixgbe_dev_set_link_down,
 529         .dev_close            = ixgbe_dev_close,
 530         .dev_reset            = ixgbe_dev_reset,
 531         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 532         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 533         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 534         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 535         .link_update          = ixgbe_dev_link_update,
 536         .stats_get            = ixgbe_dev_stats_get,
 537         .xstats_get           = ixgbe_dev_xstats_get,
 538         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 539         .stats_reset          = ixgbe_dev_stats_reset,
 540         .xstats_reset         = ixgbe_dev_xstats_reset,
 541         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 542         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 543         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 544         .fw_version_get       = ixgbe_fw_version_get,
 545         .dev_infos_get        = ixgbe_dev_info_get,
 546         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 547         .mtu_set              = ixgbe_dev_mtu_set,
 548         .vlan_filter_set      = ixgbe_vlan_filter_set,
 549         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 550         .vlan_offload_set     = ixgbe_vlan_offload_set,
 551         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 552         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 553         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 554         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 555         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 556         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 557         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 558         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 559         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 560         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 561         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 562         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 563         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 564         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 565         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 566         .dev_led_on           = ixgbe_dev_led_on,
 567         .dev_led_off          = ixgbe_dev_led_off,
 568         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 569         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 570         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 571         .mac_addr_add         = ixgbe_add_rar,
 572         .mac_addr_remove      = ixgbe_remove_rar,
 573         .mac_addr_set         = ixgbe_set_default_mac_addr,
 574         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 575         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 576         .mirror_rule_set      = ixgbe_mirror_rule_set,
 577         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 578         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 579         .reta_update          = ixgbe_dev_rss_reta_update,
 580         .reta_query           = ixgbe_dev_rss_reta_query,
 581         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 582         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 583         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 584         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 585         .rxq_info_get         = ixgbe_rxq_info_get,
 586         .txq_info_get         = ixgbe_txq_info_get,
 587         .timesync_enable      = ixgbe_timesync_enable,
 588         .timesync_disable     = ixgbe_timesync_disable,
 589         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 590         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 591         .get_reg              = ixgbe_get_regs,
 592         .get_eeprom_length    = ixgbe_get_eeprom_length,
 593         .get_eeprom           = ixgbe_get_eeprom,
 594         .set_eeprom           = ixgbe_set_eeprom,
 595         .get_module_info      = ixgbe_get_module_info,
 596         .get_module_eeprom    = ixgbe_get_module_eeprom,
 597         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 598         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 599         .timesync_read_time   = ixgbe_timesync_read_time,
 600         .timesync_write_time  = ixgbe_timesync_write_time,
 601         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 602         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 603         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 604         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 605         .tm_ops_get           = ixgbe_tm_ops_get,
 606         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 607 };
 608
 609 /*
 610  * dev_ops for virtual function, bare necessities for basic vf
 611  * operation have been implemented
 612  */
 613 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 614         .dev_configure        = ixgbevf_dev_configure,
 615         .dev_start            = ixgbevf_dev_start,
 616         .dev_stop             = ixgbevf_dev_stop,
 617         .link_update          = ixgbevf_dev_link_update,
 618         .stats_get            = ixgbevf_dev_stats_get,
 619         .xstats_get           = ixgbevf_dev_xstats_get,
 620         .stats_reset          = ixgbevf_dev_stats_reset,
 621         .xstats_reset         = ixgbevf_dev_stats_reset,
 622         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 623         .dev_close            = ixgbevf_dev_close,
 624         .dev_reset            = ixgbevf_dev_reset,
 625         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 626         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 627         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 628         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 629         .dev_infos_get        = ixgbevf_dev_info_get,
 630         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 631         .mtu_set              = ixgbevf_dev_set_mtu,
 632         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 633         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 634         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 635         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 636         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 637         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 638         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 639         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 640         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 641         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 642         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 643         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 644         .mac_addr_add         = ixgbevf_add_mac_addr,
 645         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 646         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 647         .rxq_info_get         = ixgbe_rxq_info_get,
 648         .txq_info_get         = ixgbe_txq_info_get,
 649         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 650         .get_reg              = ixgbevf_get_regs,
 651         .reta_update          = ixgbe_dev_rss_reta_update,
 652         .reta_query           = ixgbe_dev_rss_reta_query,
 653         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 654         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 655         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 656 };
 657
 658 /* store statistics names and its offset in stats structure */
 659 struct rte_ixgbe_xstats_name_off {
 660         char name[RTE_ETH_XSTATS_NAME_SIZE];
 661         unsigned offset;
 662 };
 663
 664 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 665         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 666         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 667         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 668         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 669         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 670         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 671         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 672         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 673         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 674         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 675         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 676         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 677         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 678         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 679         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 680                 prc1023)},
 681         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 682                 prc1522)},
 683         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 684         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 685         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 686         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 687         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 688         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 689         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 690         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 691         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 692         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 693         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 694         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 695         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 696         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 697         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 698         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 699         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 700                 ptc1023)},
 701         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 702                 ptc1522)},
 703         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 704         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 705         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 706         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 707
 708         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 709                 fdirustat_add)},
 710         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 711                 fdirustat_remove)},
 712         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 713                 fdirfstat_fadd)},
 714         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 715                 fdirfstat_fremove)},
 716         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 717                 fdirmatch)},
 718         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 719                 fdirmiss)},
 720
 721         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 722         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 723         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 724                 fclast)},
 725         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 726         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 727         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 728         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 729         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 730                 fcoe_noddp)},
 731         {"rx_fcoe_no_direct_data_placement_ext_buff",
 732                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 733
 734         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 735                 lxontxc)},
 736         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 737                 lxonrxc)},
 738         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 739                 lxofftxc)},
 740         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 741                 lxoffrxc)},
 742         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 743 };
 744
 745 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 746                            sizeof(rte_ixgbe_stats_strings[0]))
 747
 748 /* MACsec statistics */
 749 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 750         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 751                 out_pkts_untagged)},
 752         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 753                 out_pkts_encrypted)},
 754         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 755                 out_pkts_protected)},
 756         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 757                 out_octets_encrypted)},
 758         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 759                 out_octets_protected)},
 760         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 761                 in_pkts_untagged)},
 762         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 763                 in_pkts_badtag)},
 764         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 765                 in_pkts_nosci)},
 766         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 767                 in_pkts_unknownsci)},
 768         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 769                 in_octets_decrypted)},
 770         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 771                 in_octets_validated)},
 772         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 773                 in_pkts_unchecked)},
 774         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 775                 in_pkts_delayed)},
 776         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 777                 in_pkts_late)},
 778         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 779                 in_pkts_ok)},
 780         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 781                 in_pkts_invalid)},
 782         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 783                 in_pkts_notvalid)},
 784         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 785                 in_pkts_unusedsa)},
 786         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 787                 in_pkts_notusingsa)},
 788 };
 789
 790 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 791                            sizeof(rte_ixgbe_macsec_strings[0]))
 792
 793 /* Per-queue statistics */
 794 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 795         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 796         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 797         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 798         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 799 };
 800
 801 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 802                            sizeof(rte_ixgbe_rxq_strings[0]))
 803 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 804
 805 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 806         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 807         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 808         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 809                 pxon2offc)},
 810 };
 811
 812 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 813                            sizeof(rte_ixgbe_txq_strings[0]))
 814 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 815
 816 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 817         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 818 };
 819
 820 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 821                 sizeof(rte_ixgbevf_stats_strings[0]))
 822
 823 /*
 824  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 825  */
 826 static inline int
 827 ixgbe_is_sfp(struct ixgbe_hw *hw)
 828 {
 829         switch (hw->phy.type) {
 830         case ixgbe_phy_sfp_avago:
 831         case ixgbe_phy_sfp_ftl:
 832         case ixgbe_phy_sfp_intel:
 833         case ixgbe_phy_sfp_unknown:
 834         case ixgbe_phy_sfp_passive_tyco:
 835         case ixgbe_phy_sfp_passive_unknown:
 836                 return 1;
 837         default:
 838                 return 0;
 839         }
 840 }
 841
 842 static inline int32_t
 843 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 844 {
 845         uint32_t ctrl_ext;
 846         int32_t status;
 847
 848         status = ixgbe_reset_hw(hw);
 849
 850         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 851         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 852         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 853         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 854         IXGBE_WRITE_FLUSH(hw);
 855
 856         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 857                 status = IXGBE_SUCCESS;
 858         return status;
 859 }
 860
 861 static inline void
 862 ixgbe_enable_intr(struct rte_eth_dev *dev)
 863 {
 864         struct ixgbe_interrupt *intr =
 865                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 866         struct ixgbe_hw *hw =
 867                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 868
 869         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 870         IXGBE_WRITE_FLUSH(hw);
 871 }
 872
 873 /*
 874  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 875  */
 876 static void
 877 ixgbe_disable_intr(struct ixgbe_hw *hw)
 878 {
 879         PMD_INIT_FUNC_TRACE();
 880
 881         if (hw->mac.type == ixgbe_mac_82598EB) {
 882                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 883         } else {
 884                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 885                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 886                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 887         }
 888         IXGBE_WRITE_FLUSH(hw);
 889 }
 890
 891 /*
 892  * This function resets queue statistics mapping registers.
 893  * From Niantic datasheet, Initialization of Statistics section:
 894  * "...if software requires the queue counters, the RQSMR and TQSM registers
 895  * must be re-programmed following a device reset.
 896  */
 897 static void
 898 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 899 {
 900         uint32_t i;
 901
 902         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 903                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 904                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 905         }
 906 }
 907
 908
 909 static int
 910 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 911                                   uint16_t queue_id,
 912                                   uint8_t stat_idx,
 913                                   uint8_t is_rx)
 914 {
 915 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 916 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 917 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 918
 919         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 920         struct ixgbe_stat_mapping_registers *stat_mappings =
 921                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 922         uint32_t qsmr_mask = 0;
 923         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 924         uint32_t q_map;
 925         uint8_t n, offset;
 926
 927         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 928                 (hw->mac.type != ixgbe_mac_X540) &&
 929                 (hw->mac.type != ixgbe_mac_X550) &&
 930                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 931                 (hw->mac.type != ixgbe_mac_X550EM_a))
 932                 return -ENOSYS;
 933
 934         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 935                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 936                      queue_id, stat_idx);
 937
 938         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 939         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 940                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 941                 return -EIO;
 942         }
 943         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 944
 945         /* Now clear any previous stat_idx set */
 946         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 947         if (!is_rx)
 948                 stat_mappings->tqsm[n] &= ~clearing_mask;
 949         else
 950                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 951
 952         q_map = (uint32_t)stat_idx;
 953         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 954         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 955         if (!is_rx)
 956                 stat_mappings->tqsm[n] |= qsmr_mask;
 957         else
 958                 stat_mappings->rqsmr[n] |= qsmr_mask;
 959
 960         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 961                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 962                      queue_id, stat_idx);
 963         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 964                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 965
 966         /* Now write the mapping in the appropriate register */
 967         if (is_rx) {
 968                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 969                              stat_mappings->rqsmr[n], n);
 970                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 971         } else {
 972                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 973                              stat_mappings->tqsm[n], n);
 974                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 975         }
 976         return 0;
 977 }
 978
 979 static void
 980 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 981 {
 982         struct ixgbe_stat_mapping_registers *stat_mappings =
 983                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 984         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 985         int i;
 986
 987         /* write whatever was in stat mapping table to the NIC */
 988         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 989                 /* rx */
 990                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 991
 992                 /* tx */
 993                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 994         }
 995 }
 996
 997 static void
 998 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 999 {
1000         uint8_t i;
1001         struct ixgbe_dcb_tc_config *tc;
1002         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1003
1004         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1005         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1006         for (i = 0; i < dcb_max_tc; i++) {
1007                 tc = &dcb_config->tc_config[i];
1008                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1009                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1010                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1011                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1012                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1013                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1014                 tc->pfc = ixgbe_dcb_pfc_disabled;
1015         }
1016
1017         /* Initialize default user to priority mapping, UPx->TC0 */
1018         tc = &dcb_config->tc_config[0];
1019         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1020         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1021         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1022                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1023                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1024         }
1025         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1026         dcb_config->pfc_mode_enable = false;
1027         dcb_config->vt_mode = true;
1028         dcb_config->round_robin_enable = false;
1029         /* support all DCB capabilities in 82599 */
1030         dcb_config->support.capabilities = 0xFF;
1031
1032         /*we only support 4 Tcs for X540, X550 */
1033         if (hw->mac.type == ixgbe_mac_X540 ||
1034                 hw->mac.type == ixgbe_mac_X550 ||
1035                 hw->mac.type == ixgbe_mac_X550EM_x ||
1036                 hw->mac.type == ixgbe_mac_X550EM_a) {
1037                 dcb_config->num_tcs.pg_tcs = 4;
1038                 dcb_config->num_tcs.pfc_tcs = 4;
1039         }
1040 }
1041
1042 /*
1043  * Ensure that all locks are released before first NVM or PHY access
1044  */
1045 static void
1046 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1047 {
1048         uint16_t mask;
1049
1050         /*
1051          * Phy lock should not fail in this early stage. If this is the case,
1052          * it is due to an improper exit of the application.
1053          * So force the release of the faulty lock. Release of common lock
1054          * is done automatically by swfw_sync function.
1055          */
1056         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1057         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1058                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1059         }
1060         ixgbe_release_swfw_semaphore(hw, mask);
1061
1062         /*
1063          * These ones are more tricky since they are common to all ports; but
1064          * swfw_sync retries last long enough (1s) to be almost sure that if
1065          * lock can not be taken it is due to an improper lock of the
1066          * semaphore.
1067          */
1068         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1069         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1070                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1071         }
1072         ixgbe_release_swfw_semaphore(hw, mask);
1073 }
1074
1075 /*
1076  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1077  * It returns 0 on success.
1078  */
1079 static int
1080 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1081 {
1082         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1083         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1084         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1085         struct ixgbe_hw *hw =
1086                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1087         struct ixgbe_vfta *shadow_vfta =
1088                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1089         struct ixgbe_hwstrip *hwstrip =
1090                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1091         struct ixgbe_dcb_config *dcb_config =
1092                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1093         struct ixgbe_filter_info *filter_info =
1094                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1095         struct ixgbe_bw_conf *bw_conf =
1096                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1097         uint32_t ctrl_ext;
1098         uint16_t csum;
1099         int diag, i;
1100
1101         PMD_INIT_FUNC_TRACE();
1102
1103         ixgbe_dev_macsec_setting_reset(eth_dev);
1104
1105         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1106         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1107         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1108         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1109
1110         /*
1111          * For secondary processes, we don't initialise any further as primary
1112          * has already done this work. Only check we don't need a different
1113          * RX and TX function.
1114          */
1115         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1116                 struct ixgbe_tx_queue *txq;
1117                 /* TX queue function in primary, set by last queue initialized
1118                  * Tx queue may not initialized by primary process
1119                  */
1120                 if (eth_dev->data->tx_queues) {
1121                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1122                         ixgbe_set_tx_function(eth_dev, txq);
1123                 } else {
1124                         /* Use default TX function if we get here */
1125                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1126                                      "Using default TX function.");
1127                 }
1128
1129                 ixgbe_set_rx_function(eth_dev);
1130
1131                 return 0;
1132         }
1133
1134         rte_atomic32_clear(&ad->link_thread_running);
1135         rte_eth_copy_pci_info(eth_dev, pci_dev);
1136
1137         /* Vendor and Device ID need to be set before init of shared code */
1138         hw->device_id = pci_dev->id.device_id;
1139         hw->vendor_id = pci_dev->id.vendor_id;
1140         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1141         hw->allow_unsupported_sfp = 1;
1142
1143         /* Initialize the shared code (base driver) */
1144 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1145         diag = ixgbe_bypass_init_shared_code(hw);
1146 #else
1147         diag = ixgbe_init_shared_code(hw);
1148 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1149
1150         if (diag != IXGBE_SUCCESS) {
1151                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1152                 return -EIO;
1153         }
1154
1155         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1156                 PMD_INIT_LOG(ERR, "\nERROR: "
1157                         "Firmware recovery mode detected. Limiting functionality.\n"
1158                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1159                         "User Guide for details on firmware recovery mode.");
1160                 return -EIO;
1161         }
1162
1163         /* pick up the PCI bus settings for reporting later */
1164         ixgbe_get_bus_info(hw);
1165
1166         /* Unlock any pending hardware semaphore */
1167         ixgbe_swfw_lock_reset(hw);
1168
1169 #ifdef RTE_LIBRTE_SECURITY
1170         /* Initialize security_ctx only for primary process*/
1171         if (ixgbe_ipsec_ctx_create(eth_dev))
1172                 return -ENOMEM;
1173 #endif
1174
1175         /* Initialize DCB configuration*/
1176         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1177         ixgbe_dcb_init(hw, dcb_config);
1178         /* Get Hardware Flow Control setting */
1179         hw->fc.requested_mode = ixgbe_fc_full;
1180         hw->fc.current_mode = ixgbe_fc_full;
1181         hw->fc.pause_time = IXGBE_FC_PAUSE;
1182         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1183                 hw->fc.low_water[i] = IXGBE_FC_LO;
1184                 hw->fc.high_water[i] = IXGBE_FC_HI;
1185         }
1186         hw->fc.send_xon = 1;
1187
1188         /* Make sure we have a good EEPROM before we read from it */
1189         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1190         if (diag != IXGBE_SUCCESS) {
1191                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1192                 return -EIO;
1193         }
1194
1195 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1196         diag = ixgbe_bypass_init_hw(hw);
1197 #else
1198         diag = ixgbe_init_hw(hw);
1199         hw->mac.autotry_restart = false;
1200 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1201
1202         /*
1203          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1204          * is called too soon after the kernel driver unbinding/binding occurs.
1205          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1206          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1207          * also called. See ixgbe_identify_phy_82599(). The reason for the
1208          * failure is not known, and only occuts when virtualisation features
1209          * are disabled in the bios. A delay of 100ms  was found to be enough by
1210          * trial-and-error, and is doubled to be safe.
1211          */
1212         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1213                 rte_delay_ms(200);
1214                 diag = ixgbe_init_hw(hw);
1215         }
1216
1217         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1218                 diag = IXGBE_SUCCESS;
1219
1220         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1221                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1222                              "LOM.  Please be aware there may be issues associated "
1223                              "with your hardware.");
1224                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1225                              "please contact your Intel or hardware representative "
1226                              "who provided you with this hardware.");
1227         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1228                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1229         if (diag) {
1230                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1231                 return -EIO;
1232         }
1233
1234         /* Reset the hw statistics */
1235         ixgbe_dev_stats_reset(eth_dev);
1236
1237         /* disable interrupt */
1238         ixgbe_disable_intr(hw);
1239
1240         /* reset mappings for queue statistics hw counters*/
1241         ixgbe_reset_qstat_mappings(hw);
1242
1243         /* Allocate memory for storing MAC addresses */
1244         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1245                                                hw->mac.num_rar_entries, 0);
1246         if (eth_dev->data->mac_addrs == NULL) {
1247                 PMD_INIT_LOG(ERR,
1248                              "Failed to allocate %u bytes needed to store "
1249                              "MAC addresses",
1250                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1251                 return -ENOMEM;
1252         }
1253         /* Copy the permanent MAC address */
1254         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1255                         &eth_dev->data->mac_addrs[0]);
1256
1257         /* Allocate memory for storing hash filter MAC addresses */
1258         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1259                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1260         if (eth_dev->data->hash_mac_addrs == NULL) {
1261                 PMD_INIT_LOG(ERR,
1262                              "Failed to allocate %d bytes needed to store MAC addresses",
1263                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1264                 return -ENOMEM;
1265         }
1266
1267         /* Pass the information to the rte_eth_dev_close() that it should also
1268          * release the private port resources.
1269          */
1270         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1271
1272         /* initialize the vfta */
1273         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1274
1275         /* initialize the hw strip bitmap*/
1276         memset(hwstrip, 0, sizeof(*hwstrip));
1277
1278         /* initialize PF if max_vfs not zero */
1279         ixgbe_pf_host_init(eth_dev);
1280
1281         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1282         /* let hardware know driver is loaded */
1283         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1284         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1285         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1286         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1287         IXGBE_WRITE_FLUSH(hw);
1288
1289         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1290                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1291                              (int) hw->mac.type, (int) hw->phy.type,
1292                              (int) hw->phy.sfp_type);
1293         else
1294                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1295                              (int) hw->mac.type, (int) hw->phy.type);
1296
1297         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1298                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1299                      pci_dev->id.device_id);
1300
1301         rte_intr_callback_register(intr_handle,
1302                                    ixgbe_dev_interrupt_handler, eth_dev);
1303
1304         /* enable uio/vfio intr/eventfd mapping */
1305         rte_intr_enable(intr_handle);
1306
1307         /* enable support intr */
1308         ixgbe_enable_intr(eth_dev);
1309
1310         ixgbe_dev_set_link_down(eth_dev);
1311
1312         /* initialize filter info */
1313         memset(filter_info, 0,
1314                sizeof(struct ixgbe_filter_info));
1315
1316         /* initialize 5tuple filter list */
1317         TAILQ_INIT(&filter_info->fivetuple_list);
1318
1319         /* initialize flow director filter list & hash */
1320         ixgbe_fdir_filter_init(eth_dev);
1321
1322         /* initialize l2 tunnel filter list & hash */
1323         ixgbe_l2_tn_filter_init(eth_dev);
1324
1325         /* initialize flow filter lists */
1326         ixgbe_filterlist_init();
1327
1328         /* initialize bandwidth configuration info */
1329         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1330
1331         /* initialize Traffic Manager configuration */
1332         ixgbe_tm_conf_init(eth_dev);
1333
1334         return 0;
1335 }
1336
1337 static int
1338 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1339 {
1340         PMD_INIT_FUNC_TRACE();
1341
1342         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1343                 return 0;
1344
1345         ixgbe_dev_close(eth_dev);
1346
1347         return 0;
1348 }
1349
1350 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1351 {
1352         struct ixgbe_filter_info *filter_info =
1353                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1354         struct ixgbe_5tuple_filter *p_5tuple;
1355
1356         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1357                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1358                              p_5tuple,
1359                              entries);
1360                 rte_free(p_5tuple);
1361         }
1362         memset(filter_info->fivetuple_mask, 0,
1363                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1364
1365         return 0;
1366 }
1367
1368 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1369 {
1370         struct ixgbe_hw_fdir_info *fdir_info =
1371                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1372         struct ixgbe_fdir_filter *fdir_filter;
1373
1374                 if (fdir_info->hash_map)
1375                 rte_free(fdir_info->hash_map);
1376         if (fdir_info->hash_handle)
1377                 rte_hash_free(fdir_info->hash_handle);
1378
1379         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1380                 TAILQ_REMOVE(&fdir_info->fdir_list,
1381                              fdir_filter,
1382                              entries);
1383                 rte_free(fdir_filter);
1384         }
1385
1386         return 0;
1387 }
1388
1389 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1390 {
1391         struct ixgbe_l2_tn_info *l2_tn_info =
1392                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1393         struct ixgbe_l2_tn_filter *l2_tn_filter;
1394
1395         if (l2_tn_info->hash_map)
1396                 rte_free(l2_tn_info->hash_map);
1397         if (l2_tn_info->hash_handle)
1398                 rte_hash_free(l2_tn_info->hash_handle);
1399
1400         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1401                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1402                              l2_tn_filter,
1403                              entries);
1404                 rte_free(l2_tn_filter);
1405         }
1406
1407         return 0;
1408 }
1409
1410 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1411 {
1412         struct ixgbe_hw_fdir_info *fdir_info =
1413                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1414         char fdir_hash_name[RTE_HASH_NAMESIZE];
1415         struct rte_hash_parameters fdir_hash_params = {
1416                 .name = fdir_hash_name,
1417                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1418                 .key_len = sizeof(union ixgbe_atr_input),
1419                 .hash_func = rte_hash_crc,
1420                 .hash_func_init_val = 0,
1421                 .socket_id = rte_socket_id(),
1422         };
1423
1424         TAILQ_INIT(&fdir_info->fdir_list);
1425         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1426                  "fdir_%s", eth_dev->device->name);
1427         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1428         if (!fdir_info->hash_handle) {
1429                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1430                 return -EINVAL;
1431         }
1432         fdir_info->hash_map = rte_zmalloc("ixgbe",
1433                                           sizeof(struct ixgbe_fdir_filter *) *
1434                                           IXGBE_MAX_FDIR_FILTER_NUM,
1435                                           0);
1436         if (!fdir_info->hash_map) {
1437                 PMD_INIT_LOG(ERR,
1438                              "Failed to allocate memory for fdir hash map!");
1439                 return -ENOMEM;
1440         }
1441         fdir_info->mask_added = FALSE;
1442
1443         return 0;
1444 }
1445
1446 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1447 {
1448         struct ixgbe_l2_tn_info *l2_tn_info =
1449                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1450         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1451         struct rte_hash_parameters l2_tn_hash_params = {
1452                 .name = l2_tn_hash_name,
1453                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1454                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1455                 .hash_func = rte_hash_crc,
1456                 .hash_func_init_val = 0,
1457                 .socket_id = rte_socket_id(),
1458         };
1459
1460         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1461         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1462                  "l2_tn_%s", eth_dev->device->name);
1463         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1464         if (!l2_tn_info->hash_handle) {
1465                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1466                 return -EINVAL;
1467         }
1468         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1469                                    sizeof(struct ixgbe_l2_tn_filter *) *
1470                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1471                                    0);
1472         if (!l2_tn_info->hash_map) {
1473                 PMD_INIT_LOG(ERR,
1474                         "Failed to allocate memory for L2 TN hash map!");
1475                 return -ENOMEM;
1476         }
1477         l2_tn_info->e_tag_en = FALSE;
1478         l2_tn_info->e_tag_fwd_en = FALSE;
1479         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1480
1481         return 0;
1482 }
1483 /*
1484  * Negotiate mailbox API version with the PF.
1485  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1486  * Then we try to negotiate starting with the most recent one.
1487  * If all negotiation attempts fail, then we will proceed with
1488  * the default one (ixgbe_mbox_api_10).
1489  */
1490 static void
1491 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1492 {
1493         int32_t i;
1494
1495         /* start with highest supported, proceed down */
1496         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1497                 ixgbe_mbox_api_13,
1498                 ixgbe_mbox_api_12,
1499                 ixgbe_mbox_api_11,
1500                 ixgbe_mbox_api_10,
1501         };
1502
1503         for (i = 0;
1504                         i != RTE_DIM(sup_ver) &&
1505                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1506                         i++)
1507                 ;
1508 }
1509
1510 static void
1511 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1512 {
1513         uint64_t random;
1514
1515         /* Set Organizationally Unique Identifier (OUI) prefix. */
1516         mac_addr->addr_bytes[0] = 0x00;
1517         mac_addr->addr_bytes[1] = 0x09;
1518         mac_addr->addr_bytes[2] = 0xC0;
1519         /* Force indication of locally assigned MAC address. */
1520         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1521         /* Generate the last 3 bytes of the MAC address with a random number. */
1522         random = rte_rand();
1523         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1524 }
1525
1526 static int
1527 devarg_handle_int(__rte_unused const char *key, const char *value,
1528                   void *extra_args)
1529 {
1530         uint16_t *n = extra_args;
1531
1532         if (value == NULL || extra_args == NULL)
1533                 return -EINVAL;
1534
1535         *n = (uint16_t)strtoul(value, NULL, 0);
1536         if (*n == USHRT_MAX && errno == ERANGE)
1537                 return -1;
1538
1539         return 0;
1540 }
1541
1542 static void
1543 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1544                       struct rte_devargs *devargs)
1545 {
1546         struct rte_kvargs *kvlist;
1547         uint16_t pflink_fullchk;
1548
1549         if (devargs == NULL)
1550                 return;
1551
1552         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1553         if (kvlist == NULL)
1554                 return;
1555
1556         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1557             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1558                                devarg_handle_int, &pflink_fullchk) == 0 &&
1559             pflink_fullchk == 1)
1560                 adapter->pflink_fullchk = 1;
1561
1562         rte_kvargs_free(kvlist);
1563 }
1564
1565 /*
1566  * Virtual Function device init
1567  */
1568 static int
1569 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1570 {
1571         int diag;
1572         uint32_t tc, tcs;
1573         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1574         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1575         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1576         struct ixgbe_hw *hw =
1577                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1578         struct ixgbe_vfta *shadow_vfta =
1579                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1580         struct ixgbe_hwstrip *hwstrip =
1581                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1582         struct rte_ether_addr *perm_addr =
1583                 (struct rte_ether_addr *)hw->mac.perm_addr;
1584
1585         PMD_INIT_FUNC_TRACE();
1586
1587         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1588         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1589         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1590
1591         /* for secondary processes, we don't initialise any further as primary
1592          * has already done this work. Only check we don't need a different
1593          * RX function
1594          */
1595         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1596                 struct ixgbe_tx_queue *txq;
1597                 /* TX queue function in primary, set by last queue initialized
1598                  * Tx queue may not initialized by primary process
1599                  */
1600                 if (eth_dev->data->tx_queues) {
1601                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1602                         ixgbe_set_tx_function(eth_dev, txq);
1603                 } else {
1604                         /* Use default TX function if we get here */
1605                         PMD_INIT_LOG(NOTICE,
1606                                      "No TX queues configured yet. Using default TX function.");
1607                 }
1608
1609                 ixgbe_set_rx_function(eth_dev);
1610
1611                 return 0;
1612         }
1613
1614         rte_atomic32_clear(&ad->link_thread_running);
1615         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1616                               pci_dev->device.devargs);
1617
1618         rte_eth_copy_pci_info(eth_dev, pci_dev);
1619
1620         hw->device_id = pci_dev->id.device_id;
1621         hw->vendor_id = pci_dev->id.vendor_id;
1622         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1623
1624         /* initialize the vfta */
1625         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1626
1627         /* initialize the hw strip bitmap*/
1628         memset(hwstrip, 0, sizeof(*hwstrip));
1629
1630         /* Initialize the shared code (base driver) */
1631         diag = ixgbe_init_shared_code(hw);
1632         if (diag != IXGBE_SUCCESS) {
1633                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1634                 return -EIO;
1635         }
1636
1637         /* init_mailbox_params */
1638         hw->mbx.ops.init_params(hw);
1639
1640         /* Reset the hw statistics */
1641         ixgbevf_dev_stats_reset(eth_dev);
1642
1643         /* Disable the interrupts for VF */
1644         ixgbevf_intr_disable(eth_dev);
1645
1646         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1647         diag = hw->mac.ops.reset_hw(hw);
1648
1649         /*
1650          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1651          * the underlying PF driver has not assigned a MAC address to the VF.
1652          * In this case, assign a random MAC address.
1653          */
1654         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1655                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1656                 /*
1657                  * This error code will be propagated to the app by
1658                  * rte_eth_dev_reset, so use a public error code rather than
1659                  * the internal-only IXGBE_ERR_RESET_FAILED
1660                  */
1661                 return -EAGAIN;
1662         }
1663
1664         /* negotiate mailbox API version to use with the PF. */
1665         ixgbevf_negotiate_api(hw);
1666
1667         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1668         ixgbevf_get_queues(hw, &tcs, &tc);
1669
1670         /* Allocate memory for storing MAC addresses */
1671         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1672                                                hw->mac.num_rar_entries, 0);
1673         if (eth_dev->data->mac_addrs == NULL) {
1674                 PMD_INIT_LOG(ERR,
1675                              "Failed to allocate %u bytes needed to store "
1676                              "MAC addresses",
1677                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1678                 return -ENOMEM;
1679         }
1680
1681         /* Pass the information to the rte_eth_dev_close() that it should also
1682          * release the private port resources.
1683          */
1684         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1685
1686         /* Generate a random MAC address, if none was assigned by PF. */
1687         if (rte_is_zero_ether_addr(perm_addr)) {
1688                 generate_random_mac_addr(perm_addr);
1689                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1690                 if (diag) {
1691                         rte_free(eth_dev->data->mac_addrs);
1692                         eth_dev->data->mac_addrs = NULL;
1693                         return diag;
1694                 }
1695                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1696                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1697                              "%02x:%02x:%02x:%02x:%02x:%02x",
1698                              perm_addr->addr_bytes[0],
1699                              perm_addr->addr_bytes[1],
1700                              perm_addr->addr_bytes[2],
1701                              perm_addr->addr_bytes[3],
1702                              perm_addr->addr_bytes[4],
1703                              perm_addr->addr_bytes[5]);
1704         }
1705
1706         /* Copy the permanent MAC address */
1707         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1708
1709         /* reset the hardware with the new settings */
1710         diag = hw->mac.ops.start_hw(hw);
1711         switch (diag) {
1712         case  0:
1713                 break;
1714
1715         default:
1716                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1717                 return -EIO;
1718         }
1719
1720         rte_intr_callback_register(intr_handle,
1721                                    ixgbevf_dev_interrupt_handler, eth_dev);
1722         rte_intr_enable(intr_handle);
1723         ixgbevf_intr_enable(eth_dev);
1724
1725         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1726                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1727                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1728
1729         return 0;
1730 }
1731
1732 /* Virtual Function device uninit */
1733
1734 static int
1735 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1736 {
1737         PMD_INIT_FUNC_TRACE();
1738
1739         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1740                 return 0;
1741
1742         ixgbevf_dev_close(eth_dev);
1743
1744         return 0;
1745 }
1746
1747 static int
1748 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1749                 struct rte_pci_device *pci_dev)
1750 {
1751         char name[RTE_ETH_NAME_MAX_LEN];
1752         struct rte_eth_dev *pf_ethdev;
1753         struct rte_eth_devargs eth_da;
1754         int i, retval;
1755
1756         if (pci_dev->device.devargs) {
1757                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1758                                 &eth_da);
1759                 if (retval)
1760                         return retval;
1761         } else
1762                 memset(&eth_da, 0, sizeof(eth_da));
1763
1764         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1765                 sizeof(struct ixgbe_adapter),
1766                 eth_dev_pci_specific_init, pci_dev,
1767                 eth_ixgbe_dev_init, NULL);
1768
1769         if (retval || eth_da.nb_representor_ports < 1)
1770                 return retval;
1771
1772         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1773         if (pf_ethdev == NULL)
1774                 return -ENODEV;
1775
1776         /* probe VF representor ports */
1777         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1778                 struct ixgbe_vf_info *vfinfo;
1779                 struct ixgbe_vf_representor representor;
1780
1781                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1782                         pf_ethdev->data->dev_private);
1783                 if (vfinfo == NULL) {
1784                         PMD_DRV_LOG(ERR,
1785                                 "no virtual functions supported by PF");
1786                         break;
1787                 }
1788
1789                 representor.vf_id = eth_da.representor_ports[i];
1790                 representor.switch_domain_id = vfinfo->switch_domain_id;
1791                 representor.pf_ethdev = pf_ethdev;
1792
1793                 /* representor port net_bdf_port */
1794                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1795                         pci_dev->device.name,
1796                         eth_da.representor_ports[i]);
1797
1798                 retval = rte_eth_dev_create(&pci_dev->device, name,
1799                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1800                         ixgbe_vf_representor_init, &representor);
1801
1802                 if (retval)
1803                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1804                                 "representor %s.", name);
1805         }
1806
1807         return 0;
1808 }
1809
1810 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1811 {
1812         struct rte_eth_dev *ethdev;
1813
1814         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1815         if (!ethdev)
1816                 return 0;
1817
1818         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1819                 return rte_eth_dev_pci_generic_remove(pci_dev,
1820                                         ixgbe_vf_representor_uninit);
1821         else
1822                 return rte_eth_dev_pci_generic_remove(pci_dev,
1823                                                 eth_ixgbe_dev_uninit);
1824 }
1825
1826 static struct rte_pci_driver rte_ixgbe_pmd = {
1827         .id_table = pci_id_ixgbe_map,
1828         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1829         .probe = eth_ixgbe_pci_probe,
1830         .remove = eth_ixgbe_pci_remove,
1831 };
1832
1833 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1834         struct rte_pci_device *pci_dev)
1835 {
1836         return rte_eth_dev_pci_generic_probe(pci_dev,
1837                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1838 }
1839
1840 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1841 {
1842         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1843 }
1844
1845 /*
1846  * virtual function driver struct
1847  */
1848 static struct rte_pci_driver rte_ixgbevf_pmd = {
1849         .id_table = pci_id_ixgbevf_map,
1850         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1851         .probe = eth_ixgbevf_pci_probe,
1852         .remove = eth_ixgbevf_pci_remove,
1853 };
1854
1855 static int
1856 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1857 {
1858         struct ixgbe_hw *hw =
1859                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1860         struct ixgbe_vfta *shadow_vfta =
1861                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1862         uint32_t vfta;
1863         uint32_t vid_idx;
1864         uint32_t vid_bit;
1865
1866         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1867         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1868         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1869         if (on)
1870                 vfta |= vid_bit;
1871         else
1872                 vfta &= ~vid_bit;
1873         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1874
1875         /* update local VFTA copy */
1876         shadow_vfta->vfta[vid_idx] = vfta;
1877
1878         return 0;
1879 }
1880
1881 static void
1882 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1883 {
1884         if (on)
1885                 ixgbe_vlan_hw_strip_enable(dev, queue);
1886         else
1887                 ixgbe_vlan_hw_strip_disable(dev, queue);
1888 }
1889
1890 static int
1891 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1892                     enum rte_vlan_type vlan_type,
1893                     uint16_t tpid)
1894 {
1895         struct ixgbe_hw *hw =
1896                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1897         int ret = 0;
1898         uint32_t reg;
1899         uint32_t qinq;
1900
1901         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1902         qinq &= IXGBE_DMATXCTL_GDV;
1903
1904         switch (vlan_type) {
1905         case ETH_VLAN_TYPE_INNER:
1906                 if (qinq) {
1907                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1908                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1909                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1910                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1911                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1912                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1913                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1914                 } else {
1915                         ret = -ENOTSUP;
1916                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1917                                     " by single VLAN");
1918                 }
1919                 break;
1920         case ETH_VLAN_TYPE_OUTER:
1921                 if (qinq) {
1922                         /* Only the high 16-bits is valid */
1923                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1924                                         IXGBE_EXVET_VET_EXT_SHIFT);
1925                 } else {
1926                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1927                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1928                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1929                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1930                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1931                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1932                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1933                 }
1934
1935                 break;
1936         default:
1937                 ret = -EINVAL;
1938                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1939                 break;
1940         }
1941
1942         return ret;
1943 }
1944
1945 void
1946 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1947 {
1948         struct ixgbe_hw *hw =
1949                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1950         uint32_t vlnctrl;
1951
1952         PMD_INIT_FUNC_TRACE();
1953
1954         /* Filter Table Disable */
1955         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1956         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1957
1958         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1959 }
1960
1961 void
1962 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1963 {
1964         struct ixgbe_hw *hw =
1965                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1966         struct ixgbe_vfta *shadow_vfta =
1967                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1968         uint32_t vlnctrl;
1969         uint16_t i;
1970
1971         PMD_INIT_FUNC_TRACE();
1972
1973         /* Filter Table Enable */
1974         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1975         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1976         vlnctrl |= IXGBE_VLNCTRL_VFE;
1977
1978         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1979
1980         /* write whatever is in local vfta copy */
1981         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1982                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1983 }
1984
1985 static void
1986 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1987 {
1988         struct ixgbe_hwstrip *hwstrip =
1989                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1990         struct ixgbe_rx_queue *rxq;
1991
1992         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1993                 return;
1994
1995         if (on)
1996                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1997         else
1998                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1999
2000         if (queue >= dev->data->nb_rx_queues)
2001                 return;
2002
2003         rxq = dev->data->rx_queues[queue];
2004
2005         if (on) {
2006                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2007                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2008         } else {
2009                 rxq->vlan_flags = PKT_RX_VLAN;
2010                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2011         }
2012 }
2013
2014 static void
2015 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2016 {
2017         struct ixgbe_hw *hw =
2018                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2019         uint32_t ctrl;
2020
2021         PMD_INIT_FUNC_TRACE();
2022
2023         if (hw->mac.type == ixgbe_mac_82598EB) {
2024                 /* No queue level support */
2025                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2026                 return;
2027         }
2028
2029         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2030         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2031         ctrl &= ~IXGBE_RXDCTL_VME;
2032         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2033
2034         /* record those setting for HW strip per queue */
2035         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2036 }
2037
2038 static void
2039 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2040 {
2041         struct ixgbe_hw *hw =
2042                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2043         uint32_t ctrl;
2044
2045         PMD_INIT_FUNC_TRACE();
2046
2047         if (hw->mac.type == ixgbe_mac_82598EB) {
2048                 /* No queue level supported */
2049                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2050                 return;
2051         }
2052
2053         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2054         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2055         ctrl |= IXGBE_RXDCTL_VME;
2056         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2057
2058         /* record those setting for HW strip per queue */
2059         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2060 }
2061
2062 static void
2063 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2064 {
2065         struct ixgbe_hw *hw =
2066                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2067         uint32_t ctrl;
2068
2069         PMD_INIT_FUNC_TRACE();
2070
2071         /* DMATXCTRL: Geric Double VLAN Disable */
2072         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2073         ctrl &= ~IXGBE_DMATXCTL_GDV;
2074         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2075
2076         /* CTRL_EXT: Global Double VLAN Disable */
2077         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2078         ctrl &= ~IXGBE_EXTENDED_VLAN;
2079         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2080
2081 }
2082
2083 static void
2084 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2085 {
2086         struct ixgbe_hw *hw =
2087                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2088         uint32_t ctrl;
2089
2090         PMD_INIT_FUNC_TRACE();
2091
2092         /* DMATXCTRL: Geric Double VLAN Enable */
2093         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2094         ctrl |= IXGBE_DMATXCTL_GDV;
2095         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2096
2097         /* CTRL_EXT: Global Double VLAN Enable */
2098         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2099         ctrl |= IXGBE_EXTENDED_VLAN;
2100         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2101
2102         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2103         if (hw->mac.type == ixgbe_mac_X550 ||
2104             hw->mac.type == ixgbe_mac_X550EM_x ||
2105             hw->mac.type == ixgbe_mac_X550EM_a) {
2106                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2107                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2108                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2109         }
2110
2111         /*
2112          * VET EXT field in the EXVET register = 0x8100 by default
2113          * So no need to change. Same to VT field of DMATXCTL register
2114          */
2115 }
2116
2117 void
2118 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2119 {
2120         struct ixgbe_hw *hw =
2121                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2122         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2123         uint32_t ctrl;
2124         uint16_t i;
2125         struct ixgbe_rx_queue *rxq;
2126         bool on;
2127
2128         PMD_INIT_FUNC_TRACE();
2129
2130         if (hw->mac.type == ixgbe_mac_82598EB) {
2131                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2132                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2133                         ctrl |= IXGBE_VLNCTRL_VME;
2134                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2135                 } else {
2136                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2137                         ctrl &= ~IXGBE_VLNCTRL_VME;
2138                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2139                 }
2140         } else {
2141                 /*
2142                  * Other 10G NIC, the VLAN strip can be setup
2143                  * per queue in RXDCTL
2144                  */
2145                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2146                         rxq = dev->data->rx_queues[i];
2147                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2148                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2149                                 ctrl |= IXGBE_RXDCTL_VME;
2150                                 on = TRUE;
2151                         } else {
2152                                 ctrl &= ~IXGBE_RXDCTL_VME;
2153                                 on = FALSE;
2154                         }
2155                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2156
2157                         /* record those setting for HW strip per queue */
2158                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2159                 }
2160         }
2161 }
2162
2163 static void
2164 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2165 {
2166         uint16_t i;
2167         struct rte_eth_rxmode *rxmode;
2168         struct ixgbe_rx_queue *rxq;
2169
2170         if (mask & ETH_VLAN_STRIP_MASK) {
2171                 rxmode = &dev->data->dev_conf.rxmode;
2172                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2173                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2174                                 rxq = dev->data->rx_queues[i];
2175                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2176                         }
2177                 else
2178                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2179                                 rxq = dev->data->rx_queues[i];
2180                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2181                         }
2182         }
2183 }
2184
2185 static int
2186 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2187 {
2188         struct rte_eth_rxmode *rxmode;
2189         rxmode = &dev->data->dev_conf.rxmode;
2190
2191         if (mask & ETH_VLAN_STRIP_MASK) {
2192                 ixgbe_vlan_hw_strip_config(dev);
2193         }
2194
2195         if (mask & ETH_VLAN_FILTER_MASK) {
2196                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2197                         ixgbe_vlan_hw_filter_enable(dev);
2198                 else
2199                         ixgbe_vlan_hw_filter_disable(dev);
2200         }
2201
2202         if (mask & ETH_VLAN_EXTEND_MASK) {
2203                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2204                         ixgbe_vlan_hw_extend_enable(dev);
2205                 else
2206                         ixgbe_vlan_hw_extend_disable(dev);
2207         }
2208
2209         return 0;
2210 }
2211
2212 static int
2213 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2214 {
2215         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2216
2217         ixgbe_vlan_offload_config(dev, mask);
2218
2219         return 0;
2220 }
2221
2222 static void
2223 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2224 {
2225         struct ixgbe_hw *hw =
2226                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2227         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2228         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2229
2230         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2231         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2232 }
2233
2234 static int
2235 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2236 {
2237         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2238
2239         switch (nb_rx_q) {
2240         case 1:
2241         case 2:
2242                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2243                 break;
2244         case 4:
2245                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2246                 break;
2247         default:
2248                 return -EINVAL;
2249         }
2250
2251         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2252                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2253         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2254                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2255         return 0;
2256 }
2257
2258 static int
2259 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2260 {
2261         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2262         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2263         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2264         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2265
2266         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2267                 /* check multi-queue mode */
2268                 switch (dev_conf->rxmode.mq_mode) {
2269                 case ETH_MQ_RX_VMDQ_DCB:
2270                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2271                         break;
2272                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2273                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2274                         PMD_INIT_LOG(ERR, "SRIOV active,"
2275                                         " unsupported mq_mode rx %d.",
2276                                         dev_conf->rxmode.mq_mode);
2277                         return -EINVAL;
2278                 case ETH_MQ_RX_RSS:
2279                 case ETH_MQ_RX_VMDQ_RSS:
2280                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2281                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2282                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2283                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2284                                                 " invalid queue number"
2285                                                 " for VMDQ RSS, allowed"
2286                                                 " value are 1, 2 or 4.");
2287                                         return -EINVAL;
2288                                 }
2289                         break;
2290                 case ETH_MQ_RX_VMDQ_ONLY:
2291                 case ETH_MQ_RX_NONE:
2292                         /* if nothing mq mode configure, use default scheme */
2293                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2294                         break;
2295                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2296                         /* SRIOV only works in VMDq enable mode */
2297                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2298                                         " wrong mq_mode rx %d.",
2299                                         dev_conf->rxmode.mq_mode);
2300                         return -EINVAL;
2301                 }
2302
2303                 switch (dev_conf->txmode.mq_mode) {
2304                 case ETH_MQ_TX_VMDQ_DCB:
2305                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2306                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2307                         break;
2308                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2309                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2310                         break;
2311                 }
2312
2313                 /* check valid queue number */
2314                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2315                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2316                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2317                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2318                                         " must be less than or equal to %d.",
2319                                         nb_rx_q, nb_tx_q,
2320                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2321                         return -EINVAL;
2322                 }
2323         } else {
2324                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2325                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2326                                           " not supported.");
2327                         return -EINVAL;
2328                 }
2329                 /* check configuration for vmdb+dcb mode */
2330                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2331                         const struct rte_eth_vmdq_dcb_conf *conf;
2332
2333                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2334                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2335                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2336                                 return -EINVAL;
2337                         }
2338                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2339                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2340                                conf->nb_queue_pools == ETH_32_POOLS)) {
2341                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2342                                                 " nb_queue_pools must be %d or %d.",
2343                                                 ETH_16_POOLS, ETH_32_POOLS);
2344                                 return -EINVAL;
2345                         }
2346                 }
2347                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2348                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2349
2350                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2351                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2352                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2353                                 return -EINVAL;
2354                         }
2355                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2356                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2357                                conf->nb_queue_pools == ETH_32_POOLS)) {
2358                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2359                                                 " nb_queue_pools != %d and"
2360                                                 " nb_queue_pools != %d.",
2361                                                 ETH_16_POOLS, ETH_32_POOLS);
2362                                 return -EINVAL;
2363                         }
2364                 }
2365
2366                 /* For DCB mode check our configuration before we go further */
2367                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2368                         const struct rte_eth_dcb_rx_conf *conf;
2369
2370                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2371                         if (!(conf->nb_tcs == ETH_4_TCS ||
2372                                conf->nb_tcs == ETH_8_TCS)) {
2373                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2374                                                 " and nb_tcs != %d.",
2375                                                 ETH_4_TCS, ETH_8_TCS);
2376                                 return -EINVAL;
2377                         }
2378                 }
2379
2380                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2381                         const struct rte_eth_dcb_tx_conf *conf;
2382
2383                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2384                         if (!(conf->nb_tcs == ETH_4_TCS ||
2385                                conf->nb_tcs == ETH_8_TCS)) {
2386                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2387                                                 " and nb_tcs != %d.",
2388                                                 ETH_4_TCS, ETH_8_TCS);
2389                                 return -EINVAL;
2390                         }
2391                 }
2392
2393                 /*
2394                  * When DCB/VT is off, maximum number of queues changes,
2395                  * except for 82598EB, which remains constant.
2396                  */
2397                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2398                                 hw->mac.type != ixgbe_mac_82598EB) {
2399                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2400                                 PMD_INIT_LOG(ERR,
2401                                              "Neither VT nor DCB are enabled, "
2402                                              "nb_tx_q > %d.",
2403                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2404                                 return -EINVAL;
2405                         }
2406                 }
2407         }
2408         return 0;
2409 }
2410
2411 static int
2412 ixgbe_dev_configure(struct rte_eth_dev *dev)
2413 {
2414         struct ixgbe_interrupt *intr =
2415                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2416         struct ixgbe_adapter *adapter = dev->data->dev_private;
2417         int ret;
2418
2419         PMD_INIT_FUNC_TRACE();
2420
2421         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2422                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2423
2424         /* multipe queue mode checking */
2425         ret  = ixgbe_check_mq_mode(dev);
2426         if (ret != 0) {
2427                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2428                             ret);
2429                 return ret;
2430         }
2431
2432         /* set flag to update link status after init */
2433         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2434
2435         /*
2436          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2437          * allocation or vector Rx preconditions we will reset it.
2438          */
2439         adapter->rx_bulk_alloc_allowed = true;
2440         adapter->rx_vec_allowed = true;
2441
2442         return 0;
2443 }
2444
2445 static void
2446 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2447 {
2448         struct ixgbe_hw *hw =
2449                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2450         struct ixgbe_interrupt *intr =
2451                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2452         uint32_t gpie;
2453
2454         /* only set up it on X550EM_X */
2455         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2456                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2457                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2458                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2459                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2460                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2461         }
2462 }
2463
2464 int
2465 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2466                         uint16_t tx_rate, uint64_t q_msk)
2467 {
2468         struct ixgbe_hw *hw;
2469         struct ixgbe_vf_info *vfinfo;
2470         struct rte_eth_link link;
2471         uint8_t  nb_q_per_pool;
2472         uint32_t queue_stride;
2473         uint32_t queue_idx, idx = 0, vf_idx;
2474         uint32_t queue_end;
2475         uint16_t total_rate = 0;
2476         struct rte_pci_device *pci_dev;
2477         int ret;
2478
2479         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2480         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2481         if (ret < 0)
2482                 return ret;
2483
2484         if (vf >= pci_dev->max_vfs)
2485                 return -EINVAL;
2486
2487         if (tx_rate > link.link_speed)
2488                 return -EINVAL;
2489
2490         if (q_msk == 0)
2491                 return 0;
2492
2493         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2494         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2495         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2496         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2497         queue_idx = vf * queue_stride;
2498         queue_end = queue_idx + nb_q_per_pool - 1;
2499         if (queue_end >= hw->mac.max_tx_queues)
2500                 return -EINVAL;
2501
2502         if (vfinfo) {
2503                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2504                         if (vf_idx == vf)
2505                                 continue;
2506                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2507                                 idx++)
2508                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2509                 }
2510         } else {
2511                 return -EINVAL;
2512         }
2513
2514         /* Store tx_rate for this vf. */
2515         for (idx = 0; idx < nb_q_per_pool; idx++) {
2516                 if (((uint64_t)0x1 << idx) & q_msk) {
2517                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2518                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2519                         total_rate += tx_rate;
2520                 }
2521         }
2522
2523         if (total_rate > dev->data->dev_link.link_speed) {
2524                 /* Reset stored TX rate of the VF if it causes exceed
2525                  * link speed.
2526                  */
2527                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2528                 return -EINVAL;
2529         }
2530
2531         /* Set RTTBCNRC of each queue/pool for vf X  */
2532         for (; queue_idx <= queue_end; queue_idx++) {
2533                 if (0x1 & q_msk)
2534                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2535                 q_msk = q_msk >> 1;
2536         }
2537
2538         return 0;
2539 }
2540
2541 /*
2542  * Configure device link speed and setup link.
2543  * It returns 0 on success.
2544  */
2545 static int
2546 ixgbe_dev_start(struct rte_eth_dev *dev)
2547 {
2548         struct ixgbe_hw *hw =
2549                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2550         struct ixgbe_vf_info *vfinfo =
2551                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2552         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2553         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2554         uint32_t intr_vector = 0;
2555         int err;
2556         bool link_up = false, negotiate = 0;
2557         uint32_t speed = 0;
2558         uint32_t allowed_speeds = 0;
2559         int mask = 0;
2560         int status;
2561         uint16_t vf, idx;
2562         uint32_t *link_speeds;
2563         struct ixgbe_tm_conf *tm_conf =
2564                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2565         struct ixgbe_macsec_setting *macsec_setting =
2566                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2567
2568         PMD_INIT_FUNC_TRACE();
2569
2570         /* Stop the link setup handler before resetting the HW. */
2571         ixgbe_dev_cancel_link_thread(dev);
2572
2573         /* disable uio/vfio intr/eventfd mapping */
2574         rte_intr_disable(intr_handle);
2575
2576         /* stop adapter */
2577         hw->adapter_stopped = 0;
2578         ixgbe_stop_adapter(hw);
2579
2580         /* reinitialize adapter
2581          * this calls reset and start
2582          */
2583         status = ixgbe_pf_reset_hw(hw);
2584         if (status != 0)
2585                 return -1;
2586         hw->mac.ops.start_hw(hw);
2587         hw->mac.get_link_status = true;
2588
2589         /* configure PF module if SRIOV enabled */
2590         ixgbe_pf_host_configure(dev);
2591
2592         ixgbe_dev_phy_intr_setup(dev);
2593
2594         /* check and configure queue intr-vector mapping */
2595         if ((rte_intr_cap_multiple(intr_handle) ||
2596              !RTE_ETH_DEV_SRIOV(dev).active) &&
2597             dev->data->dev_conf.intr_conf.rxq != 0) {
2598                 intr_vector = dev->data->nb_rx_queues;
2599                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2600                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2601                                         IXGBE_MAX_INTR_QUEUE_NUM);
2602                         return -ENOTSUP;
2603                 }
2604                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2605                         return -1;
2606         }
2607
2608         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2609                 intr_handle->intr_vec =
2610                         rte_zmalloc("intr_vec",
2611                                     dev->data->nb_rx_queues * sizeof(int), 0);
2612                 if (intr_handle->intr_vec == NULL) {
2613                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2614                                      " intr_vec", dev->data->nb_rx_queues);
2615                         return -ENOMEM;
2616                 }
2617         }
2618
2619         /* confiugre msix for sleep until rx interrupt */
2620         ixgbe_configure_msix(dev);
2621
2622         /* initialize transmission unit */
2623         ixgbe_dev_tx_init(dev);
2624
2625         /* This can fail when allocating mbufs for descriptor rings */
2626         err = ixgbe_dev_rx_init(dev);
2627         if (err) {
2628                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2629                 goto error;
2630         }
2631
2632         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2633                 ETH_VLAN_EXTEND_MASK;
2634         err = ixgbe_vlan_offload_config(dev, mask);
2635         if (err) {
2636                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2637                 goto error;
2638         }
2639
2640         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2641                 /* Enable vlan filtering for VMDq */
2642                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2643         }
2644
2645         /* Configure DCB hw */
2646         ixgbe_configure_dcb(dev);
2647
2648         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2649                 err = ixgbe_fdir_configure(dev);
2650                 if (err)
2651                         goto error;
2652         }
2653
2654         /* Restore vf rate limit */
2655         if (vfinfo != NULL) {
2656                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2657                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2658                                 if (vfinfo[vf].tx_rate[idx] != 0)
2659                                         ixgbe_set_vf_rate_limit(
2660                                                 dev, vf,
2661                                                 vfinfo[vf].tx_rate[idx],
2662                                                 1 << idx);
2663         }
2664
2665         ixgbe_restore_statistics_mapping(dev);
2666
2667         err = ixgbe_dev_rxtx_start(dev);
2668         if (err < 0) {
2669                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2670                 goto error;
2671         }
2672
2673         /* Skip link setup if loopback mode is enabled. */
2674         if (dev->data->dev_conf.lpbk_mode != 0) {
2675                 err = ixgbe_check_supported_loopback_mode(dev);
2676                 if (err < 0) {
2677                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2678                         goto error;
2679                 } else {
2680                         goto skip_link_setup;
2681                 }
2682         }
2683
2684         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2685                 err = hw->mac.ops.setup_sfp(hw);
2686                 if (err)
2687                         goto error;
2688         }
2689
2690         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2691                 /* Turn on the copper */
2692                 ixgbe_set_phy_power(hw, true);
2693         } else {
2694                 /* Turn on the laser */
2695                 ixgbe_enable_tx_laser(hw);
2696         }
2697
2698         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2699         if (err)
2700                 goto error;
2701         dev->data->dev_link.link_status = link_up;
2702
2703         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2704         if (err)
2705                 goto error;
2706
2707         switch (hw->mac.type) {
2708         case ixgbe_mac_X550:
2709         case ixgbe_mac_X550EM_x:
2710         case ixgbe_mac_X550EM_a:
2711                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2712                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2713                         ETH_LINK_SPEED_10G;
2714                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2715                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2716                         allowed_speeds = ETH_LINK_SPEED_10M |
2717                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2718                 break;
2719         default:
2720                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2721                         ETH_LINK_SPEED_10G;
2722         }
2723
2724         link_speeds = &dev->data->dev_conf.link_speeds;
2725
2726         /* Ignore autoneg flag bit and check the validity of
2727          * link_speed
2728          */
2729         if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2730                 PMD_INIT_LOG(ERR, "Invalid link setting");
2731                 goto error;
2732         }
2733
2734         speed = 0x0;
2735         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2736                 switch (hw->mac.type) {
2737                 case ixgbe_mac_82598EB:
2738                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2739                         break;
2740                 case ixgbe_mac_82599EB:
2741                 case ixgbe_mac_X540:
2742                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2743                         break;
2744                 case ixgbe_mac_X550:
2745                 case ixgbe_mac_X550EM_x:
2746                 case ixgbe_mac_X550EM_a:
2747                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2748                         break;
2749                 default:
2750                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2751                 }
2752         } else {
2753                 if (*link_speeds & ETH_LINK_SPEED_10G)
2754                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2755                 if (*link_speeds & ETH_LINK_SPEED_5G)
2756                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2757                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2758                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2759                 if (*link_speeds & ETH_LINK_SPEED_1G)
2760                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2761                 if (*link_speeds & ETH_LINK_SPEED_100M)
2762                         speed |= IXGBE_LINK_SPEED_100_FULL;
2763                 if (*link_speeds & ETH_LINK_SPEED_10M)
2764                         speed |= IXGBE_LINK_SPEED_10_FULL;
2765         }
2766
2767         err = ixgbe_setup_link(hw, speed, link_up);
2768         if (err)
2769                 goto error;
2770
2771 skip_link_setup:
2772
2773         if (rte_intr_allow_others(intr_handle)) {
2774                 /* check if lsc interrupt is enabled */
2775                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2776                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2777                 else
2778                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2779                 ixgbe_dev_macsec_interrupt_setup(dev);
2780         } else {
2781                 rte_intr_callback_unregister(intr_handle,
2782                                              ixgbe_dev_interrupt_handler, dev);
2783                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2784                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2785                                      " no intr multiplex");
2786         }
2787
2788         /* check if rxq interrupt is enabled */
2789         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2790             rte_intr_dp_is_en(intr_handle))
2791                 ixgbe_dev_rxq_interrupt_setup(dev);
2792
2793         /* enable uio/vfio intr/eventfd mapping */
2794         rte_intr_enable(intr_handle);
2795
2796         /* resume enabled intr since hw reset */
2797         ixgbe_enable_intr(dev);
2798         ixgbe_l2_tunnel_conf(dev);
2799         ixgbe_filter_restore(dev);
2800
2801         if (tm_conf->root && !tm_conf->committed)
2802                 PMD_DRV_LOG(WARNING,
2803                             "please call hierarchy_commit() "
2804                             "before starting the port");
2805
2806         /* wait for the controller to acquire link */
2807         err = ixgbe_wait_for_link_up(hw);
2808         if (err)
2809                 goto error;
2810
2811         /*
2812          * Update link status right before return, because it may
2813          * start link configuration process in a separate thread.
2814          */
2815         ixgbe_dev_link_update(dev, 0);
2816
2817         /* setup the macsec setting register */
2818         if (macsec_setting->offload_en)
2819                 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2820
2821         return 0;
2822
2823 error:
2824         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2825         ixgbe_dev_clear_queues(dev);
2826         return -EIO;
2827 }
2828
2829 /*
2830  * Stop device: disable rx and tx functions to allow for reconfiguring.
2831  */
2832 static void
2833 ixgbe_dev_stop(struct rte_eth_dev *dev)
2834 {
2835         struct rte_eth_link link;
2836         struct ixgbe_adapter *adapter = dev->data->dev_private;
2837         struct ixgbe_hw *hw =
2838                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2839         struct ixgbe_vf_info *vfinfo =
2840                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2841         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2842         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2843         int vf;
2844         struct ixgbe_tm_conf *tm_conf =
2845                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2846
2847         if (hw->adapter_stopped)
2848                 return;
2849
2850         PMD_INIT_FUNC_TRACE();
2851
2852         ixgbe_dev_cancel_link_thread(dev);
2853
2854         /* disable interrupts */
2855         ixgbe_disable_intr(hw);
2856
2857         /* reset the NIC */
2858         ixgbe_pf_reset_hw(hw);
2859         hw->adapter_stopped = 0;
2860
2861         /* stop adapter */
2862         ixgbe_stop_adapter(hw);
2863
2864         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2865                 vfinfo[vf].clear_to_send = false;
2866
2867         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2868                 /* Turn off the copper */
2869                 ixgbe_set_phy_power(hw, false);
2870         } else {
2871                 /* Turn off the laser */
2872                 ixgbe_disable_tx_laser(hw);
2873         }
2874
2875         ixgbe_dev_clear_queues(dev);
2876
2877         /* Clear stored conf */
2878         dev->data->scattered_rx = 0;
2879         dev->data->lro = 0;
2880
2881         /* Clear recorded link status */
2882         memset(&link, 0, sizeof(link));
2883         rte_eth_linkstatus_set(dev, &link);
2884
2885         if (!rte_intr_allow_others(intr_handle))
2886                 /* resume to the default handler */
2887                 rte_intr_callback_register(intr_handle,
2888                                            ixgbe_dev_interrupt_handler,
2889                                            (void *)dev);
2890
2891         /* Clean datapath event and queue/vec mapping */
2892         rte_intr_efd_disable(intr_handle);
2893         if (intr_handle->intr_vec != NULL) {
2894                 rte_free(intr_handle->intr_vec);
2895                 intr_handle->intr_vec = NULL;
2896         }
2897
2898         /* reset hierarchy commit */
2899         tm_conf->committed = false;
2900
2901         adapter->rss_reta_updated = 0;
2902
2903         hw->adapter_stopped = true;
2904 }
2905
2906 /*
2907  * Set device link up: enable tx.
2908  */
2909 static int
2910 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2911 {
2912         struct ixgbe_hw *hw =
2913                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2914         if (hw->mac.type == ixgbe_mac_82599EB) {
2915 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2916                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2917                         /* Not suported in bypass mode */
2918                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2919                                      "by device id 0x%x", hw->device_id);
2920                         return -ENOTSUP;
2921                 }
2922 #endif
2923         }
2924
2925         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2926                 /* Turn on the copper */
2927                 ixgbe_set_phy_power(hw, true);
2928         } else {
2929                 /* Turn on the laser */
2930                 ixgbe_enable_tx_laser(hw);
2931                 ixgbe_dev_link_update(dev, 0);
2932         }
2933
2934         return 0;
2935 }
2936
2937 /*
2938  * Set device link down: disable tx.
2939  */
2940 static int
2941 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2942 {
2943         struct ixgbe_hw *hw =
2944                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2945         if (hw->mac.type == ixgbe_mac_82599EB) {
2946 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2947                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2948                         /* Not suported in bypass mode */
2949                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2950                                      "by device id 0x%x", hw->device_id);
2951                         return -ENOTSUP;
2952                 }
2953 #endif
2954         }
2955
2956         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2957                 /* Turn off the copper */
2958                 ixgbe_set_phy_power(hw, false);
2959         } else {
2960                 /* Turn off the laser */
2961                 ixgbe_disable_tx_laser(hw);
2962                 ixgbe_dev_link_update(dev, 0);
2963         }
2964
2965         return 0;
2966 }
2967
2968 /*
2969  * Reset and stop device.
2970  */
2971 static void
2972 ixgbe_dev_close(struct rte_eth_dev *dev)
2973 {
2974         struct ixgbe_hw *hw =
2975                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2976         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2977         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2978         int retries = 0;
2979         int ret;
2980
2981         PMD_INIT_FUNC_TRACE();
2982
2983         ixgbe_pf_reset_hw(hw);
2984
2985         ixgbe_dev_stop(dev);
2986
2987         ixgbe_dev_free_queues(dev);
2988
2989         ixgbe_disable_pcie_master(hw);
2990
2991         /* reprogram the RAR[0] in case user changed it. */
2992         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2993
2994         dev->dev_ops = NULL;
2995         dev->rx_pkt_burst = NULL;
2996         dev->tx_pkt_burst = NULL;
2997
2998         /* Unlock any pending hardware semaphore */
2999         ixgbe_swfw_lock_reset(hw);
3000
3001         /* disable uio intr before callback unregister */
3002         rte_intr_disable(intr_handle);
3003
3004         do {
3005                 ret = rte_intr_callback_unregister(intr_handle,
3006                                 ixgbe_dev_interrupt_handler, dev);
3007                 if (ret >= 0 || ret == -ENOENT) {
3008                         break;
3009                 } else if (ret != -EAGAIN) {
3010                         PMD_INIT_LOG(ERR,
3011                                 "intr callback unregister failed: %d",
3012                                 ret);
3013                 }
3014                 rte_delay_ms(100);
3015         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3016
3017         /* cancel the delay handler before remove dev */
3018         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3019
3020         /* uninitialize PF if max_vfs not zero */
3021         ixgbe_pf_host_uninit(dev);
3022
3023         /* remove all the fdir filters & hash */
3024         ixgbe_fdir_filter_uninit(dev);
3025
3026         /* remove all the L2 tunnel filters & hash */
3027         ixgbe_l2_tn_filter_uninit(dev);
3028
3029         /* Remove all ntuple filters of the device */
3030         ixgbe_ntuple_filter_uninit(dev);
3031
3032         /* clear all the filters list */
3033         ixgbe_filterlist_flush();
3034
3035         /* Remove all Traffic Manager configuration */
3036         ixgbe_tm_conf_uninit(dev);
3037
3038 #ifdef RTE_LIBRTE_SECURITY
3039         rte_free(dev->security_ctx);
3040 #endif
3041
3042 }
3043
3044 /*
3045  * Reset PF device.
3046  */
3047 static int
3048 ixgbe_dev_reset(struct rte_eth_dev *dev)
3049 {
3050         int ret;
3051
3052         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3053          * its VF to make them align with it. The detailed notification
3054          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3055          * To avoid unexpected behavior in VF, currently reset of PF with
3056          * SR-IOV activation is not supported. It might be supported later.
3057          */
3058         if (dev->data->sriov.active)
3059                 return -ENOTSUP;
3060
3061         ret = eth_ixgbe_dev_uninit(dev);
3062         if (ret)
3063                 return ret;
3064
3065         ret = eth_ixgbe_dev_init(dev, NULL);
3066
3067         return ret;
3068 }
3069
3070 static void
3071 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3072                            struct ixgbe_hw_stats *hw_stats,
3073                            struct ixgbe_macsec_stats *macsec_stats,
3074                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3075                            uint64_t *total_qprc, uint64_t *total_qprdc)
3076 {
3077         uint32_t bprc, lxon, lxoff, total;
3078         uint32_t delta_gprc = 0;
3079         unsigned i;
3080         /* Workaround for RX byte count not including CRC bytes when CRC
3081          * strip is enabled. CRC bytes are removed from counters when crc_strip
3082          * is disabled.
3083          */
3084         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3085                         IXGBE_HLREG0_RXCRCSTRP);
3086
3087         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3088         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3089         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3090         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3091
3092         for (i = 0; i < 8; i++) {
3093                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3094
3095                 /* global total per queue */
3096                 hw_stats->mpc[i] += mp;
3097                 /* Running comprehensive total for stats display */
3098                 *total_missed_rx += hw_stats->mpc[i];
3099                 if (hw->mac.type == ixgbe_mac_82598EB) {
3100                         hw_stats->rnbc[i] +=
3101                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3102                         hw_stats->pxonrxc[i] +=
3103                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3104                         hw_stats->pxoffrxc[i] +=
3105                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3106                 } else {
3107                         hw_stats->pxonrxc[i] +=
3108                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3109                         hw_stats->pxoffrxc[i] +=
3110                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3111                         hw_stats->pxon2offc[i] +=
3112                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3113                 }
3114                 hw_stats->pxontxc[i] +=
3115                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3116                 hw_stats->pxofftxc[i] +=
3117                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3118         }
3119         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3120                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3121                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3122                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3123
3124                 delta_gprc += delta_qprc;
3125
3126                 hw_stats->qprc[i] += delta_qprc;
3127                 hw_stats->qptc[i] += delta_qptc;
3128
3129                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3130                 hw_stats->qbrc[i] +=
3131                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3132                 if (crc_strip == 0)
3133                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3134
3135                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3136                 hw_stats->qbtc[i] +=
3137                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3138
3139                 hw_stats->qprdc[i] += delta_qprdc;
3140                 *total_qprdc += hw_stats->qprdc[i];
3141
3142                 *total_qprc += hw_stats->qprc[i];
3143                 *total_qbrc += hw_stats->qbrc[i];
3144         }
3145         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3146         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3147         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3148
3149         /*
3150          * An errata states that gprc actually counts good + missed packets:
3151          * Workaround to set gprc to summated queue packet receives
3152          */
3153         hw_stats->gprc = *total_qprc;
3154
3155         if (hw->mac.type != ixgbe_mac_82598EB) {
3156                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3157                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3158                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3159                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3160                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3161                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3162                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3163                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3164         } else {
3165                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3166                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3167                 /* 82598 only has a counter in the high register */
3168                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3169                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3170                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3171         }
3172         uint64_t old_tpr = hw_stats->tpr;
3173
3174         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3175         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3176
3177         if (crc_strip == 0)
3178                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3179
3180         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3181         hw_stats->gptc += delta_gptc;
3182         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3183         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3184
3185         /*
3186          * Workaround: mprc hardware is incorrectly counting
3187          * broadcasts, so for now we subtract those.
3188          */
3189         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3190         hw_stats->bprc += bprc;
3191         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3192         if (hw->mac.type == ixgbe_mac_82598EB)
3193                 hw_stats->mprc -= bprc;
3194
3195         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3196         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3197         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3198         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3199         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3200         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3201
3202         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3203         hw_stats->lxontxc += lxon;
3204         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3205         hw_stats->lxofftxc += lxoff;
3206         total = lxon + lxoff;
3207
3208         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3209         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3210         hw_stats->gptc -= total;
3211         hw_stats->mptc -= total;
3212         hw_stats->ptc64 -= total;
3213         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3214
3215         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3216         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3217         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3218         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3219         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3220         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3221         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3222         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3223         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3224         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3225         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3226         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3227         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3228         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3229         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3230         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3231         /* Only read FCOE on 82599 */
3232         if (hw->mac.type != ixgbe_mac_82598EB) {
3233                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3234                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3235                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3236                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3237                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3238         }
3239
3240         /* Flow Director Stats registers */
3241         if (hw->mac.type != ixgbe_mac_82598EB) {
3242                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3243                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3244                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3245                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3246                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3247                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3248                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3249                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3250                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3251                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3252         }
3253         /* MACsec Stats registers */
3254         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3255         macsec_stats->out_pkts_encrypted +=
3256                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3257         macsec_stats->out_pkts_protected +=
3258                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3259         macsec_stats->out_octets_encrypted +=
3260                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3261         macsec_stats->out_octets_protected +=
3262                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3263         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3264         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3265         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3266         macsec_stats->in_pkts_unknownsci +=
3267                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3268         macsec_stats->in_octets_decrypted +=
3269                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3270         macsec_stats->in_octets_validated +=
3271                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3272         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3273         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3274         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3275         for (i = 0; i < 2; i++) {
3276                 macsec_stats->in_pkts_ok +=
3277                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3278                 macsec_stats->in_pkts_invalid +=
3279                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3280                 macsec_stats->in_pkts_notvalid +=
3281                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3282         }
3283         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3284         macsec_stats->in_pkts_notusingsa +=
3285                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3286 }
3287
3288 /*
3289  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3290  */
3291 static int
3292 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3293 {
3294         struct ixgbe_hw *hw =
3295                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3296         struct ixgbe_hw_stats *hw_stats =
3297                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3298         struct ixgbe_macsec_stats *macsec_stats =
3299                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3300                                 dev->data->dev_private);
3301         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3302         unsigned i;
3303
3304         total_missed_rx = 0;
3305         total_qbrc = 0;
3306         total_qprc = 0;
3307         total_qprdc = 0;
3308
3309         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3310                         &total_qbrc, &total_qprc, &total_qprdc);
3311
3312         if (stats == NULL)
3313                 return -EINVAL;
3314
3315         /* Fill out the rte_eth_stats statistics structure */
3316         stats->ipackets = total_qprc;
3317         stats->ibytes = total_qbrc;
3318         stats->opackets = hw_stats->gptc;
3319         stats->obytes = hw_stats->gotc;
3320
3321         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3322                 stats->q_ipackets[i] = hw_stats->qprc[i];
3323                 stats->q_opackets[i] = hw_stats->qptc[i];
3324                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3325                 stats->q_obytes[i] = hw_stats->qbtc[i];
3326                 stats->q_errors[i] = hw_stats->qprdc[i];
3327         }
3328
3329         /* Rx Errors */
3330         stats->imissed  = total_missed_rx;
3331         stats->ierrors  = hw_stats->crcerrs +
3332                           hw_stats->mspdc +
3333                           hw_stats->rlec +
3334                           hw_stats->ruc +
3335                           hw_stats->roc +
3336                           hw_stats->illerrc +
3337                           hw_stats->errbc +
3338                           hw_stats->rfc +
3339                           hw_stats->fccrc +
3340                           hw_stats->fclast;
3341
3342         /* Tx Errors */
3343         stats->oerrors  = 0;
3344         return 0;
3345 }
3346
3347 static int
3348 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3349 {
3350         struct ixgbe_hw_stats *stats =
3351                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3352
3353         /* HW registers are cleared on read */
3354         ixgbe_dev_stats_get(dev, NULL);
3355
3356         /* Reset software totals */
3357         memset(stats, 0, sizeof(*stats));
3358
3359         return 0;
3360 }
3361
3362 /* This function calculates the number of xstats based on the current config */
3363 static unsigned
3364 ixgbe_xstats_calc_num(void) {
3365         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3366                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3367                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3368 }
3369
3370 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3371         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3372 {
3373         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3374         unsigned stat, i, count;
3375
3376         if (xstats_names != NULL) {
3377                 count = 0;
3378
3379                 /* Note: limit >= cnt_stats checked upstream
3380                  * in rte_eth_xstats_names()
3381                  */
3382
3383                 /* Extended stats from ixgbe_hw_stats */
3384                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3385                         strlcpy(xstats_names[count].name,
3386                                 rte_ixgbe_stats_strings[i].name,
3387                                 sizeof(xstats_names[count].name));
3388                         count++;
3389                 }
3390
3391                 /* MACsec Stats */
3392                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3393                         strlcpy(xstats_names[count].name,
3394                                 rte_ixgbe_macsec_strings[i].name,
3395                                 sizeof(xstats_names[count].name));
3396                         count++;
3397                 }
3398
3399                 /* RX Priority Stats */
3400                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3401                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3402                                 snprintf(xstats_names[count].name,
3403                                         sizeof(xstats_names[count].name),
3404                                         "rx_priority%u_%s", i,
3405                                         rte_ixgbe_rxq_strings[stat].name);
3406                                 count++;
3407                         }
3408                 }
3409
3410                 /* TX Priority Stats */
3411                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3412                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3413                                 snprintf(xstats_names[count].name,
3414                                         sizeof(xstats_names[count].name),
3415                                         "tx_priority%u_%s", i,
3416                                         rte_ixgbe_txq_strings[stat].name);
3417                                 count++;
3418                         }
3419                 }
3420         }
3421         return cnt_stats;
3422 }
3423
3424 static int ixgbe_dev_xstats_get_names_by_id(
3425         struct rte_eth_dev *dev,
3426         struct rte_eth_xstat_name *xstats_names,
3427         const uint64_t *ids,
3428         unsigned int limit)
3429 {
3430         if (!ids) {
3431                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3432                 unsigned int stat, i, count;
3433
3434                 if (xstats_names != NULL) {
3435                         count = 0;
3436
3437                         /* Note: limit >= cnt_stats checked upstream
3438                          * in rte_eth_xstats_names()
3439                          */
3440
3441                         /* Extended stats from ixgbe_hw_stats */
3442                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3443                                 strlcpy(xstats_names[count].name,
3444                                         rte_ixgbe_stats_strings[i].name,
3445                                         sizeof(xstats_names[count].name));
3446                                 count++;
3447                         }
3448
3449                         /* MACsec Stats */
3450                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3451                                 strlcpy(xstats_names[count].name,
3452                                         rte_ixgbe_macsec_strings[i].name,
3453                                         sizeof(xstats_names[count].name));
3454                                 count++;
3455                         }
3456
3457                         /* RX Priority Stats */
3458                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3459                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3460                                         snprintf(xstats_names[count].name,
3461                                             sizeof(xstats_names[count].name),
3462                                             "rx_priority%u_%s", i,
3463                                             rte_ixgbe_rxq_strings[stat].name);
3464                                         count++;
3465                                 }
3466                         }
3467
3468                         /* TX Priority Stats */
3469                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3470                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3471                                         snprintf(xstats_names[count].name,
3472                                             sizeof(xstats_names[count].name),
3473                                             "tx_priority%u_%s", i,
3474                                             rte_ixgbe_txq_strings[stat].name);
3475                                         count++;
3476                                 }
3477                         }
3478                 }
3479                 return cnt_stats;
3480         }
3481
3482         uint16_t i;
3483         uint16_t size = ixgbe_xstats_calc_num();
3484         struct rte_eth_xstat_name xstats_names_copy[size];
3485
3486         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3487                         size);
3488
3489         for (i = 0; i < limit; i++) {
3490                 if (ids[i] >= size) {
3491                         PMD_INIT_LOG(ERR, "id value isn't valid");
3492                         return -1;
3493                 }
3494                 strcpy(xstats_names[i].name,
3495                                 xstats_names_copy[ids[i]].name);
3496         }
3497         return limit;
3498 }
3499
3500 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3501         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3502 {
3503         unsigned i;
3504
3505         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3506                 return -ENOMEM;
3507
3508         if (xstats_names != NULL)
3509                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3510                         strlcpy(xstats_names[i].name,
3511                                 rte_ixgbevf_stats_strings[i].name,
3512                                 sizeof(xstats_names[i].name));
3513         return IXGBEVF_NB_XSTATS;
3514 }
3515
3516 static int
3517 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3518                                          unsigned n)
3519 {
3520         struct ixgbe_hw *hw =
3521                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3522         struct ixgbe_hw_stats *hw_stats =
3523                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3524         struct ixgbe_macsec_stats *macsec_stats =
3525                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3526                                 dev->data->dev_private);
3527         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3528         unsigned i, stat, count = 0;
3529
3530         count = ixgbe_xstats_calc_num();
3531
3532         if (n < count)
3533                 return count;
3534
3535         total_missed_rx = 0;
3536         total_qbrc = 0;
3537         total_qprc = 0;
3538         total_qprdc = 0;
3539
3540         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3541                         &total_qbrc, &total_qprc, &total_qprdc);
3542
3543         /* If this is a reset xstats is NULL, and we have cleared the
3544          * registers by reading them.
3545          */
3546         if (!xstats)
3547                 return 0;
3548
3549         /* Extended stats from ixgbe_hw_stats */
3550         count = 0;
3551         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3552                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3553                                 rte_ixgbe_stats_strings[i].offset);
3554                 xstats[count].id = count;
3555                 count++;
3556         }
3557
3558         /* MACsec Stats */
3559         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3560                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3561                                 rte_ixgbe_macsec_strings[i].offset);
3562                 xstats[count].id = count;
3563                 count++;
3564         }
3565
3566         /* RX Priority Stats */
3567         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3568                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3569                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3570                                         rte_ixgbe_rxq_strings[stat].offset +
3571                                         (sizeof(uint64_t) * i));
3572                         xstats[count].id = count;
3573                         count++;
3574                 }
3575         }
3576
3577         /* TX Priority Stats */
3578         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3579                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3580                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3581                                         rte_ixgbe_txq_strings[stat].offset +
3582                                         (sizeof(uint64_t) * i));
3583                         xstats[count].id = count;
3584                         count++;
3585                 }
3586         }
3587         return count;
3588 }
3589
3590 static int
3591 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3592                 uint64_t *values, unsigned int n)
3593 {
3594         if (!ids) {
3595                 struct ixgbe_hw *hw =
3596                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3597                 struct ixgbe_hw_stats *hw_stats =
3598                                 IXGBE_DEV_PRIVATE_TO_STATS(
3599                                                 dev->data->dev_private);
3600                 struct ixgbe_macsec_stats *macsec_stats =
3601                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3602                                         dev->data->dev_private);
3603                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3604                 unsigned int i, stat, count = 0;
3605
3606                 count = ixgbe_xstats_calc_num();
3607
3608                 if (!ids && n < count)
3609                         return count;
3610
3611                 total_missed_rx = 0;
3612                 total_qbrc = 0;
3613                 total_qprc = 0;
3614                 total_qprdc = 0;
3615
3616                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3617                                 &total_missed_rx, &total_qbrc, &total_qprc,
3618                                 &total_qprdc);
3619
3620                 /* If this is a reset xstats is NULL, and we have cleared the
3621                  * registers by reading them.
3622                  */
3623                 if (!ids && !values)
3624                         return 0;
3625
3626                 /* Extended stats from ixgbe_hw_stats */
3627                 count = 0;
3628                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3629                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3630                                         rte_ixgbe_stats_strings[i].offset);
3631                         count++;
3632                 }
3633
3634                 /* MACsec Stats */
3635                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3636                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3637                                         rte_ixgbe_macsec_strings[i].offset);
3638                         count++;
3639                 }
3640
3641                 /* RX Priority Stats */
3642                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3643                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3644                                 values[count] =
3645                                         *(uint64_t *)(((char *)hw_stats) +
3646                                         rte_ixgbe_rxq_strings[stat].offset +
3647                                         (sizeof(uint64_t) * i));
3648                                 count++;
3649                         }
3650                 }
3651
3652                 /* TX Priority Stats */
3653                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3654                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3655                                 values[count] =
3656                                         *(uint64_t *)(((char *)hw_stats) +
3657                                         rte_ixgbe_txq_strings[stat].offset +
3658                                         (sizeof(uint64_t) * i));
3659                                 count++;
3660                         }
3661                 }
3662                 return count;
3663         }
3664
3665         uint16_t i;
3666         uint16_t size = ixgbe_xstats_calc_num();
3667         uint64_t values_copy[size];
3668
3669         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3670
3671         for (i = 0; i < n; i++) {
3672                 if (ids[i] >= size) {
3673                         PMD_INIT_LOG(ERR, "id value isn't valid");
3674                         return -1;
3675                 }
3676                 values[i] = values_copy[ids[i]];
3677         }
3678         return n;
3679 }
3680
3681 static int
3682 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3683 {
3684         struct ixgbe_hw_stats *stats =
3685                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3686         struct ixgbe_macsec_stats *macsec_stats =
3687                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3688                                 dev->data->dev_private);
3689
3690         unsigned count = ixgbe_xstats_calc_num();
3691
3692         /* HW registers are cleared on read */
3693         ixgbe_dev_xstats_get(dev, NULL, count);
3694
3695         /* Reset software totals */
3696         memset(stats, 0, sizeof(*stats));
3697         memset(macsec_stats, 0, sizeof(*macsec_stats));
3698
3699         return 0;
3700 }
3701
3702 static void
3703 ixgbevf_update_stats(struct rte_eth_dev *dev)
3704 {
3705         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3706         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3707                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3708
3709         /* Good Rx packet, include VF loopback */
3710         UPDATE_VF_STAT(IXGBE_VFGPRC,
3711             hw_stats->last_vfgprc, hw_stats->vfgprc);
3712
3713         /* Good Rx octets, include VF loopback */
3714         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3715             hw_stats->last_vfgorc, hw_stats->vfgorc);
3716
3717         /* Good Tx packet, include VF loopback */
3718         UPDATE_VF_STAT(IXGBE_VFGPTC,
3719             hw_stats->last_vfgptc, hw_stats->vfgptc);
3720
3721         /* Good Tx octets, include VF loopback */
3722         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3723             hw_stats->last_vfgotc, hw_stats->vfgotc);
3724
3725         /* Rx Multicst Packet */
3726         UPDATE_VF_STAT(IXGBE_VFMPRC,
3727             hw_stats->last_vfmprc, hw_stats->vfmprc);
3728 }
3729
3730 static int
3731 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3732                        unsigned n)
3733 {
3734         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3735                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3736         unsigned i;
3737
3738         if (n < IXGBEVF_NB_XSTATS)
3739                 return IXGBEVF_NB_XSTATS;
3740
3741         ixgbevf_update_stats(dev);
3742
3743         if (!xstats)
3744                 return 0;
3745
3746         /* Extended stats */
3747         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3748                 xstats[i].id = i;
3749                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3750                         rte_ixgbevf_stats_strings[i].offset);
3751         }
3752
3753         return IXGBEVF_NB_XSTATS;
3754 }
3755
3756 static int
3757 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3758 {
3759         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3760                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3761
3762         ixgbevf_update_stats(dev);
3763
3764         if (stats == NULL)
3765                 return -EINVAL;
3766
3767         stats->ipackets = hw_stats->vfgprc;
3768         stats->ibytes = hw_stats->vfgorc;
3769         stats->opackets = hw_stats->vfgptc;
3770         stats->obytes = hw_stats->vfgotc;
3771         return 0;
3772 }
3773
3774 static int
3775 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3776 {
3777         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3778                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3779
3780         /* Sync HW register to the last stats */
3781         ixgbevf_dev_stats_get(dev, NULL);
3782
3783         /* reset HW current stats*/
3784         hw_stats->vfgprc = 0;
3785         hw_stats->vfgorc = 0;
3786         hw_stats->vfgptc = 0;
3787         hw_stats->vfgotc = 0;
3788
3789         return 0;
3790 }
3791
3792 static int
3793 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3794 {
3795         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3796         u16 eeprom_verh, eeprom_verl;
3797         u32 etrack_id;
3798         int ret;
3799
3800         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3801         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3802
3803         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3804         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3805
3806         ret += 1; /* add the size of '\0' */
3807         if (fw_size < (u32)ret)
3808                 return ret;
3809         else
3810                 return 0;
3811 }
3812
3813 static int
3814 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3815 {
3816         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3817         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3818         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3819
3820         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3821         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3822         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3823                 /*
3824                  * When DCB/VT is off, maximum number of queues changes,
3825                  * except for 82598EB, which remains constant.
3826                  */
3827                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3828                                 hw->mac.type != ixgbe_mac_82598EB)
3829                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3830         }
3831         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3832         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3833         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3834         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3835         dev_info->max_vfs = pci_dev->max_vfs;
3836         if (hw->mac.type == ixgbe_mac_82598EB)
3837                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3838         else
3839                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3840         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3841         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3842         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3843         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3844         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3845                                      dev_info->rx_queue_offload_capa);
3846         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3847         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3848
3849         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3850                 .rx_thresh = {
3851                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3852                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3853                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3854                 },
3855                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3856                 .rx_drop_en = 0,
3857                 .offloads = 0,
3858         };
3859
3860         dev_info->default_txconf = (struct rte_eth_txconf) {
3861                 .tx_thresh = {
3862                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3863                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3864                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3865                 },
3866                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3867                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3868                 .offloads = 0,
3869         };
3870
3871         dev_info->rx_desc_lim = rx_desc_lim;
3872         dev_info->tx_desc_lim = tx_desc_lim;
3873
3874         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3875         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3876         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3877
3878         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3879         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3880                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3881                 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3882                         ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3883
3884         if (hw->mac.type == ixgbe_mac_X540 ||
3885             hw->mac.type == ixgbe_mac_X540_vf ||
3886             hw->mac.type == ixgbe_mac_X550 ||
3887             hw->mac.type == ixgbe_mac_X550_vf) {
3888                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3889         }
3890         if (hw->mac.type == ixgbe_mac_X550) {
3891                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3892                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3893         }
3894
3895         /* Driver-preferred Rx/Tx parameters */
3896         dev_info->default_rxportconf.burst_size = 32;
3897         dev_info->default_txportconf.burst_size = 32;
3898         dev_info->default_rxportconf.nb_queues = 1;
3899         dev_info->default_txportconf.nb_queues = 1;
3900         dev_info->default_rxportconf.ring_size = 256;
3901         dev_info->default_txportconf.ring_size = 256;
3902
3903         return 0;
3904 }
3905
3906 static const uint32_t *
3907 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3908 {
3909         static const uint32_t ptypes[] = {
3910                 /* For non-vec functions,
3911                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3912                  * for vec functions,
3913                  * refers to _recv_raw_pkts_vec().
3914                  */
3915                 RTE_PTYPE_L2_ETHER,
3916                 RTE_PTYPE_L3_IPV4,
3917                 RTE_PTYPE_L3_IPV4_EXT,
3918                 RTE_PTYPE_L3_IPV6,
3919                 RTE_PTYPE_L3_IPV6_EXT,
3920                 RTE_PTYPE_L4_SCTP,
3921                 RTE_PTYPE_L4_TCP,
3922                 RTE_PTYPE_L4_UDP,
3923                 RTE_PTYPE_TUNNEL_IP,
3924                 RTE_PTYPE_INNER_L3_IPV6,
3925                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3926                 RTE_PTYPE_INNER_L4_TCP,
3927                 RTE_PTYPE_INNER_L4_UDP,
3928                 RTE_PTYPE_UNKNOWN
3929         };
3930
3931         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3932             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3933             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3934             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3935                 return ptypes;
3936
3937 #if defined(RTE_ARCH_X86) || defined(RTE_MACHINE_CPUFLAG_NEON)
3938         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3939             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3940                 return ptypes;
3941 #endif
3942         return NULL;
3943 }
3944
3945 static int
3946 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3947                      struct rte_eth_dev_info *dev_info)
3948 {
3949         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3950         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3951
3952         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3953         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3954         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3955         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3956         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3957         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3958         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3959         dev_info->max_vfs = pci_dev->max_vfs;
3960         if (hw->mac.type == ixgbe_mac_82598EB)
3961                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3962         else
3963                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3964         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3965         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3966                                      dev_info->rx_queue_offload_capa);
3967         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3968         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3969         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3970         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3971         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3972
3973         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3974                 .rx_thresh = {
3975                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3976                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3977                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3978                 },
3979                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3980                 .rx_drop_en = 0,
3981                 .offloads = 0,
3982         };
3983
3984         dev_info->default_txconf = (struct rte_eth_txconf) {
3985                 .tx_thresh = {
3986                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3987                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3988                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3989                 },
3990                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3991                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3992                 .offloads = 0,
3993         };
3994
3995         dev_info->rx_desc_lim = rx_desc_lim;
3996         dev_info->tx_desc_lim = tx_desc_lim;
3997
3998         return 0;
3999 }
4000
4001 static int
4002 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4003                    bool *link_up, int wait_to_complete)
4004 {
4005         struct ixgbe_adapter *adapter = container_of(hw,
4006                                                      struct ixgbe_adapter, hw);
4007         struct ixgbe_mbx_info *mbx = &hw->mbx;
4008         struct ixgbe_mac_info *mac = &hw->mac;
4009         uint32_t links_reg, in_msg;
4010         int ret_val = 0;
4011
4012         /* If we were hit with a reset drop the link */
4013         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4014                 mac->get_link_status = true;
4015
4016         if (!mac->get_link_status)
4017                 goto out;
4018
4019         /* if link status is down no point in checking to see if pf is up */
4020         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4021         if (!(links_reg & IXGBE_LINKS_UP))
4022                 goto out;
4023
4024         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4025          * before the link status is correct
4026          */
4027         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4028                 int i;
4029
4030                 for (i = 0; i < 5; i++) {
4031                         rte_delay_us(100);
4032                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4033
4034                         if (!(links_reg & IXGBE_LINKS_UP))
4035                                 goto out;
4036                 }
4037         }
4038
4039         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4040         case IXGBE_LINKS_SPEED_10G_82599:
4041                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4042                 if (hw->mac.type >= ixgbe_mac_X550) {
4043                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4044                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4045                 }
4046                 break;
4047         case IXGBE_LINKS_SPEED_1G_82599:
4048                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4049                 break;
4050         case IXGBE_LINKS_SPEED_100_82599:
4051                 *speed = IXGBE_LINK_SPEED_100_FULL;
4052                 if (hw->mac.type == ixgbe_mac_X550) {
4053                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4054                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4055                 }
4056                 break;
4057         case IXGBE_LINKS_SPEED_10_X550EM_A:
4058                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4059                 /* Since Reserved in older MAC's */
4060                 if (hw->mac.type >= ixgbe_mac_X550)
4061                         *speed = IXGBE_LINK_SPEED_10_FULL;
4062                 break;
4063         default:
4064                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4065         }
4066
4067         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4068                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4069                         mac->get_link_status = true;
4070                 else
4071                         mac->get_link_status = false;
4072
4073                 goto out;
4074         }
4075
4076         /* if the read failed it could just be a mailbox collision, best wait
4077          * until we are called again and don't report an error
4078          */
4079         if (mbx->ops.read(hw, &in_msg, 1, 0))
4080                 goto out;
4081
4082         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4083                 /* msg is not CTS and is NACK we must have lost CTS status */
4084                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4085                         mac->get_link_status = false;
4086                 goto out;
4087         }
4088
4089         /* the pf is talking, if we timed out in the past we reinit */
4090         if (!mbx->timeout) {
4091                 ret_val = -1;
4092                 goto out;
4093         }
4094
4095         /* if we passed all the tests above then the link is up and we no
4096          * longer need to check for link
4097          */
4098         mac->get_link_status = false;
4099
4100 out:
4101         *link_up = !mac->get_link_status;
4102         return ret_val;
4103 }
4104
4105 static void
4106 ixgbe_dev_cancel_link_thread(struct rte_eth_dev *dev)
4107 {
4108         struct ixgbe_adapter *ad = dev->data->dev_private;
4109         void *retval;
4110
4111         if (rte_atomic32_read(&ad->link_thread_running)) {
4112                 pthread_cancel(ad->link_thread_tid);
4113                 pthread_join(ad->link_thread_tid, &retval);
4114                 rte_atomic32_clear(&ad->link_thread_running);
4115         }
4116 }
4117
4118 static void *
4119 ixgbe_dev_setup_link_thread_handler(void *param)
4120 {
4121         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4122         struct ixgbe_adapter *ad = dev->data->dev_private;
4123         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4124         struct ixgbe_interrupt *intr =
4125                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4126         u32 speed;
4127         bool autoneg = false;
4128
4129         speed = hw->phy.autoneg_advertised;
4130         if (!speed)
4131                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4132
4133         ixgbe_setup_link(hw, speed, true);
4134
4135         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4136         rte_atomic32_clear(&ad->link_thread_running);
4137         return NULL;
4138 }
4139
4140 /*
4141  * In freebsd environment, nic_uio drivers do not support interrupts,
4142  * rte_intr_callback_register() will fail to register interrupts.
4143  * We can not make link status to change from down to up by interrupt
4144  * callback. So we need to wait for the controller to acquire link
4145  * when ports start.
4146  * It returns 0 on link up.
4147  */
4148 static int
4149 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4150 {
4151 #ifdef RTE_EXEC_ENV_FREEBSD
4152         int err, i;
4153         bool link_up = false;
4154         uint32_t speed = 0;
4155         const int nb_iter = 25;
4156
4157         for (i = 0; i < nb_iter; i++) {
4158                 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4159                 if (err)
4160                         return err;
4161                 if (link_up)
4162                         return 0;
4163                 msec_delay(200);
4164         }
4165
4166         return 0;
4167 #else
4168         RTE_SET_USED(hw);
4169         return 0;
4170 #endif
4171 }
4172
4173 /* return 0 means link status changed, -1 means not changed */
4174 int
4175 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4176                             int wait_to_complete, int vf)
4177 {
4178         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4179         struct ixgbe_adapter *ad = dev->data->dev_private;
4180         struct rte_eth_link link;
4181         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4182         struct ixgbe_interrupt *intr =
4183                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4184         bool link_up;
4185         int diag;
4186         int wait = 1;
4187         u32 esdp_reg;
4188
4189         memset(&link, 0, sizeof(link));
4190         link.link_status = ETH_LINK_DOWN;
4191         link.link_speed = ETH_SPEED_NUM_NONE;
4192         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4193         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4194                         ETH_LINK_SPEED_FIXED);
4195
4196         hw->mac.get_link_status = true;
4197
4198         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4199                 return rte_eth_linkstatus_set(dev, &link);
4200
4201         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4202         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4203                 wait = 0;
4204
4205         if (vf)
4206                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4207         else
4208                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4209
4210         if (diag != 0) {
4211                 link.link_speed = ETH_SPEED_NUM_100M;
4212                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4213                 return rte_eth_linkstatus_set(dev, &link);
4214         }
4215
4216         if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4217                 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4218                 if ((esdp_reg & IXGBE_ESDP_SDP3))
4219                         link_up = 0;
4220         }
4221
4222         if (link_up == 0) {
4223                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4224                         intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4225                         if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4226                                 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4227                                         "ixgbe-link-handler",
4228                                         NULL,
4229                                         ixgbe_dev_setup_link_thread_handler,
4230                                         dev) < 0) {
4231                                         PMD_DRV_LOG(ERR,
4232                                                 "Create link thread failed!");
4233                                         rte_atomic32_clear(&ad->link_thread_running);
4234                                 }
4235                         } else {
4236                                 PMD_DRV_LOG(ERR,
4237                                         "Other link thread is running now!");
4238                         }
4239                 }
4240                 return rte_eth_linkstatus_set(dev, &link);
4241         }
4242
4243         link.link_status = ETH_LINK_UP;
4244         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4245
4246         switch (link_speed) {
4247         default:
4248         case IXGBE_LINK_SPEED_UNKNOWN:
4249                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4250                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4251                         link.link_speed = ETH_SPEED_NUM_10M;
4252                 else
4253                         link.link_speed = ETH_SPEED_NUM_100M;
4254                 break;
4255
4256         case IXGBE_LINK_SPEED_100_FULL:
4257                 link.link_speed = ETH_SPEED_NUM_100M;
4258                 break;
4259
4260         case IXGBE_LINK_SPEED_1GB_FULL:
4261                 link.link_speed = ETH_SPEED_NUM_1G;
4262                 break;
4263
4264         case IXGBE_LINK_SPEED_2_5GB_FULL:
4265                 link.link_speed = ETH_SPEED_NUM_2_5G;
4266                 break;
4267
4268         case IXGBE_LINK_SPEED_5GB_FULL:
4269                 link.link_speed = ETH_SPEED_NUM_5G;
4270                 break;
4271
4272         case IXGBE_LINK_SPEED_10GB_FULL:
4273                 link.link_speed = ETH_SPEED_NUM_10G;
4274                 break;
4275         }
4276
4277         return rte_eth_linkstatus_set(dev, &link);
4278 }
4279
4280 static int
4281 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4282 {
4283         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4284 }
4285
4286 static int
4287 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4288 {
4289         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4290 }
4291
4292 static int
4293 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4294 {
4295         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4296         uint32_t fctrl;
4297
4298         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4299         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4300         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4301
4302         return 0;
4303 }
4304
4305 static int
4306 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4307 {
4308         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4309         uint32_t fctrl;
4310
4311         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4312         fctrl &= (~IXGBE_FCTRL_UPE);
4313         if (dev->data->all_multicast == 1)
4314                 fctrl |= IXGBE_FCTRL_MPE;
4315         else
4316                 fctrl &= (~IXGBE_FCTRL_MPE);
4317         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4318
4319         return 0;
4320 }
4321
4322 static int
4323 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4324 {
4325         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4326         uint32_t fctrl;
4327
4328         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4329         fctrl |= IXGBE_FCTRL_MPE;
4330         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4331
4332         return 0;
4333 }
4334
4335 static int
4336 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4337 {
4338         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4339         uint32_t fctrl;
4340
4341         if (dev->data->promiscuous == 1)
4342                 return 0; /* must remain in all_multicast mode */
4343
4344         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4345         fctrl &= (~IXGBE_FCTRL_MPE);
4346         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4347
4348         return 0;
4349 }
4350
4351 /**
4352  * It clears the interrupt causes and enables the interrupt.
4353  * It will be called once only during nic initialized.
4354  *
4355  * @param dev
4356  *  Pointer to struct rte_eth_dev.
4357  * @param on
4358  *  Enable or Disable.
4359  *
4360  * @return
4361  *  - On success, zero.
4362  *  - On failure, a negative value.
4363  */
4364 static int
4365 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4366 {
4367         struct ixgbe_interrupt *intr =
4368                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4369
4370         ixgbe_dev_link_status_print(dev);
4371         if (on)
4372                 intr->mask |= IXGBE_EICR_LSC;
4373         else
4374                 intr->mask &= ~IXGBE_EICR_LSC;
4375
4376         return 0;
4377 }
4378
4379 /**
4380  * It clears the interrupt causes and enables the interrupt.
4381  * It will be called once only during nic initialized.
4382  *
4383  * @param dev
4384  *  Pointer to struct rte_eth_dev.
4385  *
4386  * @return
4387  *  - On success, zero.
4388  *  - On failure, a negative value.
4389  */
4390 static int
4391 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4392 {
4393         struct ixgbe_interrupt *intr =
4394                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4395
4396         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4397
4398         return 0;
4399 }
4400
4401 /**
4402  * It clears the interrupt causes and enables the interrupt.
4403  * It will be called once only during nic initialized.
4404  *
4405  * @param dev
4406  *  Pointer to struct rte_eth_dev.
4407  *
4408  * @return
4409  *  - On success, zero.
4410  *  - On failure, a negative value.
4411  */
4412 static int
4413 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4414 {
4415         struct ixgbe_interrupt *intr =
4416                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4417
4418         intr->mask |= IXGBE_EICR_LINKSEC;
4419
4420         return 0;
4421 }
4422
4423 /*
4424  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4425  *
4426  * @param dev
4427  *  Pointer to struct rte_eth_dev.
4428  *
4429  * @return
4430  *  - On success, zero.
4431  *  - On failure, a negative value.
4432  */
4433 static int
4434 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4435 {
4436         uint32_t eicr;
4437         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4438         struct ixgbe_interrupt *intr =
4439                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4440
4441         /* clear all cause mask */
4442         ixgbe_disable_intr(hw);
4443
4444         /* read-on-clear nic registers here */
4445         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4446         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4447
4448         intr->flags = 0;
4449
4450         /* set flag for async link update */
4451         if (eicr & IXGBE_EICR_LSC)
4452                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4453
4454         if (eicr & IXGBE_EICR_MAILBOX)
4455                 intr->flags |= IXGBE_FLAG_MAILBOX;
4456
4457         if (eicr & IXGBE_EICR_LINKSEC)
4458                 intr->flags |= IXGBE_FLAG_MACSEC;
4459
4460         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4461             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4462             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4463                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4464
4465         return 0;
4466 }
4467
4468 /**
4469  * It gets and then prints the link status.
4470  *
4471  * @param dev
4472  *  Pointer to struct rte_eth_dev.
4473  *
4474  * @return
4475  *  - On success, zero.
4476  *  - On failure, a negative value.
4477  */
4478 static void
4479 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4480 {
4481         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4482         struct rte_eth_link link;
4483
4484         rte_eth_linkstatus_get(dev, &link);
4485
4486         if (link.link_status) {
4487                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4488                                         (int)(dev->data->port_id),
4489                                         (unsigned)link.link_speed,
4490                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4491                                         "full-duplex" : "half-duplex");
4492         } else {
4493                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4494                                 (int)(dev->data->port_id));
4495         }
4496         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4497                                 pci_dev->addr.domain,
4498                                 pci_dev->addr.bus,
4499                                 pci_dev->addr.devid,
4500                                 pci_dev->addr.function);
4501 }
4502
4503 /*
4504  * It executes link_update after knowing an interrupt occurred.
4505  *
4506  * @param dev
4507  *  Pointer to struct rte_eth_dev.
4508  *
4509  * @return
4510  *  - On success, zero.
4511  *  - On failure, a negative value.
4512  */
4513 static int
4514 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4515 {
4516         struct ixgbe_interrupt *intr =
4517                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4518         int64_t timeout;
4519         struct ixgbe_hw *hw =
4520                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4521
4522         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4523
4524         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4525                 ixgbe_pf_mbx_process(dev);
4526                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4527         }
4528
4529         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4530                 ixgbe_handle_lasi(hw);
4531                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4532         }
4533
4534         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4535                 struct rte_eth_link link;
4536
4537                 /* get the link status before link update, for predicting later */
4538                 rte_eth_linkstatus_get(dev, &link);
4539
4540                 ixgbe_dev_link_update(dev, 0);
4541
4542                 /* likely to up */
4543                 if (!link.link_status)
4544                         /* handle it 1 sec later, wait it being stable */
4545                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4546                 /* likely to down */
4547                 else
4548                         /* handle it 4 sec later, wait it being stable */
4549                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4550
4551                 ixgbe_dev_link_status_print(dev);
4552                 if (rte_eal_alarm_set(timeout * 1000,
4553                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4554                         PMD_DRV_LOG(ERR, "Error setting alarm");
4555                 else {
4556                         /* remember original mask */
4557                         intr->mask_original = intr->mask;
4558                         /* only disable lsc interrupt */
4559                         intr->mask &= ~IXGBE_EIMS_LSC;
4560                 }
4561         }
4562
4563         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4564         ixgbe_enable_intr(dev);
4565
4566         return 0;
4567 }
4568
4569 /**
4570  * Interrupt handler which shall be registered for alarm callback for delayed
4571  * handling specific interrupt to wait for the stable nic state. As the
4572  * NIC interrupt state is not stable for ixgbe after link is just down,
4573  * it needs to wait 4 seconds to get the stable status.
4574  *
4575  * @param handle
4576  *  Pointer to interrupt handle.
4577  * @param param
4578  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4579  *
4580  * @return
4581  *  void
4582  */
4583 static void
4584 ixgbe_dev_interrupt_delayed_handler(void *param)
4585 {
4586         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4587         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4588         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4589         struct ixgbe_interrupt *intr =
4590                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4591         struct ixgbe_hw *hw =
4592                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4593         uint32_t eicr;
4594
4595         ixgbe_disable_intr(hw);
4596
4597         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4598         if (eicr & IXGBE_EICR_MAILBOX)
4599                 ixgbe_pf_mbx_process(dev);
4600
4601         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4602                 ixgbe_handle_lasi(hw);
4603                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4604         }
4605
4606         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4607                 ixgbe_dev_link_update(dev, 0);
4608                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4609                 ixgbe_dev_link_status_print(dev);
4610                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4611                                               NULL);
4612         }
4613
4614         if (intr->flags & IXGBE_FLAG_MACSEC) {
4615                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4616                                               NULL);
4617                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4618         }
4619
4620         /* restore original mask */
4621         intr->mask = intr->mask_original;
4622         intr->mask_original = 0;
4623
4624         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4625         ixgbe_enable_intr(dev);
4626         rte_intr_ack(intr_handle);
4627 }
4628
4629 /**
4630  * Interrupt handler triggered by NIC  for handling
4631  * specific interrupt.
4632  *
4633  * @param handle
4634  *  Pointer to interrupt handle.
4635  * @param param
4636  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4637  *
4638  * @return
4639  *  void
4640  */
4641 static void
4642 ixgbe_dev_interrupt_handler(void *param)
4643 {
4644         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4645
4646         ixgbe_dev_interrupt_get_status(dev);
4647         ixgbe_dev_interrupt_action(dev);
4648 }
4649
4650 static int
4651 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4652 {
4653         struct ixgbe_hw *hw;
4654
4655         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4656         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4657 }
4658
4659 static int
4660 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4661 {
4662         struct ixgbe_hw *hw;
4663
4664         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4665         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4666 }
4667
4668 static int
4669 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4670 {
4671         struct ixgbe_hw *hw;
4672         uint32_t mflcn_reg;
4673         uint32_t fccfg_reg;
4674         int rx_pause;
4675         int tx_pause;
4676
4677         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4678
4679         fc_conf->pause_time = hw->fc.pause_time;
4680         fc_conf->high_water = hw->fc.high_water[0];
4681         fc_conf->low_water = hw->fc.low_water[0];
4682         fc_conf->send_xon = hw->fc.send_xon;
4683         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4684
4685         /*
4686          * Return rx_pause status according to actual setting of
4687          * MFLCN register.
4688          */
4689         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4690         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4691                 rx_pause = 1;
4692         else
4693                 rx_pause = 0;
4694
4695         /*
4696          * Return tx_pause status according to actual setting of
4697          * FCCFG register.
4698          */
4699         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4700         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4701                 tx_pause = 1;
4702         else
4703                 tx_pause = 0;
4704
4705         if (rx_pause && tx_pause)
4706                 fc_conf->mode = RTE_FC_FULL;
4707         else if (rx_pause)
4708                 fc_conf->mode = RTE_FC_RX_PAUSE;
4709         else if (tx_pause)
4710                 fc_conf->mode = RTE_FC_TX_PAUSE;
4711         else
4712                 fc_conf->mode = RTE_FC_NONE;
4713
4714         return 0;
4715 }
4716
4717 static int
4718 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4719 {
4720         struct ixgbe_hw *hw;
4721         int err;
4722         uint32_t rx_buf_size;
4723         uint32_t max_high_water;
4724         uint32_t mflcn;
4725         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4726                 ixgbe_fc_none,
4727                 ixgbe_fc_rx_pause,
4728                 ixgbe_fc_tx_pause,
4729                 ixgbe_fc_full
4730         };
4731
4732         PMD_INIT_FUNC_TRACE();
4733
4734         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4735         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4736         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4737
4738         /*
4739          * At least reserve one Ethernet frame for watermark
4740          * high_water/low_water in kilo bytes for ixgbe
4741          */
4742         max_high_water = (rx_buf_size -
4743                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4744         if ((fc_conf->high_water > max_high_water) ||
4745                 (fc_conf->high_water < fc_conf->low_water)) {
4746                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4747                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4748                 return -EINVAL;
4749         }
4750
4751         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4752         hw->fc.pause_time     = fc_conf->pause_time;
4753         hw->fc.high_water[0]  = fc_conf->high_water;
4754         hw->fc.low_water[0]   = fc_conf->low_water;
4755         hw->fc.send_xon       = fc_conf->send_xon;
4756         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4757
4758         err = ixgbe_fc_enable(hw);
4759
4760         /* Not negotiated is not an error case */
4761         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4762
4763                 /* check if we want to forward MAC frames - driver doesn't have native
4764                  * capability to do that, so we'll write the registers ourselves */
4765
4766                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4767
4768                 /* set or clear MFLCN.PMCF bit depending on configuration */
4769                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4770                         mflcn |= IXGBE_MFLCN_PMCF;
4771                 else
4772                         mflcn &= ~IXGBE_MFLCN_PMCF;
4773
4774                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4775                 IXGBE_WRITE_FLUSH(hw);
4776
4777                 return 0;
4778         }
4779
4780         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4781         return -EIO;
4782 }
4783
4784 /**
4785  *  ixgbe_pfc_enable_generic - Enable flow control
4786  *  @hw: pointer to hardware structure
4787  *  @tc_num: traffic class number
4788  *  Enable flow control according to the current settings.
4789  */
4790 static int
4791 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4792 {
4793         int ret_val = 0;
4794         uint32_t mflcn_reg, fccfg_reg;
4795         uint32_t reg;
4796         uint32_t fcrtl, fcrth;
4797         uint8_t i;
4798         uint8_t nb_rx_en;
4799
4800         /* Validate the water mark configuration */
4801         if (!hw->fc.pause_time) {
4802                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4803                 goto out;
4804         }
4805
4806         /* Low water mark of zero causes XOFF floods */
4807         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4808                  /* High/Low water can not be 0 */
4809                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4810                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4811                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4812                         goto out;
4813                 }
4814
4815                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4816                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4817                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4818                         goto out;
4819                 }
4820         }
4821         /* Negotiate the fc mode to use */
4822         ixgbe_fc_autoneg(hw);
4823
4824         /* Disable any previous flow control settings */
4825         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4826         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4827
4828         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4829         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4830
4831         switch (hw->fc.current_mode) {
4832         case ixgbe_fc_none:
4833                 /*
4834                  * If the count of enabled RX Priority Flow control >1,
4835                  * and the TX pause can not be disabled
4836                  */
4837                 nb_rx_en = 0;
4838                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4839                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4840                         if (reg & IXGBE_FCRTH_FCEN)
4841                                 nb_rx_en++;
4842                 }
4843                 if (nb_rx_en > 1)
4844                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4845                 break;
4846         case ixgbe_fc_rx_pause:
4847                 /*
4848                  * Rx Flow control is enabled and Tx Flow control is
4849                  * disabled by software override. Since there really
4850                  * isn't a way to advertise that we are capable of RX
4851                  * Pause ONLY, we will advertise that we support both
4852                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4853                  * disable the adapter's ability to send PAUSE frames.
4854                  */
4855                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4856                 /*
4857                  * If the count of enabled RX Priority Flow control >1,
4858                  * and the TX pause can not be disabled
4859                  */
4860                 nb_rx_en = 0;
4861                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4862                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4863                         if (reg & IXGBE_FCRTH_FCEN)
4864                                 nb_rx_en++;
4865                 }
4866                 if (nb_rx_en > 1)
4867                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4868                 break;
4869         case ixgbe_fc_tx_pause:
4870                 /*
4871                  * Tx Flow control is enabled, and Rx Flow control is
4872                  * disabled by software override.
4873                  */
4874                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4875                 break;
4876         case ixgbe_fc_full:
4877                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4878                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4879                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4880                 break;
4881         default:
4882                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4883                 ret_val = IXGBE_ERR_CONFIG;
4884                 goto out;
4885         }
4886
4887         /* Set 802.3x based flow control settings. */
4888         mflcn_reg |= IXGBE_MFLCN_DPF;
4889         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4890         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4891
4892         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4893         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4894                 hw->fc.high_water[tc_num]) {
4895                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4896                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4897                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4898         } else {
4899                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4900                 /*
4901                  * In order to prevent Tx hangs when the internal Tx
4902                  * switch is enabled we must set the high water mark
4903                  * to the maximum FCRTH value.  This allows the Tx
4904                  * switch to function even under heavy Rx workloads.
4905                  */
4906                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4907         }
4908         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4909
4910         /* Configure pause time (2 TCs per register) */
4911         reg = hw->fc.pause_time * 0x00010001;
4912         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4913                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4914
4915         /* Configure flow control refresh threshold value */
4916         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4917
4918 out:
4919         return ret_val;
4920 }
4921
4922 static int
4923 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4924 {
4925         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4926         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4927
4928         if (hw->mac.type != ixgbe_mac_82598EB) {
4929                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4930         }
4931         return ret_val;
4932 }
4933
4934 static int
4935 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4936 {
4937         int err;
4938         uint32_t rx_buf_size;
4939         uint32_t max_high_water;
4940         uint8_t tc_num;
4941         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4942         struct ixgbe_hw *hw =
4943                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4944         struct ixgbe_dcb_config *dcb_config =
4945                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4946
4947         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4948                 ixgbe_fc_none,
4949                 ixgbe_fc_rx_pause,
4950                 ixgbe_fc_tx_pause,
4951                 ixgbe_fc_full
4952         };
4953
4954         PMD_INIT_FUNC_TRACE();
4955
4956         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4957         tc_num = map[pfc_conf->priority];
4958         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4959         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4960         /*
4961          * At least reserve one Ethernet frame for watermark
4962          * high_water/low_water in kilo bytes for ixgbe
4963          */
4964         max_high_water = (rx_buf_size -
4965                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4966         if ((pfc_conf->fc.high_water > max_high_water) ||
4967             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4968                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4969                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4970                 return -EINVAL;
4971         }
4972
4973         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4974         hw->fc.pause_time = pfc_conf->fc.pause_time;
4975         hw->fc.send_xon = pfc_conf->fc.send_xon;
4976         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4977         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4978
4979         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4980
4981         /* Not negotiated is not an error case */
4982         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4983                 return 0;
4984
4985         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4986         return -EIO;
4987 }
4988
4989 static int
4990 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4991                           struct rte_eth_rss_reta_entry64 *reta_conf,
4992                           uint16_t reta_size)
4993 {
4994         uint16_t i, sp_reta_size;
4995         uint8_t j, mask;
4996         uint32_t reta, r;
4997         uint16_t idx, shift;
4998         struct ixgbe_adapter *adapter = dev->data->dev_private;
4999         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5000         uint32_t reta_reg;
5001
5002         PMD_INIT_FUNC_TRACE();
5003
5004         if (!ixgbe_rss_update_sp(hw->mac.type)) {
5005                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5006                         "NIC.");
5007                 return -ENOTSUP;
5008         }
5009
5010         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5011         if (reta_size != sp_reta_size) {
5012                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5013                         "(%d) doesn't match the number hardware can supported "
5014                         "(%d)", reta_size, sp_reta_size);
5015                 return -EINVAL;
5016         }
5017
5018         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5019                 idx = i / RTE_RETA_GROUP_SIZE;
5020                 shift = i % RTE_RETA_GROUP_SIZE;
5021                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5022                                                 IXGBE_4_BIT_MASK);
5023                 if (!mask)
5024                         continue;
5025                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5026                 if (mask == IXGBE_4_BIT_MASK)
5027                         r = 0;
5028                 else
5029                         r = IXGBE_READ_REG(hw, reta_reg);
5030                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5031                         if (mask & (0x1 << j))
5032                                 reta |= reta_conf[idx].reta[shift + j] <<
5033                                                         (CHAR_BIT * j);
5034                         else
5035                                 reta |= r & (IXGBE_8_BIT_MASK <<
5036                                                 (CHAR_BIT * j));
5037                 }
5038                 IXGBE_WRITE_REG(hw, reta_reg, reta);
5039         }
5040         adapter->rss_reta_updated = 1;
5041
5042         return 0;
5043 }
5044
5045 static int
5046 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5047                          struct rte_eth_rss_reta_entry64 *reta_conf,
5048                          uint16_t reta_size)
5049 {
5050         uint16_t i, sp_reta_size;
5051         uint8_t j, mask;
5052         uint32_t reta;
5053         uint16_t idx, shift;
5054         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5055         uint32_t reta_reg;
5056
5057         PMD_INIT_FUNC_TRACE();
5058         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5059         if (reta_size != sp_reta_size) {
5060                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5061                         "(%d) doesn't match the number hardware can supported "
5062                         "(%d)", reta_size, sp_reta_size);
5063                 return -EINVAL;
5064         }
5065
5066         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5067                 idx = i / RTE_RETA_GROUP_SIZE;
5068                 shift = i % RTE_RETA_GROUP_SIZE;
5069                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5070                                                 IXGBE_4_BIT_MASK);
5071                 if (!mask)
5072                         continue;
5073
5074                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5075                 reta = IXGBE_READ_REG(hw, reta_reg);
5076                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5077                         if (mask & (0x1 << j))
5078                                 reta_conf[idx].reta[shift + j] =
5079                                         ((reta >> (CHAR_BIT * j)) &
5080                                                 IXGBE_8_BIT_MASK);
5081                 }
5082         }
5083
5084         return 0;
5085 }
5086
5087 static int
5088 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5089                                 uint32_t index, uint32_t pool)
5090 {
5091         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5092         uint32_t enable_addr = 1;
5093
5094         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5095                              pool, enable_addr);
5096 }
5097
5098 static void
5099 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5100 {
5101         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5102
5103         ixgbe_clear_rar(hw, index);
5104 }
5105
5106 static int
5107 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5108 {
5109         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5110
5111         ixgbe_remove_rar(dev, 0);
5112         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5113
5114         return 0;
5115 }
5116
5117 static bool
5118 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5119 {
5120         if (strcmp(dev->device->driver->name, drv->driver.name))
5121                 return false;
5122
5123         return true;
5124 }
5125
5126 bool
5127 is_ixgbe_supported(struct rte_eth_dev *dev)
5128 {
5129         return is_device_supported(dev, &rte_ixgbe_pmd);
5130 }
5131
5132 static int
5133 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5134 {
5135         uint32_t hlreg0;
5136         uint32_t maxfrs;
5137         struct ixgbe_hw *hw;
5138         struct rte_eth_dev_info dev_info;
5139         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5140         struct rte_eth_dev_data *dev_data = dev->data;
5141         int ret;
5142
5143         ret = ixgbe_dev_info_get(dev, &dev_info);
5144         if (ret != 0)
5145                 return ret;
5146
5147         /* check that mtu is within the allowed range */
5148         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5149                 return -EINVAL;
5150
5151         /* If device is started, refuse mtu that requires the support of
5152          * scattered packets when this feature has not been enabled before.
5153          */
5154         if (dev_data->dev_started && !dev_data->scattered_rx &&
5155             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5156              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5157                 PMD_INIT_LOG(ERR, "Stop port first.");
5158                 return -EINVAL;
5159         }
5160
5161         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5162         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5163
5164         /* switch to jumbo mode if needed */
5165         if (frame_size > RTE_ETHER_MAX_LEN) {
5166                 dev->data->dev_conf.rxmode.offloads |=
5167                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5168                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5169         } else {
5170                 dev->data->dev_conf.rxmode.offloads &=
5171                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5172                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5173         }
5174         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5175
5176         /* update max frame size */
5177         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5178
5179         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5180         maxfrs &= 0x0000FFFF;
5181         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5182         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5183
5184         return 0;
5185 }
5186
5187 /*
5188  * Virtual Function operations
5189  */
5190 static void
5191 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5192 {
5193         struct ixgbe_interrupt *intr =
5194                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5195         struct ixgbe_hw *hw =
5196                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5197
5198         PMD_INIT_FUNC_TRACE();
5199
5200         /* Clear interrupt mask to stop from interrupts being generated */
5201         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5202
5203         IXGBE_WRITE_FLUSH(hw);
5204
5205         /* Clear mask value. */
5206         intr->mask = 0;
5207 }
5208
5209 static void
5210 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5211 {
5212         struct ixgbe_interrupt *intr =
5213                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5214         struct ixgbe_hw *hw =
5215                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5216
5217         PMD_INIT_FUNC_TRACE();
5218
5219         /* VF enable interrupt autoclean */
5220         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5221         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5222         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5223
5224         IXGBE_WRITE_FLUSH(hw);
5225
5226         /* Save IXGBE_VTEIMS value to mask. */
5227         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5228 }
5229
5230 static int
5231 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5232 {
5233         struct rte_eth_conf *conf = &dev->data->dev_conf;
5234         struct ixgbe_adapter *adapter = dev->data->dev_private;
5235
5236         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5237                      dev->data->port_id);
5238
5239         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5240                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5241
5242         /*
5243          * VF has no ability to enable/disable HW CRC
5244          * Keep the persistent behavior the same as Host PF
5245          */
5246 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5247         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5248                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5249                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5250         }
5251 #else
5252         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5253                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5254                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5255         }
5256 #endif
5257
5258         /*
5259          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5260          * allocation or vector Rx preconditions we will reset it.
5261          */
5262         adapter->rx_bulk_alloc_allowed = true;
5263         adapter->rx_vec_allowed = true;
5264
5265         return 0;
5266 }
5267
5268 static int
5269 ixgbevf_dev_start(struct rte_eth_dev *dev)
5270 {
5271         struct ixgbe_hw *hw =
5272                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5273         uint32_t intr_vector = 0;
5274         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5275         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5276
5277         int err, mask = 0;
5278
5279         PMD_INIT_FUNC_TRACE();
5280
5281         /* Stop the link setup handler before resetting the HW. */
5282         ixgbe_dev_cancel_link_thread(dev);
5283
5284         err = hw->mac.ops.reset_hw(hw);
5285         if (err) {
5286                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5287                 return err;
5288         }
5289         hw->mac.get_link_status = true;
5290
5291         /* negotiate mailbox API version to use with the PF. */
5292         ixgbevf_negotiate_api(hw);
5293
5294         ixgbevf_dev_tx_init(dev);
5295
5296         /* This can fail when allocating mbufs for descriptor rings */
5297         err = ixgbevf_dev_rx_init(dev);
5298         if (err) {
5299                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5300                 ixgbe_dev_clear_queues(dev);
5301                 return err;
5302         }
5303
5304         /* Set vfta */
5305         ixgbevf_set_vfta_all(dev, 1);
5306
5307         /* Set HW strip */
5308         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5309                 ETH_VLAN_EXTEND_MASK;
5310         err = ixgbevf_vlan_offload_config(dev, mask);
5311         if (err) {
5312                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5313                 ixgbe_dev_clear_queues(dev);
5314                 return err;
5315         }
5316
5317         ixgbevf_dev_rxtx_start(dev);
5318
5319         /* check and configure queue intr-vector mapping */
5320         if (rte_intr_cap_multiple(intr_handle) &&
5321             dev->data->dev_conf.intr_conf.rxq) {
5322                 /* According to datasheet, only vector 0/1/2 can be used,
5323                  * now only one vector is used for Rx queue
5324                  */
5325                 intr_vector = 1;
5326                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5327                         return -1;
5328         }
5329
5330         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5331                 intr_handle->intr_vec =
5332                         rte_zmalloc("intr_vec",
5333                                     dev->data->nb_rx_queues * sizeof(int), 0);
5334                 if (intr_handle->intr_vec == NULL) {
5335                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5336                                      " intr_vec", dev->data->nb_rx_queues);
5337                         return -ENOMEM;
5338                 }
5339         }
5340         ixgbevf_configure_msix(dev);
5341
5342         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5343          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5344          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5345          * is not cleared, it will fail when following rte_intr_enable( ) tries
5346          * to map Rx queue interrupt to other VFIO vectors.
5347          * So clear uio/vfio intr/evevnfd first to avoid failure.
5348          */
5349         rte_intr_disable(intr_handle);
5350
5351         rte_intr_enable(intr_handle);
5352
5353         /* Re-enable interrupt for VF */
5354         ixgbevf_intr_enable(dev);
5355
5356         /*
5357          * Update link status right before return, because it may
5358          * start link configuration process in a separate thread.
5359          */
5360         ixgbevf_dev_link_update(dev, 0);
5361
5362         hw->adapter_stopped = false;
5363
5364         return 0;
5365 }
5366
5367 static void
5368 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5369 {
5370         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5371         struct ixgbe_adapter *adapter = dev->data->dev_private;
5372         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5373         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5374
5375         if (hw->adapter_stopped)
5376                 return;
5377
5378         PMD_INIT_FUNC_TRACE();
5379
5380         ixgbe_dev_cancel_link_thread(dev);
5381
5382         ixgbevf_intr_disable(dev);
5383
5384         hw->adapter_stopped = 1;
5385         ixgbe_stop_adapter(hw);
5386
5387         /*
5388           * Clear what we set, but we still keep shadow_vfta to
5389           * restore after device starts
5390           */
5391         ixgbevf_set_vfta_all(dev, 0);
5392
5393         /* Clear stored conf */
5394         dev->data->scattered_rx = 0;
5395
5396         ixgbe_dev_clear_queues(dev);
5397
5398         /* Clean datapath event and queue/vec mapping */
5399         rte_intr_efd_disable(intr_handle);
5400         if (intr_handle->intr_vec != NULL) {
5401                 rte_free(intr_handle->intr_vec);
5402                 intr_handle->intr_vec = NULL;
5403         }
5404
5405         adapter->rss_reta_updated = 0;
5406 }
5407
5408 static void
5409 ixgbevf_dev_close(struct rte_eth_dev *dev)
5410 {
5411         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5412         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5413         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5414
5415         PMD_INIT_FUNC_TRACE();
5416
5417         ixgbe_reset_hw(hw);
5418
5419         ixgbevf_dev_stop(dev);
5420
5421         ixgbe_dev_free_queues(dev);
5422
5423         /**
5424          * Remove the VF MAC address ro ensure
5425          * that the VF traffic goes to the PF
5426          * after stop, close and detach of the VF
5427          **/
5428         ixgbevf_remove_mac_addr(dev, 0);
5429
5430         dev->dev_ops = NULL;
5431         dev->rx_pkt_burst = NULL;
5432         dev->tx_pkt_burst = NULL;
5433
5434         rte_intr_disable(intr_handle);
5435         rte_intr_callback_unregister(intr_handle,
5436                                      ixgbevf_dev_interrupt_handler, dev);
5437 }
5438
5439 /*
5440  * Reset VF device
5441  */
5442 static int
5443 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5444 {
5445         int ret;
5446
5447         ret = eth_ixgbevf_dev_uninit(dev);
5448         if (ret)
5449                 return ret;
5450
5451         ret = eth_ixgbevf_dev_init(dev);
5452
5453         return ret;
5454 }
5455
5456 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5457 {
5458         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5459         struct ixgbe_vfta *shadow_vfta =
5460                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5461         int i = 0, j = 0, vfta = 0, mask = 1;
5462
5463         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5464                 vfta = shadow_vfta->vfta[i];
5465                 if (vfta) {
5466                         mask = 1;
5467                         for (j = 0; j < 32; j++) {
5468                                 if (vfta & mask)
5469                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5470                                                        on, false);
5471                                 mask <<= 1;
5472                         }
5473                 }
5474         }
5475
5476 }
5477
5478 static int
5479 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5480 {
5481         struct ixgbe_hw *hw =
5482                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5483         struct ixgbe_vfta *shadow_vfta =
5484                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5485         uint32_t vid_idx = 0;
5486         uint32_t vid_bit = 0;
5487         int ret = 0;
5488
5489         PMD_INIT_FUNC_TRACE();
5490
5491         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5492         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5493         if (ret) {
5494                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5495                 return ret;
5496         }
5497         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5498         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5499
5500         /* Save what we set and retore it after device reset */
5501         if (on)
5502                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5503         else
5504                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5505
5506         return 0;
5507 }
5508
5509 static void
5510 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5511 {
5512         struct ixgbe_hw *hw =
5513                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5514         uint32_t ctrl;
5515
5516         PMD_INIT_FUNC_TRACE();
5517
5518         if (queue >= hw->mac.max_rx_queues)
5519                 return;
5520
5521         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5522         if (on)
5523                 ctrl |= IXGBE_RXDCTL_VME;
5524         else
5525                 ctrl &= ~IXGBE_RXDCTL_VME;
5526         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5527
5528         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5529 }
5530
5531 static int
5532 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5533 {
5534         struct ixgbe_rx_queue *rxq;
5535         uint16_t i;
5536         int on = 0;
5537
5538         /* VF function only support hw strip feature, others are not support */
5539         if (mask & ETH_VLAN_STRIP_MASK) {
5540                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5541                         rxq = dev->data->rx_queues[i];
5542                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5543                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5544                 }
5545         }
5546
5547         return 0;
5548 }
5549
5550 static int
5551 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5552 {
5553         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5554
5555         ixgbevf_vlan_offload_config(dev, mask);
5556
5557         return 0;
5558 }
5559
5560 int
5561 ixgbe_vt_check(struct ixgbe_hw *hw)
5562 {
5563         uint32_t reg_val;
5564
5565         /* if Virtualization Technology is enabled */
5566         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5567         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5568                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5569                 return -1;
5570         }
5571
5572         return 0;
5573 }
5574
5575 static uint32_t
5576 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5577 {
5578         uint32_t vector = 0;
5579
5580         switch (hw->mac.mc_filter_type) {
5581         case 0:   /* use bits [47:36] of the address */
5582                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5583                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5584                 break;
5585         case 1:   /* use bits [46:35] of the address */
5586                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5587                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5588                 break;
5589         case 2:   /* use bits [45:34] of the address */
5590                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5591                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5592                 break;
5593         case 3:   /* use bits [43:32] of the address */
5594                 vector = ((uc_addr->addr_bytes[4]) |
5595                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5596                 break;
5597         default:  /* Invalid mc_filter_type */
5598                 break;
5599         }
5600
5601         /* vector can only be 12-bits or boundary will be exceeded */
5602         vector &= 0xFFF;
5603         return vector;
5604 }
5605
5606 static int
5607 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5608                         struct rte_ether_addr *mac_addr, uint8_t on)
5609 {
5610         uint32_t vector;
5611         uint32_t uta_idx;
5612         uint32_t reg_val;
5613         uint32_t uta_shift;
5614         uint32_t rc;
5615         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5616         const uint32_t ixgbe_uta_bit_shift = 5;
5617         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5618         const uint32_t bit1 = 0x1;
5619
5620         struct ixgbe_hw *hw =
5621                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5622         struct ixgbe_uta_info *uta_info =
5623                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5624
5625         /* The UTA table only exists on 82599 hardware and newer */
5626         if (hw->mac.type < ixgbe_mac_82599EB)
5627                 return -ENOTSUP;
5628
5629         vector = ixgbe_uta_vector(hw, mac_addr);
5630         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5631         uta_shift = vector & ixgbe_uta_bit_mask;
5632
5633         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5634         if (rc == on)
5635                 return 0;
5636
5637         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5638         if (on) {
5639                 uta_info->uta_in_use++;
5640                 reg_val |= (bit1 << uta_shift);
5641                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5642         } else {
5643                 uta_info->uta_in_use--;
5644                 reg_val &= ~(bit1 << uta_shift);
5645                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5646         }
5647
5648         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5649
5650         if (uta_info->uta_in_use > 0)
5651                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5652                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5653         else
5654                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5655
5656         return 0;
5657 }
5658
5659 static int
5660 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5661 {
5662         int i;
5663         struct ixgbe_hw *hw =
5664                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5665         struct ixgbe_uta_info *uta_info =
5666                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5667
5668         /* The UTA table only exists on 82599 hardware and newer */
5669         if (hw->mac.type < ixgbe_mac_82599EB)
5670                 return -ENOTSUP;
5671
5672         if (on) {
5673                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5674                         uta_info->uta_shadow[i] = ~0;
5675                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5676                 }
5677         } else {
5678                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5679                         uta_info->uta_shadow[i] = 0;
5680                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5681                 }
5682         }
5683         return 0;
5684
5685 }
5686
5687 uint32_t
5688 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5689 {
5690         uint32_t new_val = orig_val;
5691
5692         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5693                 new_val |= IXGBE_VMOLR_AUPE;
5694         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5695                 new_val |= IXGBE_VMOLR_ROMPE;
5696         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5697                 new_val |= IXGBE_VMOLR_ROPE;
5698         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5699                 new_val |= IXGBE_VMOLR_BAM;
5700         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5701                 new_val |= IXGBE_VMOLR_MPE;
5702
5703         return new_val;
5704 }
5705
5706 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5707 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5708 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5709 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5710 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5711         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5712         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5713
5714 static int
5715 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5716                       struct rte_eth_mirror_conf *mirror_conf,
5717                       uint8_t rule_id, uint8_t on)
5718 {
5719         uint32_t mr_ctl, vlvf;
5720         uint32_t mp_lsb = 0;
5721         uint32_t mv_msb = 0;
5722         uint32_t mv_lsb = 0;
5723         uint32_t mp_msb = 0;
5724         uint8_t i = 0;
5725         int reg_index = 0;
5726         uint64_t vlan_mask = 0;
5727
5728         const uint8_t pool_mask_offset = 32;
5729         const uint8_t vlan_mask_offset = 32;
5730         const uint8_t dst_pool_offset = 8;
5731         const uint8_t rule_mr_offset  = 4;
5732         const uint8_t mirror_rule_mask = 0x0F;
5733
5734         struct ixgbe_mirror_info *mr_info =
5735                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5736         struct ixgbe_hw *hw =
5737                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5738         uint8_t mirror_type = 0;
5739
5740         if (ixgbe_vt_check(hw) < 0)
5741                 return -ENOTSUP;
5742
5743         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5744                 return -EINVAL;
5745
5746         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5747                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5748                             mirror_conf->rule_type);
5749                 return -EINVAL;
5750         }
5751
5752         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5753                 mirror_type |= IXGBE_MRCTL_VLME;
5754                 /* Check if vlan id is valid and find conresponding VLAN ID
5755                  * index in VLVF
5756                  */
5757                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5758                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5759                                 /* search vlan id related pool vlan filter
5760                                  * index
5761                                  */
5762                                 reg_index = ixgbe_find_vlvf_slot(
5763                                                 hw,
5764                                                 mirror_conf->vlan.vlan_id[i],
5765                                                 false);
5766                                 if (reg_index < 0)
5767                                         return -EINVAL;
5768                                 vlvf = IXGBE_READ_REG(hw,
5769                                                       IXGBE_VLVF(reg_index));
5770                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5771                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5772                                       mirror_conf->vlan.vlan_id[i]))
5773                                         vlan_mask |= (1ULL << reg_index);
5774                                 else
5775                                         return -EINVAL;
5776                         }
5777                 }
5778
5779                 if (on) {
5780                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5781                         mv_msb = vlan_mask >> vlan_mask_offset;
5782
5783                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5784                                                 mirror_conf->vlan.vlan_mask;
5785                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5786                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5787                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5788                                                 mirror_conf->vlan.vlan_id[i];
5789                         }
5790                 } else {
5791                         mv_lsb = 0;
5792                         mv_msb = 0;
5793                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5794                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5795                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5796                 }
5797         }
5798
5799         /**
5800          * if enable pool mirror, write related pool mask register,if disable
5801          * pool mirror, clear PFMRVM register
5802          */
5803         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5804                 mirror_type |= IXGBE_MRCTL_VPME;
5805                 if (on) {
5806                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5807                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5808                         mr_info->mr_conf[rule_id].pool_mask =
5809                                         mirror_conf->pool_mask;
5810
5811                 } else {
5812                         mp_lsb = 0;
5813                         mp_msb = 0;
5814                         mr_info->mr_conf[rule_id].pool_mask = 0;
5815                 }
5816         }
5817         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5818                 mirror_type |= IXGBE_MRCTL_UPME;
5819         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5820                 mirror_type |= IXGBE_MRCTL_DPME;
5821
5822         /* read  mirror control register and recalculate it */
5823         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5824
5825         if (on) {
5826                 mr_ctl |= mirror_type;
5827                 mr_ctl &= mirror_rule_mask;
5828                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5829         } else {
5830                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5831         }
5832
5833         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5834         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5835
5836         /* write mirrror control  register */
5837         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5838
5839         /* write pool mirrror control  register */
5840         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5841                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5842                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5843                                 mp_msb);
5844         }
5845         /* write VLAN mirrror control  register */
5846         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5847                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5848                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5849                                 mv_msb);
5850         }
5851
5852         return 0;
5853 }
5854
5855 static int
5856 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5857 {
5858         int mr_ctl = 0;
5859         uint32_t lsb_val = 0;
5860         uint32_t msb_val = 0;
5861         const uint8_t rule_mr_offset = 4;
5862
5863         struct ixgbe_hw *hw =
5864                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5865         struct ixgbe_mirror_info *mr_info =
5866                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5867
5868         if (ixgbe_vt_check(hw) < 0)
5869                 return -ENOTSUP;
5870
5871         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5872                 return -EINVAL;
5873
5874         memset(&mr_info->mr_conf[rule_id], 0,
5875                sizeof(struct rte_eth_mirror_conf));
5876
5877         /* clear PFVMCTL register */
5878         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5879
5880         /* clear pool mask register */
5881         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5882         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5883
5884         /* clear vlan mask register */
5885         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5886         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5887
5888         return 0;
5889 }
5890
5891 static int
5892 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5893 {
5894         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5895         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5896         struct ixgbe_interrupt *intr =
5897                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5898         struct ixgbe_hw *hw =
5899                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5900         uint32_t vec = IXGBE_MISC_VEC_ID;
5901
5902         if (rte_intr_allow_others(intr_handle))
5903                 vec = IXGBE_RX_VEC_START;
5904         intr->mask |= (1 << vec);
5905         RTE_SET_USED(queue_id);
5906         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5907
5908         rte_intr_ack(intr_handle);
5909
5910         return 0;
5911 }
5912
5913 static int
5914 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5915 {
5916         struct ixgbe_interrupt *intr =
5917                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5918         struct ixgbe_hw *hw =
5919                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5920         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5921         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5922         uint32_t vec = IXGBE_MISC_VEC_ID;
5923
5924         if (rte_intr_allow_others(intr_handle))
5925                 vec = IXGBE_RX_VEC_START;
5926         intr->mask &= ~(1 << vec);
5927         RTE_SET_USED(queue_id);
5928         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5929
5930         return 0;
5931 }
5932
5933 static int
5934 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5935 {
5936         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5937         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5938         uint32_t mask;
5939         struct ixgbe_hw *hw =
5940                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5941         struct ixgbe_interrupt *intr =
5942                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5943
5944         if (queue_id < 16) {
5945                 ixgbe_disable_intr(hw);
5946                 intr->mask |= (1 << queue_id);
5947                 ixgbe_enable_intr(dev);
5948         } else if (queue_id < 32) {
5949                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5950                 mask &= (1 << queue_id);
5951                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5952         } else if (queue_id < 64) {
5953                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5954                 mask &= (1 << (queue_id - 32));
5955                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5956         }
5957         rte_intr_ack(intr_handle);
5958
5959         return 0;
5960 }
5961
5962 static int
5963 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5964 {
5965         uint32_t mask;
5966         struct ixgbe_hw *hw =
5967                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5968         struct ixgbe_interrupt *intr =
5969                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5970
5971         if (queue_id < 16) {
5972                 ixgbe_disable_intr(hw);
5973                 intr->mask &= ~(1 << queue_id);
5974                 ixgbe_enable_intr(dev);
5975         } else if (queue_id < 32) {
5976                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5977                 mask &= ~(1 << queue_id);
5978                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5979         } else if (queue_id < 64) {
5980                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5981                 mask &= ~(1 << (queue_id - 32));
5982                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5983         }
5984
5985         return 0;
5986 }
5987
5988 static void
5989 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5990                      uint8_t queue, uint8_t msix_vector)
5991 {
5992         uint32_t tmp, idx;
5993
5994         if (direction == -1) {
5995                 /* other causes */
5996                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5997                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5998                 tmp &= ~0xFF;
5999                 tmp |= msix_vector;
6000                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6001         } else {
6002                 /* rx or tx cause */
6003                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6004                 idx = ((16 * (queue & 1)) + (8 * direction));
6005                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6006                 tmp &= ~(0xFF << idx);
6007                 tmp |= (msix_vector << idx);
6008                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6009         }
6010 }
6011
6012 /**
6013  * set the IVAR registers, mapping interrupt causes to vectors
6014  * @param hw
6015  *  pointer to ixgbe_hw struct
6016  * @direction
6017  *  0 for Rx, 1 for Tx, -1 for other causes
6018  * @queue
6019  *  queue to map the corresponding interrupt to
6020  * @msix_vector
6021  *  the vector to map to the corresponding queue
6022  */
6023 static void
6024 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6025                    uint8_t queue, uint8_t msix_vector)
6026 {
6027         uint32_t tmp, idx;
6028
6029         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6030         if (hw->mac.type == ixgbe_mac_82598EB) {
6031                 if (direction == -1)
6032                         direction = 0;
6033                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6034                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6035                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6036                 tmp |= (msix_vector << (8 * (queue & 0x3)));
6037                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6038         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6039                         (hw->mac.type == ixgbe_mac_X540) ||
6040                         (hw->mac.type == ixgbe_mac_X550) ||
6041                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
6042                 if (direction == -1) {
6043                         /* other causes */
6044                         idx = ((queue & 1) * 8);
6045                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6046                         tmp &= ~(0xFF << idx);
6047                         tmp |= (msix_vector << idx);
6048                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6049                 } else {
6050                         /* rx or tx causes */
6051                         idx = ((16 * (queue & 1)) + (8 * direction));
6052                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6053                         tmp &= ~(0xFF << idx);
6054                         tmp |= (msix_vector << idx);
6055                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6056                 }
6057         }
6058 }
6059
6060 static void
6061 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6062 {
6063         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6064         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6065         struct ixgbe_hw *hw =
6066                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6067         uint32_t q_idx;
6068         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6069         uint32_t base = IXGBE_MISC_VEC_ID;
6070
6071         /* Configure VF other cause ivar */
6072         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6073
6074         /* won't configure msix register if no mapping is done
6075          * between intr vector and event fd.
6076          */
6077         if (!rte_intr_dp_is_en(intr_handle))
6078                 return;
6079
6080         if (rte_intr_allow_others(intr_handle)) {
6081                 base = IXGBE_RX_VEC_START;
6082                 vector_idx = IXGBE_RX_VEC_START;
6083         }
6084
6085         /* Configure all RX queues of VF */
6086         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6087                 /* Force all queue use vector 0,
6088                  * as IXGBE_VF_MAXMSIVECOTR = 1
6089                  */
6090                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6091                 intr_handle->intr_vec[q_idx] = vector_idx;
6092                 if (vector_idx < base + intr_handle->nb_efd - 1)
6093                         vector_idx++;
6094         }
6095
6096         /* As RX queue setting above show, all queues use the vector 0.
6097          * Set only the ITR value of IXGBE_MISC_VEC_ID.
6098          */
6099         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6100                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6101                         | IXGBE_EITR_CNT_WDIS);
6102 }
6103
6104 /**
6105  * Sets up the hardware to properly generate MSI-X interrupts
6106  * @hw
6107  *  board private structure
6108  */
6109 static void
6110 ixgbe_configure_msix(struct rte_eth_dev *dev)
6111 {
6112         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6113         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6114         struct ixgbe_hw *hw =
6115                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6116         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6117         uint32_t vec = IXGBE_MISC_VEC_ID;
6118         uint32_t mask;
6119         uint32_t gpie;
6120
6121         /* won't configure msix register if no mapping is done
6122          * between intr vector and event fd
6123          * but if misx has been enabled already, need to configure
6124          * auto clean, auto mask and throttling.
6125          */
6126         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6127         if (!rte_intr_dp_is_en(intr_handle) &&
6128             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6129                 return;
6130
6131         if (rte_intr_allow_others(intr_handle))
6132                 vec = base = IXGBE_RX_VEC_START;
6133
6134         /* setup GPIE for MSI-x mode */
6135         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6136         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6137                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6138         /* auto clearing and auto setting corresponding bits in EIMS
6139          * when MSI-X interrupt is triggered
6140          */
6141         if (hw->mac.type == ixgbe_mac_82598EB) {
6142                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6143         } else {
6144                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6145                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6146         }
6147         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6148
6149         /* Populate the IVAR table and set the ITR values to the
6150          * corresponding register.
6151          */
6152         if (rte_intr_dp_is_en(intr_handle)) {
6153                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6154                         queue_id++) {
6155                         /* by default, 1:1 mapping */
6156                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6157                         intr_handle->intr_vec[queue_id] = vec;
6158                         if (vec < base + intr_handle->nb_efd - 1)
6159                                 vec++;
6160                 }
6161
6162                 switch (hw->mac.type) {
6163                 case ixgbe_mac_82598EB:
6164                         ixgbe_set_ivar_map(hw, -1,
6165                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6166                                            IXGBE_MISC_VEC_ID);
6167                         break;
6168                 case ixgbe_mac_82599EB:
6169                 case ixgbe_mac_X540:
6170                 case ixgbe_mac_X550:
6171                 case ixgbe_mac_X550EM_x:
6172                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6173                         break;
6174                 default:
6175                         break;
6176                 }
6177         }
6178         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6179                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6180                         | IXGBE_EITR_CNT_WDIS);
6181
6182         /* set up to autoclear timer, and the vectors */
6183         mask = IXGBE_EIMS_ENABLE_MASK;
6184         mask &= ~(IXGBE_EIMS_OTHER |
6185                   IXGBE_EIMS_MAILBOX |
6186                   IXGBE_EIMS_LSC);
6187
6188         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6189 }
6190
6191 int
6192 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6193                            uint16_t queue_idx, uint16_t tx_rate)
6194 {
6195         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6196         struct rte_eth_rxmode *rxmode;
6197         uint32_t rf_dec, rf_int;
6198         uint32_t bcnrc_val;
6199         uint16_t link_speed = dev->data->dev_link.link_speed;
6200
6201         if (queue_idx >= hw->mac.max_tx_queues)
6202                 return -EINVAL;
6203
6204         if (tx_rate != 0) {
6205                 /* Calculate the rate factor values to set */
6206                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6207                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6208                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6209
6210                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6211                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6212                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6213                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6214         } else {
6215                 bcnrc_val = 0;
6216         }
6217
6218         rxmode = &dev->data->dev_conf.rxmode;
6219         /*
6220          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6221          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6222          * set as 0x4.
6223          */
6224         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6225             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6226                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6227                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6228         else
6229                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6230                         IXGBE_MMW_SIZE_DEFAULT);
6231
6232         /* Set RTTBCNRC of queue X */
6233         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6234         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6235         IXGBE_WRITE_FLUSH(hw);
6236
6237         return 0;
6238 }
6239
6240 static int
6241 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6242                      __attribute__((unused)) uint32_t index,
6243                      __attribute__((unused)) uint32_t pool)
6244 {
6245         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6246         int diag;
6247
6248         /*
6249          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6250          * operation. Trap this case to avoid exhausting the [very limited]
6251          * set of PF resources used to store VF MAC addresses.
6252          */
6253         if (memcmp(hw->mac.perm_addr, mac_addr,
6254                         sizeof(struct rte_ether_addr)) == 0)
6255                 return -1;
6256         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6257         if (diag != 0)
6258                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6259                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6260                             mac_addr->addr_bytes[0],
6261                             mac_addr->addr_bytes[1],
6262                             mac_addr->addr_bytes[2],
6263                             mac_addr->addr_bytes[3],
6264                             mac_addr->addr_bytes[4],
6265                             mac_addr->addr_bytes[5],
6266                             diag);
6267         return diag;
6268 }
6269
6270 static void
6271 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6272 {
6273         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6274         struct rte_ether_addr *perm_addr =
6275                 (struct rte_ether_addr *)hw->mac.perm_addr;
6276         struct rte_ether_addr *mac_addr;
6277         uint32_t i;
6278         int diag;
6279
6280         /*
6281          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6282          * not support the deletion of a given MAC address.
6283          * Instead, it imposes to delete all MAC addresses, then to add again
6284          * all MAC addresses with the exception of the one to be deleted.
6285          */
6286         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6287
6288         /*
6289          * Add again all MAC addresses, with the exception of the deleted one
6290          * and of the permanent MAC address.
6291          */
6292         for (i = 0, mac_addr = dev->data->mac_addrs;
6293              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6294                 /* Skip the deleted MAC address */
6295                 if (i == index)
6296                         continue;
6297                 /* Skip NULL MAC addresses */
6298                 if (rte_is_zero_ether_addr(mac_addr))
6299                         continue;
6300                 /* Skip the permanent MAC address */
6301                 if (memcmp(perm_addr, mac_addr,
6302                                 sizeof(struct rte_ether_addr)) == 0)
6303                         continue;
6304                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6305                 if (diag != 0)
6306                         PMD_DRV_LOG(ERR,
6307                                     "Adding again MAC address "
6308                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6309                                     "diag=%d",
6310                                     mac_addr->addr_bytes[0],
6311                                     mac_addr->addr_bytes[1],
6312                                     mac_addr->addr_bytes[2],
6313                                     mac_addr->addr_bytes[3],
6314                                     mac_addr->addr_bytes[4],
6315                                     mac_addr->addr_bytes[5],
6316                                     diag);
6317         }
6318 }
6319
6320 static int
6321 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6322                         struct rte_ether_addr *addr)
6323 {
6324         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6325
6326         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6327
6328         return 0;
6329 }
6330
6331 int
6332 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6333                         struct rte_eth_syn_filter *filter,
6334                         bool add)
6335 {
6336         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6337         struct ixgbe_filter_info *filter_info =
6338                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6339         uint32_t syn_info;
6340         uint32_t synqf;
6341
6342         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6343                 return -EINVAL;
6344
6345         syn_info = filter_info->syn_info;
6346
6347         if (add) {
6348                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6349                         return -EINVAL;
6350                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6351                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6352
6353                 if (filter->hig_pri)
6354                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6355                 else
6356                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6357         } else {
6358                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6359                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6360                         return -ENOENT;
6361                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6362         }
6363
6364         filter_info->syn_info = synqf;
6365         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6366         IXGBE_WRITE_FLUSH(hw);
6367         return 0;
6368 }
6369
6370 static int
6371 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6372                         struct rte_eth_syn_filter *filter)
6373 {
6374         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6375         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6376
6377         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6378                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6379                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6380                 return 0;
6381         }
6382         return -ENOENT;
6383 }
6384
6385 static int
6386 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6387                         enum rte_filter_op filter_op,
6388                         void *arg)
6389 {
6390         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6391         int ret;
6392
6393         MAC_TYPE_FILTER_SUP(hw->mac.type);
6394
6395         if (filter_op == RTE_ETH_FILTER_NOP)
6396                 return 0;
6397
6398         if (arg == NULL) {
6399                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6400                             filter_op);
6401                 return -EINVAL;
6402         }
6403
6404         switch (filter_op) {
6405         case RTE_ETH_FILTER_ADD:
6406                 ret = ixgbe_syn_filter_set(dev,
6407                                 (struct rte_eth_syn_filter *)arg,
6408                                 TRUE);
6409                 break;
6410         case RTE_ETH_FILTER_DELETE:
6411                 ret = ixgbe_syn_filter_set(dev,
6412                                 (struct rte_eth_syn_filter *)arg,
6413                                 FALSE);
6414                 break;
6415         case RTE_ETH_FILTER_GET:
6416                 ret = ixgbe_syn_filter_get(dev,
6417                                 (struct rte_eth_syn_filter *)arg);
6418                 break;
6419         default:
6420                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6421                 ret = -EINVAL;
6422                 break;
6423         }
6424
6425         return ret;
6426 }
6427
6428
6429 static inline enum ixgbe_5tuple_protocol
6430 convert_protocol_type(uint8_t protocol_value)
6431 {
6432         if (protocol_value == IPPROTO_TCP)
6433                 return IXGBE_FILTER_PROTOCOL_TCP;
6434         else if (protocol_value == IPPROTO_UDP)
6435                 return IXGBE_FILTER_PROTOCOL_UDP;
6436         else if (protocol_value == IPPROTO_SCTP)
6437                 return IXGBE_FILTER_PROTOCOL_SCTP;
6438         else
6439                 return IXGBE_FILTER_PROTOCOL_NONE;
6440 }
6441
6442 /* inject a 5-tuple filter to HW */
6443 static inline void
6444 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6445                            struct ixgbe_5tuple_filter *filter)
6446 {
6447         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6448         int i;
6449         uint32_t ftqf, sdpqf;
6450         uint32_t l34timir = 0;
6451         uint8_t mask = 0xff;
6452
6453         i = filter->index;
6454
6455         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6456                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6457         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6458
6459         ftqf = (uint32_t)(filter->filter_info.proto &
6460                 IXGBE_FTQF_PROTOCOL_MASK);
6461         ftqf |= (uint32_t)((filter->filter_info.priority &
6462                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6463         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6464                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6465         if (filter->filter_info.dst_ip_mask == 0)
6466                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6467         if (filter->filter_info.src_port_mask == 0)
6468                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6469         if (filter->filter_info.dst_port_mask == 0)
6470                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6471         if (filter->filter_info.proto_mask == 0)
6472                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6473         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6474         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6475         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6476
6477         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6478         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6479         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6480         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6481
6482         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6483         l34timir |= (uint32_t)(filter->queue <<
6484                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6485         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6486 }
6487
6488 /*
6489  * add a 5tuple filter
6490  *
6491  * @param
6492  * dev: Pointer to struct rte_eth_dev.
6493  * index: the index the filter allocates.
6494  * filter: ponter to the filter that will be added.
6495  * rx_queue: the queue id the filter assigned to.
6496  *
6497  * @return
6498  *    - On success, zero.
6499  *    - On failure, a negative value.
6500  */
6501 static int
6502 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6503                         struct ixgbe_5tuple_filter *filter)
6504 {
6505         struct ixgbe_filter_info *filter_info =
6506                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6507         int i, idx, shift;
6508
6509         /*
6510          * look for an unused 5tuple filter index,
6511          * and insert the filter to list.
6512          */
6513         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6514                 idx = i / (sizeof(uint32_t) * NBBY);
6515                 shift = i % (sizeof(uint32_t) * NBBY);
6516                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6517                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6518                         filter->index = i;
6519                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6520                                           filter,
6521                                           entries);
6522                         break;
6523                 }
6524         }
6525         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6526                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6527                 return -ENOSYS;
6528         }
6529
6530         ixgbe_inject_5tuple_filter(dev, filter);
6531
6532         return 0;
6533 }
6534
6535 /*
6536  * remove a 5tuple filter
6537  *
6538  * @param
6539  * dev: Pointer to struct rte_eth_dev.
6540  * filter: the pointer of the filter will be removed.
6541  */
6542 static void
6543 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6544                         struct ixgbe_5tuple_filter *filter)
6545 {
6546         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6547         struct ixgbe_filter_info *filter_info =
6548                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6549         uint16_t index = filter->index;
6550
6551         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6552                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6553         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6554         rte_free(filter);
6555
6556         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6557         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6558         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6559         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6560         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6561 }
6562
6563 static int
6564 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6565 {
6566         struct ixgbe_hw *hw;
6567         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6568         struct rte_eth_dev_data *dev_data = dev->data;
6569
6570         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6571
6572         if (mtu < RTE_ETHER_MIN_MTU ||
6573                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6574                 return -EINVAL;
6575
6576         /* If device is started, refuse mtu that requires the support of
6577          * scattered packets when this feature has not been enabled before.
6578          */
6579         if (dev_data->dev_started && !dev_data->scattered_rx &&
6580             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6581              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6582                 PMD_INIT_LOG(ERR, "Stop port first.");
6583                 return -EINVAL;
6584         }
6585
6586         /*
6587          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6588          * request of the version 2.0 of the mailbox API.
6589          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6590          * of the mailbox API.
6591          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6592          * prior to 3.11.33 which contains the following change:
6593          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6594          */
6595         ixgbevf_rlpml_set_vf(hw, max_frame);
6596
6597         /* update max frame size */
6598         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6599         return 0;
6600 }
6601
6602 static inline struct ixgbe_5tuple_filter *
6603 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6604                         struct ixgbe_5tuple_filter_info *key)
6605 {
6606         struct ixgbe_5tuple_filter *it;
6607
6608         TAILQ_FOREACH(it, filter_list, entries) {
6609                 if (memcmp(key, &it->filter_info,
6610                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6611                         return it;
6612                 }
6613         }
6614         return NULL;
6615 }
6616
6617 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6618 static inline int
6619 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6620                         struct ixgbe_5tuple_filter_info *filter_info)
6621 {
6622         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6623                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6624                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6625                 return -EINVAL;
6626
6627         switch (filter->dst_ip_mask) {
6628         case UINT32_MAX:
6629                 filter_info->dst_ip_mask = 0;
6630                 filter_info->dst_ip = filter->dst_ip;
6631                 break;
6632         case 0:
6633                 filter_info->dst_ip_mask = 1;
6634                 break;
6635         default:
6636                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6637                 return -EINVAL;
6638         }
6639
6640         switch (filter->src_ip_mask) {
6641         case UINT32_MAX:
6642                 filter_info->src_ip_mask = 0;
6643                 filter_info->src_ip = filter->src_ip;
6644                 break;
6645         case 0:
6646                 filter_info->src_ip_mask = 1;
6647                 break;
6648         default:
6649                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6650                 return -EINVAL;
6651         }
6652
6653         switch (filter->dst_port_mask) {
6654         case UINT16_MAX:
6655                 filter_info->dst_port_mask = 0;
6656                 filter_info->dst_port = filter->dst_port;
6657                 break;
6658         case 0:
6659                 filter_info->dst_port_mask = 1;
6660                 break;
6661         default:
6662                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6663                 return -EINVAL;
6664         }
6665
6666         switch (filter->src_port_mask) {
6667         case UINT16_MAX:
6668                 filter_info->src_port_mask = 0;
6669                 filter_info->src_port = filter->src_port;
6670                 break;
6671         case 0:
6672                 filter_info->src_port_mask = 1;
6673                 break;
6674         default:
6675                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6676                 return -EINVAL;
6677         }
6678
6679         switch (filter->proto_mask) {
6680         case UINT8_MAX:
6681                 filter_info->proto_mask = 0;
6682                 filter_info->proto =
6683                         convert_protocol_type(filter->proto);
6684                 break;
6685         case 0:
6686                 filter_info->proto_mask = 1;
6687                 break;
6688         default:
6689                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6690                 return -EINVAL;
6691         }
6692
6693         filter_info->priority = (uint8_t)filter->priority;
6694         return 0;
6695 }
6696
6697 /*
6698  * add or delete a ntuple filter
6699  *
6700  * @param
6701  * dev: Pointer to struct rte_eth_dev.
6702  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6703  * add: if true, add filter, if false, remove filter
6704  *
6705  * @return
6706  *    - On success, zero.
6707  *    - On failure, a negative value.
6708  */
6709 int
6710 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6711                         struct rte_eth_ntuple_filter *ntuple_filter,
6712                         bool add)
6713 {
6714         struct ixgbe_filter_info *filter_info =
6715                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6716         struct ixgbe_5tuple_filter_info filter_5tuple;
6717         struct ixgbe_5tuple_filter *filter;
6718         int ret;
6719
6720         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6721                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6722                 return -EINVAL;
6723         }
6724
6725         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6726         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6727         if (ret < 0)
6728                 return ret;
6729
6730         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6731                                          &filter_5tuple);
6732         if (filter != NULL && add) {
6733                 PMD_DRV_LOG(ERR, "filter exists.");
6734                 return -EEXIST;
6735         }
6736         if (filter == NULL && !add) {
6737                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6738                 return -ENOENT;
6739         }
6740
6741         if (add) {
6742                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6743                                 sizeof(struct ixgbe_5tuple_filter), 0);
6744                 if (filter == NULL)
6745                         return -ENOMEM;
6746                 rte_memcpy(&filter->filter_info,
6747                                  &filter_5tuple,
6748                                  sizeof(struct ixgbe_5tuple_filter_info));
6749                 filter->queue = ntuple_filter->queue;
6750                 ret = ixgbe_add_5tuple_filter(dev, filter);
6751                 if (ret < 0) {
6752                         rte_free(filter);
6753                         return ret;
6754                 }
6755         } else
6756                 ixgbe_remove_5tuple_filter(dev, filter);
6757
6758         return 0;
6759 }
6760
6761 /*
6762  * get a ntuple filter
6763  *
6764  * @param
6765  * dev: Pointer to struct rte_eth_dev.
6766  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6767  *
6768  * @return
6769  *    - On success, zero.
6770  *    - On failure, a negative value.
6771  */
6772 static int
6773 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6774                         struct rte_eth_ntuple_filter *ntuple_filter)
6775 {
6776         struct ixgbe_filter_info *filter_info =
6777                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6778         struct ixgbe_5tuple_filter_info filter_5tuple;
6779         struct ixgbe_5tuple_filter *filter;
6780         int ret;
6781
6782         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6783                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6784                 return -EINVAL;
6785         }
6786
6787         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6788         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6789         if (ret < 0)
6790                 return ret;
6791
6792         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6793                                          &filter_5tuple);
6794         if (filter == NULL) {
6795                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6796                 return -ENOENT;
6797         }
6798         ntuple_filter->queue = filter->queue;
6799         return 0;
6800 }
6801
6802 /*
6803  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6804  * @dev: pointer to rte_eth_dev structure
6805  * @filter_op:operation will be taken.
6806  * @arg: a pointer to specific structure corresponding to the filter_op
6807  *
6808  * @return
6809  *    - On success, zero.
6810  *    - On failure, a negative value.
6811  */
6812 static int
6813 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6814                                 enum rte_filter_op filter_op,
6815                                 void *arg)
6816 {
6817         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6818         int ret;
6819
6820         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6821
6822         if (filter_op == RTE_ETH_FILTER_NOP)
6823                 return 0;
6824
6825         if (arg == NULL) {
6826                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6827                             filter_op);
6828                 return -EINVAL;
6829         }
6830
6831         switch (filter_op) {
6832         case RTE_ETH_FILTER_ADD:
6833                 ret = ixgbe_add_del_ntuple_filter(dev,
6834                         (struct rte_eth_ntuple_filter *)arg,
6835                         TRUE);
6836                 break;
6837         case RTE_ETH_FILTER_DELETE:
6838                 ret = ixgbe_add_del_ntuple_filter(dev,
6839                         (struct rte_eth_ntuple_filter *)arg,
6840                         FALSE);
6841                 break;
6842         case RTE_ETH_FILTER_GET:
6843                 ret = ixgbe_get_ntuple_filter(dev,
6844                         (struct rte_eth_ntuple_filter *)arg);
6845                 break;
6846         default:
6847                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6848                 ret = -EINVAL;
6849                 break;
6850         }
6851         return ret;
6852 }
6853
6854 int
6855 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6856                         struct rte_eth_ethertype_filter *filter,
6857                         bool add)
6858 {
6859         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6860         struct ixgbe_filter_info *filter_info =
6861                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6862         uint32_t etqf = 0;
6863         uint32_t etqs = 0;
6864         int ret;
6865         struct ixgbe_ethertype_filter ethertype_filter;
6866
6867         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6868                 return -EINVAL;
6869
6870         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6871                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6872                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6873                         " ethertype filter.", filter->ether_type);
6874                 return -EINVAL;
6875         }
6876
6877         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6878                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6879                 return -EINVAL;
6880         }
6881         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6882                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6883                 return -EINVAL;
6884         }
6885
6886         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6887         if (ret >= 0 && add) {
6888                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6889                             filter->ether_type);
6890                 return -EEXIST;
6891         }
6892         if (ret < 0 && !add) {
6893                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6894                             filter->ether_type);
6895                 return -ENOENT;
6896         }
6897
6898         if (add) {
6899                 etqf = IXGBE_ETQF_FILTER_EN;
6900                 etqf |= (uint32_t)filter->ether_type;
6901                 etqs |= (uint32_t)((filter->queue <<
6902                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6903                                     IXGBE_ETQS_RX_QUEUE);
6904                 etqs |= IXGBE_ETQS_QUEUE_EN;
6905
6906                 ethertype_filter.ethertype = filter->ether_type;
6907                 ethertype_filter.etqf = etqf;
6908                 ethertype_filter.etqs = etqs;
6909                 ethertype_filter.conf = FALSE;
6910                 ret = ixgbe_ethertype_filter_insert(filter_info,
6911                                                     &ethertype_filter);
6912                 if (ret < 0) {
6913                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6914                         return -ENOSPC;
6915                 }
6916         } else {
6917                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6918                 if (ret < 0)
6919                         return -ENOSYS;
6920         }
6921         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6922         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6923         IXGBE_WRITE_FLUSH(hw);
6924
6925         return 0;
6926 }
6927
6928 static int
6929 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6930                         struct rte_eth_ethertype_filter *filter)
6931 {
6932         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6933         struct ixgbe_filter_info *filter_info =
6934                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6935         uint32_t etqf, etqs;
6936         int ret;
6937
6938         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6939         if (ret < 0) {
6940                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6941                             filter->ether_type);
6942                 return -ENOENT;
6943         }
6944
6945         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6946         if (etqf & IXGBE_ETQF_FILTER_EN) {
6947                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6948                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6949                 filter->flags = 0;
6950                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6951                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6952                 return 0;
6953         }
6954         return -ENOENT;
6955 }
6956
6957 /*
6958  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6959  * @dev: pointer to rte_eth_dev structure
6960  * @filter_op:operation will be taken.
6961  * @arg: a pointer to specific structure corresponding to the filter_op
6962  */
6963 static int
6964 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6965                                 enum rte_filter_op filter_op,
6966                                 void *arg)
6967 {
6968         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6969         int ret;
6970
6971         MAC_TYPE_FILTER_SUP(hw->mac.type);
6972
6973         if (filter_op == RTE_ETH_FILTER_NOP)
6974                 return 0;
6975
6976         if (arg == NULL) {
6977                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6978                             filter_op);
6979                 return -EINVAL;
6980         }
6981
6982         switch (filter_op) {
6983         case RTE_ETH_FILTER_ADD:
6984                 ret = ixgbe_add_del_ethertype_filter(dev,
6985                         (struct rte_eth_ethertype_filter *)arg,
6986                         TRUE);
6987                 break;
6988         case RTE_ETH_FILTER_DELETE:
6989                 ret = ixgbe_add_del_ethertype_filter(dev,
6990                         (struct rte_eth_ethertype_filter *)arg,
6991                         FALSE);
6992                 break;
6993         case RTE_ETH_FILTER_GET:
6994                 ret = ixgbe_get_ethertype_filter(dev,
6995                         (struct rte_eth_ethertype_filter *)arg);
6996                 break;
6997         default:
6998                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6999                 ret = -EINVAL;
7000                 break;
7001         }
7002         return ret;
7003 }
7004
7005 static int
7006 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
7007                      enum rte_filter_type filter_type,
7008                      enum rte_filter_op filter_op,
7009                      void *arg)
7010 {
7011         int ret = 0;
7012
7013         switch (filter_type) {
7014         case RTE_ETH_FILTER_NTUPLE:
7015                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
7016                 break;
7017         case RTE_ETH_FILTER_ETHERTYPE:
7018                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
7019                 break;
7020         case RTE_ETH_FILTER_SYN:
7021                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
7022                 break;
7023         case RTE_ETH_FILTER_FDIR:
7024                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
7025                 break;
7026         case RTE_ETH_FILTER_L2_TUNNEL:
7027                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
7028                 break;
7029         case RTE_ETH_FILTER_GENERIC:
7030                 if (filter_op != RTE_ETH_FILTER_GET)
7031                         return -EINVAL;
7032                 *(const void **)arg = &ixgbe_flow_ops;
7033                 break;
7034         default:
7035                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7036                                                         filter_type);
7037                 ret = -EINVAL;
7038                 break;
7039         }
7040
7041         return ret;
7042 }
7043
7044 static u8 *
7045 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
7046                         u8 **mc_addr_ptr, u32 *vmdq)
7047 {
7048         u8 *mc_addr;
7049
7050         *vmdq = 0;
7051         mc_addr = *mc_addr_ptr;
7052         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
7053         return mc_addr;
7054 }
7055
7056 static int
7057 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
7058                           struct rte_ether_addr *mc_addr_set,
7059                           uint32_t nb_mc_addr)
7060 {
7061         struct ixgbe_hw *hw;
7062         u8 *mc_addr_list;
7063
7064         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7065         mc_addr_list = (u8 *)mc_addr_set;
7066         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
7067                                          ixgbe_dev_addr_list_itr, TRUE);
7068 }
7069
7070 static uint64_t
7071 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
7072 {
7073         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7074         uint64_t systime_cycles;
7075
7076         switch (hw->mac.type) {
7077         case ixgbe_mac_X550:
7078         case ixgbe_mac_X550EM_x:
7079         case ixgbe_mac_X550EM_a:
7080                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
7081                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7082                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7083                                 * NSEC_PER_SEC;
7084                 break;
7085         default:
7086                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7087                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7088                                 << 32;
7089         }
7090
7091         return systime_cycles;
7092 }
7093
7094 static uint64_t
7095 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7096 {
7097         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7098         uint64_t rx_tstamp_cycles;
7099
7100         switch (hw->mac.type) {
7101         case ixgbe_mac_X550:
7102         case ixgbe_mac_X550EM_x:
7103         case ixgbe_mac_X550EM_a:
7104                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7105                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7106                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7107                                 * NSEC_PER_SEC;
7108                 break;
7109         default:
7110                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7111                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7112                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7113                                 << 32;
7114         }
7115
7116         return rx_tstamp_cycles;
7117 }
7118
7119 static uint64_t
7120 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7121 {
7122         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7123         uint64_t tx_tstamp_cycles;
7124
7125         switch (hw->mac.type) {
7126         case ixgbe_mac_X550:
7127         case ixgbe_mac_X550EM_x:
7128         case ixgbe_mac_X550EM_a:
7129                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7130                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7131                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7132                                 * NSEC_PER_SEC;
7133                 break;
7134         default:
7135                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7136                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7137                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7138                                 << 32;
7139         }
7140
7141         return tx_tstamp_cycles;
7142 }
7143
7144 static void
7145 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7146 {
7147         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7148         struct ixgbe_adapter *adapter = dev->data->dev_private;
7149         struct rte_eth_link link;
7150         uint32_t incval = 0;
7151         uint32_t shift = 0;
7152
7153         /* Get current link speed. */
7154         ixgbe_dev_link_update(dev, 1);
7155         rte_eth_linkstatus_get(dev, &link);
7156
7157         switch (link.link_speed) {
7158         case ETH_SPEED_NUM_100M:
7159                 incval = IXGBE_INCVAL_100;
7160                 shift = IXGBE_INCVAL_SHIFT_100;
7161                 break;
7162         case ETH_SPEED_NUM_1G:
7163                 incval = IXGBE_INCVAL_1GB;
7164                 shift = IXGBE_INCVAL_SHIFT_1GB;
7165                 break;
7166         case ETH_SPEED_NUM_10G:
7167         default:
7168                 incval = IXGBE_INCVAL_10GB;
7169                 shift = IXGBE_INCVAL_SHIFT_10GB;
7170                 break;
7171         }
7172
7173         switch (hw->mac.type) {
7174         case ixgbe_mac_X550:
7175         case ixgbe_mac_X550EM_x:
7176         case ixgbe_mac_X550EM_a:
7177                 /* Independent of link speed. */
7178                 incval = 1;
7179                 /* Cycles read will be interpreted as ns. */
7180                 shift = 0;
7181                 /* Fall-through */
7182         case ixgbe_mac_X540:
7183                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7184                 break;
7185         case ixgbe_mac_82599EB:
7186                 incval >>= IXGBE_INCVAL_SHIFT_82599;
7187                 shift -= IXGBE_INCVAL_SHIFT_82599;
7188                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7189                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7190                 break;
7191         default:
7192                 /* Not supported. */
7193                 return;
7194         }
7195
7196         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7197         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7198         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7199
7200         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7201         adapter->systime_tc.cc_shift = shift;
7202         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7203
7204         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7205         adapter->rx_tstamp_tc.cc_shift = shift;
7206         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7207
7208         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7209         adapter->tx_tstamp_tc.cc_shift = shift;
7210         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7211 }
7212
7213 static int
7214 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7215 {
7216         struct ixgbe_adapter *adapter = dev->data->dev_private;
7217
7218         adapter->systime_tc.nsec += delta;
7219         adapter->rx_tstamp_tc.nsec += delta;
7220         adapter->tx_tstamp_tc.nsec += delta;
7221
7222         return 0;
7223 }
7224
7225 static int
7226 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7227 {
7228         uint64_t ns;
7229         struct ixgbe_adapter *adapter = dev->data->dev_private;
7230
7231         ns = rte_timespec_to_ns(ts);
7232         /* Set the timecounters to a new value. */
7233         adapter->systime_tc.nsec = ns;
7234         adapter->rx_tstamp_tc.nsec = ns;
7235         adapter->tx_tstamp_tc.nsec = ns;
7236
7237         return 0;
7238 }
7239
7240 static int
7241 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7242 {
7243         uint64_t ns, systime_cycles;
7244         struct ixgbe_adapter *adapter = dev->data->dev_private;
7245
7246         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7247         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7248         *ts = rte_ns_to_timespec(ns);
7249
7250         return 0;
7251 }
7252
7253 static int
7254 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7255 {
7256         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7257         uint32_t tsync_ctl;
7258         uint32_t tsauxc;
7259
7260         /* Stop the timesync system time. */
7261         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7262         /* Reset the timesync system time value. */
7263         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7264         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7265
7266         /* Enable system time for platforms where it isn't on by default. */
7267         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7268         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7269         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7270
7271         ixgbe_start_timecounters(dev);
7272
7273         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7274         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7275                         (RTE_ETHER_TYPE_1588 |
7276                          IXGBE_ETQF_FILTER_EN |
7277                          IXGBE_ETQF_1588));
7278
7279         /* Enable timestamping of received PTP packets. */
7280         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7281         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7282         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7283
7284         /* Enable timestamping of transmitted PTP packets. */
7285         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7286         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7287         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7288
7289         IXGBE_WRITE_FLUSH(hw);
7290
7291         return 0;
7292 }
7293
7294 static int
7295 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7296 {
7297         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7298         uint32_t tsync_ctl;
7299
7300         /* Disable timestamping of transmitted PTP packets. */
7301         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7302         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7303         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7304
7305         /* Disable timestamping of received PTP packets. */
7306         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7307         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7308         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7309
7310         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7311         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7312
7313         /* Stop incrementating the System Time registers. */
7314         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7315
7316         return 0;
7317 }
7318
7319 static int
7320 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7321                                  struct timespec *timestamp,
7322                                  uint32_t flags __rte_unused)
7323 {
7324         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7325         struct ixgbe_adapter *adapter = dev->data->dev_private;
7326         uint32_t tsync_rxctl;
7327         uint64_t rx_tstamp_cycles;
7328         uint64_t ns;
7329
7330         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7331         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7332                 return -EINVAL;
7333
7334         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7335         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7336         *timestamp = rte_ns_to_timespec(ns);
7337
7338         return  0;
7339 }
7340
7341 static int
7342 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7343                                  struct timespec *timestamp)
7344 {
7345         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7346         struct ixgbe_adapter *adapter = dev->data->dev_private;
7347         uint32_t tsync_txctl;
7348         uint64_t tx_tstamp_cycles;
7349         uint64_t ns;
7350
7351         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7352         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7353                 return -EINVAL;
7354
7355         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7356         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7357         *timestamp = rte_ns_to_timespec(ns);
7358
7359         return 0;
7360 }
7361
7362 static int
7363 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7364 {
7365         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7366         int count = 0;
7367         int g_ind = 0;
7368         const struct reg_info *reg_group;
7369         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7370                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7371
7372         while ((reg_group = reg_set[g_ind++]))
7373                 count += ixgbe_regs_group_count(reg_group);
7374
7375         return count;
7376 }
7377
7378 static int
7379 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7380 {
7381         int count = 0;
7382         int g_ind = 0;
7383         const struct reg_info *reg_group;
7384
7385         while ((reg_group = ixgbevf_regs[g_ind++]))
7386                 count += ixgbe_regs_group_count(reg_group);
7387
7388         return count;
7389 }
7390
7391 static int
7392 ixgbe_get_regs(struct rte_eth_dev *dev,
7393               struct rte_dev_reg_info *regs)
7394 {
7395         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7396         uint32_t *data = regs->data;
7397         int g_ind = 0;
7398         int count = 0;
7399         const struct reg_info *reg_group;
7400         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7401                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7402
7403         if (data == NULL) {
7404                 regs->length = ixgbe_get_reg_length(dev);
7405                 regs->width = sizeof(uint32_t);
7406                 return 0;
7407         }
7408
7409         /* Support only full register dump */
7410         if ((regs->length == 0) ||
7411             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7412                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7413                         hw->device_id;
7414                 while ((reg_group = reg_set[g_ind++]))
7415                         count += ixgbe_read_regs_group(dev, &data[count],
7416                                 reg_group);
7417                 return 0;
7418         }
7419
7420         return -ENOTSUP;
7421 }
7422
7423 static int
7424 ixgbevf_get_regs(struct rte_eth_dev *dev,
7425                 struct rte_dev_reg_info *regs)
7426 {
7427         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7428         uint32_t *data = regs->data;
7429         int g_ind = 0;
7430         int count = 0;
7431         const struct reg_info *reg_group;
7432
7433         if (data == NULL) {
7434                 regs->length = ixgbevf_get_reg_length(dev);
7435                 regs->width = sizeof(uint32_t);
7436                 return 0;
7437         }
7438
7439         /* Support only full register dump */
7440         if ((regs->length == 0) ||
7441             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7442                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7443                         hw->device_id;
7444                 while ((reg_group = ixgbevf_regs[g_ind++]))
7445                         count += ixgbe_read_regs_group(dev, &data[count],
7446                                                       reg_group);
7447                 return 0;
7448         }
7449
7450         return -ENOTSUP;
7451 }
7452
7453 static int
7454 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7455 {
7456         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7457
7458         /* Return unit is byte count */
7459         return hw->eeprom.word_size * 2;
7460 }
7461
7462 static int
7463 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7464                 struct rte_dev_eeprom_info *in_eeprom)
7465 {
7466         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7467         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7468         uint16_t *data = in_eeprom->data;
7469         int first, length;
7470
7471         first = in_eeprom->offset >> 1;
7472         length = in_eeprom->length >> 1;
7473         if ((first > hw->eeprom.word_size) ||
7474             ((first + length) > hw->eeprom.word_size))
7475                 return -EINVAL;
7476
7477         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7478
7479         return eeprom->ops.read_buffer(hw, first, length, data);
7480 }
7481
7482 static int
7483 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7484                 struct rte_dev_eeprom_info *in_eeprom)
7485 {
7486         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7487         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7488         uint16_t *data = in_eeprom->data;
7489         int first, length;
7490
7491         first = in_eeprom->offset >> 1;
7492         length = in_eeprom->length >> 1;
7493         if ((first > hw->eeprom.word_size) ||
7494             ((first + length) > hw->eeprom.word_size))
7495                 return -EINVAL;
7496
7497         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7498
7499         return eeprom->ops.write_buffer(hw,  first, length, data);
7500 }
7501
7502 static int
7503 ixgbe_get_module_info(struct rte_eth_dev *dev,
7504                       struct rte_eth_dev_module_info *modinfo)
7505 {
7506         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7507         uint32_t status;
7508         uint8_t sff8472_rev, addr_mode;
7509         bool page_swap = false;
7510
7511         /* Check whether we support SFF-8472 or not */
7512         status = hw->phy.ops.read_i2c_eeprom(hw,
7513                                              IXGBE_SFF_SFF_8472_COMP,
7514                                              &sff8472_rev);
7515         if (status != 0)
7516                 return -EIO;
7517
7518         /* addressing mode is not supported */
7519         status = hw->phy.ops.read_i2c_eeprom(hw,
7520                                              IXGBE_SFF_SFF_8472_SWAP,
7521                                              &addr_mode);
7522         if (status != 0)
7523                 return -EIO;
7524
7525         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7526                 PMD_DRV_LOG(ERR,
7527                             "Address change required to access page 0xA2, "
7528                             "but not supported. Please report the module "
7529                             "type to the driver maintainers.");
7530                 page_swap = true;
7531         }
7532
7533         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7534                 /* We have a SFP, but it does not support SFF-8472 */
7535                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7536                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7537         } else {
7538                 /* We have a SFP which supports a revision of SFF-8472. */
7539                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7540                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7541         }
7542
7543         return 0;
7544 }
7545
7546 static int
7547 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7548                         struct rte_dev_eeprom_info *info)
7549 {
7550         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7551         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7552         uint8_t databyte = 0xFF;
7553         uint8_t *data = info->data;
7554         uint32_t i = 0;
7555
7556         if (info->length == 0)
7557                 return -EINVAL;
7558
7559         for (i = info->offset; i < info->offset + info->length; i++) {
7560                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7561                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7562                 else
7563                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7564
7565                 if (status != 0)
7566                         return -EIO;
7567
7568                 data[i - info->offset] = databyte;
7569         }
7570
7571         return 0;
7572 }
7573
7574 uint16_t
7575 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7576         switch (mac_type) {
7577         case ixgbe_mac_X550:
7578         case ixgbe_mac_X550EM_x:
7579         case ixgbe_mac_X550EM_a:
7580                 return ETH_RSS_RETA_SIZE_512;
7581         case ixgbe_mac_X550_vf:
7582         case ixgbe_mac_X550EM_x_vf:
7583         case ixgbe_mac_X550EM_a_vf:
7584                 return ETH_RSS_RETA_SIZE_64;
7585         case ixgbe_mac_X540_vf:
7586         case ixgbe_mac_82599_vf:
7587                 return 0;
7588         default:
7589                 return ETH_RSS_RETA_SIZE_128;
7590         }
7591 }
7592
7593 uint32_t
7594 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7595         switch (mac_type) {
7596         case ixgbe_mac_X550:
7597         case ixgbe_mac_X550EM_x:
7598         case ixgbe_mac_X550EM_a:
7599                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7600                         return IXGBE_RETA(reta_idx >> 2);
7601                 else
7602                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7603         case ixgbe_mac_X550_vf:
7604         case ixgbe_mac_X550EM_x_vf:
7605         case ixgbe_mac_X550EM_a_vf:
7606                 return IXGBE_VFRETA(reta_idx >> 2);
7607         default:
7608                 return IXGBE_RETA(reta_idx >> 2);
7609         }
7610 }
7611
7612 uint32_t
7613 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7614         switch (mac_type) {
7615         case ixgbe_mac_X550_vf:
7616         case ixgbe_mac_X550EM_x_vf:
7617         case ixgbe_mac_X550EM_a_vf:
7618                 return IXGBE_VFMRQC;
7619         default:
7620                 return IXGBE_MRQC;
7621         }
7622 }
7623
7624 uint32_t
7625 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7626         switch (mac_type) {
7627         case ixgbe_mac_X550_vf:
7628         case ixgbe_mac_X550EM_x_vf:
7629         case ixgbe_mac_X550EM_a_vf:
7630                 return IXGBE_VFRSSRK(i);
7631         default:
7632                 return IXGBE_RSSRK(i);
7633         }
7634 }
7635
7636 bool
7637 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7638         switch (mac_type) {
7639         case ixgbe_mac_82599_vf:
7640         case ixgbe_mac_X540_vf:
7641                 return 0;
7642         default:
7643                 return 1;
7644         }
7645 }
7646
7647 static int
7648 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7649                         struct rte_eth_dcb_info *dcb_info)
7650 {
7651         struct ixgbe_dcb_config *dcb_config =
7652                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7653         struct ixgbe_dcb_tc_config *tc;
7654         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7655         uint8_t nb_tcs;
7656         uint8_t i, j;
7657
7658         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7659                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7660         else
7661                 dcb_info->nb_tcs = 1;
7662
7663         tc_queue = &dcb_info->tc_queue;
7664         nb_tcs = dcb_info->nb_tcs;
7665
7666         if (dcb_config->vt_mode) { /* vt is enabled*/
7667                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7668                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7669                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7670                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7671                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7672                         for (j = 0; j < nb_tcs; j++) {
7673                                 tc_queue->tc_rxq[0][j].base = j;
7674                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7675                                 tc_queue->tc_txq[0][j].base = j;
7676                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7677                         }
7678                 } else {
7679                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7680                                 for (j = 0; j < nb_tcs; j++) {
7681                                         tc_queue->tc_rxq[i][j].base =
7682                                                 i * nb_tcs + j;
7683                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7684                                         tc_queue->tc_txq[i][j].base =
7685                                                 i * nb_tcs + j;
7686                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7687                                 }
7688                         }
7689                 }
7690         } else { /* vt is disabled*/
7691                 struct rte_eth_dcb_rx_conf *rx_conf =
7692                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7693                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7694                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7695                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7696                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7697                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7698                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7699                         }
7700                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7701                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7702                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7703                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7704                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7705                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7706                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7707                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7708                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7709                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7710                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7711                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7712                         }
7713                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7714                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7715                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7716                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7717                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7718                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7719                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7720                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7721                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7722                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7723                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7724                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7725                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7726                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7727                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7728                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7729                 }
7730         }
7731         for (i = 0; i < dcb_info->nb_tcs; i++) {
7732                 tc = &dcb_config->tc_config[i];
7733                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7734         }
7735         return 0;
7736 }
7737
7738 /* Update e-tag ether type */
7739 static int
7740 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7741                             uint16_t ether_type)
7742 {
7743         uint32_t etag_etype;
7744
7745         if (hw->mac.type != ixgbe_mac_X550 &&
7746             hw->mac.type != ixgbe_mac_X550EM_x &&
7747             hw->mac.type != ixgbe_mac_X550EM_a) {
7748                 return -ENOTSUP;
7749         }
7750
7751         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7752         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7753         etag_etype |= ether_type;
7754         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7755         IXGBE_WRITE_FLUSH(hw);
7756
7757         return 0;
7758 }
7759
7760 /* Config l2 tunnel ether type */
7761 static int
7762 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7763                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7764 {
7765         int ret = 0;
7766         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7767         struct ixgbe_l2_tn_info *l2_tn_info =
7768                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7769
7770         if (l2_tunnel == NULL)
7771                 return -EINVAL;
7772
7773         switch (l2_tunnel->l2_tunnel_type) {
7774         case RTE_L2_TUNNEL_TYPE_E_TAG:
7775                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7776                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7777                 break;
7778         default:
7779                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7780                 ret = -EINVAL;
7781                 break;
7782         }
7783
7784         return ret;
7785 }
7786
7787 /* Enable e-tag tunnel */
7788 static int
7789 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7790 {
7791         uint32_t etag_etype;
7792
7793         if (hw->mac.type != ixgbe_mac_X550 &&
7794             hw->mac.type != ixgbe_mac_X550EM_x &&
7795             hw->mac.type != ixgbe_mac_X550EM_a) {
7796                 return -ENOTSUP;
7797         }
7798
7799         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7800         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7801         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7802         IXGBE_WRITE_FLUSH(hw);
7803
7804         return 0;
7805 }
7806
7807 /* Enable l2 tunnel */
7808 static int
7809 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7810                            enum rte_eth_tunnel_type l2_tunnel_type)
7811 {
7812         int ret = 0;
7813         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7814         struct ixgbe_l2_tn_info *l2_tn_info =
7815                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7816
7817         switch (l2_tunnel_type) {
7818         case RTE_L2_TUNNEL_TYPE_E_TAG:
7819                 l2_tn_info->e_tag_en = TRUE;
7820                 ret = ixgbe_e_tag_enable(hw);
7821                 break;
7822         default:
7823                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7824                 ret = -EINVAL;
7825                 break;
7826         }
7827
7828         return ret;
7829 }
7830
7831 /* Disable e-tag tunnel */
7832 static int
7833 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7834 {
7835         uint32_t etag_etype;
7836
7837         if (hw->mac.type != ixgbe_mac_X550 &&
7838             hw->mac.type != ixgbe_mac_X550EM_x &&
7839             hw->mac.type != ixgbe_mac_X550EM_a) {
7840                 return -ENOTSUP;
7841         }
7842
7843         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7844         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7845         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7846         IXGBE_WRITE_FLUSH(hw);
7847
7848         return 0;
7849 }
7850
7851 /* Disable l2 tunnel */
7852 static int
7853 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7854                             enum rte_eth_tunnel_type l2_tunnel_type)
7855 {
7856         int ret = 0;
7857         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7858         struct ixgbe_l2_tn_info *l2_tn_info =
7859                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7860
7861         switch (l2_tunnel_type) {
7862         case RTE_L2_TUNNEL_TYPE_E_TAG:
7863                 l2_tn_info->e_tag_en = FALSE;
7864                 ret = ixgbe_e_tag_disable(hw);
7865                 break;
7866         default:
7867                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7868                 ret = -EINVAL;
7869                 break;
7870         }
7871
7872         return ret;
7873 }
7874
7875 static int
7876 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7877                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7878 {
7879         int ret = 0;
7880         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7881         uint32_t i, rar_entries;
7882         uint32_t rar_low, rar_high;
7883
7884         if (hw->mac.type != ixgbe_mac_X550 &&
7885             hw->mac.type != ixgbe_mac_X550EM_x &&
7886             hw->mac.type != ixgbe_mac_X550EM_a) {
7887                 return -ENOTSUP;
7888         }
7889
7890         rar_entries = ixgbe_get_num_rx_addrs(hw);
7891
7892         for (i = 1; i < rar_entries; i++) {
7893                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7894                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7895                 if ((rar_high & IXGBE_RAH_AV) &&
7896                     (rar_high & IXGBE_RAH_ADTYPE) &&
7897                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7898                      l2_tunnel->tunnel_id)) {
7899                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7900                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7901
7902                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7903
7904                         return ret;
7905                 }
7906         }
7907
7908         return ret;
7909 }
7910
7911 static int
7912 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7913                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7914 {
7915         int ret = 0;
7916         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7917         uint32_t i, rar_entries;
7918         uint32_t rar_low, rar_high;
7919
7920         if (hw->mac.type != ixgbe_mac_X550 &&
7921             hw->mac.type != ixgbe_mac_X550EM_x &&
7922             hw->mac.type != ixgbe_mac_X550EM_a) {
7923                 return -ENOTSUP;
7924         }
7925
7926         /* One entry for one tunnel. Try to remove potential existing entry. */
7927         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7928
7929         rar_entries = ixgbe_get_num_rx_addrs(hw);
7930
7931         for (i = 1; i < rar_entries; i++) {
7932                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7933                 if (rar_high & IXGBE_RAH_AV) {
7934                         continue;
7935                 } else {
7936                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7937                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7938                         rar_low = l2_tunnel->tunnel_id;
7939
7940                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7941                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7942
7943                         return ret;
7944                 }
7945         }
7946
7947         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7948                      " Please remove a rule before adding a new one.");
7949         return -EINVAL;
7950 }
7951
7952 static inline struct ixgbe_l2_tn_filter *
7953 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7954                           struct ixgbe_l2_tn_key *key)
7955 {
7956         int ret;
7957
7958         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7959         if (ret < 0)
7960                 return NULL;
7961
7962         return l2_tn_info->hash_map[ret];
7963 }
7964
7965 static inline int
7966 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7967                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7968 {
7969         int ret;
7970
7971         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7972                                &l2_tn_filter->key);
7973
7974         if (ret < 0) {
7975                 PMD_DRV_LOG(ERR,
7976                             "Failed to insert L2 tunnel filter"
7977                             " to hash table %d!",
7978                             ret);
7979                 return ret;
7980         }
7981
7982         l2_tn_info->hash_map[ret] = l2_tn_filter;
7983
7984         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7985
7986         return 0;
7987 }
7988
7989 static inline int
7990 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7991                           struct ixgbe_l2_tn_key *key)
7992 {
7993         int ret;
7994         struct ixgbe_l2_tn_filter *l2_tn_filter;
7995
7996         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7997
7998         if (ret < 0) {
7999                 PMD_DRV_LOG(ERR,
8000                             "No such L2 tunnel filter to delete %d!",
8001                             ret);
8002                 return ret;
8003         }
8004
8005         l2_tn_filter = l2_tn_info->hash_map[ret];
8006         l2_tn_info->hash_map[ret] = NULL;
8007
8008         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8009         rte_free(l2_tn_filter);
8010
8011         return 0;
8012 }
8013
8014 /* Add l2 tunnel filter */
8015 int
8016 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
8017                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
8018                                bool restore)
8019 {
8020         int ret;
8021         struct ixgbe_l2_tn_info *l2_tn_info =
8022                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8023         struct ixgbe_l2_tn_key key;
8024         struct ixgbe_l2_tn_filter *node;
8025
8026         if (!restore) {
8027                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8028                 key.tn_id = l2_tunnel->tunnel_id;
8029
8030                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
8031
8032                 if (node) {
8033                         PMD_DRV_LOG(ERR,
8034                                     "The L2 tunnel filter already exists!");
8035                         return -EINVAL;
8036                 }
8037
8038                 node = rte_zmalloc("ixgbe_l2_tn",
8039                                    sizeof(struct ixgbe_l2_tn_filter),
8040                                    0);
8041                 if (!node)
8042                         return -ENOMEM;
8043
8044                 rte_memcpy(&node->key,
8045                                  &key,
8046                                  sizeof(struct ixgbe_l2_tn_key));
8047                 node->pool = l2_tunnel->pool;
8048                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
8049                 if (ret < 0) {
8050                         rte_free(node);
8051                         return ret;
8052                 }
8053         }
8054
8055         switch (l2_tunnel->l2_tunnel_type) {
8056         case RTE_L2_TUNNEL_TYPE_E_TAG:
8057                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
8058                 break;
8059         default:
8060                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8061                 ret = -EINVAL;
8062                 break;
8063         }
8064
8065         if ((!restore) && (ret < 0))
8066                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8067
8068         return ret;
8069 }
8070
8071 /* Delete l2 tunnel filter */
8072 int
8073 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
8074                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
8075 {
8076         int ret;
8077         struct ixgbe_l2_tn_info *l2_tn_info =
8078                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8079         struct ixgbe_l2_tn_key key;
8080
8081         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8082         key.tn_id = l2_tunnel->tunnel_id;
8083         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8084         if (ret < 0)
8085                 return ret;
8086
8087         switch (l2_tunnel->l2_tunnel_type) {
8088         case RTE_L2_TUNNEL_TYPE_E_TAG:
8089                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
8090                 break;
8091         default:
8092                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8093                 ret = -EINVAL;
8094                 break;
8095         }
8096
8097         return ret;
8098 }
8099
8100 /**
8101  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8102  * @dev: pointer to rte_eth_dev structure
8103  * @filter_op:operation will be taken.
8104  * @arg: a pointer to specific structure corresponding to the filter_op
8105  */
8106 static int
8107 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8108                                   enum rte_filter_op filter_op,
8109                                   void *arg)
8110 {
8111         int ret;
8112
8113         if (filter_op == RTE_ETH_FILTER_NOP)
8114                 return 0;
8115
8116         if (arg == NULL) {
8117                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8118                             filter_op);
8119                 return -EINVAL;
8120         }
8121
8122         switch (filter_op) {
8123         case RTE_ETH_FILTER_ADD:
8124                 ret = ixgbe_dev_l2_tunnel_filter_add
8125                         (dev,
8126                          (struct rte_eth_l2_tunnel_conf *)arg,
8127                          FALSE);
8128                 break;
8129         case RTE_ETH_FILTER_DELETE:
8130                 ret = ixgbe_dev_l2_tunnel_filter_del
8131                         (dev,
8132                          (struct rte_eth_l2_tunnel_conf *)arg);
8133                 break;
8134         default:
8135                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8136                 ret = -EINVAL;
8137                 break;
8138         }
8139         return ret;
8140 }
8141
8142 static int
8143 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8144 {
8145         int ret = 0;
8146         uint32_t ctrl;
8147         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8148
8149         if (hw->mac.type != ixgbe_mac_X550 &&
8150             hw->mac.type != ixgbe_mac_X550EM_x &&
8151             hw->mac.type != ixgbe_mac_X550EM_a) {
8152                 return -ENOTSUP;
8153         }
8154
8155         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8156         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8157         if (en)
8158                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8159         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8160
8161         return ret;
8162 }
8163
8164 /* Enable l2 tunnel forwarding */
8165 static int
8166 ixgbe_dev_l2_tunnel_forwarding_enable
8167         (struct rte_eth_dev *dev,
8168          enum rte_eth_tunnel_type l2_tunnel_type)
8169 {
8170         struct ixgbe_l2_tn_info *l2_tn_info =
8171                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8172         int ret = 0;
8173
8174         switch (l2_tunnel_type) {
8175         case RTE_L2_TUNNEL_TYPE_E_TAG:
8176                 l2_tn_info->e_tag_fwd_en = TRUE;
8177                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8178                 break;
8179         default:
8180                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8181                 ret = -EINVAL;
8182                 break;
8183         }
8184
8185         return ret;
8186 }
8187
8188 /* Disable l2 tunnel forwarding */
8189 static int
8190 ixgbe_dev_l2_tunnel_forwarding_disable
8191         (struct rte_eth_dev *dev,
8192          enum rte_eth_tunnel_type l2_tunnel_type)
8193 {
8194         struct ixgbe_l2_tn_info *l2_tn_info =
8195                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8196         int ret = 0;
8197
8198         switch (l2_tunnel_type) {
8199         case RTE_L2_TUNNEL_TYPE_E_TAG:
8200                 l2_tn_info->e_tag_fwd_en = FALSE;
8201                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8202                 break;
8203         default:
8204                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8205                 ret = -EINVAL;
8206                 break;
8207         }
8208
8209         return ret;
8210 }
8211
8212 static int
8213 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8214                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
8215                              bool en)
8216 {
8217         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8218         int ret = 0;
8219         uint32_t vmtir, vmvir;
8220         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8221
8222         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8223                 PMD_DRV_LOG(ERR,
8224                             "VF id %u should be less than %u",
8225                             l2_tunnel->vf_id,
8226                             pci_dev->max_vfs);
8227                 return -EINVAL;
8228         }
8229
8230         if (hw->mac.type != ixgbe_mac_X550 &&
8231             hw->mac.type != ixgbe_mac_X550EM_x &&
8232             hw->mac.type != ixgbe_mac_X550EM_a) {
8233                 return -ENOTSUP;
8234         }
8235
8236         if (en)
8237                 vmtir = l2_tunnel->tunnel_id;
8238         else
8239                 vmtir = 0;
8240
8241         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8242
8243         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8244         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8245         if (en)
8246                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8247         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8248
8249         return ret;
8250 }
8251
8252 /* Enable l2 tunnel tag insertion */
8253 static int
8254 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8255                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8256 {
8257         int ret = 0;
8258
8259         switch (l2_tunnel->l2_tunnel_type) {
8260         case RTE_L2_TUNNEL_TYPE_E_TAG:
8261                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8262                 break;
8263         default:
8264                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8265                 ret = -EINVAL;
8266                 break;
8267         }
8268
8269         return ret;
8270 }
8271
8272 /* Disable l2 tunnel tag insertion */
8273 static int
8274 ixgbe_dev_l2_tunnel_insertion_disable
8275         (struct rte_eth_dev *dev,
8276          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8277 {
8278         int ret = 0;
8279
8280         switch (l2_tunnel->l2_tunnel_type) {
8281         case RTE_L2_TUNNEL_TYPE_E_TAG:
8282                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8283                 break;
8284         default:
8285                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8286                 ret = -EINVAL;
8287                 break;
8288         }
8289
8290         return ret;
8291 }
8292
8293 static int
8294 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8295                              bool en)
8296 {
8297         int ret = 0;
8298         uint32_t qde;
8299         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8300
8301         if (hw->mac.type != ixgbe_mac_X550 &&
8302             hw->mac.type != ixgbe_mac_X550EM_x &&
8303             hw->mac.type != ixgbe_mac_X550EM_a) {
8304                 return -ENOTSUP;
8305         }
8306
8307         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8308         if (en)
8309                 qde |= IXGBE_QDE_STRIP_TAG;
8310         else
8311                 qde &= ~IXGBE_QDE_STRIP_TAG;
8312         qde &= ~IXGBE_QDE_READ;
8313         qde |= IXGBE_QDE_WRITE;
8314         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8315
8316         return ret;
8317 }
8318
8319 /* Enable l2 tunnel tag stripping */
8320 static int
8321 ixgbe_dev_l2_tunnel_stripping_enable
8322         (struct rte_eth_dev *dev,
8323          enum rte_eth_tunnel_type l2_tunnel_type)
8324 {
8325         int ret = 0;
8326
8327         switch (l2_tunnel_type) {
8328         case RTE_L2_TUNNEL_TYPE_E_TAG:
8329                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8330                 break;
8331         default:
8332                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8333                 ret = -EINVAL;
8334                 break;
8335         }
8336
8337         return ret;
8338 }
8339
8340 /* Disable l2 tunnel tag stripping */
8341 static int
8342 ixgbe_dev_l2_tunnel_stripping_disable
8343         (struct rte_eth_dev *dev,
8344          enum rte_eth_tunnel_type l2_tunnel_type)
8345 {
8346         int ret = 0;
8347
8348         switch (l2_tunnel_type) {
8349         case RTE_L2_TUNNEL_TYPE_E_TAG:
8350                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8351                 break;
8352         default:
8353                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8354                 ret = -EINVAL;
8355                 break;
8356         }
8357
8358         return ret;
8359 }
8360
8361 /* Enable/disable l2 tunnel offload functions */
8362 static int
8363 ixgbe_dev_l2_tunnel_offload_set
8364         (struct rte_eth_dev *dev,
8365          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8366          uint32_t mask,
8367          uint8_t en)
8368 {
8369         int ret = 0;
8370
8371         if (l2_tunnel == NULL)
8372                 return -EINVAL;
8373
8374         ret = -EINVAL;
8375         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8376                 if (en)
8377                         ret = ixgbe_dev_l2_tunnel_enable(
8378                                 dev,
8379                                 l2_tunnel->l2_tunnel_type);
8380                 else
8381                         ret = ixgbe_dev_l2_tunnel_disable(
8382                                 dev,
8383                                 l2_tunnel->l2_tunnel_type);
8384         }
8385
8386         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8387                 if (en)
8388                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8389                                 dev,
8390                                 l2_tunnel);
8391                 else
8392                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8393                                 dev,
8394                                 l2_tunnel);
8395         }
8396
8397         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8398                 if (en)
8399                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8400                                 dev,
8401                                 l2_tunnel->l2_tunnel_type);
8402                 else
8403                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8404                                 dev,
8405                                 l2_tunnel->l2_tunnel_type);
8406         }
8407
8408         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8409                 if (en)
8410                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8411                                 dev,
8412                                 l2_tunnel->l2_tunnel_type);
8413                 else
8414                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8415                                 dev,
8416                                 l2_tunnel->l2_tunnel_type);
8417         }
8418
8419         return ret;
8420 }
8421
8422 static int
8423 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8424                         uint16_t port)
8425 {
8426         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8427         IXGBE_WRITE_FLUSH(hw);
8428
8429         return 0;
8430 }
8431
8432 /* There's only one register for VxLAN UDP port.
8433  * So, we cannot add several ports. Will update it.
8434  */
8435 static int
8436 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8437                      uint16_t port)
8438 {
8439         if (port == 0) {
8440                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8441                 return -EINVAL;
8442         }
8443
8444         return ixgbe_update_vxlan_port(hw, port);
8445 }
8446
8447 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8448  * UDP port, it must have a value.
8449  * So, will reset it to the original value 0.
8450  */
8451 static int
8452 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8453                      uint16_t port)
8454 {
8455         uint16_t cur_port;
8456
8457         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8458
8459         if (cur_port != port) {
8460                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8461                 return -EINVAL;
8462         }
8463
8464         return ixgbe_update_vxlan_port(hw, 0);
8465 }
8466
8467 /* Add UDP tunneling port */
8468 static int
8469 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8470                               struct rte_eth_udp_tunnel *udp_tunnel)
8471 {
8472         int ret = 0;
8473         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8474
8475         if (hw->mac.type != ixgbe_mac_X550 &&
8476             hw->mac.type != ixgbe_mac_X550EM_x &&
8477             hw->mac.type != ixgbe_mac_X550EM_a) {
8478                 return -ENOTSUP;
8479         }
8480
8481         if (udp_tunnel == NULL)
8482                 return -EINVAL;
8483
8484         switch (udp_tunnel->prot_type) {
8485         case RTE_TUNNEL_TYPE_VXLAN:
8486                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8487                 break;
8488
8489         case RTE_TUNNEL_TYPE_GENEVE:
8490         case RTE_TUNNEL_TYPE_TEREDO:
8491                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8492                 ret = -EINVAL;
8493                 break;
8494
8495         default:
8496                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8497                 ret = -EINVAL;
8498                 break;
8499         }
8500
8501         return ret;
8502 }
8503
8504 /* Remove UDP tunneling port */
8505 static int
8506 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8507                               struct rte_eth_udp_tunnel *udp_tunnel)
8508 {
8509         int ret = 0;
8510         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8511
8512         if (hw->mac.type != ixgbe_mac_X550 &&
8513             hw->mac.type != ixgbe_mac_X550EM_x &&
8514             hw->mac.type != ixgbe_mac_X550EM_a) {
8515                 return -ENOTSUP;
8516         }
8517
8518         if (udp_tunnel == NULL)
8519                 return -EINVAL;
8520
8521         switch (udp_tunnel->prot_type) {
8522         case RTE_TUNNEL_TYPE_VXLAN:
8523                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8524                 break;
8525         case RTE_TUNNEL_TYPE_GENEVE:
8526         case RTE_TUNNEL_TYPE_TEREDO:
8527                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8528                 ret = -EINVAL;
8529                 break;
8530         default:
8531                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8532                 ret = -EINVAL;
8533                 break;
8534         }
8535
8536         return ret;
8537 }
8538
8539 static int
8540 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8541 {
8542         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8543         int ret;
8544
8545         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8546         case IXGBE_SUCCESS:
8547                 ret = 0;
8548                 break;
8549         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8550                 ret = -ENOTSUP;
8551                 break;
8552         default:
8553                 ret = -EAGAIN;
8554                 break;
8555         }
8556
8557         return ret;
8558 }
8559
8560 static int
8561 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8562 {
8563         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8564         int ret;
8565
8566         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8567         case IXGBE_SUCCESS:
8568                 ret = 0;
8569                 break;
8570         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8571                 ret = -ENOTSUP;
8572                 break;
8573         default:
8574                 ret = -EAGAIN;
8575                 break;
8576         }
8577
8578         return ret;
8579 }
8580
8581 static int
8582 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8583 {
8584         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8585         int ret;
8586         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8587
8588         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8589         case IXGBE_SUCCESS:
8590                 ret = 0;
8591                 break;
8592         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8593                 ret = -ENOTSUP;
8594                 break;
8595         default:
8596                 ret = -EAGAIN;
8597                 break;
8598         }
8599
8600         return ret;
8601 }
8602
8603 static int
8604 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8605 {
8606         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8607         int ret;
8608
8609         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8610         case IXGBE_SUCCESS:
8611                 ret = 0;
8612                 break;
8613         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8614                 ret = -ENOTSUP;
8615                 break;
8616         default:
8617                 ret = -EAGAIN;
8618                 break;
8619         }
8620
8621         return ret;
8622 }
8623
8624 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8625 {
8626         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8627         u32 in_msg = 0;
8628
8629         /* peek the message first */
8630         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8631
8632         /* PF reset VF event */
8633         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8634                 /* dummy mbx read to ack pf */
8635                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8636                         return;
8637                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8638                                               NULL);
8639         }
8640 }
8641
8642 static int
8643 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8644 {
8645         uint32_t eicr;
8646         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8647         struct ixgbe_interrupt *intr =
8648                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8649         ixgbevf_intr_disable(dev);
8650
8651         /* read-on-clear nic registers here */
8652         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8653         intr->flags = 0;
8654
8655         /* only one misc vector supported - mailbox */
8656         eicr &= IXGBE_VTEICR_MASK;
8657         if (eicr == IXGBE_MISC_VEC_ID)
8658                 intr->flags |= IXGBE_FLAG_MAILBOX;
8659
8660         return 0;
8661 }
8662
8663 static int
8664 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8665 {
8666         struct ixgbe_interrupt *intr =
8667                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8668
8669         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8670                 ixgbevf_mbx_process(dev);
8671                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8672         }
8673
8674         ixgbevf_intr_enable(dev);
8675
8676         return 0;
8677 }
8678
8679 static void
8680 ixgbevf_dev_interrupt_handler(void *param)
8681 {
8682         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8683
8684         ixgbevf_dev_interrupt_get_status(dev);
8685         ixgbevf_dev_interrupt_action(dev);
8686 }
8687
8688 /**
8689  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8690  *  @hw: pointer to hardware structure
8691  *
8692  *  Stops the transmit data path and waits for the HW to internally empty
8693  *  the Tx security block
8694  **/
8695 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8696 {
8697 #define IXGBE_MAX_SECTX_POLL 40
8698
8699         int i;
8700         int sectxreg;
8701
8702         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8703         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8704         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8705         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8706                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8707                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8708                         break;
8709                 /* Use interrupt-safe sleep just in case */
8710                 usec_delay(1000);
8711         }
8712
8713         /* For informational purposes only */
8714         if (i >= IXGBE_MAX_SECTX_POLL)
8715                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8716                          "path fully disabled.  Continuing with init.");
8717
8718         return IXGBE_SUCCESS;
8719 }
8720
8721 /**
8722  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8723  *  @hw: pointer to hardware structure
8724  *
8725  *  Enables the transmit data path.
8726  **/
8727 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8728 {
8729         uint32_t sectxreg;
8730
8731         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8732         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8733         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8734         IXGBE_WRITE_FLUSH(hw);
8735
8736         return IXGBE_SUCCESS;
8737 }
8738
8739 /* restore n-tuple filter */
8740 static inline void
8741 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8742 {
8743         struct ixgbe_filter_info *filter_info =
8744                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8745         struct ixgbe_5tuple_filter *node;
8746
8747         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8748                 ixgbe_inject_5tuple_filter(dev, node);
8749         }
8750 }
8751
8752 /* restore ethernet type filter */
8753 static inline void
8754 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8755 {
8756         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8757         struct ixgbe_filter_info *filter_info =
8758                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8759         int i;
8760
8761         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8762                 if (filter_info->ethertype_mask & (1 << i)) {
8763                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8764                                         filter_info->ethertype_filters[i].etqf);
8765                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8766                                         filter_info->ethertype_filters[i].etqs);
8767                         IXGBE_WRITE_FLUSH(hw);
8768                 }
8769         }
8770 }
8771
8772 /* restore SYN filter */
8773 static inline void
8774 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8775 {
8776         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8777         struct ixgbe_filter_info *filter_info =
8778                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8779         uint32_t synqf;
8780
8781         synqf = filter_info->syn_info;
8782
8783         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8784                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8785                 IXGBE_WRITE_FLUSH(hw);
8786         }
8787 }
8788
8789 /* restore L2 tunnel filter */
8790 static inline void
8791 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8792 {
8793         struct ixgbe_l2_tn_info *l2_tn_info =
8794                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8795         struct ixgbe_l2_tn_filter *node;
8796         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8797
8798         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8799                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8800                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8801                 l2_tn_conf.pool           = node->pool;
8802                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8803         }
8804 }
8805
8806 /* restore rss filter */
8807 static inline void
8808 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8809 {
8810         struct ixgbe_filter_info *filter_info =
8811                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8812
8813         if (filter_info->rss_info.conf.queue_num)
8814                 ixgbe_config_rss_filter(dev,
8815                         &filter_info->rss_info, TRUE);
8816 }
8817
8818 static int
8819 ixgbe_filter_restore(struct rte_eth_dev *dev)
8820 {
8821         ixgbe_ntuple_filter_restore(dev);
8822         ixgbe_ethertype_filter_restore(dev);
8823         ixgbe_syn_filter_restore(dev);
8824         ixgbe_fdir_filter_restore(dev);
8825         ixgbe_l2_tn_filter_restore(dev);
8826         ixgbe_rss_filter_restore(dev);
8827
8828         return 0;
8829 }
8830
8831 static void
8832 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8833 {
8834         struct ixgbe_l2_tn_info *l2_tn_info =
8835                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8836         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8837
8838         if (l2_tn_info->e_tag_en)
8839                 (void)ixgbe_e_tag_enable(hw);
8840
8841         if (l2_tn_info->e_tag_fwd_en)
8842                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8843
8844         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8845 }
8846
8847 /* remove all the n-tuple filters */
8848 void
8849 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8850 {
8851         struct ixgbe_filter_info *filter_info =
8852                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8853         struct ixgbe_5tuple_filter *p_5tuple;
8854
8855         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8856                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8857 }
8858
8859 /* remove all the ether type filters */
8860 void
8861 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8862 {
8863         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8864         struct ixgbe_filter_info *filter_info =
8865                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8866         int i;
8867
8868         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8869                 if (filter_info->ethertype_mask & (1 << i) &&
8870                     !filter_info->ethertype_filters[i].conf) {
8871                         (void)ixgbe_ethertype_filter_remove(filter_info,
8872                                                             (uint8_t)i);
8873                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8874                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8875                         IXGBE_WRITE_FLUSH(hw);
8876                 }
8877         }
8878 }
8879
8880 /* remove the SYN filter */
8881 void
8882 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8883 {
8884         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8885         struct ixgbe_filter_info *filter_info =
8886                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8887
8888         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8889                 filter_info->syn_info = 0;
8890
8891                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8892                 IXGBE_WRITE_FLUSH(hw);
8893         }
8894 }
8895
8896 /* remove all the L2 tunnel filters */
8897 int
8898 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8899 {
8900         struct ixgbe_l2_tn_info *l2_tn_info =
8901                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8902         struct ixgbe_l2_tn_filter *l2_tn_filter;
8903         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8904         int ret = 0;
8905
8906         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8907                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8908                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8909                 l2_tn_conf.pool           = l2_tn_filter->pool;
8910                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8911                 if (ret < 0)
8912                         return ret;
8913         }
8914
8915         return 0;
8916 }
8917
8918 void
8919 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8920                                 struct ixgbe_macsec_setting *macsec_setting)
8921 {
8922         struct ixgbe_macsec_setting *macsec =
8923                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8924
8925         macsec->offload_en = macsec_setting->offload_en;
8926         macsec->encrypt_en = macsec_setting->encrypt_en;
8927         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8928 }
8929
8930 void
8931 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8932 {
8933         struct ixgbe_macsec_setting *macsec =
8934                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8935
8936         macsec->offload_en = 0;
8937         macsec->encrypt_en = 0;
8938         macsec->replayprotect_en = 0;
8939 }
8940
8941 void
8942 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8943                                 struct ixgbe_macsec_setting *macsec_setting)
8944 {
8945         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8946         uint32_t ctrl;
8947         uint8_t en = macsec_setting->encrypt_en;
8948         uint8_t rp = macsec_setting->replayprotect_en;
8949
8950         /**
8951          * Workaround:
8952          * As no ixgbe_disable_sec_rx_path equivalent is
8953          * implemented for tx in the base code, and we are
8954          * not allowed to modify the base code in DPDK, so
8955          * just call the hand-written one directly for now.
8956          * The hardware support has been checked by
8957          * ixgbe_disable_sec_rx_path().
8958          */
8959         ixgbe_disable_sec_tx_path_generic(hw);
8960
8961         /* Enable Ethernet CRC (required by MACsec offload) */
8962         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8963         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8964         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8965
8966         /* Enable the TX and RX crypto engines */
8967         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8968         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8969         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8970
8971         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8972         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8973         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8974
8975         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8976         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8977         ctrl |= 0x3;
8978         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8979
8980         /* Enable SA lookup */
8981         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8982         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8983         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8984                      IXGBE_LSECTXCTRL_AUTH;
8985         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8986         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8987         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8988         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8989
8990         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8991         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8992         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8993         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8994         if (rp)
8995                 ctrl |= IXGBE_LSECRXCTRL_RP;
8996         else
8997                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8998         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8999
9000         /* Start the data paths */
9001         ixgbe_enable_sec_rx_path(hw);
9002         /**
9003          * Workaround:
9004          * As no ixgbe_enable_sec_rx_path equivalent is
9005          * implemented for tx in the base code, and we are
9006          * not allowed to modify the base code in DPDK, so
9007          * just call the hand-written one directly for now.
9008          */
9009         ixgbe_enable_sec_tx_path_generic(hw);
9010 }
9011
9012 void
9013 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
9014 {
9015         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9016         uint32_t ctrl;
9017
9018         /**
9019          * Workaround:
9020          * As no ixgbe_disable_sec_rx_path equivalent is
9021          * implemented for tx in the base code, and we are
9022          * not allowed to modify the base code in DPDK, so
9023          * just call the hand-written one directly for now.
9024          * The hardware support has been checked by
9025          * ixgbe_disable_sec_rx_path().
9026          */
9027         ixgbe_disable_sec_tx_path_generic(hw);
9028
9029         /* Disable the TX and RX crypto engines */
9030         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9031         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
9032         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9033
9034         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9035         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
9036         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9037
9038         /* Disable SA lookup */
9039         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9040         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9041         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
9042         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9043
9044         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9045         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9046         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
9047         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9048
9049         /* Start the data paths */
9050         ixgbe_enable_sec_rx_path(hw);
9051         /**
9052          * Workaround:
9053          * As no ixgbe_enable_sec_rx_path equivalent is
9054          * implemented for tx in the base code, and we are
9055          * not allowed to modify the base code in DPDK, so
9056          * just call the hand-written one directly for now.
9057          */
9058         ixgbe_enable_sec_tx_path_generic(hw);
9059 }
9060
9061 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
9062 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
9063 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
9064 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
9065 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
9066 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
9067 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
9068                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
9069
9070 RTE_INIT(ixgbe_init_log)
9071 {
9072         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
9073         if (ixgbe_logtype_init >= 0)
9074                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
9075         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
9076         if (ixgbe_logtype_driver >= 0)
9077                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
9078 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
9079         ixgbe_logtype_rx = rte_log_register("pmd.net.ixgbe.rx");
9080         if (ixgbe_logtype_rx >= 0)
9081                 rte_log_set_level(ixgbe_logtype_rx, RTE_LOG_DEBUG);
9082 #endif
9083
9084 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
9085         ixgbe_logtype_tx = rte_log_register("pmd.net.ixgbe.tx");
9086         if (ixgbe_logtype_tx >= 0)
9087                 rte_log_set_level(ixgbe_logtype_tx, RTE_LOG_DEBUG);
9088 #endif
9089
9090 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
9091         ixgbe_logtype_tx_free = rte_log_register("pmd.net.ixgbe.tx_free");
9092         if (ixgbe_logtype_tx_free >= 0)
9093                 rte_log_set_level(ixgbe_logtype_tx_free, RTE_LOG_DEBUG);
9094 #endif
9095 }