drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_eal.h>
  27 #include <rte_alarm.h>
  28 #include <rte_ether.h>
  29 #include <rte_ethdev_driver.h>
  30 #include <rte_ethdev_pci.h>
  31 #include <rte_malloc.h>
  32 #include <rte_random.h>
  33 #include <rte_dev.h>
  34 #include <rte_hash_crc.h>
  35 #ifdef RTE_LIBRTE_SECURITY
  36 #include <rte_security_driver.h>
  37 #endif
  38
  39 #include "ixgbe_logs.h"
  40 #include "base/ixgbe_api.h"
  41 #include "base/ixgbe_vf.h"
  42 #include "base/ixgbe_common.h"
  43 #include "ixgbe_ethdev.h"
  44 #include "ixgbe_bypass.h"
  45 #include "ixgbe_rxtx.h"
  46 #include "base/ixgbe_type.h"
  47 #include "base/ixgbe_phy.h"
  48 #include "ixgbe_regs.h"
  49
  50 /*
  51  * High threshold controlling when to start sending XOFF frames. Must be at
  52  * least 8 bytes less than receive packet buffer size. This value is in units
  53  * of 1024 bytes.
  54  */
  55 #define IXGBE_FC_HI    0x80
  56
  57 /*
  58  * Low threshold controlling when to start sending XON frames. This value is
  59  * in units of 1024 bytes.
  60  */
  61 #define IXGBE_FC_LO    0x40
  62
  63 /* Timer value included in XOFF frames. */
  64 #define IXGBE_FC_PAUSE 0x680
  65
  66 /*Default value of Max Rx Queue*/
  67 #define IXGBE_MAX_RX_QUEUE_NUM 128
  68
  69 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  70 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  71 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  72
  73 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  74 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  75 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  76
  77 /*
  78  *  Default values for RX/TX configuration
  79  */
  80 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  81 #define IXGBE_DEFAULT_RX_PTHRESH      8
  82 #define IXGBE_DEFAULT_RX_HTHRESH      8
  83 #define IXGBE_DEFAULT_RX_WTHRESH      0
  84
  85 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  86 #define IXGBE_DEFAULT_TX_PTHRESH      32
  87 #define IXGBE_DEFAULT_TX_HTHRESH      0
  88 #define IXGBE_DEFAULT_TX_WTHRESH      0
  89 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  90
  91 /* Bit shift and mask */
  92 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  93 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  94 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  95 #define IXGBE_8_BIT_MASK   UINT8_MAX
  96
  97 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  98
  99 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 100
 101 /* Additional timesync values. */
 102 #define NSEC_PER_SEC             1000000000L
 103 #define IXGBE_INCVAL_10GB        0x66666666
 104 #define IXGBE_INCVAL_1GB         0x40000000
 105 #define IXGBE_INCVAL_100         0x50000000
 106 #define IXGBE_INCVAL_SHIFT_10GB  28
 107 #define IXGBE_INCVAL_SHIFT_1GB   24
 108 #define IXGBE_INCVAL_SHIFT_100   21
 109 #define IXGBE_INCVAL_SHIFT_82599 7
 110 #define IXGBE_INCPER_SHIFT_82599 24
 111
 112 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 113
 114 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 115 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 116 #define IXGBE_ETAG_ETYPE                       0x00005084
 117 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 118 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 119 #define IXGBE_RAH_ADTYPE                       0x40000000
 120 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 121 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 122 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 123 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 124 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 125 #define IXGBE_VTEICR_MASK                      0x07
 126
 127 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 128 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 129
 130 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 131 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 132 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 133 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 134 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 135 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 136 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 137 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 138 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 139 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 141 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 142 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 143 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 146 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 148 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 149                                 int wait_to_complete);
 150 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 151                                 struct rte_eth_stats *stats);
 152 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 153                                 struct rte_eth_xstat *xstats, unsigned n);
 154 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 155                                   struct rte_eth_xstat *xstats, unsigned n);
 156 static int
 157 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 158                 uint64_t *values, unsigned int n);
 159 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 160 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 161 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 162         struct rte_eth_xstat_name *xstats_names,
 163         unsigned int size);
 164 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 165         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 166 static int ixgbe_dev_xstats_get_names_by_id(
 167         struct rte_eth_dev *dev,
 168         struct rte_eth_xstat_name *xstats_names,
 169         const uint64_t *ids,
 170         unsigned int limit);
 171 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 172                                              uint16_t queue_id,
 173                                              uint8_t stat_idx,
 174                                              uint8_t is_rx);
 175 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 176                                  size_t fw_size);
 177 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 178                                struct rte_eth_dev_info *dev_info);
 179 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 180 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 181                                  struct rte_eth_dev_info *dev_info);
 182 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 183
 184 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 185                 uint16_t vlan_id, int on);
 186 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 187                                enum rte_vlan_type vlan_type,
 188                                uint16_t tpid_id);
 189 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 190                 uint16_t queue, bool on);
 191 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 192                 int on);
 193 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 194                                                   int mask);
 195 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 196 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 197 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 198 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 199 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 200 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 201
 202 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 203 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 204 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 205                                struct rte_eth_fc_conf *fc_conf);
 206 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 207                                struct rte_eth_fc_conf *fc_conf);
 208 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 209                 struct rte_eth_pfc_conf *pfc_conf);
 210 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 211                         struct rte_eth_rss_reta_entry64 *reta_conf,
 212                         uint16_t reta_size);
 213 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 214                         struct rte_eth_rss_reta_entry64 *reta_conf,
 215                         uint16_t reta_size);
 216 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 217 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 218 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 220 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 221 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 222 static void ixgbe_dev_interrupt_handler(void *param);
 223 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 224 static void ixgbe_dev_setup_link_alarm_handler(void *param);
 225
 226 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 227                         struct rte_ether_addr *mac_addr,
 228                         uint32_t index, uint32_t pool);
 229 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 230 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 231                                            struct rte_ether_addr *mac_addr);
 232 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 233 static bool is_device_supported(struct rte_eth_dev *dev,
 234                                 struct rte_pci_driver *drv);
 235
 236 /* For Virtual Function support */
 237 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 238 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 239 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 240 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 241 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 242                                    int wait_to_complete);
 243 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 244 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 245 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 246 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 247 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 248 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 249                 struct rte_eth_stats *stats);
 250 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 251 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 252                 uint16_t vlan_id, int on);
 253 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 254                 uint16_t queue, int on);
 255 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 256 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 257 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 258 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 259                                             uint16_t queue_id);
 260 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 261                                              uint16_t queue_id);
 262 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 263                                  uint8_t queue, uint8_t msix_vector);
 264 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 265 static void ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 266 static void ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 267 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 268 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 269
 270 /* For Eth VMDQ APIs support */
 271 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 272                 rte_ether_addr * mac_addr, uint8_t on);
 273 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 274 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 275                 struct rte_eth_mirror_conf *mirror_conf,
 276                 uint8_t rule_id, uint8_t on);
 277 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 278                 uint8_t rule_id);
 279 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 280                                           uint16_t queue_id);
 281 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 282                                            uint16_t queue_id);
 283 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 284                                uint8_t queue, uint8_t msix_vector);
 285 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 286
 287 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 288                                 struct rte_ether_addr *mac_addr,
 289                                 uint32_t index, uint32_t pool);
 290 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 291 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 292                                              struct rte_ether_addr *mac_addr);
 293 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 294                         struct rte_eth_syn_filter *filter);
 295 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 296                         enum rte_filter_op filter_op,
 297                         void *arg);
 298 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 299                         struct ixgbe_5tuple_filter *filter);
 300 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 301                         struct ixgbe_5tuple_filter *filter);
 302 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 303                                 enum rte_filter_op filter_op,
 304                                 void *arg);
 305 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 306                         struct rte_eth_ntuple_filter *filter);
 307 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 308                                 enum rte_filter_op filter_op,
 309                                 void *arg);
 310 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 311                         struct rte_eth_ethertype_filter *filter);
 312 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 313                      enum rte_filter_type filter_type,
 314                      enum rte_filter_op filter_op,
 315                      void *arg);
 316 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 317
 318 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 319                                       struct rte_ether_addr *mc_addr_set,
 320                                       uint32_t nb_mc_addr);
 321 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 322                                    struct rte_eth_dcb_info *dcb_info);
 323
 324 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 325 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 326                             struct rte_dev_reg_info *regs);
 327 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 328 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 329                                 struct rte_dev_eeprom_info *eeprom);
 330 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 331                                 struct rte_dev_eeprom_info *eeprom);
 332
 333 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 334                                  struct rte_eth_dev_module_info *modinfo);
 335 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 336                                    struct rte_dev_eeprom_info *info);
 337
 338 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 339 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 340                                 struct rte_dev_reg_info *regs);
 341
 342 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 343 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 344 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 345                                             struct timespec *timestamp,
 346                                             uint32_t flags);
 347 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 348                                             struct timespec *timestamp);
 349 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 350 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 351                                    struct timespec *timestamp);
 352 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 353                                    const struct timespec *timestamp);
 354 static void ixgbevf_dev_interrupt_handler(void *param);
 355
 356 static int ixgbe_dev_l2_tunnel_eth_type_conf
 357         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 358 static int ixgbe_dev_l2_tunnel_offload_set
 359         (struct rte_eth_dev *dev,
 360          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 361          uint32_t mask,
 362          uint8_t en);
 363 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 364                                              enum rte_filter_op filter_op,
 365                                              void *arg);
 366
 367 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 368                                          struct rte_eth_udp_tunnel *udp_tunnel);
 369 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 370                                          struct rte_eth_udp_tunnel *udp_tunnel);
 371 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 372 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 373
 374 /*
 375  * Define VF Stats MACRO for Non "cleared on read" register
 376  */
 377 #define UPDATE_VF_STAT(reg, last, cur)                          \
 378 {                                                               \
 379         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 380         cur += (latest - last) & UINT_MAX;                      \
 381         last = latest;                                          \
 382 }
 383
 384 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 385 {                                                                \
 386         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 387         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 388         u64 latest = ((new_msb << 32) | new_lsb);                \
 389         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 390         last = latest;                                           \
 391 }
 392
 393 #define IXGBE_SET_HWSTRIP(h, q) do {\
 394                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 395                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 396                 (h)->bitmap[idx] |= 1 << bit;\
 397         } while (0)
 398
 399 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 400                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 401                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 402                 (h)->bitmap[idx] &= ~(1 << bit);\
 403         } while (0)
 404
 405 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 406                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 407                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 408                 (r) = (h)->bitmap[idx] >> bit & 1;\
 409         } while (0)
 410
 411 int ixgbe_logtype_init;
 412 int ixgbe_logtype_driver;
 413
 414 /*
 415  * The set of PCI devices this driver supports
 416  */
 417 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 466 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 468 #endif
 469         { .vendor_id = 0, /* sentinel */ },
 470 };
 471
 472 /*
 473  * The set of PCI devices this driver supports (for 82599 VF)
 474  */
 475 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 486         { .vendor_id = 0, /* sentinel */ },
 487 };
 488
 489 static const struct rte_eth_desc_lim rx_desc_lim = {
 490         .nb_max = IXGBE_MAX_RING_DESC,
 491         .nb_min = IXGBE_MIN_RING_DESC,
 492         .nb_align = IXGBE_RXD_ALIGN,
 493 };
 494
 495 static const struct rte_eth_desc_lim tx_desc_lim = {
 496         .nb_max = IXGBE_MAX_RING_DESC,
 497         .nb_min = IXGBE_MIN_RING_DESC,
 498         .nb_align = IXGBE_TXD_ALIGN,
 499         .nb_seg_max = IXGBE_TX_MAX_SEG,
 500         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 501 };
 502
 503 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 504         .dev_configure        = ixgbe_dev_configure,
 505         .dev_start            = ixgbe_dev_start,
 506         .dev_stop             = ixgbe_dev_stop,
 507         .dev_set_link_up    = ixgbe_dev_set_link_up,
 508         .dev_set_link_down  = ixgbe_dev_set_link_down,
 509         .dev_close            = ixgbe_dev_close,
 510         .dev_reset            = ixgbe_dev_reset,
 511         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 512         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 513         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 514         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 515         .link_update          = ixgbe_dev_link_update,
 516         .stats_get            = ixgbe_dev_stats_get,
 517         .xstats_get           = ixgbe_dev_xstats_get,
 518         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 519         .stats_reset          = ixgbe_dev_stats_reset,
 520         .xstats_reset         = ixgbe_dev_xstats_reset,
 521         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 522         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 523         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 524         .fw_version_get       = ixgbe_fw_version_get,
 525         .dev_infos_get        = ixgbe_dev_info_get,
 526         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 527         .mtu_set              = ixgbe_dev_mtu_set,
 528         .vlan_filter_set      = ixgbe_vlan_filter_set,
 529         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 530         .vlan_offload_set     = ixgbe_vlan_offload_set,
 531         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 532         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 533         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 534         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 535         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 536         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 537         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 538         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 539         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 540         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 541         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 542         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 543         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 544         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 545         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 546         .dev_led_on           = ixgbe_dev_led_on,
 547         .dev_led_off          = ixgbe_dev_led_off,
 548         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 549         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 550         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 551         .mac_addr_add         = ixgbe_add_rar,
 552         .mac_addr_remove      = ixgbe_remove_rar,
 553         .mac_addr_set         = ixgbe_set_default_mac_addr,
 554         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 555         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 556         .mirror_rule_set      = ixgbe_mirror_rule_set,
 557         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 558         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 559         .reta_update          = ixgbe_dev_rss_reta_update,
 560         .reta_query           = ixgbe_dev_rss_reta_query,
 561         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 562         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 563         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 564         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 565         .rxq_info_get         = ixgbe_rxq_info_get,
 566         .txq_info_get         = ixgbe_txq_info_get,
 567         .timesync_enable      = ixgbe_timesync_enable,
 568         .timesync_disable     = ixgbe_timesync_disable,
 569         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 570         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 571         .get_reg              = ixgbe_get_regs,
 572         .get_eeprom_length    = ixgbe_get_eeprom_length,
 573         .get_eeprom           = ixgbe_get_eeprom,
 574         .set_eeprom           = ixgbe_set_eeprom,
 575         .get_module_info      = ixgbe_get_module_info,
 576         .get_module_eeprom    = ixgbe_get_module_eeprom,
 577         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 578         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 579         .timesync_read_time   = ixgbe_timesync_read_time,
 580         .timesync_write_time  = ixgbe_timesync_write_time,
 581         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 582         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 583         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 584         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 585         .tm_ops_get           = ixgbe_tm_ops_get,
 586 };
 587
 588 /*
 589  * dev_ops for virtual function, bare necessities for basic vf
 590  * operation have been implemented
 591  */
 592 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 593         .dev_configure        = ixgbevf_dev_configure,
 594         .dev_start            = ixgbevf_dev_start,
 595         .dev_stop             = ixgbevf_dev_stop,
 596         .link_update          = ixgbevf_dev_link_update,
 597         .stats_get            = ixgbevf_dev_stats_get,
 598         .xstats_get           = ixgbevf_dev_xstats_get,
 599         .stats_reset          = ixgbevf_dev_stats_reset,
 600         .xstats_reset         = ixgbevf_dev_stats_reset,
 601         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 602         .dev_close            = ixgbevf_dev_close,
 603         .dev_reset            = ixgbevf_dev_reset,
 604         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 605         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 606         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 607         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 608         .dev_infos_get        = ixgbevf_dev_info_get,
 609         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 610         .mtu_set              = ixgbevf_dev_set_mtu,
 611         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 612         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 613         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 614         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 615         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 616         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 617         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 618         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 619         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 620         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 621         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 622         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 623         .mac_addr_add         = ixgbevf_add_mac_addr,
 624         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 625         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 626         .rxq_info_get         = ixgbe_rxq_info_get,
 627         .txq_info_get         = ixgbe_txq_info_get,
 628         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 629         .get_reg              = ixgbevf_get_regs,
 630         .reta_update          = ixgbe_dev_rss_reta_update,
 631         .reta_query           = ixgbe_dev_rss_reta_query,
 632         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 633         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 634 };
 635
 636 /* store statistics names and its offset in stats structure */
 637 struct rte_ixgbe_xstats_name_off {
 638         char name[RTE_ETH_XSTATS_NAME_SIZE];
 639         unsigned offset;
 640 };
 641
 642 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 643         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 644         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 645         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 646         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 647         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 648         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 649         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 650         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 651         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 652         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 653         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 654         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 655         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 656         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 657         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 658                 prc1023)},
 659         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 660                 prc1522)},
 661         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 662         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 663         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 664         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 665         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 666         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 667         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 668         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 669         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 670         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 671         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 672         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 673         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 674         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 675         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 676         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 677         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 678                 ptc1023)},
 679         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 680                 ptc1522)},
 681         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 682         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 683         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 684         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 685
 686         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 687                 fdirustat_add)},
 688         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 689                 fdirustat_remove)},
 690         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 691                 fdirfstat_fadd)},
 692         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 693                 fdirfstat_fremove)},
 694         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 695                 fdirmatch)},
 696         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 697                 fdirmiss)},
 698
 699         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 700         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 701         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 702                 fclast)},
 703         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 704         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 705         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 706         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 707         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 708                 fcoe_noddp)},
 709         {"rx_fcoe_no_direct_data_placement_ext_buff",
 710                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 711
 712         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 713                 lxontxc)},
 714         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 715                 lxonrxc)},
 716         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 717                 lxofftxc)},
 718         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 719                 lxoffrxc)},
 720         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 721 };
 722
 723 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 724                            sizeof(rte_ixgbe_stats_strings[0]))
 725
 726 /* MACsec statistics */
 727 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 728         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 729                 out_pkts_untagged)},
 730         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 731                 out_pkts_encrypted)},
 732         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 733                 out_pkts_protected)},
 734         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 735                 out_octets_encrypted)},
 736         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 737                 out_octets_protected)},
 738         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 739                 in_pkts_untagged)},
 740         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 741                 in_pkts_badtag)},
 742         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 743                 in_pkts_nosci)},
 744         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 745                 in_pkts_unknownsci)},
 746         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 747                 in_octets_decrypted)},
 748         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 749                 in_octets_validated)},
 750         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_unchecked)},
 752         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_delayed)},
 754         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 755                 in_pkts_late)},
 756         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 757                 in_pkts_ok)},
 758         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 759                 in_pkts_invalid)},
 760         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 761                 in_pkts_notvalid)},
 762         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 763                 in_pkts_unusedsa)},
 764         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 765                 in_pkts_notusingsa)},
 766 };
 767
 768 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 769                            sizeof(rte_ixgbe_macsec_strings[0]))
 770
 771 /* Per-queue statistics */
 772 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 773         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 774         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 775         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 776         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 777 };
 778
 779 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 780                            sizeof(rte_ixgbe_rxq_strings[0]))
 781 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 782
 783 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 784         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 785         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 786         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 787                 pxon2offc)},
 788 };
 789
 790 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 791                            sizeof(rte_ixgbe_txq_strings[0]))
 792 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 793
 794 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 795         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 796 };
 797
 798 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 799                 sizeof(rte_ixgbevf_stats_strings[0]))
 800
 801 /*
 802  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 803  */
 804 static inline int
 805 ixgbe_is_sfp(struct ixgbe_hw *hw)
 806 {
 807         switch (hw->phy.type) {
 808         case ixgbe_phy_sfp_avago:
 809         case ixgbe_phy_sfp_ftl:
 810         case ixgbe_phy_sfp_intel:
 811         case ixgbe_phy_sfp_unknown:
 812         case ixgbe_phy_sfp_passive_tyco:
 813         case ixgbe_phy_sfp_passive_unknown:
 814                 return 1;
 815         default:
 816                 return 0;
 817         }
 818 }
 819
 820 static inline int32_t
 821 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 822 {
 823         uint32_t ctrl_ext;
 824         int32_t status;
 825
 826         status = ixgbe_reset_hw(hw);
 827
 828         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 829         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 830         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 831         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 832         IXGBE_WRITE_FLUSH(hw);
 833
 834         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 835                 status = IXGBE_SUCCESS;
 836         return status;
 837 }
 838
 839 static inline void
 840 ixgbe_enable_intr(struct rte_eth_dev *dev)
 841 {
 842         struct ixgbe_interrupt *intr =
 843                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 844         struct ixgbe_hw *hw =
 845                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 846
 847         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 848         IXGBE_WRITE_FLUSH(hw);
 849 }
 850
 851 /*
 852  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 853  */
 854 static void
 855 ixgbe_disable_intr(struct ixgbe_hw *hw)
 856 {
 857         PMD_INIT_FUNC_TRACE();
 858
 859         if (hw->mac.type == ixgbe_mac_82598EB) {
 860                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 861         } else {
 862                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 863                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 864                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 865         }
 866         IXGBE_WRITE_FLUSH(hw);
 867 }
 868
 869 /*
 870  * This function resets queue statistics mapping registers.
 871  * From Niantic datasheet, Initialization of Statistics section:
 872  * "...if software requires the queue counters, the RQSMR and TQSM registers
 873  * must be re-programmed following a device reset.
 874  */
 875 static void
 876 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 877 {
 878         uint32_t i;
 879
 880         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 881                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 882                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 883         }
 884 }
 885
 886
 887 static int
 888 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 889                                   uint16_t queue_id,
 890                                   uint8_t stat_idx,
 891                                   uint8_t is_rx)
 892 {
 893 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 894 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 895 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 896
 897         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 898         struct ixgbe_stat_mapping_registers *stat_mappings =
 899                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 900         uint32_t qsmr_mask = 0;
 901         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 902         uint32_t q_map;
 903         uint8_t n, offset;
 904
 905         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 906                 (hw->mac.type != ixgbe_mac_X540) &&
 907                 (hw->mac.type != ixgbe_mac_X550) &&
 908                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 909                 (hw->mac.type != ixgbe_mac_X550EM_a))
 910                 return -ENOSYS;
 911
 912         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 913                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 914                      queue_id, stat_idx);
 915
 916         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 917         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 918                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 919                 return -EIO;
 920         }
 921         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 922
 923         /* Now clear any previous stat_idx set */
 924         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 925         if (!is_rx)
 926                 stat_mappings->tqsm[n] &= ~clearing_mask;
 927         else
 928                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 929
 930         q_map = (uint32_t)stat_idx;
 931         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 932         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 933         if (!is_rx)
 934                 stat_mappings->tqsm[n] |= qsmr_mask;
 935         else
 936                 stat_mappings->rqsmr[n] |= qsmr_mask;
 937
 938         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 939                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 940                      queue_id, stat_idx);
 941         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 942                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 943
 944         /* Now write the mapping in the appropriate register */
 945         if (is_rx) {
 946                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 947                              stat_mappings->rqsmr[n], n);
 948                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 949         } else {
 950                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 951                              stat_mappings->tqsm[n], n);
 952                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 953         }
 954         return 0;
 955 }
 956
 957 static void
 958 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 959 {
 960         struct ixgbe_stat_mapping_registers *stat_mappings =
 961                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 962         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 963         int i;
 964
 965         /* write whatever was in stat mapping table to the NIC */
 966         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 967                 /* rx */
 968                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 969
 970                 /* tx */
 971                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 972         }
 973 }
 974
 975 static void
 976 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 977 {
 978         uint8_t i;
 979         struct ixgbe_dcb_tc_config *tc;
 980         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 981
 982         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 983         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 984         for (i = 0; i < dcb_max_tc; i++) {
 985                 tc = &dcb_config->tc_config[i];
 986                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 987                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 988                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 989                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 990                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 991                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 992                 tc->pfc = ixgbe_dcb_pfc_disabled;
 993         }
 994
 995         /* Initialize default user to priority mapping, UPx->TC0 */
 996         tc = &dcb_config->tc_config[0];
 997         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 998         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 999         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1000                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1001                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1002         }
1003         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1004         dcb_config->pfc_mode_enable = false;
1005         dcb_config->vt_mode = true;
1006         dcb_config->round_robin_enable = false;
1007         /* support all DCB capabilities in 82599 */
1008         dcb_config->support.capabilities = 0xFF;
1009
1010         /*we only support 4 Tcs for X540, X550 */
1011         if (hw->mac.type == ixgbe_mac_X540 ||
1012                 hw->mac.type == ixgbe_mac_X550 ||
1013                 hw->mac.type == ixgbe_mac_X550EM_x ||
1014                 hw->mac.type == ixgbe_mac_X550EM_a) {
1015                 dcb_config->num_tcs.pg_tcs = 4;
1016                 dcb_config->num_tcs.pfc_tcs = 4;
1017         }
1018 }
1019
1020 /*
1021  * Ensure that all locks are released before first NVM or PHY access
1022  */
1023 static void
1024 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1025 {
1026         uint16_t mask;
1027
1028         /*
1029          * Phy lock should not fail in this early stage. If this is the case,
1030          * it is due to an improper exit of the application.
1031          * So force the release of the faulty lock. Release of common lock
1032          * is done automatically by swfw_sync function.
1033          */
1034         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1035         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1036                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1037         }
1038         ixgbe_release_swfw_semaphore(hw, mask);
1039
1040         /*
1041          * These ones are more tricky since they are common to all ports; but
1042          * swfw_sync retries last long enough (1s) to be almost sure that if
1043          * lock can not be taken it is due to an improper lock of the
1044          * semaphore.
1045          */
1046         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1047         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1048                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1049         }
1050         ixgbe_release_swfw_semaphore(hw, mask);
1051 }
1052
1053 /*
1054  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1055  * It returns 0 on success.
1056  */
1057 static int
1058 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1059 {
1060         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1061         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1062         struct ixgbe_hw *hw =
1063                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1064         struct ixgbe_vfta *shadow_vfta =
1065                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1066         struct ixgbe_hwstrip *hwstrip =
1067                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1068         struct ixgbe_dcb_config *dcb_config =
1069                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1070         struct ixgbe_filter_info *filter_info =
1071                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1072         struct ixgbe_bw_conf *bw_conf =
1073                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1074         uint32_t ctrl_ext;
1075         uint16_t csum;
1076         int diag, i;
1077
1078         PMD_INIT_FUNC_TRACE();
1079
1080         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1081         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1082         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1083         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1084
1085         /*
1086          * For secondary processes, we don't initialise any further as primary
1087          * has already done this work. Only check we don't need a different
1088          * RX and TX function.
1089          */
1090         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1091                 struct ixgbe_tx_queue *txq;
1092                 /* TX queue function in primary, set by last queue initialized
1093                  * Tx queue may not initialized by primary process
1094                  */
1095                 if (eth_dev->data->tx_queues) {
1096                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1097                         ixgbe_set_tx_function(eth_dev, txq);
1098                 } else {
1099                         /* Use default TX function if we get here */
1100                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1101                                      "Using default TX function.");
1102                 }
1103
1104                 ixgbe_set_rx_function(eth_dev);
1105
1106                 return 0;
1107         }
1108
1109         rte_eth_copy_pci_info(eth_dev, pci_dev);
1110
1111         /* Vendor and Device ID need to be set before init of shared code */
1112         hw->device_id = pci_dev->id.device_id;
1113         hw->vendor_id = pci_dev->id.vendor_id;
1114         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1115         hw->allow_unsupported_sfp = 1;
1116
1117         /* Initialize the shared code (base driver) */
1118 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1119         diag = ixgbe_bypass_init_shared_code(hw);
1120 #else
1121         diag = ixgbe_init_shared_code(hw);
1122 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1123
1124         if (diag != IXGBE_SUCCESS) {
1125                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1126                 return -EIO;
1127         }
1128
1129         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1130                 PMD_INIT_LOG(ERR, "\nERROR: "
1131                         "Firmware recovery mode detected. Limiting functionality.\n"
1132                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1133                         "User Guide for details on firmware recovery mode.");
1134                 return -EIO;
1135         }
1136
1137         /* pick up the PCI bus settings for reporting later */
1138         ixgbe_get_bus_info(hw);
1139
1140         /* Unlock any pending hardware semaphore */
1141         ixgbe_swfw_lock_reset(hw);
1142
1143 #ifdef RTE_LIBRTE_SECURITY
1144         /* Initialize security_ctx only for primary process*/
1145         if (ixgbe_ipsec_ctx_create(eth_dev))
1146                 return -ENOMEM;
1147 #endif
1148
1149         /* Initialize DCB configuration*/
1150         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1151         ixgbe_dcb_init(hw, dcb_config);
1152         /* Get Hardware Flow Control setting */
1153         hw->fc.requested_mode = ixgbe_fc_full;
1154         hw->fc.current_mode = ixgbe_fc_full;
1155         hw->fc.pause_time = IXGBE_FC_PAUSE;
1156         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1157                 hw->fc.low_water[i] = IXGBE_FC_LO;
1158                 hw->fc.high_water[i] = IXGBE_FC_HI;
1159         }
1160         hw->fc.send_xon = 1;
1161
1162         /* Make sure we have a good EEPROM before we read from it */
1163         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1164         if (diag != IXGBE_SUCCESS) {
1165                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1166                 return -EIO;
1167         }
1168
1169 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1170         diag = ixgbe_bypass_init_hw(hw);
1171 #else
1172         diag = ixgbe_init_hw(hw);
1173 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1174
1175         /*
1176          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1177          * is called too soon after the kernel driver unbinding/binding occurs.
1178          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1179          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1180          * also called. See ixgbe_identify_phy_82599(). The reason for the
1181          * failure is not known, and only occuts when virtualisation features
1182          * are disabled in the bios. A delay of 100ms  was found to be enough by
1183          * trial-and-error, and is doubled to be safe.
1184          */
1185         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1186                 rte_delay_ms(200);
1187                 diag = ixgbe_init_hw(hw);
1188         }
1189
1190         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1191                 diag = IXGBE_SUCCESS;
1192
1193         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1194                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1195                              "LOM.  Please be aware there may be issues associated "
1196                              "with your hardware.");
1197                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1198                              "please contact your Intel or hardware representative "
1199                              "who provided you with this hardware.");
1200         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1201                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1202         if (diag) {
1203                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1204                 return -EIO;
1205         }
1206
1207         /* Reset the hw statistics */
1208         ixgbe_dev_stats_reset(eth_dev);
1209
1210         /* disable interrupt */
1211         ixgbe_disable_intr(hw);
1212
1213         /* reset mappings for queue statistics hw counters*/
1214         ixgbe_reset_qstat_mappings(hw);
1215
1216         /* Allocate memory for storing MAC addresses */
1217         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1218                                                hw->mac.num_rar_entries, 0);
1219         if (eth_dev->data->mac_addrs == NULL) {
1220                 PMD_INIT_LOG(ERR,
1221                              "Failed to allocate %u bytes needed to store "
1222                              "MAC addresses",
1223                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1224                 return -ENOMEM;
1225         }
1226         /* Copy the permanent MAC address */
1227         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1228                         &eth_dev->data->mac_addrs[0]);
1229
1230         /* Allocate memory for storing hash filter MAC addresses */
1231         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1232                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1233         if (eth_dev->data->hash_mac_addrs == NULL) {
1234                 PMD_INIT_LOG(ERR,
1235                              "Failed to allocate %d bytes needed to store MAC addresses",
1236                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1237                 return -ENOMEM;
1238         }
1239
1240         /* initialize the vfta */
1241         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1242
1243         /* initialize the hw strip bitmap*/
1244         memset(hwstrip, 0, sizeof(*hwstrip));
1245
1246         /* initialize PF if max_vfs not zero */
1247         ixgbe_pf_host_init(eth_dev);
1248
1249         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1250         /* let hardware know driver is loaded */
1251         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1252         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1253         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1254         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1255         IXGBE_WRITE_FLUSH(hw);
1256
1257         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1258                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1259                              (int) hw->mac.type, (int) hw->phy.type,
1260                              (int) hw->phy.sfp_type);
1261         else
1262                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1263                              (int) hw->mac.type, (int) hw->phy.type);
1264
1265         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1266                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1267                      pci_dev->id.device_id);
1268
1269         rte_intr_callback_register(intr_handle,
1270                                    ixgbe_dev_interrupt_handler, eth_dev);
1271
1272         /* enable uio/vfio intr/eventfd mapping */
1273         rte_intr_enable(intr_handle);
1274
1275         /* enable support intr */
1276         ixgbe_enable_intr(eth_dev);
1277
1278         /* initialize filter info */
1279         memset(filter_info, 0,
1280                sizeof(struct ixgbe_filter_info));
1281
1282         /* initialize 5tuple filter list */
1283         TAILQ_INIT(&filter_info->fivetuple_list);
1284
1285         /* initialize flow director filter list & hash */
1286         ixgbe_fdir_filter_init(eth_dev);
1287
1288         /* initialize l2 tunnel filter list & hash */
1289         ixgbe_l2_tn_filter_init(eth_dev);
1290
1291         /* initialize flow filter lists */
1292         ixgbe_filterlist_init();
1293
1294         /* initialize bandwidth configuration info */
1295         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1296
1297         /* initialize Traffic Manager configuration */
1298         ixgbe_tm_conf_init(eth_dev);
1299
1300         return 0;
1301 }
1302
1303 static int
1304 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1305 {
1306         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1307         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1308         struct ixgbe_hw *hw;
1309         int retries = 0;
1310         int ret;
1311
1312         PMD_INIT_FUNC_TRACE();
1313
1314         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1315                 return 0;
1316
1317         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1318
1319         if (hw->adapter_stopped == 0)
1320                 ixgbe_dev_close(eth_dev);
1321
1322         eth_dev->dev_ops = NULL;
1323         eth_dev->rx_pkt_burst = NULL;
1324         eth_dev->tx_pkt_burst = NULL;
1325
1326         /* Unlock any pending hardware semaphore */
1327         ixgbe_swfw_lock_reset(hw);
1328
1329         /* disable uio intr before callback unregister */
1330         rte_intr_disable(intr_handle);
1331
1332         do {
1333                 ret = rte_intr_callback_unregister(intr_handle,
1334                                 ixgbe_dev_interrupt_handler, eth_dev);
1335                 if (ret >= 0) {
1336                         break;
1337                 } else if (ret != -EAGAIN) {
1338                         PMD_INIT_LOG(ERR,
1339                                 "intr callback unregister failed: %d",
1340                                 ret);
1341                         return ret;
1342                 }
1343                 rte_delay_ms(100);
1344         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1345
1346         /* cancel the delay handler before remove dev */
1347         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, eth_dev);
1348
1349         /* cancel the link handler before remove dev */
1350         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, eth_dev);
1351
1352         /* uninitialize PF if max_vfs not zero */
1353         ixgbe_pf_host_uninit(eth_dev);
1354
1355         /* remove all the fdir filters & hash */
1356         ixgbe_fdir_filter_uninit(eth_dev);
1357
1358         /* remove all the L2 tunnel filters & hash */
1359         ixgbe_l2_tn_filter_uninit(eth_dev);
1360
1361         /* Remove all ntuple filters of the device */
1362         ixgbe_ntuple_filter_uninit(eth_dev);
1363
1364         /* clear all the filters list */
1365         ixgbe_filterlist_flush();
1366
1367         /* Remove all Traffic Manager configuration */
1368         ixgbe_tm_conf_uninit(eth_dev);
1369
1370 #ifdef RTE_LIBRTE_SECURITY
1371         rte_free(eth_dev->security_ctx);
1372 #endif
1373
1374         return 0;
1375 }
1376
1377 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1378 {
1379         struct ixgbe_filter_info *filter_info =
1380                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1381         struct ixgbe_5tuple_filter *p_5tuple;
1382
1383         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1384                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1385                              p_5tuple,
1386                              entries);
1387                 rte_free(p_5tuple);
1388         }
1389         memset(filter_info->fivetuple_mask, 0,
1390                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1391
1392         return 0;
1393 }
1394
1395 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1396 {
1397         struct ixgbe_hw_fdir_info *fdir_info =
1398                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1399         struct ixgbe_fdir_filter *fdir_filter;
1400
1401                 if (fdir_info->hash_map)
1402                 rte_free(fdir_info->hash_map);
1403         if (fdir_info->hash_handle)
1404                 rte_hash_free(fdir_info->hash_handle);
1405
1406         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1407                 TAILQ_REMOVE(&fdir_info->fdir_list,
1408                              fdir_filter,
1409                              entries);
1410                 rte_free(fdir_filter);
1411         }
1412
1413         return 0;
1414 }
1415
1416 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1417 {
1418         struct ixgbe_l2_tn_info *l2_tn_info =
1419                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1420         struct ixgbe_l2_tn_filter *l2_tn_filter;
1421
1422         if (l2_tn_info->hash_map)
1423                 rte_free(l2_tn_info->hash_map);
1424         if (l2_tn_info->hash_handle)
1425                 rte_hash_free(l2_tn_info->hash_handle);
1426
1427         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1428                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1429                              l2_tn_filter,
1430                              entries);
1431                 rte_free(l2_tn_filter);
1432         }
1433
1434         return 0;
1435 }
1436
1437 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1438 {
1439         struct ixgbe_hw_fdir_info *fdir_info =
1440                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1441         char fdir_hash_name[RTE_HASH_NAMESIZE];
1442         struct rte_hash_parameters fdir_hash_params = {
1443                 .name = fdir_hash_name,
1444                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1445                 .key_len = sizeof(union ixgbe_atr_input),
1446                 .hash_func = rte_hash_crc,
1447                 .hash_func_init_val = 0,
1448                 .socket_id = rte_socket_id(),
1449         };
1450
1451         TAILQ_INIT(&fdir_info->fdir_list);
1452         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1453                  "fdir_%s", eth_dev->device->name);
1454         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1455         if (!fdir_info->hash_handle) {
1456                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1457                 return -EINVAL;
1458         }
1459         fdir_info->hash_map = rte_zmalloc("ixgbe",
1460                                           sizeof(struct ixgbe_fdir_filter *) *
1461                                           IXGBE_MAX_FDIR_FILTER_NUM,
1462                                           0);
1463         if (!fdir_info->hash_map) {
1464                 PMD_INIT_LOG(ERR,
1465                              "Failed to allocate memory for fdir hash map!");
1466                 return -ENOMEM;
1467         }
1468         fdir_info->mask_added = FALSE;
1469
1470         return 0;
1471 }
1472
1473 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1474 {
1475         struct ixgbe_l2_tn_info *l2_tn_info =
1476                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1477         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1478         struct rte_hash_parameters l2_tn_hash_params = {
1479                 .name = l2_tn_hash_name,
1480                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1481                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1482                 .hash_func = rte_hash_crc,
1483                 .hash_func_init_val = 0,
1484                 .socket_id = rte_socket_id(),
1485         };
1486
1487         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1488         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1489                  "l2_tn_%s", eth_dev->device->name);
1490         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1491         if (!l2_tn_info->hash_handle) {
1492                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1493                 return -EINVAL;
1494         }
1495         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1496                                    sizeof(struct ixgbe_l2_tn_filter *) *
1497                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1498                                    0);
1499         if (!l2_tn_info->hash_map) {
1500                 PMD_INIT_LOG(ERR,
1501                         "Failed to allocate memory for L2 TN hash map!");
1502                 return -ENOMEM;
1503         }
1504         l2_tn_info->e_tag_en = FALSE;
1505         l2_tn_info->e_tag_fwd_en = FALSE;
1506         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1507
1508         return 0;
1509 }
1510 /*
1511  * Negotiate mailbox API version with the PF.
1512  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1513  * Then we try to negotiate starting with the most recent one.
1514  * If all negotiation attempts fail, then we will proceed with
1515  * the default one (ixgbe_mbox_api_10).
1516  */
1517 static void
1518 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1519 {
1520         int32_t i;
1521
1522         /* start with highest supported, proceed down */
1523         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1524                 ixgbe_mbox_api_13,
1525                 ixgbe_mbox_api_12,
1526                 ixgbe_mbox_api_11,
1527                 ixgbe_mbox_api_10,
1528         };
1529
1530         for (i = 0;
1531                         i != RTE_DIM(sup_ver) &&
1532                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1533                         i++)
1534                 ;
1535 }
1536
1537 static void
1538 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1539 {
1540         uint64_t random;
1541
1542         /* Set Organizationally Unique Identifier (OUI) prefix. */
1543         mac_addr->addr_bytes[0] = 0x00;
1544         mac_addr->addr_bytes[1] = 0x09;
1545         mac_addr->addr_bytes[2] = 0xC0;
1546         /* Force indication of locally assigned MAC address. */
1547         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1548         /* Generate the last 3 bytes of the MAC address with a random number. */
1549         random = rte_rand();
1550         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1551 }
1552
1553 /*
1554  * Virtual Function device init
1555  */
1556 static int
1557 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1558 {
1559         int diag;
1560         uint32_t tc, tcs;
1561         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1562         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1563         struct ixgbe_hw *hw =
1564                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1565         struct ixgbe_vfta *shadow_vfta =
1566                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1567         struct ixgbe_hwstrip *hwstrip =
1568                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1569         struct rte_ether_addr *perm_addr =
1570                 (struct rte_ether_addr *)hw->mac.perm_addr;
1571
1572         PMD_INIT_FUNC_TRACE();
1573
1574         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1575         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1576         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1577
1578         /* for secondary processes, we don't initialise any further as primary
1579          * has already done this work. Only check we don't need a different
1580          * RX function
1581          */
1582         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1583                 struct ixgbe_tx_queue *txq;
1584                 /* TX queue function in primary, set by last queue initialized
1585                  * Tx queue may not initialized by primary process
1586                  */
1587                 if (eth_dev->data->tx_queues) {
1588                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1589                         ixgbe_set_tx_function(eth_dev, txq);
1590                 } else {
1591                         /* Use default TX function if we get here */
1592                         PMD_INIT_LOG(NOTICE,
1593                                      "No TX queues configured yet. Using default TX function.");
1594                 }
1595
1596                 ixgbe_set_rx_function(eth_dev);
1597
1598                 return 0;
1599         }
1600
1601         rte_eth_copy_pci_info(eth_dev, pci_dev);
1602
1603         hw->device_id = pci_dev->id.device_id;
1604         hw->vendor_id = pci_dev->id.vendor_id;
1605         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1606
1607         /* initialize the vfta */
1608         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1609
1610         /* initialize the hw strip bitmap*/
1611         memset(hwstrip, 0, sizeof(*hwstrip));
1612
1613         /* Initialize the shared code (base driver) */
1614         diag = ixgbe_init_shared_code(hw);
1615         if (diag != IXGBE_SUCCESS) {
1616                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1617                 return -EIO;
1618         }
1619
1620         /* init_mailbox_params */
1621         hw->mbx.ops.init_params(hw);
1622
1623         /* Reset the hw statistics */
1624         ixgbevf_dev_stats_reset(eth_dev);
1625
1626         /* Disable the interrupts for VF */
1627         ixgbevf_intr_disable(eth_dev);
1628
1629         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1630         diag = hw->mac.ops.reset_hw(hw);
1631
1632         /*
1633          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1634          * the underlying PF driver has not assigned a MAC address to the VF.
1635          * In this case, assign a random MAC address.
1636          */
1637         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1638                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1639                 /*
1640                  * This error code will be propagated to the app by
1641                  * rte_eth_dev_reset, so use a public error code rather than
1642                  * the internal-only IXGBE_ERR_RESET_FAILED
1643                  */
1644                 return -EAGAIN;
1645         }
1646
1647         /* negotiate mailbox API version to use with the PF. */
1648         ixgbevf_negotiate_api(hw);
1649
1650         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1651         ixgbevf_get_queues(hw, &tcs, &tc);
1652
1653         /* Allocate memory for storing MAC addresses */
1654         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1655                                                hw->mac.num_rar_entries, 0);
1656         if (eth_dev->data->mac_addrs == NULL) {
1657                 PMD_INIT_LOG(ERR,
1658                              "Failed to allocate %u bytes needed to store "
1659                              "MAC addresses",
1660                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1661                 return -ENOMEM;
1662         }
1663
1664         /* Generate a random MAC address, if none was assigned by PF. */
1665         if (rte_is_zero_ether_addr(perm_addr)) {
1666                 generate_random_mac_addr(perm_addr);
1667                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1668                 if (diag) {
1669                         rte_free(eth_dev->data->mac_addrs);
1670                         eth_dev->data->mac_addrs = NULL;
1671                         return diag;
1672                 }
1673                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1674                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1675                              "%02x:%02x:%02x:%02x:%02x:%02x",
1676                              perm_addr->addr_bytes[0],
1677                              perm_addr->addr_bytes[1],
1678                              perm_addr->addr_bytes[2],
1679                              perm_addr->addr_bytes[3],
1680                              perm_addr->addr_bytes[4],
1681                              perm_addr->addr_bytes[5]);
1682         }
1683
1684         /* Copy the permanent MAC address */
1685         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1686
1687         /* reset the hardware with the new settings */
1688         diag = hw->mac.ops.start_hw(hw);
1689         switch (diag) {
1690         case  0:
1691                 break;
1692
1693         default:
1694                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1695                 return -EIO;
1696         }
1697
1698         rte_intr_callback_register(intr_handle,
1699                                    ixgbevf_dev_interrupt_handler, eth_dev);
1700         rte_intr_enable(intr_handle);
1701         ixgbevf_intr_enable(eth_dev);
1702
1703         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1704                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1705                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1706
1707         return 0;
1708 }
1709
1710 /* Virtual Function device uninit */
1711
1712 static int
1713 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1714 {
1715         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1716         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1717         struct ixgbe_hw *hw;
1718
1719         PMD_INIT_FUNC_TRACE();
1720
1721         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1722                 return 0;
1723
1724         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1725
1726         if (hw->adapter_stopped == 0)
1727                 ixgbevf_dev_close(eth_dev);
1728
1729         eth_dev->dev_ops = NULL;
1730         eth_dev->rx_pkt_burst = NULL;
1731         eth_dev->tx_pkt_burst = NULL;
1732
1733         /* Disable the interrupts for VF */
1734         ixgbevf_intr_disable(eth_dev);
1735
1736         rte_intr_disable(intr_handle);
1737         rte_intr_callback_unregister(intr_handle,
1738                                      ixgbevf_dev_interrupt_handler, eth_dev);
1739
1740         return 0;
1741 }
1742
1743 static int
1744 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1745                 struct rte_pci_device *pci_dev)
1746 {
1747         char name[RTE_ETH_NAME_MAX_LEN];
1748         struct rte_eth_dev *pf_ethdev;
1749         struct rte_eth_devargs eth_da;
1750         int i, retval;
1751
1752         if (pci_dev->device.devargs) {
1753                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1754                                 &eth_da);
1755                 if (retval)
1756                         return retval;
1757         } else
1758                 memset(&eth_da, 0, sizeof(eth_da));
1759
1760         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1761                 sizeof(struct ixgbe_adapter),
1762                 eth_dev_pci_specific_init, pci_dev,
1763                 eth_ixgbe_dev_init, NULL);
1764
1765         if (retval || eth_da.nb_representor_ports < 1)
1766                 return retval;
1767
1768         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1769         if (pf_ethdev == NULL)
1770                 return -ENODEV;
1771
1772         /* probe VF representor ports */
1773         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1774                 struct ixgbe_vf_info *vfinfo;
1775                 struct ixgbe_vf_representor representor;
1776
1777                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1778                         pf_ethdev->data->dev_private);
1779                 if (vfinfo == NULL) {
1780                         PMD_DRV_LOG(ERR,
1781                                 "no virtual functions supported by PF");
1782                         break;
1783                 }
1784
1785                 representor.vf_id = eth_da.representor_ports[i];
1786                 representor.switch_domain_id = vfinfo->switch_domain_id;
1787                 representor.pf_ethdev = pf_ethdev;
1788
1789                 /* representor port net_bdf_port */
1790                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1791                         pci_dev->device.name,
1792                         eth_da.representor_ports[i]);
1793
1794                 retval = rte_eth_dev_create(&pci_dev->device, name,
1795                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1796                         ixgbe_vf_representor_init, &representor);
1797
1798                 if (retval)
1799                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1800                                 "representor %s.", name);
1801         }
1802
1803         return 0;
1804 }
1805
1806 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1807 {
1808         struct rte_eth_dev *ethdev;
1809
1810         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1811         if (!ethdev)
1812                 return -ENODEV;
1813
1814         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1815                 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1816         else
1817                 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1818 }
1819
1820 static struct rte_pci_driver rte_ixgbe_pmd = {
1821         .id_table = pci_id_ixgbe_map,
1822         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1823                      RTE_PCI_DRV_IOVA_AS_VA,
1824         .probe = eth_ixgbe_pci_probe,
1825         .remove = eth_ixgbe_pci_remove,
1826 };
1827
1828 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1829         struct rte_pci_device *pci_dev)
1830 {
1831         return rte_eth_dev_pci_generic_probe(pci_dev,
1832                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1833 }
1834
1835 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1836 {
1837         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1838 }
1839
1840 /*
1841  * virtual function driver struct
1842  */
1843 static struct rte_pci_driver rte_ixgbevf_pmd = {
1844         .id_table = pci_id_ixgbevf_map,
1845         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1846         .probe = eth_ixgbevf_pci_probe,
1847         .remove = eth_ixgbevf_pci_remove,
1848 };
1849
1850 static int
1851 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1852 {
1853         struct ixgbe_hw *hw =
1854                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1855         struct ixgbe_vfta *shadow_vfta =
1856                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1857         uint32_t vfta;
1858         uint32_t vid_idx;
1859         uint32_t vid_bit;
1860
1861         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1862         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1863         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1864         if (on)
1865                 vfta |= vid_bit;
1866         else
1867                 vfta &= ~vid_bit;
1868         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1869
1870         /* update local VFTA copy */
1871         shadow_vfta->vfta[vid_idx] = vfta;
1872
1873         return 0;
1874 }
1875
1876 static void
1877 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1878 {
1879         if (on)
1880                 ixgbe_vlan_hw_strip_enable(dev, queue);
1881         else
1882                 ixgbe_vlan_hw_strip_disable(dev, queue);
1883 }
1884
1885 static int
1886 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1887                     enum rte_vlan_type vlan_type,
1888                     uint16_t tpid)
1889 {
1890         struct ixgbe_hw *hw =
1891                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1892         int ret = 0;
1893         uint32_t reg;
1894         uint32_t qinq;
1895
1896         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1897         qinq &= IXGBE_DMATXCTL_GDV;
1898
1899         switch (vlan_type) {
1900         case ETH_VLAN_TYPE_INNER:
1901                 if (qinq) {
1902                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1903                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1904                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1905                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1906                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1907                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1908                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1909                 } else {
1910                         ret = -ENOTSUP;
1911                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1912                                     " by single VLAN");
1913                 }
1914                 break;
1915         case ETH_VLAN_TYPE_OUTER:
1916                 if (qinq) {
1917                         /* Only the high 16-bits is valid */
1918                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1919                                         IXGBE_EXVET_VET_EXT_SHIFT);
1920                 } else {
1921                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1922                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1923                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1924                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1925                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1926                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1927                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1928                 }
1929
1930                 break;
1931         default:
1932                 ret = -EINVAL;
1933                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1934                 break;
1935         }
1936
1937         return ret;
1938 }
1939
1940 void
1941 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1942 {
1943         struct ixgbe_hw *hw =
1944                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1945         uint32_t vlnctrl;
1946
1947         PMD_INIT_FUNC_TRACE();
1948
1949         /* Filter Table Disable */
1950         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1951         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1952
1953         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1954 }
1955
1956 void
1957 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1958 {
1959         struct ixgbe_hw *hw =
1960                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1961         struct ixgbe_vfta *shadow_vfta =
1962                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1963         uint32_t vlnctrl;
1964         uint16_t i;
1965
1966         PMD_INIT_FUNC_TRACE();
1967
1968         /* Filter Table Enable */
1969         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1970         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1971         vlnctrl |= IXGBE_VLNCTRL_VFE;
1972
1973         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1974
1975         /* write whatever is in local vfta copy */
1976         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1977                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1978 }
1979
1980 static void
1981 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1982 {
1983         struct ixgbe_hwstrip *hwstrip =
1984                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1985         struct ixgbe_rx_queue *rxq;
1986
1987         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1988                 return;
1989
1990         if (on)
1991                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1992         else
1993                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1994
1995         if (queue >= dev->data->nb_rx_queues)
1996                 return;
1997
1998         rxq = dev->data->rx_queues[queue];
1999
2000         if (on) {
2001                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2002                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2003         } else {
2004                 rxq->vlan_flags = PKT_RX_VLAN;
2005                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2006         }
2007 }
2008
2009 static void
2010 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2011 {
2012         struct ixgbe_hw *hw =
2013                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2014         uint32_t ctrl;
2015
2016         PMD_INIT_FUNC_TRACE();
2017
2018         if (hw->mac.type == ixgbe_mac_82598EB) {
2019                 /* No queue level support */
2020                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2021                 return;
2022         }
2023
2024         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2025         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2026         ctrl &= ~IXGBE_RXDCTL_VME;
2027         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2028
2029         /* record those setting for HW strip per queue */
2030         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2031 }
2032
2033 static void
2034 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2035 {
2036         struct ixgbe_hw *hw =
2037                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2038         uint32_t ctrl;
2039
2040         PMD_INIT_FUNC_TRACE();
2041
2042         if (hw->mac.type == ixgbe_mac_82598EB) {
2043                 /* No queue level supported */
2044                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2045                 return;
2046         }
2047
2048         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2049         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2050         ctrl |= IXGBE_RXDCTL_VME;
2051         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2052
2053         /* record those setting for HW strip per queue */
2054         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2055 }
2056
2057 static void
2058 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2059 {
2060         struct ixgbe_hw *hw =
2061                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2062         uint32_t ctrl;
2063
2064         PMD_INIT_FUNC_TRACE();
2065
2066         /* DMATXCTRL: Geric Double VLAN Disable */
2067         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2068         ctrl &= ~IXGBE_DMATXCTL_GDV;
2069         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2070
2071         /* CTRL_EXT: Global Double VLAN Disable */
2072         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2073         ctrl &= ~IXGBE_EXTENDED_VLAN;
2074         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2075
2076 }
2077
2078 static void
2079 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2080 {
2081         struct ixgbe_hw *hw =
2082                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2083         uint32_t ctrl;
2084
2085         PMD_INIT_FUNC_TRACE();
2086
2087         /* DMATXCTRL: Geric Double VLAN Enable */
2088         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2089         ctrl |= IXGBE_DMATXCTL_GDV;
2090         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2091
2092         /* CTRL_EXT: Global Double VLAN Enable */
2093         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2094         ctrl |= IXGBE_EXTENDED_VLAN;
2095         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2096
2097         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2098         if (hw->mac.type == ixgbe_mac_X550 ||
2099             hw->mac.type == ixgbe_mac_X550EM_x ||
2100             hw->mac.type == ixgbe_mac_X550EM_a) {
2101                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2102                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2103                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2104         }
2105
2106         /*
2107          * VET EXT field in the EXVET register = 0x8100 by default
2108          * So no need to change. Same to VT field of DMATXCTL register
2109          */
2110 }
2111
2112 void
2113 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2114 {
2115         struct ixgbe_hw *hw =
2116                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2117         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2118         uint32_t ctrl;
2119         uint16_t i;
2120         struct ixgbe_rx_queue *rxq;
2121         bool on;
2122
2123         PMD_INIT_FUNC_TRACE();
2124
2125         if (hw->mac.type == ixgbe_mac_82598EB) {
2126                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2127                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2128                         ctrl |= IXGBE_VLNCTRL_VME;
2129                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2130                 } else {
2131                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2132                         ctrl &= ~IXGBE_VLNCTRL_VME;
2133                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2134                 }
2135         } else {
2136                 /*
2137                  * Other 10G NIC, the VLAN strip can be setup
2138                  * per queue in RXDCTL
2139                  */
2140                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2141                         rxq = dev->data->rx_queues[i];
2142                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2143                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2144                                 ctrl |= IXGBE_RXDCTL_VME;
2145                                 on = TRUE;
2146                         } else {
2147                                 ctrl &= ~IXGBE_RXDCTL_VME;
2148                                 on = FALSE;
2149                         }
2150                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2151
2152                         /* record those setting for HW strip per queue */
2153                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2154                 }
2155         }
2156 }
2157
2158 static void
2159 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2160 {
2161         uint16_t i;
2162         struct rte_eth_rxmode *rxmode;
2163         struct ixgbe_rx_queue *rxq;
2164
2165         if (mask & ETH_VLAN_STRIP_MASK) {
2166                 rxmode = &dev->data->dev_conf.rxmode;
2167                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2168                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2169                                 rxq = dev->data->rx_queues[i];
2170                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2171                         }
2172                 else
2173                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2174                                 rxq = dev->data->rx_queues[i];
2175                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2176                         }
2177         }
2178 }
2179
2180 static int
2181 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2182 {
2183         struct rte_eth_rxmode *rxmode;
2184         rxmode = &dev->data->dev_conf.rxmode;
2185
2186         if (mask & ETH_VLAN_STRIP_MASK) {
2187                 ixgbe_vlan_hw_strip_config(dev);
2188         }
2189
2190         if (mask & ETH_VLAN_FILTER_MASK) {
2191                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2192                         ixgbe_vlan_hw_filter_enable(dev);
2193                 else
2194                         ixgbe_vlan_hw_filter_disable(dev);
2195         }
2196
2197         if (mask & ETH_VLAN_EXTEND_MASK) {
2198                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2199                         ixgbe_vlan_hw_extend_enable(dev);
2200                 else
2201                         ixgbe_vlan_hw_extend_disable(dev);
2202         }
2203
2204         return 0;
2205 }
2206
2207 static int
2208 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2209 {
2210         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2211
2212         ixgbe_vlan_offload_config(dev, mask);
2213
2214         return 0;
2215 }
2216
2217 static void
2218 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2219 {
2220         struct ixgbe_hw *hw =
2221                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2222         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2223         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2224
2225         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2226         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2227 }
2228
2229 static int
2230 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2231 {
2232         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2233
2234         switch (nb_rx_q) {
2235         case 1:
2236         case 2:
2237                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2238                 break;
2239         case 4:
2240                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2241                 break;
2242         default:
2243                 return -EINVAL;
2244         }
2245
2246         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2247                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2248         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2249                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2250         return 0;
2251 }
2252
2253 static int
2254 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2255 {
2256         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2257         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2258         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2259         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2260
2261         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2262                 /* check multi-queue mode */
2263                 switch (dev_conf->rxmode.mq_mode) {
2264                 case ETH_MQ_RX_VMDQ_DCB:
2265                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2266                         break;
2267                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2268                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2269                         PMD_INIT_LOG(ERR, "SRIOV active,"
2270                                         " unsupported mq_mode rx %d.",
2271                                         dev_conf->rxmode.mq_mode);
2272                         return -EINVAL;
2273                 case ETH_MQ_RX_RSS:
2274                 case ETH_MQ_RX_VMDQ_RSS:
2275                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2276                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2277                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2278                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2279                                                 " invalid queue number"
2280                                                 " for VMDQ RSS, allowed"
2281                                                 " value are 1, 2 or 4.");
2282                                         return -EINVAL;
2283                                 }
2284                         break;
2285                 case ETH_MQ_RX_VMDQ_ONLY:
2286                 case ETH_MQ_RX_NONE:
2287                         /* if nothing mq mode configure, use default scheme */
2288                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2289                         break;
2290                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2291                         /* SRIOV only works in VMDq enable mode */
2292                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2293                                         " wrong mq_mode rx %d.",
2294                                         dev_conf->rxmode.mq_mode);
2295                         return -EINVAL;
2296                 }
2297
2298                 switch (dev_conf->txmode.mq_mode) {
2299                 case ETH_MQ_TX_VMDQ_DCB:
2300                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2301                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2302                         break;
2303                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2304                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2305                         break;
2306                 }
2307
2308                 /* check valid queue number */
2309                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2310                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2311                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2312                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2313                                         " must be less than or equal to %d.",
2314                                         nb_rx_q, nb_tx_q,
2315                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2316                         return -EINVAL;
2317                 }
2318         } else {
2319                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2320                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2321                                           " not supported.");
2322                         return -EINVAL;
2323                 }
2324                 /* check configuration for vmdb+dcb mode */
2325                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2326                         const struct rte_eth_vmdq_dcb_conf *conf;
2327
2328                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2329                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2330                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2331                                 return -EINVAL;
2332                         }
2333                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2334                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2335                                conf->nb_queue_pools == ETH_32_POOLS)) {
2336                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2337                                                 " nb_queue_pools must be %d or %d.",
2338                                                 ETH_16_POOLS, ETH_32_POOLS);
2339                                 return -EINVAL;
2340                         }
2341                 }
2342                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2343                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2344
2345                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2346                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2347                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2348                                 return -EINVAL;
2349                         }
2350                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2351                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2352                                conf->nb_queue_pools == ETH_32_POOLS)) {
2353                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2354                                                 " nb_queue_pools != %d and"
2355                                                 " nb_queue_pools != %d.",
2356                                                 ETH_16_POOLS, ETH_32_POOLS);
2357                                 return -EINVAL;
2358                         }
2359                 }
2360
2361                 /* For DCB mode check our configuration before we go further */
2362                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2363                         const struct rte_eth_dcb_rx_conf *conf;
2364
2365                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2366                         if (!(conf->nb_tcs == ETH_4_TCS ||
2367                                conf->nb_tcs == ETH_8_TCS)) {
2368                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2369                                                 " and nb_tcs != %d.",
2370                                                 ETH_4_TCS, ETH_8_TCS);
2371                                 return -EINVAL;
2372                         }
2373                 }
2374
2375                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2376                         const struct rte_eth_dcb_tx_conf *conf;
2377
2378                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2379                         if (!(conf->nb_tcs == ETH_4_TCS ||
2380                                conf->nb_tcs == ETH_8_TCS)) {
2381                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2382                                                 " and nb_tcs != %d.",
2383                                                 ETH_4_TCS, ETH_8_TCS);
2384                                 return -EINVAL;
2385                         }
2386                 }
2387
2388                 /*
2389                  * When DCB/VT is off, maximum number of queues changes,
2390                  * except for 82598EB, which remains constant.
2391                  */
2392                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2393                                 hw->mac.type != ixgbe_mac_82598EB) {
2394                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2395                                 PMD_INIT_LOG(ERR,
2396                                              "Neither VT nor DCB are enabled, "
2397                                              "nb_tx_q > %d.",
2398                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2399                                 return -EINVAL;
2400                         }
2401                 }
2402         }
2403         return 0;
2404 }
2405
2406 static int
2407 ixgbe_dev_configure(struct rte_eth_dev *dev)
2408 {
2409         struct ixgbe_interrupt *intr =
2410                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2411         struct ixgbe_adapter *adapter = dev->data->dev_private;
2412         int ret;
2413
2414         PMD_INIT_FUNC_TRACE();
2415         /* multipe queue mode checking */
2416         ret  = ixgbe_check_mq_mode(dev);
2417         if (ret != 0) {
2418                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2419                             ret);
2420                 return ret;
2421         }
2422
2423         /* set flag to update link status after init */
2424         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2425
2426         /*
2427          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2428          * allocation or vector Rx preconditions we will reset it.
2429          */
2430         adapter->rx_bulk_alloc_allowed = true;
2431         adapter->rx_vec_allowed = true;
2432
2433         return 0;
2434 }
2435
2436 static void
2437 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2438 {
2439         struct ixgbe_hw *hw =
2440                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2441         struct ixgbe_interrupt *intr =
2442                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2443         uint32_t gpie;
2444
2445         /* only set up it on X550EM_X */
2446         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2447                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2448                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2449                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2450                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2451                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2452         }
2453 }
2454
2455 int
2456 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2457                         uint16_t tx_rate, uint64_t q_msk)
2458 {
2459         struct ixgbe_hw *hw;
2460         struct ixgbe_vf_info *vfinfo;
2461         struct rte_eth_link link;
2462         uint8_t  nb_q_per_pool;
2463         uint32_t queue_stride;
2464         uint32_t queue_idx, idx = 0, vf_idx;
2465         uint32_t queue_end;
2466         uint16_t total_rate = 0;
2467         struct rte_pci_device *pci_dev;
2468
2469         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2470         rte_eth_link_get_nowait(dev->data->port_id, &link);
2471
2472         if (vf >= pci_dev->max_vfs)
2473                 return -EINVAL;
2474
2475         if (tx_rate > link.link_speed)
2476                 return -EINVAL;
2477
2478         if (q_msk == 0)
2479                 return 0;
2480
2481         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2482         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2483         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2484         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2485         queue_idx = vf * queue_stride;
2486         queue_end = queue_idx + nb_q_per_pool - 1;
2487         if (queue_end >= hw->mac.max_tx_queues)
2488                 return -EINVAL;
2489
2490         if (vfinfo) {
2491                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2492                         if (vf_idx == vf)
2493                                 continue;
2494                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2495                                 idx++)
2496                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2497                 }
2498         } else {
2499                 return -EINVAL;
2500         }
2501
2502         /* Store tx_rate for this vf. */
2503         for (idx = 0; idx < nb_q_per_pool; idx++) {
2504                 if (((uint64_t)0x1 << idx) & q_msk) {
2505                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2506                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2507                         total_rate += tx_rate;
2508                 }
2509         }
2510
2511         if (total_rate > dev->data->dev_link.link_speed) {
2512                 /* Reset stored TX rate of the VF if it causes exceed
2513                  * link speed.
2514                  */
2515                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2516                 return -EINVAL;
2517         }
2518
2519         /* Set RTTBCNRC of each queue/pool for vf X  */
2520         for (; queue_idx <= queue_end; queue_idx++) {
2521                 if (0x1 & q_msk)
2522                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2523                 q_msk = q_msk >> 1;
2524         }
2525
2526         return 0;
2527 }
2528
2529 /*
2530  * Configure device link speed and setup link.
2531  * It returns 0 on success.
2532  */
2533 static int
2534 ixgbe_dev_start(struct rte_eth_dev *dev)
2535 {
2536         struct ixgbe_hw *hw =
2537                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2538         struct ixgbe_vf_info *vfinfo =
2539                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2540         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2541         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2542         uint32_t intr_vector = 0;
2543         int err, link_up = 0, negotiate = 0;
2544         uint32_t speed = 0;
2545         uint32_t allowed_speeds = 0;
2546         int mask = 0;
2547         int status;
2548         uint16_t vf, idx;
2549         uint32_t *link_speeds;
2550         struct ixgbe_tm_conf *tm_conf =
2551                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2552
2553         PMD_INIT_FUNC_TRACE();
2554
2555         /* IXGBE devices don't support:
2556         *    - half duplex (checked afterwards for valid speeds)
2557         *    - fixed speed: TODO implement
2558         */
2559         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2560                 PMD_INIT_LOG(ERR,
2561                 "Invalid link_speeds for port %u, fix speed not supported",
2562                                 dev->data->port_id);
2563                 return -EINVAL;
2564         }
2565
2566         /* Stop the link setup handler before resetting the HW. */
2567         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2568
2569         /* disable uio/vfio intr/eventfd mapping */
2570         rte_intr_disable(intr_handle);
2571
2572         /* stop adapter */
2573         hw->adapter_stopped = 0;
2574         ixgbe_stop_adapter(hw);
2575
2576         /* reinitialize adapter
2577          * this calls reset and start
2578          */
2579         status = ixgbe_pf_reset_hw(hw);
2580         if (status != 0)
2581                 return -1;
2582         hw->mac.ops.start_hw(hw);
2583         hw->mac.get_link_status = true;
2584
2585         /* configure PF module if SRIOV enabled */
2586         ixgbe_pf_host_configure(dev);
2587
2588         ixgbe_dev_phy_intr_setup(dev);
2589
2590         /* check and configure queue intr-vector mapping */
2591         if ((rte_intr_cap_multiple(intr_handle) ||
2592              !RTE_ETH_DEV_SRIOV(dev).active) &&
2593             dev->data->dev_conf.intr_conf.rxq != 0) {
2594                 intr_vector = dev->data->nb_rx_queues;
2595                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2596                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2597                                         IXGBE_MAX_INTR_QUEUE_NUM);
2598                         return -ENOTSUP;
2599                 }
2600                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2601                         return -1;
2602         }
2603
2604         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2605                 intr_handle->intr_vec =
2606                         rte_zmalloc("intr_vec",
2607                                     dev->data->nb_rx_queues * sizeof(int), 0);
2608                 if (intr_handle->intr_vec == NULL) {
2609                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2610                                      " intr_vec", dev->data->nb_rx_queues);
2611                         return -ENOMEM;
2612                 }
2613         }
2614
2615         /* confiugre msix for sleep until rx interrupt */
2616         ixgbe_configure_msix(dev);
2617
2618         /* initialize transmission unit */
2619         ixgbe_dev_tx_init(dev);
2620
2621         /* This can fail when allocating mbufs for descriptor rings */
2622         err = ixgbe_dev_rx_init(dev);
2623         if (err) {
2624                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2625                 goto error;
2626         }
2627
2628         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2629                 ETH_VLAN_EXTEND_MASK;
2630         err = ixgbe_vlan_offload_config(dev, mask);
2631         if (err) {
2632                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2633                 goto error;
2634         }
2635
2636         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2637                 /* Enable vlan filtering for VMDq */
2638                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2639         }
2640
2641         /* Configure DCB hw */
2642         ixgbe_configure_dcb(dev);
2643
2644         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2645                 err = ixgbe_fdir_configure(dev);
2646                 if (err)
2647                         goto error;
2648         }
2649
2650         /* Restore vf rate limit */
2651         if (vfinfo != NULL) {
2652                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2653                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2654                                 if (vfinfo[vf].tx_rate[idx] != 0)
2655                                         ixgbe_set_vf_rate_limit(
2656                                                 dev, vf,
2657                                                 vfinfo[vf].tx_rate[idx],
2658                                                 1 << idx);
2659         }
2660
2661         ixgbe_restore_statistics_mapping(dev);
2662
2663         err = ixgbe_dev_rxtx_start(dev);
2664         if (err < 0) {
2665                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2666                 goto error;
2667         }
2668
2669         /* Skip link setup if loopback mode is enabled. */
2670         if (dev->data->dev_conf.lpbk_mode != 0) {
2671                 err = ixgbe_check_supported_loopback_mode(dev);
2672                 if (err < 0) {
2673                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2674                         goto error;
2675                 } else {
2676                         goto skip_link_setup;
2677                 }
2678         }
2679
2680         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2681                 err = hw->mac.ops.setup_sfp(hw);
2682                 if (err)
2683                         goto error;
2684         }
2685
2686         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2687                 /* Turn on the copper */
2688                 ixgbe_set_phy_power(hw, true);
2689         } else {
2690                 /* Turn on the laser */
2691                 ixgbe_enable_tx_laser(hw);
2692         }
2693
2694         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2695         if (err)
2696                 goto error;
2697         dev->data->dev_link.link_status = link_up;
2698
2699         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2700         if (err)
2701                 goto error;
2702
2703         switch (hw->mac.type) {
2704         case ixgbe_mac_X550:
2705         case ixgbe_mac_X550EM_x:
2706         case ixgbe_mac_X550EM_a:
2707                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2708                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2709                         ETH_LINK_SPEED_10G;
2710                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2711                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2712                         allowed_speeds = ETH_LINK_SPEED_10M |
2713                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2714                 break;
2715         default:
2716                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2717                         ETH_LINK_SPEED_10G;
2718         }
2719
2720         link_speeds = &dev->data->dev_conf.link_speeds;
2721         if (*link_speeds & ~allowed_speeds) {
2722                 PMD_INIT_LOG(ERR, "Invalid link setting");
2723                 goto error;
2724         }
2725
2726         speed = 0x0;
2727         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2728                 switch (hw->mac.type) {
2729                 case ixgbe_mac_82598EB:
2730                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2731                         break;
2732                 case ixgbe_mac_82599EB:
2733                 case ixgbe_mac_X540:
2734                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2735                         break;
2736                 case ixgbe_mac_X550:
2737                 case ixgbe_mac_X550EM_x:
2738                 case ixgbe_mac_X550EM_a:
2739                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2740                         break;
2741                 default:
2742                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2743                 }
2744         } else {
2745                 if (*link_speeds & ETH_LINK_SPEED_10G)
2746                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2747                 if (*link_speeds & ETH_LINK_SPEED_5G)
2748                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2749                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2750                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2751                 if (*link_speeds & ETH_LINK_SPEED_1G)
2752                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2753                 if (*link_speeds & ETH_LINK_SPEED_100M)
2754                         speed |= IXGBE_LINK_SPEED_100_FULL;
2755                 if (*link_speeds & ETH_LINK_SPEED_10M)
2756                         speed |= IXGBE_LINK_SPEED_10_FULL;
2757         }
2758
2759         err = ixgbe_setup_link(hw, speed, link_up);
2760         if (err)
2761                 goto error;
2762
2763 skip_link_setup:
2764
2765         if (rte_intr_allow_others(intr_handle)) {
2766                 /* check if lsc interrupt is enabled */
2767                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2768                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2769                 else
2770                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2771                 ixgbe_dev_macsec_interrupt_setup(dev);
2772         } else {
2773                 rte_intr_callback_unregister(intr_handle,
2774                                              ixgbe_dev_interrupt_handler, dev);
2775                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2776                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2777                                      " no intr multiplex");
2778         }
2779
2780         /* check if rxq interrupt is enabled */
2781         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2782             rte_intr_dp_is_en(intr_handle))
2783                 ixgbe_dev_rxq_interrupt_setup(dev);
2784
2785         /* enable uio/vfio intr/eventfd mapping */
2786         rte_intr_enable(intr_handle);
2787
2788         /* resume enabled intr since hw reset */
2789         ixgbe_enable_intr(dev);
2790         ixgbe_l2_tunnel_conf(dev);
2791         ixgbe_filter_restore(dev);
2792
2793         if (tm_conf->root && !tm_conf->committed)
2794                 PMD_DRV_LOG(WARNING,
2795                             "please call hierarchy_commit() "
2796                             "before starting the port");
2797
2798         /*
2799          * Update link status right before return, because it may
2800          * start link configuration process in a separate thread.
2801          */
2802         ixgbe_dev_link_update(dev, 0);
2803
2804         return 0;
2805
2806 error:
2807         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2808         ixgbe_dev_clear_queues(dev);
2809         return -EIO;
2810 }
2811
2812 /*
2813  * Stop device: disable rx and tx functions to allow for reconfiguring.
2814  */
2815 static void
2816 ixgbe_dev_stop(struct rte_eth_dev *dev)
2817 {
2818         struct rte_eth_link link;
2819         struct ixgbe_adapter *adapter = dev->data->dev_private;
2820         struct ixgbe_hw *hw =
2821                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2822         struct ixgbe_vf_info *vfinfo =
2823                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2824         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2825         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2826         int vf;
2827         struct ixgbe_tm_conf *tm_conf =
2828                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2829
2830         PMD_INIT_FUNC_TRACE();
2831
2832         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2833
2834         /* disable interrupts */
2835         ixgbe_disable_intr(hw);
2836
2837         /* reset the NIC */
2838         ixgbe_pf_reset_hw(hw);
2839         hw->adapter_stopped = 0;
2840
2841         /* stop adapter */
2842         ixgbe_stop_adapter(hw);
2843
2844         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2845                 vfinfo[vf].clear_to_send = false;
2846
2847         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2848                 /* Turn off the copper */
2849                 ixgbe_set_phy_power(hw, false);
2850         } else {
2851                 /* Turn off the laser */
2852                 ixgbe_disable_tx_laser(hw);
2853         }
2854
2855         ixgbe_dev_clear_queues(dev);
2856
2857         /* Clear stored conf */
2858         dev->data->scattered_rx = 0;
2859         dev->data->lro = 0;
2860
2861         /* Clear recorded link status */
2862         memset(&link, 0, sizeof(link));
2863         rte_eth_linkstatus_set(dev, &link);
2864
2865         if (!rte_intr_allow_others(intr_handle))
2866                 /* resume to the default handler */
2867                 rte_intr_callback_register(intr_handle,
2868                                            ixgbe_dev_interrupt_handler,
2869                                            (void *)dev);
2870
2871         /* Clean datapath event and queue/vec mapping */
2872         rte_intr_efd_disable(intr_handle);
2873         if (intr_handle->intr_vec != NULL) {
2874                 rte_free(intr_handle->intr_vec);
2875                 intr_handle->intr_vec = NULL;
2876         }
2877
2878         /* reset hierarchy commit */
2879         tm_conf->committed = false;
2880
2881         adapter->rss_reta_updated = 0;
2882 }
2883
2884 /*
2885  * Set device link up: enable tx.
2886  */
2887 static int
2888 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2889 {
2890         struct ixgbe_hw *hw =
2891                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2892         if (hw->mac.type == ixgbe_mac_82599EB) {
2893 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2894                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2895                         /* Not suported in bypass mode */
2896                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2897                                      "by device id 0x%x", hw->device_id);
2898                         return -ENOTSUP;
2899                 }
2900 #endif
2901         }
2902
2903         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2904                 /* Turn on the copper */
2905                 ixgbe_set_phy_power(hw, true);
2906         } else {
2907                 /* Turn on the laser */
2908                 ixgbe_enable_tx_laser(hw);
2909         }
2910
2911         return 0;
2912 }
2913
2914 /*
2915  * Set device link down: disable tx.
2916  */
2917 static int
2918 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2919 {
2920         struct ixgbe_hw *hw =
2921                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2922         if (hw->mac.type == ixgbe_mac_82599EB) {
2923 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2924                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2925                         /* Not suported in bypass mode */
2926                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2927                                      "by device id 0x%x", hw->device_id);
2928                         return -ENOTSUP;
2929                 }
2930 #endif
2931         }
2932
2933         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2934                 /* Turn off the copper */
2935                 ixgbe_set_phy_power(hw, false);
2936         } else {
2937                 /* Turn off the laser */
2938                 ixgbe_disable_tx_laser(hw);
2939         }
2940
2941         return 0;
2942 }
2943
2944 /*
2945  * Reset and stop device.
2946  */
2947 static void
2948 ixgbe_dev_close(struct rte_eth_dev *dev)
2949 {
2950         struct ixgbe_hw *hw =
2951                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2952
2953         PMD_INIT_FUNC_TRACE();
2954
2955         ixgbe_pf_reset_hw(hw);
2956
2957         ixgbe_dev_stop(dev);
2958         hw->adapter_stopped = 1;
2959
2960         ixgbe_dev_free_queues(dev);
2961
2962         ixgbe_disable_pcie_master(hw);
2963
2964         /* reprogram the RAR[0] in case user changed it. */
2965         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2966 }
2967
2968 /*
2969  * Reset PF device.
2970  */
2971 static int
2972 ixgbe_dev_reset(struct rte_eth_dev *dev)
2973 {
2974         int ret;
2975
2976         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2977          * its VF to make them align with it. The detailed notification
2978          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2979          * To avoid unexpected behavior in VF, currently reset of PF with
2980          * SR-IOV activation is not supported. It might be supported later.
2981          */
2982         if (dev->data->sriov.active)
2983                 return -ENOTSUP;
2984
2985         ret = eth_ixgbe_dev_uninit(dev);
2986         if (ret)
2987                 return ret;
2988
2989         ret = eth_ixgbe_dev_init(dev, NULL);
2990
2991         return ret;
2992 }
2993
2994 static void
2995 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2996                            struct ixgbe_hw_stats *hw_stats,
2997                            struct ixgbe_macsec_stats *macsec_stats,
2998                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2999                            uint64_t *total_qprc, uint64_t *total_qprdc)
3000 {
3001         uint32_t bprc, lxon, lxoff, total;
3002         uint32_t delta_gprc = 0;
3003         unsigned i;
3004         /* Workaround for RX byte count not including CRC bytes when CRC
3005          * strip is enabled. CRC bytes are removed from counters when crc_strip
3006          * is disabled.
3007          */
3008         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3009                         IXGBE_HLREG0_RXCRCSTRP);
3010
3011         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3012         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3013         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3014         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3015
3016         for (i = 0; i < 8; i++) {
3017                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3018
3019                 /* global total per queue */
3020                 hw_stats->mpc[i] += mp;
3021                 /* Running comprehensive total for stats display */
3022                 *total_missed_rx += hw_stats->mpc[i];
3023                 if (hw->mac.type == ixgbe_mac_82598EB) {
3024                         hw_stats->rnbc[i] +=
3025                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3026                         hw_stats->pxonrxc[i] +=
3027                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3028                         hw_stats->pxoffrxc[i] +=
3029                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3030                 } else {
3031                         hw_stats->pxonrxc[i] +=
3032                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3033                         hw_stats->pxoffrxc[i] +=
3034                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3035                         hw_stats->pxon2offc[i] +=
3036                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3037                 }
3038                 hw_stats->pxontxc[i] +=
3039                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3040                 hw_stats->pxofftxc[i] +=
3041                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3042         }
3043         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3044                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3045                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3046                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3047
3048                 delta_gprc += delta_qprc;
3049
3050                 hw_stats->qprc[i] += delta_qprc;
3051                 hw_stats->qptc[i] += delta_qptc;
3052
3053                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3054                 hw_stats->qbrc[i] +=
3055                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3056                 if (crc_strip == 0)
3057                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3058
3059                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3060                 hw_stats->qbtc[i] +=
3061                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3062
3063                 hw_stats->qprdc[i] += delta_qprdc;
3064                 *total_qprdc += hw_stats->qprdc[i];
3065
3066                 *total_qprc += hw_stats->qprc[i];
3067                 *total_qbrc += hw_stats->qbrc[i];
3068         }
3069         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3070         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3071         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3072
3073         /*
3074          * An errata states that gprc actually counts good + missed packets:
3075          * Workaround to set gprc to summated queue packet receives
3076          */
3077         hw_stats->gprc = *total_qprc;
3078
3079         if (hw->mac.type != ixgbe_mac_82598EB) {
3080                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3081                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3082                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3083                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3084                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3085                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3086                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3087                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3088         } else {
3089                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3090                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3091                 /* 82598 only has a counter in the high register */
3092                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3093                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3094                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3095         }
3096         uint64_t old_tpr = hw_stats->tpr;
3097
3098         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3099         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3100
3101         if (crc_strip == 0)
3102                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3103
3104         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3105         hw_stats->gptc += delta_gptc;
3106         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3107         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3108
3109         /*
3110          * Workaround: mprc hardware is incorrectly counting
3111          * broadcasts, so for now we subtract those.
3112          */
3113         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3114         hw_stats->bprc += bprc;
3115         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3116         if (hw->mac.type == ixgbe_mac_82598EB)
3117                 hw_stats->mprc -= bprc;
3118
3119         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3120         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3121         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3122         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3123         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3124         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3125
3126         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3127         hw_stats->lxontxc += lxon;
3128         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3129         hw_stats->lxofftxc += lxoff;
3130         total = lxon + lxoff;
3131
3132         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3133         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3134         hw_stats->gptc -= total;
3135         hw_stats->mptc -= total;
3136         hw_stats->ptc64 -= total;
3137         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3138
3139         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3140         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3141         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3142         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3143         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3144         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3145         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3146         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3147         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3148         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3149         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3150         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3151         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3152         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3153         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3154         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3155         /* Only read FCOE on 82599 */
3156         if (hw->mac.type != ixgbe_mac_82598EB) {
3157                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3158                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3159                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3160                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3161                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3162         }
3163
3164         /* Flow Director Stats registers */
3165         if (hw->mac.type != ixgbe_mac_82598EB) {
3166                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3167                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3168                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3169                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3170                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3171                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3172                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3173                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3174                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3175                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3176         }
3177         /* MACsec Stats registers */
3178         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3179         macsec_stats->out_pkts_encrypted +=
3180                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3181         macsec_stats->out_pkts_protected +=
3182                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3183         macsec_stats->out_octets_encrypted +=
3184                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3185         macsec_stats->out_octets_protected +=
3186                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3187         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3188         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3189         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3190         macsec_stats->in_pkts_unknownsci +=
3191                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3192         macsec_stats->in_octets_decrypted +=
3193                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3194         macsec_stats->in_octets_validated +=
3195                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3196         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3197         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3198         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3199         for (i = 0; i < 2; i++) {
3200                 macsec_stats->in_pkts_ok +=
3201                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3202                 macsec_stats->in_pkts_invalid +=
3203                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3204                 macsec_stats->in_pkts_notvalid +=
3205                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3206         }
3207         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3208         macsec_stats->in_pkts_notusingsa +=
3209                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3210 }
3211
3212 /*
3213  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3214  */
3215 static int
3216 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3217 {
3218         struct ixgbe_hw *hw =
3219                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3220         struct ixgbe_hw_stats *hw_stats =
3221                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3222         struct ixgbe_macsec_stats *macsec_stats =
3223                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3224                                 dev->data->dev_private);
3225         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3226         unsigned i;
3227
3228         total_missed_rx = 0;
3229         total_qbrc = 0;
3230         total_qprc = 0;
3231         total_qprdc = 0;
3232
3233         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3234                         &total_qbrc, &total_qprc, &total_qprdc);
3235
3236         if (stats == NULL)
3237                 return -EINVAL;
3238
3239         /* Fill out the rte_eth_stats statistics structure */
3240         stats->ipackets = total_qprc;
3241         stats->ibytes = total_qbrc;
3242         stats->opackets = hw_stats->gptc;
3243         stats->obytes = hw_stats->gotc;
3244
3245         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3246                 stats->q_ipackets[i] = hw_stats->qprc[i];
3247                 stats->q_opackets[i] = hw_stats->qptc[i];
3248                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3249                 stats->q_obytes[i] = hw_stats->qbtc[i];
3250                 stats->q_errors[i] = hw_stats->qprdc[i];
3251         }
3252
3253         /* Rx Errors */
3254         stats->imissed  = total_missed_rx;
3255         stats->ierrors  = hw_stats->crcerrs +
3256                           hw_stats->mspdc +
3257                           hw_stats->rlec +
3258                           hw_stats->ruc +
3259                           hw_stats->roc +
3260                           hw_stats->illerrc +
3261                           hw_stats->errbc +
3262                           hw_stats->rfc +
3263                           hw_stats->fccrc +
3264                           hw_stats->fclast;
3265
3266         /* Tx Errors */
3267         stats->oerrors  = 0;
3268         return 0;
3269 }
3270
3271 static void
3272 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3273 {
3274         struct ixgbe_hw_stats *stats =
3275                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3276
3277         /* HW registers are cleared on read */
3278         ixgbe_dev_stats_get(dev, NULL);
3279
3280         /* Reset software totals */
3281         memset(stats, 0, sizeof(*stats));
3282 }
3283
3284 /* This function calculates the number of xstats based on the current config */
3285 static unsigned
3286 ixgbe_xstats_calc_num(void) {
3287         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3288                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3289                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3290 }
3291
3292 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3293         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3294 {
3295         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3296         unsigned stat, i, count;
3297
3298         if (xstats_names != NULL) {
3299                 count = 0;
3300
3301                 /* Note: limit >= cnt_stats checked upstream
3302                  * in rte_eth_xstats_names()
3303                  */
3304
3305                 /* Extended stats from ixgbe_hw_stats */
3306                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3307                         strlcpy(xstats_names[count].name,
3308                                 rte_ixgbe_stats_strings[i].name,
3309                                 sizeof(xstats_names[count].name));
3310                         count++;
3311                 }
3312
3313                 /* MACsec Stats */
3314                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3315                         strlcpy(xstats_names[count].name,
3316                                 rte_ixgbe_macsec_strings[i].name,
3317                                 sizeof(xstats_names[count].name));
3318                         count++;
3319                 }
3320
3321                 /* RX Priority Stats */
3322                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3323                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3324                                 snprintf(xstats_names[count].name,
3325                                         sizeof(xstats_names[count].name),
3326                                         "rx_priority%u_%s", i,
3327                                         rte_ixgbe_rxq_strings[stat].name);
3328                                 count++;
3329                         }
3330                 }
3331
3332                 /* TX Priority Stats */
3333                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3334                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3335                                 snprintf(xstats_names[count].name,
3336                                         sizeof(xstats_names[count].name),
3337                                         "tx_priority%u_%s", i,
3338                                         rte_ixgbe_txq_strings[stat].name);
3339                                 count++;
3340                         }
3341                 }
3342         }
3343         return cnt_stats;
3344 }
3345
3346 static int ixgbe_dev_xstats_get_names_by_id(
3347         struct rte_eth_dev *dev,
3348         struct rte_eth_xstat_name *xstats_names,
3349         const uint64_t *ids,
3350         unsigned int limit)
3351 {
3352         if (!ids) {
3353                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3354                 unsigned int stat, i, count;
3355
3356                 if (xstats_names != NULL) {
3357                         count = 0;
3358
3359                         /* Note: limit >= cnt_stats checked upstream
3360                          * in rte_eth_xstats_names()
3361                          */
3362
3363                         /* Extended stats from ixgbe_hw_stats */
3364                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3365                                 strlcpy(xstats_names[count].name,
3366                                         rte_ixgbe_stats_strings[i].name,
3367                                         sizeof(xstats_names[count].name));
3368                                 count++;
3369                         }
3370
3371                         /* MACsec Stats */
3372                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3373                                 strlcpy(xstats_names[count].name,
3374                                         rte_ixgbe_macsec_strings[i].name,
3375                                         sizeof(xstats_names[count].name));
3376                                 count++;
3377                         }
3378
3379                         /* RX Priority Stats */
3380                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3381                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3382                                         snprintf(xstats_names[count].name,
3383                                             sizeof(xstats_names[count].name),
3384                                             "rx_priority%u_%s", i,
3385                                             rte_ixgbe_rxq_strings[stat].name);
3386                                         count++;
3387                                 }
3388                         }
3389
3390                         /* TX Priority Stats */
3391                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3392                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3393                                         snprintf(xstats_names[count].name,
3394                                             sizeof(xstats_names[count].name),
3395                                             "tx_priority%u_%s", i,
3396                                             rte_ixgbe_txq_strings[stat].name);
3397                                         count++;
3398                                 }
3399                         }
3400                 }
3401                 return cnt_stats;
3402         }
3403
3404         uint16_t i;
3405         uint16_t size = ixgbe_xstats_calc_num();
3406         struct rte_eth_xstat_name xstats_names_copy[size];
3407
3408         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3409                         size);
3410
3411         for (i = 0; i < limit; i++) {
3412                 if (ids[i] >= size) {
3413                         PMD_INIT_LOG(ERR, "id value isn't valid");
3414                         return -1;
3415                 }
3416                 strcpy(xstats_names[i].name,
3417                                 xstats_names_copy[ids[i]].name);
3418         }
3419         return limit;
3420 }
3421
3422 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3423         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3424 {
3425         unsigned i;
3426
3427         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3428                 return -ENOMEM;
3429
3430         if (xstats_names != NULL)
3431                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3432                         strlcpy(xstats_names[i].name,
3433                                 rte_ixgbevf_stats_strings[i].name,
3434                                 sizeof(xstats_names[i].name));
3435         return IXGBEVF_NB_XSTATS;
3436 }
3437
3438 static int
3439 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3440                                          unsigned n)
3441 {
3442         struct ixgbe_hw *hw =
3443                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3444         struct ixgbe_hw_stats *hw_stats =
3445                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3446         struct ixgbe_macsec_stats *macsec_stats =
3447                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3448                                 dev->data->dev_private);
3449         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3450         unsigned i, stat, count = 0;
3451
3452         count = ixgbe_xstats_calc_num();
3453
3454         if (n < count)
3455                 return count;
3456
3457         total_missed_rx = 0;
3458         total_qbrc = 0;
3459         total_qprc = 0;
3460         total_qprdc = 0;
3461
3462         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3463                         &total_qbrc, &total_qprc, &total_qprdc);
3464
3465         /* If this is a reset xstats is NULL, and we have cleared the
3466          * registers by reading them.
3467          */
3468         if (!xstats)
3469                 return 0;
3470
3471         /* Extended stats from ixgbe_hw_stats */
3472         count = 0;
3473         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3474                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3475                                 rte_ixgbe_stats_strings[i].offset);
3476                 xstats[count].id = count;
3477                 count++;
3478         }
3479
3480         /* MACsec Stats */
3481         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3482                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3483                                 rte_ixgbe_macsec_strings[i].offset);
3484                 xstats[count].id = count;
3485                 count++;
3486         }
3487
3488         /* RX Priority Stats */
3489         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3490                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3491                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3492                                         rte_ixgbe_rxq_strings[stat].offset +
3493                                         (sizeof(uint64_t) * i));
3494                         xstats[count].id = count;
3495                         count++;
3496                 }
3497         }
3498
3499         /* TX Priority Stats */
3500         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3501                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3502                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3503                                         rte_ixgbe_txq_strings[stat].offset +
3504                                         (sizeof(uint64_t) * i));
3505                         xstats[count].id = count;
3506                         count++;
3507                 }
3508         }
3509         return count;
3510 }
3511
3512 static int
3513 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3514                 uint64_t *values, unsigned int n)
3515 {
3516         if (!ids) {
3517                 struct ixgbe_hw *hw =
3518                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3519                 struct ixgbe_hw_stats *hw_stats =
3520                                 IXGBE_DEV_PRIVATE_TO_STATS(
3521                                                 dev->data->dev_private);
3522                 struct ixgbe_macsec_stats *macsec_stats =
3523                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3524                                         dev->data->dev_private);
3525                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3526                 unsigned int i, stat, count = 0;
3527
3528                 count = ixgbe_xstats_calc_num();
3529
3530                 if (!ids && n < count)
3531                         return count;
3532
3533                 total_missed_rx = 0;
3534                 total_qbrc = 0;
3535                 total_qprc = 0;
3536                 total_qprdc = 0;
3537
3538                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3539                                 &total_missed_rx, &total_qbrc, &total_qprc,
3540                                 &total_qprdc);
3541
3542                 /* If this is a reset xstats is NULL, and we have cleared the
3543                  * registers by reading them.
3544                  */
3545                 if (!ids && !values)
3546                         return 0;
3547
3548                 /* Extended stats from ixgbe_hw_stats */
3549                 count = 0;
3550                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3551                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3552                                         rte_ixgbe_stats_strings[i].offset);
3553                         count++;
3554                 }
3555
3556                 /* MACsec Stats */
3557                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3558                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3559                                         rte_ixgbe_macsec_strings[i].offset);
3560                         count++;
3561                 }
3562
3563                 /* RX Priority Stats */
3564                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3565                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3566                                 values[count] =
3567                                         *(uint64_t *)(((char *)hw_stats) +
3568                                         rte_ixgbe_rxq_strings[stat].offset +
3569                                         (sizeof(uint64_t) * i));
3570                                 count++;
3571                         }
3572                 }
3573
3574                 /* TX Priority Stats */
3575                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3576                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3577                                 values[count] =
3578                                         *(uint64_t *)(((char *)hw_stats) +
3579                                         rte_ixgbe_txq_strings[stat].offset +
3580                                         (sizeof(uint64_t) * i));
3581                                 count++;
3582                         }
3583                 }
3584                 return count;
3585         }
3586
3587         uint16_t i;
3588         uint16_t size = ixgbe_xstats_calc_num();
3589         uint64_t values_copy[size];
3590
3591         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3592
3593         for (i = 0; i < n; i++) {
3594                 if (ids[i] >= size) {
3595                         PMD_INIT_LOG(ERR, "id value isn't valid");
3596                         return -1;
3597                 }
3598                 values[i] = values_copy[ids[i]];
3599         }
3600         return n;
3601 }
3602
3603 static void
3604 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3605 {
3606         struct ixgbe_hw_stats *stats =
3607                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3608         struct ixgbe_macsec_stats *macsec_stats =
3609                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3610                                 dev->data->dev_private);
3611
3612         unsigned count = ixgbe_xstats_calc_num();
3613
3614         /* HW registers are cleared on read */
3615         ixgbe_dev_xstats_get(dev, NULL, count);
3616
3617         /* Reset software totals */
3618         memset(stats, 0, sizeof(*stats));
3619         memset(macsec_stats, 0, sizeof(*macsec_stats));
3620 }
3621
3622 static void
3623 ixgbevf_update_stats(struct rte_eth_dev *dev)
3624 {
3625         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3626         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3627                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3628
3629         /* Good Rx packet, include VF loopback */
3630         UPDATE_VF_STAT(IXGBE_VFGPRC,
3631             hw_stats->last_vfgprc, hw_stats->vfgprc);
3632
3633         /* Good Rx octets, include VF loopback */
3634         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3635             hw_stats->last_vfgorc, hw_stats->vfgorc);
3636
3637         /* Good Tx packet, include VF loopback */
3638         UPDATE_VF_STAT(IXGBE_VFGPTC,
3639             hw_stats->last_vfgptc, hw_stats->vfgptc);
3640
3641         /* Good Tx octets, include VF loopback */
3642         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3643             hw_stats->last_vfgotc, hw_stats->vfgotc);
3644
3645         /* Rx Multicst Packet */
3646         UPDATE_VF_STAT(IXGBE_VFMPRC,
3647             hw_stats->last_vfmprc, hw_stats->vfmprc);
3648 }
3649
3650 static int
3651 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3652                        unsigned n)
3653 {
3654         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3655                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3656         unsigned i;
3657
3658         if (n < IXGBEVF_NB_XSTATS)
3659                 return IXGBEVF_NB_XSTATS;
3660
3661         ixgbevf_update_stats(dev);
3662
3663         if (!xstats)
3664                 return 0;
3665
3666         /* Extended stats */
3667         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3668                 xstats[i].id = i;
3669                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3670                         rte_ixgbevf_stats_strings[i].offset);
3671         }
3672
3673         return IXGBEVF_NB_XSTATS;
3674 }
3675
3676 static int
3677 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3678 {
3679         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3680                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3681
3682         ixgbevf_update_stats(dev);
3683
3684         if (stats == NULL)
3685                 return -EINVAL;
3686
3687         stats->ipackets = hw_stats->vfgprc;
3688         stats->ibytes = hw_stats->vfgorc;
3689         stats->opackets = hw_stats->vfgptc;
3690         stats->obytes = hw_stats->vfgotc;
3691         return 0;
3692 }
3693
3694 static void
3695 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3696 {
3697         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3698                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3699
3700         /* Sync HW register to the last stats */
3701         ixgbevf_dev_stats_get(dev, NULL);
3702
3703         /* reset HW current stats*/
3704         hw_stats->vfgprc = 0;
3705         hw_stats->vfgorc = 0;
3706         hw_stats->vfgptc = 0;
3707         hw_stats->vfgotc = 0;
3708 }
3709
3710 static int
3711 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3712 {
3713         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3714         u16 eeprom_verh, eeprom_verl;
3715         u32 etrack_id;
3716         int ret;
3717
3718         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3719         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3720
3721         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3722         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3723
3724         ret += 1; /* add the size of '\0' */
3725         if (fw_size < (u32)ret)
3726                 return ret;
3727         else
3728                 return 0;
3729 }
3730
3731 static void
3732 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3733 {
3734         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3735         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3736         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3737
3738         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3739         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3740         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3741                 /*
3742                  * When DCB/VT is off, maximum number of queues changes,
3743                  * except for 82598EB, which remains constant.
3744                  */
3745                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3746                                 hw->mac.type != ixgbe_mac_82598EB)
3747                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3748         }
3749         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3750         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3751         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3752         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3753         dev_info->max_vfs = pci_dev->max_vfs;
3754         if (hw->mac.type == ixgbe_mac_82598EB)
3755                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3756         else
3757                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3758         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3759         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3760         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3761         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3762         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3763                                      dev_info->rx_queue_offload_capa);
3764         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3765         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3766
3767         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3768                 .rx_thresh = {
3769                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3770                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3771                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3772                 },
3773                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3774                 .rx_drop_en = 0,
3775                 .offloads = 0,
3776         };
3777
3778         dev_info->default_txconf = (struct rte_eth_txconf) {
3779                 .tx_thresh = {
3780                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3781                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3782                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3783                 },
3784                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3785                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3786                 .offloads = 0,
3787         };
3788
3789         dev_info->rx_desc_lim = rx_desc_lim;
3790         dev_info->tx_desc_lim = tx_desc_lim;
3791
3792         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3793         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3794         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3795
3796         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3797         if (hw->mac.type == ixgbe_mac_X540 ||
3798             hw->mac.type == ixgbe_mac_X540_vf ||
3799             hw->mac.type == ixgbe_mac_X550 ||
3800             hw->mac.type == ixgbe_mac_X550_vf) {
3801                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3802         }
3803         if (hw->mac.type == ixgbe_mac_X550) {
3804                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3805                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3806         }
3807
3808         /* Driver-preferred Rx/Tx parameters */
3809         dev_info->default_rxportconf.burst_size = 32;
3810         dev_info->default_txportconf.burst_size = 32;
3811         dev_info->default_rxportconf.nb_queues = 1;
3812         dev_info->default_txportconf.nb_queues = 1;
3813         dev_info->default_rxportconf.ring_size = 256;
3814         dev_info->default_txportconf.ring_size = 256;
3815 }
3816
3817 static const uint32_t *
3818 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3819 {
3820         static const uint32_t ptypes[] = {
3821                 /* For non-vec functions,
3822                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3823                  * for vec functions,
3824                  * refers to _recv_raw_pkts_vec().
3825                  */
3826                 RTE_PTYPE_L2_ETHER,
3827                 RTE_PTYPE_L3_IPV4,
3828                 RTE_PTYPE_L3_IPV4_EXT,
3829                 RTE_PTYPE_L3_IPV6,
3830                 RTE_PTYPE_L3_IPV6_EXT,
3831                 RTE_PTYPE_L4_SCTP,
3832                 RTE_PTYPE_L4_TCP,
3833                 RTE_PTYPE_L4_UDP,
3834                 RTE_PTYPE_TUNNEL_IP,
3835                 RTE_PTYPE_INNER_L3_IPV6,
3836                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3837                 RTE_PTYPE_INNER_L4_TCP,
3838                 RTE_PTYPE_INNER_L4_UDP,
3839                 RTE_PTYPE_UNKNOWN
3840         };
3841
3842         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3843             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3844             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3845             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3846                 return ptypes;
3847
3848 #if defined(RTE_ARCH_X86)
3849         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3850             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3851                 return ptypes;
3852 #endif
3853         return NULL;
3854 }
3855
3856 static void
3857 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3858                      struct rte_eth_dev_info *dev_info)
3859 {
3860         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3861         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3862
3863         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3864         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3865         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3866         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3867         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3868         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3869         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3870         dev_info->max_vfs = pci_dev->max_vfs;
3871         if (hw->mac.type == ixgbe_mac_82598EB)
3872                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3873         else
3874                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3875         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3876         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3877                                      dev_info->rx_queue_offload_capa);
3878         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3879         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3880
3881         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3882                 .rx_thresh = {
3883                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3884                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3885                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3886                 },
3887                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3888                 .rx_drop_en = 0,
3889                 .offloads = 0,
3890         };
3891
3892         dev_info->default_txconf = (struct rte_eth_txconf) {
3893                 .tx_thresh = {
3894                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3895                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3896                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3897                 },
3898                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3899                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3900                 .offloads = 0,
3901         };
3902
3903         dev_info->rx_desc_lim = rx_desc_lim;
3904         dev_info->tx_desc_lim = tx_desc_lim;
3905 }
3906
3907 static int
3908 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3909                    int *link_up, int wait_to_complete)
3910 {
3911         struct ixgbe_mbx_info *mbx = &hw->mbx;
3912         struct ixgbe_mac_info *mac = &hw->mac;
3913         uint32_t links_reg, in_msg;
3914         int ret_val = 0;
3915
3916         /* If we were hit with a reset drop the link */
3917         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3918                 mac->get_link_status = true;
3919
3920         if (!mac->get_link_status)
3921                 goto out;
3922
3923         /* if link status is down no point in checking to see if pf is up */
3924         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3925         if (!(links_reg & IXGBE_LINKS_UP))
3926                 goto out;
3927
3928         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3929          * before the link status is correct
3930          */
3931         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3932                 int i;
3933
3934                 for (i = 0; i < 5; i++) {
3935                         rte_delay_us(100);
3936                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3937
3938                         if (!(links_reg & IXGBE_LINKS_UP))
3939                                 goto out;
3940                 }
3941         }
3942
3943         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3944         case IXGBE_LINKS_SPEED_10G_82599:
3945                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3946                 if (hw->mac.type >= ixgbe_mac_X550) {
3947                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3948                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3949                 }
3950                 break;
3951         case IXGBE_LINKS_SPEED_1G_82599:
3952                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3953                 break;
3954         case IXGBE_LINKS_SPEED_100_82599:
3955                 *speed = IXGBE_LINK_SPEED_100_FULL;
3956                 if (hw->mac.type == ixgbe_mac_X550) {
3957                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3958                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3959                 }
3960                 break;
3961         case IXGBE_LINKS_SPEED_10_X550EM_A:
3962                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3963                 /* Since Reserved in older MAC's */
3964                 if (hw->mac.type >= ixgbe_mac_X550)
3965                         *speed = IXGBE_LINK_SPEED_10_FULL;
3966                 break;
3967         default:
3968                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3969         }
3970
3971         /* if the read failed it could just be a mailbox collision, best wait
3972          * until we are called again and don't report an error
3973          */
3974         if (mbx->ops.read(hw, &in_msg, 1, 0))
3975                 goto out;
3976
3977         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3978                 /* msg is not CTS and is NACK we must have lost CTS status */
3979                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3980                         mac->get_link_status = false;
3981                 goto out;
3982         }
3983
3984         /* the pf is talking, if we timed out in the past we reinit */
3985         if (!mbx->timeout) {
3986                 ret_val = -1;
3987                 goto out;
3988         }
3989
3990         /* if we passed all the tests above then the link is up and we no
3991          * longer need to check for link
3992          */
3993         mac->get_link_status = false;
3994
3995 out:
3996         *link_up = !mac->get_link_status;
3997         return ret_val;
3998 }
3999
4000 static void
4001 ixgbe_dev_setup_link_alarm_handler(void *param)
4002 {
4003         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4004         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4005         struct ixgbe_interrupt *intr =
4006                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4007         u32 speed;
4008         bool autoneg = false;
4009
4010         speed = hw->phy.autoneg_advertised;
4011         if (!speed)
4012                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4013
4014         ixgbe_setup_link(hw, speed, true);
4015
4016         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4017 }
4018
4019 /* return 0 means link status changed, -1 means not changed */
4020 int
4021 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4022                             int wait_to_complete, int vf)
4023 {
4024         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4025         struct rte_eth_link link;
4026         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4027         struct ixgbe_interrupt *intr =
4028                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4029         int link_up;
4030         int diag;
4031         int wait = 1;
4032
4033         memset(&link, 0, sizeof(link));
4034         link.link_status = ETH_LINK_DOWN;
4035         link.link_speed = ETH_SPEED_NUM_NONE;
4036         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4037         link.link_autoneg = ETH_LINK_AUTONEG;
4038
4039         hw->mac.get_link_status = true;
4040
4041         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4042                 return rte_eth_linkstatus_set(dev, &link);
4043
4044         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4045         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4046                 wait = 0;
4047
4048         if (vf)
4049                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4050         else
4051                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4052
4053         if (diag != 0) {
4054                 link.link_speed = ETH_SPEED_NUM_100M;
4055                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4056                 return rte_eth_linkstatus_set(dev, &link);
4057         }
4058
4059         if (link_up == 0) {
4060                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4061                         intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4062                         rte_eal_alarm_set(10,
4063                                 ixgbe_dev_setup_link_alarm_handler, dev);
4064                 }
4065                 return rte_eth_linkstatus_set(dev, &link);
4066         }
4067
4068         link.link_status = ETH_LINK_UP;
4069         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4070
4071         switch (link_speed) {
4072         default:
4073         case IXGBE_LINK_SPEED_UNKNOWN:
4074                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4075                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4076                         link.link_speed = ETH_SPEED_NUM_10M;
4077                 else
4078                         link.link_speed = ETH_SPEED_NUM_100M;
4079                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4080                 break;
4081
4082         case IXGBE_LINK_SPEED_100_FULL:
4083                 link.link_speed = ETH_SPEED_NUM_100M;
4084                 break;
4085
4086         case IXGBE_LINK_SPEED_1GB_FULL:
4087                 link.link_speed = ETH_SPEED_NUM_1G;
4088                 break;
4089
4090         case IXGBE_LINK_SPEED_2_5GB_FULL:
4091                 link.link_speed = ETH_SPEED_NUM_2_5G;
4092                 break;
4093
4094         case IXGBE_LINK_SPEED_5GB_FULL:
4095                 link.link_speed = ETH_SPEED_NUM_5G;
4096                 break;
4097
4098         case IXGBE_LINK_SPEED_10GB_FULL:
4099                 link.link_speed = ETH_SPEED_NUM_10G;
4100                 break;
4101         }
4102
4103         return rte_eth_linkstatus_set(dev, &link);
4104 }
4105
4106 static int
4107 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4108 {
4109         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4110 }
4111
4112 static int
4113 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4114 {
4115         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4116 }
4117
4118 static void
4119 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4120 {
4121         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4122         uint32_t fctrl;
4123
4124         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4125         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4126         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4127 }
4128
4129 static void
4130 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4131 {
4132         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4133         uint32_t fctrl;
4134
4135         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4136         fctrl &= (~IXGBE_FCTRL_UPE);
4137         if (dev->data->all_multicast == 1)
4138                 fctrl |= IXGBE_FCTRL_MPE;
4139         else
4140                 fctrl &= (~IXGBE_FCTRL_MPE);
4141         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4142 }
4143
4144 static void
4145 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4146 {
4147         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4148         uint32_t fctrl;
4149
4150         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4151         fctrl |= IXGBE_FCTRL_MPE;
4152         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4153 }
4154
4155 static void
4156 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4157 {
4158         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4159         uint32_t fctrl;
4160
4161         if (dev->data->promiscuous == 1)
4162                 return; /* must remain in all_multicast mode */
4163
4164         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4165         fctrl &= (~IXGBE_FCTRL_MPE);
4166         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4167 }
4168
4169 /**
4170  * It clears the interrupt causes and enables the interrupt.
4171  * It will be called once only during nic initialized.
4172  *
4173  * @param dev
4174  *  Pointer to struct rte_eth_dev.
4175  * @param on
4176  *  Enable or Disable.
4177  *
4178  * @return
4179  *  - On success, zero.
4180  *  - On failure, a negative value.
4181  */
4182 static int
4183 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4184 {
4185         struct ixgbe_interrupt *intr =
4186                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4187
4188         ixgbe_dev_link_status_print(dev);
4189         if (on)
4190                 intr->mask |= IXGBE_EICR_LSC;
4191         else
4192                 intr->mask &= ~IXGBE_EICR_LSC;
4193
4194         return 0;
4195 }
4196
4197 /**
4198  * It clears the interrupt causes and enables the interrupt.
4199  * It will be called once only during nic initialized.
4200  *
4201  * @param dev
4202  *  Pointer to struct rte_eth_dev.
4203  *
4204  * @return
4205  *  - On success, zero.
4206  *  - On failure, a negative value.
4207  */
4208 static int
4209 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4210 {
4211         struct ixgbe_interrupt *intr =
4212                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4213
4214         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4215
4216         return 0;
4217 }
4218
4219 /**
4220  * It clears the interrupt causes and enables the interrupt.
4221  * It will be called once only during nic initialized.
4222  *
4223  * @param dev
4224  *  Pointer to struct rte_eth_dev.
4225  *
4226  * @return
4227  *  - On success, zero.
4228  *  - On failure, a negative value.
4229  */
4230 static int
4231 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4232 {
4233         struct ixgbe_interrupt *intr =
4234                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4235
4236         intr->mask |= IXGBE_EICR_LINKSEC;
4237
4238         return 0;
4239 }
4240
4241 /*
4242  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4243  *
4244  * @param dev
4245  *  Pointer to struct rte_eth_dev.
4246  *
4247  * @return
4248  *  - On success, zero.
4249  *  - On failure, a negative value.
4250  */
4251 static int
4252 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4253 {
4254         uint32_t eicr;
4255         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4256         struct ixgbe_interrupt *intr =
4257                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4258
4259         /* clear all cause mask */
4260         ixgbe_disable_intr(hw);
4261
4262         /* read-on-clear nic registers here */
4263         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4264         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4265
4266         intr->flags = 0;
4267
4268         /* set flag for async link update */
4269         if (eicr & IXGBE_EICR_LSC)
4270                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4271
4272         if (eicr & IXGBE_EICR_MAILBOX)
4273                 intr->flags |= IXGBE_FLAG_MAILBOX;
4274
4275         if (eicr & IXGBE_EICR_LINKSEC)
4276                 intr->flags |= IXGBE_FLAG_MACSEC;
4277
4278         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4279             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4280             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4281                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4282
4283         return 0;
4284 }
4285
4286 /**
4287  * It gets and then prints the link status.
4288  *
4289  * @param dev
4290  *  Pointer to struct rte_eth_dev.
4291  *
4292  * @return
4293  *  - On success, zero.
4294  *  - On failure, a negative value.
4295  */
4296 static void
4297 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4298 {
4299         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4300         struct rte_eth_link link;
4301
4302         rte_eth_linkstatus_get(dev, &link);
4303
4304         if (link.link_status) {
4305                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4306                                         (int)(dev->data->port_id),
4307                                         (unsigned)link.link_speed,
4308                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4309                                         "full-duplex" : "half-duplex");
4310         } else {
4311                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4312                                 (int)(dev->data->port_id));
4313         }
4314         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4315                                 pci_dev->addr.domain,
4316                                 pci_dev->addr.bus,
4317                                 pci_dev->addr.devid,
4318                                 pci_dev->addr.function);
4319 }
4320
4321 /*
4322  * It executes link_update after knowing an interrupt occurred.
4323  *
4324  * @param dev
4325  *  Pointer to struct rte_eth_dev.
4326  *
4327  * @return
4328  *  - On success, zero.
4329  *  - On failure, a negative value.
4330  */
4331 static int
4332 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4333 {
4334         struct ixgbe_interrupt *intr =
4335                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4336         int64_t timeout;
4337         struct ixgbe_hw *hw =
4338                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4339
4340         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4341
4342         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4343                 ixgbe_pf_mbx_process(dev);
4344                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4345         }
4346
4347         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4348                 ixgbe_handle_lasi(hw);
4349                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4350         }
4351
4352         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4353                 struct rte_eth_link link;
4354
4355                 /* get the link status before link update, for predicting later */
4356                 rte_eth_linkstatus_get(dev, &link);
4357
4358                 ixgbe_dev_link_update(dev, 0);
4359
4360                 /* likely to up */
4361                 if (!link.link_status)
4362                         /* handle it 1 sec later, wait it being stable */
4363                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4364                 /* likely to down */
4365                 else
4366                         /* handle it 4 sec later, wait it being stable */
4367                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4368
4369                 ixgbe_dev_link_status_print(dev);
4370                 if (rte_eal_alarm_set(timeout * 1000,
4371                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4372                         PMD_DRV_LOG(ERR, "Error setting alarm");
4373                 else {
4374                         /* remember original mask */
4375                         intr->mask_original = intr->mask;
4376                         /* only disable lsc interrupt */
4377                         intr->mask &= ~IXGBE_EIMS_LSC;
4378                 }
4379         }
4380
4381         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4382         ixgbe_enable_intr(dev);
4383
4384         return 0;
4385 }
4386
4387 /**
4388  * Interrupt handler which shall be registered for alarm callback for delayed
4389  * handling specific interrupt to wait for the stable nic state. As the
4390  * NIC interrupt state is not stable for ixgbe after link is just down,
4391  * it needs to wait 4 seconds to get the stable status.
4392  *
4393  * @param handle
4394  *  Pointer to interrupt handle.
4395  * @param param
4396  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4397  *
4398  * @return
4399  *  void
4400  */
4401 static void
4402 ixgbe_dev_interrupt_delayed_handler(void *param)
4403 {
4404         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4405         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4406         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4407         struct ixgbe_interrupt *intr =
4408                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4409         struct ixgbe_hw *hw =
4410                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4411         uint32_t eicr;
4412
4413         ixgbe_disable_intr(hw);
4414
4415         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4416         if (eicr & IXGBE_EICR_MAILBOX)
4417                 ixgbe_pf_mbx_process(dev);
4418
4419         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4420                 ixgbe_handle_lasi(hw);
4421                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4422         }
4423
4424         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4425                 ixgbe_dev_link_update(dev, 0);
4426                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4427                 ixgbe_dev_link_status_print(dev);
4428                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4429                                               NULL);
4430         }
4431
4432         if (intr->flags & IXGBE_FLAG_MACSEC) {
4433                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4434                                               NULL);
4435                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4436         }
4437
4438         /* restore original mask */
4439         intr->mask = intr->mask_original;
4440         intr->mask_original = 0;
4441
4442         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4443         ixgbe_enable_intr(dev);
4444         rte_intr_enable(intr_handle);
4445 }
4446
4447 /**
4448  * Interrupt handler triggered by NIC  for handling
4449  * specific interrupt.
4450  *
4451  * @param handle
4452  *  Pointer to interrupt handle.
4453  * @param param
4454  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4455  *
4456  * @return
4457  *  void
4458  */
4459 static void
4460 ixgbe_dev_interrupt_handler(void *param)
4461 {
4462         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4463
4464         ixgbe_dev_interrupt_get_status(dev);
4465         ixgbe_dev_interrupt_action(dev);
4466 }
4467
4468 static int
4469 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4470 {
4471         struct ixgbe_hw *hw;
4472
4473         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4474         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4475 }
4476
4477 static int
4478 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4479 {
4480         struct ixgbe_hw *hw;
4481
4482         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4483         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4484 }
4485
4486 static int
4487 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4488 {
4489         struct ixgbe_hw *hw;
4490         uint32_t mflcn_reg;
4491         uint32_t fccfg_reg;
4492         int rx_pause;
4493         int tx_pause;
4494
4495         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4496
4497         fc_conf->pause_time = hw->fc.pause_time;
4498         fc_conf->high_water = hw->fc.high_water[0];
4499         fc_conf->low_water = hw->fc.low_water[0];
4500         fc_conf->send_xon = hw->fc.send_xon;
4501         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4502
4503         /*
4504          * Return rx_pause status according to actual setting of
4505          * MFLCN register.
4506          */
4507         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4508         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4509                 rx_pause = 1;
4510         else
4511                 rx_pause = 0;
4512
4513         /*
4514          * Return tx_pause status according to actual setting of
4515          * FCCFG register.
4516          */
4517         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4518         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4519                 tx_pause = 1;
4520         else
4521                 tx_pause = 0;
4522
4523         if (rx_pause && tx_pause)
4524                 fc_conf->mode = RTE_FC_FULL;
4525         else if (rx_pause)
4526                 fc_conf->mode = RTE_FC_RX_PAUSE;
4527         else if (tx_pause)
4528                 fc_conf->mode = RTE_FC_TX_PAUSE;
4529         else
4530                 fc_conf->mode = RTE_FC_NONE;
4531
4532         return 0;
4533 }
4534
4535 static int
4536 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4537 {
4538         struct ixgbe_hw *hw;
4539         int err;
4540         uint32_t rx_buf_size;
4541         uint32_t max_high_water;
4542         uint32_t mflcn;
4543         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4544                 ixgbe_fc_none,
4545                 ixgbe_fc_rx_pause,
4546                 ixgbe_fc_tx_pause,
4547                 ixgbe_fc_full
4548         };
4549
4550         PMD_INIT_FUNC_TRACE();
4551
4552         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4553         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4554         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4555
4556         /*
4557          * At least reserve one Ethernet frame for watermark
4558          * high_water/low_water in kilo bytes for ixgbe
4559          */
4560         max_high_water = (rx_buf_size -
4561                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4562         if ((fc_conf->high_water > max_high_water) ||
4563                 (fc_conf->high_water < fc_conf->low_water)) {
4564                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4565                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4566                 return -EINVAL;
4567         }
4568
4569         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4570         hw->fc.pause_time     = fc_conf->pause_time;
4571         hw->fc.high_water[0]  = fc_conf->high_water;
4572         hw->fc.low_water[0]   = fc_conf->low_water;
4573         hw->fc.send_xon       = fc_conf->send_xon;
4574         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4575
4576         err = ixgbe_fc_enable(hw);
4577
4578         /* Not negotiated is not an error case */
4579         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4580
4581                 /* check if we want to forward MAC frames - driver doesn't have native
4582                  * capability to do that, so we'll write the registers ourselves */
4583
4584                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4585
4586                 /* set or clear MFLCN.PMCF bit depending on configuration */
4587                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4588                         mflcn |= IXGBE_MFLCN_PMCF;
4589                 else
4590                         mflcn &= ~IXGBE_MFLCN_PMCF;
4591
4592                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4593                 IXGBE_WRITE_FLUSH(hw);
4594
4595                 return 0;
4596         }
4597
4598         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4599         return -EIO;
4600 }
4601
4602 /**
4603  *  ixgbe_pfc_enable_generic - Enable flow control
4604  *  @hw: pointer to hardware structure
4605  *  @tc_num: traffic class number
4606  *  Enable flow control according to the current settings.
4607  */
4608 static int
4609 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4610 {
4611         int ret_val = 0;
4612         uint32_t mflcn_reg, fccfg_reg;
4613         uint32_t reg;
4614         uint32_t fcrtl, fcrth;
4615         uint8_t i;
4616         uint8_t nb_rx_en;
4617
4618         /* Validate the water mark configuration */
4619         if (!hw->fc.pause_time) {
4620                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4621                 goto out;
4622         }
4623
4624         /* Low water mark of zero causes XOFF floods */
4625         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4626                  /* High/Low water can not be 0 */
4627                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4628                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4629                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4630                         goto out;
4631                 }
4632
4633                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4634                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4635                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4636                         goto out;
4637                 }
4638         }
4639         /* Negotiate the fc mode to use */
4640         ixgbe_fc_autoneg(hw);
4641
4642         /* Disable any previous flow control settings */
4643         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4644         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4645
4646         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4647         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4648
4649         switch (hw->fc.current_mode) {
4650         case ixgbe_fc_none:
4651                 /*
4652                  * If the count of enabled RX Priority Flow control >1,
4653                  * and the TX pause can not be disabled
4654                  */
4655                 nb_rx_en = 0;
4656                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4657                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4658                         if (reg & IXGBE_FCRTH_FCEN)
4659                                 nb_rx_en++;
4660                 }
4661                 if (nb_rx_en > 1)
4662                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4663                 break;
4664         case ixgbe_fc_rx_pause:
4665                 /*
4666                  * Rx Flow control is enabled and Tx Flow control is
4667                  * disabled by software override. Since there really
4668                  * isn't a way to advertise that we are capable of RX
4669                  * Pause ONLY, we will advertise that we support both
4670                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4671                  * disable the adapter's ability to send PAUSE frames.
4672                  */
4673                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4674                 /*
4675                  * If the count of enabled RX Priority Flow control >1,
4676                  * and the TX pause can not be disabled
4677                  */
4678                 nb_rx_en = 0;
4679                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4680                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4681                         if (reg & IXGBE_FCRTH_FCEN)
4682                                 nb_rx_en++;
4683                 }
4684                 if (nb_rx_en > 1)
4685                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4686                 break;
4687         case ixgbe_fc_tx_pause:
4688                 /*
4689                  * Tx Flow control is enabled, and Rx Flow control is
4690                  * disabled by software override.
4691                  */
4692                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4693                 break;
4694         case ixgbe_fc_full:
4695                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4696                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4697                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4698                 break;
4699         default:
4700                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4701                 ret_val = IXGBE_ERR_CONFIG;
4702                 goto out;
4703         }
4704
4705         /* Set 802.3x based flow control settings. */
4706         mflcn_reg |= IXGBE_MFLCN_DPF;
4707         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4708         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4709
4710         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4711         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4712                 hw->fc.high_water[tc_num]) {
4713                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4714                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4715                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4716         } else {
4717                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4718                 /*
4719                  * In order to prevent Tx hangs when the internal Tx
4720                  * switch is enabled we must set the high water mark
4721                  * to the maximum FCRTH value.  This allows the Tx
4722                  * switch to function even under heavy Rx workloads.
4723                  */
4724                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4725         }
4726         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4727
4728         /* Configure pause time (2 TCs per register) */
4729         reg = hw->fc.pause_time * 0x00010001;
4730         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4731                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4732
4733         /* Configure flow control refresh threshold value */
4734         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4735
4736 out:
4737         return ret_val;
4738 }
4739
4740 static int
4741 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4742 {
4743         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4744         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4745
4746         if (hw->mac.type != ixgbe_mac_82598EB) {
4747                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4748         }
4749         return ret_val;
4750 }
4751
4752 static int
4753 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4754 {
4755         int err;
4756         uint32_t rx_buf_size;
4757         uint32_t max_high_water;
4758         uint8_t tc_num;
4759         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4760         struct ixgbe_hw *hw =
4761                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4762         struct ixgbe_dcb_config *dcb_config =
4763                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4764
4765         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4766                 ixgbe_fc_none,
4767                 ixgbe_fc_rx_pause,
4768                 ixgbe_fc_tx_pause,
4769                 ixgbe_fc_full
4770         };
4771
4772         PMD_INIT_FUNC_TRACE();
4773
4774         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4775         tc_num = map[pfc_conf->priority];
4776         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4777         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4778         /*
4779          * At least reserve one Ethernet frame for watermark
4780          * high_water/low_water in kilo bytes for ixgbe
4781          */
4782         max_high_water = (rx_buf_size -
4783                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4784         if ((pfc_conf->fc.high_water > max_high_water) ||
4785             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4786                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4787                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4788                 return -EINVAL;
4789         }
4790
4791         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4792         hw->fc.pause_time = pfc_conf->fc.pause_time;
4793         hw->fc.send_xon = pfc_conf->fc.send_xon;
4794         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4795         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4796
4797         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4798
4799         /* Not negotiated is not an error case */
4800         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4801                 return 0;
4802
4803         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4804         return -EIO;
4805 }
4806
4807 static int
4808 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4809                           struct rte_eth_rss_reta_entry64 *reta_conf,
4810                           uint16_t reta_size)
4811 {
4812         uint16_t i, sp_reta_size;
4813         uint8_t j, mask;
4814         uint32_t reta, r;
4815         uint16_t idx, shift;
4816         struct ixgbe_adapter *adapter = dev->data->dev_private;
4817         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4818         uint32_t reta_reg;
4819
4820         PMD_INIT_FUNC_TRACE();
4821
4822         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4823                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4824                         "NIC.");
4825                 return -ENOTSUP;
4826         }
4827
4828         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4829         if (reta_size != sp_reta_size) {
4830                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4831                         "(%d) doesn't match the number hardware can supported "
4832                         "(%d)", reta_size, sp_reta_size);
4833                 return -EINVAL;
4834         }
4835
4836         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4837                 idx = i / RTE_RETA_GROUP_SIZE;
4838                 shift = i % RTE_RETA_GROUP_SIZE;
4839                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4840                                                 IXGBE_4_BIT_MASK);
4841                 if (!mask)
4842                         continue;
4843                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4844                 if (mask == IXGBE_4_BIT_MASK)
4845                         r = 0;
4846                 else
4847                         r = IXGBE_READ_REG(hw, reta_reg);
4848                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4849                         if (mask & (0x1 << j))
4850                                 reta |= reta_conf[idx].reta[shift + j] <<
4851                                                         (CHAR_BIT * j);
4852                         else
4853                                 reta |= r & (IXGBE_8_BIT_MASK <<
4854                                                 (CHAR_BIT * j));
4855                 }
4856                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4857         }
4858         adapter->rss_reta_updated = 1;
4859
4860         return 0;
4861 }
4862
4863 static int
4864 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4865                          struct rte_eth_rss_reta_entry64 *reta_conf,
4866                          uint16_t reta_size)
4867 {
4868         uint16_t i, sp_reta_size;
4869         uint8_t j, mask;
4870         uint32_t reta;
4871         uint16_t idx, shift;
4872         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4873         uint32_t reta_reg;
4874
4875         PMD_INIT_FUNC_TRACE();
4876         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4877         if (reta_size != sp_reta_size) {
4878                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4879                         "(%d) doesn't match the number hardware can supported "
4880                         "(%d)", reta_size, sp_reta_size);
4881                 return -EINVAL;
4882         }
4883
4884         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4885                 idx = i / RTE_RETA_GROUP_SIZE;
4886                 shift = i % RTE_RETA_GROUP_SIZE;
4887                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4888                                                 IXGBE_4_BIT_MASK);
4889                 if (!mask)
4890                         continue;
4891
4892                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4893                 reta = IXGBE_READ_REG(hw, reta_reg);
4894                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4895                         if (mask & (0x1 << j))
4896                                 reta_conf[idx].reta[shift + j] =
4897                                         ((reta >> (CHAR_BIT * j)) &
4898                                                 IXGBE_8_BIT_MASK);
4899                 }
4900         }
4901
4902         return 0;
4903 }
4904
4905 static int
4906 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
4907                                 uint32_t index, uint32_t pool)
4908 {
4909         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4910         uint32_t enable_addr = 1;
4911
4912         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4913                              pool, enable_addr);
4914 }
4915
4916 static void
4917 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4918 {
4919         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4920
4921         ixgbe_clear_rar(hw, index);
4922 }
4923
4924 static int
4925 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
4926 {
4927         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4928
4929         ixgbe_remove_rar(dev, 0);
4930         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4931
4932         return 0;
4933 }
4934
4935 static bool
4936 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4937 {
4938         if (strcmp(dev->device->driver->name, drv->driver.name))
4939                 return false;
4940
4941         return true;
4942 }
4943
4944 bool
4945 is_ixgbe_supported(struct rte_eth_dev *dev)
4946 {
4947         return is_device_supported(dev, &rte_ixgbe_pmd);
4948 }
4949
4950 static int
4951 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4952 {
4953         uint32_t hlreg0;
4954         uint32_t maxfrs;
4955         struct ixgbe_hw *hw;
4956         struct rte_eth_dev_info dev_info;
4957         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
4958         struct rte_eth_dev_data *dev_data = dev->data;
4959
4960         ixgbe_dev_info_get(dev, &dev_info);
4961
4962         /* check that mtu is within the allowed range */
4963         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
4964                 return -EINVAL;
4965
4966         /* If device is started, refuse mtu that requires the support of
4967          * scattered packets when this feature has not been enabled before.
4968          */
4969         if (dev_data->dev_started && !dev_data->scattered_rx &&
4970             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4971              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4972                 PMD_INIT_LOG(ERR, "Stop port first.");
4973                 return -EINVAL;
4974         }
4975
4976         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4977         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4978
4979         /* switch to jumbo mode if needed */
4980         if (frame_size > RTE_ETHER_MAX_LEN) {
4981                 dev->data->dev_conf.rxmode.offloads |=
4982                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4983                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4984         } else {
4985                 dev->data->dev_conf.rxmode.offloads &=
4986                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4987                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4988         }
4989         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4990
4991         /* update max frame size */
4992         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4993
4994         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4995         maxfrs &= 0x0000FFFF;
4996         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4997         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4998
4999         return 0;
5000 }
5001
5002 /*
5003  * Virtual Function operations
5004  */
5005 static void
5006 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5007 {
5008         struct ixgbe_interrupt *intr =
5009                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5010         struct ixgbe_hw *hw =
5011                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5012
5013         PMD_INIT_FUNC_TRACE();
5014
5015         /* Clear interrupt mask to stop from interrupts being generated */
5016         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5017
5018         IXGBE_WRITE_FLUSH(hw);
5019
5020         /* Clear mask value. */
5021         intr->mask = 0;
5022 }
5023
5024 static void
5025 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5026 {
5027         struct ixgbe_interrupt *intr =
5028                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5029         struct ixgbe_hw *hw =
5030                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5031
5032         PMD_INIT_FUNC_TRACE();
5033
5034         /* VF enable interrupt autoclean */
5035         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5036         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5037         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5038
5039         IXGBE_WRITE_FLUSH(hw);
5040
5041         /* Save IXGBE_VTEIMS value to mask. */
5042         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5043 }
5044
5045 static int
5046 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5047 {
5048         struct rte_eth_conf *conf = &dev->data->dev_conf;
5049         struct ixgbe_adapter *adapter = dev->data->dev_private;
5050
5051         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5052                      dev->data->port_id);
5053
5054         /*
5055          * VF has no ability to enable/disable HW CRC
5056          * Keep the persistent behavior the same as Host PF
5057          */
5058 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5059         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5060                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5061                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5062         }
5063 #else
5064         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5065                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5066                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5067         }
5068 #endif
5069
5070         /*
5071          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5072          * allocation or vector Rx preconditions we will reset it.
5073          */
5074         adapter->rx_bulk_alloc_allowed = true;
5075         adapter->rx_vec_allowed = true;
5076
5077         return 0;
5078 }
5079
5080 static int
5081 ixgbevf_dev_start(struct rte_eth_dev *dev)
5082 {
5083         struct ixgbe_hw *hw =
5084                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5085         uint32_t intr_vector = 0;
5086         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5087         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5088
5089         int err, mask = 0;
5090
5091         PMD_INIT_FUNC_TRACE();
5092
5093         /* Stop the link setup handler before resetting the HW. */
5094         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5095
5096         err = hw->mac.ops.reset_hw(hw);
5097         if (err) {
5098                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5099                 return err;
5100         }
5101         hw->mac.get_link_status = true;
5102
5103         /* negotiate mailbox API version to use with the PF. */
5104         ixgbevf_negotiate_api(hw);
5105
5106         ixgbevf_dev_tx_init(dev);
5107
5108         /* This can fail when allocating mbufs for descriptor rings */
5109         err = ixgbevf_dev_rx_init(dev);
5110         if (err) {
5111                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5112                 ixgbe_dev_clear_queues(dev);
5113                 return err;
5114         }
5115
5116         /* Set vfta */
5117         ixgbevf_set_vfta_all(dev, 1);
5118
5119         /* Set HW strip */
5120         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5121                 ETH_VLAN_EXTEND_MASK;
5122         err = ixgbevf_vlan_offload_config(dev, mask);
5123         if (err) {
5124                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5125                 ixgbe_dev_clear_queues(dev);
5126                 return err;
5127         }
5128
5129         ixgbevf_dev_rxtx_start(dev);
5130
5131         /* check and configure queue intr-vector mapping */
5132         if (rte_intr_cap_multiple(intr_handle) &&
5133             dev->data->dev_conf.intr_conf.rxq) {
5134                 /* According to datasheet, only vector 0/1/2 can be used,
5135                  * now only one vector is used for Rx queue
5136                  */
5137                 intr_vector = 1;
5138                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5139                         return -1;
5140         }
5141
5142         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5143                 intr_handle->intr_vec =
5144                         rte_zmalloc("intr_vec",
5145                                     dev->data->nb_rx_queues * sizeof(int), 0);
5146                 if (intr_handle->intr_vec == NULL) {
5147                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5148                                      " intr_vec", dev->data->nb_rx_queues);
5149                         return -ENOMEM;
5150                 }
5151         }
5152         ixgbevf_configure_msix(dev);
5153
5154         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5155          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5156          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5157          * is not cleared, it will fail when following rte_intr_enable( ) tries
5158          * to map Rx queue interrupt to other VFIO vectors.
5159          * So clear uio/vfio intr/evevnfd first to avoid failure.
5160          */
5161         rte_intr_disable(intr_handle);
5162
5163         rte_intr_enable(intr_handle);
5164
5165         /* Re-enable interrupt for VF */
5166         ixgbevf_intr_enable(dev);
5167
5168         /*
5169          * Update link status right before return, because it may
5170          * start link configuration process in a separate thread.
5171          */
5172         ixgbevf_dev_link_update(dev, 0);
5173
5174         return 0;
5175 }
5176
5177 static void
5178 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5179 {
5180         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5181         struct ixgbe_adapter *adapter = dev->data->dev_private;
5182         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5183         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5184
5185         PMD_INIT_FUNC_TRACE();
5186
5187         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5188
5189         ixgbevf_intr_disable(dev);
5190
5191         hw->adapter_stopped = 1;
5192         ixgbe_stop_adapter(hw);
5193
5194         /*
5195           * Clear what we set, but we still keep shadow_vfta to
5196           * restore after device starts
5197           */
5198         ixgbevf_set_vfta_all(dev, 0);
5199
5200         /* Clear stored conf */
5201         dev->data->scattered_rx = 0;
5202
5203         ixgbe_dev_clear_queues(dev);
5204
5205         /* Clean datapath event and queue/vec mapping */
5206         rte_intr_efd_disable(intr_handle);
5207         if (intr_handle->intr_vec != NULL) {
5208                 rte_free(intr_handle->intr_vec);
5209                 intr_handle->intr_vec = NULL;
5210         }
5211
5212         adapter->rss_reta_updated = 0;
5213 }
5214
5215 static void
5216 ixgbevf_dev_close(struct rte_eth_dev *dev)
5217 {
5218         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5219
5220         PMD_INIT_FUNC_TRACE();
5221
5222         ixgbe_reset_hw(hw);
5223
5224         ixgbevf_dev_stop(dev);
5225
5226         ixgbe_dev_free_queues(dev);
5227
5228         /**
5229          * Remove the VF MAC address ro ensure
5230          * that the VF traffic goes to the PF
5231          * after stop, close and detach of the VF
5232          **/
5233         ixgbevf_remove_mac_addr(dev, 0);
5234 }
5235
5236 /*
5237  * Reset VF device
5238  */
5239 static int
5240 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5241 {
5242         int ret;
5243
5244         ret = eth_ixgbevf_dev_uninit(dev);
5245         if (ret)
5246                 return ret;
5247
5248         ret = eth_ixgbevf_dev_init(dev);
5249
5250         return ret;
5251 }
5252
5253 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5254 {
5255         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5256         struct ixgbe_vfta *shadow_vfta =
5257                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5258         int i = 0, j = 0, vfta = 0, mask = 1;
5259
5260         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5261                 vfta = shadow_vfta->vfta[i];
5262                 if (vfta) {
5263                         mask = 1;
5264                         for (j = 0; j < 32; j++) {
5265                                 if (vfta & mask)
5266                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5267                                                        on, false);
5268                                 mask <<= 1;
5269                         }
5270                 }
5271         }
5272
5273 }
5274
5275 static int
5276 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5277 {
5278         struct ixgbe_hw *hw =
5279                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5280         struct ixgbe_vfta *shadow_vfta =
5281                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5282         uint32_t vid_idx = 0;
5283         uint32_t vid_bit = 0;
5284         int ret = 0;
5285
5286         PMD_INIT_FUNC_TRACE();
5287
5288         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5289         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5290         if (ret) {
5291                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5292                 return ret;
5293         }
5294         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5295         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5296
5297         /* Save what we set and retore it after device reset */
5298         if (on)
5299                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5300         else
5301                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5302
5303         return 0;
5304 }
5305
5306 static void
5307 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5308 {
5309         struct ixgbe_hw *hw =
5310                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5311         uint32_t ctrl;
5312
5313         PMD_INIT_FUNC_TRACE();
5314
5315         if (queue >= hw->mac.max_rx_queues)
5316                 return;
5317
5318         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5319         if (on)
5320                 ctrl |= IXGBE_RXDCTL_VME;
5321         else
5322                 ctrl &= ~IXGBE_RXDCTL_VME;
5323         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5324
5325         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5326 }
5327
5328 static int
5329 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5330 {
5331         struct ixgbe_rx_queue *rxq;
5332         uint16_t i;
5333         int on = 0;
5334
5335         /* VF function only support hw strip feature, others are not support */
5336         if (mask & ETH_VLAN_STRIP_MASK) {
5337                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5338                         rxq = dev->data->rx_queues[i];
5339                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5340                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5341                 }
5342         }
5343
5344         return 0;
5345 }
5346
5347 static int
5348 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5349 {
5350         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5351
5352         ixgbevf_vlan_offload_config(dev, mask);
5353
5354         return 0;
5355 }
5356
5357 int
5358 ixgbe_vt_check(struct ixgbe_hw *hw)
5359 {
5360         uint32_t reg_val;
5361
5362         /* if Virtualization Technology is enabled */
5363         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5364         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5365                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5366                 return -1;
5367         }
5368
5369         return 0;
5370 }
5371
5372 static uint32_t
5373 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5374 {
5375         uint32_t vector = 0;
5376
5377         switch (hw->mac.mc_filter_type) {
5378         case 0:   /* use bits [47:36] of the address */
5379                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5380                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5381                 break;
5382         case 1:   /* use bits [46:35] of the address */
5383                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5384                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5385                 break;
5386         case 2:   /* use bits [45:34] of the address */
5387                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5388                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5389                 break;
5390         case 3:   /* use bits [43:32] of the address */
5391                 vector = ((uc_addr->addr_bytes[4]) |
5392                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5393                 break;
5394         default:  /* Invalid mc_filter_type */
5395                 break;
5396         }
5397
5398         /* vector can only be 12-bits or boundary will be exceeded */
5399         vector &= 0xFFF;
5400         return vector;
5401 }
5402
5403 static int
5404 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5405                         struct rte_ether_addr *mac_addr, uint8_t on)
5406 {
5407         uint32_t vector;
5408         uint32_t uta_idx;
5409         uint32_t reg_val;
5410         uint32_t uta_shift;
5411         uint32_t rc;
5412         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5413         const uint32_t ixgbe_uta_bit_shift = 5;
5414         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5415         const uint32_t bit1 = 0x1;
5416
5417         struct ixgbe_hw *hw =
5418                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5419         struct ixgbe_uta_info *uta_info =
5420                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5421
5422         /* The UTA table only exists on 82599 hardware and newer */
5423         if (hw->mac.type < ixgbe_mac_82599EB)
5424                 return -ENOTSUP;
5425
5426         vector = ixgbe_uta_vector(hw, mac_addr);
5427         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5428         uta_shift = vector & ixgbe_uta_bit_mask;
5429
5430         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5431         if (rc == on)
5432                 return 0;
5433
5434         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5435         if (on) {
5436                 uta_info->uta_in_use++;
5437                 reg_val |= (bit1 << uta_shift);
5438                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5439         } else {
5440                 uta_info->uta_in_use--;
5441                 reg_val &= ~(bit1 << uta_shift);
5442                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5443         }
5444
5445         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5446
5447         if (uta_info->uta_in_use > 0)
5448                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5449                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5450         else
5451                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5452
5453         return 0;
5454 }
5455
5456 static int
5457 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5458 {
5459         int i;
5460         struct ixgbe_hw *hw =
5461                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5462         struct ixgbe_uta_info *uta_info =
5463                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5464
5465         /* The UTA table only exists on 82599 hardware and newer */
5466         if (hw->mac.type < ixgbe_mac_82599EB)
5467                 return -ENOTSUP;
5468
5469         if (on) {
5470                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5471                         uta_info->uta_shadow[i] = ~0;
5472                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5473                 }
5474         } else {
5475                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5476                         uta_info->uta_shadow[i] = 0;
5477                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5478                 }
5479         }
5480         return 0;
5481
5482 }
5483
5484 uint32_t
5485 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5486 {
5487         uint32_t new_val = orig_val;
5488
5489         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5490                 new_val |= IXGBE_VMOLR_AUPE;
5491         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5492                 new_val |= IXGBE_VMOLR_ROMPE;
5493         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5494                 new_val |= IXGBE_VMOLR_ROPE;
5495         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5496                 new_val |= IXGBE_VMOLR_BAM;
5497         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5498                 new_val |= IXGBE_VMOLR_MPE;
5499
5500         return new_val;
5501 }
5502
5503 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5504 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5505 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5506 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5507 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5508         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5509         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5510
5511 static int
5512 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5513                       struct rte_eth_mirror_conf *mirror_conf,
5514                       uint8_t rule_id, uint8_t on)
5515 {
5516         uint32_t mr_ctl, vlvf;
5517         uint32_t mp_lsb = 0;
5518         uint32_t mv_msb = 0;
5519         uint32_t mv_lsb = 0;
5520         uint32_t mp_msb = 0;
5521         uint8_t i = 0;
5522         int reg_index = 0;
5523         uint64_t vlan_mask = 0;
5524
5525         const uint8_t pool_mask_offset = 32;
5526         const uint8_t vlan_mask_offset = 32;
5527         const uint8_t dst_pool_offset = 8;
5528         const uint8_t rule_mr_offset  = 4;
5529         const uint8_t mirror_rule_mask = 0x0F;
5530
5531         struct ixgbe_mirror_info *mr_info =
5532                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5533         struct ixgbe_hw *hw =
5534                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5535         uint8_t mirror_type = 0;
5536
5537         if (ixgbe_vt_check(hw) < 0)
5538                 return -ENOTSUP;
5539
5540         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5541                 return -EINVAL;
5542
5543         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5544                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5545                             mirror_conf->rule_type);
5546                 return -EINVAL;
5547         }
5548
5549         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5550                 mirror_type |= IXGBE_MRCTL_VLME;
5551                 /* Check if vlan id is valid and find conresponding VLAN ID
5552                  * index in VLVF
5553                  */
5554                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5555                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5556                                 /* search vlan id related pool vlan filter
5557                                  * index
5558                                  */
5559                                 reg_index = ixgbe_find_vlvf_slot(
5560                                                 hw,
5561                                                 mirror_conf->vlan.vlan_id[i],
5562                                                 false);
5563                                 if (reg_index < 0)
5564                                         return -EINVAL;
5565                                 vlvf = IXGBE_READ_REG(hw,
5566                                                       IXGBE_VLVF(reg_index));
5567                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5568                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5569                                       mirror_conf->vlan.vlan_id[i]))
5570                                         vlan_mask |= (1ULL << reg_index);
5571                                 else
5572                                         return -EINVAL;
5573                         }
5574                 }
5575
5576                 if (on) {
5577                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5578                         mv_msb = vlan_mask >> vlan_mask_offset;
5579
5580                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5581                                                 mirror_conf->vlan.vlan_mask;
5582                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5583                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5584                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5585                                                 mirror_conf->vlan.vlan_id[i];
5586                         }
5587                 } else {
5588                         mv_lsb = 0;
5589                         mv_msb = 0;
5590                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5591                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5592                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5593                 }
5594         }
5595
5596         /**
5597          * if enable pool mirror, write related pool mask register,if disable
5598          * pool mirror, clear PFMRVM register
5599          */
5600         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5601                 mirror_type |= IXGBE_MRCTL_VPME;
5602                 if (on) {
5603                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5604                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5605                         mr_info->mr_conf[rule_id].pool_mask =
5606                                         mirror_conf->pool_mask;
5607
5608                 } else {
5609                         mp_lsb = 0;
5610                         mp_msb = 0;
5611                         mr_info->mr_conf[rule_id].pool_mask = 0;
5612                 }
5613         }
5614         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5615                 mirror_type |= IXGBE_MRCTL_UPME;
5616         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5617                 mirror_type |= IXGBE_MRCTL_DPME;
5618
5619         /* read  mirror control register and recalculate it */
5620         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5621
5622         if (on) {
5623                 mr_ctl |= mirror_type;
5624                 mr_ctl &= mirror_rule_mask;
5625                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5626         } else {
5627                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5628         }
5629
5630         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5631         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5632
5633         /* write mirrror control  register */
5634         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5635
5636         /* write pool mirrror control  register */
5637         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5638                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5639                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5640                                 mp_msb);
5641         }
5642         /* write VLAN mirrror control  register */
5643         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5644                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5645                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5646                                 mv_msb);
5647         }
5648
5649         return 0;
5650 }
5651
5652 static int
5653 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5654 {
5655         int mr_ctl = 0;
5656         uint32_t lsb_val = 0;
5657         uint32_t msb_val = 0;
5658         const uint8_t rule_mr_offset = 4;
5659
5660         struct ixgbe_hw *hw =
5661                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5662         struct ixgbe_mirror_info *mr_info =
5663                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5664
5665         if (ixgbe_vt_check(hw) < 0)
5666                 return -ENOTSUP;
5667
5668         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5669                 return -EINVAL;
5670
5671         memset(&mr_info->mr_conf[rule_id], 0,
5672                sizeof(struct rte_eth_mirror_conf));
5673
5674         /* clear PFVMCTL register */
5675         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5676
5677         /* clear pool mask register */
5678         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5679         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5680
5681         /* clear vlan mask register */
5682         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5683         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5684
5685         return 0;
5686 }
5687
5688 static int
5689 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5690 {
5691         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5692         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5693         struct ixgbe_interrupt *intr =
5694                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5695         struct ixgbe_hw *hw =
5696                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5697         uint32_t vec = IXGBE_MISC_VEC_ID;
5698
5699         if (rte_intr_allow_others(intr_handle))
5700                 vec = IXGBE_RX_VEC_START;
5701         intr->mask |= (1 << vec);
5702         RTE_SET_USED(queue_id);
5703         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5704
5705         rte_intr_enable(intr_handle);
5706
5707         return 0;
5708 }
5709
5710 static int
5711 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5712 {
5713         struct ixgbe_interrupt *intr =
5714                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5715         struct ixgbe_hw *hw =
5716                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5717         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5718         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5719         uint32_t vec = IXGBE_MISC_VEC_ID;
5720
5721         if (rte_intr_allow_others(intr_handle))
5722                 vec = IXGBE_RX_VEC_START;
5723         intr->mask &= ~(1 << vec);
5724         RTE_SET_USED(queue_id);
5725         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5726
5727         return 0;
5728 }
5729
5730 static int
5731 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5732 {
5733         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5734         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5735         uint32_t mask;
5736         struct ixgbe_hw *hw =
5737                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5738         struct ixgbe_interrupt *intr =
5739                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5740
5741         if (queue_id < 16) {
5742                 ixgbe_disable_intr(hw);
5743                 intr->mask |= (1 << queue_id);
5744                 ixgbe_enable_intr(dev);
5745         } else if (queue_id < 32) {
5746                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5747                 mask &= (1 << queue_id);
5748                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5749         } else if (queue_id < 64) {
5750                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5751                 mask &= (1 << (queue_id - 32));
5752                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5753         }
5754         rte_intr_enable(intr_handle);
5755
5756         return 0;
5757 }
5758
5759 static int
5760 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5761 {
5762         uint32_t mask;
5763         struct ixgbe_hw *hw =
5764                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5765         struct ixgbe_interrupt *intr =
5766                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5767
5768         if (queue_id < 16) {
5769                 ixgbe_disable_intr(hw);
5770                 intr->mask &= ~(1 << queue_id);
5771                 ixgbe_enable_intr(dev);
5772         } else if (queue_id < 32) {
5773                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5774                 mask &= ~(1 << queue_id);
5775                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5776         } else if (queue_id < 64) {
5777                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5778                 mask &= ~(1 << (queue_id - 32));
5779                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5780         }
5781
5782         return 0;
5783 }
5784
5785 static void
5786 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5787                      uint8_t queue, uint8_t msix_vector)
5788 {
5789         uint32_t tmp, idx;
5790
5791         if (direction == -1) {
5792                 /* other causes */
5793                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5794                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5795                 tmp &= ~0xFF;
5796                 tmp |= msix_vector;
5797                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5798         } else {
5799                 /* rx or tx cause */
5800                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5801                 idx = ((16 * (queue & 1)) + (8 * direction));
5802                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5803                 tmp &= ~(0xFF << idx);
5804                 tmp |= (msix_vector << idx);
5805                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5806         }
5807 }
5808
5809 /**
5810  * set the IVAR registers, mapping interrupt causes to vectors
5811  * @param hw
5812  *  pointer to ixgbe_hw struct
5813  * @direction
5814  *  0 for Rx, 1 for Tx, -1 for other causes
5815  * @queue
5816  *  queue to map the corresponding interrupt to
5817  * @msix_vector
5818  *  the vector to map to the corresponding queue
5819  */
5820 static void
5821 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5822                    uint8_t queue, uint8_t msix_vector)
5823 {
5824         uint32_t tmp, idx;
5825
5826         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5827         if (hw->mac.type == ixgbe_mac_82598EB) {
5828                 if (direction == -1)
5829                         direction = 0;
5830                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5831                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5832                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5833                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5834                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5835         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5836                         (hw->mac.type == ixgbe_mac_X540) ||
5837                         (hw->mac.type == ixgbe_mac_X550)) {
5838                 if (direction == -1) {
5839                         /* other causes */
5840                         idx = ((queue & 1) * 8);
5841                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5842                         tmp &= ~(0xFF << idx);
5843                         tmp |= (msix_vector << idx);
5844                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5845                 } else {
5846                         /* rx or tx causes */
5847                         idx = ((16 * (queue & 1)) + (8 * direction));
5848                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5849                         tmp &= ~(0xFF << idx);
5850                         tmp |= (msix_vector << idx);
5851                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5852                 }
5853         }
5854 }
5855
5856 static void
5857 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5858 {
5859         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5860         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5861         struct ixgbe_hw *hw =
5862                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5863         uint32_t q_idx;
5864         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5865         uint32_t base = IXGBE_MISC_VEC_ID;
5866
5867         /* Configure VF other cause ivar */
5868         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5869
5870         /* won't configure msix register if no mapping is done
5871          * between intr vector and event fd.
5872          */
5873         if (!rte_intr_dp_is_en(intr_handle))
5874                 return;
5875
5876         if (rte_intr_allow_others(intr_handle)) {
5877                 base = IXGBE_RX_VEC_START;
5878                 vector_idx = IXGBE_RX_VEC_START;
5879         }
5880
5881         /* Configure all RX queues of VF */
5882         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5883                 /* Force all queue use vector 0,
5884                  * as IXGBE_VF_MAXMSIVECOTR = 1
5885                  */
5886                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5887                 intr_handle->intr_vec[q_idx] = vector_idx;
5888                 if (vector_idx < base + intr_handle->nb_efd - 1)
5889                         vector_idx++;
5890         }
5891
5892         /* As RX queue setting above show, all queues use the vector 0.
5893          * Set only the ITR value of IXGBE_MISC_VEC_ID.
5894          */
5895         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5896                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5897                         | IXGBE_EITR_CNT_WDIS);
5898 }
5899
5900 /**
5901  * Sets up the hardware to properly generate MSI-X interrupts
5902  * @hw
5903  *  board private structure
5904  */
5905 static void
5906 ixgbe_configure_msix(struct rte_eth_dev *dev)
5907 {
5908         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5909         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5910         struct ixgbe_hw *hw =
5911                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5912         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5913         uint32_t vec = IXGBE_MISC_VEC_ID;
5914         uint32_t mask;
5915         uint32_t gpie;
5916
5917         /* won't configure msix register if no mapping is done
5918          * between intr vector and event fd
5919          * but if misx has been enabled already, need to configure
5920          * auto clean, auto mask and throttling.
5921          */
5922         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5923         if (!rte_intr_dp_is_en(intr_handle) &&
5924             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
5925                 return;
5926
5927         if (rte_intr_allow_others(intr_handle))
5928                 vec = base = IXGBE_RX_VEC_START;
5929
5930         /* setup GPIE for MSI-x mode */
5931         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5932         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5933                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5934         /* auto clearing and auto setting corresponding bits in EIMS
5935          * when MSI-X interrupt is triggered
5936          */
5937         if (hw->mac.type == ixgbe_mac_82598EB) {
5938                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5939         } else {
5940                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5941                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5942         }
5943         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5944
5945         /* Populate the IVAR table and set the ITR values to the
5946          * corresponding register.
5947          */
5948         if (rte_intr_dp_is_en(intr_handle)) {
5949                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5950                         queue_id++) {
5951                         /* by default, 1:1 mapping */
5952                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5953                         intr_handle->intr_vec[queue_id] = vec;
5954                         if (vec < base + intr_handle->nb_efd - 1)
5955                                 vec++;
5956                 }
5957
5958                 switch (hw->mac.type) {
5959                 case ixgbe_mac_82598EB:
5960                         ixgbe_set_ivar_map(hw, -1,
5961                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
5962                                            IXGBE_MISC_VEC_ID);
5963                         break;
5964                 case ixgbe_mac_82599EB:
5965                 case ixgbe_mac_X540:
5966                 case ixgbe_mac_X550:
5967                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5968                         break;
5969                 default:
5970                         break;
5971                 }
5972         }
5973         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5974                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5975                         | IXGBE_EITR_CNT_WDIS);
5976
5977         /* set up to autoclear timer, and the vectors */
5978         mask = IXGBE_EIMS_ENABLE_MASK;
5979         mask &= ~(IXGBE_EIMS_OTHER |
5980                   IXGBE_EIMS_MAILBOX |
5981                   IXGBE_EIMS_LSC);
5982
5983         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5984 }
5985
5986 int
5987 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5988                            uint16_t queue_idx, uint16_t tx_rate)
5989 {
5990         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5991         struct rte_eth_rxmode *rxmode;
5992         uint32_t rf_dec, rf_int;
5993         uint32_t bcnrc_val;
5994         uint16_t link_speed = dev->data->dev_link.link_speed;
5995
5996         if (queue_idx >= hw->mac.max_tx_queues)
5997                 return -EINVAL;
5998
5999         if (tx_rate != 0) {
6000                 /* Calculate the rate factor values to set */
6001                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6002                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6003                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6004
6005                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6006                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6007                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6008                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6009         } else {
6010                 bcnrc_val = 0;
6011         }
6012
6013         rxmode = &dev->data->dev_conf.rxmode;
6014         /*
6015          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6016          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6017          * set as 0x4.
6018          */
6019         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6020             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6021                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6022                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6023         else
6024                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6025                         IXGBE_MMW_SIZE_DEFAULT);
6026
6027         /* Set RTTBCNRC of queue X */
6028         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6029         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6030         IXGBE_WRITE_FLUSH(hw);
6031
6032         return 0;
6033 }
6034
6035 static int
6036 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6037                      __attribute__((unused)) uint32_t index,
6038                      __attribute__((unused)) uint32_t pool)
6039 {
6040         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6041         int diag;
6042
6043         /*
6044          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6045          * operation. Trap this case to avoid exhausting the [very limited]
6046          * set of PF resources used to store VF MAC addresses.
6047          */
6048         if (memcmp(hw->mac.perm_addr, mac_addr,
6049                         sizeof(struct rte_ether_addr)) == 0)
6050                 return -1;
6051         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6052         if (diag != 0)
6053                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6054                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6055                             mac_addr->addr_bytes[0],
6056                             mac_addr->addr_bytes[1],
6057                             mac_addr->addr_bytes[2],
6058                             mac_addr->addr_bytes[3],
6059                             mac_addr->addr_bytes[4],
6060                             mac_addr->addr_bytes[5],
6061                             diag);
6062         return diag;
6063 }
6064
6065 static void
6066 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6067 {
6068         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6069         struct rte_ether_addr *perm_addr =
6070                 (struct rte_ether_addr *)hw->mac.perm_addr;
6071         struct rte_ether_addr *mac_addr;
6072         uint32_t i;
6073         int diag;
6074
6075         /*
6076          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6077          * not support the deletion of a given MAC address.
6078          * Instead, it imposes to delete all MAC addresses, then to add again
6079          * all MAC addresses with the exception of the one to be deleted.
6080          */
6081         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6082
6083         /*
6084          * Add again all MAC addresses, with the exception of the deleted one
6085          * and of the permanent MAC address.
6086          */
6087         for (i = 0, mac_addr = dev->data->mac_addrs;
6088              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6089                 /* Skip the deleted MAC address */
6090                 if (i == index)
6091                         continue;
6092                 /* Skip NULL MAC addresses */
6093                 if (rte_is_zero_ether_addr(mac_addr))
6094                         continue;
6095                 /* Skip the permanent MAC address */
6096                 if (memcmp(perm_addr, mac_addr,
6097                                 sizeof(struct rte_ether_addr)) == 0)
6098                         continue;
6099                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6100                 if (diag != 0)
6101                         PMD_DRV_LOG(ERR,
6102                                     "Adding again MAC address "
6103                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6104                                     "diag=%d",
6105                                     mac_addr->addr_bytes[0],
6106                                     mac_addr->addr_bytes[1],
6107                                     mac_addr->addr_bytes[2],
6108                                     mac_addr->addr_bytes[3],
6109                                     mac_addr->addr_bytes[4],
6110                                     mac_addr->addr_bytes[5],
6111                                     diag);
6112         }
6113 }
6114
6115 static int
6116 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6117                         struct rte_ether_addr *addr)
6118 {
6119         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6120
6121         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6122
6123         return 0;
6124 }
6125
6126 int
6127 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6128                         struct rte_eth_syn_filter *filter,
6129                         bool add)
6130 {
6131         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6132         struct ixgbe_filter_info *filter_info =
6133                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6134         uint32_t syn_info;
6135         uint32_t synqf;
6136
6137         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6138                 return -EINVAL;
6139
6140         syn_info = filter_info->syn_info;
6141
6142         if (add) {
6143                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6144                         return -EINVAL;
6145                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6146                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6147
6148                 if (filter->hig_pri)
6149                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6150                 else
6151                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6152         } else {
6153                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6154                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6155                         return -ENOENT;
6156                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6157         }
6158
6159         filter_info->syn_info = synqf;
6160         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6161         IXGBE_WRITE_FLUSH(hw);
6162         return 0;
6163 }
6164
6165 static int
6166 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6167                         struct rte_eth_syn_filter *filter)
6168 {
6169         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6170         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6171
6172         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6173                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6174                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6175                 return 0;
6176         }
6177         return -ENOENT;
6178 }
6179
6180 static int
6181 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6182                         enum rte_filter_op filter_op,
6183                         void *arg)
6184 {
6185         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6186         int ret;
6187
6188         MAC_TYPE_FILTER_SUP(hw->mac.type);
6189
6190         if (filter_op == RTE_ETH_FILTER_NOP)
6191                 return 0;
6192
6193         if (arg == NULL) {
6194                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6195                             filter_op);
6196                 return -EINVAL;
6197         }
6198
6199         switch (filter_op) {
6200         case RTE_ETH_FILTER_ADD:
6201                 ret = ixgbe_syn_filter_set(dev,
6202                                 (struct rte_eth_syn_filter *)arg,
6203                                 TRUE);
6204                 break;
6205         case RTE_ETH_FILTER_DELETE:
6206                 ret = ixgbe_syn_filter_set(dev,
6207                                 (struct rte_eth_syn_filter *)arg,
6208                                 FALSE);
6209                 break;
6210         case RTE_ETH_FILTER_GET:
6211                 ret = ixgbe_syn_filter_get(dev,
6212                                 (struct rte_eth_syn_filter *)arg);
6213                 break;
6214         default:
6215                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6216                 ret = -EINVAL;
6217                 break;
6218         }
6219
6220         return ret;
6221 }
6222
6223
6224 static inline enum ixgbe_5tuple_protocol
6225 convert_protocol_type(uint8_t protocol_value)
6226 {
6227         if (protocol_value == IPPROTO_TCP)
6228                 return IXGBE_FILTER_PROTOCOL_TCP;
6229         else if (protocol_value == IPPROTO_UDP)
6230                 return IXGBE_FILTER_PROTOCOL_UDP;
6231         else if (protocol_value == IPPROTO_SCTP)
6232                 return IXGBE_FILTER_PROTOCOL_SCTP;
6233         else
6234                 return IXGBE_FILTER_PROTOCOL_NONE;
6235 }
6236
6237 /* inject a 5-tuple filter to HW */
6238 static inline void
6239 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6240                            struct ixgbe_5tuple_filter *filter)
6241 {
6242         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6243         int i;
6244         uint32_t ftqf, sdpqf;
6245         uint32_t l34timir = 0;
6246         uint8_t mask = 0xff;
6247
6248         i = filter->index;
6249
6250         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6251                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6252         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6253
6254         ftqf = (uint32_t)(filter->filter_info.proto &
6255                 IXGBE_FTQF_PROTOCOL_MASK);
6256         ftqf |= (uint32_t)((filter->filter_info.priority &
6257                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6258         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6259                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6260         if (filter->filter_info.dst_ip_mask == 0)
6261                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6262         if (filter->filter_info.src_port_mask == 0)
6263                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6264         if (filter->filter_info.dst_port_mask == 0)
6265                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6266         if (filter->filter_info.proto_mask == 0)
6267                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6268         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6269         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6270         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6271
6272         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6273         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6274         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6275         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6276
6277         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6278         l34timir |= (uint32_t)(filter->queue <<
6279                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6280         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6281 }
6282
6283 /*
6284  * add a 5tuple filter
6285  *
6286  * @param
6287  * dev: Pointer to struct rte_eth_dev.
6288  * index: the index the filter allocates.
6289  * filter: ponter to the filter that will be added.
6290  * rx_queue: the queue id the filter assigned to.
6291  *
6292  * @return
6293  *    - On success, zero.
6294  *    - On failure, a negative value.
6295  */
6296 static int
6297 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6298                         struct ixgbe_5tuple_filter *filter)
6299 {
6300         struct ixgbe_filter_info *filter_info =
6301                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6302         int i, idx, shift;
6303
6304         /*
6305          * look for an unused 5tuple filter index,
6306          * and insert the filter to list.
6307          */
6308         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6309                 idx = i / (sizeof(uint32_t) * NBBY);
6310                 shift = i % (sizeof(uint32_t) * NBBY);
6311                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6312                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6313                         filter->index = i;
6314                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6315                                           filter,
6316                                           entries);
6317                         break;
6318                 }
6319         }
6320         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6321                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6322                 return -ENOSYS;
6323         }
6324
6325         ixgbe_inject_5tuple_filter(dev, filter);
6326
6327         return 0;
6328 }
6329
6330 /*
6331  * remove a 5tuple filter
6332  *
6333  * @param
6334  * dev: Pointer to struct rte_eth_dev.
6335  * filter: the pointer of the filter will be removed.
6336  */
6337 static void
6338 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6339                         struct ixgbe_5tuple_filter *filter)
6340 {
6341         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6342         struct ixgbe_filter_info *filter_info =
6343                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6344         uint16_t index = filter->index;
6345
6346         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6347                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6348         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6349         rte_free(filter);
6350
6351         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6352         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6353         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6354         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6355         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6356 }
6357
6358 static int
6359 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6360 {
6361         struct ixgbe_hw *hw;
6362         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6363         struct rte_eth_dev_data *dev_data = dev->data;
6364
6365         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6366
6367         if (mtu < RTE_ETHER_MIN_MTU ||
6368                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6369                 return -EINVAL;
6370
6371         /* If device is started, refuse mtu that requires the support of
6372          * scattered packets when this feature has not been enabled before.
6373          */
6374         if (dev_data->dev_started && !dev_data->scattered_rx &&
6375             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6376              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6377                 PMD_INIT_LOG(ERR, "Stop port first.");
6378                 return -EINVAL;
6379         }
6380
6381         /*
6382          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6383          * request of the version 2.0 of the mailbox API.
6384          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6385          * of the mailbox API.
6386          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6387          * prior to 3.11.33 which contains the following change:
6388          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6389          */
6390         ixgbevf_rlpml_set_vf(hw, max_frame);
6391
6392         /* update max frame size */
6393         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6394         return 0;
6395 }
6396
6397 static inline struct ixgbe_5tuple_filter *
6398 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6399                         struct ixgbe_5tuple_filter_info *key)
6400 {
6401         struct ixgbe_5tuple_filter *it;
6402
6403         TAILQ_FOREACH(it, filter_list, entries) {
6404                 if (memcmp(key, &it->filter_info,
6405                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6406                         return it;
6407                 }
6408         }
6409         return NULL;
6410 }
6411
6412 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6413 static inline int
6414 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6415                         struct ixgbe_5tuple_filter_info *filter_info)
6416 {
6417         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6418                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6419                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6420                 return -EINVAL;
6421
6422         switch (filter->dst_ip_mask) {
6423         case UINT32_MAX:
6424                 filter_info->dst_ip_mask = 0;
6425                 filter_info->dst_ip = filter->dst_ip;
6426                 break;
6427         case 0:
6428                 filter_info->dst_ip_mask = 1;
6429                 break;
6430         default:
6431                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6432                 return -EINVAL;
6433         }
6434
6435         switch (filter->src_ip_mask) {
6436         case UINT32_MAX:
6437                 filter_info->src_ip_mask = 0;
6438                 filter_info->src_ip = filter->src_ip;
6439                 break;
6440         case 0:
6441                 filter_info->src_ip_mask = 1;
6442                 break;
6443         default:
6444                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6445                 return -EINVAL;
6446         }
6447
6448         switch (filter->dst_port_mask) {
6449         case UINT16_MAX:
6450                 filter_info->dst_port_mask = 0;
6451                 filter_info->dst_port = filter->dst_port;
6452                 break;
6453         case 0:
6454                 filter_info->dst_port_mask = 1;
6455                 break;
6456         default:
6457                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6458                 return -EINVAL;
6459         }
6460
6461         switch (filter->src_port_mask) {
6462         case UINT16_MAX:
6463                 filter_info->src_port_mask = 0;
6464                 filter_info->src_port = filter->src_port;
6465                 break;
6466         case 0:
6467                 filter_info->src_port_mask = 1;
6468                 break;
6469         default:
6470                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6471                 return -EINVAL;
6472         }
6473
6474         switch (filter->proto_mask) {
6475         case UINT8_MAX:
6476                 filter_info->proto_mask = 0;
6477                 filter_info->proto =
6478                         convert_protocol_type(filter->proto);
6479                 break;
6480         case 0:
6481                 filter_info->proto_mask = 1;
6482                 break;
6483         default:
6484                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6485                 return -EINVAL;
6486         }
6487
6488         filter_info->priority = (uint8_t)filter->priority;
6489         return 0;
6490 }
6491
6492 /*
6493  * add or delete a ntuple filter
6494  *
6495  * @param
6496  * dev: Pointer to struct rte_eth_dev.
6497  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6498  * add: if true, add filter, if false, remove filter
6499  *
6500  * @return
6501  *    - On success, zero.
6502  *    - On failure, a negative value.
6503  */
6504 int
6505 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6506                         struct rte_eth_ntuple_filter *ntuple_filter,
6507                         bool add)
6508 {
6509         struct ixgbe_filter_info *filter_info =
6510                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6511         struct ixgbe_5tuple_filter_info filter_5tuple;
6512         struct ixgbe_5tuple_filter *filter;
6513         int ret;
6514
6515         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6516                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6517                 return -EINVAL;
6518         }
6519
6520         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6521         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6522         if (ret < 0)
6523                 return ret;
6524
6525         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6526                                          &filter_5tuple);
6527         if (filter != NULL && add) {
6528                 PMD_DRV_LOG(ERR, "filter exists.");
6529                 return -EEXIST;
6530         }
6531         if (filter == NULL && !add) {
6532                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6533                 return -ENOENT;
6534         }
6535
6536         if (add) {
6537                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6538                                 sizeof(struct ixgbe_5tuple_filter), 0);
6539                 if (filter == NULL)
6540                         return -ENOMEM;
6541                 rte_memcpy(&filter->filter_info,
6542                                  &filter_5tuple,
6543                                  sizeof(struct ixgbe_5tuple_filter_info));
6544                 filter->queue = ntuple_filter->queue;
6545                 ret = ixgbe_add_5tuple_filter(dev, filter);
6546                 if (ret < 0) {
6547                         rte_free(filter);
6548                         return ret;
6549                 }
6550         } else
6551                 ixgbe_remove_5tuple_filter(dev, filter);
6552
6553         return 0;
6554 }
6555
6556 /*
6557  * get a ntuple filter
6558  *
6559  * @param
6560  * dev: Pointer to struct rte_eth_dev.
6561  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6562  *
6563  * @return
6564  *    - On success, zero.
6565  *    - On failure, a negative value.
6566  */
6567 static int
6568 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6569                         struct rte_eth_ntuple_filter *ntuple_filter)
6570 {
6571         struct ixgbe_filter_info *filter_info =
6572                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6573         struct ixgbe_5tuple_filter_info filter_5tuple;
6574         struct ixgbe_5tuple_filter *filter;
6575         int ret;
6576
6577         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6578                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6579                 return -EINVAL;
6580         }
6581
6582         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6583         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6584         if (ret < 0)
6585                 return ret;
6586
6587         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6588                                          &filter_5tuple);
6589         if (filter == NULL) {
6590                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6591                 return -ENOENT;
6592         }
6593         ntuple_filter->queue = filter->queue;
6594         return 0;
6595 }
6596
6597 /*
6598  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6599  * @dev: pointer to rte_eth_dev structure
6600  * @filter_op:operation will be taken.
6601  * @arg: a pointer to specific structure corresponding to the filter_op
6602  *
6603  * @return
6604  *    - On success, zero.
6605  *    - On failure, a negative value.
6606  */
6607 static int
6608 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6609                                 enum rte_filter_op filter_op,
6610                                 void *arg)
6611 {
6612         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6613         int ret;
6614
6615         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6616
6617         if (filter_op == RTE_ETH_FILTER_NOP)
6618                 return 0;
6619
6620         if (arg == NULL) {
6621                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6622                             filter_op);
6623                 return -EINVAL;
6624         }
6625
6626         switch (filter_op) {
6627         case RTE_ETH_FILTER_ADD:
6628                 ret = ixgbe_add_del_ntuple_filter(dev,
6629                         (struct rte_eth_ntuple_filter *)arg,
6630                         TRUE);
6631                 break;
6632         case RTE_ETH_FILTER_DELETE:
6633                 ret = ixgbe_add_del_ntuple_filter(dev,
6634                         (struct rte_eth_ntuple_filter *)arg,
6635                         FALSE);
6636                 break;
6637         case RTE_ETH_FILTER_GET:
6638                 ret = ixgbe_get_ntuple_filter(dev,
6639                         (struct rte_eth_ntuple_filter *)arg);
6640                 break;
6641         default:
6642                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6643                 ret = -EINVAL;
6644                 break;
6645         }
6646         return ret;
6647 }
6648
6649 int
6650 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6651                         struct rte_eth_ethertype_filter *filter,
6652                         bool add)
6653 {
6654         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6655         struct ixgbe_filter_info *filter_info =
6656                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6657         uint32_t etqf = 0;
6658         uint32_t etqs = 0;
6659         int ret;
6660         struct ixgbe_ethertype_filter ethertype_filter;
6661
6662         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6663                 return -EINVAL;
6664
6665         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6666                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6667                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6668                         " ethertype filter.", filter->ether_type);
6669                 return -EINVAL;
6670         }
6671
6672         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6673                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6674                 return -EINVAL;
6675         }
6676         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6677                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6678                 return -EINVAL;
6679         }
6680
6681         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6682         if (ret >= 0 && add) {
6683                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6684                             filter->ether_type);
6685                 return -EEXIST;
6686         }
6687         if (ret < 0 && !add) {
6688                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6689                             filter->ether_type);
6690                 return -ENOENT;
6691         }
6692
6693         if (add) {
6694                 etqf = IXGBE_ETQF_FILTER_EN;
6695                 etqf |= (uint32_t)filter->ether_type;
6696                 etqs |= (uint32_t)((filter->queue <<
6697                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6698                                     IXGBE_ETQS_RX_QUEUE);
6699                 etqs |= IXGBE_ETQS_QUEUE_EN;
6700
6701                 ethertype_filter.ethertype = filter->ether_type;
6702                 ethertype_filter.etqf = etqf;
6703                 ethertype_filter.etqs = etqs;
6704                 ethertype_filter.conf = FALSE;
6705                 ret = ixgbe_ethertype_filter_insert(filter_info,
6706                                                     &ethertype_filter);
6707                 if (ret < 0) {
6708                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6709                         return -ENOSPC;
6710                 }
6711         } else {
6712                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6713                 if (ret < 0)
6714                         return -ENOSYS;
6715         }
6716         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6717         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6718         IXGBE_WRITE_FLUSH(hw);
6719
6720         return 0;
6721 }
6722
6723 static int
6724 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6725                         struct rte_eth_ethertype_filter *filter)
6726 {
6727         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6728         struct ixgbe_filter_info *filter_info =
6729                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6730         uint32_t etqf, etqs;
6731         int ret;
6732
6733         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6734         if (ret < 0) {
6735                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6736                             filter->ether_type);
6737                 return -ENOENT;
6738         }
6739
6740         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6741         if (etqf & IXGBE_ETQF_FILTER_EN) {
6742                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6743                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6744                 filter->flags = 0;
6745                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6746                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6747                 return 0;
6748         }
6749         return -ENOENT;
6750 }
6751
6752 /*
6753  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6754  * @dev: pointer to rte_eth_dev structure
6755  * @filter_op:operation will be taken.
6756  * @arg: a pointer to specific structure corresponding to the filter_op
6757  */
6758 static int
6759 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6760                                 enum rte_filter_op filter_op,
6761                                 void *arg)
6762 {
6763         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6764         int ret;
6765
6766         MAC_TYPE_FILTER_SUP(hw->mac.type);
6767
6768         if (filter_op == RTE_ETH_FILTER_NOP)
6769                 return 0;
6770
6771         if (arg == NULL) {
6772                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6773                             filter_op);
6774                 return -EINVAL;
6775         }
6776
6777         switch (filter_op) {
6778         case RTE_ETH_FILTER_ADD:
6779                 ret = ixgbe_add_del_ethertype_filter(dev,
6780                         (struct rte_eth_ethertype_filter *)arg,
6781                         TRUE);
6782                 break;
6783         case RTE_ETH_FILTER_DELETE:
6784                 ret = ixgbe_add_del_ethertype_filter(dev,
6785                         (struct rte_eth_ethertype_filter *)arg,
6786                         FALSE);
6787                 break;
6788         case RTE_ETH_FILTER_GET:
6789                 ret = ixgbe_get_ethertype_filter(dev,
6790                         (struct rte_eth_ethertype_filter *)arg);
6791                 break;
6792         default:
6793                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6794                 ret = -EINVAL;
6795                 break;
6796         }
6797         return ret;
6798 }
6799
6800 static int
6801 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6802                      enum rte_filter_type filter_type,
6803                      enum rte_filter_op filter_op,
6804                      void *arg)
6805 {
6806         int ret = 0;
6807
6808         switch (filter_type) {
6809         case RTE_ETH_FILTER_NTUPLE:
6810                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6811                 break;
6812         case RTE_ETH_FILTER_ETHERTYPE:
6813                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6814                 break;
6815         case RTE_ETH_FILTER_SYN:
6816                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6817                 break;
6818         case RTE_ETH_FILTER_FDIR:
6819                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6820                 break;
6821         case RTE_ETH_FILTER_L2_TUNNEL:
6822                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6823                 break;
6824         case RTE_ETH_FILTER_GENERIC:
6825                 if (filter_op != RTE_ETH_FILTER_GET)
6826                         return -EINVAL;
6827                 *(const void **)arg = &ixgbe_flow_ops;
6828                 break;
6829         default:
6830                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6831                                                         filter_type);
6832                 ret = -EINVAL;
6833                 break;
6834         }
6835
6836         return ret;
6837 }
6838
6839 static u8 *
6840 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6841                         u8 **mc_addr_ptr, u32 *vmdq)
6842 {
6843         u8 *mc_addr;
6844
6845         *vmdq = 0;
6846         mc_addr = *mc_addr_ptr;
6847         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6848         return mc_addr;
6849 }
6850
6851 static int
6852 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6853                           struct rte_ether_addr *mc_addr_set,
6854                           uint32_t nb_mc_addr)
6855 {
6856         struct ixgbe_hw *hw;
6857         u8 *mc_addr_list;
6858
6859         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6860         mc_addr_list = (u8 *)mc_addr_set;
6861         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6862                                          ixgbe_dev_addr_list_itr, TRUE);
6863 }
6864
6865 static uint64_t
6866 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6867 {
6868         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6869         uint64_t systime_cycles;
6870
6871         switch (hw->mac.type) {
6872         case ixgbe_mac_X550:
6873         case ixgbe_mac_X550EM_x:
6874         case ixgbe_mac_X550EM_a:
6875                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6876                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6877                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6878                                 * NSEC_PER_SEC;
6879                 break;
6880         default:
6881                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6882                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6883                                 << 32;
6884         }
6885
6886         return systime_cycles;
6887 }
6888
6889 static uint64_t
6890 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6891 {
6892         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6893         uint64_t rx_tstamp_cycles;
6894
6895         switch (hw->mac.type) {
6896         case ixgbe_mac_X550:
6897         case ixgbe_mac_X550EM_x:
6898         case ixgbe_mac_X550EM_a:
6899                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6900                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6901                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6902                                 * NSEC_PER_SEC;
6903                 break;
6904         default:
6905                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6906                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6907                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6908                                 << 32;
6909         }
6910
6911         return rx_tstamp_cycles;
6912 }
6913
6914 static uint64_t
6915 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6916 {
6917         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6918         uint64_t tx_tstamp_cycles;
6919
6920         switch (hw->mac.type) {
6921         case ixgbe_mac_X550:
6922         case ixgbe_mac_X550EM_x:
6923         case ixgbe_mac_X550EM_a:
6924                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6925                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6926                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6927                                 * NSEC_PER_SEC;
6928                 break;
6929         default:
6930                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6931                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6932                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6933                                 << 32;
6934         }
6935
6936         return tx_tstamp_cycles;
6937 }
6938
6939 static void
6940 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6941 {
6942         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6943         struct ixgbe_adapter *adapter = dev->data->dev_private;
6944         struct rte_eth_link link;
6945         uint32_t incval = 0;
6946         uint32_t shift = 0;
6947
6948         /* Get current link speed. */
6949         ixgbe_dev_link_update(dev, 1);
6950         rte_eth_linkstatus_get(dev, &link);
6951
6952         switch (link.link_speed) {
6953         case ETH_SPEED_NUM_100M:
6954                 incval = IXGBE_INCVAL_100;
6955                 shift = IXGBE_INCVAL_SHIFT_100;
6956                 break;
6957         case ETH_SPEED_NUM_1G:
6958                 incval = IXGBE_INCVAL_1GB;
6959                 shift = IXGBE_INCVAL_SHIFT_1GB;
6960                 break;
6961         case ETH_SPEED_NUM_10G:
6962         default:
6963                 incval = IXGBE_INCVAL_10GB;
6964                 shift = IXGBE_INCVAL_SHIFT_10GB;
6965                 break;
6966         }
6967
6968         switch (hw->mac.type) {
6969         case ixgbe_mac_X550:
6970         case ixgbe_mac_X550EM_x:
6971         case ixgbe_mac_X550EM_a:
6972                 /* Independent of link speed. */
6973                 incval = 1;
6974                 /* Cycles read will be interpreted as ns. */
6975                 shift = 0;
6976                 /* Fall-through */
6977         case ixgbe_mac_X540:
6978                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6979                 break;
6980         case ixgbe_mac_82599EB:
6981                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6982                 shift -= IXGBE_INCVAL_SHIFT_82599;
6983                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6984                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6985                 break;
6986         default:
6987                 /* Not supported. */
6988                 return;
6989         }
6990
6991         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6992         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6993         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6994
6995         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6996         adapter->systime_tc.cc_shift = shift;
6997         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6998
6999         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7000         adapter->rx_tstamp_tc.cc_shift = shift;
7001         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7002
7003         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7004         adapter->tx_tstamp_tc.cc_shift = shift;
7005         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7006 }
7007
7008 static int
7009 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7010 {
7011         struct ixgbe_adapter *adapter = dev->data->dev_private;
7012
7013         adapter->systime_tc.nsec += delta;
7014         adapter->rx_tstamp_tc.nsec += delta;
7015         adapter->tx_tstamp_tc.nsec += delta;
7016
7017         return 0;
7018 }
7019
7020 static int
7021 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7022 {
7023         uint64_t ns;
7024         struct ixgbe_adapter *adapter = dev->data->dev_private;
7025
7026         ns = rte_timespec_to_ns(ts);
7027         /* Set the timecounters to a new value. */
7028         adapter->systime_tc.nsec = ns;
7029         adapter->rx_tstamp_tc.nsec = ns;
7030         adapter->tx_tstamp_tc.nsec = ns;
7031
7032         return 0;
7033 }
7034
7035 static int
7036 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7037 {
7038         uint64_t ns, systime_cycles;
7039         struct ixgbe_adapter *adapter = dev->data->dev_private;
7040
7041         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7042         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7043         *ts = rte_ns_to_timespec(ns);
7044
7045         return 0;
7046 }
7047
7048 static int
7049 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7050 {
7051         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7052         uint32_t tsync_ctl;
7053         uint32_t tsauxc;
7054
7055         /* Stop the timesync system time. */
7056         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7057         /* Reset the timesync system time value. */
7058         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7059         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7060
7061         /* Enable system time for platforms where it isn't on by default. */
7062         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7063         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7064         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7065
7066         ixgbe_start_timecounters(dev);
7067
7068         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7069         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7070                         (RTE_ETHER_TYPE_1588 |
7071                          IXGBE_ETQF_FILTER_EN |
7072                          IXGBE_ETQF_1588));
7073
7074         /* Enable timestamping of received PTP packets. */
7075         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7076         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7077         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7078
7079         /* Enable timestamping of transmitted PTP packets. */
7080         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7081         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7082         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7083
7084         IXGBE_WRITE_FLUSH(hw);
7085
7086         return 0;
7087 }
7088
7089 static int
7090 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7091 {
7092         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7093         uint32_t tsync_ctl;
7094
7095         /* Disable timestamping of transmitted PTP packets. */
7096         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7097         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7098         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7099
7100         /* Disable timestamping of received PTP packets. */
7101         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7102         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7103         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7104
7105         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7106         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7107
7108         /* Stop incrementating the System Time registers. */
7109         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7110
7111         return 0;
7112 }
7113
7114 static int
7115 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7116                                  struct timespec *timestamp,
7117                                  uint32_t flags __rte_unused)
7118 {
7119         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7120         struct ixgbe_adapter *adapter = dev->data->dev_private;
7121         uint32_t tsync_rxctl;
7122         uint64_t rx_tstamp_cycles;
7123         uint64_t ns;
7124
7125         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7126         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7127                 return -EINVAL;
7128
7129         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7130         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7131         *timestamp = rte_ns_to_timespec(ns);
7132
7133         return  0;
7134 }
7135
7136 static int
7137 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7138                                  struct timespec *timestamp)
7139 {
7140         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7141         struct ixgbe_adapter *adapter = dev->data->dev_private;
7142         uint32_t tsync_txctl;
7143         uint64_t tx_tstamp_cycles;
7144         uint64_t ns;
7145
7146         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7147         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7148                 return -EINVAL;
7149
7150         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7151         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7152         *timestamp = rte_ns_to_timespec(ns);
7153
7154         return 0;
7155 }
7156
7157 static int
7158 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7159 {
7160         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7161         int count = 0;
7162         int g_ind = 0;
7163         const struct reg_info *reg_group;
7164         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7165                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7166
7167         while ((reg_group = reg_set[g_ind++]))
7168                 count += ixgbe_regs_group_count(reg_group);
7169
7170         return count;
7171 }
7172
7173 static int
7174 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7175 {
7176         int count = 0;
7177         int g_ind = 0;
7178         const struct reg_info *reg_group;
7179
7180         while ((reg_group = ixgbevf_regs[g_ind++]))
7181                 count += ixgbe_regs_group_count(reg_group);
7182
7183         return count;
7184 }
7185
7186 static int
7187 ixgbe_get_regs(struct rte_eth_dev *dev,
7188               struct rte_dev_reg_info *regs)
7189 {
7190         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7191         uint32_t *data = regs->data;
7192         int g_ind = 0;
7193         int count = 0;
7194         const struct reg_info *reg_group;
7195         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7196                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7197
7198         if (data == NULL) {
7199                 regs->length = ixgbe_get_reg_length(dev);
7200                 regs->width = sizeof(uint32_t);
7201                 return 0;
7202         }
7203
7204         /* Support only full register dump */
7205         if ((regs->length == 0) ||
7206             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7207                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7208                         hw->device_id;
7209                 while ((reg_group = reg_set[g_ind++]))
7210                         count += ixgbe_read_regs_group(dev, &data[count],
7211                                 reg_group);
7212                 return 0;
7213         }
7214
7215         return -ENOTSUP;
7216 }
7217
7218 static int
7219 ixgbevf_get_regs(struct rte_eth_dev *dev,
7220                 struct rte_dev_reg_info *regs)
7221 {
7222         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7223         uint32_t *data = regs->data;
7224         int g_ind = 0;
7225         int count = 0;
7226         const struct reg_info *reg_group;
7227
7228         if (data == NULL) {
7229                 regs->length = ixgbevf_get_reg_length(dev);
7230                 regs->width = sizeof(uint32_t);
7231                 return 0;
7232         }
7233
7234         /* Support only full register dump */
7235         if ((regs->length == 0) ||
7236             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7237                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7238                         hw->device_id;
7239                 while ((reg_group = ixgbevf_regs[g_ind++]))
7240                         count += ixgbe_read_regs_group(dev, &data[count],
7241                                                       reg_group);
7242                 return 0;
7243         }
7244
7245         return -ENOTSUP;
7246 }
7247
7248 static int
7249 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7250 {
7251         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7252
7253         /* Return unit is byte count */
7254         return hw->eeprom.word_size * 2;
7255 }
7256
7257 static int
7258 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7259                 struct rte_dev_eeprom_info *in_eeprom)
7260 {
7261         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7262         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7263         uint16_t *data = in_eeprom->data;
7264         int first, length;
7265
7266         first = in_eeprom->offset >> 1;
7267         length = in_eeprom->length >> 1;
7268         if ((first > hw->eeprom.word_size) ||
7269             ((first + length) > hw->eeprom.word_size))
7270                 return -EINVAL;
7271
7272         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7273
7274         return eeprom->ops.read_buffer(hw, first, length, data);
7275 }
7276
7277 static int
7278 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7279                 struct rte_dev_eeprom_info *in_eeprom)
7280 {
7281         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7282         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7283         uint16_t *data = in_eeprom->data;
7284         int first, length;
7285
7286         first = in_eeprom->offset >> 1;
7287         length = in_eeprom->length >> 1;
7288         if ((first > hw->eeprom.word_size) ||
7289             ((first + length) > hw->eeprom.word_size))
7290                 return -EINVAL;
7291
7292         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7293
7294         return eeprom->ops.write_buffer(hw,  first, length, data);
7295 }
7296
7297 static int
7298 ixgbe_get_module_info(struct rte_eth_dev *dev,
7299                       struct rte_eth_dev_module_info *modinfo)
7300 {
7301         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7302         uint32_t status;
7303         uint8_t sff8472_rev, addr_mode;
7304         bool page_swap = false;
7305
7306         /* Check whether we support SFF-8472 or not */
7307         status = hw->phy.ops.read_i2c_eeprom(hw,
7308                                              IXGBE_SFF_SFF_8472_COMP,
7309                                              &sff8472_rev);
7310         if (status != 0)
7311                 return -EIO;
7312
7313         /* addressing mode is not supported */
7314         status = hw->phy.ops.read_i2c_eeprom(hw,
7315                                              IXGBE_SFF_SFF_8472_SWAP,
7316                                              &addr_mode);
7317         if (status != 0)
7318                 return -EIO;
7319
7320         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7321                 PMD_DRV_LOG(ERR,
7322                             "Address change required to access page 0xA2, "
7323                             "but not supported. Please report the module "
7324                             "type to the driver maintainers.");
7325                 page_swap = true;
7326         }
7327
7328         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7329                 /* We have a SFP, but it does not support SFF-8472 */
7330                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7331                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7332         } else {
7333                 /* We have a SFP which supports a revision of SFF-8472. */
7334                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7335                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7336         }
7337
7338         return 0;
7339 }
7340
7341 static int
7342 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7343                         struct rte_dev_eeprom_info *info)
7344 {
7345         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7346         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7347         uint8_t databyte = 0xFF;
7348         uint8_t *data = info->data;
7349         uint32_t i = 0;
7350
7351         if (info->length == 0)
7352                 return -EINVAL;
7353
7354         for (i = info->offset; i < info->offset + info->length; i++) {
7355                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7356                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7357                 else
7358                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7359
7360                 if (status != 0)
7361                         return -EIO;
7362
7363                 data[i - info->offset] = databyte;
7364         }
7365
7366         return 0;
7367 }
7368
7369 uint16_t
7370 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7371         switch (mac_type) {
7372         case ixgbe_mac_X550:
7373         case ixgbe_mac_X550EM_x:
7374         case ixgbe_mac_X550EM_a:
7375                 return ETH_RSS_RETA_SIZE_512;
7376         case ixgbe_mac_X550_vf:
7377         case ixgbe_mac_X550EM_x_vf:
7378         case ixgbe_mac_X550EM_a_vf:
7379                 return ETH_RSS_RETA_SIZE_64;
7380         default:
7381                 return ETH_RSS_RETA_SIZE_128;
7382         }
7383 }
7384
7385 uint32_t
7386 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7387         switch (mac_type) {
7388         case ixgbe_mac_X550:
7389         case ixgbe_mac_X550EM_x:
7390         case ixgbe_mac_X550EM_a:
7391                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7392                         return IXGBE_RETA(reta_idx >> 2);
7393                 else
7394                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7395         case ixgbe_mac_X550_vf:
7396         case ixgbe_mac_X550EM_x_vf:
7397         case ixgbe_mac_X550EM_a_vf:
7398                 return IXGBE_VFRETA(reta_idx >> 2);
7399         default:
7400                 return IXGBE_RETA(reta_idx >> 2);
7401         }
7402 }
7403
7404 uint32_t
7405 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7406         switch (mac_type) {
7407         case ixgbe_mac_X550_vf:
7408         case ixgbe_mac_X550EM_x_vf:
7409         case ixgbe_mac_X550EM_a_vf:
7410                 return IXGBE_VFMRQC;
7411         default:
7412                 return IXGBE_MRQC;
7413         }
7414 }
7415
7416 uint32_t
7417 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7418         switch (mac_type) {
7419         case ixgbe_mac_X550_vf:
7420         case ixgbe_mac_X550EM_x_vf:
7421         case ixgbe_mac_X550EM_a_vf:
7422                 return IXGBE_VFRSSRK(i);
7423         default:
7424                 return IXGBE_RSSRK(i);
7425         }
7426 }
7427
7428 bool
7429 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7430         switch (mac_type) {
7431         case ixgbe_mac_82599_vf:
7432         case ixgbe_mac_X540_vf:
7433                 return 0;
7434         default:
7435                 return 1;
7436         }
7437 }
7438
7439 static int
7440 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7441                         struct rte_eth_dcb_info *dcb_info)
7442 {
7443         struct ixgbe_dcb_config *dcb_config =
7444                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7445         struct ixgbe_dcb_tc_config *tc;
7446         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7447         uint8_t nb_tcs;
7448         uint8_t i, j;
7449
7450         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7451                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7452         else
7453                 dcb_info->nb_tcs = 1;
7454
7455         tc_queue = &dcb_info->tc_queue;
7456         nb_tcs = dcb_info->nb_tcs;
7457
7458         if (dcb_config->vt_mode) { /* vt is enabled*/
7459                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7460                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7461                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7462                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7463                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7464                         for (j = 0; j < nb_tcs; j++) {
7465                                 tc_queue->tc_rxq[0][j].base = j;
7466                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7467                                 tc_queue->tc_txq[0][j].base = j;
7468                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7469                         }
7470                 } else {
7471                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7472                                 for (j = 0; j < nb_tcs; j++) {
7473                                         tc_queue->tc_rxq[i][j].base =
7474                                                 i * nb_tcs + j;
7475                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7476                                         tc_queue->tc_txq[i][j].base =
7477                                                 i * nb_tcs + j;
7478                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7479                                 }
7480                         }
7481                 }
7482         } else { /* vt is disabled*/
7483                 struct rte_eth_dcb_rx_conf *rx_conf =
7484                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7485                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7486                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7487                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7488                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7489                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7490                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7491                         }
7492                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7493                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7494                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7495                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7496                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7497                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7498                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7499                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7500                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7501                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7502                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7503                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7504                         }
7505                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7506                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7507                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7508                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7509                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7510                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7511                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7512                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7513                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7514                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7515                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7516                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7517                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7518                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7519                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7520                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7521                 }
7522         }
7523         for (i = 0; i < dcb_info->nb_tcs; i++) {
7524                 tc = &dcb_config->tc_config[i];
7525                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7526         }
7527         return 0;
7528 }
7529
7530 /* Update e-tag ether type */
7531 static int
7532 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7533                             uint16_t ether_type)
7534 {
7535         uint32_t etag_etype;
7536
7537         if (hw->mac.type != ixgbe_mac_X550 &&
7538             hw->mac.type != ixgbe_mac_X550EM_x &&
7539             hw->mac.type != ixgbe_mac_X550EM_a) {
7540                 return -ENOTSUP;
7541         }
7542
7543         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7544         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7545         etag_etype |= ether_type;
7546         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7547         IXGBE_WRITE_FLUSH(hw);
7548
7549         return 0;
7550 }
7551
7552 /* Config l2 tunnel ether type */
7553 static int
7554 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7555                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7556 {
7557         int ret = 0;
7558         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7559         struct ixgbe_l2_tn_info *l2_tn_info =
7560                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7561
7562         if (l2_tunnel == NULL)
7563                 return -EINVAL;
7564
7565         switch (l2_tunnel->l2_tunnel_type) {
7566         case RTE_L2_TUNNEL_TYPE_E_TAG:
7567                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7568                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7569                 break;
7570         default:
7571                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7572                 ret = -EINVAL;
7573                 break;
7574         }
7575
7576         return ret;
7577 }
7578
7579 /* Enable e-tag tunnel */
7580 static int
7581 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7582 {
7583         uint32_t etag_etype;
7584
7585         if (hw->mac.type != ixgbe_mac_X550 &&
7586             hw->mac.type != ixgbe_mac_X550EM_x &&
7587             hw->mac.type != ixgbe_mac_X550EM_a) {
7588                 return -ENOTSUP;
7589         }
7590
7591         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7592         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7593         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7594         IXGBE_WRITE_FLUSH(hw);
7595
7596         return 0;
7597 }
7598
7599 /* Enable l2 tunnel */
7600 static int
7601 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7602                            enum rte_eth_tunnel_type l2_tunnel_type)
7603 {
7604         int ret = 0;
7605         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7606         struct ixgbe_l2_tn_info *l2_tn_info =
7607                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7608
7609         switch (l2_tunnel_type) {
7610         case RTE_L2_TUNNEL_TYPE_E_TAG:
7611                 l2_tn_info->e_tag_en = TRUE;
7612                 ret = ixgbe_e_tag_enable(hw);
7613                 break;
7614         default:
7615                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7616                 ret = -EINVAL;
7617                 break;
7618         }
7619
7620         return ret;
7621 }
7622
7623 /* Disable e-tag tunnel */
7624 static int
7625 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7626 {
7627         uint32_t etag_etype;
7628
7629         if (hw->mac.type != ixgbe_mac_X550 &&
7630             hw->mac.type != ixgbe_mac_X550EM_x &&
7631             hw->mac.type != ixgbe_mac_X550EM_a) {
7632                 return -ENOTSUP;
7633         }
7634
7635         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7636         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7637         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7638         IXGBE_WRITE_FLUSH(hw);
7639
7640         return 0;
7641 }
7642
7643 /* Disable l2 tunnel */
7644 static int
7645 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7646                             enum rte_eth_tunnel_type l2_tunnel_type)
7647 {
7648         int ret = 0;
7649         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7650         struct ixgbe_l2_tn_info *l2_tn_info =
7651                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7652
7653         switch (l2_tunnel_type) {
7654         case RTE_L2_TUNNEL_TYPE_E_TAG:
7655                 l2_tn_info->e_tag_en = FALSE;
7656                 ret = ixgbe_e_tag_disable(hw);
7657                 break;
7658         default:
7659                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7660                 ret = -EINVAL;
7661                 break;
7662         }
7663
7664         return ret;
7665 }
7666
7667 static int
7668 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7669                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7670 {
7671         int ret = 0;
7672         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7673         uint32_t i, rar_entries;
7674         uint32_t rar_low, rar_high;
7675
7676         if (hw->mac.type != ixgbe_mac_X550 &&
7677             hw->mac.type != ixgbe_mac_X550EM_x &&
7678             hw->mac.type != ixgbe_mac_X550EM_a) {
7679                 return -ENOTSUP;
7680         }
7681
7682         rar_entries = ixgbe_get_num_rx_addrs(hw);
7683
7684         for (i = 1; i < rar_entries; i++) {
7685                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7686                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7687                 if ((rar_high & IXGBE_RAH_AV) &&
7688                     (rar_high & IXGBE_RAH_ADTYPE) &&
7689                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7690                      l2_tunnel->tunnel_id)) {
7691                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7692                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7693
7694                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7695
7696                         return ret;
7697                 }
7698         }
7699
7700         return ret;
7701 }
7702
7703 static int
7704 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7705                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7706 {
7707         int ret = 0;
7708         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7709         uint32_t i, rar_entries;
7710         uint32_t rar_low, rar_high;
7711
7712         if (hw->mac.type != ixgbe_mac_X550 &&
7713             hw->mac.type != ixgbe_mac_X550EM_x &&
7714             hw->mac.type != ixgbe_mac_X550EM_a) {
7715                 return -ENOTSUP;
7716         }
7717
7718         /* One entry for one tunnel. Try to remove potential existing entry. */
7719         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7720
7721         rar_entries = ixgbe_get_num_rx_addrs(hw);
7722
7723         for (i = 1; i < rar_entries; i++) {
7724                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7725                 if (rar_high & IXGBE_RAH_AV) {
7726                         continue;
7727                 } else {
7728                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7729                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7730                         rar_low = l2_tunnel->tunnel_id;
7731
7732                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7733                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7734
7735                         return ret;
7736                 }
7737         }
7738
7739         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7740                      " Please remove a rule before adding a new one.");
7741         return -EINVAL;
7742 }
7743
7744 static inline struct ixgbe_l2_tn_filter *
7745 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7746                           struct ixgbe_l2_tn_key *key)
7747 {
7748         int ret;
7749
7750         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7751         if (ret < 0)
7752                 return NULL;
7753
7754         return l2_tn_info->hash_map[ret];
7755 }
7756
7757 static inline int
7758 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7759                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7760 {
7761         int ret;
7762
7763         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7764                                &l2_tn_filter->key);
7765
7766         if (ret < 0) {
7767                 PMD_DRV_LOG(ERR,
7768                             "Failed to insert L2 tunnel filter"
7769                             " to hash table %d!",
7770                             ret);
7771                 return ret;
7772         }
7773
7774         l2_tn_info->hash_map[ret] = l2_tn_filter;
7775
7776         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7777
7778         return 0;
7779 }
7780
7781 static inline int
7782 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7783                           struct ixgbe_l2_tn_key *key)
7784 {
7785         int ret;
7786         struct ixgbe_l2_tn_filter *l2_tn_filter;
7787
7788         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7789
7790         if (ret < 0) {
7791                 PMD_DRV_LOG(ERR,
7792                             "No such L2 tunnel filter to delete %d!",
7793                             ret);
7794                 return ret;
7795         }
7796
7797         l2_tn_filter = l2_tn_info->hash_map[ret];
7798         l2_tn_info->hash_map[ret] = NULL;
7799
7800         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7801         rte_free(l2_tn_filter);
7802
7803         return 0;
7804 }
7805
7806 /* Add l2 tunnel filter */
7807 int
7808 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7809                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7810                                bool restore)
7811 {
7812         int ret;
7813         struct ixgbe_l2_tn_info *l2_tn_info =
7814                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7815         struct ixgbe_l2_tn_key key;
7816         struct ixgbe_l2_tn_filter *node;
7817
7818         if (!restore) {
7819                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7820                 key.tn_id = l2_tunnel->tunnel_id;
7821
7822                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7823
7824                 if (node) {
7825                         PMD_DRV_LOG(ERR,
7826                                     "The L2 tunnel filter already exists!");
7827                         return -EINVAL;
7828                 }
7829
7830                 node = rte_zmalloc("ixgbe_l2_tn",
7831                                    sizeof(struct ixgbe_l2_tn_filter),
7832                                    0);
7833                 if (!node)
7834                         return -ENOMEM;
7835
7836                 rte_memcpy(&node->key,
7837                                  &key,
7838                                  sizeof(struct ixgbe_l2_tn_key));
7839                 node->pool = l2_tunnel->pool;
7840                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7841                 if (ret < 0) {
7842                         rte_free(node);
7843                         return ret;
7844                 }
7845         }
7846
7847         switch (l2_tunnel->l2_tunnel_type) {
7848         case RTE_L2_TUNNEL_TYPE_E_TAG:
7849                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7850                 break;
7851         default:
7852                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7853                 ret = -EINVAL;
7854                 break;
7855         }
7856
7857         if ((!restore) && (ret < 0))
7858                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7859
7860         return ret;
7861 }
7862
7863 /* Delete l2 tunnel filter */
7864 int
7865 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7866                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7867 {
7868         int ret;
7869         struct ixgbe_l2_tn_info *l2_tn_info =
7870                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7871         struct ixgbe_l2_tn_key key;
7872
7873         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7874         key.tn_id = l2_tunnel->tunnel_id;
7875         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7876         if (ret < 0)
7877                 return ret;
7878
7879         switch (l2_tunnel->l2_tunnel_type) {
7880         case RTE_L2_TUNNEL_TYPE_E_TAG:
7881                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7882                 break;
7883         default:
7884                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7885                 ret = -EINVAL;
7886                 break;
7887         }
7888
7889         return ret;
7890 }
7891
7892 /**
7893  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7894  * @dev: pointer to rte_eth_dev structure
7895  * @filter_op:operation will be taken.
7896  * @arg: a pointer to specific structure corresponding to the filter_op
7897  */
7898 static int
7899 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7900                                   enum rte_filter_op filter_op,
7901                                   void *arg)
7902 {
7903         int ret;
7904
7905         if (filter_op == RTE_ETH_FILTER_NOP)
7906                 return 0;
7907
7908         if (arg == NULL) {
7909                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7910                             filter_op);
7911                 return -EINVAL;
7912         }
7913
7914         switch (filter_op) {
7915         case RTE_ETH_FILTER_ADD:
7916                 ret = ixgbe_dev_l2_tunnel_filter_add
7917                         (dev,
7918                          (struct rte_eth_l2_tunnel_conf *)arg,
7919                          FALSE);
7920                 break;
7921         case RTE_ETH_FILTER_DELETE:
7922                 ret = ixgbe_dev_l2_tunnel_filter_del
7923                         (dev,
7924                          (struct rte_eth_l2_tunnel_conf *)arg);
7925                 break;
7926         default:
7927                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7928                 ret = -EINVAL;
7929                 break;
7930         }
7931         return ret;
7932 }
7933
7934 static int
7935 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7936 {
7937         int ret = 0;
7938         uint32_t ctrl;
7939         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7940
7941         if (hw->mac.type != ixgbe_mac_X550 &&
7942             hw->mac.type != ixgbe_mac_X550EM_x &&
7943             hw->mac.type != ixgbe_mac_X550EM_a) {
7944                 return -ENOTSUP;
7945         }
7946
7947         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7948         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7949         if (en)
7950                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7951         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7952
7953         return ret;
7954 }
7955
7956 /* Enable l2 tunnel forwarding */
7957 static int
7958 ixgbe_dev_l2_tunnel_forwarding_enable
7959         (struct rte_eth_dev *dev,
7960          enum rte_eth_tunnel_type l2_tunnel_type)
7961 {
7962         struct ixgbe_l2_tn_info *l2_tn_info =
7963                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7964         int ret = 0;
7965
7966         switch (l2_tunnel_type) {
7967         case RTE_L2_TUNNEL_TYPE_E_TAG:
7968                 l2_tn_info->e_tag_fwd_en = TRUE;
7969                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7970                 break;
7971         default:
7972                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7973                 ret = -EINVAL;
7974                 break;
7975         }
7976
7977         return ret;
7978 }
7979
7980 /* Disable l2 tunnel forwarding */
7981 static int
7982 ixgbe_dev_l2_tunnel_forwarding_disable
7983         (struct rte_eth_dev *dev,
7984          enum rte_eth_tunnel_type l2_tunnel_type)
7985 {
7986         struct ixgbe_l2_tn_info *l2_tn_info =
7987                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7988         int ret = 0;
7989
7990         switch (l2_tunnel_type) {
7991         case RTE_L2_TUNNEL_TYPE_E_TAG:
7992                 l2_tn_info->e_tag_fwd_en = FALSE;
7993                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7994                 break;
7995         default:
7996                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7997                 ret = -EINVAL;
7998                 break;
7999         }
8000
8001         return ret;
8002 }
8003
8004 static int
8005 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8006                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
8007                              bool en)
8008 {
8009         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8010         int ret = 0;
8011         uint32_t vmtir, vmvir;
8012         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8013
8014         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8015                 PMD_DRV_LOG(ERR,
8016                             "VF id %u should be less than %u",
8017                             l2_tunnel->vf_id,
8018                             pci_dev->max_vfs);
8019                 return -EINVAL;
8020         }
8021
8022         if (hw->mac.type != ixgbe_mac_X550 &&
8023             hw->mac.type != ixgbe_mac_X550EM_x &&
8024             hw->mac.type != ixgbe_mac_X550EM_a) {
8025                 return -ENOTSUP;
8026         }
8027
8028         if (en)
8029                 vmtir = l2_tunnel->tunnel_id;
8030         else
8031                 vmtir = 0;
8032
8033         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8034
8035         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8036         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8037         if (en)
8038                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8039         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8040
8041         return ret;
8042 }
8043
8044 /* Enable l2 tunnel tag insertion */
8045 static int
8046 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8047                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8048 {
8049         int ret = 0;
8050
8051         switch (l2_tunnel->l2_tunnel_type) {
8052         case RTE_L2_TUNNEL_TYPE_E_TAG:
8053                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8054                 break;
8055         default:
8056                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8057                 ret = -EINVAL;
8058                 break;
8059         }
8060
8061         return ret;
8062 }
8063
8064 /* Disable l2 tunnel tag insertion */
8065 static int
8066 ixgbe_dev_l2_tunnel_insertion_disable
8067         (struct rte_eth_dev *dev,
8068          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8069 {
8070         int ret = 0;
8071
8072         switch (l2_tunnel->l2_tunnel_type) {
8073         case RTE_L2_TUNNEL_TYPE_E_TAG:
8074                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8075                 break;
8076         default:
8077                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8078                 ret = -EINVAL;
8079                 break;
8080         }
8081
8082         return ret;
8083 }
8084
8085 static int
8086 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8087                              bool en)
8088 {
8089         int ret = 0;
8090         uint32_t qde;
8091         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8092
8093         if (hw->mac.type != ixgbe_mac_X550 &&
8094             hw->mac.type != ixgbe_mac_X550EM_x &&
8095             hw->mac.type != ixgbe_mac_X550EM_a) {
8096                 return -ENOTSUP;
8097         }
8098
8099         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8100         if (en)
8101                 qde |= IXGBE_QDE_STRIP_TAG;
8102         else
8103                 qde &= ~IXGBE_QDE_STRIP_TAG;
8104         qde &= ~IXGBE_QDE_READ;
8105         qde |= IXGBE_QDE_WRITE;
8106         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8107
8108         return ret;
8109 }
8110
8111 /* Enable l2 tunnel tag stripping */
8112 static int
8113 ixgbe_dev_l2_tunnel_stripping_enable
8114         (struct rte_eth_dev *dev,
8115          enum rte_eth_tunnel_type l2_tunnel_type)
8116 {
8117         int ret = 0;
8118
8119         switch (l2_tunnel_type) {
8120         case RTE_L2_TUNNEL_TYPE_E_TAG:
8121                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8122                 break;
8123         default:
8124                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8125                 ret = -EINVAL;
8126                 break;
8127         }
8128
8129         return ret;
8130 }
8131
8132 /* Disable l2 tunnel tag stripping */
8133 static int
8134 ixgbe_dev_l2_tunnel_stripping_disable
8135         (struct rte_eth_dev *dev,
8136          enum rte_eth_tunnel_type l2_tunnel_type)
8137 {
8138         int ret = 0;
8139
8140         switch (l2_tunnel_type) {
8141         case RTE_L2_TUNNEL_TYPE_E_TAG:
8142                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8143                 break;
8144         default:
8145                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8146                 ret = -EINVAL;
8147                 break;
8148         }
8149
8150         return ret;
8151 }
8152
8153 /* Enable/disable l2 tunnel offload functions */
8154 static int
8155 ixgbe_dev_l2_tunnel_offload_set
8156         (struct rte_eth_dev *dev,
8157          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8158          uint32_t mask,
8159          uint8_t en)
8160 {
8161         int ret = 0;
8162
8163         if (l2_tunnel == NULL)
8164                 return -EINVAL;
8165
8166         ret = -EINVAL;
8167         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8168                 if (en)
8169                         ret = ixgbe_dev_l2_tunnel_enable(
8170                                 dev,
8171                                 l2_tunnel->l2_tunnel_type);
8172                 else
8173                         ret = ixgbe_dev_l2_tunnel_disable(
8174                                 dev,
8175                                 l2_tunnel->l2_tunnel_type);
8176         }
8177
8178         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8179                 if (en)
8180                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8181                                 dev,
8182                                 l2_tunnel);
8183                 else
8184                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8185                                 dev,
8186                                 l2_tunnel);
8187         }
8188
8189         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8190                 if (en)
8191                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8192                                 dev,
8193                                 l2_tunnel->l2_tunnel_type);
8194                 else
8195                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8196                                 dev,
8197                                 l2_tunnel->l2_tunnel_type);
8198         }
8199
8200         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8201                 if (en)
8202                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8203                                 dev,
8204                                 l2_tunnel->l2_tunnel_type);
8205                 else
8206                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8207                                 dev,
8208                                 l2_tunnel->l2_tunnel_type);
8209         }
8210
8211         return ret;
8212 }
8213
8214 static int
8215 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8216                         uint16_t port)
8217 {
8218         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8219         IXGBE_WRITE_FLUSH(hw);
8220
8221         return 0;
8222 }
8223
8224 /* There's only one register for VxLAN UDP port.
8225  * So, we cannot add several ports. Will update it.
8226  */
8227 static int
8228 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8229                      uint16_t port)
8230 {
8231         if (port == 0) {
8232                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8233                 return -EINVAL;
8234         }
8235
8236         return ixgbe_update_vxlan_port(hw, port);
8237 }
8238
8239 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8240  * UDP port, it must have a value.
8241  * So, will reset it to the original value 0.
8242  */
8243 static int
8244 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8245                      uint16_t port)
8246 {
8247         uint16_t cur_port;
8248
8249         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8250
8251         if (cur_port != port) {
8252                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8253                 return -EINVAL;
8254         }
8255
8256         return ixgbe_update_vxlan_port(hw, 0);
8257 }
8258
8259 /* Add UDP tunneling port */
8260 static int
8261 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8262                               struct rte_eth_udp_tunnel *udp_tunnel)
8263 {
8264         int ret = 0;
8265         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8266
8267         if (hw->mac.type != ixgbe_mac_X550 &&
8268             hw->mac.type != ixgbe_mac_X550EM_x &&
8269             hw->mac.type != ixgbe_mac_X550EM_a) {
8270                 return -ENOTSUP;
8271         }
8272
8273         if (udp_tunnel == NULL)
8274                 return -EINVAL;
8275
8276         switch (udp_tunnel->prot_type) {
8277         case RTE_TUNNEL_TYPE_VXLAN:
8278                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8279                 break;
8280
8281         case RTE_TUNNEL_TYPE_GENEVE:
8282         case RTE_TUNNEL_TYPE_TEREDO:
8283                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8284                 ret = -EINVAL;
8285                 break;
8286
8287         default:
8288                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8289                 ret = -EINVAL;
8290                 break;
8291         }
8292
8293         return ret;
8294 }
8295
8296 /* Remove UDP tunneling port */
8297 static int
8298 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8299                               struct rte_eth_udp_tunnel *udp_tunnel)
8300 {
8301         int ret = 0;
8302         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8303
8304         if (hw->mac.type != ixgbe_mac_X550 &&
8305             hw->mac.type != ixgbe_mac_X550EM_x &&
8306             hw->mac.type != ixgbe_mac_X550EM_a) {
8307                 return -ENOTSUP;
8308         }
8309
8310         if (udp_tunnel == NULL)
8311                 return -EINVAL;
8312
8313         switch (udp_tunnel->prot_type) {
8314         case RTE_TUNNEL_TYPE_VXLAN:
8315                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8316                 break;
8317         case RTE_TUNNEL_TYPE_GENEVE:
8318         case RTE_TUNNEL_TYPE_TEREDO:
8319                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8320                 ret = -EINVAL;
8321                 break;
8322         default:
8323                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8324                 ret = -EINVAL;
8325                 break;
8326         }
8327
8328         return ret;
8329 }
8330
8331 static void
8332 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8333 {
8334         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8335
8336         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC);
8337 }
8338
8339 static void
8340 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8341 {
8342         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8343
8344         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
8345 }
8346
8347 static void
8348 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8349 {
8350         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8351
8352         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8353 }
8354
8355 static void
8356 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8357 {
8358         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8359
8360         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8361 }
8362
8363 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8364 {
8365         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8366         u32 in_msg = 0;
8367
8368         /* peek the message first */
8369         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8370
8371         /* PF reset VF event */
8372         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8373                 /* dummy mbx read to ack pf */
8374                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8375                         return;
8376                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8377                                               NULL);
8378         }
8379 }
8380
8381 static int
8382 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8383 {
8384         uint32_t eicr;
8385         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8386         struct ixgbe_interrupt *intr =
8387                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8388         ixgbevf_intr_disable(dev);
8389
8390         /* read-on-clear nic registers here */
8391         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8392         intr->flags = 0;
8393
8394         /* only one misc vector supported - mailbox */
8395         eicr &= IXGBE_VTEICR_MASK;
8396         if (eicr == IXGBE_MISC_VEC_ID)
8397                 intr->flags |= IXGBE_FLAG_MAILBOX;
8398
8399         return 0;
8400 }
8401
8402 static int
8403 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8404 {
8405         struct ixgbe_interrupt *intr =
8406                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8407
8408         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8409                 ixgbevf_mbx_process(dev);
8410                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8411         }
8412
8413         ixgbevf_intr_enable(dev);
8414
8415         return 0;
8416 }
8417
8418 static void
8419 ixgbevf_dev_interrupt_handler(void *param)
8420 {
8421         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8422
8423         ixgbevf_dev_interrupt_get_status(dev);
8424         ixgbevf_dev_interrupt_action(dev);
8425 }
8426
8427 /**
8428  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8429  *  @hw: pointer to hardware structure
8430  *
8431  *  Stops the transmit data path and waits for the HW to internally empty
8432  *  the Tx security block
8433  **/
8434 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8435 {
8436 #define IXGBE_MAX_SECTX_POLL 40
8437
8438         int i;
8439         int sectxreg;
8440
8441         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8442         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8443         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8444         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8445                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8446                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8447                         break;
8448                 /* Use interrupt-safe sleep just in case */
8449                 usec_delay(1000);
8450         }
8451
8452         /* For informational purposes only */
8453         if (i >= IXGBE_MAX_SECTX_POLL)
8454                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8455                          "path fully disabled.  Continuing with init.");
8456
8457         return IXGBE_SUCCESS;
8458 }
8459
8460 /**
8461  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8462  *  @hw: pointer to hardware structure
8463  *
8464  *  Enables the transmit data path.
8465  **/
8466 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8467 {
8468         uint32_t sectxreg;
8469
8470         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8471         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8472         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8473         IXGBE_WRITE_FLUSH(hw);
8474
8475         return IXGBE_SUCCESS;
8476 }
8477
8478 /* restore n-tuple filter */
8479 static inline void
8480 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8481 {
8482         struct ixgbe_filter_info *filter_info =
8483                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8484         struct ixgbe_5tuple_filter *node;
8485
8486         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8487                 ixgbe_inject_5tuple_filter(dev, node);
8488         }
8489 }
8490
8491 /* restore ethernet type filter */
8492 static inline void
8493 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8494 {
8495         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8496         struct ixgbe_filter_info *filter_info =
8497                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8498         int i;
8499
8500         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8501                 if (filter_info->ethertype_mask & (1 << i)) {
8502                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8503                                         filter_info->ethertype_filters[i].etqf);
8504                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8505                                         filter_info->ethertype_filters[i].etqs);
8506                         IXGBE_WRITE_FLUSH(hw);
8507                 }
8508         }
8509 }
8510
8511 /* restore SYN filter */
8512 static inline void
8513 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8514 {
8515         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8516         struct ixgbe_filter_info *filter_info =
8517                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8518         uint32_t synqf;
8519
8520         synqf = filter_info->syn_info;
8521
8522         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8523                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8524                 IXGBE_WRITE_FLUSH(hw);
8525         }
8526 }
8527
8528 /* restore L2 tunnel filter */
8529 static inline void
8530 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8531 {
8532         struct ixgbe_l2_tn_info *l2_tn_info =
8533                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8534         struct ixgbe_l2_tn_filter *node;
8535         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8536
8537         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8538                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8539                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8540                 l2_tn_conf.pool           = node->pool;
8541                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8542         }
8543 }
8544
8545 /* restore rss filter */
8546 static inline void
8547 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8548 {
8549         struct ixgbe_filter_info *filter_info =
8550                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8551
8552         if (filter_info->rss_info.conf.queue_num)
8553                 ixgbe_config_rss_filter(dev,
8554                         &filter_info->rss_info, TRUE);
8555 }
8556
8557 static int
8558 ixgbe_filter_restore(struct rte_eth_dev *dev)
8559 {
8560         ixgbe_ntuple_filter_restore(dev);
8561         ixgbe_ethertype_filter_restore(dev);
8562         ixgbe_syn_filter_restore(dev);
8563         ixgbe_fdir_filter_restore(dev);
8564         ixgbe_l2_tn_filter_restore(dev);
8565         ixgbe_rss_filter_restore(dev);
8566
8567         return 0;
8568 }
8569
8570 static void
8571 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8572 {
8573         struct ixgbe_l2_tn_info *l2_tn_info =
8574                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8575         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8576
8577         if (l2_tn_info->e_tag_en)
8578                 (void)ixgbe_e_tag_enable(hw);
8579
8580         if (l2_tn_info->e_tag_fwd_en)
8581                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8582
8583         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8584 }
8585
8586 /* remove all the n-tuple filters */
8587 void
8588 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8589 {
8590         struct ixgbe_filter_info *filter_info =
8591                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8592         struct ixgbe_5tuple_filter *p_5tuple;
8593
8594         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8595                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8596 }
8597
8598 /* remove all the ether type filters */
8599 void
8600 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8601 {
8602         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8603         struct ixgbe_filter_info *filter_info =
8604                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8605         int i;
8606
8607         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8608                 if (filter_info->ethertype_mask & (1 << i) &&
8609                     !filter_info->ethertype_filters[i].conf) {
8610                         (void)ixgbe_ethertype_filter_remove(filter_info,
8611                                                             (uint8_t)i);
8612                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8613                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8614                         IXGBE_WRITE_FLUSH(hw);
8615                 }
8616         }
8617 }
8618
8619 /* remove the SYN filter */
8620 void
8621 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8622 {
8623         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8624         struct ixgbe_filter_info *filter_info =
8625                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8626
8627         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8628                 filter_info->syn_info = 0;
8629
8630                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8631                 IXGBE_WRITE_FLUSH(hw);
8632         }
8633 }
8634
8635 /* remove all the L2 tunnel filters */
8636 int
8637 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8638 {
8639         struct ixgbe_l2_tn_info *l2_tn_info =
8640                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8641         struct ixgbe_l2_tn_filter *l2_tn_filter;
8642         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8643         int ret = 0;
8644
8645         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8646                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8647                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8648                 l2_tn_conf.pool           = l2_tn_filter->pool;
8649                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8650                 if (ret < 0)
8651                         return ret;
8652         }
8653
8654         return 0;
8655 }
8656
8657 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8658 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8659 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8660 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8661 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8662 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8663
8664 RTE_INIT(ixgbe_init_log)
8665 {
8666         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8667         if (ixgbe_logtype_init >= 0)
8668                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8669         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8670         if (ixgbe_logtype_driver >= 0)
8671                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8672 }