drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIBRTE_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void ixgbe_dev_setup_link_alarm_handler(void *param);
 233
 234 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 235                         struct rte_ether_addr *mac_addr,
 236                         uint32_t index, uint32_t pool);
 237 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 238 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 239                                            struct rte_ether_addr *mac_addr);
 240 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 241 static bool is_device_supported(struct rte_eth_dev *dev,
 242                                 struct rte_pci_driver *drv);
 243
 244 /* For Virtual Function support */
 245 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 246 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 247 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 248 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 249 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 250                                    int wait_to_complete);
 251 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 252 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 253 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 254 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 255 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 256 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 257                 struct rte_eth_stats *stats);
 258 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 259 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 260                 uint16_t vlan_id, int on);
 261 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 262                 uint16_t queue, int on);
 263 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 264 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 265 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 266 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 267                                             uint16_t queue_id);
 268 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 269                                              uint16_t queue_id);
 270 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 271                                  uint8_t queue, uint8_t msix_vector);
 272 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 273 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 274 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 275 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 276 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 277
 278 /* For Eth VMDQ APIs support */
 279 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 280                 rte_ether_addr * mac_addr, uint8_t on);
 281 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 282 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 283                 struct rte_eth_mirror_conf *mirror_conf,
 284                 uint8_t rule_id, uint8_t on);
 285 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 286                 uint8_t rule_id);
 287 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 288                                           uint16_t queue_id);
 289 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 290                                            uint16_t queue_id);
 291 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 292                                uint8_t queue, uint8_t msix_vector);
 293 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 294
 295 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 296                                 struct rte_ether_addr *mac_addr,
 297                                 uint32_t index, uint32_t pool);
 298 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 299 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 300                                              struct rte_ether_addr *mac_addr);
 301 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 302                         struct rte_eth_syn_filter *filter);
 303 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 304                         enum rte_filter_op filter_op,
 305                         void *arg);
 306 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 307                         struct ixgbe_5tuple_filter *filter);
 308 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 309                         struct ixgbe_5tuple_filter *filter);
 310 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 311                                 enum rte_filter_op filter_op,
 312                                 void *arg);
 313 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 314                         struct rte_eth_ntuple_filter *filter);
 315 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 316                                 enum rte_filter_op filter_op,
 317                                 void *arg);
 318 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 319                         struct rte_eth_ethertype_filter *filter);
 320 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 321                      enum rte_filter_type filter_type,
 322                      enum rte_filter_op filter_op,
 323                      void *arg);
 324 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 325
 326 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 327                                       struct rte_ether_addr *mc_addr_set,
 328                                       uint32_t nb_mc_addr);
 329 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 330                                    struct rte_eth_dcb_info *dcb_info);
 331
 332 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 333 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 334                             struct rte_dev_reg_info *regs);
 335 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 336 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 337                                 struct rte_dev_eeprom_info *eeprom);
 338 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 339                                 struct rte_dev_eeprom_info *eeprom);
 340
 341 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 342                                  struct rte_eth_dev_module_info *modinfo);
 343 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 344                                    struct rte_dev_eeprom_info *info);
 345
 346 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 347 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 348                                 struct rte_dev_reg_info *regs);
 349
 350 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 351 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 352 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 353                                             struct timespec *timestamp,
 354                                             uint32_t flags);
 355 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 356                                             struct timespec *timestamp);
 357 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 358 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 359                                    struct timespec *timestamp);
 360 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 361                                    const struct timespec *timestamp);
 362 static void ixgbevf_dev_interrupt_handler(void *param);
 363
 364 static int ixgbe_dev_l2_tunnel_eth_type_conf
 365         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 366 static int ixgbe_dev_l2_tunnel_offload_set
 367         (struct rte_eth_dev *dev,
 368          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 369          uint32_t mask,
 370          uint8_t en);
 371 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 372                                              enum rte_filter_op filter_op,
 373                                              void *arg);
 374
 375 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 376                                          struct rte_eth_udp_tunnel *udp_tunnel);
 377 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 380 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 381
 382 /*
 383  * Define VF Stats MACRO for Non "cleared on read" register
 384  */
 385 #define UPDATE_VF_STAT(reg, last, cur)                          \
 386 {                                                               \
 387         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 388         cur += (latest - last) & UINT_MAX;                      \
 389         last = latest;                                          \
 390 }
 391
 392 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 393 {                                                                \
 394         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 395         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 396         u64 latest = ((new_msb << 32) | new_lsb);                \
 397         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 398         last = latest;                                           \
 399 }
 400
 401 #define IXGBE_SET_HWSTRIP(h, q) do {\
 402                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 403                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 404                 (h)->bitmap[idx] |= 1 << bit;\
 405         } while (0)
 406
 407 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 408                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 409                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 410                 (h)->bitmap[idx] &= ~(1 << bit);\
 411         } while (0)
 412
 413 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 414                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 415                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 416                 (r) = (h)->bitmap[idx] >> bit & 1;\
 417         } while (0)
 418
 419 int ixgbe_logtype_init;
 420 int ixgbe_logtype_driver;
 421
 422 /*
 423  * The set of PCI devices this driver supports
 424  */
 425 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 474 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 476 #endif
 477         { .vendor_id = 0, /* sentinel */ },
 478 };
 479
 480 /*
 481  * The set of PCI devices this driver supports (for 82599 VF)
 482  */
 483 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 492         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 494         { .vendor_id = 0, /* sentinel */ },
 495 };
 496
 497 static const struct rte_eth_desc_lim rx_desc_lim = {
 498         .nb_max = IXGBE_MAX_RING_DESC,
 499         .nb_min = IXGBE_MIN_RING_DESC,
 500         .nb_align = IXGBE_RXD_ALIGN,
 501 };
 502
 503 static const struct rte_eth_desc_lim tx_desc_lim = {
 504         .nb_max = IXGBE_MAX_RING_DESC,
 505         .nb_min = IXGBE_MIN_RING_DESC,
 506         .nb_align = IXGBE_TXD_ALIGN,
 507         .nb_seg_max = IXGBE_TX_MAX_SEG,
 508         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 509 };
 510
 511 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 512         .dev_configure        = ixgbe_dev_configure,
 513         .dev_start            = ixgbe_dev_start,
 514         .dev_stop             = ixgbe_dev_stop,
 515         .dev_set_link_up    = ixgbe_dev_set_link_up,
 516         .dev_set_link_down  = ixgbe_dev_set_link_down,
 517         .dev_close            = ixgbe_dev_close,
 518         .dev_reset            = ixgbe_dev_reset,
 519         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 520         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 521         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 522         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 523         .link_update          = ixgbe_dev_link_update,
 524         .stats_get            = ixgbe_dev_stats_get,
 525         .xstats_get           = ixgbe_dev_xstats_get,
 526         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 527         .stats_reset          = ixgbe_dev_stats_reset,
 528         .xstats_reset         = ixgbe_dev_xstats_reset,
 529         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 530         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 531         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 532         .fw_version_get       = ixgbe_fw_version_get,
 533         .dev_infos_get        = ixgbe_dev_info_get,
 534         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 535         .mtu_set              = ixgbe_dev_mtu_set,
 536         .vlan_filter_set      = ixgbe_vlan_filter_set,
 537         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 538         .vlan_offload_set     = ixgbe_vlan_offload_set,
 539         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 540         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 541         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 542         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 543         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 544         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 545         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 546         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 547         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 548         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 549         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 550         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 551         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 552         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 553         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 554         .dev_led_on           = ixgbe_dev_led_on,
 555         .dev_led_off          = ixgbe_dev_led_off,
 556         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 557         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 558         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 559         .mac_addr_add         = ixgbe_add_rar,
 560         .mac_addr_remove      = ixgbe_remove_rar,
 561         .mac_addr_set         = ixgbe_set_default_mac_addr,
 562         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 563         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 564         .mirror_rule_set      = ixgbe_mirror_rule_set,
 565         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 566         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 567         .reta_update          = ixgbe_dev_rss_reta_update,
 568         .reta_query           = ixgbe_dev_rss_reta_query,
 569         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 570         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 571         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 572         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 573         .rxq_info_get         = ixgbe_rxq_info_get,
 574         .txq_info_get         = ixgbe_txq_info_get,
 575         .timesync_enable      = ixgbe_timesync_enable,
 576         .timesync_disable     = ixgbe_timesync_disable,
 577         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 578         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 579         .get_reg              = ixgbe_get_regs,
 580         .get_eeprom_length    = ixgbe_get_eeprom_length,
 581         .get_eeprom           = ixgbe_get_eeprom,
 582         .set_eeprom           = ixgbe_set_eeprom,
 583         .get_module_info      = ixgbe_get_module_info,
 584         .get_module_eeprom    = ixgbe_get_module_eeprom,
 585         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 586         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 587         .timesync_read_time   = ixgbe_timesync_read_time,
 588         .timesync_write_time  = ixgbe_timesync_write_time,
 589         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 590         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 591         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 592         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 593         .tm_ops_get           = ixgbe_tm_ops_get,
 594 };
 595
 596 /*
 597  * dev_ops for virtual function, bare necessities for basic vf
 598  * operation have been implemented
 599  */
 600 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 601         .dev_configure        = ixgbevf_dev_configure,
 602         .dev_start            = ixgbevf_dev_start,
 603         .dev_stop             = ixgbevf_dev_stop,
 604         .link_update          = ixgbevf_dev_link_update,
 605         .stats_get            = ixgbevf_dev_stats_get,
 606         .xstats_get           = ixgbevf_dev_xstats_get,
 607         .stats_reset          = ixgbevf_dev_stats_reset,
 608         .xstats_reset         = ixgbevf_dev_stats_reset,
 609         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 610         .dev_close            = ixgbevf_dev_close,
 611         .dev_reset            = ixgbevf_dev_reset,
 612         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 613         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 614         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 615         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 616         .dev_infos_get        = ixgbevf_dev_info_get,
 617         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 618         .mtu_set              = ixgbevf_dev_set_mtu,
 619         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 620         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 621         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 622         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 623         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 624         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 625         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 626         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 627         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 628         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 629         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 630         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 631         .mac_addr_add         = ixgbevf_add_mac_addr,
 632         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 633         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 634         .rxq_info_get         = ixgbe_rxq_info_get,
 635         .txq_info_get         = ixgbe_txq_info_get,
 636         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 637         .get_reg              = ixgbevf_get_regs,
 638         .reta_update          = ixgbe_dev_rss_reta_update,
 639         .reta_query           = ixgbe_dev_rss_reta_query,
 640         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 641         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 642 };
 643
 644 /* store statistics names and its offset in stats structure */
 645 struct rte_ixgbe_xstats_name_off {
 646         char name[RTE_ETH_XSTATS_NAME_SIZE];
 647         unsigned offset;
 648 };
 649
 650 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 651         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 652         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 653         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 654         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 655         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 656         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 657         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 658         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 659         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 660         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 661         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 662         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 663         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 664         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 665         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 666                 prc1023)},
 667         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 668                 prc1522)},
 669         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 670         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 671         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 672         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 673         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 674         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 675         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 676         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 677         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 678         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 679         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 680         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 681         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 682         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 683         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 684         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 685         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 686                 ptc1023)},
 687         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 688                 ptc1522)},
 689         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 690         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 691         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 692         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 693
 694         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 695                 fdirustat_add)},
 696         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 697                 fdirustat_remove)},
 698         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 699                 fdirfstat_fadd)},
 700         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 701                 fdirfstat_fremove)},
 702         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 703                 fdirmatch)},
 704         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 705                 fdirmiss)},
 706
 707         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 708         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 709         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 710                 fclast)},
 711         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 712         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 713         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 714         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 715         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 716                 fcoe_noddp)},
 717         {"rx_fcoe_no_direct_data_placement_ext_buff",
 718                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 719
 720         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 721                 lxontxc)},
 722         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 723                 lxonrxc)},
 724         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 725                 lxofftxc)},
 726         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 727                 lxoffrxc)},
 728         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 729 };
 730
 731 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 732                            sizeof(rte_ixgbe_stats_strings[0]))
 733
 734 /* MACsec statistics */
 735 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 736         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 737                 out_pkts_untagged)},
 738         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 739                 out_pkts_encrypted)},
 740         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 741                 out_pkts_protected)},
 742         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 743                 out_octets_encrypted)},
 744         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 745                 out_octets_protected)},
 746         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 747                 in_pkts_untagged)},
 748         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 749                 in_pkts_badtag)},
 750         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_nosci)},
 752         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_unknownsci)},
 754         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 755                 in_octets_decrypted)},
 756         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 757                 in_octets_validated)},
 758         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 759                 in_pkts_unchecked)},
 760         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 761                 in_pkts_delayed)},
 762         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 763                 in_pkts_late)},
 764         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 765                 in_pkts_ok)},
 766         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 767                 in_pkts_invalid)},
 768         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 769                 in_pkts_notvalid)},
 770         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 771                 in_pkts_unusedsa)},
 772         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 773                 in_pkts_notusingsa)},
 774 };
 775
 776 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 777                            sizeof(rte_ixgbe_macsec_strings[0]))
 778
 779 /* Per-queue statistics */
 780 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 781         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 782         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 783         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 784         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 785 };
 786
 787 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 788                            sizeof(rte_ixgbe_rxq_strings[0]))
 789 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 790
 791 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 792         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 793         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 794         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 795                 pxon2offc)},
 796 };
 797
 798 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 799                            sizeof(rte_ixgbe_txq_strings[0]))
 800 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 801
 802 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 803         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 804 };
 805
 806 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 807                 sizeof(rte_ixgbevf_stats_strings[0]))
 808
 809 /*
 810  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 811  */
 812 static inline int
 813 ixgbe_is_sfp(struct ixgbe_hw *hw)
 814 {
 815         switch (hw->phy.type) {
 816         case ixgbe_phy_sfp_avago:
 817         case ixgbe_phy_sfp_ftl:
 818         case ixgbe_phy_sfp_intel:
 819         case ixgbe_phy_sfp_unknown:
 820         case ixgbe_phy_sfp_passive_tyco:
 821         case ixgbe_phy_sfp_passive_unknown:
 822                 return 1;
 823         default:
 824                 return 0;
 825         }
 826 }
 827
 828 static inline int32_t
 829 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 830 {
 831         uint32_t ctrl_ext;
 832         int32_t status;
 833
 834         status = ixgbe_reset_hw(hw);
 835
 836         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 837         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 838         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 839         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 840         IXGBE_WRITE_FLUSH(hw);
 841
 842         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 843                 status = IXGBE_SUCCESS;
 844         return status;
 845 }
 846
 847 static inline void
 848 ixgbe_enable_intr(struct rte_eth_dev *dev)
 849 {
 850         struct ixgbe_interrupt *intr =
 851                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 852         struct ixgbe_hw *hw =
 853                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 854
 855         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 856         IXGBE_WRITE_FLUSH(hw);
 857 }
 858
 859 /*
 860  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 861  */
 862 static void
 863 ixgbe_disable_intr(struct ixgbe_hw *hw)
 864 {
 865         PMD_INIT_FUNC_TRACE();
 866
 867         if (hw->mac.type == ixgbe_mac_82598EB) {
 868                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 869         } else {
 870                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 871                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 872                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 873         }
 874         IXGBE_WRITE_FLUSH(hw);
 875 }
 876
 877 /*
 878  * This function resets queue statistics mapping registers.
 879  * From Niantic datasheet, Initialization of Statistics section:
 880  * "...if software requires the queue counters, the RQSMR and TQSM registers
 881  * must be re-programmed following a device reset.
 882  */
 883 static void
 884 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 885 {
 886         uint32_t i;
 887
 888         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 889                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 890                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 891         }
 892 }
 893
 894
 895 static int
 896 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 897                                   uint16_t queue_id,
 898                                   uint8_t stat_idx,
 899                                   uint8_t is_rx)
 900 {
 901 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 902 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 903 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 904
 905         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 906         struct ixgbe_stat_mapping_registers *stat_mappings =
 907                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 908         uint32_t qsmr_mask = 0;
 909         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 910         uint32_t q_map;
 911         uint8_t n, offset;
 912
 913         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 914                 (hw->mac.type != ixgbe_mac_X540) &&
 915                 (hw->mac.type != ixgbe_mac_X550) &&
 916                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 917                 (hw->mac.type != ixgbe_mac_X550EM_a))
 918                 return -ENOSYS;
 919
 920         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 921                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 922                      queue_id, stat_idx);
 923
 924         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 925         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 926                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 927                 return -EIO;
 928         }
 929         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 930
 931         /* Now clear any previous stat_idx set */
 932         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 933         if (!is_rx)
 934                 stat_mappings->tqsm[n] &= ~clearing_mask;
 935         else
 936                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 937
 938         q_map = (uint32_t)stat_idx;
 939         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 940         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 941         if (!is_rx)
 942                 stat_mappings->tqsm[n] |= qsmr_mask;
 943         else
 944                 stat_mappings->rqsmr[n] |= qsmr_mask;
 945
 946         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 947                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 948                      queue_id, stat_idx);
 949         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 950                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 951
 952         /* Now write the mapping in the appropriate register */
 953         if (is_rx) {
 954                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 955                              stat_mappings->rqsmr[n], n);
 956                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 957         } else {
 958                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 959                              stat_mappings->tqsm[n], n);
 960                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 961         }
 962         return 0;
 963 }
 964
 965 static void
 966 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 967 {
 968         struct ixgbe_stat_mapping_registers *stat_mappings =
 969                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 970         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 971         int i;
 972
 973         /* write whatever was in stat mapping table to the NIC */
 974         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 975                 /* rx */
 976                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 977
 978                 /* tx */
 979                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 980         }
 981 }
 982
 983 static void
 984 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 985 {
 986         uint8_t i;
 987         struct ixgbe_dcb_tc_config *tc;
 988         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 989
 990         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 991         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 992         for (i = 0; i < dcb_max_tc; i++) {
 993                 tc = &dcb_config->tc_config[i];
 994                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 995                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 996                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 997                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 998                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 999                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1000                 tc->pfc = ixgbe_dcb_pfc_disabled;
1001         }
1002
1003         /* Initialize default user to priority mapping, UPx->TC0 */
1004         tc = &dcb_config->tc_config[0];
1005         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1006         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1007         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1008                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1009                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1010         }
1011         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1012         dcb_config->pfc_mode_enable = false;
1013         dcb_config->vt_mode = true;
1014         dcb_config->round_robin_enable = false;
1015         /* support all DCB capabilities in 82599 */
1016         dcb_config->support.capabilities = 0xFF;
1017
1018         /*we only support 4 Tcs for X540, X550 */
1019         if (hw->mac.type == ixgbe_mac_X540 ||
1020                 hw->mac.type == ixgbe_mac_X550 ||
1021                 hw->mac.type == ixgbe_mac_X550EM_x ||
1022                 hw->mac.type == ixgbe_mac_X550EM_a) {
1023                 dcb_config->num_tcs.pg_tcs = 4;
1024                 dcb_config->num_tcs.pfc_tcs = 4;
1025         }
1026 }
1027
1028 /*
1029  * Ensure that all locks are released before first NVM or PHY access
1030  */
1031 static void
1032 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1033 {
1034         uint16_t mask;
1035
1036         /*
1037          * Phy lock should not fail in this early stage. If this is the case,
1038          * it is due to an improper exit of the application.
1039          * So force the release of the faulty lock. Release of common lock
1040          * is done automatically by swfw_sync function.
1041          */
1042         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1043         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1044                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1045         }
1046         ixgbe_release_swfw_semaphore(hw, mask);
1047
1048         /*
1049          * These ones are more tricky since they are common to all ports; but
1050          * swfw_sync retries last long enough (1s) to be almost sure that if
1051          * lock can not be taken it is due to an improper lock of the
1052          * semaphore.
1053          */
1054         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1055         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1056                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1057         }
1058         ixgbe_release_swfw_semaphore(hw, mask);
1059 }
1060
1061 /*
1062  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1063  * It returns 0 on success.
1064  */
1065 static int
1066 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1067 {
1068         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1069         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1070         struct ixgbe_hw *hw =
1071                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1072         struct ixgbe_vfta *shadow_vfta =
1073                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1074         struct ixgbe_hwstrip *hwstrip =
1075                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1076         struct ixgbe_dcb_config *dcb_config =
1077                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1078         struct ixgbe_filter_info *filter_info =
1079                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1080         struct ixgbe_bw_conf *bw_conf =
1081                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1082         uint32_t ctrl_ext;
1083         uint16_t csum;
1084         int diag, i;
1085
1086         PMD_INIT_FUNC_TRACE();
1087
1088         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1089         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1090         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1091         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1092
1093         /*
1094          * For secondary processes, we don't initialise any further as primary
1095          * has already done this work. Only check we don't need a different
1096          * RX and TX function.
1097          */
1098         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1099                 struct ixgbe_tx_queue *txq;
1100                 /* TX queue function in primary, set by last queue initialized
1101                  * Tx queue may not initialized by primary process
1102                  */
1103                 if (eth_dev->data->tx_queues) {
1104                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1105                         ixgbe_set_tx_function(eth_dev, txq);
1106                 } else {
1107                         /* Use default TX function if we get here */
1108                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1109                                      "Using default TX function.");
1110                 }
1111
1112                 ixgbe_set_rx_function(eth_dev);
1113
1114                 return 0;
1115         }
1116
1117         rte_eth_copy_pci_info(eth_dev, pci_dev);
1118
1119         /* Vendor and Device ID need to be set before init of shared code */
1120         hw->device_id = pci_dev->id.device_id;
1121         hw->vendor_id = pci_dev->id.vendor_id;
1122         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1123         hw->allow_unsupported_sfp = 1;
1124
1125         /* Initialize the shared code (base driver) */
1126 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1127         diag = ixgbe_bypass_init_shared_code(hw);
1128 #else
1129         diag = ixgbe_init_shared_code(hw);
1130 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1131
1132         if (diag != IXGBE_SUCCESS) {
1133                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1134                 return -EIO;
1135         }
1136
1137         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1138                 PMD_INIT_LOG(ERR, "\nERROR: "
1139                         "Firmware recovery mode detected. Limiting functionality.\n"
1140                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1141                         "User Guide for details on firmware recovery mode.");
1142                 return -EIO;
1143         }
1144
1145         /* pick up the PCI bus settings for reporting later */
1146         ixgbe_get_bus_info(hw);
1147
1148         /* Unlock any pending hardware semaphore */
1149         ixgbe_swfw_lock_reset(hw);
1150
1151 #ifdef RTE_LIBRTE_SECURITY
1152         /* Initialize security_ctx only for primary process*/
1153         if (ixgbe_ipsec_ctx_create(eth_dev))
1154                 return -ENOMEM;
1155 #endif
1156
1157         /* Initialize DCB configuration*/
1158         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1159         ixgbe_dcb_init(hw, dcb_config);
1160         /* Get Hardware Flow Control setting */
1161         hw->fc.requested_mode = ixgbe_fc_full;
1162         hw->fc.current_mode = ixgbe_fc_full;
1163         hw->fc.pause_time = IXGBE_FC_PAUSE;
1164         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1165                 hw->fc.low_water[i] = IXGBE_FC_LO;
1166                 hw->fc.high_water[i] = IXGBE_FC_HI;
1167         }
1168         hw->fc.send_xon = 1;
1169
1170         /* Make sure we have a good EEPROM before we read from it */
1171         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1172         if (diag != IXGBE_SUCCESS) {
1173                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1174                 return -EIO;
1175         }
1176
1177 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1178         diag = ixgbe_bypass_init_hw(hw);
1179 #else
1180         diag = ixgbe_init_hw(hw);
1181 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1182
1183         /*
1184          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1185          * is called too soon after the kernel driver unbinding/binding occurs.
1186          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1187          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1188          * also called. See ixgbe_identify_phy_82599(). The reason for the
1189          * failure is not known, and only occuts when virtualisation features
1190          * are disabled in the bios. A delay of 100ms  was found to be enough by
1191          * trial-and-error, and is doubled to be safe.
1192          */
1193         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1194                 rte_delay_ms(200);
1195                 diag = ixgbe_init_hw(hw);
1196         }
1197
1198         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1199                 diag = IXGBE_SUCCESS;
1200
1201         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1202                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1203                              "LOM.  Please be aware there may be issues associated "
1204                              "with your hardware.");
1205                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1206                              "please contact your Intel or hardware representative "
1207                              "who provided you with this hardware.");
1208         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1209                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1210         if (diag) {
1211                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1212                 return -EIO;
1213         }
1214
1215         /* Reset the hw statistics */
1216         ixgbe_dev_stats_reset(eth_dev);
1217
1218         /* disable interrupt */
1219         ixgbe_disable_intr(hw);
1220
1221         /* reset mappings for queue statistics hw counters*/
1222         ixgbe_reset_qstat_mappings(hw);
1223
1224         /* Allocate memory for storing MAC addresses */
1225         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1226                                                hw->mac.num_rar_entries, 0);
1227         if (eth_dev->data->mac_addrs == NULL) {
1228                 PMD_INIT_LOG(ERR,
1229                              "Failed to allocate %u bytes needed to store "
1230                              "MAC addresses",
1231                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1232                 return -ENOMEM;
1233         }
1234         /* Copy the permanent MAC address */
1235         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1236                         &eth_dev->data->mac_addrs[0]);
1237
1238         /* Allocate memory for storing hash filter MAC addresses */
1239         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1240                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1241         if (eth_dev->data->hash_mac_addrs == NULL) {
1242                 PMD_INIT_LOG(ERR,
1243                              "Failed to allocate %d bytes needed to store MAC addresses",
1244                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1245                 return -ENOMEM;
1246         }
1247
1248         /* initialize the vfta */
1249         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1250
1251         /* initialize the hw strip bitmap*/
1252         memset(hwstrip, 0, sizeof(*hwstrip));
1253
1254         /* initialize PF if max_vfs not zero */
1255         ixgbe_pf_host_init(eth_dev);
1256
1257         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1258         /* let hardware know driver is loaded */
1259         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1260         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1261         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1262         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1263         IXGBE_WRITE_FLUSH(hw);
1264
1265         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1266                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1267                              (int) hw->mac.type, (int) hw->phy.type,
1268                              (int) hw->phy.sfp_type);
1269         else
1270                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1271                              (int) hw->mac.type, (int) hw->phy.type);
1272
1273         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1274                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1275                      pci_dev->id.device_id);
1276
1277         rte_intr_callback_register(intr_handle,
1278                                    ixgbe_dev_interrupt_handler, eth_dev);
1279
1280         /* enable uio/vfio intr/eventfd mapping */
1281         rte_intr_enable(intr_handle);
1282
1283         /* enable support intr */
1284         ixgbe_enable_intr(eth_dev);
1285
1286         /* initialize filter info */
1287         memset(filter_info, 0,
1288                sizeof(struct ixgbe_filter_info));
1289
1290         /* initialize 5tuple filter list */
1291         TAILQ_INIT(&filter_info->fivetuple_list);
1292
1293         /* initialize flow director filter list & hash */
1294         ixgbe_fdir_filter_init(eth_dev);
1295
1296         /* initialize l2 tunnel filter list & hash */
1297         ixgbe_l2_tn_filter_init(eth_dev);
1298
1299         /* initialize flow filter lists */
1300         ixgbe_filterlist_init();
1301
1302         /* initialize bandwidth configuration info */
1303         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1304
1305         /* initialize Traffic Manager configuration */
1306         ixgbe_tm_conf_init(eth_dev);
1307
1308         return 0;
1309 }
1310
1311 static int
1312 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1313 {
1314         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1315         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1316         struct ixgbe_hw *hw;
1317         int retries = 0;
1318         int ret;
1319
1320         PMD_INIT_FUNC_TRACE();
1321
1322         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1323                 return 0;
1324
1325         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1326
1327         if (hw->adapter_stopped == 0)
1328                 ixgbe_dev_close(eth_dev);
1329
1330         eth_dev->dev_ops = NULL;
1331         eth_dev->rx_pkt_burst = NULL;
1332         eth_dev->tx_pkt_burst = NULL;
1333
1334         /* Unlock any pending hardware semaphore */
1335         ixgbe_swfw_lock_reset(hw);
1336
1337         /* disable uio intr before callback unregister */
1338         rte_intr_disable(intr_handle);
1339
1340         do {
1341                 ret = rte_intr_callback_unregister(intr_handle,
1342                                 ixgbe_dev_interrupt_handler, eth_dev);
1343                 if (ret >= 0) {
1344                         break;
1345                 } else if (ret != -EAGAIN) {
1346                         PMD_INIT_LOG(ERR,
1347                                 "intr callback unregister failed: %d",
1348                                 ret);
1349                         return ret;
1350                 }
1351                 rte_delay_ms(100);
1352         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1353
1354         /* cancel the delay handler before remove dev */
1355         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, eth_dev);
1356
1357         /* cancel the link handler before remove dev */
1358         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, eth_dev);
1359
1360         /* uninitialize PF if max_vfs not zero */
1361         ixgbe_pf_host_uninit(eth_dev);
1362
1363         /* remove all the fdir filters & hash */
1364         ixgbe_fdir_filter_uninit(eth_dev);
1365
1366         /* remove all the L2 tunnel filters & hash */
1367         ixgbe_l2_tn_filter_uninit(eth_dev);
1368
1369         /* Remove all ntuple filters of the device */
1370         ixgbe_ntuple_filter_uninit(eth_dev);
1371
1372         /* clear all the filters list */
1373         ixgbe_filterlist_flush();
1374
1375         /* Remove all Traffic Manager configuration */
1376         ixgbe_tm_conf_uninit(eth_dev);
1377
1378 #ifdef RTE_LIBRTE_SECURITY
1379         rte_free(eth_dev->security_ctx);
1380 #endif
1381
1382         return 0;
1383 }
1384
1385 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1386 {
1387         struct ixgbe_filter_info *filter_info =
1388                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1389         struct ixgbe_5tuple_filter *p_5tuple;
1390
1391         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1392                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1393                              p_5tuple,
1394                              entries);
1395                 rte_free(p_5tuple);
1396         }
1397         memset(filter_info->fivetuple_mask, 0,
1398                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1399
1400         return 0;
1401 }
1402
1403 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1404 {
1405         struct ixgbe_hw_fdir_info *fdir_info =
1406                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1407         struct ixgbe_fdir_filter *fdir_filter;
1408
1409                 if (fdir_info->hash_map)
1410                 rte_free(fdir_info->hash_map);
1411         if (fdir_info->hash_handle)
1412                 rte_hash_free(fdir_info->hash_handle);
1413
1414         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1415                 TAILQ_REMOVE(&fdir_info->fdir_list,
1416                              fdir_filter,
1417                              entries);
1418                 rte_free(fdir_filter);
1419         }
1420
1421         return 0;
1422 }
1423
1424 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1425 {
1426         struct ixgbe_l2_tn_info *l2_tn_info =
1427                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1428         struct ixgbe_l2_tn_filter *l2_tn_filter;
1429
1430         if (l2_tn_info->hash_map)
1431                 rte_free(l2_tn_info->hash_map);
1432         if (l2_tn_info->hash_handle)
1433                 rte_hash_free(l2_tn_info->hash_handle);
1434
1435         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1436                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1437                              l2_tn_filter,
1438                              entries);
1439                 rte_free(l2_tn_filter);
1440         }
1441
1442         return 0;
1443 }
1444
1445 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1446 {
1447         struct ixgbe_hw_fdir_info *fdir_info =
1448                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1449         char fdir_hash_name[RTE_HASH_NAMESIZE];
1450         struct rte_hash_parameters fdir_hash_params = {
1451                 .name = fdir_hash_name,
1452                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1453                 .key_len = sizeof(union ixgbe_atr_input),
1454                 .hash_func = rte_hash_crc,
1455                 .hash_func_init_val = 0,
1456                 .socket_id = rte_socket_id(),
1457         };
1458
1459         TAILQ_INIT(&fdir_info->fdir_list);
1460         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1461                  "fdir_%s", eth_dev->device->name);
1462         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1463         if (!fdir_info->hash_handle) {
1464                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1465                 return -EINVAL;
1466         }
1467         fdir_info->hash_map = rte_zmalloc("ixgbe",
1468                                           sizeof(struct ixgbe_fdir_filter *) *
1469                                           IXGBE_MAX_FDIR_FILTER_NUM,
1470                                           0);
1471         if (!fdir_info->hash_map) {
1472                 PMD_INIT_LOG(ERR,
1473                              "Failed to allocate memory for fdir hash map!");
1474                 return -ENOMEM;
1475         }
1476         fdir_info->mask_added = FALSE;
1477
1478         return 0;
1479 }
1480
1481 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1482 {
1483         struct ixgbe_l2_tn_info *l2_tn_info =
1484                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1485         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1486         struct rte_hash_parameters l2_tn_hash_params = {
1487                 .name = l2_tn_hash_name,
1488                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1489                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1490                 .hash_func = rte_hash_crc,
1491                 .hash_func_init_val = 0,
1492                 .socket_id = rte_socket_id(),
1493         };
1494
1495         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1496         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1497                  "l2_tn_%s", eth_dev->device->name);
1498         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1499         if (!l2_tn_info->hash_handle) {
1500                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1501                 return -EINVAL;
1502         }
1503         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1504                                    sizeof(struct ixgbe_l2_tn_filter *) *
1505                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1506                                    0);
1507         if (!l2_tn_info->hash_map) {
1508                 PMD_INIT_LOG(ERR,
1509                         "Failed to allocate memory for L2 TN hash map!");
1510                 return -ENOMEM;
1511         }
1512         l2_tn_info->e_tag_en = FALSE;
1513         l2_tn_info->e_tag_fwd_en = FALSE;
1514         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1515
1516         return 0;
1517 }
1518 /*
1519  * Negotiate mailbox API version with the PF.
1520  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1521  * Then we try to negotiate starting with the most recent one.
1522  * If all negotiation attempts fail, then we will proceed with
1523  * the default one (ixgbe_mbox_api_10).
1524  */
1525 static void
1526 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1527 {
1528         int32_t i;
1529
1530         /* start with highest supported, proceed down */
1531         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1532                 ixgbe_mbox_api_13,
1533                 ixgbe_mbox_api_12,
1534                 ixgbe_mbox_api_11,
1535                 ixgbe_mbox_api_10,
1536         };
1537
1538         for (i = 0;
1539                         i != RTE_DIM(sup_ver) &&
1540                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1541                         i++)
1542                 ;
1543 }
1544
1545 static void
1546 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1547 {
1548         uint64_t random;
1549
1550         /* Set Organizationally Unique Identifier (OUI) prefix. */
1551         mac_addr->addr_bytes[0] = 0x00;
1552         mac_addr->addr_bytes[1] = 0x09;
1553         mac_addr->addr_bytes[2] = 0xC0;
1554         /* Force indication of locally assigned MAC address. */
1555         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1556         /* Generate the last 3 bytes of the MAC address with a random number. */
1557         random = rte_rand();
1558         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1559 }
1560
1561 static int
1562 devarg_handle_int(__rte_unused const char *key, const char *value,
1563                   void *extra_args)
1564 {
1565         uint16_t *n = extra_args;
1566
1567         if (value == NULL || extra_args == NULL)
1568                 return -EINVAL;
1569
1570         *n = (uint16_t)strtoul(value, NULL, 0);
1571         if (*n == USHRT_MAX && errno == ERANGE)
1572                 return -1;
1573
1574         return 0;
1575 }
1576
1577 static void
1578 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1579                       struct rte_devargs *devargs)
1580 {
1581         struct rte_kvargs *kvlist;
1582         uint16_t pflink_fullchk;
1583
1584         if (devargs == NULL)
1585                 return;
1586
1587         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1588         if (kvlist == NULL)
1589                 return;
1590
1591         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1592             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1593                                devarg_handle_int, &pflink_fullchk) == 0 &&
1594             pflink_fullchk == 1)
1595                 adapter->pflink_fullchk = 1;
1596
1597         rte_kvargs_free(kvlist);
1598 }
1599
1600 /*
1601  * Virtual Function device init
1602  */
1603 static int
1604 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1605 {
1606         int diag;
1607         uint32_t tc, tcs;
1608         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1609         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1610         struct ixgbe_hw *hw =
1611                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1612         struct ixgbe_vfta *shadow_vfta =
1613                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1614         struct ixgbe_hwstrip *hwstrip =
1615                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1616         struct rte_ether_addr *perm_addr =
1617                 (struct rte_ether_addr *)hw->mac.perm_addr;
1618
1619         PMD_INIT_FUNC_TRACE();
1620
1621         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1622         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1623         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1624
1625         /* for secondary processes, we don't initialise any further as primary
1626          * has already done this work. Only check we don't need a different
1627          * RX function
1628          */
1629         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1630                 struct ixgbe_tx_queue *txq;
1631                 /* TX queue function in primary, set by last queue initialized
1632                  * Tx queue may not initialized by primary process
1633                  */
1634                 if (eth_dev->data->tx_queues) {
1635                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1636                         ixgbe_set_tx_function(eth_dev, txq);
1637                 } else {
1638                         /* Use default TX function if we get here */
1639                         PMD_INIT_LOG(NOTICE,
1640                                      "No TX queues configured yet. Using default TX function.");
1641                 }
1642
1643                 ixgbe_set_rx_function(eth_dev);
1644
1645                 return 0;
1646         }
1647
1648         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1649                               pci_dev->device.devargs);
1650
1651         rte_eth_copy_pci_info(eth_dev, pci_dev);
1652
1653         hw->device_id = pci_dev->id.device_id;
1654         hw->vendor_id = pci_dev->id.vendor_id;
1655         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1656
1657         /* initialize the vfta */
1658         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1659
1660         /* initialize the hw strip bitmap*/
1661         memset(hwstrip, 0, sizeof(*hwstrip));
1662
1663         /* Initialize the shared code (base driver) */
1664         diag = ixgbe_init_shared_code(hw);
1665         if (diag != IXGBE_SUCCESS) {
1666                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1667                 return -EIO;
1668         }
1669
1670         /* init_mailbox_params */
1671         hw->mbx.ops.init_params(hw);
1672
1673         /* Reset the hw statistics */
1674         ixgbevf_dev_stats_reset(eth_dev);
1675
1676         /* Disable the interrupts for VF */
1677         ixgbevf_intr_disable(eth_dev);
1678
1679         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1680         diag = hw->mac.ops.reset_hw(hw);
1681
1682         /*
1683          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1684          * the underlying PF driver has not assigned a MAC address to the VF.
1685          * In this case, assign a random MAC address.
1686          */
1687         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1688                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1689                 /*
1690                  * This error code will be propagated to the app by
1691                  * rte_eth_dev_reset, so use a public error code rather than
1692                  * the internal-only IXGBE_ERR_RESET_FAILED
1693                  */
1694                 return -EAGAIN;
1695         }
1696
1697         /* negotiate mailbox API version to use with the PF. */
1698         ixgbevf_negotiate_api(hw);
1699
1700         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1701         ixgbevf_get_queues(hw, &tcs, &tc);
1702
1703         /* Allocate memory for storing MAC addresses */
1704         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1705                                                hw->mac.num_rar_entries, 0);
1706         if (eth_dev->data->mac_addrs == NULL) {
1707                 PMD_INIT_LOG(ERR,
1708                              "Failed to allocate %u bytes needed to store "
1709                              "MAC addresses",
1710                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1711                 return -ENOMEM;
1712         }
1713
1714         /* Generate a random MAC address, if none was assigned by PF. */
1715         if (rte_is_zero_ether_addr(perm_addr)) {
1716                 generate_random_mac_addr(perm_addr);
1717                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1718                 if (diag) {
1719                         rte_free(eth_dev->data->mac_addrs);
1720                         eth_dev->data->mac_addrs = NULL;
1721                         return diag;
1722                 }
1723                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1724                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1725                              "%02x:%02x:%02x:%02x:%02x:%02x",
1726                              perm_addr->addr_bytes[0],
1727                              perm_addr->addr_bytes[1],
1728                              perm_addr->addr_bytes[2],
1729                              perm_addr->addr_bytes[3],
1730                              perm_addr->addr_bytes[4],
1731                              perm_addr->addr_bytes[5]);
1732         }
1733
1734         /* Copy the permanent MAC address */
1735         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1736
1737         /* reset the hardware with the new settings */
1738         diag = hw->mac.ops.start_hw(hw);
1739         switch (diag) {
1740         case  0:
1741                 break;
1742
1743         default:
1744                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1745                 return -EIO;
1746         }
1747
1748         rte_intr_callback_register(intr_handle,
1749                                    ixgbevf_dev_interrupt_handler, eth_dev);
1750         rte_intr_enable(intr_handle);
1751         ixgbevf_intr_enable(eth_dev);
1752
1753         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1754                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1755                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1756
1757         return 0;
1758 }
1759
1760 /* Virtual Function device uninit */
1761
1762 static int
1763 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1764 {
1765         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1766         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1767         struct ixgbe_hw *hw;
1768
1769         PMD_INIT_FUNC_TRACE();
1770
1771         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1772                 return 0;
1773
1774         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1775
1776         if (hw->adapter_stopped == 0)
1777                 ixgbevf_dev_close(eth_dev);
1778
1779         eth_dev->dev_ops = NULL;
1780         eth_dev->rx_pkt_burst = NULL;
1781         eth_dev->tx_pkt_burst = NULL;
1782
1783         /* Disable the interrupts for VF */
1784         ixgbevf_intr_disable(eth_dev);
1785
1786         rte_intr_disable(intr_handle);
1787         rte_intr_callback_unregister(intr_handle,
1788                                      ixgbevf_dev_interrupt_handler, eth_dev);
1789
1790         return 0;
1791 }
1792
1793 static int
1794 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1795                 struct rte_pci_device *pci_dev)
1796 {
1797         char name[RTE_ETH_NAME_MAX_LEN];
1798         struct rte_eth_dev *pf_ethdev;
1799         struct rte_eth_devargs eth_da;
1800         int i, retval;
1801
1802         if (pci_dev->device.devargs) {
1803                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1804                                 &eth_da);
1805                 if (retval)
1806                         return retval;
1807         } else
1808                 memset(&eth_da, 0, sizeof(eth_da));
1809
1810         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1811                 sizeof(struct ixgbe_adapter),
1812                 eth_dev_pci_specific_init, pci_dev,
1813                 eth_ixgbe_dev_init, NULL);
1814
1815         if (retval || eth_da.nb_representor_ports < 1)
1816                 return retval;
1817
1818         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1819         if (pf_ethdev == NULL)
1820                 return -ENODEV;
1821
1822         /* probe VF representor ports */
1823         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1824                 struct ixgbe_vf_info *vfinfo;
1825                 struct ixgbe_vf_representor representor;
1826
1827                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1828                         pf_ethdev->data->dev_private);
1829                 if (vfinfo == NULL) {
1830                         PMD_DRV_LOG(ERR,
1831                                 "no virtual functions supported by PF");
1832                         break;
1833                 }
1834
1835                 representor.vf_id = eth_da.representor_ports[i];
1836                 representor.switch_domain_id = vfinfo->switch_domain_id;
1837                 representor.pf_ethdev = pf_ethdev;
1838
1839                 /* representor port net_bdf_port */
1840                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1841                         pci_dev->device.name,
1842                         eth_da.representor_ports[i]);
1843
1844                 retval = rte_eth_dev_create(&pci_dev->device, name,
1845                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1846                         ixgbe_vf_representor_init, &representor);
1847
1848                 if (retval)
1849                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1850                                 "representor %s.", name);
1851         }
1852
1853         return 0;
1854 }
1855
1856 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1857 {
1858         struct rte_eth_dev *ethdev;
1859
1860         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1861         if (!ethdev)
1862                 return -ENODEV;
1863
1864         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1865                 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1866         else
1867                 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1868 }
1869
1870 static struct rte_pci_driver rte_ixgbe_pmd = {
1871         .id_table = pci_id_ixgbe_map,
1872         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1873         .probe = eth_ixgbe_pci_probe,
1874         .remove = eth_ixgbe_pci_remove,
1875 };
1876
1877 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1878         struct rte_pci_device *pci_dev)
1879 {
1880         return rte_eth_dev_pci_generic_probe(pci_dev,
1881                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1882 }
1883
1884 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1885 {
1886         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1887 }
1888
1889 /*
1890  * virtual function driver struct
1891  */
1892 static struct rte_pci_driver rte_ixgbevf_pmd = {
1893         .id_table = pci_id_ixgbevf_map,
1894         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1895         .probe = eth_ixgbevf_pci_probe,
1896         .remove = eth_ixgbevf_pci_remove,
1897 };
1898
1899 static int
1900 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1901 {
1902         struct ixgbe_hw *hw =
1903                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1904         struct ixgbe_vfta *shadow_vfta =
1905                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1906         uint32_t vfta;
1907         uint32_t vid_idx;
1908         uint32_t vid_bit;
1909
1910         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1911         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1912         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1913         if (on)
1914                 vfta |= vid_bit;
1915         else
1916                 vfta &= ~vid_bit;
1917         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1918
1919         /* update local VFTA copy */
1920         shadow_vfta->vfta[vid_idx] = vfta;
1921
1922         return 0;
1923 }
1924
1925 static void
1926 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1927 {
1928         if (on)
1929                 ixgbe_vlan_hw_strip_enable(dev, queue);
1930         else
1931                 ixgbe_vlan_hw_strip_disable(dev, queue);
1932 }
1933
1934 static int
1935 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1936                     enum rte_vlan_type vlan_type,
1937                     uint16_t tpid)
1938 {
1939         struct ixgbe_hw *hw =
1940                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1941         int ret = 0;
1942         uint32_t reg;
1943         uint32_t qinq;
1944
1945         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1946         qinq &= IXGBE_DMATXCTL_GDV;
1947
1948         switch (vlan_type) {
1949         case ETH_VLAN_TYPE_INNER:
1950                 if (qinq) {
1951                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1952                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1953                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1954                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1955                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1956                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1957                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1958                 } else {
1959                         ret = -ENOTSUP;
1960                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1961                                     " by single VLAN");
1962                 }
1963                 break;
1964         case ETH_VLAN_TYPE_OUTER:
1965                 if (qinq) {
1966                         /* Only the high 16-bits is valid */
1967                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1968                                         IXGBE_EXVET_VET_EXT_SHIFT);
1969                 } else {
1970                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1971                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1972                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1973                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1974                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1975                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1976                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1977                 }
1978
1979                 break;
1980         default:
1981                 ret = -EINVAL;
1982                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1983                 break;
1984         }
1985
1986         return ret;
1987 }
1988
1989 void
1990 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1991 {
1992         struct ixgbe_hw *hw =
1993                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1994         uint32_t vlnctrl;
1995
1996         PMD_INIT_FUNC_TRACE();
1997
1998         /* Filter Table Disable */
1999         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2000         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2001
2002         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2003 }
2004
2005 void
2006 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2007 {
2008         struct ixgbe_hw *hw =
2009                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2010         struct ixgbe_vfta *shadow_vfta =
2011                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2012         uint32_t vlnctrl;
2013         uint16_t i;
2014
2015         PMD_INIT_FUNC_TRACE();
2016
2017         /* Filter Table Enable */
2018         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2019         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2020         vlnctrl |= IXGBE_VLNCTRL_VFE;
2021
2022         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2023
2024         /* write whatever is in local vfta copy */
2025         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
2026                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
2027 }
2028
2029 static void
2030 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
2031 {
2032         struct ixgbe_hwstrip *hwstrip =
2033                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
2034         struct ixgbe_rx_queue *rxq;
2035
2036         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
2037                 return;
2038
2039         if (on)
2040                 IXGBE_SET_HWSTRIP(hwstrip, queue);
2041         else
2042                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
2043
2044         if (queue >= dev->data->nb_rx_queues)
2045                 return;
2046
2047         rxq = dev->data->rx_queues[queue];
2048
2049         if (on) {
2050                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2051                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2052         } else {
2053                 rxq->vlan_flags = PKT_RX_VLAN;
2054                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2055         }
2056 }
2057
2058 static void
2059 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2060 {
2061         struct ixgbe_hw *hw =
2062                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2063         uint32_t ctrl;
2064
2065         PMD_INIT_FUNC_TRACE();
2066
2067         if (hw->mac.type == ixgbe_mac_82598EB) {
2068                 /* No queue level support */
2069                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2070                 return;
2071         }
2072
2073         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2074         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2075         ctrl &= ~IXGBE_RXDCTL_VME;
2076         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2077
2078         /* record those setting for HW strip per queue */
2079         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2080 }
2081
2082 static void
2083 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2084 {
2085         struct ixgbe_hw *hw =
2086                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2087         uint32_t ctrl;
2088
2089         PMD_INIT_FUNC_TRACE();
2090
2091         if (hw->mac.type == ixgbe_mac_82598EB) {
2092                 /* No queue level supported */
2093                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2094                 return;
2095         }
2096
2097         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2098         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2099         ctrl |= IXGBE_RXDCTL_VME;
2100         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2101
2102         /* record those setting for HW strip per queue */
2103         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2104 }
2105
2106 static void
2107 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2108 {
2109         struct ixgbe_hw *hw =
2110                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2111         uint32_t ctrl;
2112
2113         PMD_INIT_FUNC_TRACE();
2114
2115         /* DMATXCTRL: Geric Double VLAN Disable */
2116         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2117         ctrl &= ~IXGBE_DMATXCTL_GDV;
2118         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2119
2120         /* CTRL_EXT: Global Double VLAN Disable */
2121         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2122         ctrl &= ~IXGBE_EXTENDED_VLAN;
2123         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2124
2125 }
2126
2127 static void
2128 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2129 {
2130         struct ixgbe_hw *hw =
2131                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2132         uint32_t ctrl;
2133
2134         PMD_INIT_FUNC_TRACE();
2135
2136         /* DMATXCTRL: Geric Double VLAN Enable */
2137         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2138         ctrl |= IXGBE_DMATXCTL_GDV;
2139         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2140
2141         /* CTRL_EXT: Global Double VLAN Enable */
2142         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2143         ctrl |= IXGBE_EXTENDED_VLAN;
2144         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2145
2146         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2147         if (hw->mac.type == ixgbe_mac_X550 ||
2148             hw->mac.type == ixgbe_mac_X550EM_x ||
2149             hw->mac.type == ixgbe_mac_X550EM_a) {
2150                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2151                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2152                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2153         }
2154
2155         /*
2156          * VET EXT field in the EXVET register = 0x8100 by default
2157          * So no need to change. Same to VT field of DMATXCTL register
2158          */
2159 }
2160
2161 void
2162 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2163 {
2164         struct ixgbe_hw *hw =
2165                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2166         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2167         uint32_t ctrl;
2168         uint16_t i;
2169         struct ixgbe_rx_queue *rxq;
2170         bool on;
2171
2172         PMD_INIT_FUNC_TRACE();
2173
2174         if (hw->mac.type == ixgbe_mac_82598EB) {
2175                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2176                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2177                         ctrl |= IXGBE_VLNCTRL_VME;
2178                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2179                 } else {
2180                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2181                         ctrl &= ~IXGBE_VLNCTRL_VME;
2182                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2183                 }
2184         } else {
2185                 /*
2186                  * Other 10G NIC, the VLAN strip can be setup
2187                  * per queue in RXDCTL
2188                  */
2189                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2190                         rxq = dev->data->rx_queues[i];
2191                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2192                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2193                                 ctrl |= IXGBE_RXDCTL_VME;
2194                                 on = TRUE;
2195                         } else {
2196                                 ctrl &= ~IXGBE_RXDCTL_VME;
2197                                 on = FALSE;
2198                         }
2199                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2200
2201                         /* record those setting for HW strip per queue */
2202                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2203                 }
2204         }
2205 }
2206
2207 static void
2208 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2209 {
2210         uint16_t i;
2211         struct rte_eth_rxmode *rxmode;
2212         struct ixgbe_rx_queue *rxq;
2213
2214         if (mask & ETH_VLAN_STRIP_MASK) {
2215                 rxmode = &dev->data->dev_conf.rxmode;
2216                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2217                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2218                                 rxq = dev->data->rx_queues[i];
2219                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2220                         }
2221                 else
2222                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2223                                 rxq = dev->data->rx_queues[i];
2224                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2225                         }
2226         }
2227 }
2228
2229 static int
2230 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2231 {
2232         struct rte_eth_rxmode *rxmode;
2233         rxmode = &dev->data->dev_conf.rxmode;
2234
2235         if (mask & ETH_VLAN_STRIP_MASK) {
2236                 ixgbe_vlan_hw_strip_config(dev);
2237         }
2238
2239         if (mask & ETH_VLAN_FILTER_MASK) {
2240                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2241                         ixgbe_vlan_hw_filter_enable(dev);
2242                 else
2243                         ixgbe_vlan_hw_filter_disable(dev);
2244         }
2245
2246         if (mask & ETH_VLAN_EXTEND_MASK) {
2247                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2248                         ixgbe_vlan_hw_extend_enable(dev);
2249                 else
2250                         ixgbe_vlan_hw_extend_disable(dev);
2251         }
2252
2253         return 0;
2254 }
2255
2256 static int
2257 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2258 {
2259         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2260
2261         ixgbe_vlan_offload_config(dev, mask);
2262
2263         return 0;
2264 }
2265
2266 static void
2267 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2268 {
2269         struct ixgbe_hw *hw =
2270                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2271         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2272         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2273
2274         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2275         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2276 }
2277
2278 static int
2279 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2280 {
2281         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2282
2283         switch (nb_rx_q) {
2284         case 1:
2285         case 2:
2286                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2287                 break;
2288         case 4:
2289                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2290                 break;
2291         default:
2292                 return -EINVAL;
2293         }
2294
2295         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2296                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2297         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2298                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2299         return 0;
2300 }
2301
2302 static int
2303 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2304 {
2305         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2306         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2307         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2308         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2309
2310         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2311                 /* check multi-queue mode */
2312                 switch (dev_conf->rxmode.mq_mode) {
2313                 case ETH_MQ_RX_VMDQ_DCB:
2314                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2315                         break;
2316                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2317                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2318                         PMD_INIT_LOG(ERR, "SRIOV active,"
2319                                         " unsupported mq_mode rx %d.",
2320                                         dev_conf->rxmode.mq_mode);
2321                         return -EINVAL;
2322                 case ETH_MQ_RX_RSS:
2323                 case ETH_MQ_RX_VMDQ_RSS:
2324                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2325                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2326                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2327                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2328                                                 " invalid queue number"
2329                                                 " for VMDQ RSS, allowed"
2330                                                 " value are 1, 2 or 4.");
2331                                         return -EINVAL;
2332                                 }
2333                         break;
2334                 case ETH_MQ_RX_VMDQ_ONLY:
2335                 case ETH_MQ_RX_NONE:
2336                         /* if nothing mq mode configure, use default scheme */
2337                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2338                         break;
2339                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2340                         /* SRIOV only works in VMDq enable mode */
2341                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2342                                         " wrong mq_mode rx %d.",
2343                                         dev_conf->rxmode.mq_mode);
2344                         return -EINVAL;
2345                 }
2346
2347                 switch (dev_conf->txmode.mq_mode) {
2348                 case ETH_MQ_TX_VMDQ_DCB:
2349                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2350                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2351                         break;
2352                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2353                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2354                         break;
2355                 }
2356
2357                 /* check valid queue number */
2358                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2359                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2360                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2361                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2362                                         " must be less than or equal to %d.",
2363                                         nb_rx_q, nb_tx_q,
2364                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2365                         return -EINVAL;
2366                 }
2367         } else {
2368                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2369                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2370                                           " not supported.");
2371                         return -EINVAL;
2372                 }
2373                 /* check configuration for vmdb+dcb mode */
2374                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2375                         const struct rte_eth_vmdq_dcb_conf *conf;
2376
2377                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2378                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2379                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2380                                 return -EINVAL;
2381                         }
2382                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2383                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2384                                conf->nb_queue_pools == ETH_32_POOLS)) {
2385                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2386                                                 " nb_queue_pools must be %d or %d.",
2387                                                 ETH_16_POOLS, ETH_32_POOLS);
2388                                 return -EINVAL;
2389                         }
2390                 }
2391                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2392                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2393
2394                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2395                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2396                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2397                                 return -EINVAL;
2398                         }
2399                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2400                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2401                                conf->nb_queue_pools == ETH_32_POOLS)) {
2402                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2403                                                 " nb_queue_pools != %d and"
2404                                                 " nb_queue_pools != %d.",
2405                                                 ETH_16_POOLS, ETH_32_POOLS);
2406                                 return -EINVAL;
2407                         }
2408                 }
2409
2410                 /* For DCB mode check our configuration before we go further */
2411                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2412                         const struct rte_eth_dcb_rx_conf *conf;
2413
2414                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2415                         if (!(conf->nb_tcs == ETH_4_TCS ||
2416                                conf->nb_tcs == ETH_8_TCS)) {
2417                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2418                                                 " and nb_tcs != %d.",
2419                                                 ETH_4_TCS, ETH_8_TCS);
2420                                 return -EINVAL;
2421                         }
2422                 }
2423
2424                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2425                         const struct rte_eth_dcb_tx_conf *conf;
2426
2427                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2428                         if (!(conf->nb_tcs == ETH_4_TCS ||
2429                                conf->nb_tcs == ETH_8_TCS)) {
2430                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2431                                                 " and nb_tcs != %d.",
2432                                                 ETH_4_TCS, ETH_8_TCS);
2433                                 return -EINVAL;
2434                         }
2435                 }
2436
2437                 /*
2438                  * When DCB/VT is off, maximum number of queues changes,
2439                  * except for 82598EB, which remains constant.
2440                  */
2441                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2442                                 hw->mac.type != ixgbe_mac_82598EB) {
2443                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2444                                 PMD_INIT_LOG(ERR,
2445                                              "Neither VT nor DCB are enabled, "
2446                                              "nb_tx_q > %d.",
2447                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2448                                 return -EINVAL;
2449                         }
2450                 }
2451         }
2452         return 0;
2453 }
2454
2455 static int
2456 ixgbe_dev_configure(struct rte_eth_dev *dev)
2457 {
2458         struct ixgbe_interrupt *intr =
2459                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2460         struct ixgbe_adapter *adapter = dev->data->dev_private;
2461         int ret;
2462
2463         PMD_INIT_FUNC_TRACE();
2464         /* multipe queue mode checking */
2465         ret  = ixgbe_check_mq_mode(dev);
2466         if (ret != 0) {
2467                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2468                             ret);
2469                 return ret;
2470         }
2471
2472         /* set flag to update link status after init */
2473         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2474
2475         /*
2476          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2477          * allocation or vector Rx preconditions we will reset it.
2478          */
2479         adapter->rx_bulk_alloc_allowed = true;
2480         adapter->rx_vec_allowed = true;
2481
2482         return 0;
2483 }
2484
2485 static void
2486 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2487 {
2488         struct ixgbe_hw *hw =
2489                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2490         struct ixgbe_interrupt *intr =
2491                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2492         uint32_t gpie;
2493
2494         /* only set up it on X550EM_X */
2495         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2496                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2497                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2498                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2499                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2500                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2501         }
2502 }
2503
2504 int
2505 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2506                         uint16_t tx_rate, uint64_t q_msk)
2507 {
2508         struct ixgbe_hw *hw;
2509         struct ixgbe_vf_info *vfinfo;
2510         struct rte_eth_link link;
2511         uint8_t  nb_q_per_pool;
2512         uint32_t queue_stride;
2513         uint32_t queue_idx, idx = 0, vf_idx;
2514         uint32_t queue_end;
2515         uint16_t total_rate = 0;
2516         struct rte_pci_device *pci_dev;
2517         int ret;
2518
2519         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2520         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2521         if (ret < 0)
2522                 return ret;
2523
2524         if (vf >= pci_dev->max_vfs)
2525                 return -EINVAL;
2526
2527         if (tx_rate > link.link_speed)
2528                 return -EINVAL;
2529
2530         if (q_msk == 0)
2531                 return 0;
2532
2533         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2534         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2535         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2536         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2537         queue_idx = vf * queue_stride;
2538         queue_end = queue_idx + nb_q_per_pool - 1;
2539         if (queue_end >= hw->mac.max_tx_queues)
2540                 return -EINVAL;
2541
2542         if (vfinfo) {
2543                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2544                         if (vf_idx == vf)
2545                                 continue;
2546                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2547                                 idx++)
2548                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2549                 }
2550         } else {
2551                 return -EINVAL;
2552         }
2553
2554         /* Store tx_rate for this vf. */
2555         for (idx = 0; idx < nb_q_per_pool; idx++) {
2556                 if (((uint64_t)0x1 << idx) & q_msk) {
2557                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2558                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2559                         total_rate += tx_rate;
2560                 }
2561         }
2562
2563         if (total_rate > dev->data->dev_link.link_speed) {
2564                 /* Reset stored TX rate of the VF if it causes exceed
2565                  * link speed.
2566                  */
2567                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2568                 return -EINVAL;
2569         }
2570
2571         /* Set RTTBCNRC of each queue/pool for vf X  */
2572         for (; queue_idx <= queue_end; queue_idx++) {
2573                 if (0x1 & q_msk)
2574                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2575                 q_msk = q_msk >> 1;
2576         }
2577
2578         return 0;
2579 }
2580
2581 /*
2582  * Configure device link speed and setup link.
2583  * It returns 0 on success.
2584  */
2585 static int
2586 ixgbe_dev_start(struct rte_eth_dev *dev)
2587 {
2588         struct ixgbe_hw *hw =
2589                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2590         struct ixgbe_vf_info *vfinfo =
2591                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2592         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2593         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2594         uint32_t intr_vector = 0;
2595         int err, link_up = 0, negotiate = 0;
2596         uint32_t speed = 0;
2597         uint32_t allowed_speeds = 0;
2598         int mask = 0;
2599         int status;
2600         uint16_t vf, idx;
2601         uint32_t *link_speeds;
2602         struct ixgbe_tm_conf *tm_conf =
2603                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2604
2605         PMD_INIT_FUNC_TRACE();
2606
2607         /* IXGBE devices don't support:
2608         *    - half duplex (checked afterwards for valid speeds)
2609         *    - fixed speed: TODO implement
2610         */
2611         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2612                 PMD_INIT_LOG(ERR,
2613                 "Invalid link_speeds for port %u, fix speed not supported",
2614                                 dev->data->port_id);
2615                 return -EINVAL;
2616         }
2617
2618         /* Stop the link setup handler before resetting the HW. */
2619         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2620
2621         /* disable uio/vfio intr/eventfd mapping */
2622         rte_intr_disable(intr_handle);
2623
2624         /* stop adapter */
2625         hw->adapter_stopped = 0;
2626         ixgbe_stop_adapter(hw);
2627
2628         /* reinitialize adapter
2629          * this calls reset and start
2630          */
2631         status = ixgbe_pf_reset_hw(hw);
2632         if (status != 0)
2633                 return -1;
2634         hw->mac.ops.start_hw(hw);
2635         hw->mac.get_link_status = true;
2636
2637         /* configure PF module if SRIOV enabled */
2638         ixgbe_pf_host_configure(dev);
2639
2640         ixgbe_dev_phy_intr_setup(dev);
2641
2642         /* check and configure queue intr-vector mapping */
2643         if ((rte_intr_cap_multiple(intr_handle) ||
2644              !RTE_ETH_DEV_SRIOV(dev).active) &&
2645             dev->data->dev_conf.intr_conf.rxq != 0) {
2646                 intr_vector = dev->data->nb_rx_queues;
2647                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2648                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2649                                         IXGBE_MAX_INTR_QUEUE_NUM);
2650                         return -ENOTSUP;
2651                 }
2652                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2653                         return -1;
2654         }
2655
2656         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2657                 intr_handle->intr_vec =
2658                         rte_zmalloc("intr_vec",
2659                                     dev->data->nb_rx_queues * sizeof(int), 0);
2660                 if (intr_handle->intr_vec == NULL) {
2661                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2662                                      " intr_vec", dev->data->nb_rx_queues);
2663                         return -ENOMEM;
2664                 }
2665         }
2666
2667         /* confiugre msix for sleep until rx interrupt */
2668         ixgbe_configure_msix(dev);
2669
2670         /* initialize transmission unit */
2671         ixgbe_dev_tx_init(dev);
2672
2673         /* This can fail when allocating mbufs for descriptor rings */
2674         err = ixgbe_dev_rx_init(dev);
2675         if (err) {
2676                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2677                 goto error;
2678         }
2679
2680         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2681                 ETH_VLAN_EXTEND_MASK;
2682         err = ixgbe_vlan_offload_config(dev, mask);
2683         if (err) {
2684                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2685                 goto error;
2686         }
2687
2688         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2689                 /* Enable vlan filtering for VMDq */
2690                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2691         }
2692
2693         /* Configure DCB hw */
2694         ixgbe_configure_dcb(dev);
2695
2696         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2697                 err = ixgbe_fdir_configure(dev);
2698                 if (err)
2699                         goto error;
2700         }
2701
2702         /* Restore vf rate limit */
2703         if (vfinfo != NULL) {
2704                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2705                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2706                                 if (vfinfo[vf].tx_rate[idx] != 0)
2707                                         ixgbe_set_vf_rate_limit(
2708                                                 dev, vf,
2709                                                 vfinfo[vf].tx_rate[idx],
2710                                                 1 << idx);
2711         }
2712
2713         ixgbe_restore_statistics_mapping(dev);
2714
2715         err = ixgbe_dev_rxtx_start(dev);
2716         if (err < 0) {
2717                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2718                 goto error;
2719         }
2720
2721         /* Skip link setup if loopback mode is enabled. */
2722         if (dev->data->dev_conf.lpbk_mode != 0) {
2723                 err = ixgbe_check_supported_loopback_mode(dev);
2724                 if (err < 0) {
2725                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2726                         goto error;
2727                 } else {
2728                         goto skip_link_setup;
2729                 }
2730         }
2731
2732         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2733                 err = hw->mac.ops.setup_sfp(hw);
2734                 if (err)
2735                         goto error;
2736         }
2737
2738         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2739                 /* Turn on the copper */
2740                 ixgbe_set_phy_power(hw, true);
2741         } else {
2742                 /* Turn on the laser */
2743                 ixgbe_enable_tx_laser(hw);
2744         }
2745
2746         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2747         if (err)
2748                 goto error;
2749         dev->data->dev_link.link_status = link_up;
2750
2751         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2752         if (err)
2753                 goto error;
2754
2755         switch (hw->mac.type) {
2756         case ixgbe_mac_X550:
2757         case ixgbe_mac_X550EM_x:
2758         case ixgbe_mac_X550EM_a:
2759                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2760                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2761                         ETH_LINK_SPEED_10G;
2762                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2763                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2764                         allowed_speeds = ETH_LINK_SPEED_10M |
2765                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2766                 break;
2767         default:
2768                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2769                         ETH_LINK_SPEED_10G;
2770         }
2771
2772         link_speeds = &dev->data->dev_conf.link_speeds;
2773         if (*link_speeds & ~allowed_speeds) {
2774                 PMD_INIT_LOG(ERR, "Invalid link setting");
2775                 goto error;
2776         }
2777
2778         speed = 0x0;
2779         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2780                 switch (hw->mac.type) {
2781                 case ixgbe_mac_82598EB:
2782                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2783                         break;
2784                 case ixgbe_mac_82599EB:
2785                 case ixgbe_mac_X540:
2786                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2787                         break;
2788                 case ixgbe_mac_X550:
2789                 case ixgbe_mac_X550EM_x:
2790                 case ixgbe_mac_X550EM_a:
2791                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2792                         break;
2793                 default:
2794                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2795                 }
2796         } else {
2797                 if (*link_speeds & ETH_LINK_SPEED_10G)
2798                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2799                 if (*link_speeds & ETH_LINK_SPEED_5G)
2800                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2801                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2802                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2803                 if (*link_speeds & ETH_LINK_SPEED_1G)
2804                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2805                 if (*link_speeds & ETH_LINK_SPEED_100M)
2806                         speed |= IXGBE_LINK_SPEED_100_FULL;
2807                 if (*link_speeds & ETH_LINK_SPEED_10M)
2808                         speed |= IXGBE_LINK_SPEED_10_FULL;
2809         }
2810
2811         err = ixgbe_setup_link(hw, speed, link_up);
2812         if (err)
2813                 goto error;
2814
2815 skip_link_setup:
2816
2817         if (rte_intr_allow_others(intr_handle)) {
2818                 /* check if lsc interrupt is enabled */
2819                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2820                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2821                 else
2822                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2823                 ixgbe_dev_macsec_interrupt_setup(dev);
2824         } else {
2825                 rte_intr_callback_unregister(intr_handle,
2826                                              ixgbe_dev_interrupt_handler, dev);
2827                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2828                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2829                                      " no intr multiplex");
2830         }
2831
2832         /* check if rxq interrupt is enabled */
2833         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2834             rte_intr_dp_is_en(intr_handle))
2835                 ixgbe_dev_rxq_interrupt_setup(dev);
2836
2837         /* enable uio/vfio intr/eventfd mapping */
2838         rte_intr_enable(intr_handle);
2839
2840         /* resume enabled intr since hw reset */
2841         ixgbe_enable_intr(dev);
2842         ixgbe_l2_tunnel_conf(dev);
2843         ixgbe_filter_restore(dev);
2844
2845         if (tm_conf->root && !tm_conf->committed)
2846                 PMD_DRV_LOG(WARNING,
2847                             "please call hierarchy_commit() "
2848                             "before starting the port");
2849
2850         /*
2851          * Update link status right before return, because it may
2852          * start link configuration process in a separate thread.
2853          */
2854         ixgbe_dev_link_update(dev, 0);
2855
2856         return 0;
2857
2858 error:
2859         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2860         ixgbe_dev_clear_queues(dev);
2861         return -EIO;
2862 }
2863
2864 /*
2865  * Stop device: disable rx and tx functions to allow for reconfiguring.
2866  */
2867 static void
2868 ixgbe_dev_stop(struct rte_eth_dev *dev)
2869 {
2870         struct rte_eth_link link;
2871         struct ixgbe_adapter *adapter = dev->data->dev_private;
2872         struct ixgbe_hw *hw =
2873                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2874         struct ixgbe_vf_info *vfinfo =
2875                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2876         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2877         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2878         int vf;
2879         struct ixgbe_tm_conf *tm_conf =
2880                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2881
2882         PMD_INIT_FUNC_TRACE();
2883
2884         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2885
2886         /* disable interrupts */
2887         ixgbe_disable_intr(hw);
2888
2889         /* reset the NIC */
2890         ixgbe_pf_reset_hw(hw);
2891         hw->adapter_stopped = 0;
2892
2893         /* stop adapter */
2894         ixgbe_stop_adapter(hw);
2895
2896         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2897                 vfinfo[vf].clear_to_send = false;
2898
2899         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2900                 /* Turn off the copper */
2901                 ixgbe_set_phy_power(hw, false);
2902         } else {
2903                 /* Turn off the laser */
2904                 ixgbe_disable_tx_laser(hw);
2905         }
2906
2907         ixgbe_dev_clear_queues(dev);
2908
2909         /* Clear stored conf */
2910         dev->data->scattered_rx = 0;
2911         dev->data->lro = 0;
2912
2913         /* Clear recorded link status */
2914         memset(&link, 0, sizeof(link));
2915         rte_eth_linkstatus_set(dev, &link);
2916
2917         if (!rte_intr_allow_others(intr_handle))
2918                 /* resume to the default handler */
2919                 rte_intr_callback_register(intr_handle,
2920                                            ixgbe_dev_interrupt_handler,
2921                                            (void *)dev);
2922
2923         /* Clean datapath event and queue/vec mapping */
2924         rte_intr_efd_disable(intr_handle);
2925         if (intr_handle->intr_vec != NULL) {
2926                 rte_free(intr_handle->intr_vec);
2927                 intr_handle->intr_vec = NULL;
2928         }
2929
2930         /* reset hierarchy commit */
2931         tm_conf->committed = false;
2932
2933         adapter->rss_reta_updated = 0;
2934 }
2935
2936 /*
2937  * Set device link up: enable tx.
2938  */
2939 static int
2940 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2941 {
2942         struct ixgbe_hw *hw =
2943                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2944         if (hw->mac.type == ixgbe_mac_82599EB) {
2945 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2946                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2947                         /* Not suported in bypass mode */
2948                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2949                                      "by device id 0x%x", hw->device_id);
2950                         return -ENOTSUP;
2951                 }
2952 #endif
2953         }
2954
2955         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2956                 /* Turn on the copper */
2957                 ixgbe_set_phy_power(hw, true);
2958         } else {
2959                 /* Turn on the laser */
2960                 ixgbe_enable_tx_laser(hw);
2961         }
2962
2963         return 0;
2964 }
2965
2966 /*
2967  * Set device link down: disable tx.
2968  */
2969 static int
2970 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2971 {
2972         struct ixgbe_hw *hw =
2973                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2974         if (hw->mac.type == ixgbe_mac_82599EB) {
2975 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2976                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2977                         /* Not suported in bypass mode */
2978                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2979                                      "by device id 0x%x", hw->device_id);
2980                         return -ENOTSUP;
2981                 }
2982 #endif
2983         }
2984
2985         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2986                 /* Turn off the copper */
2987                 ixgbe_set_phy_power(hw, false);
2988         } else {
2989                 /* Turn off the laser */
2990                 ixgbe_disable_tx_laser(hw);
2991         }
2992
2993         return 0;
2994 }
2995
2996 /*
2997  * Reset and stop device.
2998  */
2999 static void
3000 ixgbe_dev_close(struct rte_eth_dev *dev)
3001 {
3002         struct ixgbe_hw *hw =
3003                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3004
3005         PMD_INIT_FUNC_TRACE();
3006
3007         ixgbe_pf_reset_hw(hw);
3008
3009         ixgbe_dev_stop(dev);
3010         hw->adapter_stopped = 1;
3011
3012         ixgbe_dev_free_queues(dev);
3013
3014         ixgbe_disable_pcie_master(hw);
3015
3016         /* reprogram the RAR[0] in case user changed it. */
3017         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3018 }
3019
3020 /*
3021  * Reset PF device.
3022  */
3023 static int
3024 ixgbe_dev_reset(struct rte_eth_dev *dev)
3025 {
3026         int ret;
3027
3028         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3029          * its VF to make them align with it. The detailed notification
3030          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3031          * To avoid unexpected behavior in VF, currently reset of PF with
3032          * SR-IOV activation is not supported. It might be supported later.
3033          */
3034         if (dev->data->sriov.active)
3035                 return -ENOTSUP;
3036
3037         ret = eth_ixgbe_dev_uninit(dev);
3038         if (ret)
3039                 return ret;
3040
3041         ret = eth_ixgbe_dev_init(dev, NULL);
3042
3043         return ret;
3044 }
3045
3046 static void
3047 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3048                            struct ixgbe_hw_stats *hw_stats,
3049                            struct ixgbe_macsec_stats *macsec_stats,
3050                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3051                            uint64_t *total_qprc, uint64_t *total_qprdc)
3052 {
3053         uint32_t bprc, lxon, lxoff, total;
3054         uint32_t delta_gprc = 0;
3055         unsigned i;
3056         /* Workaround for RX byte count not including CRC bytes when CRC
3057          * strip is enabled. CRC bytes are removed from counters when crc_strip
3058          * is disabled.
3059          */
3060         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3061                         IXGBE_HLREG0_RXCRCSTRP);
3062
3063         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3064         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3065         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3066         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3067
3068         for (i = 0; i < 8; i++) {
3069                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3070
3071                 /* global total per queue */
3072                 hw_stats->mpc[i] += mp;
3073                 /* Running comprehensive total for stats display */
3074                 *total_missed_rx += hw_stats->mpc[i];
3075                 if (hw->mac.type == ixgbe_mac_82598EB) {
3076                         hw_stats->rnbc[i] +=
3077                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3078                         hw_stats->pxonrxc[i] +=
3079                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3080                         hw_stats->pxoffrxc[i] +=
3081                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3082                 } else {
3083                         hw_stats->pxonrxc[i] +=
3084                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3085                         hw_stats->pxoffrxc[i] +=
3086                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3087                         hw_stats->pxon2offc[i] +=
3088                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3089                 }
3090                 hw_stats->pxontxc[i] +=
3091                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3092                 hw_stats->pxofftxc[i] +=
3093                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3094         }
3095         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3096                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3097                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3098                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3099
3100                 delta_gprc += delta_qprc;
3101
3102                 hw_stats->qprc[i] += delta_qprc;
3103                 hw_stats->qptc[i] += delta_qptc;
3104
3105                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3106                 hw_stats->qbrc[i] +=
3107                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3108                 if (crc_strip == 0)
3109                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3110
3111                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3112                 hw_stats->qbtc[i] +=
3113                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3114
3115                 hw_stats->qprdc[i] += delta_qprdc;
3116                 *total_qprdc += hw_stats->qprdc[i];
3117
3118                 *total_qprc += hw_stats->qprc[i];
3119                 *total_qbrc += hw_stats->qbrc[i];
3120         }
3121         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3122         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3123         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3124
3125         /*
3126          * An errata states that gprc actually counts good + missed packets:
3127          * Workaround to set gprc to summated queue packet receives
3128          */
3129         hw_stats->gprc = *total_qprc;
3130
3131         if (hw->mac.type != ixgbe_mac_82598EB) {
3132                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3133                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3134                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3135                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3136                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3137                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3138                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3139                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3140         } else {
3141                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3142                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3143                 /* 82598 only has a counter in the high register */
3144                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3145                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3146                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3147         }
3148         uint64_t old_tpr = hw_stats->tpr;
3149
3150         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3151         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3152
3153         if (crc_strip == 0)
3154                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3155
3156         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3157         hw_stats->gptc += delta_gptc;
3158         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3159         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3160
3161         /*
3162          * Workaround: mprc hardware is incorrectly counting
3163          * broadcasts, so for now we subtract those.
3164          */
3165         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3166         hw_stats->bprc += bprc;
3167         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3168         if (hw->mac.type == ixgbe_mac_82598EB)
3169                 hw_stats->mprc -= bprc;
3170
3171         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3172         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3173         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3174         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3175         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3176         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3177
3178         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3179         hw_stats->lxontxc += lxon;
3180         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3181         hw_stats->lxofftxc += lxoff;
3182         total = lxon + lxoff;
3183
3184         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3185         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3186         hw_stats->gptc -= total;
3187         hw_stats->mptc -= total;
3188         hw_stats->ptc64 -= total;
3189         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3190
3191         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3192         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3193         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3194         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3195         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3196         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3197         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3198         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3199         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3200         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3201         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3202         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3203         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3204         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3205         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3206         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3207         /* Only read FCOE on 82599 */
3208         if (hw->mac.type != ixgbe_mac_82598EB) {
3209                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3210                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3211                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3212                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3213                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3214         }
3215
3216         /* Flow Director Stats registers */
3217         if (hw->mac.type != ixgbe_mac_82598EB) {
3218                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3219                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3220                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3221                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3222                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3223                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3224                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3225                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3226                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3227                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3228         }
3229         /* MACsec Stats registers */
3230         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3231         macsec_stats->out_pkts_encrypted +=
3232                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3233         macsec_stats->out_pkts_protected +=
3234                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3235         macsec_stats->out_octets_encrypted +=
3236                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3237         macsec_stats->out_octets_protected +=
3238                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3239         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3240         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3241         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3242         macsec_stats->in_pkts_unknownsci +=
3243                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3244         macsec_stats->in_octets_decrypted +=
3245                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3246         macsec_stats->in_octets_validated +=
3247                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3248         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3249         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3250         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3251         for (i = 0; i < 2; i++) {
3252                 macsec_stats->in_pkts_ok +=
3253                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3254                 macsec_stats->in_pkts_invalid +=
3255                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3256                 macsec_stats->in_pkts_notvalid +=
3257                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3258         }
3259         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3260         macsec_stats->in_pkts_notusingsa +=
3261                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3262 }
3263
3264 /*
3265  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3266  */
3267 static int
3268 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3269 {
3270         struct ixgbe_hw *hw =
3271                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3272         struct ixgbe_hw_stats *hw_stats =
3273                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3274         struct ixgbe_macsec_stats *macsec_stats =
3275                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3276                                 dev->data->dev_private);
3277         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3278         unsigned i;
3279
3280         total_missed_rx = 0;
3281         total_qbrc = 0;
3282         total_qprc = 0;
3283         total_qprdc = 0;
3284
3285         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3286                         &total_qbrc, &total_qprc, &total_qprdc);
3287
3288         if (stats == NULL)
3289                 return -EINVAL;
3290
3291         /* Fill out the rte_eth_stats statistics structure */
3292         stats->ipackets = total_qprc;
3293         stats->ibytes = total_qbrc;
3294         stats->opackets = hw_stats->gptc;
3295         stats->obytes = hw_stats->gotc;
3296
3297         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3298                 stats->q_ipackets[i] = hw_stats->qprc[i];
3299                 stats->q_opackets[i] = hw_stats->qptc[i];
3300                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3301                 stats->q_obytes[i] = hw_stats->qbtc[i];
3302                 stats->q_errors[i] = hw_stats->qprdc[i];
3303         }
3304
3305         /* Rx Errors */
3306         stats->imissed  = total_missed_rx;
3307         stats->ierrors  = hw_stats->crcerrs +
3308                           hw_stats->mspdc +
3309                           hw_stats->rlec +
3310                           hw_stats->ruc +
3311                           hw_stats->roc +
3312                           hw_stats->illerrc +
3313                           hw_stats->errbc +
3314                           hw_stats->rfc +
3315                           hw_stats->fccrc +
3316                           hw_stats->fclast;
3317
3318         /* Tx Errors */
3319         stats->oerrors  = 0;
3320         return 0;
3321 }
3322
3323 static int
3324 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3325 {
3326         struct ixgbe_hw_stats *stats =
3327                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3328
3329         /* HW registers are cleared on read */
3330         ixgbe_dev_stats_get(dev, NULL);
3331
3332         /* Reset software totals */
3333         memset(stats, 0, sizeof(*stats));
3334
3335         return 0;
3336 }
3337
3338 /* This function calculates the number of xstats based on the current config */
3339 static unsigned
3340 ixgbe_xstats_calc_num(void) {
3341         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3342                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3343                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3344 }
3345
3346 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3347         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3348 {
3349         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3350         unsigned stat, i, count;
3351
3352         if (xstats_names != NULL) {
3353                 count = 0;
3354
3355                 /* Note: limit >= cnt_stats checked upstream
3356                  * in rte_eth_xstats_names()
3357                  */
3358
3359                 /* Extended stats from ixgbe_hw_stats */
3360                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3361                         strlcpy(xstats_names[count].name,
3362                                 rte_ixgbe_stats_strings[i].name,
3363                                 sizeof(xstats_names[count].name));
3364                         count++;
3365                 }
3366
3367                 /* MACsec Stats */
3368                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3369                         strlcpy(xstats_names[count].name,
3370                                 rte_ixgbe_macsec_strings[i].name,
3371                                 sizeof(xstats_names[count].name));
3372                         count++;
3373                 }
3374
3375                 /* RX Priority Stats */
3376                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3377                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3378                                 snprintf(xstats_names[count].name,
3379                                         sizeof(xstats_names[count].name),
3380                                         "rx_priority%u_%s", i,
3381                                         rte_ixgbe_rxq_strings[stat].name);
3382                                 count++;
3383                         }
3384                 }
3385
3386                 /* TX Priority Stats */
3387                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3388                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3389                                 snprintf(xstats_names[count].name,
3390                                         sizeof(xstats_names[count].name),
3391                                         "tx_priority%u_%s", i,
3392                                         rte_ixgbe_txq_strings[stat].name);
3393                                 count++;
3394                         }
3395                 }
3396         }
3397         return cnt_stats;
3398 }
3399
3400 static int ixgbe_dev_xstats_get_names_by_id(
3401         struct rte_eth_dev *dev,
3402         struct rte_eth_xstat_name *xstats_names,
3403         const uint64_t *ids,
3404         unsigned int limit)
3405 {
3406         if (!ids) {
3407                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3408                 unsigned int stat, i, count;
3409
3410                 if (xstats_names != NULL) {
3411                         count = 0;
3412
3413                         /* Note: limit >= cnt_stats checked upstream
3414                          * in rte_eth_xstats_names()
3415                          */
3416
3417                         /* Extended stats from ixgbe_hw_stats */
3418                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3419                                 strlcpy(xstats_names[count].name,
3420                                         rte_ixgbe_stats_strings[i].name,
3421                                         sizeof(xstats_names[count].name));
3422                                 count++;
3423                         }
3424
3425                         /* MACsec Stats */
3426                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3427                                 strlcpy(xstats_names[count].name,
3428                                         rte_ixgbe_macsec_strings[i].name,
3429                                         sizeof(xstats_names[count].name));
3430                                 count++;
3431                         }
3432
3433                         /* RX Priority Stats */
3434                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3435                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3436                                         snprintf(xstats_names[count].name,
3437                                             sizeof(xstats_names[count].name),
3438                                             "rx_priority%u_%s", i,
3439                                             rte_ixgbe_rxq_strings[stat].name);
3440                                         count++;
3441                                 }
3442                         }
3443
3444                         /* TX Priority Stats */
3445                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3446                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3447                                         snprintf(xstats_names[count].name,
3448                                             sizeof(xstats_names[count].name),
3449                                             "tx_priority%u_%s", i,
3450                                             rte_ixgbe_txq_strings[stat].name);
3451                                         count++;
3452                                 }
3453                         }
3454                 }
3455                 return cnt_stats;
3456         }
3457
3458         uint16_t i;
3459         uint16_t size = ixgbe_xstats_calc_num();
3460         struct rte_eth_xstat_name xstats_names_copy[size];
3461
3462         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3463                         size);
3464
3465         for (i = 0; i < limit; i++) {
3466                 if (ids[i] >= size) {
3467                         PMD_INIT_LOG(ERR, "id value isn't valid");
3468                         return -1;
3469                 }
3470                 strcpy(xstats_names[i].name,
3471                                 xstats_names_copy[ids[i]].name);
3472         }
3473         return limit;
3474 }
3475
3476 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3477         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3478 {
3479         unsigned i;
3480
3481         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3482                 return -ENOMEM;
3483
3484         if (xstats_names != NULL)
3485                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3486                         strlcpy(xstats_names[i].name,
3487                                 rte_ixgbevf_stats_strings[i].name,
3488                                 sizeof(xstats_names[i].name));
3489         return IXGBEVF_NB_XSTATS;
3490 }
3491
3492 static int
3493 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3494                                          unsigned n)
3495 {
3496         struct ixgbe_hw *hw =
3497                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3498         struct ixgbe_hw_stats *hw_stats =
3499                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3500         struct ixgbe_macsec_stats *macsec_stats =
3501                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3502                                 dev->data->dev_private);
3503         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3504         unsigned i, stat, count = 0;
3505
3506         count = ixgbe_xstats_calc_num();
3507
3508         if (n < count)
3509                 return count;
3510
3511         total_missed_rx = 0;
3512         total_qbrc = 0;
3513         total_qprc = 0;
3514         total_qprdc = 0;
3515
3516         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3517                         &total_qbrc, &total_qprc, &total_qprdc);
3518
3519         /* If this is a reset xstats is NULL, and we have cleared the
3520          * registers by reading them.
3521          */
3522         if (!xstats)
3523                 return 0;
3524
3525         /* Extended stats from ixgbe_hw_stats */
3526         count = 0;
3527         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3528                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3529                                 rte_ixgbe_stats_strings[i].offset);
3530                 xstats[count].id = count;
3531                 count++;
3532         }
3533
3534         /* MACsec Stats */
3535         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3536                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3537                                 rte_ixgbe_macsec_strings[i].offset);
3538                 xstats[count].id = count;
3539                 count++;
3540         }
3541
3542         /* RX Priority Stats */
3543         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3544                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3545                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3546                                         rte_ixgbe_rxq_strings[stat].offset +
3547                                         (sizeof(uint64_t) * i));
3548                         xstats[count].id = count;
3549                         count++;
3550                 }
3551         }
3552
3553         /* TX Priority Stats */
3554         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3555                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3556                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3557                                         rte_ixgbe_txq_strings[stat].offset +
3558                                         (sizeof(uint64_t) * i));
3559                         xstats[count].id = count;
3560                         count++;
3561                 }
3562         }
3563         return count;
3564 }
3565
3566 static int
3567 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3568                 uint64_t *values, unsigned int n)
3569 {
3570         if (!ids) {
3571                 struct ixgbe_hw *hw =
3572                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3573                 struct ixgbe_hw_stats *hw_stats =
3574                                 IXGBE_DEV_PRIVATE_TO_STATS(
3575                                                 dev->data->dev_private);
3576                 struct ixgbe_macsec_stats *macsec_stats =
3577                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3578                                         dev->data->dev_private);
3579                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3580                 unsigned int i, stat, count = 0;
3581
3582                 count = ixgbe_xstats_calc_num();
3583
3584                 if (!ids && n < count)
3585                         return count;
3586
3587                 total_missed_rx = 0;
3588                 total_qbrc = 0;
3589                 total_qprc = 0;
3590                 total_qprdc = 0;
3591
3592                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3593                                 &total_missed_rx, &total_qbrc, &total_qprc,
3594                                 &total_qprdc);
3595
3596                 /* If this is a reset xstats is NULL, and we have cleared the
3597                  * registers by reading them.
3598                  */
3599                 if (!ids && !values)
3600                         return 0;
3601
3602                 /* Extended stats from ixgbe_hw_stats */
3603                 count = 0;
3604                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3605                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3606                                         rte_ixgbe_stats_strings[i].offset);
3607                         count++;
3608                 }
3609
3610                 /* MACsec Stats */
3611                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3612                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3613                                         rte_ixgbe_macsec_strings[i].offset);
3614                         count++;
3615                 }
3616
3617                 /* RX Priority Stats */
3618                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3619                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3620                                 values[count] =
3621                                         *(uint64_t *)(((char *)hw_stats) +
3622                                         rte_ixgbe_rxq_strings[stat].offset +
3623                                         (sizeof(uint64_t) * i));
3624                                 count++;
3625                         }
3626                 }
3627
3628                 /* TX Priority Stats */
3629                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3630                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3631                                 values[count] =
3632                                         *(uint64_t *)(((char *)hw_stats) +
3633                                         rte_ixgbe_txq_strings[stat].offset +
3634                                         (sizeof(uint64_t) * i));
3635                                 count++;
3636                         }
3637                 }
3638                 return count;
3639         }
3640
3641         uint16_t i;
3642         uint16_t size = ixgbe_xstats_calc_num();
3643         uint64_t values_copy[size];
3644
3645         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3646
3647         for (i = 0; i < n; i++) {
3648                 if (ids[i] >= size) {
3649                         PMD_INIT_LOG(ERR, "id value isn't valid");
3650                         return -1;
3651                 }
3652                 values[i] = values_copy[ids[i]];
3653         }
3654         return n;
3655 }
3656
3657 static int
3658 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3659 {
3660         struct ixgbe_hw_stats *stats =
3661                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3662         struct ixgbe_macsec_stats *macsec_stats =
3663                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3664                                 dev->data->dev_private);
3665
3666         unsigned count = ixgbe_xstats_calc_num();
3667
3668         /* HW registers are cleared on read */
3669         ixgbe_dev_xstats_get(dev, NULL, count);
3670
3671         /* Reset software totals */
3672         memset(stats, 0, sizeof(*stats));
3673         memset(macsec_stats, 0, sizeof(*macsec_stats));
3674
3675         return 0;
3676 }
3677
3678 static void
3679 ixgbevf_update_stats(struct rte_eth_dev *dev)
3680 {
3681         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3682         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3683                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3684
3685         /* Good Rx packet, include VF loopback */
3686         UPDATE_VF_STAT(IXGBE_VFGPRC,
3687             hw_stats->last_vfgprc, hw_stats->vfgprc);
3688
3689         /* Good Rx octets, include VF loopback */
3690         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3691             hw_stats->last_vfgorc, hw_stats->vfgorc);
3692
3693         /* Good Tx packet, include VF loopback */
3694         UPDATE_VF_STAT(IXGBE_VFGPTC,
3695             hw_stats->last_vfgptc, hw_stats->vfgptc);
3696
3697         /* Good Tx octets, include VF loopback */
3698         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3699             hw_stats->last_vfgotc, hw_stats->vfgotc);
3700
3701         /* Rx Multicst Packet */
3702         UPDATE_VF_STAT(IXGBE_VFMPRC,
3703             hw_stats->last_vfmprc, hw_stats->vfmprc);
3704 }
3705
3706 static int
3707 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3708                        unsigned n)
3709 {
3710         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3711                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3712         unsigned i;
3713
3714         if (n < IXGBEVF_NB_XSTATS)
3715                 return IXGBEVF_NB_XSTATS;
3716
3717         ixgbevf_update_stats(dev);
3718
3719         if (!xstats)
3720                 return 0;
3721
3722         /* Extended stats */
3723         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3724                 xstats[i].id = i;
3725                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3726                         rte_ixgbevf_stats_strings[i].offset);
3727         }
3728
3729         return IXGBEVF_NB_XSTATS;
3730 }
3731
3732 static int
3733 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3734 {
3735         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3736                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3737
3738         ixgbevf_update_stats(dev);
3739
3740         if (stats == NULL)
3741                 return -EINVAL;
3742
3743         stats->ipackets = hw_stats->vfgprc;
3744         stats->ibytes = hw_stats->vfgorc;
3745         stats->opackets = hw_stats->vfgptc;
3746         stats->obytes = hw_stats->vfgotc;
3747         return 0;
3748 }
3749
3750 static int
3751 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3752 {
3753         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3754                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3755
3756         /* Sync HW register to the last stats */
3757         ixgbevf_dev_stats_get(dev, NULL);
3758
3759         /* reset HW current stats*/
3760         hw_stats->vfgprc = 0;
3761         hw_stats->vfgorc = 0;
3762         hw_stats->vfgptc = 0;
3763         hw_stats->vfgotc = 0;
3764
3765         return 0;
3766 }
3767
3768 static int
3769 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3770 {
3771         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3772         u16 eeprom_verh, eeprom_verl;
3773         u32 etrack_id;
3774         int ret;
3775
3776         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3777         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3778
3779         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3780         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3781
3782         ret += 1; /* add the size of '\0' */
3783         if (fw_size < (u32)ret)
3784                 return ret;
3785         else
3786                 return 0;
3787 }
3788
3789 static int
3790 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3791 {
3792         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3793         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3794         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3795
3796         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3797         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3798         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3799                 /*
3800                  * When DCB/VT is off, maximum number of queues changes,
3801                  * except for 82598EB, which remains constant.
3802                  */
3803                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3804                                 hw->mac.type != ixgbe_mac_82598EB)
3805                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3806         }
3807         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3808         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3809         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3810         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3811         dev_info->max_vfs = pci_dev->max_vfs;
3812         if (hw->mac.type == ixgbe_mac_82598EB)
3813                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3814         else
3815                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3816         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3817         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3818         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3819         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3820         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3821                                      dev_info->rx_queue_offload_capa);
3822         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3823         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3824
3825         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3826                 .rx_thresh = {
3827                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3828                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3829                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3830                 },
3831                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3832                 .rx_drop_en = 0,
3833                 .offloads = 0,
3834         };
3835
3836         dev_info->default_txconf = (struct rte_eth_txconf) {
3837                 .tx_thresh = {
3838                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3839                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3840                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3841                 },
3842                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3843                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3844                 .offloads = 0,
3845         };
3846
3847         dev_info->rx_desc_lim = rx_desc_lim;
3848         dev_info->tx_desc_lim = tx_desc_lim;
3849
3850         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3851         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3852         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3853
3854         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3855         if (hw->mac.type == ixgbe_mac_X540 ||
3856             hw->mac.type == ixgbe_mac_X540_vf ||
3857             hw->mac.type == ixgbe_mac_X550 ||
3858             hw->mac.type == ixgbe_mac_X550_vf) {
3859                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3860         }
3861         if (hw->mac.type == ixgbe_mac_X550) {
3862                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3863                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3864         }
3865
3866         /* Driver-preferred Rx/Tx parameters */
3867         dev_info->default_rxportconf.burst_size = 32;
3868         dev_info->default_txportconf.burst_size = 32;
3869         dev_info->default_rxportconf.nb_queues = 1;
3870         dev_info->default_txportconf.nb_queues = 1;
3871         dev_info->default_rxportconf.ring_size = 256;
3872         dev_info->default_txportconf.ring_size = 256;
3873
3874         return 0;
3875 }
3876
3877 static const uint32_t *
3878 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3879 {
3880         static const uint32_t ptypes[] = {
3881                 /* For non-vec functions,
3882                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3883                  * for vec functions,
3884                  * refers to _recv_raw_pkts_vec().
3885                  */
3886                 RTE_PTYPE_L2_ETHER,
3887                 RTE_PTYPE_L3_IPV4,
3888                 RTE_PTYPE_L3_IPV4_EXT,
3889                 RTE_PTYPE_L3_IPV6,
3890                 RTE_PTYPE_L3_IPV6_EXT,
3891                 RTE_PTYPE_L4_SCTP,
3892                 RTE_PTYPE_L4_TCP,
3893                 RTE_PTYPE_L4_UDP,
3894                 RTE_PTYPE_TUNNEL_IP,
3895                 RTE_PTYPE_INNER_L3_IPV6,
3896                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3897                 RTE_PTYPE_INNER_L4_TCP,
3898                 RTE_PTYPE_INNER_L4_UDP,
3899                 RTE_PTYPE_UNKNOWN
3900         };
3901
3902         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3903             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3904             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3905             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3906                 return ptypes;
3907
3908 #if defined(RTE_ARCH_X86)
3909         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3910             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3911                 return ptypes;
3912 #endif
3913         return NULL;
3914 }
3915
3916 static int
3917 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3918                      struct rte_eth_dev_info *dev_info)
3919 {
3920         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3921         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3922
3923         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3924         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3925         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3926         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3927         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3928         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3929         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3930         dev_info->max_vfs = pci_dev->max_vfs;
3931         if (hw->mac.type == ixgbe_mac_82598EB)
3932                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3933         else
3934                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3935         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3936         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3937                                      dev_info->rx_queue_offload_capa);
3938         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3939         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3940         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3941         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3942         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3943
3944         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3945                 .rx_thresh = {
3946                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3947                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3948                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3949                 },
3950                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3951                 .rx_drop_en = 0,
3952                 .offloads = 0,
3953         };
3954
3955         dev_info->default_txconf = (struct rte_eth_txconf) {
3956                 .tx_thresh = {
3957                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3958                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3959                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3960                 },
3961                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3962                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3963                 .offloads = 0,
3964         };
3965
3966         dev_info->rx_desc_lim = rx_desc_lim;
3967         dev_info->tx_desc_lim = tx_desc_lim;
3968
3969         return 0;
3970 }
3971
3972 static int
3973 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3974                    int *link_up, int wait_to_complete)
3975 {
3976         struct ixgbe_adapter *adapter = container_of(hw,
3977                                                      struct ixgbe_adapter, hw);
3978         struct ixgbe_mbx_info *mbx = &hw->mbx;
3979         struct ixgbe_mac_info *mac = &hw->mac;
3980         uint32_t links_reg, in_msg;
3981         int ret_val = 0;
3982
3983         /* If we were hit with a reset drop the link */
3984         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3985                 mac->get_link_status = true;
3986
3987         if (!mac->get_link_status)
3988                 goto out;
3989
3990         /* if link status is down no point in checking to see if pf is up */
3991         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3992         if (!(links_reg & IXGBE_LINKS_UP))
3993                 goto out;
3994
3995         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3996          * before the link status is correct
3997          */
3998         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3999                 int i;
4000
4001                 for (i = 0; i < 5; i++) {
4002                         rte_delay_us(100);
4003                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4004
4005                         if (!(links_reg & IXGBE_LINKS_UP))
4006                                 goto out;
4007                 }
4008         }
4009
4010         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4011         case IXGBE_LINKS_SPEED_10G_82599:
4012                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4013                 if (hw->mac.type >= ixgbe_mac_X550) {
4014                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4015                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4016                 }
4017                 break;
4018         case IXGBE_LINKS_SPEED_1G_82599:
4019                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4020                 break;
4021         case IXGBE_LINKS_SPEED_100_82599:
4022                 *speed = IXGBE_LINK_SPEED_100_FULL;
4023                 if (hw->mac.type == ixgbe_mac_X550) {
4024                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4025                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4026                 }
4027                 break;
4028         case IXGBE_LINKS_SPEED_10_X550EM_A:
4029                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4030                 /* Since Reserved in older MAC's */
4031                 if (hw->mac.type >= ixgbe_mac_X550)
4032                         *speed = IXGBE_LINK_SPEED_10_FULL;
4033                 break;
4034         default:
4035                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4036         }
4037
4038         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4039                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4040                         mac->get_link_status = true;
4041                 else
4042                         mac->get_link_status = false;
4043
4044                 goto out;
4045         }
4046
4047         /* if the read failed it could just be a mailbox collision, best wait
4048          * until we are called again and don't report an error
4049          */
4050         if (mbx->ops.read(hw, &in_msg, 1, 0))
4051                 goto out;
4052
4053         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4054                 /* msg is not CTS and is NACK we must have lost CTS status */
4055                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4056                         mac->get_link_status = false;
4057                 goto out;
4058         }
4059
4060         /* the pf is talking, if we timed out in the past we reinit */
4061         if (!mbx->timeout) {
4062                 ret_val = -1;
4063                 goto out;
4064         }
4065
4066         /* if we passed all the tests above then the link is up and we no
4067          * longer need to check for link
4068          */
4069         mac->get_link_status = false;
4070
4071 out:
4072         *link_up = !mac->get_link_status;
4073         return ret_val;
4074 }
4075
4076 static void
4077 ixgbe_dev_setup_link_alarm_handler(void *param)
4078 {
4079         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4080         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4081         struct ixgbe_interrupt *intr =
4082                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4083         u32 speed;
4084         bool autoneg = false;
4085
4086         speed = hw->phy.autoneg_advertised;
4087         if (!speed)
4088                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4089
4090         ixgbe_setup_link(hw, speed, true);
4091
4092         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4093 }
4094
4095 /* return 0 means link status changed, -1 means not changed */
4096 int
4097 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4098                             int wait_to_complete, int vf)
4099 {
4100         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4101         struct rte_eth_link link;
4102         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4103         struct ixgbe_interrupt *intr =
4104                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4105         int link_up;
4106         int diag;
4107         int wait = 1;
4108
4109         memset(&link, 0, sizeof(link));
4110         link.link_status = ETH_LINK_DOWN;
4111         link.link_speed = ETH_SPEED_NUM_NONE;
4112         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4113         link.link_autoneg = ETH_LINK_AUTONEG;
4114
4115         hw->mac.get_link_status = true;
4116
4117         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4118                 return rte_eth_linkstatus_set(dev, &link);
4119
4120         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4121         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4122                 wait = 0;
4123
4124         if (vf)
4125                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4126         else
4127                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4128
4129         if (diag != 0) {
4130                 link.link_speed = ETH_SPEED_NUM_100M;
4131                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4132                 return rte_eth_linkstatus_set(dev, &link);
4133         }
4134
4135         if (link_up == 0) {
4136                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4137                         intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4138                         rte_eal_alarm_set(10,
4139                                 ixgbe_dev_setup_link_alarm_handler, dev);
4140                 }
4141                 return rte_eth_linkstatus_set(dev, &link);
4142         }
4143
4144         link.link_status = ETH_LINK_UP;
4145         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4146
4147         switch (link_speed) {
4148         default:
4149         case IXGBE_LINK_SPEED_UNKNOWN:
4150                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4151                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4152                         link.link_speed = ETH_SPEED_NUM_10M;
4153                 else
4154                         link.link_speed = ETH_SPEED_NUM_100M;
4155                 break;
4156
4157         case IXGBE_LINK_SPEED_100_FULL:
4158                 link.link_speed = ETH_SPEED_NUM_100M;
4159                 break;
4160
4161         case IXGBE_LINK_SPEED_1GB_FULL:
4162                 link.link_speed = ETH_SPEED_NUM_1G;
4163                 break;
4164
4165         case IXGBE_LINK_SPEED_2_5GB_FULL:
4166                 link.link_speed = ETH_SPEED_NUM_2_5G;
4167                 break;
4168
4169         case IXGBE_LINK_SPEED_5GB_FULL:
4170                 link.link_speed = ETH_SPEED_NUM_5G;
4171                 break;
4172
4173         case IXGBE_LINK_SPEED_10GB_FULL:
4174                 link.link_speed = ETH_SPEED_NUM_10G;
4175                 break;
4176         }
4177
4178         return rte_eth_linkstatus_set(dev, &link);
4179 }
4180
4181 static int
4182 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4183 {
4184         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4185 }
4186
4187 static int
4188 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4189 {
4190         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4191 }
4192
4193 static int
4194 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4195 {
4196         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4197         uint32_t fctrl;
4198
4199         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4200         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4201         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4202
4203         return 0;
4204 }
4205
4206 static int
4207 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4208 {
4209         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4210         uint32_t fctrl;
4211
4212         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4213         fctrl &= (~IXGBE_FCTRL_UPE);
4214         if (dev->data->all_multicast == 1)
4215                 fctrl |= IXGBE_FCTRL_MPE;
4216         else
4217                 fctrl &= (~IXGBE_FCTRL_MPE);
4218         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4219
4220         return 0;
4221 }
4222
4223 static void
4224 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4225 {
4226         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4227         uint32_t fctrl;
4228
4229         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4230         fctrl |= IXGBE_FCTRL_MPE;
4231         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4232 }
4233
4234 static void
4235 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4236 {
4237         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4238         uint32_t fctrl;
4239
4240         if (dev->data->promiscuous == 1)
4241                 return; /* must remain in all_multicast mode */
4242
4243         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4244         fctrl &= (~IXGBE_FCTRL_MPE);
4245         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4246 }
4247
4248 /**
4249  * It clears the interrupt causes and enables the interrupt.
4250  * It will be called once only during nic initialized.
4251  *
4252  * @param dev
4253  *  Pointer to struct rte_eth_dev.
4254  * @param on
4255  *  Enable or Disable.
4256  *
4257  * @return
4258  *  - On success, zero.
4259  *  - On failure, a negative value.
4260  */
4261 static int
4262 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4263 {
4264         struct ixgbe_interrupt *intr =
4265                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4266
4267         ixgbe_dev_link_status_print(dev);
4268         if (on)
4269                 intr->mask |= IXGBE_EICR_LSC;
4270         else
4271                 intr->mask &= ~IXGBE_EICR_LSC;
4272
4273         return 0;
4274 }
4275
4276 /**
4277  * It clears the interrupt causes and enables the interrupt.
4278  * It will be called once only during nic initialized.
4279  *
4280  * @param dev
4281  *  Pointer to struct rte_eth_dev.
4282  *
4283  * @return
4284  *  - On success, zero.
4285  *  - On failure, a negative value.
4286  */
4287 static int
4288 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4289 {
4290         struct ixgbe_interrupt *intr =
4291                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4292
4293         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4294
4295         return 0;
4296 }
4297
4298 /**
4299  * It clears the interrupt causes and enables the interrupt.
4300  * It will be called once only during nic initialized.
4301  *
4302  * @param dev
4303  *  Pointer to struct rte_eth_dev.
4304  *
4305  * @return
4306  *  - On success, zero.
4307  *  - On failure, a negative value.
4308  */
4309 static int
4310 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4311 {
4312         struct ixgbe_interrupt *intr =
4313                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4314
4315         intr->mask |= IXGBE_EICR_LINKSEC;
4316
4317         return 0;
4318 }
4319
4320 /*
4321  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4322  *
4323  * @param dev
4324  *  Pointer to struct rte_eth_dev.
4325  *
4326  * @return
4327  *  - On success, zero.
4328  *  - On failure, a negative value.
4329  */
4330 static int
4331 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4332 {
4333         uint32_t eicr;
4334         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4335         struct ixgbe_interrupt *intr =
4336                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4337
4338         /* clear all cause mask */
4339         ixgbe_disable_intr(hw);
4340
4341         /* read-on-clear nic registers here */
4342         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4343         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4344
4345         intr->flags = 0;
4346
4347         /* set flag for async link update */
4348         if (eicr & IXGBE_EICR_LSC)
4349                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4350
4351         if (eicr & IXGBE_EICR_MAILBOX)
4352                 intr->flags |= IXGBE_FLAG_MAILBOX;
4353
4354         if (eicr & IXGBE_EICR_LINKSEC)
4355                 intr->flags |= IXGBE_FLAG_MACSEC;
4356
4357         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4358             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4359             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4360                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4361
4362         return 0;
4363 }
4364
4365 /**
4366  * It gets and then prints the link status.
4367  *
4368  * @param dev
4369  *  Pointer to struct rte_eth_dev.
4370  *
4371  * @return
4372  *  - On success, zero.
4373  *  - On failure, a negative value.
4374  */
4375 static void
4376 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4377 {
4378         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4379         struct rte_eth_link link;
4380
4381         rte_eth_linkstatus_get(dev, &link);
4382
4383         if (link.link_status) {
4384                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4385                                         (int)(dev->data->port_id),
4386                                         (unsigned)link.link_speed,
4387                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4388                                         "full-duplex" : "half-duplex");
4389         } else {
4390                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4391                                 (int)(dev->data->port_id));
4392         }
4393         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4394                                 pci_dev->addr.domain,
4395                                 pci_dev->addr.bus,
4396                                 pci_dev->addr.devid,
4397                                 pci_dev->addr.function);
4398 }
4399
4400 /*
4401  * It executes link_update after knowing an interrupt occurred.
4402  *
4403  * @param dev
4404  *  Pointer to struct rte_eth_dev.
4405  *
4406  * @return
4407  *  - On success, zero.
4408  *  - On failure, a negative value.
4409  */
4410 static int
4411 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4412 {
4413         struct ixgbe_interrupt *intr =
4414                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4415         int64_t timeout;
4416         struct ixgbe_hw *hw =
4417                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4418
4419         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4420
4421         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4422                 ixgbe_pf_mbx_process(dev);
4423                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4424         }
4425
4426         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4427                 ixgbe_handle_lasi(hw);
4428                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4429         }
4430
4431         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4432                 struct rte_eth_link link;
4433
4434                 /* get the link status before link update, for predicting later */
4435                 rte_eth_linkstatus_get(dev, &link);
4436
4437                 ixgbe_dev_link_update(dev, 0);
4438
4439                 /* likely to up */
4440                 if (!link.link_status)
4441                         /* handle it 1 sec later, wait it being stable */
4442                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4443                 /* likely to down */
4444                 else
4445                         /* handle it 4 sec later, wait it being stable */
4446                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4447
4448                 ixgbe_dev_link_status_print(dev);
4449                 if (rte_eal_alarm_set(timeout * 1000,
4450                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4451                         PMD_DRV_LOG(ERR, "Error setting alarm");
4452                 else {
4453                         /* remember original mask */
4454                         intr->mask_original = intr->mask;
4455                         /* only disable lsc interrupt */
4456                         intr->mask &= ~IXGBE_EIMS_LSC;
4457                 }
4458         }
4459
4460         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4461         ixgbe_enable_intr(dev);
4462
4463         return 0;
4464 }
4465
4466 /**
4467  * Interrupt handler which shall be registered for alarm callback for delayed
4468  * handling specific interrupt to wait for the stable nic state. As the
4469  * NIC interrupt state is not stable for ixgbe after link is just down,
4470  * it needs to wait 4 seconds to get the stable status.
4471  *
4472  * @param handle
4473  *  Pointer to interrupt handle.
4474  * @param param
4475  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4476  *
4477  * @return
4478  *  void
4479  */
4480 static void
4481 ixgbe_dev_interrupt_delayed_handler(void *param)
4482 {
4483         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4484         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4485         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4486         struct ixgbe_interrupt *intr =
4487                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4488         struct ixgbe_hw *hw =
4489                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4490         uint32_t eicr;
4491
4492         ixgbe_disable_intr(hw);
4493
4494         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4495         if (eicr & IXGBE_EICR_MAILBOX)
4496                 ixgbe_pf_mbx_process(dev);
4497
4498         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4499                 ixgbe_handle_lasi(hw);
4500                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4501         }
4502
4503         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4504                 ixgbe_dev_link_update(dev, 0);
4505                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4506                 ixgbe_dev_link_status_print(dev);
4507                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4508                                               NULL);
4509         }
4510
4511         if (intr->flags & IXGBE_FLAG_MACSEC) {
4512                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4513                                               NULL);
4514                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4515         }
4516
4517         /* restore original mask */
4518         intr->mask = intr->mask_original;
4519         intr->mask_original = 0;
4520
4521         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4522         ixgbe_enable_intr(dev);
4523         rte_intr_ack(intr_handle);
4524 }
4525
4526 /**
4527  * Interrupt handler triggered by NIC  for handling
4528  * specific interrupt.
4529  *
4530  * @param handle
4531  *  Pointer to interrupt handle.
4532  * @param param
4533  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4534  *
4535  * @return
4536  *  void
4537  */
4538 static void
4539 ixgbe_dev_interrupt_handler(void *param)
4540 {
4541         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4542
4543         ixgbe_dev_interrupt_get_status(dev);
4544         ixgbe_dev_interrupt_action(dev);
4545 }
4546
4547 static int
4548 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4549 {
4550         struct ixgbe_hw *hw;
4551
4552         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4553         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4554 }
4555
4556 static int
4557 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4558 {
4559         struct ixgbe_hw *hw;
4560
4561         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4562         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4563 }
4564
4565 static int
4566 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4567 {
4568         struct ixgbe_hw *hw;
4569         uint32_t mflcn_reg;
4570         uint32_t fccfg_reg;
4571         int rx_pause;
4572         int tx_pause;
4573
4574         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4575
4576         fc_conf->pause_time = hw->fc.pause_time;
4577         fc_conf->high_water = hw->fc.high_water[0];
4578         fc_conf->low_water = hw->fc.low_water[0];
4579         fc_conf->send_xon = hw->fc.send_xon;
4580         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4581
4582         /*
4583          * Return rx_pause status according to actual setting of
4584          * MFLCN register.
4585          */
4586         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4587         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4588                 rx_pause = 1;
4589         else
4590                 rx_pause = 0;
4591
4592         /*
4593          * Return tx_pause status according to actual setting of
4594          * FCCFG register.
4595          */
4596         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4597         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4598                 tx_pause = 1;
4599         else
4600                 tx_pause = 0;
4601
4602         if (rx_pause && tx_pause)
4603                 fc_conf->mode = RTE_FC_FULL;
4604         else if (rx_pause)
4605                 fc_conf->mode = RTE_FC_RX_PAUSE;
4606         else if (tx_pause)
4607                 fc_conf->mode = RTE_FC_TX_PAUSE;
4608         else
4609                 fc_conf->mode = RTE_FC_NONE;
4610
4611         return 0;
4612 }
4613
4614 static int
4615 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4616 {
4617         struct ixgbe_hw *hw;
4618         int err;
4619         uint32_t rx_buf_size;
4620         uint32_t max_high_water;
4621         uint32_t mflcn;
4622         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4623                 ixgbe_fc_none,
4624                 ixgbe_fc_rx_pause,
4625                 ixgbe_fc_tx_pause,
4626                 ixgbe_fc_full
4627         };
4628
4629         PMD_INIT_FUNC_TRACE();
4630
4631         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4632         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4633         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4634
4635         /*
4636          * At least reserve one Ethernet frame for watermark
4637          * high_water/low_water in kilo bytes for ixgbe
4638          */
4639         max_high_water = (rx_buf_size -
4640                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4641         if ((fc_conf->high_water > max_high_water) ||
4642                 (fc_conf->high_water < fc_conf->low_water)) {
4643                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4644                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4645                 return -EINVAL;
4646         }
4647
4648         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4649         hw->fc.pause_time     = fc_conf->pause_time;
4650         hw->fc.high_water[0]  = fc_conf->high_water;
4651         hw->fc.low_water[0]   = fc_conf->low_water;
4652         hw->fc.send_xon       = fc_conf->send_xon;
4653         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4654
4655         err = ixgbe_fc_enable(hw);
4656
4657         /* Not negotiated is not an error case */
4658         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4659
4660                 /* check if we want to forward MAC frames - driver doesn't have native
4661                  * capability to do that, so we'll write the registers ourselves */
4662
4663                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4664
4665                 /* set or clear MFLCN.PMCF bit depending on configuration */
4666                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4667                         mflcn |= IXGBE_MFLCN_PMCF;
4668                 else
4669                         mflcn &= ~IXGBE_MFLCN_PMCF;
4670
4671                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4672                 IXGBE_WRITE_FLUSH(hw);
4673
4674                 return 0;
4675         }
4676
4677         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4678         return -EIO;
4679 }
4680
4681 /**
4682  *  ixgbe_pfc_enable_generic - Enable flow control
4683  *  @hw: pointer to hardware structure
4684  *  @tc_num: traffic class number
4685  *  Enable flow control according to the current settings.
4686  */
4687 static int
4688 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4689 {
4690         int ret_val = 0;
4691         uint32_t mflcn_reg, fccfg_reg;
4692         uint32_t reg;
4693         uint32_t fcrtl, fcrth;
4694         uint8_t i;
4695         uint8_t nb_rx_en;
4696
4697         /* Validate the water mark configuration */
4698         if (!hw->fc.pause_time) {
4699                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4700                 goto out;
4701         }
4702
4703         /* Low water mark of zero causes XOFF floods */
4704         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4705                  /* High/Low water can not be 0 */
4706                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4707                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4708                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4709                         goto out;
4710                 }
4711
4712                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4713                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4714                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4715                         goto out;
4716                 }
4717         }
4718         /* Negotiate the fc mode to use */
4719         ixgbe_fc_autoneg(hw);
4720
4721         /* Disable any previous flow control settings */
4722         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4723         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4724
4725         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4726         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4727
4728         switch (hw->fc.current_mode) {
4729         case ixgbe_fc_none:
4730                 /*
4731                  * If the count of enabled RX Priority Flow control >1,
4732                  * and the TX pause can not be disabled
4733                  */
4734                 nb_rx_en = 0;
4735                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4736                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4737                         if (reg & IXGBE_FCRTH_FCEN)
4738                                 nb_rx_en++;
4739                 }
4740                 if (nb_rx_en > 1)
4741                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4742                 break;
4743         case ixgbe_fc_rx_pause:
4744                 /*
4745                  * Rx Flow control is enabled and Tx Flow control is
4746                  * disabled by software override. Since there really
4747                  * isn't a way to advertise that we are capable of RX
4748                  * Pause ONLY, we will advertise that we support both
4749                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4750                  * disable the adapter's ability to send PAUSE frames.
4751                  */
4752                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4753                 /*
4754                  * If the count of enabled RX Priority Flow control >1,
4755                  * and the TX pause can not be disabled
4756                  */
4757                 nb_rx_en = 0;
4758                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4759                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4760                         if (reg & IXGBE_FCRTH_FCEN)
4761                                 nb_rx_en++;
4762                 }
4763                 if (nb_rx_en > 1)
4764                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4765                 break;
4766         case ixgbe_fc_tx_pause:
4767                 /*
4768                  * Tx Flow control is enabled, and Rx Flow control is
4769                  * disabled by software override.
4770                  */
4771                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4772                 break;
4773         case ixgbe_fc_full:
4774                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4775                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4776                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4777                 break;
4778         default:
4779                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4780                 ret_val = IXGBE_ERR_CONFIG;
4781                 goto out;
4782         }
4783
4784         /* Set 802.3x based flow control settings. */
4785         mflcn_reg |= IXGBE_MFLCN_DPF;
4786         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4787         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4788
4789         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4790         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4791                 hw->fc.high_water[tc_num]) {
4792                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4793                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4794                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4795         } else {
4796                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4797                 /*
4798                  * In order to prevent Tx hangs when the internal Tx
4799                  * switch is enabled we must set the high water mark
4800                  * to the maximum FCRTH value.  This allows the Tx
4801                  * switch to function even under heavy Rx workloads.
4802                  */
4803                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4804         }
4805         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4806
4807         /* Configure pause time (2 TCs per register) */
4808         reg = hw->fc.pause_time * 0x00010001;
4809         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4810                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4811
4812         /* Configure flow control refresh threshold value */
4813         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4814
4815 out:
4816         return ret_val;
4817 }
4818
4819 static int
4820 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4821 {
4822         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4823         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4824
4825         if (hw->mac.type != ixgbe_mac_82598EB) {
4826                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4827         }
4828         return ret_val;
4829 }
4830
4831 static int
4832 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4833 {
4834         int err;
4835         uint32_t rx_buf_size;
4836         uint32_t max_high_water;
4837         uint8_t tc_num;
4838         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4839         struct ixgbe_hw *hw =
4840                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4841         struct ixgbe_dcb_config *dcb_config =
4842                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4843
4844         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4845                 ixgbe_fc_none,
4846                 ixgbe_fc_rx_pause,
4847                 ixgbe_fc_tx_pause,
4848                 ixgbe_fc_full
4849         };
4850
4851         PMD_INIT_FUNC_TRACE();
4852
4853         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4854         tc_num = map[pfc_conf->priority];
4855         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4856         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4857         /*
4858          * At least reserve one Ethernet frame for watermark
4859          * high_water/low_water in kilo bytes for ixgbe
4860          */
4861         max_high_water = (rx_buf_size -
4862                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4863         if ((pfc_conf->fc.high_water > max_high_water) ||
4864             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4865                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4866                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4867                 return -EINVAL;
4868         }
4869
4870         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4871         hw->fc.pause_time = pfc_conf->fc.pause_time;
4872         hw->fc.send_xon = pfc_conf->fc.send_xon;
4873         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4874         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4875
4876         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4877
4878         /* Not negotiated is not an error case */
4879         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4880                 return 0;
4881
4882         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4883         return -EIO;
4884 }
4885
4886 static int
4887 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4888                           struct rte_eth_rss_reta_entry64 *reta_conf,
4889                           uint16_t reta_size)
4890 {
4891         uint16_t i, sp_reta_size;
4892         uint8_t j, mask;
4893         uint32_t reta, r;
4894         uint16_t idx, shift;
4895         struct ixgbe_adapter *adapter = dev->data->dev_private;
4896         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4897         uint32_t reta_reg;
4898
4899         PMD_INIT_FUNC_TRACE();
4900
4901         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4902                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4903                         "NIC.");
4904                 return -ENOTSUP;
4905         }
4906
4907         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4908         if (reta_size != sp_reta_size) {
4909                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4910                         "(%d) doesn't match the number hardware can supported "
4911                         "(%d)", reta_size, sp_reta_size);
4912                 return -EINVAL;
4913         }
4914
4915         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4916                 idx = i / RTE_RETA_GROUP_SIZE;
4917                 shift = i % RTE_RETA_GROUP_SIZE;
4918                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4919                                                 IXGBE_4_BIT_MASK);
4920                 if (!mask)
4921                         continue;
4922                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4923                 if (mask == IXGBE_4_BIT_MASK)
4924                         r = 0;
4925                 else
4926                         r = IXGBE_READ_REG(hw, reta_reg);
4927                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4928                         if (mask & (0x1 << j))
4929                                 reta |= reta_conf[idx].reta[shift + j] <<
4930                                                         (CHAR_BIT * j);
4931                         else
4932                                 reta |= r & (IXGBE_8_BIT_MASK <<
4933                                                 (CHAR_BIT * j));
4934                 }
4935                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4936         }
4937         adapter->rss_reta_updated = 1;
4938
4939         return 0;
4940 }
4941
4942 static int
4943 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4944                          struct rte_eth_rss_reta_entry64 *reta_conf,
4945                          uint16_t reta_size)
4946 {
4947         uint16_t i, sp_reta_size;
4948         uint8_t j, mask;
4949         uint32_t reta;
4950         uint16_t idx, shift;
4951         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4952         uint32_t reta_reg;
4953
4954         PMD_INIT_FUNC_TRACE();
4955         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4956         if (reta_size != sp_reta_size) {
4957                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4958                         "(%d) doesn't match the number hardware can supported "
4959                         "(%d)", reta_size, sp_reta_size);
4960                 return -EINVAL;
4961         }
4962
4963         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4964                 idx = i / RTE_RETA_GROUP_SIZE;
4965                 shift = i % RTE_RETA_GROUP_SIZE;
4966                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4967                                                 IXGBE_4_BIT_MASK);
4968                 if (!mask)
4969                         continue;
4970
4971                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4972                 reta = IXGBE_READ_REG(hw, reta_reg);
4973                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4974                         if (mask & (0x1 << j))
4975                                 reta_conf[idx].reta[shift + j] =
4976                                         ((reta >> (CHAR_BIT * j)) &
4977                                                 IXGBE_8_BIT_MASK);
4978                 }
4979         }
4980
4981         return 0;
4982 }
4983
4984 static int
4985 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
4986                                 uint32_t index, uint32_t pool)
4987 {
4988         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4989         uint32_t enable_addr = 1;
4990
4991         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4992                              pool, enable_addr);
4993 }
4994
4995 static void
4996 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4997 {
4998         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4999
5000         ixgbe_clear_rar(hw, index);
5001 }
5002
5003 static int
5004 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5005 {
5006         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5007
5008         ixgbe_remove_rar(dev, 0);
5009         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5010
5011         return 0;
5012 }
5013
5014 static bool
5015 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5016 {
5017         if (strcmp(dev->device->driver->name, drv->driver.name))
5018                 return false;
5019
5020         return true;
5021 }
5022
5023 bool
5024 is_ixgbe_supported(struct rte_eth_dev *dev)
5025 {
5026         return is_device_supported(dev, &rte_ixgbe_pmd);
5027 }
5028
5029 static int
5030 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5031 {
5032         uint32_t hlreg0;
5033         uint32_t maxfrs;
5034         struct ixgbe_hw *hw;
5035         struct rte_eth_dev_info dev_info;
5036         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5037         struct rte_eth_dev_data *dev_data = dev->data;
5038         int ret;
5039
5040         ret = ixgbe_dev_info_get(dev, &dev_info);
5041         if (ret != 0)
5042                 return ret;
5043
5044         /* check that mtu is within the allowed range */
5045         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5046                 return -EINVAL;
5047
5048         /* If device is started, refuse mtu that requires the support of
5049          * scattered packets when this feature has not been enabled before.
5050          */
5051         if (dev_data->dev_started && !dev_data->scattered_rx &&
5052             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5053              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5054                 PMD_INIT_LOG(ERR, "Stop port first.");
5055                 return -EINVAL;
5056         }
5057
5058         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5059         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5060
5061         /* switch to jumbo mode if needed */
5062         if (frame_size > RTE_ETHER_MAX_LEN) {
5063                 dev->data->dev_conf.rxmode.offloads |=
5064                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5065                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5066         } else {
5067                 dev->data->dev_conf.rxmode.offloads &=
5068                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5069                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5070         }
5071         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5072
5073         /* update max frame size */
5074         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5075
5076         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5077         maxfrs &= 0x0000FFFF;
5078         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5079         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5080
5081         return 0;
5082 }
5083
5084 /*
5085  * Virtual Function operations
5086  */
5087 static void
5088 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5089 {
5090         struct ixgbe_interrupt *intr =
5091                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5092         struct ixgbe_hw *hw =
5093                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5094
5095         PMD_INIT_FUNC_TRACE();
5096
5097         /* Clear interrupt mask to stop from interrupts being generated */
5098         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5099
5100         IXGBE_WRITE_FLUSH(hw);
5101
5102         /* Clear mask value. */
5103         intr->mask = 0;
5104 }
5105
5106 static void
5107 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5108 {
5109         struct ixgbe_interrupt *intr =
5110                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5111         struct ixgbe_hw *hw =
5112                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5113
5114         PMD_INIT_FUNC_TRACE();
5115
5116         /* VF enable interrupt autoclean */
5117         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5118         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5119         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5120
5121         IXGBE_WRITE_FLUSH(hw);
5122
5123         /* Save IXGBE_VTEIMS value to mask. */
5124         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5125 }
5126
5127 static int
5128 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5129 {
5130         struct rte_eth_conf *conf = &dev->data->dev_conf;
5131         struct ixgbe_adapter *adapter = dev->data->dev_private;
5132
5133         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5134                      dev->data->port_id);
5135
5136         /*
5137          * VF has no ability to enable/disable HW CRC
5138          * Keep the persistent behavior the same as Host PF
5139          */
5140 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5141         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5142                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5143                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5144         }
5145 #else
5146         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5147                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5148                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5149         }
5150 #endif
5151
5152         /*
5153          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5154          * allocation or vector Rx preconditions we will reset it.
5155          */
5156         adapter->rx_bulk_alloc_allowed = true;
5157         adapter->rx_vec_allowed = true;
5158
5159         return 0;
5160 }
5161
5162 static int
5163 ixgbevf_dev_start(struct rte_eth_dev *dev)
5164 {
5165         struct ixgbe_hw *hw =
5166                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5167         uint32_t intr_vector = 0;
5168         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5169         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5170
5171         int err, mask = 0;
5172
5173         PMD_INIT_FUNC_TRACE();
5174
5175         /* Stop the link setup handler before resetting the HW. */
5176         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5177
5178         err = hw->mac.ops.reset_hw(hw);
5179         if (err) {
5180                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5181                 return err;
5182         }
5183         hw->mac.get_link_status = true;
5184
5185         /* negotiate mailbox API version to use with the PF. */
5186         ixgbevf_negotiate_api(hw);
5187
5188         ixgbevf_dev_tx_init(dev);
5189
5190         /* This can fail when allocating mbufs for descriptor rings */
5191         err = ixgbevf_dev_rx_init(dev);
5192         if (err) {
5193                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5194                 ixgbe_dev_clear_queues(dev);
5195                 return err;
5196         }
5197
5198         /* Set vfta */
5199         ixgbevf_set_vfta_all(dev, 1);
5200
5201         /* Set HW strip */
5202         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5203                 ETH_VLAN_EXTEND_MASK;
5204         err = ixgbevf_vlan_offload_config(dev, mask);
5205         if (err) {
5206                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5207                 ixgbe_dev_clear_queues(dev);
5208                 return err;
5209         }
5210
5211         ixgbevf_dev_rxtx_start(dev);
5212
5213         /* check and configure queue intr-vector mapping */
5214         if (rte_intr_cap_multiple(intr_handle) &&
5215             dev->data->dev_conf.intr_conf.rxq) {
5216                 /* According to datasheet, only vector 0/1/2 can be used,
5217                  * now only one vector is used for Rx queue
5218                  */
5219                 intr_vector = 1;
5220                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5221                         return -1;
5222         }
5223
5224         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5225                 intr_handle->intr_vec =
5226                         rte_zmalloc("intr_vec",
5227                                     dev->data->nb_rx_queues * sizeof(int), 0);
5228                 if (intr_handle->intr_vec == NULL) {
5229                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5230                                      " intr_vec", dev->data->nb_rx_queues);
5231                         return -ENOMEM;
5232                 }
5233         }
5234         ixgbevf_configure_msix(dev);
5235
5236         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5237          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5238          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5239          * is not cleared, it will fail when following rte_intr_enable( ) tries
5240          * to map Rx queue interrupt to other VFIO vectors.
5241          * So clear uio/vfio intr/evevnfd first to avoid failure.
5242          */
5243         rte_intr_disable(intr_handle);
5244
5245         rte_intr_enable(intr_handle);
5246
5247         /* Re-enable interrupt for VF */
5248         ixgbevf_intr_enable(dev);
5249
5250         /*
5251          * Update link status right before return, because it may
5252          * start link configuration process in a separate thread.
5253          */
5254         ixgbevf_dev_link_update(dev, 0);
5255
5256         return 0;
5257 }
5258
5259 static void
5260 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5261 {
5262         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5263         struct ixgbe_adapter *adapter = dev->data->dev_private;
5264         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5265         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5266
5267         PMD_INIT_FUNC_TRACE();
5268
5269         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5270
5271         ixgbevf_intr_disable(dev);
5272
5273         hw->adapter_stopped = 1;
5274         ixgbe_stop_adapter(hw);
5275
5276         /*
5277           * Clear what we set, but we still keep shadow_vfta to
5278           * restore after device starts
5279           */
5280         ixgbevf_set_vfta_all(dev, 0);
5281
5282         /* Clear stored conf */
5283         dev->data->scattered_rx = 0;
5284
5285         ixgbe_dev_clear_queues(dev);
5286
5287         /* Clean datapath event and queue/vec mapping */
5288         rte_intr_efd_disable(intr_handle);
5289         if (intr_handle->intr_vec != NULL) {
5290                 rte_free(intr_handle->intr_vec);
5291                 intr_handle->intr_vec = NULL;
5292         }
5293
5294         adapter->rss_reta_updated = 0;
5295 }
5296
5297 static void
5298 ixgbevf_dev_close(struct rte_eth_dev *dev)
5299 {
5300         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5301
5302         PMD_INIT_FUNC_TRACE();
5303
5304         ixgbe_reset_hw(hw);
5305
5306         ixgbevf_dev_stop(dev);
5307
5308         ixgbe_dev_free_queues(dev);
5309
5310         /**
5311          * Remove the VF MAC address ro ensure
5312          * that the VF traffic goes to the PF
5313          * after stop, close and detach of the VF
5314          **/
5315         ixgbevf_remove_mac_addr(dev, 0);
5316 }
5317
5318 /*
5319  * Reset VF device
5320  */
5321 static int
5322 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5323 {
5324         int ret;
5325
5326         ret = eth_ixgbevf_dev_uninit(dev);
5327         if (ret)
5328                 return ret;
5329
5330         ret = eth_ixgbevf_dev_init(dev);
5331
5332         return ret;
5333 }
5334
5335 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5336 {
5337         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5338         struct ixgbe_vfta *shadow_vfta =
5339                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5340         int i = 0, j = 0, vfta = 0, mask = 1;
5341
5342         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5343                 vfta = shadow_vfta->vfta[i];
5344                 if (vfta) {
5345                         mask = 1;
5346                         for (j = 0; j < 32; j++) {
5347                                 if (vfta & mask)
5348                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5349                                                        on, false);
5350                                 mask <<= 1;
5351                         }
5352                 }
5353         }
5354
5355 }
5356
5357 static int
5358 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5359 {
5360         struct ixgbe_hw *hw =
5361                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5362         struct ixgbe_vfta *shadow_vfta =
5363                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5364         uint32_t vid_idx = 0;
5365         uint32_t vid_bit = 0;
5366         int ret = 0;
5367
5368         PMD_INIT_FUNC_TRACE();
5369
5370         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5371         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5372         if (ret) {
5373                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5374                 return ret;
5375         }
5376         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5377         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5378
5379         /* Save what we set and retore it after device reset */
5380         if (on)
5381                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5382         else
5383                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5384
5385         return 0;
5386 }
5387
5388 static void
5389 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5390 {
5391         struct ixgbe_hw *hw =
5392                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5393         uint32_t ctrl;
5394
5395         PMD_INIT_FUNC_TRACE();
5396
5397         if (queue >= hw->mac.max_rx_queues)
5398                 return;
5399
5400         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5401         if (on)
5402                 ctrl |= IXGBE_RXDCTL_VME;
5403         else
5404                 ctrl &= ~IXGBE_RXDCTL_VME;
5405         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5406
5407         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5408 }
5409
5410 static int
5411 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5412 {
5413         struct ixgbe_rx_queue *rxq;
5414         uint16_t i;
5415         int on = 0;
5416
5417         /* VF function only support hw strip feature, others are not support */
5418         if (mask & ETH_VLAN_STRIP_MASK) {
5419                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5420                         rxq = dev->data->rx_queues[i];
5421                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5422                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5423                 }
5424         }
5425
5426         return 0;
5427 }
5428
5429 static int
5430 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5431 {
5432         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5433
5434         ixgbevf_vlan_offload_config(dev, mask);
5435
5436         return 0;
5437 }
5438
5439 int
5440 ixgbe_vt_check(struct ixgbe_hw *hw)
5441 {
5442         uint32_t reg_val;
5443
5444         /* if Virtualization Technology is enabled */
5445         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5446         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5447                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5448                 return -1;
5449         }
5450
5451         return 0;
5452 }
5453
5454 static uint32_t
5455 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5456 {
5457         uint32_t vector = 0;
5458
5459         switch (hw->mac.mc_filter_type) {
5460         case 0:   /* use bits [47:36] of the address */
5461                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5462                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5463                 break;
5464         case 1:   /* use bits [46:35] of the address */
5465                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5466                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5467                 break;
5468         case 2:   /* use bits [45:34] of the address */
5469                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5470                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5471                 break;
5472         case 3:   /* use bits [43:32] of the address */
5473                 vector = ((uc_addr->addr_bytes[4]) |
5474                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5475                 break;
5476         default:  /* Invalid mc_filter_type */
5477                 break;
5478         }
5479
5480         /* vector can only be 12-bits or boundary will be exceeded */
5481         vector &= 0xFFF;
5482         return vector;
5483 }
5484
5485 static int
5486 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5487                         struct rte_ether_addr *mac_addr, uint8_t on)
5488 {
5489         uint32_t vector;
5490         uint32_t uta_idx;
5491         uint32_t reg_val;
5492         uint32_t uta_shift;
5493         uint32_t rc;
5494         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5495         const uint32_t ixgbe_uta_bit_shift = 5;
5496         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5497         const uint32_t bit1 = 0x1;
5498
5499         struct ixgbe_hw *hw =
5500                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5501         struct ixgbe_uta_info *uta_info =
5502                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5503
5504         /* The UTA table only exists on 82599 hardware and newer */
5505         if (hw->mac.type < ixgbe_mac_82599EB)
5506                 return -ENOTSUP;
5507
5508         vector = ixgbe_uta_vector(hw, mac_addr);
5509         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5510         uta_shift = vector & ixgbe_uta_bit_mask;
5511
5512         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5513         if (rc == on)
5514                 return 0;
5515
5516         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5517         if (on) {
5518                 uta_info->uta_in_use++;
5519                 reg_val |= (bit1 << uta_shift);
5520                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5521         } else {
5522                 uta_info->uta_in_use--;
5523                 reg_val &= ~(bit1 << uta_shift);
5524                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5525         }
5526
5527         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5528
5529         if (uta_info->uta_in_use > 0)
5530                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5531                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5532         else
5533                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5534
5535         return 0;
5536 }
5537
5538 static int
5539 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5540 {
5541         int i;
5542         struct ixgbe_hw *hw =
5543                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5544         struct ixgbe_uta_info *uta_info =
5545                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5546
5547         /* The UTA table only exists on 82599 hardware and newer */
5548         if (hw->mac.type < ixgbe_mac_82599EB)
5549                 return -ENOTSUP;
5550
5551         if (on) {
5552                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5553                         uta_info->uta_shadow[i] = ~0;
5554                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5555                 }
5556         } else {
5557                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5558                         uta_info->uta_shadow[i] = 0;
5559                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5560                 }
5561         }
5562         return 0;
5563
5564 }
5565
5566 uint32_t
5567 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5568 {
5569         uint32_t new_val = orig_val;
5570
5571         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5572                 new_val |= IXGBE_VMOLR_AUPE;
5573         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5574                 new_val |= IXGBE_VMOLR_ROMPE;
5575         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5576                 new_val |= IXGBE_VMOLR_ROPE;
5577         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5578                 new_val |= IXGBE_VMOLR_BAM;
5579         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5580                 new_val |= IXGBE_VMOLR_MPE;
5581
5582         return new_val;
5583 }
5584
5585 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5586 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5587 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5588 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5589 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5590         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5591         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5592
5593 static int
5594 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5595                       struct rte_eth_mirror_conf *mirror_conf,
5596                       uint8_t rule_id, uint8_t on)
5597 {
5598         uint32_t mr_ctl, vlvf;
5599         uint32_t mp_lsb = 0;
5600         uint32_t mv_msb = 0;
5601         uint32_t mv_lsb = 0;
5602         uint32_t mp_msb = 0;
5603         uint8_t i = 0;
5604         int reg_index = 0;
5605         uint64_t vlan_mask = 0;
5606
5607         const uint8_t pool_mask_offset = 32;
5608         const uint8_t vlan_mask_offset = 32;
5609         const uint8_t dst_pool_offset = 8;
5610         const uint8_t rule_mr_offset  = 4;
5611         const uint8_t mirror_rule_mask = 0x0F;
5612
5613         struct ixgbe_mirror_info *mr_info =
5614                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5615         struct ixgbe_hw *hw =
5616                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5617         uint8_t mirror_type = 0;
5618
5619         if (ixgbe_vt_check(hw) < 0)
5620                 return -ENOTSUP;
5621
5622         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5623                 return -EINVAL;
5624
5625         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5626                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5627                             mirror_conf->rule_type);
5628                 return -EINVAL;
5629         }
5630
5631         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5632                 mirror_type |= IXGBE_MRCTL_VLME;
5633                 /* Check if vlan id is valid and find conresponding VLAN ID
5634                  * index in VLVF
5635                  */
5636                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5637                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5638                                 /* search vlan id related pool vlan filter
5639                                  * index
5640                                  */
5641                                 reg_index = ixgbe_find_vlvf_slot(
5642                                                 hw,
5643                                                 mirror_conf->vlan.vlan_id[i],
5644                                                 false);
5645                                 if (reg_index < 0)
5646                                         return -EINVAL;
5647                                 vlvf = IXGBE_READ_REG(hw,
5648                                                       IXGBE_VLVF(reg_index));
5649                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5650                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5651                                       mirror_conf->vlan.vlan_id[i]))
5652                                         vlan_mask |= (1ULL << reg_index);
5653                                 else
5654                                         return -EINVAL;
5655                         }
5656                 }
5657
5658                 if (on) {
5659                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5660                         mv_msb = vlan_mask >> vlan_mask_offset;
5661
5662                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5663                                                 mirror_conf->vlan.vlan_mask;
5664                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5665                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5666                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5667                                                 mirror_conf->vlan.vlan_id[i];
5668                         }
5669                 } else {
5670                         mv_lsb = 0;
5671                         mv_msb = 0;
5672                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5673                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5674                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5675                 }
5676         }
5677
5678         /**
5679          * if enable pool mirror, write related pool mask register,if disable
5680          * pool mirror, clear PFMRVM register
5681          */
5682         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5683                 mirror_type |= IXGBE_MRCTL_VPME;
5684                 if (on) {
5685                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5686                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5687                         mr_info->mr_conf[rule_id].pool_mask =
5688                                         mirror_conf->pool_mask;
5689
5690                 } else {
5691                         mp_lsb = 0;
5692                         mp_msb = 0;
5693                         mr_info->mr_conf[rule_id].pool_mask = 0;
5694                 }
5695         }
5696         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5697                 mirror_type |= IXGBE_MRCTL_UPME;
5698         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5699                 mirror_type |= IXGBE_MRCTL_DPME;
5700
5701         /* read  mirror control register and recalculate it */
5702         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5703
5704         if (on) {
5705                 mr_ctl |= mirror_type;
5706                 mr_ctl &= mirror_rule_mask;
5707                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5708         } else {
5709                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5710         }
5711
5712         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5713         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5714
5715         /* write mirrror control  register */
5716         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5717
5718         /* write pool mirrror control  register */
5719         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5720                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5721                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5722                                 mp_msb);
5723         }
5724         /* write VLAN mirrror control  register */
5725         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5726                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5727                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5728                                 mv_msb);
5729         }
5730
5731         return 0;
5732 }
5733
5734 static int
5735 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5736 {
5737         int mr_ctl = 0;
5738         uint32_t lsb_val = 0;
5739         uint32_t msb_val = 0;
5740         const uint8_t rule_mr_offset = 4;
5741
5742         struct ixgbe_hw *hw =
5743                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5744         struct ixgbe_mirror_info *mr_info =
5745                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5746
5747         if (ixgbe_vt_check(hw) < 0)
5748                 return -ENOTSUP;
5749
5750         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5751                 return -EINVAL;
5752
5753         memset(&mr_info->mr_conf[rule_id], 0,
5754                sizeof(struct rte_eth_mirror_conf));
5755
5756         /* clear PFVMCTL register */
5757         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5758
5759         /* clear pool mask register */
5760         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5761         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5762
5763         /* clear vlan mask register */
5764         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5765         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5766
5767         return 0;
5768 }
5769
5770 static int
5771 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5772 {
5773         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5774         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5775         struct ixgbe_interrupt *intr =
5776                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5777         struct ixgbe_hw *hw =
5778                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5779         uint32_t vec = IXGBE_MISC_VEC_ID;
5780
5781         if (rte_intr_allow_others(intr_handle))
5782                 vec = IXGBE_RX_VEC_START;
5783         intr->mask |= (1 << vec);
5784         RTE_SET_USED(queue_id);
5785         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5786
5787         rte_intr_ack(intr_handle);
5788
5789         return 0;
5790 }
5791
5792 static int
5793 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5794 {
5795         struct ixgbe_interrupt *intr =
5796                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5797         struct ixgbe_hw *hw =
5798                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5799         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5800         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5801         uint32_t vec = IXGBE_MISC_VEC_ID;
5802
5803         if (rte_intr_allow_others(intr_handle))
5804                 vec = IXGBE_RX_VEC_START;
5805         intr->mask &= ~(1 << vec);
5806         RTE_SET_USED(queue_id);
5807         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5808
5809         return 0;
5810 }
5811
5812 static int
5813 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5814 {
5815         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5816         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5817         uint32_t mask;
5818         struct ixgbe_hw *hw =
5819                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5820         struct ixgbe_interrupt *intr =
5821                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5822
5823         if (queue_id < 16) {
5824                 ixgbe_disable_intr(hw);
5825                 intr->mask |= (1 << queue_id);
5826                 ixgbe_enable_intr(dev);
5827         } else if (queue_id < 32) {
5828                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5829                 mask &= (1 << queue_id);
5830                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5831         } else if (queue_id < 64) {
5832                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5833                 mask &= (1 << (queue_id - 32));
5834                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5835         }
5836         rte_intr_ack(intr_handle);
5837
5838         return 0;
5839 }
5840
5841 static int
5842 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5843 {
5844         uint32_t mask;
5845         struct ixgbe_hw *hw =
5846                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5847         struct ixgbe_interrupt *intr =
5848                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5849
5850         if (queue_id < 16) {
5851                 ixgbe_disable_intr(hw);
5852                 intr->mask &= ~(1 << queue_id);
5853                 ixgbe_enable_intr(dev);
5854         } else if (queue_id < 32) {
5855                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5856                 mask &= ~(1 << queue_id);
5857                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5858         } else if (queue_id < 64) {
5859                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5860                 mask &= ~(1 << (queue_id - 32));
5861                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5862         }
5863
5864         return 0;
5865 }
5866
5867 static void
5868 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5869                      uint8_t queue, uint8_t msix_vector)
5870 {
5871         uint32_t tmp, idx;
5872
5873         if (direction == -1) {
5874                 /* other causes */
5875                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5876                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5877                 tmp &= ~0xFF;
5878                 tmp |= msix_vector;
5879                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5880         } else {
5881                 /* rx or tx cause */
5882                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5883                 idx = ((16 * (queue & 1)) + (8 * direction));
5884                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5885                 tmp &= ~(0xFF << idx);
5886                 tmp |= (msix_vector << idx);
5887                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5888         }
5889 }
5890
5891 /**
5892  * set the IVAR registers, mapping interrupt causes to vectors
5893  * @param hw
5894  *  pointer to ixgbe_hw struct
5895  * @direction
5896  *  0 for Rx, 1 for Tx, -1 for other causes
5897  * @queue
5898  *  queue to map the corresponding interrupt to
5899  * @msix_vector
5900  *  the vector to map to the corresponding queue
5901  */
5902 static void
5903 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5904                    uint8_t queue, uint8_t msix_vector)
5905 {
5906         uint32_t tmp, idx;
5907
5908         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5909         if (hw->mac.type == ixgbe_mac_82598EB) {
5910                 if (direction == -1)
5911                         direction = 0;
5912                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5913                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5914                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5915                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5916                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5917         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5918                         (hw->mac.type == ixgbe_mac_X540) ||
5919                         (hw->mac.type == ixgbe_mac_X550) ||
5920                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
5921                 if (direction == -1) {
5922                         /* other causes */
5923                         idx = ((queue & 1) * 8);
5924                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5925                         tmp &= ~(0xFF << idx);
5926                         tmp |= (msix_vector << idx);
5927                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5928                 } else {
5929                         /* rx or tx causes */
5930                         idx = ((16 * (queue & 1)) + (8 * direction));
5931                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5932                         tmp &= ~(0xFF << idx);
5933                         tmp |= (msix_vector << idx);
5934                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5935                 }
5936         }
5937 }
5938
5939 static void
5940 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5941 {
5942         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5943         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5944         struct ixgbe_hw *hw =
5945                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5946         uint32_t q_idx;
5947         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5948         uint32_t base = IXGBE_MISC_VEC_ID;
5949
5950         /* Configure VF other cause ivar */
5951         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5952
5953         /* won't configure msix register if no mapping is done
5954          * between intr vector and event fd.
5955          */
5956         if (!rte_intr_dp_is_en(intr_handle))
5957                 return;
5958
5959         if (rte_intr_allow_others(intr_handle)) {
5960                 base = IXGBE_RX_VEC_START;
5961                 vector_idx = IXGBE_RX_VEC_START;
5962         }
5963
5964         /* Configure all RX queues of VF */
5965         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5966                 /* Force all queue use vector 0,
5967                  * as IXGBE_VF_MAXMSIVECOTR = 1
5968                  */
5969                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5970                 intr_handle->intr_vec[q_idx] = vector_idx;
5971                 if (vector_idx < base + intr_handle->nb_efd - 1)
5972                         vector_idx++;
5973         }
5974
5975         /* As RX queue setting above show, all queues use the vector 0.
5976          * Set only the ITR value of IXGBE_MISC_VEC_ID.
5977          */
5978         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5979                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5980                         | IXGBE_EITR_CNT_WDIS);
5981 }
5982
5983 /**
5984  * Sets up the hardware to properly generate MSI-X interrupts
5985  * @hw
5986  *  board private structure
5987  */
5988 static void
5989 ixgbe_configure_msix(struct rte_eth_dev *dev)
5990 {
5991         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5992         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5993         struct ixgbe_hw *hw =
5994                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5995         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5996         uint32_t vec = IXGBE_MISC_VEC_ID;
5997         uint32_t mask;
5998         uint32_t gpie;
5999
6000         /* won't configure msix register if no mapping is done
6001          * between intr vector and event fd
6002          * but if misx has been enabled already, need to configure
6003          * auto clean, auto mask and throttling.
6004          */
6005         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6006         if (!rte_intr_dp_is_en(intr_handle) &&
6007             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6008                 return;
6009
6010         if (rte_intr_allow_others(intr_handle))
6011                 vec = base = IXGBE_RX_VEC_START;
6012
6013         /* setup GPIE for MSI-x mode */
6014         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6015         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6016                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6017         /* auto clearing and auto setting corresponding bits in EIMS
6018          * when MSI-X interrupt is triggered
6019          */
6020         if (hw->mac.type == ixgbe_mac_82598EB) {
6021                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6022         } else {
6023                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6024                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6025         }
6026         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6027
6028         /* Populate the IVAR table and set the ITR values to the
6029          * corresponding register.
6030          */
6031         if (rte_intr_dp_is_en(intr_handle)) {
6032                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6033                         queue_id++) {
6034                         /* by default, 1:1 mapping */
6035                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6036                         intr_handle->intr_vec[queue_id] = vec;
6037                         if (vec < base + intr_handle->nb_efd - 1)
6038                                 vec++;
6039                 }
6040
6041                 switch (hw->mac.type) {
6042                 case ixgbe_mac_82598EB:
6043                         ixgbe_set_ivar_map(hw, -1,
6044                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6045                                            IXGBE_MISC_VEC_ID);
6046                         break;
6047                 case ixgbe_mac_82599EB:
6048                 case ixgbe_mac_X540:
6049                 case ixgbe_mac_X550:
6050                 case ixgbe_mac_X550EM_x:
6051                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6052                         break;
6053                 default:
6054                         break;
6055                 }
6056         }
6057         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6058                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6059                         | IXGBE_EITR_CNT_WDIS);
6060
6061         /* set up to autoclear timer, and the vectors */
6062         mask = IXGBE_EIMS_ENABLE_MASK;
6063         mask &= ~(IXGBE_EIMS_OTHER |
6064                   IXGBE_EIMS_MAILBOX |
6065                   IXGBE_EIMS_LSC);
6066
6067         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6068 }
6069
6070 int
6071 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6072                            uint16_t queue_idx, uint16_t tx_rate)
6073 {
6074         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6075         struct rte_eth_rxmode *rxmode;
6076         uint32_t rf_dec, rf_int;
6077         uint32_t bcnrc_val;
6078         uint16_t link_speed = dev->data->dev_link.link_speed;
6079
6080         if (queue_idx >= hw->mac.max_tx_queues)
6081                 return -EINVAL;
6082
6083         if (tx_rate != 0) {
6084                 /* Calculate the rate factor values to set */
6085                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6086                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6087                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6088
6089                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6090                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6091                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6092                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6093         } else {
6094                 bcnrc_val = 0;
6095         }
6096
6097         rxmode = &dev->data->dev_conf.rxmode;
6098         /*
6099          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6100          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6101          * set as 0x4.
6102          */
6103         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6104             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6105                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6106                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6107         else
6108                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6109                         IXGBE_MMW_SIZE_DEFAULT);
6110
6111         /* Set RTTBCNRC of queue X */
6112         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6113         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6114         IXGBE_WRITE_FLUSH(hw);
6115
6116         return 0;
6117 }
6118
6119 static int
6120 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6121                      __attribute__((unused)) uint32_t index,
6122                      __attribute__((unused)) uint32_t pool)
6123 {
6124         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6125         int diag;
6126
6127         /*
6128          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6129          * operation. Trap this case to avoid exhausting the [very limited]
6130          * set of PF resources used to store VF MAC addresses.
6131          */
6132         if (memcmp(hw->mac.perm_addr, mac_addr,
6133                         sizeof(struct rte_ether_addr)) == 0)
6134                 return -1;
6135         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6136         if (diag != 0)
6137                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6138                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6139                             mac_addr->addr_bytes[0],
6140                             mac_addr->addr_bytes[1],
6141                             mac_addr->addr_bytes[2],
6142                             mac_addr->addr_bytes[3],
6143                             mac_addr->addr_bytes[4],
6144                             mac_addr->addr_bytes[5],
6145                             diag);
6146         return diag;
6147 }
6148
6149 static void
6150 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6151 {
6152         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6153         struct rte_ether_addr *perm_addr =
6154                 (struct rte_ether_addr *)hw->mac.perm_addr;
6155         struct rte_ether_addr *mac_addr;
6156         uint32_t i;
6157         int diag;
6158
6159         /*
6160          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6161          * not support the deletion of a given MAC address.
6162          * Instead, it imposes to delete all MAC addresses, then to add again
6163          * all MAC addresses with the exception of the one to be deleted.
6164          */
6165         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6166
6167         /*
6168          * Add again all MAC addresses, with the exception of the deleted one
6169          * and of the permanent MAC address.
6170          */
6171         for (i = 0, mac_addr = dev->data->mac_addrs;
6172              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6173                 /* Skip the deleted MAC address */
6174                 if (i == index)
6175                         continue;
6176                 /* Skip NULL MAC addresses */
6177                 if (rte_is_zero_ether_addr(mac_addr))
6178                         continue;
6179                 /* Skip the permanent MAC address */
6180                 if (memcmp(perm_addr, mac_addr,
6181                                 sizeof(struct rte_ether_addr)) == 0)
6182                         continue;
6183                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6184                 if (diag != 0)
6185                         PMD_DRV_LOG(ERR,
6186                                     "Adding again MAC address "
6187                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6188                                     "diag=%d",
6189                                     mac_addr->addr_bytes[0],
6190                                     mac_addr->addr_bytes[1],
6191                                     mac_addr->addr_bytes[2],
6192                                     mac_addr->addr_bytes[3],
6193                                     mac_addr->addr_bytes[4],
6194                                     mac_addr->addr_bytes[5],
6195                                     diag);
6196         }
6197 }
6198
6199 static int
6200 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6201                         struct rte_ether_addr *addr)
6202 {
6203         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6204
6205         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6206
6207         return 0;
6208 }
6209
6210 int
6211 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6212                         struct rte_eth_syn_filter *filter,
6213                         bool add)
6214 {
6215         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6216         struct ixgbe_filter_info *filter_info =
6217                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6218         uint32_t syn_info;
6219         uint32_t synqf;
6220
6221         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6222                 return -EINVAL;
6223
6224         syn_info = filter_info->syn_info;
6225
6226         if (add) {
6227                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6228                         return -EINVAL;
6229                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6230                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6231
6232                 if (filter->hig_pri)
6233                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6234                 else
6235                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6236         } else {
6237                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6238                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6239                         return -ENOENT;
6240                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6241         }
6242
6243         filter_info->syn_info = synqf;
6244         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6245         IXGBE_WRITE_FLUSH(hw);
6246         return 0;
6247 }
6248
6249 static int
6250 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6251                         struct rte_eth_syn_filter *filter)
6252 {
6253         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6254         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6255
6256         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6257                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6258                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6259                 return 0;
6260         }
6261         return -ENOENT;
6262 }
6263
6264 static int
6265 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6266                         enum rte_filter_op filter_op,
6267                         void *arg)
6268 {
6269         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6270         int ret;
6271
6272         MAC_TYPE_FILTER_SUP(hw->mac.type);
6273
6274         if (filter_op == RTE_ETH_FILTER_NOP)
6275                 return 0;
6276
6277         if (arg == NULL) {
6278                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6279                             filter_op);
6280                 return -EINVAL;
6281         }
6282
6283         switch (filter_op) {
6284         case RTE_ETH_FILTER_ADD:
6285                 ret = ixgbe_syn_filter_set(dev,
6286                                 (struct rte_eth_syn_filter *)arg,
6287                                 TRUE);
6288                 break;
6289         case RTE_ETH_FILTER_DELETE:
6290                 ret = ixgbe_syn_filter_set(dev,
6291                                 (struct rte_eth_syn_filter *)arg,
6292                                 FALSE);
6293                 break;
6294         case RTE_ETH_FILTER_GET:
6295                 ret = ixgbe_syn_filter_get(dev,
6296                                 (struct rte_eth_syn_filter *)arg);
6297                 break;
6298         default:
6299                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6300                 ret = -EINVAL;
6301                 break;
6302         }
6303
6304         return ret;
6305 }
6306
6307
6308 static inline enum ixgbe_5tuple_protocol
6309 convert_protocol_type(uint8_t protocol_value)
6310 {
6311         if (protocol_value == IPPROTO_TCP)
6312                 return IXGBE_FILTER_PROTOCOL_TCP;
6313         else if (protocol_value == IPPROTO_UDP)
6314                 return IXGBE_FILTER_PROTOCOL_UDP;
6315         else if (protocol_value == IPPROTO_SCTP)
6316                 return IXGBE_FILTER_PROTOCOL_SCTP;
6317         else
6318                 return IXGBE_FILTER_PROTOCOL_NONE;
6319 }
6320
6321 /* inject a 5-tuple filter to HW */
6322 static inline void
6323 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6324                            struct ixgbe_5tuple_filter *filter)
6325 {
6326         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6327         int i;
6328         uint32_t ftqf, sdpqf;
6329         uint32_t l34timir = 0;
6330         uint8_t mask = 0xff;
6331
6332         i = filter->index;
6333
6334         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6335                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6336         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6337
6338         ftqf = (uint32_t)(filter->filter_info.proto &
6339                 IXGBE_FTQF_PROTOCOL_MASK);
6340         ftqf |= (uint32_t)((filter->filter_info.priority &
6341                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6342         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6343                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6344         if (filter->filter_info.dst_ip_mask == 0)
6345                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6346         if (filter->filter_info.src_port_mask == 0)
6347                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6348         if (filter->filter_info.dst_port_mask == 0)
6349                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6350         if (filter->filter_info.proto_mask == 0)
6351                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6352         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6353         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6354         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6355
6356         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6357         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6358         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6359         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6360
6361         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6362         l34timir |= (uint32_t)(filter->queue <<
6363                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6364         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6365 }
6366
6367 /*
6368  * add a 5tuple filter
6369  *
6370  * @param
6371  * dev: Pointer to struct rte_eth_dev.
6372  * index: the index the filter allocates.
6373  * filter: ponter to the filter that will be added.
6374  * rx_queue: the queue id the filter assigned to.
6375  *
6376  * @return
6377  *    - On success, zero.
6378  *    - On failure, a negative value.
6379  */
6380 static int
6381 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6382                         struct ixgbe_5tuple_filter *filter)
6383 {
6384         struct ixgbe_filter_info *filter_info =
6385                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6386         int i, idx, shift;
6387
6388         /*
6389          * look for an unused 5tuple filter index,
6390          * and insert the filter to list.
6391          */
6392         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6393                 idx = i / (sizeof(uint32_t) * NBBY);
6394                 shift = i % (sizeof(uint32_t) * NBBY);
6395                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6396                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6397                         filter->index = i;
6398                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6399                                           filter,
6400                                           entries);
6401                         break;
6402                 }
6403         }
6404         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6405                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6406                 return -ENOSYS;
6407         }
6408
6409         ixgbe_inject_5tuple_filter(dev, filter);
6410
6411         return 0;
6412 }
6413
6414 /*
6415  * remove a 5tuple filter
6416  *
6417  * @param
6418  * dev: Pointer to struct rte_eth_dev.
6419  * filter: the pointer of the filter will be removed.
6420  */
6421 static void
6422 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6423                         struct ixgbe_5tuple_filter *filter)
6424 {
6425         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6426         struct ixgbe_filter_info *filter_info =
6427                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6428         uint16_t index = filter->index;
6429
6430         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6431                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6432         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6433         rte_free(filter);
6434
6435         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6436         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6437         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6438         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6439         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6440 }
6441
6442 static int
6443 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6444 {
6445         struct ixgbe_hw *hw;
6446         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6447         struct rte_eth_dev_data *dev_data = dev->data;
6448
6449         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6450
6451         if (mtu < RTE_ETHER_MIN_MTU ||
6452                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6453                 return -EINVAL;
6454
6455         /* If device is started, refuse mtu that requires the support of
6456          * scattered packets when this feature has not been enabled before.
6457          */
6458         if (dev_data->dev_started && !dev_data->scattered_rx &&
6459             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6460              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6461                 PMD_INIT_LOG(ERR, "Stop port first.");
6462                 return -EINVAL;
6463         }
6464
6465         /*
6466          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6467          * request of the version 2.0 of the mailbox API.
6468          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6469          * of the mailbox API.
6470          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6471          * prior to 3.11.33 which contains the following change:
6472          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6473          */
6474         ixgbevf_rlpml_set_vf(hw, max_frame);
6475
6476         /* update max frame size */
6477         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6478         return 0;
6479 }
6480
6481 static inline struct ixgbe_5tuple_filter *
6482 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6483                         struct ixgbe_5tuple_filter_info *key)
6484 {
6485         struct ixgbe_5tuple_filter *it;
6486
6487         TAILQ_FOREACH(it, filter_list, entries) {
6488                 if (memcmp(key, &it->filter_info,
6489                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6490                         return it;
6491                 }
6492         }
6493         return NULL;
6494 }
6495
6496 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6497 static inline int
6498 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6499                         struct ixgbe_5tuple_filter_info *filter_info)
6500 {
6501         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6502                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6503                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6504                 return -EINVAL;
6505
6506         switch (filter->dst_ip_mask) {
6507         case UINT32_MAX:
6508                 filter_info->dst_ip_mask = 0;
6509                 filter_info->dst_ip = filter->dst_ip;
6510                 break;
6511         case 0:
6512                 filter_info->dst_ip_mask = 1;
6513                 break;
6514         default:
6515                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6516                 return -EINVAL;
6517         }
6518
6519         switch (filter->src_ip_mask) {
6520         case UINT32_MAX:
6521                 filter_info->src_ip_mask = 0;
6522                 filter_info->src_ip = filter->src_ip;
6523                 break;
6524         case 0:
6525                 filter_info->src_ip_mask = 1;
6526                 break;
6527         default:
6528                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6529                 return -EINVAL;
6530         }
6531
6532         switch (filter->dst_port_mask) {
6533         case UINT16_MAX:
6534                 filter_info->dst_port_mask = 0;
6535                 filter_info->dst_port = filter->dst_port;
6536                 break;
6537         case 0:
6538                 filter_info->dst_port_mask = 1;
6539                 break;
6540         default:
6541                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6542                 return -EINVAL;
6543         }
6544
6545         switch (filter->src_port_mask) {
6546         case UINT16_MAX:
6547                 filter_info->src_port_mask = 0;
6548                 filter_info->src_port = filter->src_port;
6549                 break;
6550         case 0:
6551                 filter_info->src_port_mask = 1;
6552                 break;
6553         default:
6554                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6555                 return -EINVAL;
6556         }
6557
6558         switch (filter->proto_mask) {
6559         case UINT8_MAX:
6560                 filter_info->proto_mask = 0;
6561                 filter_info->proto =
6562                         convert_protocol_type(filter->proto);
6563                 break;
6564         case 0:
6565                 filter_info->proto_mask = 1;
6566                 break;
6567         default:
6568                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6569                 return -EINVAL;
6570         }
6571
6572         filter_info->priority = (uint8_t)filter->priority;
6573         return 0;
6574 }
6575
6576 /*
6577  * add or delete a ntuple filter
6578  *
6579  * @param
6580  * dev: Pointer to struct rte_eth_dev.
6581  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6582  * add: if true, add filter, if false, remove filter
6583  *
6584  * @return
6585  *    - On success, zero.
6586  *    - On failure, a negative value.
6587  */
6588 int
6589 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6590                         struct rte_eth_ntuple_filter *ntuple_filter,
6591                         bool add)
6592 {
6593         struct ixgbe_filter_info *filter_info =
6594                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6595         struct ixgbe_5tuple_filter_info filter_5tuple;
6596         struct ixgbe_5tuple_filter *filter;
6597         int ret;
6598
6599         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6600                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6601                 return -EINVAL;
6602         }
6603
6604         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6605         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6606         if (ret < 0)
6607                 return ret;
6608
6609         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6610                                          &filter_5tuple);
6611         if (filter != NULL && add) {
6612                 PMD_DRV_LOG(ERR, "filter exists.");
6613                 return -EEXIST;
6614         }
6615         if (filter == NULL && !add) {
6616                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6617                 return -ENOENT;
6618         }
6619
6620         if (add) {
6621                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6622                                 sizeof(struct ixgbe_5tuple_filter), 0);
6623                 if (filter == NULL)
6624                         return -ENOMEM;
6625                 rte_memcpy(&filter->filter_info,
6626                                  &filter_5tuple,
6627                                  sizeof(struct ixgbe_5tuple_filter_info));
6628                 filter->queue = ntuple_filter->queue;
6629                 ret = ixgbe_add_5tuple_filter(dev, filter);
6630                 if (ret < 0) {
6631                         rte_free(filter);
6632                         return ret;
6633                 }
6634         } else
6635                 ixgbe_remove_5tuple_filter(dev, filter);
6636
6637         return 0;
6638 }
6639
6640 /*
6641  * get a ntuple filter
6642  *
6643  * @param
6644  * dev: Pointer to struct rte_eth_dev.
6645  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6646  *
6647  * @return
6648  *    - On success, zero.
6649  *    - On failure, a negative value.
6650  */
6651 static int
6652 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6653                         struct rte_eth_ntuple_filter *ntuple_filter)
6654 {
6655         struct ixgbe_filter_info *filter_info =
6656                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6657         struct ixgbe_5tuple_filter_info filter_5tuple;
6658         struct ixgbe_5tuple_filter *filter;
6659         int ret;
6660
6661         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6662                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6663                 return -EINVAL;
6664         }
6665
6666         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6667         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6668         if (ret < 0)
6669                 return ret;
6670
6671         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6672                                          &filter_5tuple);
6673         if (filter == NULL) {
6674                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6675                 return -ENOENT;
6676         }
6677         ntuple_filter->queue = filter->queue;
6678         return 0;
6679 }
6680
6681 /*
6682  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6683  * @dev: pointer to rte_eth_dev structure
6684  * @filter_op:operation will be taken.
6685  * @arg: a pointer to specific structure corresponding to the filter_op
6686  *
6687  * @return
6688  *    - On success, zero.
6689  *    - On failure, a negative value.
6690  */
6691 static int
6692 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6693                                 enum rte_filter_op filter_op,
6694                                 void *arg)
6695 {
6696         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6697         int ret;
6698
6699         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6700
6701         if (filter_op == RTE_ETH_FILTER_NOP)
6702                 return 0;
6703
6704         if (arg == NULL) {
6705                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6706                             filter_op);
6707                 return -EINVAL;
6708         }
6709
6710         switch (filter_op) {
6711         case RTE_ETH_FILTER_ADD:
6712                 ret = ixgbe_add_del_ntuple_filter(dev,
6713                         (struct rte_eth_ntuple_filter *)arg,
6714                         TRUE);
6715                 break;
6716         case RTE_ETH_FILTER_DELETE:
6717                 ret = ixgbe_add_del_ntuple_filter(dev,
6718                         (struct rte_eth_ntuple_filter *)arg,
6719                         FALSE);
6720                 break;
6721         case RTE_ETH_FILTER_GET:
6722                 ret = ixgbe_get_ntuple_filter(dev,
6723                         (struct rte_eth_ntuple_filter *)arg);
6724                 break;
6725         default:
6726                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6727                 ret = -EINVAL;
6728                 break;
6729         }
6730         return ret;
6731 }
6732
6733 int
6734 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6735                         struct rte_eth_ethertype_filter *filter,
6736                         bool add)
6737 {
6738         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6739         struct ixgbe_filter_info *filter_info =
6740                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6741         uint32_t etqf = 0;
6742         uint32_t etqs = 0;
6743         int ret;
6744         struct ixgbe_ethertype_filter ethertype_filter;
6745
6746         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6747                 return -EINVAL;
6748
6749         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6750                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6751                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6752                         " ethertype filter.", filter->ether_type);
6753                 return -EINVAL;
6754         }
6755
6756         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6757                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6758                 return -EINVAL;
6759         }
6760         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6761                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6762                 return -EINVAL;
6763         }
6764
6765         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6766         if (ret >= 0 && add) {
6767                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6768                             filter->ether_type);
6769                 return -EEXIST;
6770         }
6771         if (ret < 0 && !add) {
6772                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6773                             filter->ether_type);
6774                 return -ENOENT;
6775         }
6776
6777         if (add) {
6778                 etqf = IXGBE_ETQF_FILTER_EN;
6779                 etqf |= (uint32_t)filter->ether_type;
6780                 etqs |= (uint32_t)((filter->queue <<
6781                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6782                                     IXGBE_ETQS_RX_QUEUE);
6783                 etqs |= IXGBE_ETQS_QUEUE_EN;
6784
6785                 ethertype_filter.ethertype = filter->ether_type;
6786                 ethertype_filter.etqf = etqf;
6787                 ethertype_filter.etqs = etqs;
6788                 ethertype_filter.conf = FALSE;
6789                 ret = ixgbe_ethertype_filter_insert(filter_info,
6790                                                     &ethertype_filter);
6791                 if (ret < 0) {
6792                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6793                         return -ENOSPC;
6794                 }
6795         } else {
6796                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6797                 if (ret < 0)
6798                         return -ENOSYS;
6799         }
6800         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6801         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6802         IXGBE_WRITE_FLUSH(hw);
6803
6804         return 0;
6805 }
6806
6807 static int
6808 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6809                         struct rte_eth_ethertype_filter *filter)
6810 {
6811         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6812         struct ixgbe_filter_info *filter_info =
6813                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6814         uint32_t etqf, etqs;
6815         int ret;
6816
6817         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6818         if (ret < 0) {
6819                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6820                             filter->ether_type);
6821                 return -ENOENT;
6822         }
6823
6824         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6825         if (etqf & IXGBE_ETQF_FILTER_EN) {
6826                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6827                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6828                 filter->flags = 0;
6829                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6830                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6831                 return 0;
6832         }
6833         return -ENOENT;
6834 }
6835
6836 /*
6837  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6838  * @dev: pointer to rte_eth_dev structure
6839  * @filter_op:operation will be taken.
6840  * @arg: a pointer to specific structure corresponding to the filter_op
6841  */
6842 static int
6843 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6844                                 enum rte_filter_op filter_op,
6845                                 void *arg)
6846 {
6847         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6848         int ret;
6849
6850         MAC_TYPE_FILTER_SUP(hw->mac.type);
6851
6852         if (filter_op == RTE_ETH_FILTER_NOP)
6853                 return 0;
6854
6855         if (arg == NULL) {
6856                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6857                             filter_op);
6858                 return -EINVAL;
6859         }
6860
6861         switch (filter_op) {
6862         case RTE_ETH_FILTER_ADD:
6863                 ret = ixgbe_add_del_ethertype_filter(dev,
6864                         (struct rte_eth_ethertype_filter *)arg,
6865                         TRUE);
6866                 break;
6867         case RTE_ETH_FILTER_DELETE:
6868                 ret = ixgbe_add_del_ethertype_filter(dev,
6869                         (struct rte_eth_ethertype_filter *)arg,
6870                         FALSE);
6871                 break;
6872         case RTE_ETH_FILTER_GET:
6873                 ret = ixgbe_get_ethertype_filter(dev,
6874                         (struct rte_eth_ethertype_filter *)arg);
6875                 break;
6876         default:
6877                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6878                 ret = -EINVAL;
6879                 break;
6880         }
6881         return ret;
6882 }
6883
6884 static int
6885 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6886                      enum rte_filter_type filter_type,
6887                      enum rte_filter_op filter_op,
6888                      void *arg)
6889 {
6890         int ret = 0;
6891
6892         switch (filter_type) {
6893         case RTE_ETH_FILTER_NTUPLE:
6894                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6895                 break;
6896         case RTE_ETH_FILTER_ETHERTYPE:
6897                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6898                 break;
6899         case RTE_ETH_FILTER_SYN:
6900                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6901                 break;
6902         case RTE_ETH_FILTER_FDIR:
6903                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6904                 break;
6905         case RTE_ETH_FILTER_L2_TUNNEL:
6906                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6907                 break;
6908         case RTE_ETH_FILTER_GENERIC:
6909                 if (filter_op != RTE_ETH_FILTER_GET)
6910                         return -EINVAL;
6911                 *(const void **)arg = &ixgbe_flow_ops;
6912                 break;
6913         default:
6914                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6915                                                         filter_type);
6916                 ret = -EINVAL;
6917                 break;
6918         }
6919
6920         return ret;
6921 }
6922
6923 static u8 *
6924 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6925                         u8 **mc_addr_ptr, u32 *vmdq)
6926 {
6927         u8 *mc_addr;
6928
6929         *vmdq = 0;
6930         mc_addr = *mc_addr_ptr;
6931         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6932         return mc_addr;
6933 }
6934
6935 static int
6936 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6937                           struct rte_ether_addr *mc_addr_set,
6938                           uint32_t nb_mc_addr)
6939 {
6940         struct ixgbe_hw *hw;
6941         u8 *mc_addr_list;
6942
6943         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6944         mc_addr_list = (u8 *)mc_addr_set;
6945         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6946                                          ixgbe_dev_addr_list_itr, TRUE);
6947 }
6948
6949 static uint64_t
6950 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6951 {
6952         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6953         uint64_t systime_cycles;
6954
6955         switch (hw->mac.type) {
6956         case ixgbe_mac_X550:
6957         case ixgbe_mac_X550EM_x:
6958         case ixgbe_mac_X550EM_a:
6959                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6960                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6961                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6962                                 * NSEC_PER_SEC;
6963                 break;
6964         default:
6965                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6966                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6967                                 << 32;
6968         }
6969
6970         return systime_cycles;
6971 }
6972
6973 static uint64_t
6974 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6975 {
6976         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6977         uint64_t rx_tstamp_cycles;
6978
6979         switch (hw->mac.type) {
6980         case ixgbe_mac_X550:
6981         case ixgbe_mac_X550EM_x:
6982         case ixgbe_mac_X550EM_a:
6983                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6984                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6985                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6986                                 * NSEC_PER_SEC;
6987                 break;
6988         default:
6989                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6990                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6991                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6992                                 << 32;
6993         }
6994
6995         return rx_tstamp_cycles;
6996 }
6997
6998 static uint64_t
6999 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7000 {
7001         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7002         uint64_t tx_tstamp_cycles;
7003
7004         switch (hw->mac.type) {
7005         case ixgbe_mac_X550:
7006         case ixgbe_mac_X550EM_x:
7007         case ixgbe_mac_X550EM_a:
7008                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7009                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7010                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7011                                 * NSEC_PER_SEC;
7012                 break;
7013         default:
7014                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7015                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7016                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7017                                 << 32;
7018         }
7019
7020         return tx_tstamp_cycles;
7021 }
7022
7023 static void
7024 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7025 {
7026         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7027         struct ixgbe_adapter *adapter = dev->data->dev_private;
7028         struct rte_eth_link link;
7029         uint32_t incval = 0;
7030         uint32_t shift = 0;
7031
7032         /* Get current link speed. */
7033         ixgbe_dev_link_update(dev, 1);
7034         rte_eth_linkstatus_get(dev, &link);
7035
7036         switch (link.link_speed) {
7037         case ETH_SPEED_NUM_100M:
7038                 incval = IXGBE_INCVAL_100;
7039                 shift = IXGBE_INCVAL_SHIFT_100;
7040                 break;
7041         case ETH_SPEED_NUM_1G:
7042                 incval = IXGBE_INCVAL_1GB;
7043                 shift = IXGBE_INCVAL_SHIFT_1GB;
7044                 break;
7045         case ETH_SPEED_NUM_10G:
7046         default:
7047                 incval = IXGBE_INCVAL_10GB;
7048                 shift = IXGBE_INCVAL_SHIFT_10GB;
7049                 break;
7050         }
7051
7052         switch (hw->mac.type) {
7053         case ixgbe_mac_X550:
7054         case ixgbe_mac_X550EM_x:
7055         case ixgbe_mac_X550EM_a:
7056                 /* Independent of link speed. */
7057                 incval = 1;
7058                 /* Cycles read will be interpreted as ns. */
7059                 shift = 0;
7060                 /* Fall-through */
7061         case ixgbe_mac_X540:
7062                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7063                 break;
7064         case ixgbe_mac_82599EB:
7065                 incval >>= IXGBE_INCVAL_SHIFT_82599;
7066                 shift -= IXGBE_INCVAL_SHIFT_82599;
7067                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7068                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7069                 break;
7070         default:
7071                 /* Not supported. */
7072                 return;
7073         }
7074
7075         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7076         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7077         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7078
7079         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7080         adapter->systime_tc.cc_shift = shift;
7081         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7082
7083         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7084         adapter->rx_tstamp_tc.cc_shift = shift;
7085         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7086
7087         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7088         adapter->tx_tstamp_tc.cc_shift = shift;
7089         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7090 }
7091
7092 static int
7093 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7094 {
7095         struct ixgbe_adapter *adapter = dev->data->dev_private;
7096
7097         adapter->systime_tc.nsec += delta;
7098         adapter->rx_tstamp_tc.nsec += delta;
7099         adapter->tx_tstamp_tc.nsec += delta;
7100
7101         return 0;
7102 }
7103
7104 static int
7105 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7106 {
7107         uint64_t ns;
7108         struct ixgbe_adapter *adapter = dev->data->dev_private;
7109
7110         ns = rte_timespec_to_ns(ts);
7111         /* Set the timecounters to a new value. */
7112         adapter->systime_tc.nsec = ns;
7113         adapter->rx_tstamp_tc.nsec = ns;
7114         adapter->tx_tstamp_tc.nsec = ns;
7115
7116         return 0;
7117 }
7118
7119 static int
7120 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7121 {
7122         uint64_t ns, systime_cycles;
7123         struct ixgbe_adapter *adapter = dev->data->dev_private;
7124
7125         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7126         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7127         *ts = rte_ns_to_timespec(ns);
7128
7129         return 0;
7130 }
7131
7132 static int
7133 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7134 {
7135         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7136         uint32_t tsync_ctl;
7137         uint32_t tsauxc;
7138
7139         /* Stop the timesync system time. */
7140         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7141         /* Reset the timesync system time value. */
7142         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7143         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7144
7145         /* Enable system time for platforms where it isn't on by default. */
7146         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7147         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7148         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7149
7150         ixgbe_start_timecounters(dev);
7151
7152         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7153         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7154                         (RTE_ETHER_TYPE_1588 |
7155                          IXGBE_ETQF_FILTER_EN |
7156                          IXGBE_ETQF_1588));
7157
7158         /* Enable timestamping of received PTP packets. */
7159         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7160         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7161         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7162
7163         /* Enable timestamping of transmitted PTP packets. */
7164         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7165         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7166         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7167
7168         IXGBE_WRITE_FLUSH(hw);
7169
7170         return 0;
7171 }
7172
7173 static int
7174 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7175 {
7176         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7177         uint32_t tsync_ctl;
7178
7179         /* Disable timestamping of transmitted PTP packets. */
7180         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7181         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7182         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7183
7184         /* Disable timestamping of received PTP packets. */
7185         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7186         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7187         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7188
7189         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7190         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7191
7192         /* Stop incrementating the System Time registers. */
7193         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7194
7195         return 0;
7196 }
7197
7198 static int
7199 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7200                                  struct timespec *timestamp,
7201                                  uint32_t flags __rte_unused)
7202 {
7203         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7204         struct ixgbe_adapter *adapter = dev->data->dev_private;
7205         uint32_t tsync_rxctl;
7206         uint64_t rx_tstamp_cycles;
7207         uint64_t ns;
7208
7209         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7210         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7211                 return -EINVAL;
7212
7213         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7214         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7215         *timestamp = rte_ns_to_timespec(ns);
7216
7217         return  0;
7218 }
7219
7220 static int
7221 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7222                                  struct timespec *timestamp)
7223 {
7224         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7225         struct ixgbe_adapter *adapter = dev->data->dev_private;
7226         uint32_t tsync_txctl;
7227         uint64_t tx_tstamp_cycles;
7228         uint64_t ns;
7229
7230         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7231         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7232                 return -EINVAL;
7233
7234         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7235         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7236         *timestamp = rte_ns_to_timespec(ns);
7237
7238         return 0;
7239 }
7240
7241 static int
7242 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7243 {
7244         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7245         int count = 0;
7246         int g_ind = 0;
7247         const struct reg_info *reg_group;
7248         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7249                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7250
7251         while ((reg_group = reg_set[g_ind++]))
7252                 count += ixgbe_regs_group_count(reg_group);
7253
7254         return count;
7255 }
7256
7257 static int
7258 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7259 {
7260         int count = 0;
7261         int g_ind = 0;
7262         const struct reg_info *reg_group;
7263
7264         while ((reg_group = ixgbevf_regs[g_ind++]))
7265                 count += ixgbe_regs_group_count(reg_group);
7266
7267         return count;
7268 }
7269
7270 static int
7271 ixgbe_get_regs(struct rte_eth_dev *dev,
7272               struct rte_dev_reg_info *regs)
7273 {
7274         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7275         uint32_t *data = regs->data;
7276         int g_ind = 0;
7277         int count = 0;
7278         const struct reg_info *reg_group;
7279         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7280                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7281
7282         if (data == NULL) {
7283                 regs->length = ixgbe_get_reg_length(dev);
7284                 regs->width = sizeof(uint32_t);
7285                 return 0;
7286         }
7287
7288         /* Support only full register dump */
7289         if ((regs->length == 0) ||
7290             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7291                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7292                         hw->device_id;
7293                 while ((reg_group = reg_set[g_ind++]))
7294                         count += ixgbe_read_regs_group(dev, &data[count],
7295                                 reg_group);
7296                 return 0;
7297         }
7298
7299         return -ENOTSUP;
7300 }
7301
7302 static int
7303 ixgbevf_get_regs(struct rte_eth_dev *dev,
7304                 struct rte_dev_reg_info *regs)
7305 {
7306         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7307         uint32_t *data = regs->data;
7308         int g_ind = 0;
7309         int count = 0;
7310         const struct reg_info *reg_group;
7311
7312         if (data == NULL) {
7313                 regs->length = ixgbevf_get_reg_length(dev);
7314                 regs->width = sizeof(uint32_t);
7315                 return 0;
7316         }
7317
7318         /* Support only full register dump */
7319         if ((regs->length == 0) ||
7320             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7321                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7322                         hw->device_id;
7323                 while ((reg_group = ixgbevf_regs[g_ind++]))
7324                         count += ixgbe_read_regs_group(dev, &data[count],
7325                                                       reg_group);
7326                 return 0;
7327         }
7328
7329         return -ENOTSUP;
7330 }
7331
7332 static int
7333 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7334 {
7335         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7336
7337         /* Return unit is byte count */
7338         return hw->eeprom.word_size * 2;
7339 }
7340
7341 static int
7342 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7343                 struct rte_dev_eeprom_info *in_eeprom)
7344 {
7345         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7346         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7347         uint16_t *data = in_eeprom->data;
7348         int first, length;
7349
7350         first = in_eeprom->offset >> 1;
7351         length = in_eeprom->length >> 1;
7352         if ((first > hw->eeprom.word_size) ||
7353             ((first + length) > hw->eeprom.word_size))
7354                 return -EINVAL;
7355
7356         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7357
7358         return eeprom->ops.read_buffer(hw, first, length, data);
7359 }
7360
7361 static int
7362 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7363                 struct rte_dev_eeprom_info *in_eeprom)
7364 {
7365         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7366         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7367         uint16_t *data = in_eeprom->data;
7368         int first, length;
7369
7370         first = in_eeprom->offset >> 1;
7371         length = in_eeprom->length >> 1;
7372         if ((first > hw->eeprom.word_size) ||
7373             ((first + length) > hw->eeprom.word_size))
7374                 return -EINVAL;
7375
7376         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7377
7378         return eeprom->ops.write_buffer(hw,  first, length, data);
7379 }
7380
7381 static int
7382 ixgbe_get_module_info(struct rte_eth_dev *dev,
7383                       struct rte_eth_dev_module_info *modinfo)
7384 {
7385         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7386         uint32_t status;
7387         uint8_t sff8472_rev, addr_mode;
7388         bool page_swap = false;
7389
7390         /* Check whether we support SFF-8472 or not */
7391         status = hw->phy.ops.read_i2c_eeprom(hw,
7392                                              IXGBE_SFF_SFF_8472_COMP,
7393                                              &sff8472_rev);
7394         if (status != 0)
7395                 return -EIO;
7396
7397         /* addressing mode is not supported */
7398         status = hw->phy.ops.read_i2c_eeprom(hw,
7399                                              IXGBE_SFF_SFF_8472_SWAP,
7400                                              &addr_mode);
7401         if (status != 0)
7402                 return -EIO;
7403
7404         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7405                 PMD_DRV_LOG(ERR,
7406                             "Address change required to access page 0xA2, "
7407                             "but not supported. Please report the module "
7408                             "type to the driver maintainers.");
7409                 page_swap = true;
7410         }
7411
7412         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7413                 /* We have a SFP, but it does not support SFF-8472 */
7414                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7415                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7416         } else {
7417                 /* We have a SFP which supports a revision of SFF-8472. */
7418                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7419                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7420         }
7421
7422         return 0;
7423 }
7424
7425 static int
7426 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7427                         struct rte_dev_eeprom_info *info)
7428 {
7429         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7430         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7431         uint8_t databyte = 0xFF;
7432         uint8_t *data = info->data;
7433         uint32_t i = 0;
7434
7435         if (info->length == 0)
7436                 return -EINVAL;
7437
7438         for (i = info->offset; i < info->offset + info->length; i++) {
7439                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7440                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7441                 else
7442                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7443
7444                 if (status != 0)
7445                         return -EIO;
7446
7447                 data[i - info->offset] = databyte;
7448         }
7449
7450         return 0;
7451 }
7452
7453 uint16_t
7454 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7455         switch (mac_type) {
7456         case ixgbe_mac_X550:
7457         case ixgbe_mac_X550EM_x:
7458         case ixgbe_mac_X550EM_a:
7459                 return ETH_RSS_RETA_SIZE_512;
7460         case ixgbe_mac_X550_vf:
7461         case ixgbe_mac_X550EM_x_vf:
7462         case ixgbe_mac_X550EM_a_vf:
7463                 return ETH_RSS_RETA_SIZE_64;
7464         case ixgbe_mac_X540_vf:
7465         case ixgbe_mac_82599_vf:
7466                 return 0;
7467         default:
7468                 return ETH_RSS_RETA_SIZE_128;
7469         }
7470 }
7471
7472 uint32_t
7473 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7474         switch (mac_type) {
7475         case ixgbe_mac_X550:
7476         case ixgbe_mac_X550EM_x:
7477         case ixgbe_mac_X550EM_a:
7478                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7479                         return IXGBE_RETA(reta_idx >> 2);
7480                 else
7481                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7482         case ixgbe_mac_X550_vf:
7483         case ixgbe_mac_X550EM_x_vf:
7484         case ixgbe_mac_X550EM_a_vf:
7485                 return IXGBE_VFRETA(reta_idx >> 2);
7486         default:
7487                 return IXGBE_RETA(reta_idx >> 2);
7488         }
7489 }
7490
7491 uint32_t
7492 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7493         switch (mac_type) {
7494         case ixgbe_mac_X550_vf:
7495         case ixgbe_mac_X550EM_x_vf:
7496         case ixgbe_mac_X550EM_a_vf:
7497                 return IXGBE_VFMRQC;
7498         default:
7499                 return IXGBE_MRQC;
7500         }
7501 }
7502
7503 uint32_t
7504 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7505         switch (mac_type) {
7506         case ixgbe_mac_X550_vf:
7507         case ixgbe_mac_X550EM_x_vf:
7508         case ixgbe_mac_X550EM_a_vf:
7509                 return IXGBE_VFRSSRK(i);
7510         default:
7511                 return IXGBE_RSSRK(i);
7512         }
7513 }
7514
7515 bool
7516 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7517         switch (mac_type) {
7518         case ixgbe_mac_82599_vf:
7519         case ixgbe_mac_X540_vf:
7520                 return 0;
7521         default:
7522                 return 1;
7523         }
7524 }
7525
7526 static int
7527 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7528                         struct rte_eth_dcb_info *dcb_info)
7529 {
7530         struct ixgbe_dcb_config *dcb_config =
7531                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7532         struct ixgbe_dcb_tc_config *tc;
7533         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7534         uint8_t nb_tcs;
7535         uint8_t i, j;
7536
7537         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7538                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7539         else
7540                 dcb_info->nb_tcs = 1;
7541
7542         tc_queue = &dcb_info->tc_queue;
7543         nb_tcs = dcb_info->nb_tcs;
7544
7545         if (dcb_config->vt_mode) { /* vt is enabled*/
7546                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7547                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7548                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7549                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7550                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7551                         for (j = 0; j < nb_tcs; j++) {
7552                                 tc_queue->tc_rxq[0][j].base = j;
7553                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7554                                 tc_queue->tc_txq[0][j].base = j;
7555                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7556                         }
7557                 } else {
7558                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7559                                 for (j = 0; j < nb_tcs; j++) {
7560                                         tc_queue->tc_rxq[i][j].base =
7561                                                 i * nb_tcs + j;
7562                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7563                                         tc_queue->tc_txq[i][j].base =
7564                                                 i * nb_tcs + j;
7565                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7566                                 }
7567                         }
7568                 }
7569         } else { /* vt is disabled*/
7570                 struct rte_eth_dcb_rx_conf *rx_conf =
7571                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7572                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7573                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7574                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7575                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7576                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7577                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7578                         }
7579                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7580                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7581                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7582                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7583                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7584                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7585                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7586                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7587                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7588                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7589                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7590                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7591                         }
7592                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7593                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7594                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7595                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7596                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7597                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7598                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7599                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7600                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7601                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7602                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7603                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7604                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7605                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7606                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7607                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7608                 }
7609         }
7610         for (i = 0; i < dcb_info->nb_tcs; i++) {
7611                 tc = &dcb_config->tc_config[i];
7612                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7613         }
7614         return 0;
7615 }
7616
7617 /* Update e-tag ether type */
7618 static int
7619 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7620                             uint16_t ether_type)
7621 {
7622         uint32_t etag_etype;
7623
7624         if (hw->mac.type != ixgbe_mac_X550 &&
7625             hw->mac.type != ixgbe_mac_X550EM_x &&
7626             hw->mac.type != ixgbe_mac_X550EM_a) {
7627                 return -ENOTSUP;
7628         }
7629
7630         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7631         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7632         etag_etype |= ether_type;
7633         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7634         IXGBE_WRITE_FLUSH(hw);
7635
7636         return 0;
7637 }
7638
7639 /* Config l2 tunnel ether type */
7640 static int
7641 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7642                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7643 {
7644         int ret = 0;
7645         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7646         struct ixgbe_l2_tn_info *l2_tn_info =
7647                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7648
7649         if (l2_tunnel == NULL)
7650                 return -EINVAL;
7651
7652         switch (l2_tunnel->l2_tunnel_type) {
7653         case RTE_L2_TUNNEL_TYPE_E_TAG:
7654                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7655                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7656                 break;
7657         default:
7658                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7659                 ret = -EINVAL;
7660                 break;
7661         }
7662
7663         return ret;
7664 }
7665
7666 /* Enable e-tag tunnel */
7667 static int
7668 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7669 {
7670         uint32_t etag_etype;
7671
7672         if (hw->mac.type != ixgbe_mac_X550 &&
7673             hw->mac.type != ixgbe_mac_X550EM_x &&
7674             hw->mac.type != ixgbe_mac_X550EM_a) {
7675                 return -ENOTSUP;
7676         }
7677
7678         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7679         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7680         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7681         IXGBE_WRITE_FLUSH(hw);
7682
7683         return 0;
7684 }
7685
7686 /* Enable l2 tunnel */
7687 static int
7688 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7689                            enum rte_eth_tunnel_type l2_tunnel_type)
7690 {
7691         int ret = 0;
7692         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7693         struct ixgbe_l2_tn_info *l2_tn_info =
7694                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7695
7696         switch (l2_tunnel_type) {
7697         case RTE_L2_TUNNEL_TYPE_E_TAG:
7698                 l2_tn_info->e_tag_en = TRUE;
7699                 ret = ixgbe_e_tag_enable(hw);
7700                 break;
7701         default:
7702                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7703                 ret = -EINVAL;
7704                 break;
7705         }
7706
7707         return ret;
7708 }
7709
7710 /* Disable e-tag tunnel */
7711 static int
7712 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7713 {
7714         uint32_t etag_etype;
7715
7716         if (hw->mac.type != ixgbe_mac_X550 &&
7717             hw->mac.type != ixgbe_mac_X550EM_x &&
7718             hw->mac.type != ixgbe_mac_X550EM_a) {
7719                 return -ENOTSUP;
7720         }
7721
7722         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7723         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7724         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7725         IXGBE_WRITE_FLUSH(hw);
7726
7727         return 0;
7728 }
7729
7730 /* Disable l2 tunnel */
7731 static int
7732 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7733                             enum rte_eth_tunnel_type l2_tunnel_type)
7734 {
7735         int ret = 0;
7736         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7737         struct ixgbe_l2_tn_info *l2_tn_info =
7738                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7739
7740         switch (l2_tunnel_type) {
7741         case RTE_L2_TUNNEL_TYPE_E_TAG:
7742                 l2_tn_info->e_tag_en = FALSE;
7743                 ret = ixgbe_e_tag_disable(hw);
7744                 break;
7745         default:
7746                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7747                 ret = -EINVAL;
7748                 break;
7749         }
7750
7751         return ret;
7752 }
7753
7754 static int
7755 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7756                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7757 {
7758         int ret = 0;
7759         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7760         uint32_t i, rar_entries;
7761         uint32_t rar_low, rar_high;
7762
7763         if (hw->mac.type != ixgbe_mac_X550 &&
7764             hw->mac.type != ixgbe_mac_X550EM_x &&
7765             hw->mac.type != ixgbe_mac_X550EM_a) {
7766                 return -ENOTSUP;
7767         }
7768
7769         rar_entries = ixgbe_get_num_rx_addrs(hw);
7770
7771         for (i = 1; i < rar_entries; i++) {
7772                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7773                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7774                 if ((rar_high & IXGBE_RAH_AV) &&
7775                     (rar_high & IXGBE_RAH_ADTYPE) &&
7776                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7777                      l2_tunnel->tunnel_id)) {
7778                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7779                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7780
7781                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7782
7783                         return ret;
7784                 }
7785         }
7786
7787         return ret;
7788 }
7789
7790 static int
7791 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7792                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7793 {
7794         int ret = 0;
7795         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7796         uint32_t i, rar_entries;
7797         uint32_t rar_low, rar_high;
7798
7799         if (hw->mac.type != ixgbe_mac_X550 &&
7800             hw->mac.type != ixgbe_mac_X550EM_x &&
7801             hw->mac.type != ixgbe_mac_X550EM_a) {
7802                 return -ENOTSUP;
7803         }
7804
7805         /* One entry for one tunnel. Try to remove potential existing entry. */
7806         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7807
7808         rar_entries = ixgbe_get_num_rx_addrs(hw);
7809
7810         for (i = 1; i < rar_entries; i++) {
7811                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7812                 if (rar_high & IXGBE_RAH_AV) {
7813                         continue;
7814                 } else {
7815                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7816                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7817                         rar_low = l2_tunnel->tunnel_id;
7818
7819                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7820                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7821
7822                         return ret;
7823                 }
7824         }
7825
7826         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7827                      " Please remove a rule before adding a new one.");
7828         return -EINVAL;
7829 }
7830
7831 static inline struct ixgbe_l2_tn_filter *
7832 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7833                           struct ixgbe_l2_tn_key *key)
7834 {
7835         int ret;
7836
7837         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7838         if (ret < 0)
7839                 return NULL;
7840
7841         return l2_tn_info->hash_map[ret];
7842 }
7843
7844 static inline int
7845 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7846                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7847 {
7848         int ret;
7849
7850         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7851                                &l2_tn_filter->key);
7852
7853         if (ret < 0) {
7854                 PMD_DRV_LOG(ERR,
7855                             "Failed to insert L2 tunnel filter"
7856                             " to hash table %d!",
7857                             ret);
7858                 return ret;
7859         }
7860
7861         l2_tn_info->hash_map[ret] = l2_tn_filter;
7862
7863         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7864
7865         return 0;
7866 }
7867
7868 static inline int
7869 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7870                           struct ixgbe_l2_tn_key *key)
7871 {
7872         int ret;
7873         struct ixgbe_l2_tn_filter *l2_tn_filter;
7874
7875         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7876
7877         if (ret < 0) {
7878                 PMD_DRV_LOG(ERR,
7879                             "No such L2 tunnel filter to delete %d!",
7880                             ret);
7881                 return ret;
7882         }
7883
7884         l2_tn_filter = l2_tn_info->hash_map[ret];
7885         l2_tn_info->hash_map[ret] = NULL;
7886
7887         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7888         rte_free(l2_tn_filter);
7889
7890         return 0;
7891 }
7892
7893 /* Add l2 tunnel filter */
7894 int
7895 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7896                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7897                                bool restore)
7898 {
7899         int ret;
7900         struct ixgbe_l2_tn_info *l2_tn_info =
7901                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7902         struct ixgbe_l2_tn_key key;
7903         struct ixgbe_l2_tn_filter *node;
7904
7905         if (!restore) {
7906                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7907                 key.tn_id = l2_tunnel->tunnel_id;
7908
7909                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7910
7911                 if (node) {
7912                         PMD_DRV_LOG(ERR,
7913                                     "The L2 tunnel filter already exists!");
7914                         return -EINVAL;
7915                 }
7916
7917                 node = rte_zmalloc("ixgbe_l2_tn",
7918                                    sizeof(struct ixgbe_l2_tn_filter),
7919                                    0);
7920                 if (!node)
7921                         return -ENOMEM;
7922
7923                 rte_memcpy(&node->key,
7924                                  &key,
7925                                  sizeof(struct ixgbe_l2_tn_key));
7926                 node->pool = l2_tunnel->pool;
7927                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7928                 if (ret < 0) {
7929                         rte_free(node);
7930                         return ret;
7931                 }
7932         }
7933
7934         switch (l2_tunnel->l2_tunnel_type) {
7935         case RTE_L2_TUNNEL_TYPE_E_TAG:
7936                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7937                 break;
7938         default:
7939                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7940                 ret = -EINVAL;
7941                 break;
7942         }
7943
7944         if ((!restore) && (ret < 0))
7945                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7946
7947         return ret;
7948 }
7949
7950 /* Delete l2 tunnel filter */
7951 int
7952 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7953                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7954 {
7955         int ret;
7956         struct ixgbe_l2_tn_info *l2_tn_info =
7957                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7958         struct ixgbe_l2_tn_key key;
7959
7960         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7961         key.tn_id = l2_tunnel->tunnel_id;
7962         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7963         if (ret < 0)
7964                 return ret;
7965
7966         switch (l2_tunnel->l2_tunnel_type) {
7967         case RTE_L2_TUNNEL_TYPE_E_TAG:
7968                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7969                 break;
7970         default:
7971                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7972                 ret = -EINVAL;
7973                 break;
7974         }
7975
7976         return ret;
7977 }
7978
7979 /**
7980  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7981  * @dev: pointer to rte_eth_dev structure
7982  * @filter_op:operation will be taken.
7983  * @arg: a pointer to specific structure corresponding to the filter_op
7984  */
7985 static int
7986 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7987                                   enum rte_filter_op filter_op,
7988                                   void *arg)
7989 {
7990         int ret;
7991
7992         if (filter_op == RTE_ETH_FILTER_NOP)
7993                 return 0;
7994
7995         if (arg == NULL) {
7996                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7997                             filter_op);
7998                 return -EINVAL;
7999         }
8000
8001         switch (filter_op) {
8002         case RTE_ETH_FILTER_ADD:
8003                 ret = ixgbe_dev_l2_tunnel_filter_add
8004                         (dev,
8005                          (struct rte_eth_l2_tunnel_conf *)arg,
8006                          FALSE);
8007                 break;
8008         case RTE_ETH_FILTER_DELETE:
8009                 ret = ixgbe_dev_l2_tunnel_filter_del
8010                         (dev,
8011                          (struct rte_eth_l2_tunnel_conf *)arg);
8012                 break;
8013         default:
8014                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8015                 ret = -EINVAL;
8016                 break;
8017         }
8018         return ret;
8019 }
8020
8021 static int
8022 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8023 {
8024         int ret = 0;
8025         uint32_t ctrl;
8026         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8027
8028         if (hw->mac.type != ixgbe_mac_X550 &&
8029             hw->mac.type != ixgbe_mac_X550EM_x &&
8030             hw->mac.type != ixgbe_mac_X550EM_a) {
8031                 return -ENOTSUP;
8032         }
8033
8034         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8035         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8036         if (en)
8037                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8038         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8039
8040         return ret;
8041 }
8042
8043 /* Enable l2 tunnel forwarding */
8044 static int
8045 ixgbe_dev_l2_tunnel_forwarding_enable
8046         (struct rte_eth_dev *dev,
8047          enum rte_eth_tunnel_type l2_tunnel_type)
8048 {
8049         struct ixgbe_l2_tn_info *l2_tn_info =
8050                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8051         int ret = 0;
8052
8053         switch (l2_tunnel_type) {
8054         case RTE_L2_TUNNEL_TYPE_E_TAG:
8055                 l2_tn_info->e_tag_fwd_en = TRUE;
8056                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8057                 break;
8058         default:
8059                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8060                 ret = -EINVAL;
8061                 break;
8062         }
8063
8064         return ret;
8065 }
8066
8067 /* Disable l2 tunnel forwarding */
8068 static int
8069 ixgbe_dev_l2_tunnel_forwarding_disable
8070         (struct rte_eth_dev *dev,
8071          enum rte_eth_tunnel_type l2_tunnel_type)
8072 {
8073         struct ixgbe_l2_tn_info *l2_tn_info =
8074                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8075         int ret = 0;
8076
8077         switch (l2_tunnel_type) {
8078         case RTE_L2_TUNNEL_TYPE_E_TAG:
8079                 l2_tn_info->e_tag_fwd_en = FALSE;
8080                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8081                 break;
8082         default:
8083                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8084                 ret = -EINVAL;
8085                 break;
8086         }
8087
8088         return ret;
8089 }
8090
8091 static int
8092 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8093                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
8094                              bool en)
8095 {
8096         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8097         int ret = 0;
8098         uint32_t vmtir, vmvir;
8099         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8100
8101         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8102                 PMD_DRV_LOG(ERR,
8103                             "VF id %u should be less than %u",
8104                             l2_tunnel->vf_id,
8105                             pci_dev->max_vfs);
8106                 return -EINVAL;
8107         }
8108
8109         if (hw->mac.type != ixgbe_mac_X550 &&
8110             hw->mac.type != ixgbe_mac_X550EM_x &&
8111             hw->mac.type != ixgbe_mac_X550EM_a) {
8112                 return -ENOTSUP;
8113         }
8114
8115         if (en)
8116                 vmtir = l2_tunnel->tunnel_id;
8117         else
8118                 vmtir = 0;
8119
8120         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8121
8122         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8123         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8124         if (en)
8125                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8126         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8127
8128         return ret;
8129 }
8130
8131 /* Enable l2 tunnel tag insertion */
8132 static int
8133 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8134                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8135 {
8136         int ret = 0;
8137
8138         switch (l2_tunnel->l2_tunnel_type) {
8139         case RTE_L2_TUNNEL_TYPE_E_TAG:
8140                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8141                 break;
8142         default:
8143                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8144                 ret = -EINVAL;
8145                 break;
8146         }
8147
8148         return ret;
8149 }
8150
8151 /* Disable l2 tunnel tag insertion */
8152 static int
8153 ixgbe_dev_l2_tunnel_insertion_disable
8154         (struct rte_eth_dev *dev,
8155          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8156 {
8157         int ret = 0;
8158
8159         switch (l2_tunnel->l2_tunnel_type) {
8160         case RTE_L2_TUNNEL_TYPE_E_TAG:
8161                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8162                 break;
8163         default:
8164                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8165                 ret = -EINVAL;
8166                 break;
8167         }
8168
8169         return ret;
8170 }
8171
8172 static int
8173 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8174                              bool en)
8175 {
8176         int ret = 0;
8177         uint32_t qde;
8178         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8179
8180         if (hw->mac.type != ixgbe_mac_X550 &&
8181             hw->mac.type != ixgbe_mac_X550EM_x &&
8182             hw->mac.type != ixgbe_mac_X550EM_a) {
8183                 return -ENOTSUP;
8184         }
8185
8186         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8187         if (en)
8188                 qde |= IXGBE_QDE_STRIP_TAG;
8189         else
8190                 qde &= ~IXGBE_QDE_STRIP_TAG;
8191         qde &= ~IXGBE_QDE_READ;
8192         qde |= IXGBE_QDE_WRITE;
8193         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8194
8195         return ret;
8196 }
8197
8198 /* Enable l2 tunnel tag stripping */
8199 static int
8200 ixgbe_dev_l2_tunnel_stripping_enable
8201         (struct rte_eth_dev *dev,
8202          enum rte_eth_tunnel_type l2_tunnel_type)
8203 {
8204         int ret = 0;
8205
8206         switch (l2_tunnel_type) {
8207         case RTE_L2_TUNNEL_TYPE_E_TAG:
8208                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8209                 break;
8210         default:
8211                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8212                 ret = -EINVAL;
8213                 break;
8214         }
8215
8216         return ret;
8217 }
8218
8219 /* Disable l2 tunnel tag stripping */
8220 static int
8221 ixgbe_dev_l2_tunnel_stripping_disable
8222         (struct rte_eth_dev *dev,
8223          enum rte_eth_tunnel_type l2_tunnel_type)
8224 {
8225         int ret = 0;
8226
8227         switch (l2_tunnel_type) {
8228         case RTE_L2_TUNNEL_TYPE_E_TAG:
8229                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8230                 break;
8231         default:
8232                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8233                 ret = -EINVAL;
8234                 break;
8235         }
8236
8237         return ret;
8238 }
8239
8240 /* Enable/disable l2 tunnel offload functions */
8241 static int
8242 ixgbe_dev_l2_tunnel_offload_set
8243         (struct rte_eth_dev *dev,
8244          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8245          uint32_t mask,
8246          uint8_t en)
8247 {
8248         int ret = 0;
8249
8250         if (l2_tunnel == NULL)
8251                 return -EINVAL;
8252
8253         ret = -EINVAL;
8254         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8255                 if (en)
8256                         ret = ixgbe_dev_l2_tunnel_enable(
8257                                 dev,
8258                                 l2_tunnel->l2_tunnel_type);
8259                 else
8260                         ret = ixgbe_dev_l2_tunnel_disable(
8261                                 dev,
8262                                 l2_tunnel->l2_tunnel_type);
8263         }
8264
8265         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8266                 if (en)
8267                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8268                                 dev,
8269                                 l2_tunnel);
8270                 else
8271                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8272                                 dev,
8273                                 l2_tunnel);
8274         }
8275
8276         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8277                 if (en)
8278                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8279                                 dev,
8280                                 l2_tunnel->l2_tunnel_type);
8281                 else
8282                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8283                                 dev,
8284                                 l2_tunnel->l2_tunnel_type);
8285         }
8286
8287         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8288                 if (en)
8289                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8290                                 dev,
8291                                 l2_tunnel->l2_tunnel_type);
8292                 else
8293                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8294                                 dev,
8295                                 l2_tunnel->l2_tunnel_type);
8296         }
8297
8298         return ret;
8299 }
8300
8301 static int
8302 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8303                         uint16_t port)
8304 {
8305         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8306         IXGBE_WRITE_FLUSH(hw);
8307
8308         return 0;
8309 }
8310
8311 /* There's only one register for VxLAN UDP port.
8312  * So, we cannot add several ports. Will update it.
8313  */
8314 static int
8315 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8316                      uint16_t port)
8317 {
8318         if (port == 0) {
8319                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8320                 return -EINVAL;
8321         }
8322
8323         return ixgbe_update_vxlan_port(hw, port);
8324 }
8325
8326 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8327  * UDP port, it must have a value.
8328  * So, will reset it to the original value 0.
8329  */
8330 static int
8331 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8332                      uint16_t port)
8333 {
8334         uint16_t cur_port;
8335
8336         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8337
8338         if (cur_port != port) {
8339                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8340                 return -EINVAL;
8341         }
8342
8343         return ixgbe_update_vxlan_port(hw, 0);
8344 }
8345
8346 /* Add UDP tunneling port */
8347 static int
8348 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8349                               struct rte_eth_udp_tunnel *udp_tunnel)
8350 {
8351         int ret = 0;
8352         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8353
8354         if (hw->mac.type != ixgbe_mac_X550 &&
8355             hw->mac.type != ixgbe_mac_X550EM_x &&
8356             hw->mac.type != ixgbe_mac_X550EM_a) {
8357                 return -ENOTSUP;
8358         }
8359
8360         if (udp_tunnel == NULL)
8361                 return -EINVAL;
8362
8363         switch (udp_tunnel->prot_type) {
8364         case RTE_TUNNEL_TYPE_VXLAN:
8365                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8366                 break;
8367
8368         case RTE_TUNNEL_TYPE_GENEVE:
8369         case RTE_TUNNEL_TYPE_TEREDO:
8370                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8371                 ret = -EINVAL;
8372                 break;
8373
8374         default:
8375                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8376                 ret = -EINVAL;
8377                 break;
8378         }
8379
8380         return ret;
8381 }
8382
8383 /* Remove UDP tunneling port */
8384 static int
8385 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8386                               struct rte_eth_udp_tunnel *udp_tunnel)
8387 {
8388         int ret = 0;
8389         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8390
8391         if (hw->mac.type != ixgbe_mac_X550 &&
8392             hw->mac.type != ixgbe_mac_X550EM_x &&
8393             hw->mac.type != ixgbe_mac_X550EM_a) {
8394                 return -ENOTSUP;
8395         }
8396
8397         if (udp_tunnel == NULL)
8398                 return -EINVAL;
8399
8400         switch (udp_tunnel->prot_type) {
8401         case RTE_TUNNEL_TYPE_VXLAN:
8402                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8403                 break;
8404         case RTE_TUNNEL_TYPE_GENEVE:
8405         case RTE_TUNNEL_TYPE_TEREDO:
8406                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8407                 ret = -EINVAL;
8408                 break;
8409         default:
8410                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8411                 ret = -EINVAL;
8412                 break;
8413         }
8414
8415         return ret;
8416 }
8417
8418 static int
8419 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8420 {
8421         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8422         int ret;
8423
8424         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8425         case IXGBE_SUCCESS:
8426                 ret = 0;
8427                 break;
8428         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8429                 ret = -ENOTSUP;
8430                 break;
8431         default:
8432                 ret = -EAGAIN;
8433                 break;
8434         }
8435
8436         return ret;
8437 }
8438
8439 static int
8440 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8441 {
8442         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8443         int ret;
8444
8445         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8446         case IXGBE_SUCCESS:
8447                 ret = 0;
8448                 break;
8449         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8450                 ret = -ENOTSUP;
8451                 break;
8452         default:
8453                 ret = -EAGAIN;
8454                 break;
8455         }
8456
8457         return ret;
8458 }
8459
8460 static void
8461 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8462 {
8463         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8464
8465         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8466 }
8467
8468 static void
8469 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8470 {
8471         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8472
8473         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8474 }
8475
8476 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8477 {
8478         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8479         u32 in_msg = 0;
8480
8481         /* peek the message first */
8482         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8483
8484         /* PF reset VF event */
8485         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8486                 /* dummy mbx read to ack pf */
8487                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8488                         return;
8489                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8490                                               NULL);
8491         }
8492 }
8493
8494 static int
8495 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8496 {
8497         uint32_t eicr;
8498         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8499         struct ixgbe_interrupt *intr =
8500                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8501         ixgbevf_intr_disable(dev);
8502
8503         /* read-on-clear nic registers here */
8504         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8505         intr->flags = 0;
8506
8507         /* only one misc vector supported - mailbox */
8508         eicr &= IXGBE_VTEICR_MASK;
8509         if (eicr == IXGBE_MISC_VEC_ID)
8510                 intr->flags |= IXGBE_FLAG_MAILBOX;
8511
8512         return 0;
8513 }
8514
8515 static int
8516 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8517 {
8518         struct ixgbe_interrupt *intr =
8519                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8520
8521         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8522                 ixgbevf_mbx_process(dev);
8523                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8524         }
8525
8526         ixgbevf_intr_enable(dev);
8527
8528         return 0;
8529 }
8530
8531 static void
8532 ixgbevf_dev_interrupt_handler(void *param)
8533 {
8534         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8535
8536         ixgbevf_dev_interrupt_get_status(dev);
8537         ixgbevf_dev_interrupt_action(dev);
8538 }
8539
8540 /**
8541  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8542  *  @hw: pointer to hardware structure
8543  *
8544  *  Stops the transmit data path and waits for the HW to internally empty
8545  *  the Tx security block
8546  **/
8547 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8548 {
8549 #define IXGBE_MAX_SECTX_POLL 40
8550
8551         int i;
8552         int sectxreg;
8553
8554         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8555         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8556         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8557         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8558                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8559                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8560                         break;
8561                 /* Use interrupt-safe sleep just in case */
8562                 usec_delay(1000);
8563         }
8564
8565         /* For informational purposes only */
8566         if (i >= IXGBE_MAX_SECTX_POLL)
8567                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8568                          "path fully disabled.  Continuing with init.");
8569
8570         return IXGBE_SUCCESS;
8571 }
8572
8573 /**
8574  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8575  *  @hw: pointer to hardware structure
8576  *
8577  *  Enables the transmit data path.
8578  **/
8579 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8580 {
8581         uint32_t sectxreg;
8582
8583         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8584         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8585         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8586         IXGBE_WRITE_FLUSH(hw);
8587
8588         return IXGBE_SUCCESS;
8589 }
8590
8591 /* restore n-tuple filter */
8592 static inline void
8593 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8594 {
8595         struct ixgbe_filter_info *filter_info =
8596                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8597         struct ixgbe_5tuple_filter *node;
8598
8599         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8600                 ixgbe_inject_5tuple_filter(dev, node);
8601         }
8602 }
8603
8604 /* restore ethernet type filter */
8605 static inline void
8606 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8607 {
8608         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8609         struct ixgbe_filter_info *filter_info =
8610                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8611         int i;
8612
8613         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8614                 if (filter_info->ethertype_mask & (1 << i)) {
8615                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8616                                         filter_info->ethertype_filters[i].etqf);
8617                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8618                                         filter_info->ethertype_filters[i].etqs);
8619                         IXGBE_WRITE_FLUSH(hw);
8620                 }
8621         }
8622 }
8623
8624 /* restore SYN filter */
8625 static inline void
8626 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8627 {
8628         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8629         struct ixgbe_filter_info *filter_info =
8630                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8631         uint32_t synqf;
8632
8633         synqf = filter_info->syn_info;
8634
8635         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8636                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8637                 IXGBE_WRITE_FLUSH(hw);
8638         }
8639 }
8640
8641 /* restore L2 tunnel filter */
8642 static inline void
8643 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8644 {
8645         struct ixgbe_l2_tn_info *l2_tn_info =
8646                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8647         struct ixgbe_l2_tn_filter *node;
8648         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8649
8650         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8651                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8652                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8653                 l2_tn_conf.pool           = node->pool;
8654                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8655         }
8656 }
8657
8658 /* restore rss filter */
8659 static inline void
8660 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8661 {
8662         struct ixgbe_filter_info *filter_info =
8663                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8664
8665         if (filter_info->rss_info.conf.queue_num)
8666                 ixgbe_config_rss_filter(dev,
8667                         &filter_info->rss_info, TRUE);
8668 }
8669
8670 static int
8671 ixgbe_filter_restore(struct rte_eth_dev *dev)
8672 {
8673         ixgbe_ntuple_filter_restore(dev);
8674         ixgbe_ethertype_filter_restore(dev);
8675         ixgbe_syn_filter_restore(dev);
8676         ixgbe_fdir_filter_restore(dev);
8677         ixgbe_l2_tn_filter_restore(dev);
8678         ixgbe_rss_filter_restore(dev);
8679
8680         return 0;
8681 }
8682
8683 static void
8684 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8685 {
8686         struct ixgbe_l2_tn_info *l2_tn_info =
8687                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8688         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8689
8690         if (l2_tn_info->e_tag_en)
8691                 (void)ixgbe_e_tag_enable(hw);
8692
8693         if (l2_tn_info->e_tag_fwd_en)
8694                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8695
8696         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8697 }
8698
8699 /* remove all the n-tuple filters */
8700 void
8701 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8702 {
8703         struct ixgbe_filter_info *filter_info =
8704                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8705         struct ixgbe_5tuple_filter *p_5tuple;
8706
8707         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8708                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8709 }
8710
8711 /* remove all the ether type filters */
8712 void
8713 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8714 {
8715         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8716         struct ixgbe_filter_info *filter_info =
8717                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8718         int i;
8719
8720         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8721                 if (filter_info->ethertype_mask & (1 << i) &&
8722                     !filter_info->ethertype_filters[i].conf) {
8723                         (void)ixgbe_ethertype_filter_remove(filter_info,
8724                                                             (uint8_t)i);
8725                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8726                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8727                         IXGBE_WRITE_FLUSH(hw);
8728                 }
8729         }
8730 }
8731
8732 /* remove the SYN filter */
8733 void
8734 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8735 {
8736         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8737         struct ixgbe_filter_info *filter_info =
8738                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8739
8740         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8741                 filter_info->syn_info = 0;
8742
8743                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8744                 IXGBE_WRITE_FLUSH(hw);
8745         }
8746 }
8747
8748 /* remove all the L2 tunnel filters */
8749 int
8750 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8751 {
8752         struct ixgbe_l2_tn_info *l2_tn_info =
8753                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8754         struct ixgbe_l2_tn_filter *l2_tn_filter;
8755         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8756         int ret = 0;
8757
8758         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8759                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8760                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8761                 l2_tn_conf.pool           = l2_tn_filter->pool;
8762                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8763                 if (ret < 0)
8764                         return ret;
8765         }
8766
8767         return 0;
8768 }
8769
8770 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8771 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8772 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8773 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8774 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8775 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8776 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
8777                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
8778
8779 RTE_INIT(ixgbe_init_log)
8780 {
8781         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8782         if (ixgbe_logtype_init >= 0)
8783                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8784         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8785         if (ixgbe_logtype_driver >= 0)
8786                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8787 }