drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <ethdev_driver.h>
  31 #include <ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIB_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static int ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
 233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
 234                                               uint32_t timeout_ms);
 235
 236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 237                         struct rte_ether_addr *mac_addr,
 238                         uint32_t index, uint32_t pool);
 239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 241                                            struct rte_ether_addr *mac_addr);
 242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 243 static bool is_device_supported(struct rte_eth_dev *dev,
 244                                 struct rte_pci_driver *drv);
 245
 246 /* For Virtual Function support */
 247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 250 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 252                                    int wait_to_complete);
 253 static int ixgbevf_dev_stop(struct rte_eth_dev *dev);
 254 static int ixgbevf_dev_close(struct rte_eth_dev *dev);
 255 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 259                 struct rte_eth_stats *stats);
 260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 262                 uint16_t vlan_id, int on);
 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 264                 uint16_t queue, int on);
 265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 269                                             uint16_t queue_id);
 270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 271                                              uint16_t queue_id);
 272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 273                                  uint8_t queue, uint8_t msix_vector);
 274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 rte_ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 285                 struct rte_eth_mirror_conf *mirror_conf,
 286                 uint8_t rule_id, uint8_t on);
 287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 288                 uint8_t rule_id);
 289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 290                                           uint16_t queue_id);
 291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 292                                            uint16_t queue_id);
 293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 294                                uint8_t queue, uint8_t msix_vector);
 295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 296
 297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 298                                 struct rte_ether_addr *mac_addr,
 299                                 uint32_t index, uint32_t pool);
 300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 302                                              struct rte_ether_addr *mac_addr);
 303 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 304                         struct ixgbe_5tuple_filter *filter);
 305 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 306                         struct ixgbe_5tuple_filter *filter);
 307 static int ixgbe_dev_flow_ops_get(struct rte_eth_dev *dev,
 308                                   const struct rte_flow_ops **ops);
 309 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 310
 311 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 312                                       struct rte_ether_addr *mc_addr_set,
 313                                       uint32_t nb_mc_addr);
 314 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 315                                    struct rte_eth_dcb_info *dcb_info);
 316
 317 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 318 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 319                             struct rte_dev_reg_info *regs);
 320 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 321 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 322                                 struct rte_dev_eeprom_info *eeprom);
 323 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 324                                 struct rte_dev_eeprom_info *eeprom);
 325
 326 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 327                                  struct rte_eth_dev_module_info *modinfo);
 328 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 329                                    struct rte_dev_eeprom_info *info);
 330
 331 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 332 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 333                                 struct rte_dev_reg_info *regs);
 334
 335 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 336 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 337 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 338                                             struct timespec *timestamp,
 339                                             uint32_t flags);
 340 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 341                                             struct timespec *timestamp);
 342 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 343 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 344                                    struct timespec *timestamp);
 345 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 346                                    const struct timespec *timestamp);
 347 static void ixgbevf_dev_interrupt_handler(void *param);
 348
 349 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 350                                          struct rte_eth_udp_tunnel *udp_tunnel);
 351 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 352                                          struct rte_eth_udp_tunnel *udp_tunnel);
 353 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 354 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 355 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
 356
 357 /*
 358  * Define VF Stats MACRO for Non "cleared on read" register
 359  */
 360 #define UPDATE_VF_STAT(reg, last, cur)                          \
 361 {                                                               \
 362         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 363         cur += (latest - last) & UINT_MAX;                      \
 364         last = latest;                                          \
 365 }
 366
 367 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 368 {                                                                \
 369         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 370         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 371         u64 latest = ((new_msb << 32) | new_lsb);                \
 372         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 373         last = latest;                                           \
 374 }
 375
 376 #define IXGBE_SET_HWSTRIP(h, q) do {\
 377                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 378                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 379                 (h)->bitmap[idx] |= 1 << bit;\
 380         } while (0)
 381
 382 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 383                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 384                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 385                 (h)->bitmap[idx] &= ~(1 << bit);\
 386         } while (0)
 387
 388 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 389                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 390                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 391                 (r) = (h)->bitmap[idx] >> bit & 1;\
 392         } while (0)
 393
 394 /*
 395  * The set of PCI devices this driver supports
 396  */
 397 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 398         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 399         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 400         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 401         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 402         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 403         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 404         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 405         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 406         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 407         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 408         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 409         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 410         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 411         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 446 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 448 #endif
 449         { .vendor_id = 0, /* sentinel */ },
 450 };
 451
 452 /*
 453  * The set of PCI devices this driver supports (for 82599 VF)
 454  */
 455 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 466         { .vendor_id = 0, /* sentinel */ },
 467 };
 468
 469 static const struct rte_eth_desc_lim rx_desc_lim = {
 470         .nb_max = IXGBE_MAX_RING_DESC,
 471         .nb_min = IXGBE_MIN_RING_DESC,
 472         .nb_align = IXGBE_RXD_ALIGN,
 473 };
 474
 475 static const struct rte_eth_desc_lim tx_desc_lim = {
 476         .nb_max = IXGBE_MAX_RING_DESC,
 477         .nb_min = IXGBE_MIN_RING_DESC,
 478         .nb_align = IXGBE_TXD_ALIGN,
 479         .nb_seg_max = IXGBE_TX_MAX_SEG,
 480         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 481 };
 482
 483 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 484         .dev_configure        = ixgbe_dev_configure,
 485         .dev_start            = ixgbe_dev_start,
 486         .dev_stop             = ixgbe_dev_stop,
 487         .dev_set_link_up    = ixgbe_dev_set_link_up,
 488         .dev_set_link_down  = ixgbe_dev_set_link_down,
 489         .dev_close            = ixgbe_dev_close,
 490         .dev_reset            = ixgbe_dev_reset,
 491         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 492         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 493         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 494         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 495         .link_update          = ixgbe_dev_link_update,
 496         .stats_get            = ixgbe_dev_stats_get,
 497         .xstats_get           = ixgbe_dev_xstats_get,
 498         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 499         .stats_reset          = ixgbe_dev_stats_reset,
 500         .xstats_reset         = ixgbe_dev_xstats_reset,
 501         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 502         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 503         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 504         .fw_version_get       = ixgbe_fw_version_get,
 505         .dev_infos_get        = ixgbe_dev_info_get,
 506         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 507         .mtu_set              = ixgbe_dev_mtu_set,
 508         .vlan_filter_set      = ixgbe_vlan_filter_set,
 509         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 510         .vlan_offload_set     = ixgbe_vlan_offload_set,
 511         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 512         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 513         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 514         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 515         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 516         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 517         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 518         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 519         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 520         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 521         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 522         .dev_led_on           = ixgbe_dev_led_on,
 523         .dev_led_off          = ixgbe_dev_led_off,
 524         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 525         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 526         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 527         .mac_addr_add         = ixgbe_add_rar,
 528         .mac_addr_remove      = ixgbe_remove_rar,
 529         .mac_addr_set         = ixgbe_set_default_mac_addr,
 530         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 531         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 532         .mirror_rule_set      = ixgbe_mirror_rule_set,
 533         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 534         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 535         .reta_update          = ixgbe_dev_rss_reta_update,
 536         .reta_query           = ixgbe_dev_rss_reta_query,
 537         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 538         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 539         .flow_ops_get         = ixgbe_dev_flow_ops_get,
 540         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 541         .rxq_info_get         = ixgbe_rxq_info_get,
 542         .txq_info_get         = ixgbe_txq_info_get,
 543         .timesync_enable      = ixgbe_timesync_enable,
 544         .timesync_disable     = ixgbe_timesync_disable,
 545         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 546         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 547         .get_reg              = ixgbe_get_regs,
 548         .get_eeprom_length    = ixgbe_get_eeprom_length,
 549         .get_eeprom           = ixgbe_get_eeprom,
 550         .set_eeprom           = ixgbe_set_eeprom,
 551         .get_module_info      = ixgbe_get_module_info,
 552         .get_module_eeprom    = ixgbe_get_module_eeprom,
 553         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 554         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 555         .timesync_read_time   = ixgbe_timesync_read_time,
 556         .timesync_write_time  = ixgbe_timesync_write_time,
 557         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 558         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 559         .tm_ops_get           = ixgbe_tm_ops_get,
 560         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 561         .get_monitor_addr     = ixgbe_get_monitor_addr,
 562 };
 563
 564 /*
 565  * dev_ops for virtual function, bare necessities for basic vf
 566  * operation have been implemented
 567  */
 568 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 569         .dev_configure        = ixgbevf_dev_configure,
 570         .dev_start            = ixgbevf_dev_start,
 571         .dev_stop             = ixgbevf_dev_stop,
 572         .link_update          = ixgbevf_dev_link_update,
 573         .stats_get            = ixgbevf_dev_stats_get,
 574         .xstats_get           = ixgbevf_dev_xstats_get,
 575         .stats_reset          = ixgbevf_dev_stats_reset,
 576         .xstats_reset         = ixgbevf_dev_stats_reset,
 577         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 578         .dev_close            = ixgbevf_dev_close,
 579         .dev_reset            = ixgbevf_dev_reset,
 580         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 581         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 582         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 583         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 584         .dev_infos_get        = ixgbevf_dev_info_get,
 585         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 586         .mtu_set              = ixgbevf_dev_set_mtu,
 587         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 588         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 589         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 590         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 591         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 592         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 593         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 594         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 595         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 596         .mac_addr_add         = ixgbevf_add_mac_addr,
 597         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 598         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 599         .rxq_info_get         = ixgbe_rxq_info_get,
 600         .txq_info_get         = ixgbe_txq_info_get,
 601         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 602         .get_reg              = ixgbevf_get_regs,
 603         .reta_update          = ixgbe_dev_rss_reta_update,
 604         .reta_query           = ixgbe_dev_rss_reta_query,
 605         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 606         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 607         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 608         .get_monitor_addr     = ixgbe_get_monitor_addr,
 609 };
 610
 611 /* store statistics names and its offset in stats structure */
 612 struct rte_ixgbe_xstats_name_off {
 613         char name[RTE_ETH_XSTATS_NAME_SIZE];
 614         unsigned offset;
 615 };
 616
 617 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 618         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 619         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 620         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 621         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 622         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 623         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 624         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 625         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 626         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 627         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 628         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 629         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 630         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 631         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 632         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 633                 prc1023)},
 634         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 635                 prc1522)},
 636         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 637         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 638         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 639         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 640         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 641         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 642         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 643         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 644         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 645         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 646         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 647         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 648         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 649         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 650         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 651         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 652         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 653                 ptc1023)},
 654         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 655                 ptc1522)},
 656         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 657         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 658         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 659         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 660
 661         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 662                 fdirustat_add)},
 663         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 664                 fdirustat_remove)},
 665         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 666                 fdirfstat_fadd)},
 667         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 668                 fdirfstat_fremove)},
 669         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 670                 fdirmatch)},
 671         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 672                 fdirmiss)},
 673
 674         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 675         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 676         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 677                 fclast)},
 678         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 679         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 680         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 681         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 682         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 683                 fcoe_noddp)},
 684         {"rx_fcoe_no_direct_data_placement_ext_buff",
 685                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 686
 687         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 688                 lxontxc)},
 689         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 690                 lxonrxc)},
 691         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 692                 lxofftxc)},
 693         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 694                 lxoffrxc)},
 695         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 696 };
 697
 698 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 699                            sizeof(rte_ixgbe_stats_strings[0]))
 700
 701 /* MACsec statistics */
 702 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 703         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 704                 out_pkts_untagged)},
 705         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 706                 out_pkts_encrypted)},
 707         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 708                 out_pkts_protected)},
 709         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 710                 out_octets_encrypted)},
 711         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 712                 out_octets_protected)},
 713         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 714                 in_pkts_untagged)},
 715         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 716                 in_pkts_badtag)},
 717         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 718                 in_pkts_nosci)},
 719         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 720                 in_pkts_unknownsci)},
 721         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 722                 in_octets_decrypted)},
 723         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 724                 in_octets_validated)},
 725         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 726                 in_pkts_unchecked)},
 727         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 728                 in_pkts_delayed)},
 729         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 730                 in_pkts_late)},
 731         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 732                 in_pkts_ok)},
 733         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 734                 in_pkts_invalid)},
 735         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 736                 in_pkts_notvalid)},
 737         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 738                 in_pkts_unusedsa)},
 739         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 740                 in_pkts_notusingsa)},
 741 };
 742
 743 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 744                            sizeof(rte_ixgbe_macsec_strings[0]))
 745
 746 /* Per-queue statistics */
 747 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 748         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 749         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 750         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 751         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 752 };
 753
 754 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 755                            sizeof(rte_ixgbe_rxq_strings[0]))
 756 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 757
 758 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 759         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 760         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 761         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 762                 pxon2offc)},
 763 };
 764
 765 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 766                            sizeof(rte_ixgbe_txq_strings[0]))
 767 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 768
 769 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 770         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 771 };
 772
 773 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 774                 sizeof(rte_ixgbevf_stats_strings[0]))
 775
 776 /*
 777  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 778  */
 779 static inline int
 780 ixgbe_is_sfp(struct ixgbe_hw *hw)
 781 {
 782         switch (hw->phy.type) {
 783         case ixgbe_phy_sfp_avago:
 784         case ixgbe_phy_sfp_ftl:
 785         case ixgbe_phy_sfp_intel:
 786         case ixgbe_phy_sfp_unknown:
 787         case ixgbe_phy_sfp_passive_tyco:
 788         case ixgbe_phy_sfp_passive_unknown:
 789                 return 1;
 790         default:
 791                 return 0;
 792         }
 793 }
 794
 795 static inline int32_t
 796 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 797 {
 798         uint32_t ctrl_ext;
 799         int32_t status;
 800
 801         status = ixgbe_reset_hw(hw);
 802
 803         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 804         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 805         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 806         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 807         IXGBE_WRITE_FLUSH(hw);
 808
 809         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 810                 status = IXGBE_SUCCESS;
 811         return status;
 812 }
 813
 814 static inline void
 815 ixgbe_enable_intr(struct rte_eth_dev *dev)
 816 {
 817         struct ixgbe_interrupt *intr =
 818                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 819         struct ixgbe_hw *hw =
 820                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 821
 822         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 823         IXGBE_WRITE_FLUSH(hw);
 824 }
 825
 826 /*
 827  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 828  */
 829 static void
 830 ixgbe_disable_intr(struct ixgbe_hw *hw)
 831 {
 832         PMD_INIT_FUNC_TRACE();
 833
 834         if (hw->mac.type == ixgbe_mac_82598EB) {
 835                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 836         } else {
 837                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 838                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 839                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 840         }
 841         IXGBE_WRITE_FLUSH(hw);
 842 }
 843
 844 /*
 845  * This function resets queue statistics mapping registers.
 846  * From Niantic datasheet, Initialization of Statistics section:
 847  * "...if software requires the queue counters, the RQSMR and TQSM registers
 848  * must be re-programmed following a device reset.
 849  */
 850 static void
 851 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 852 {
 853         uint32_t i;
 854
 855         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 856                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 857                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 858         }
 859 }
 860
 861
 862 static int
 863 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 864                                   uint16_t queue_id,
 865                                   uint8_t stat_idx,
 866                                   uint8_t is_rx)
 867 {
 868 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 869 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 870 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 871
 872         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 873         struct ixgbe_stat_mapping_registers *stat_mappings =
 874                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 875         uint32_t qsmr_mask = 0;
 876         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 877         uint32_t q_map;
 878         uint8_t n, offset;
 879
 880         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 881                 (hw->mac.type != ixgbe_mac_X540) &&
 882                 (hw->mac.type != ixgbe_mac_X550) &&
 883                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 884                 (hw->mac.type != ixgbe_mac_X550EM_a))
 885                 return -ENOSYS;
 886
 887         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 888                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 889                      queue_id, stat_idx);
 890
 891         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 892         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 893                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 894                 return -EIO;
 895         }
 896         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 897
 898         /* Now clear any previous stat_idx set */
 899         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 900         if (!is_rx)
 901                 stat_mappings->tqsm[n] &= ~clearing_mask;
 902         else
 903                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 904
 905         q_map = (uint32_t)stat_idx;
 906         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 907         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 908         if (!is_rx)
 909                 stat_mappings->tqsm[n] |= qsmr_mask;
 910         else
 911                 stat_mappings->rqsmr[n] |= qsmr_mask;
 912
 913         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 914                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 915                      queue_id, stat_idx);
 916         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 917                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 918
 919         /* Now write the mapping in the appropriate register */
 920         if (is_rx) {
 921                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 922                              stat_mappings->rqsmr[n], n);
 923                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 924         } else {
 925                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 926                              stat_mappings->tqsm[n], n);
 927                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 928         }
 929         return 0;
 930 }
 931
 932 static void
 933 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 934 {
 935         struct ixgbe_stat_mapping_registers *stat_mappings =
 936                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 937         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 938         int i;
 939
 940         /* write whatever was in stat mapping table to the NIC */
 941         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 942                 /* rx */
 943                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 944
 945                 /* tx */
 946                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 947         }
 948 }
 949
 950 static void
 951 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 952 {
 953         uint8_t i;
 954         struct ixgbe_dcb_tc_config *tc;
 955         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 956
 957         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 958         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 959         for (i = 0; i < dcb_max_tc; i++) {
 960                 tc = &dcb_config->tc_config[i];
 961                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 962                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 963                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 964                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 965                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 966                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 967                 tc->pfc = ixgbe_dcb_pfc_disabled;
 968         }
 969
 970         /* Initialize default user to priority mapping, UPx->TC0 */
 971         tc = &dcb_config->tc_config[0];
 972         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 973         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 974         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 975                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 976                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 977         }
 978         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 979         dcb_config->pfc_mode_enable = false;
 980         dcb_config->vt_mode = true;
 981         dcb_config->round_robin_enable = false;
 982         /* support all DCB capabilities in 82599 */
 983         dcb_config->support.capabilities = 0xFF;
 984
 985         /*we only support 4 Tcs for X540, X550 */
 986         if (hw->mac.type == ixgbe_mac_X540 ||
 987                 hw->mac.type == ixgbe_mac_X550 ||
 988                 hw->mac.type == ixgbe_mac_X550EM_x ||
 989                 hw->mac.type == ixgbe_mac_X550EM_a) {
 990                 dcb_config->num_tcs.pg_tcs = 4;
 991                 dcb_config->num_tcs.pfc_tcs = 4;
 992         }
 993 }
 994
 995 /*
 996  * Ensure that all locks are released before first NVM or PHY access
 997  */
 998 static void
 999 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1000 {
1001         uint16_t mask;
1002
1003         /*
1004          * Phy lock should not fail in this early stage. If this is the case,
1005          * it is due to an improper exit of the application.
1006          * So force the release of the faulty lock. Release of common lock
1007          * is done automatically by swfw_sync function.
1008          */
1009         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1010         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1011                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1012         }
1013         ixgbe_release_swfw_semaphore(hw, mask);
1014
1015         /*
1016          * These ones are more tricky since they are common to all ports; but
1017          * swfw_sync retries last long enough (1s) to be almost sure that if
1018          * lock can not be taken it is due to an improper lock of the
1019          * semaphore.
1020          */
1021         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1022         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1023                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1024         }
1025         ixgbe_release_swfw_semaphore(hw, mask);
1026 }
1027
1028 /*
1029  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1030  * It returns 0 on success.
1031  */
1032 static int
1033 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1034 {
1035         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1036         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1037         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1038         struct ixgbe_hw *hw =
1039                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1040         struct ixgbe_vfta *shadow_vfta =
1041                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1042         struct ixgbe_hwstrip *hwstrip =
1043                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1044         struct ixgbe_dcb_config *dcb_config =
1045                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1046         struct ixgbe_filter_info *filter_info =
1047                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1048         struct ixgbe_bw_conf *bw_conf =
1049                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1050         uint32_t ctrl_ext;
1051         uint16_t csum;
1052         int diag, i, ret;
1053
1054         PMD_INIT_FUNC_TRACE();
1055
1056         ixgbe_dev_macsec_setting_reset(eth_dev);
1057
1058         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1059         eth_dev->rx_queue_count       = ixgbe_dev_rx_queue_count;
1060         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1061         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1062         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1063         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1064         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1065         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1066
1067         /*
1068          * For secondary processes, we don't initialise any further as primary
1069          * has already done this work. Only check we don't need a different
1070          * RX and TX function.
1071          */
1072         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1073                 struct ixgbe_tx_queue *txq;
1074                 /* TX queue function in primary, set by last queue initialized
1075                  * Tx queue may not initialized by primary process
1076                  */
1077                 if (eth_dev->data->tx_queues) {
1078                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1079                         ixgbe_set_tx_function(eth_dev, txq);
1080                 } else {
1081                         /* Use default TX function if we get here */
1082                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1083                                      "Using default TX function.");
1084                 }
1085
1086                 ixgbe_set_rx_function(eth_dev);
1087
1088                 return 0;
1089         }
1090
1091         rte_atomic32_clear(&ad->link_thread_running);
1092         rte_eth_copy_pci_info(eth_dev, pci_dev);
1093         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1094
1095         /* Vendor and Device ID need to be set before init of shared code */
1096         hw->device_id = pci_dev->id.device_id;
1097         hw->vendor_id = pci_dev->id.vendor_id;
1098         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1099         hw->allow_unsupported_sfp = 1;
1100
1101         /* Initialize the shared code (base driver) */
1102 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1103         diag = ixgbe_bypass_init_shared_code(hw);
1104 #else
1105         diag = ixgbe_init_shared_code(hw);
1106 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1107
1108         if (diag != IXGBE_SUCCESS) {
1109                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1110                 return -EIO;
1111         }
1112
1113         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1114                 PMD_INIT_LOG(ERR, "\nERROR: "
1115                         "Firmware recovery mode detected. Limiting functionality.\n"
1116                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1117                         "User Guide for details on firmware recovery mode.");
1118                 return -EIO;
1119         }
1120
1121         /* pick up the PCI bus settings for reporting later */
1122         ixgbe_get_bus_info(hw);
1123
1124         /* Unlock any pending hardware semaphore */
1125         ixgbe_swfw_lock_reset(hw);
1126
1127 #ifdef RTE_LIB_SECURITY
1128         /* Initialize security_ctx only for primary process*/
1129         if (ixgbe_ipsec_ctx_create(eth_dev))
1130                 return -ENOMEM;
1131 #endif
1132
1133         /* Initialize DCB configuration*/
1134         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1135         ixgbe_dcb_init(hw, dcb_config);
1136         /* Get Hardware Flow Control setting */
1137         hw->fc.requested_mode = ixgbe_fc_none;
1138         hw->fc.current_mode = ixgbe_fc_none;
1139         hw->fc.pause_time = IXGBE_FC_PAUSE;
1140         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1141                 hw->fc.low_water[i] = IXGBE_FC_LO;
1142                 hw->fc.high_water[i] = IXGBE_FC_HI;
1143         }
1144         hw->fc.send_xon = 1;
1145
1146         /* Make sure we have a good EEPROM before we read from it */
1147         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1148         if (diag != IXGBE_SUCCESS) {
1149                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1150                 return -EIO;
1151         }
1152
1153 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1154         diag = ixgbe_bypass_init_hw(hw);
1155 #else
1156         diag = ixgbe_init_hw(hw);
1157 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1158
1159         /*
1160          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1161          * is called too soon after the kernel driver unbinding/binding occurs.
1162          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1163          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1164          * also called. See ixgbe_identify_phy_82599(). The reason for the
1165          * failure is not known, and only occuts when virtualisation features
1166          * are disabled in the bios. A delay of 100ms  was found to be enough by
1167          * trial-and-error, and is doubled to be safe.
1168          */
1169         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1170                 rte_delay_ms(200);
1171                 diag = ixgbe_init_hw(hw);
1172         }
1173
1174         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1175                 diag = IXGBE_SUCCESS;
1176
1177         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1178                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1179                              "LOM.  Please be aware there may be issues associated "
1180                              "with your hardware.");
1181                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1182                              "please contact your Intel or hardware representative "
1183                              "who provided you with this hardware.");
1184         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1185                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1186         if (diag) {
1187                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1188                 return -EIO;
1189         }
1190
1191         /* Reset the hw statistics */
1192         ixgbe_dev_stats_reset(eth_dev);
1193
1194         /* disable interrupt */
1195         ixgbe_disable_intr(hw);
1196
1197         /* reset mappings for queue statistics hw counters*/
1198         ixgbe_reset_qstat_mappings(hw);
1199
1200         /* Allocate memory for storing MAC addresses */
1201         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1202                                                hw->mac.num_rar_entries, 0);
1203         if (eth_dev->data->mac_addrs == NULL) {
1204                 PMD_INIT_LOG(ERR,
1205                              "Failed to allocate %u bytes needed to store "
1206                              "MAC addresses",
1207                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1208                 return -ENOMEM;
1209         }
1210         /* Copy the permanent MAC address */
1211         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1212                         &eth_dev->data->mac_addrs[0]);
1213
1214         /* Allocate memory for storing hash filter MAC addresses */
1215         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1216                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1217         if (eth_dev->data->hash_mac_addrs == NULL) {
1218                 PMD_INIT_LOG(ERR,
1219                              "Failed to allocate %d bytes needed to store MAC addresses",
1220                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1221                 return -ENOMEM;
1222         }
1223
1224         /* initialize the vfta */
1225         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1226
1227         /* initialize the hw strip bitmap*/
1228         memset(hwstrip, 0, sizeof(*hwstrip));
1229
1230         /* initialize PF if max_vfs not zero */
1231         ret = ixgbe_pf_host_init(eth_dev);
1232         if (ret) {
1233                 rte_free(eth_dev->data->mac_addrs);
1234                 eth_dev->data->mac_addrs = NULL;
1235                 rte_free(eth_dev->data->hash_mac_addrs);
1236                 eth_dev->data->hash_mac_addrs = NULL;
1237                 return ret;
1238         }
1239
1240         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1241         /* let hardware know driver is loaded */
1242         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1243         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1244         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1245         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1246         IXGBE_WRITE_FLUSH(hw);
1247
1248         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1249                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1250                              (int) hw->mac.type, (int) hw->phy.type,
1251                              (int) hw->phy.sfp_type);
1252         else
1253                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1254                              (int) hw->mac.type, (int) hw->phy.type);
1255
1256         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1257                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1258                      pci_dev->id.device_id);
1259
1260         rte_intr_callback_register(intr_handle,
1261                                    ixgbe_dev_interrupt_handler, eth_dev);
1262
1263         /* enable uio/vfio intr/eventfd mapping */
1264         rte_intr_enable(intr_handle);
1265
1266         /* enable support intr */
1267         ixgbe_enable_intr(eth_dev);
1268
1269         /* initialize filter info */
1270         memset(filter_info, 0,
1271                sizeof(struct ixgbe_filter_info));
1272
1273         /* initialize 5tuple filter list */
1274         TAILQ_INIT(&filter_info->fivetuple_list);
1275
1276         /* initialize flow director filter list & hash */
1277         ixgbe_fdir_filter_init(eth_dev);
1278
1279         /* initialize l2 tunnel filter list & hash */
1280         ixgbe_l2_tn_filter_init(eth_dev);
1281
1282         /* initialize flow filter lists */
1283         ixgbe_filterlist_init();
1284
1285         /* initialize bandwidth configuration info */
1286         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1287
1288         /* initialize Traffic Manager configuration */
1289         ixgbe_tm_conf_init(eth_dev);
1290
1291         return 0;
1292 }
1293
1294 static int
1295 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1296 {
1297         PMD_INIT_FUNC_TRACE();
1298
1299         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1300                 return 0;
1301
1302         ixgbe_dev_close(eth_dev);
1303
1304         return 0;
1305 }
1306
1307 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1308 {
1309         struct ixgbe_filter_info *filter_info =
1310                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1311         struct ixgbe_5tuple_filter *p_5tuple;
1312
1313         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1314                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1315                              p_5tuple,
1316                              entries);
1317                 rte_free(p_5tuple);
1318         }
1319         memset(filter_info->fivetuple_mask, 0,
1320                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1321
1322         return 0;
1323 }
1324
1325 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1326 {
1327         struct ixgbe_hw_fdir_info *fdir_info =
1328                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1329         struct ixgbe_fdir_filter *fdir_filter;
1330
1331                 if (fdir_info->hash_map)
1332                 rte_free(fdir_info->hash_map);
1333         if (fdir_info->hash_handle)
1334                 rte_hash_free(fdir_info->hash_handle);
1335
1336         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1337                 TAILQ_REMOVE(&fdir_info->fdir_list,
1338                              fdir_filter,
1339                              entries);
1340                 rte_free(fdir_filter);
1341         }
1342
1343         return 0;
1344 }
1345
1346 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1347 {
1348         struct ixgbe_l2_tn_info *l2_tn_info =
1349                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1350         struct ixgbe_l2_tn_filter *l2_tn_filter;
1351
1352         if (l2_tn_info->hash_map)
1353                 rte_free(l2_tn_info->hash_map);
1354         if (l2_tn_info->hash_handle)
1355                 rte_hash_free(l2_tn_info->hash_handle);
1356
1357         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1358                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1359                              l2_tn_filter,
1360                              entries);
1361                 rte_free(l2_tn_filter);
1362         }
1363
1364         return 0;
1365 }
1366
1367 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1368 {
1369         struct ixgbe_hw_fdir_info *fdir_info =
1370                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1371         char fdir_hash_name[RTE_HASH_NAMESIZE];
1372         struct rte_hash_parameters fdir_hash_params = {
1373                 .name = fdir_hash_name,
1374                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1375                 .key_len = sizeof(union ixgbe_atr_input),
1376                 .hash_func = rte_hash_crc,
1377                 .hash_func_init_val = 0,
1378                 .socket_id = rte_socket_id(),
1379         };
1380
1381         TAILQ_INIT(&fdir_info->fdir_list);
1382         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1383                  "fdir_%s", eth_dev->device->name);
1384         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1385         if (!fdir_info->hash_handle) {
1386                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1387                 return -EINVAL;
1388         }
1389         fdir_info->hash_map = rte_zmalloc("ixgbe",
1390                                           sizeof(struct ixgbe_fdir_filter *) *
1391                                           IXGBE_MAX_FDIR_FILTER_NUM,
1392                                           0);
1393         if (!fdir_info->hash_map) {
1394                 PMD_INIT_LOG(ERR,
1395                              "Failed to allocate memory for fdir hash map!");
1396                 return -ENOMEM;
1397         }
1398         fdir_info->mask_added = FALSE;
1399
1400         return 0;
1401 }
1402
1403 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1404 {
1405         struct ixgbe_l2_tn_info *l2_tn_info =
1406                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1407         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1408         struct rte_hash_parameters l2_tn_hash_params = {
1409                 .name = l2_tn_hash_name,
1410                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1411                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1412                 .hash_func = rte_hash_crc,
1413                 .hash_func_init_val = 0,
1414                 .socket_id = rte_socket_id(),
1415         };
1416
1417         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1418         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1419                  "l2_tn_%s", eth_dev->device->name);
1420         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1421         if (!l2_tn_info->hash_handle) {
1422                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1423                 return -EINVAL;
1424         }
1425         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1426                                    sizeof(struct ixgbe_l2_tn_filter *) *
1427                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1428                                    0);
1429         if (!l2_tn_info->hash_map) {
1430                 PMD_INIT_LOG(ERR,
1431                         "Failed to allocate memory for L2 TN hash map!");
1432                 return -ENOMEM;
1433         }
1434         l2_tn_info->e_tag_en = FALSE;
1435         l2_tn_info->e_tag_fwd_en = FALSE;
1436         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1437
1438         return 0;
1439 }
1440 /*
1441  * Negotiate mailbox API version with the PF.
1442  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1443  * Then we try to negotiate starting with the most recent one.
1444  * If all negotiation attempts fail, then we will proceed with
1445  * the default one (ixgbe_mbox_api_10).
1446  */
1447 static void
1448 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1449 {
1450         int32_t i;
1451
1452         /* start with highest supported, proceed down */
1453         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1454                 ixgbe_mbox_api_13,
1455                 ixgbe_mbox_api_12,
1456                 ixgbe_mbox_api_11,
1457                 ixgbe_mbox_api_10,
1458         };
1459
1460         for (i = 0;
1461                         i != RTE_DIM(sup_ver) &&
1462                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1463                         i++)
1464                 ;
1465 }
1466
1467 static void
1468 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1469 {
1470         uint64_t random;
1471
1472         /* Set Organizationally Unique Identifier (OUI) prefix. */
1473         mac_addr->addr_bytes[0] = 0x00;
1474         mac_addr->addr_bytes[1] = 0x09;
1475         mac_addr->addr_bytes[2] = 0xC0;
1476         /* Force indication of locally assigned MAC address. */
1477         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1478         /* Generate the last 3 bytes of the MAC address with a random number. */
1479         random = rte_rand();
1480         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1481 }
1482
1483 static int
1484 devarg_handle_int(__rte_unused const char *key, const char *value,
1485                   void *extra_args)
1486 {
1487         uint16_t *n = extra_args;
1488
1489         if (value == NULL || extra_args == NULL)
1490                 return -EINVAL;
1491
1492         *n = (uint16_t)strtoul(value, NULL, 0);
1493         if (*n == USHRT_MAX && errno == ERANGE)
1494                 return -1;
1495
1496         return 0;
1497 }
1498
1499 static void
1500 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1501                       struct rte_devargs *devargs)
1502 {
1503         struct rte_kvargs *kvlist;
1504         uint16_t pflink_fullchk;
1505
1506         if (devargs == NULL)
1507                 return;
1508
1509         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1510         if (kvlist == NULL)
1511                 return;
1512
1513         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1514             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1515                                devarg_handle_int, &pflink_fullchk) == 0 &&
1516             pflink_fullchk == 1)
1517                 adapter->pflink_fullchk = 1;
1518
1519         rte_kvargs_free(kvlist);
1520 }
1521
1522 /*
1523  * Virtual Function device init
1524  */
1525 static int
1526 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1527 {
1528         int diag;
1529         uint32_t tc, tcs;
1530         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1531         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1532         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1533         struct ixgbe_hw *hw =
1534                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1535         struct ixgbe_vfta *shadow_vfta =
1536                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1537         struct ixgbe_hwstrip *hwstrip =
1538                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1539         struct rte_ether_addr *perm_addr =
1540                 (struct rte_ether_addr *)hw->mac.perm_addr;
1541
1542         PMD_INIT_FUNC_TRACE();
1543
1544         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1545         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1546         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1547         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1548         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1549         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1550
1551         /* for secondary processes, we don't initialise any further as primary
1552          * has already done this work. Only check we don't need a different
1553          * RX function
1554          */
1555         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1556                 struct ixgbe_tx_queue *txq;
1557                 /* TX queue function in primary, set by last queue initialized
1558                  * Tx queue may not initialized by primary process
1559                  */
1560                 if (eth_dev->data->tx_queues) {
1561                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1562                         ixgbe_set_tx_function(eth_dev, txq);
1563                 } else {
1564                         /* Use default TX function if we get here */
1565                         PMD_INIT_LOG(NOTICE,
1566                                      "No TX queues configured yet. Using default TX function.");
1567                 }
1568
1569                 ixgbe_set_rx_function(eth_dev);
1570
1571                 return 0;
1572         }
1573
1574         rte_atomic32_clear(&ad->link_thread_running);
1575         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1576                               pci_dev->device.devargs);
1577
1578         rte_eth_copy_pci_info(eth_dev, pci_dev);
1579         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1580
1581         hw->device_id = pci_dev->id.device_id;
1582         hw->vendor_id = pci_dev->id.vendor_id;
1583         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1584
1585         /* initialize the vfta */
1586         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1587
1588         /* initialize the hw strip bitmap*/
1589         memset(hwstrip, 0, sizeof(*hwstrip));
1590
1591         /* Initialize the shared code (base driver) */
1592         diag = ixgbe_init_shared_code(hw);
1593         if (diag != IXGBE_SUCCESS) {
1594                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1595                 return -EIO;
1596         }
1597
1598         /* init_mailbox_params */
1599         hw->mbx.ops.init_params(hw);
1600
1601         /* Reset the hw statistics */
1602         ixgbevf_dev_stats_reset(eth_dev);
1603
1604         /* Disable the interrupts for VF */
1605         ixgbevf_intr_disable(eth_dev);
1606
1607         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1608         diag = hw->mac.ops.reset_hw(hw);
1609
1610         /*
1611          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1612          * the underlying PF driver has not assigned a MAC address to the VF.
1613          * In this case, assign a random MAC address.
1614          */
1615         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1616                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1617                 /*
1618                  * This error code will be propagated to the app by
1619                  * rte_eth_dev_reset, so use a public error code rather than
1620                  * the internal-only IXGBE_ERR_RESET_FAILED
1621                  */
1622                 return -EAGAIN;
1623         }
1624
1625         /* negotiate mailbox API version to use with the PF. */
1626         ixgbevf_negotiate_api(hw);
1627
1628         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1629         ixgbevf_get_queues(hw, &tcs, &tc);
1630
1631         /* Allocate memory for storing MAC addresses */
1632         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1633                                                hw->mac.num_rar_entries, 0);
1634         if (eth_dev->data->mac_addrs == NULL) {
1635                 PMD_INIT_LOG(ERR,
1636                              "Failed to allocate %u bytes needed to store "
1637                              "MAC addresses",
1638                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1639                 return -ENOMEM;
1640         }
1641
1642         /* Generate a random MAC address, if none was assigned by PF. */
1643         if (rte_is_zero_ether_addr(perm_addr)) {
1644                 generate_random_mac_addr(perm_addr);
1645                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1646                 if (diag) {
1647                         rte_free(eth_dev->data->mac_addrs);
1648                         eth_dev->data->mac_addrs = NULL;
1649                         return diag;
1650                 }
1651                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1652                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1653                              RTE_ETHER_ADDR_PRT_FMT,
1654                                  RTE_ETHER_ADDR_BYTES(perm_addr));
1655         }
1656
1657         /* Copy the permanent MAC address */
1658         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1659
1660         /* reset the hardware with the new settings */
1661         diag = hw->mac.ops.start_hw(hw);
1662         switch (diag) {
1663         case  0:
1664                 break;
1665
1666         default:
1667                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1668                 return -EIO;
1669         }
1670
1671         rte_intr_callback_register(intr_handle,
1672                                    ixgbevf_dev_interrupt_handler, eth_dev);
1673         rte_intr_enable(intr_handle);
1674         ixgbevf_intr_enable(eth_dev);
1675
1676         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1677                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1678                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1679
1680         return 0;
1681 }
1682
1683 /* Virtual Function device uninit */
1684
1685 static int
1686 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1687 {
1688         PMD_INIT_FUNC_TRACE();
1689
1690         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1691                 return 0;
1692
1693         ixgbevf_dev_close(eth_dev);
1694
1695         return 0;
1696 }
1697
1698 static int
1699 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1700                 struct rte_pci_device *pci_dev)
1701 {
1702         char name[RTE_ETH_NAME_MAX_LEN];
1703         struct rte_eth_dev *pf_ethdev;
1704         struct rte_eth_devargs eth_da;
1705         int i, retval;
1706
1707         if (pci_dev->device.devargs) {
1708                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1709                                 &eth_da);
1710                 if (retval)
1711                         return retval;
1712         } else
1713                 memset(&eth_da, 0, sizeof(eth_da));
1714
1715         if (eth_da.nb_representor_ports > 0 &&
1716             eth_da.type != RTE_ETH_REPRESENTOR_VF) {
1717                 PMD_DRV_LOG(ERR, "unsupported representor type: %s\n",
1718                             pci_dev->device.devargs->args);
1719                 return -ENOTSUP;
1720         }
1721
1722         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1723                 sizeof(struct ixgbe_adapter),
1724                 eth_dev_pci_specific_init, pci_dev,
1725                 eth_ixgbe_dev_init, NULL);
1726
1727         if (retval || eth_da.nb_representor_ports < 1)
1728                 return retval;
1729
1730         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1731         if (pf_ethdev == NULL)
1732                 return -ENODEV;
1733
1734         /* probe VF representor ports */
1735         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1736                 struct ixgbe_vf_info *vfinfo;
1737                 struct ixgbe_vf_representor representor;
1738
1739                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1740                         pf_ethdev->data->dev_private);
1741                 if (vfinfo == NULL) {
1742                         PMD_DRV_LOG(ERR,
1743                                 "no virtual functions supported by PF");
1744                         break;
1745                 }
1746
1747                 representor.vf_id = eth_da.representor_ports[i];
1748                 representor.switch_domain_id = vfinfo->switch_domain_id;
1749                 representor.pf_ethdev = pf_ethdev;
1750
1751                 /* representor port net_bdf_port */
1752                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1753                         pci_dev->device.name,
1754                         eth_da.representor_ports[i]);
1755
1756                 retval = rte_eth_dev_create(&pci_dev->device, name,
1757                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1758                         ixgbe_vf_representor_init, &representor);
1759
1760                 if (retval)
1761                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1762                                 "representor %s.", name);
1763         }
1764
1765         return 0;
1766 }
1767
1768 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1769 {
1770         struct rte_eth_dev *ethdev;
1771
1772         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1773         if (!ethdev)
1774                 return 0;
1775
1776         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1777                 return rte_eth_dev_pci_generic_remove(pci_dev,
1778                                         ixgbe_vf_representor_uninit);
1779         else
1780                 return rte_eth_dev_pci_generic_remove(pci_dev,
1781                                                 eth_ixgbe_dev_uninit);
1782 }
1783
1784 static struct rte_pci_driver rte_ixgbe_pmd = {
1785         .id_table = pci_id_ixgbe_map,
1786         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1787         .probe = eth_ixgbe_pci_probe,
1788         .remove = eth_ixgbe_pci_remove,
1789 };
1790
1791 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1792         struct rte_pci_device *pci_dev)
1793 {
1794         return rte_eth_dev_pci_generic_probe(pci_dev,
1795                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1796 }
1797
1798 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1799 {
1800         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1801 }
1802
1803 /*
1804  * virtual function driver struct
1805  */
1806 static struct rte_pci_driver rte_ixgbevf_pmd = {
1807         .id_table = pci_id_ixgbevf_map,
1808         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1809         .probe = eth_ixgbevf_pci_probe,
1810         .remove = eth_ixgbevf_pci_remove,
1811 };
1812
1813 static int
1814 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1815 {
1816         struct ixgbe_hw *hw =
1817                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1818         struct ixgbe_vfta *shadow_vfta =
1819                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1820         uint32_t vfta;
1821         uint32_t vid_idx;
1822         uint32_t vid_bit;
1823
1824         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1825         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1826         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1827         if (on)
1828                 vfta |= vid_bit;
1829         else
1830                 vfta &= ~vid_bit;
1831         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1832
1833         /* update local VFTA copy */
1834         shadow_vfta->vfta[vid_idx] = vfta;
1835
1836         return 0;
1837 }
1838
1839 static void
1840 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1841 {
1842         if (on)
1843                 ixgbe_vlan_hw_strip_enable(dev, queue);
1844         else
1845                 ixgbe_vlan_hw_strip_disable(dev, queue);
1846 }
1847
1848 static int
1849 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1850                     enum rte_vlan_type vlan_type,
1851                     uint16_t tpid)
1852 {
1853         struct ixgbe_hw *hw =
1854                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1855         int ret = 0;
1856         uint32_t reg;
1857         uint32_t qinq;
1858
1859         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1860         qinq &= IXGBE_DMATXCTL_GDV;
1861
1862         switch (vlan_type) {
1863         case ETH_VLAN_TYPE_INNER:
1864                 if (qinq) {
1865                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1866                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1867                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1868                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1869                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1870                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1871                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1872                 } else {
1873                         ret = -ENOTSUP;
1874                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1875                                     " by single VLAN");
1876                 }
1877                 break;
1878         case ETH_VLAN_TYPE_OUTER:
1879                 if (qinq) {
1880                         /* Only the high 16-bits is valid */
1881                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1882                                         IXGBE_EXVET_VET_EXT_SHIFT);
1883                 } else {
1884                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1885                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1886                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1887                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1888                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1889                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1890                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1891                 }
1892
1893                 break;
1894         default:
1895                 ret = -EINVAL;
1896                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1897                 break;
1898         }
1899
1900         return ret;
1901 }
1902
1903 void
1904 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1905 {
1906         struct ixgbe_hw *hw =
1907                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1908         uint32_t vlnctrl;
1909
1910         PMD_INIT_FUNC_TRACE();
1911
1912         /* Filter Table Disable */
1913         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1914         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1915
1916         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1917 }
1918
1919 void
1920 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1921 {
1922         struct ixgbe_hw *hw =
1923                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1924         struct ixgbe_vfta *shadow_vfta =
1925                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1926         uint32_t vlnctrl;
1927         uint16_t i;
1928
1929         PMD_INIT_FUNC_TRACE();
1930
1931         /* Filter Table Enable */
1932         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1933         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1934         vlnctrl |= IXGBE_VLNCTRL_VFE;
1935
1936         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1937
1938         /* write whatever is in local vfta copy */
1939         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1940                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1941 }
1942
1943 static void
1944 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1945 {
1946         struct ixgbe_hwstrip *hwstrip =
1947                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1948         struct ixgbe_rx_queue *rxq;
1949
1950         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1951                 return;
1952
1953         if (on)
1954                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1955         else
1956                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1957
1958         if (queue >= dev->data->nb_rx_queues)
1959                 return;
1960
1961         rxq = dev->data->rx_queues[queue];
1962
1963         if (on) {
1964                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1965                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1966         } else {
1967                 rxq->vlan_flags = PKT_RX_VLAN;
1968                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1969         }
1970 }
1971
1972 static void
1973 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1974 {
1975         struct ixgbe_hw *hw =
1976                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1977         uint32_t ctrl;
1978
1979         PMD_INIT_FUNC_TRACE();
1980
1981         if (hw->mac.type == ixgbe_mac_82598EB) {
1982                 /* No queue level support */
1983                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1984                 return;
1985         }
1986
1987         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1988         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1989         ctrl &= ~IXGBE_RXDCTL_VME;
1990         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1991
1992         /* record those setting for HW strip per queue */
1993         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1994 }
1995
1996 static void
1997 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1998 {
1999         struct ixgbe_hw *hw =
2000                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2001         uint32_t ctrl;
2002
2003         PMD_INIT_FUNC_TRACE();
2004
2005         if (hw->mac.type == ixgbe_mac_82598EB) {
2006                 /* No queue level supported */
2007                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2008                 return;
2009         }
2010
2011         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2012         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2013         ctrl |= IXGBE_RXDCTL_VME;
2014         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2015
2016         /* record those setting for HW strip per queue */
2017         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2018 }
2019
2020 static void
2021 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2022 {
2023         struct ixgbe_hw *hw =
2024                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2025         uint32_t ctrl;
2026
2027         PMD_INIT_FUNC_TRACE();
2028
2029         /* DMATXCTRL: Geric Double VLAN Disable */
2030         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2031         ctrl &= ~IXGBE_DMATXCTL_GDV;
2032         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2033
2034         /* CTRL_EXT: Global Double VLAN Disable */
2035         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2036         ctrl &= ~IXGBE_EXTENDED_VLAN;
2037         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2038
2039 }
2040
2041 static void
2042 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2043 {
2044         struct ixgbe_hw *hw =
2045                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2046         uint32_t ctrl;
2047
2048         PMD_INIT_FUNC_TRACE();
2049
2050         /* DMATXCTRL: Geric Double VLAN Enable */
2051         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2052         ctrl |= IXGBE_DMATXCTL_GDV;
2053         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2054
2055         /* CTRL_EXT: Global Double VLAN Enable */
2056         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2057         ctrl |= IXGBE_EXTENDED_VLAN;
2058         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2059
2060         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2061         if (hw->mac.type == ixgbe_mac_X550 ||
2062             hw->mac.type == ixgbe_mac_X550EM_x ||
2063             hw->mac.type == ixgbe_mac_X550EM_a) {
2064                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2065                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2066                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2067         }
2068
2069         /*
2070          * VET EXT field in the EXVET register = 0x8100 by default
2071          * So no need to change. Same to VT field of DMATXCTL register
2072          */
2073 }
2074
2075 void
2076 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2077 {
2078         struct ixgbe_hw *hw =
2079                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2080         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2081         uint32_t ctrl;
2082         uint16_t i;
2083         struct ixgbe_rx_queue *rxq;
2084         bool on;
2085
2086         PMD_INIT_FUNC_TRACE();
2087
2088         if (hw->mac.type == ixgbe_mac_82598EB) {
2089                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2090                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2091                         ctrl |= IXGBE_VLNCTRL_VME;
2092                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2093                 } else {
2094                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2095                         ctrl &= ~IXGBE_VLNCTRL_VME;
2096                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2097                 }
2098         } else {
2099                 /*
2100                  * Other 10G NIC, the VLAN strip can be setup
2101                  * per queue in RXDCTL
2102                  */
2103                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2104                         rxq = dev->data->rx_queues[i];
2105                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2106                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2107                                 ctrl |= IXGBE_RXDCTL_VME;
2108                                 on = TRUE;
2109                         } else {
2110                                 ctrl &= ~IXGBE_RXDCTL_VME;
2111                                 on = FALSE;
2112                         }
2113                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2114
2115                         /* record those setting for HW strip per queue */
2116                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2117                 }
2118         }
2119 }
2120
2121 static void
2122 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2123 {
2124         uint16_t i;
2125         struct rte_eth_rxmode *rxmode;
2126         struct ixgbe_rx_queue *rxq;
2127
2128         if (mask & ETH_VLAN_STRIP_MASK) {
2129                 rxmode = &dev->data->dev_conf.rxmode;
2130                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2131                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2132                                 rxq = dev->data->rx_queues[i];
2133                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2134                         }
2135                 else
2136                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2137                                 rxq = dev->data->rx_queues[i];
2138                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2139                         }
2140         }
2141 }
2142
2143 static int
2144 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2145 {
2146         struct rte_eth_rxmode *rxmode;
2147         rxmode = &dev->data->dev_conf.rxmode;
2148
2149         if (mask & ETH_VLAN_STRIP_MASK) {
2150                 ixgbe_vlan_hw_strip_config(dev);
2151         }
2152
2153         if (mask & ETH_VLAN_FILTER_MASK) {
2154                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2155                         ixgbe_vlan_hw_filter_enable(dev);
2156                 else
2157                         ixgbe_vlan_hw_filter_disable(dev);
2158         }
2159
2160         if (mask & ETH_VLAN_EXTEND_MASK) {
2161                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2162                         ixgbe_vlan_hw_extend_enable(dev);
2163                 else
2164                         ixgbe_vlan_hw_extend_disable(dev);
2165         }
2166
2167         return 0;
2168 }
2169
2170 static int
2171 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2172 {
2173         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2174
2175         ixgbe_vlan_offload_config(dev, mask);
2176
2177         return 0;
2178 }
2179
2180 static void
2181 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2182 {
2183         struct ixgbe_hw *hw =
2184                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2185         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2186         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2187
2188         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2189         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2190 }
2191
2192 static int
2193 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2194 {
2195         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2196
2197         switch (nb_rx_q) {
2198         case 1:
2199         case 2:
2200                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2201                 break;
2202         case 4:
2203                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2204                 break;
2205         default:
2206                 return -EINVAL;
2207         }
2208
2209         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2210                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2211         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2212                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2213         return 0;
2214 }
2215
2216 static int
2217 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2218 {
2219         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2220         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2221         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2222         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2223
2224         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2225                 /* check multi-queue mode */
2226                 switch (dev_conf->rxmode.mq_mode) {
2227                 case ETH_MQ_RX_VMDQ_DCB:
2228                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2229                         break;
2230                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2231                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2232                         PMD_INIT_LOG(ERR, "SRIOV active,"
2233                                         " unsupported mq_mode rx %d.",
2234                                         dev_conf->rxmode.mq_mode);
2235                         return -EINVAL;
2236                 case ETH_MQ_RX_RSS:
2237                 case ETH_MQ_RX_VMDQ_RSS:
2238                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2239                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2240                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2241                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2242                                                 " invalid queue number"
2243                                                 " for VMDQ RSS, allowed"
2244                                                 " value are 1, 2 or 4.");
2245                                         return -EINVAL;
2246                                 }
2247                         break;
2248                 case ETH_MQ_RX_VMDQ_ONLY:
2249                 case ETH_MQ_RX_NONE:
2250                         /* if nothing mq mode configure, use default scheme */
2251                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2252                         break;
2253                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2254                         /* SRIOV only works in VMDq enable mode */
2255                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2256                                         " wrong mq_mode rx %d.",
2257                                         dev_conf->rxmode.mq_mode);
2258                         return -EINVAL;
2259                 }
2260
2261                 switch (dev_conf->txmode.mq_mode) {
2262                 case ETH_MQ_TX_VMDQ_DCB:
2263                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2264                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2265                         break;
2266                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2267                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2268                         break;
2269                 }
2270
2271                 /* check valid queue number */
2272                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2273                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2274                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2275                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2276                                         " must be less than or equal to %d.",
2277                                         nb_rx_q, nb_tx_q,
2278                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2279                         return -EINVAL;
2280                 }
2281         } else {
2282                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2283                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2284                                           " not supported.");
2285                         return -EINVAL;
2286                 }
2287                 /* check configuration for vmdb+dcb mode */
2288                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2289                         const struct rte_eth_vmdq_dcb_conf *conf;
2290
2291                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2292                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2293                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2294                                 return -EINVAL;
2295                         }
2296                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2297                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2298                                conf->nb_queue_pools == ETH_32_POOLS)) {
2299                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2300                                                 " nb_queue_pools must be %d or %d.",
2301                                                 ETH_16_POOLS, ETH_32_POOLS);
2302                                 return -EINVAL;
2303                         }
2304                 }
2305                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2306                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2307
2308                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2309                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2310                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2311                                 return -EINVAL;
2312                         }
2313                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2314                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2315                                conf->nb_queue_pools == ETH_32_POOLS)) {
2316                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2317                                                 " nb_queue_pools != %d and"
2318                                                 " nb_queue_pools != %d.",
2319                                                 ETH_16_POOLS, ETH_32_POOLS);
2320                                 return -EINVAL;
2321                         }
2322                 }
2323
2324                 /* For DCB mode check our configuration before we go further */
2325                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2326                         const struct rte_eth_dcb_rx_conf *conf;
2327
2328                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2329                         if (!(conf->nb_tcs == ETH_4_TCS ||
2330                                conf->nb_tcs == ETH_8_TCS)) {
2331                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2332                                                 " and nb_tcs != %d.",
2333                                                 ETH_4_TCS, ETH_8_TCS);
2334                                 return -EINVAL;
2335                         }
2336                 }
2337
2338                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2339                         const struct rte_eth_dcb_tx_conf *conf;
2340
2341                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2342                         if (!(conf->nb_tcs == ETH_4_TCS ||
2343                                conf->nb_tcs == ETH_8_TCS)) {
2344                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2345                                                 " and nb_tcs != %d.",
2346                                                 ETH_4_TCS, ETH_8_TCS);
2347                                 return -EINVAL;
2348                         }
2349                 }
2350
2351                 /*
2352                  * When DCB/VT is off, maximum number of queues changes,
2353                  * except for 82598EB, which remains constant.
2354                  */
2355                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2356                                 hw->mac.type != ixgbe_mac_82598EB) {
2357                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2358                                 PMD_INIT_LOG(ERR,
2359                                              "Neither VT nor DCB are enabled, "
2360                                              "nb_tx_q > %d.",
2361                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2362                                 return -EINVAL;
2363                         }
2364                 }
2365         }
2366         return 0;
2367 }
2368
2369 static int
2370 ixgbe_dev_configure(struct rte_eth_dev *dev)
2371 {
2372         struct ixgbe_interrupt *intr =
2373                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2374         struct ixgbe_adapter *adapter = dev->data->dev_private;
2375         int ret;
2376
2377         PMD_INIT_FUNC_TRACE();
2378
2379         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2380                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2381
2382         /* multipe queue mode checking */
2383         ret  = ixgbe_check_mq_mode(dev);
2384         if (ret != 0) {
2385                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2386                             ret);
2387                 return ret;
2388         }
2389
2390         /* set flag to update link status after init */
2391         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2392
2393         /*
2394          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2395          * allocation or vector Rx preconditions we will reset it.
2396          */
2397         adapter->rx_bulk_alloc_allowed = true;
2398         adapter->rx_vec_allowed = true;
2399
2400         return 0;
2401 }
2402
2403 static void
2404 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2405 {
2406         struct ixgbe_hw *hw =
2407                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2408         struct ixgbe_interrupt *intr =
2409                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2410         uint32_t gpie;
2411
2412         /* only set up it on X550EM_X */
2413         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2414                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2415                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2416                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2417                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2418                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2419         }
2420 }
2421
2422 int
2423 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2424                         uint16_t tx_rate, uint64_t q_msk)
2425 {
2426         struct ixgbe_hw *hw;
2427         struct ixgbe_vf_info *vfinfo;
2428         struct rte_eth_link link;
2429         uint8_t  nb_q_per_pool;
2430         uint32_t queue_stride;
2431         uint32_t queue_idx, idx = 0, vf_idx;
2432         uint32_t queue_end;
2433         uint16_t total_rate = 0;
2434         struct rte_pci_device *pci_dev;
2435         int ret;
2436
2437         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2438         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2439         if (ret < 0)
2440                 return ret;
2441
2442         if (vf >= pci_dev->max_vfs)
2443                 return -EINVAL;
2444
2445         if (tx_rate > link.link_speed)
2446                 return -EINVAL;
2447
2448         if (q_msk == 0)
2449                 return 0;
2450
2451         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2452         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2453         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2454         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2455         queue_idx = vf * queue_stride;
2456         queue_end = queue_idx + nb_q_per_pool - 1;
2457         if (queue_end >= hw->mac.max_tx_queues)
2458                 return -EINVAL;
2459
2460         if (vfinfo) {
2461                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2462                         if (vf_idx == vf)
2463                                 continue;
2464                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2465                                 idx++)
2466                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2467                 }
2468         } else {
2469                 return -EINVAL;
2470         }
2471
2472         /* Store tx_rate for this vf. */
2473         for (idx = 0; idx < nb_q_per_pool; idx++) {
2474                 if (((uint64_t)0x1 << idx) & q_msk) {
2475                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2476                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2477                         total_rate += tx_rate;
2478                 }
2479         }
2480
2481         if (total_rate > dev->data->dev_link.link_speed) {
2482                 /* Reset stored TX rate of the VF if it causes exceed
2483                  * link speed.
2484                  */
2485                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2486                 return -EINVAL;
2487         }
2488
2489         /* Set RTTBCNRC of each queue/pool for vf X  */
2490         for (; queue_idx <= queue_end; queue_idx++) {
2491                 if (0x1 & q_msk)
2492                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2493                 q_msk = q_msk >> 1;
2494         }
2495
2496         return 0;
2497 }
2498
2499 static int
2500 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2501 {
2502         struct ixgbe_adapter *adapter = dev->data->dev_private;
2503         int err;
2504         uint32_t mflcn;
2505
2506         ixgbe_setup_fc(hw);
2507
2508         err = ixgbe_fc_enable(hw);
2509
2510         /* Not negotiated is not an error case */
2511         if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2512                 /*
2513                  *check if we want to forward MAC frames - driver doesn't
2514                  *have native capability to do that,
2515                  *so we'll write the registers ourselves
2516                  */
2517
2518                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2519
2520                 /* set or clear MFLCN.PMCF bit depending on configuration */
2521                 if (adapter->mac_ctrl_frame_fwd != 0)
2522                         mflcn |= IXGBE_MFLCN_PMCF;
2523                 else
2524                         mflcn &= ~IXGBE_MFLCN_PMCF;
2525
2526                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2527                 IXGBE_WRITE_FLUSH(hw);
2528
2529                 return 0;
2530         }
2531         return err;
2532 }
2533
2534 /*
2535  * Configure device link speed and setup link.
2536  * It returns 0 on success.
2537  */
2538 static int
2539 ixgbe_dev_start(struct rte_eth_dev *dev)
2540 {
2541         struct ixgbe_hw *hw =
2542                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2543         struct ixgbe_vf_info *vfinfo =
2544                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2545         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2546         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2547         uint32_t intr_vector = 0;
2548         int err;
2549         bool link_up = false, negotiate = 0;
2550         uint32_t speed = 0;
2551         uint32_t allowed_speeds = 0;
2552         int mask = 0;
2553         int status;
2554         uint16_t vf, idx;
2555         uint32_t *link_speeds;
2556         struct ixgbe_tm_conf *tm_conf =
2557                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2558         struct ixgbe_macsec_setting *macsec_setting =
2559                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2560
2561         PMD_INIT_FUNC_TRACE();
2562
2563         /* Stop the link setup handler before resetting the HW. */
2564         ixgbe_dev_wait_setup_link_complete(dev, 0);
2565
2566         /* disable uio/vfio intr/eventfd mapping */
2567         rte_intr_disable(intr_handle);
2568
2569         /* stop adapter */
2570         hw->adapter_stopped = 0;
2571         ixgbe_stop_adapter(hw);
2572
2573         /* reinitialize adapter
2574          * this calls reset and start
2575          */
2576         status = ixgbe_pf_reset_hw(hw);
2577         if (status != 0)
2578                 return -1;
2579         hw->mac.ops.start_hw(hw);
2580         hw->mac.get_link_status = true;
2581
2582         /* configure PF module if SRIOV enabled */
2583         ixgbe_pf_host_configure(dev);
2584
2585         ixgbe_dev_phy_intr_setup(dev);
2586
2587         /* check and configure queue intr-vector mapping */
2588         if ((rte_intr_cap_multiple(intr_handle) ||
2589              !RTE_ETH_DEV_SRIOV(dev).active) &&
2590             dev->data->dev_conf.intr_conf.rxq != 0) {
2591                 intr_vector = dev->data->nb_rx_queues;
2592                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2593                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2594                                         IXGBE_MAX_INTR_QUEUE_NUM);
2595                         return -ENOTSUP;
2596                 }
2597                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2598                         return -1;
2599         }
2600
2601         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2602                 intr_handle->intr_vec =
2603                         rte_zmalloc("intr_vec",
2604                                     dev->data->nb_rx_queues * sizeof(int), 0);
2605                 if (intr_handle->intr_vec == NULL) {
2606                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2607                                      " intr_vec", dev->data->nb_rx_queues);
2608                         return -ENOMEM;
2609                 }
2610         }
2611
2612         /* confiugre msix for sleep until rx interrupt */
2613         ixgbe_configure_msix(dev);
2614
2615         /* initialize transmission unit */
2616         ixgbe_dev_tx_init(dev);
2617
2618         /* This can fail when allocating mbufs for descriptor rings */
2619         err = ixgbe_dev_rx_init(dev);
2620         if (err) {
2621                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2622                 goto error;
2623         }
2624
2625         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2626                 ETH_VLAN_EXTEND_MASK;
2627         err = ixgbe_vlan_offload_config(dev, mask);
2628         if (err) {
2629                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2630                 goto error;
2631         }
2632
2633         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2634                 /* Enable vlan filtering for VMDq */
2635                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2636         }
2637
2638         /* Configure DCB hw */
2639         ixgbe_configure_dcb(dev);
2640
2641         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2642                 err = ixgbe_fdir_configure(dev);
2643                 if (err)
2644                         goto error;
2645         }
2646
2647         /* Restore vf rate limit */
2648         if (vfinfo != NULL) {
2649                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2650                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2651                                 if (vfinfo[vf].tx_rate[idx] != 0)
2652                                         ixgbe_set_vf_rate_limit(
2653                                                 dev, vf,
2654                                                 vfinfo[vf].tx_rate[idx],
2655                                                 1 << idx);
2656         }
2657
2658         ixgbe_restore_statistics_mapping(dev);
2659
2660         err = ixgbe_flow_ctrl_enable(dev, hw);
2661         if (err < 0) {
2662                 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2663                 goto error;
2664         }
2665
2666         err = ixgbe_dev_rxtx_start(dev);
2667         if (err < 0) {
2668                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2669                 goto error;
2670         }
2671
2672         /* Skip link setup if loopback mode is enabled. */
2673         if (dev->data->dev_conf.lpbk_mode != 0) {
2674                 err = ixgbe_check_supported_loopback_mode(dev);
2675                 if (err < 0) {
2676                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2677                         goto error;
2678                 } else {
2679                         goto skip_link_setup;
2680                 }
2681         }
2682
2683         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2684                 err = hw->mac.ops.setup_sfp(hw);
2685                 if (err)
2686                         goto error;
2687         }
2688
2689         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2690                 /* Turn on the copper */
2691                 ixgbe_set_phy_power(hw, true);
2692         } else {
2693                 /* Turn on the laser */
2694                 ixgbe_enable_tx_laser(hw);
2695         }
2696
2697         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2698         if (err)
2699                 goto error;
2700         dev->data->dev_link.link_status = link_up;
2701
2702         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2703         if (err)
2704                 goto error;
2705
2706         switch (hw->mac.type) {
2707         case ixgbe_mac_X550:
2708         case ixgbe_mac_X550EM_x:
2709         case ixgbe_mac_X550EM_a:
2710                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2711                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2712                         ETH_LINK_SPEED_10G;
2713                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2714                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2715                         allowed_speeds = ETH_LINK_SPEED_10M |
2716                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2717                 break;
2718         default:
2719                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2720                         ETH_LINK_SPEED_10G;
2721         }
2722
2723         link_speeds = &dev->data->dev_conf.link_speeds;
2724
2725         /* Ignore autoneg flag bit and check the validity of
2726          * link_speed
2727          */
2728         if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2729                 PMD_INIT_LOG(ERR, "Invalid link setting");
2730                 goto error;
2731         }
2732
2733         speed = 0x0;
2734         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2735                 switch (hw->mac.type) {
2736                 case ixgbe_mac_82598EB:
2737                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2738                         break;
2739                 case ixgbe_mac_82599EB:
2740                 case ixgbe_mac_X540:
2741                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2742                         break;
2743                 case ixgbe_mac_X550:
2744                 case ixgbe_mac_X550EM_x:
2745                 case ixgbe_mac_X550EM_a:
2746                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2747                         break;
2748                 default:
2749                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2750                 }
2751         } else {
2752                 if (*link_speeds & ETH_LINK_SPEED_10G)
2753                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2754                 if (*link_speeds & ETH_LINK_SPEED_5G)
2755                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2756                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2757                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2758                 if (*link_speeds & ETH_LINK_SPEED_1G)
2759                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2760                 if (*link_speeds & ETH_LINK_SPEED_100M)
2761                         speed |= IXGBE_LINK_SPEED_100_FULL;
2762                 if (*link_speeds & ETH_LINK_SPEED_10M)
2763                         speed |= IXGBE_LINK_SPEED_10_FULL;
2764         }
2765
2766         err = ixgbe_setup_link(hw, speed, link_up);
2767         if (err)
2768                 goto error;
2769
2770 skip_link_setup:
2771
2772         if (rte_intr_allow_others(intr_handle)) {
2773                 /* check if lsc interrupt is enabled */
2774                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2775                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2776                 else
2777                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2778                 ixgbe_dev_macsec_interrupt_setup(dev);
2779         } else {
2780                 rte_intr_callback_unregister(intr_handle,
2781                                              ixgbe_dev_interrupt_handler, dev);
2782                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2783                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2784                                      " no intr multiplex");
2785         }
2786
2787         /* check if rxq interrupt is enabled */
2788         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2789             rte_intr_dp_is_en(intr_handle))
2790                 ixgbe_dev_rxq_interrupt_setup(dev);
2791
2792         /* enable uio/vfio intr/eventfd mapping */
2793         rte_intr_enable(intr_handle);
2794
2795         /* resume enabled intr since hw reset */
2796         ixgbe_enable_intr(dev);
2797         ixgbe_l2_tunnel_conf(dev);
2798         ixgbe_filter_restore(dev);
2799
2800         if (tm_conf->root && !tm_conf->committed)
2801                 PMD_DRV_LOG(WARNING,
2802                             "please call hierarchy_commit() "
2803                             "before starting the port");
2804
2805         /* wait for the controller to acquire link */
2806         err = ixgbe_wait_for_link_up(hw);
2807         if (err)
2808                 goto error;
2809
2810         /*
2811          * Update link status right before return, because it may
2812          * start link configuration process in a separate thread.
2813          */
2814         ixgbe_dev_link_update(dev, 0);
2815
2816         /* setup the macsec setting register */
2817         if (macsec_setting->offload_en)
2818                 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2819
2820         return 0;
2821
2822 error:
2823         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2824         ixgbe_dev_clear_queues(dev);
2825         return -EIO;
2826 }
2827
2828 /*
2829  * Stop device: disable rx and tx functions to allow for reconfiguring.
2830  */
2831 static int
2832 ixgbe_dev_stop(struct rte_eth_dev *dev)
2833 {
2834         struct rte_eth_link link;
2835         struct ixgbe_adapter *adapter = dev->data->dev_private;
2836         struct ixgbe_hw *hw =
2837                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2838         struct ixgbe_vf_info *vfinfo =
2839                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2840         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2841         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2842         int vf;
2843         struct ixgbe_tm_conf *tm_conf =
2844                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2845
2846         if (hw->adapter_stopped)
2847                 return 0;
2848
2849         PMD_INIT_FUNC_TRACE();
2850
2851         ixgbe_dev_wait_setup_link_complete(dev, 0);
2852
2853         /* disable interrupts */
2854         ixgbe_disable_intr(hw);
2855
2856         /* reset the NIC */
2857         ixgbe_pf_reset_hw(hw);
2858         hw->adapter_stopped = 0;
2859
2860         /* stop adapter */
2861         ixgbe_stop_adapter(hw);
2862
2863         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2864                 vfinfo[vf].clear_to_send = false;
2865
2866         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2867                 /* Turn off the copper */
2868                 ixgbe_set_phy_power(hw, false);
2869         } else {
2870                 /* Turn off the laser */
2871                 ixgbe_disable_tx_laser(hw);
2872         }
2873
2874         ixgbe_dev_clear_queues(dev);
2875
2876         /* Clear stored conf */
2877         dev->data->scattered_rx = 0;
2878         dev->data->lro = 0;
2879
2880         /* Clear recorded link status */
2881         memset(&link, 0, sizeof(link));
2882         rte_eth_linkstatus_set(dev, &link);
2883
2884         if (!rte_intr_allow_others(intr_handle))
2885                 /* resume to the default handler */
2886                 rte_intr_callback_register(intr_handle,
2887                                            ixgbe_dev_interrupt_handler,
2888                                            (void *)dev);
2889
2890         /* Clean datapath event and queue/vec mapping */
2891         rte_intr_efd_disable(intr_handle);
2892         if (intr_handle->intr_vec != NULL) {
2893                 rte_free(intr_handle->intr_vec);
2894                 intr_handle->intr_vec = NULL;
2895         }
2896
2897         /* reset hierarchy commit */
2898         tm_conf->committed = false;
2899
2900         adapter->rss_reta_updated = 0;
2901
2902         hw->adapter_stopped = true;
2903         dev->data->dev_started = 0;
2904
2905         return 0;
2906 }
2907
2908 /*
2909  * Set device link up: enable tx.
2910  */
2911 static int
2912 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2913 {
2914         struct ixgbe_hw *hw =
2915                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2916         if (hw->mac.type == ixgbe_mac_82599EB) {
2917 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2918                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2919                         /* Not suported in bypass mode */
2920                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2921                                      "by device id 0x%x", hw->device_id);
2922                         return -ENOTSUP;
2923                 }
2924 #endif
2925         }
2926
2927         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2928                 /* Turn on the copper */
2929                 ixgbe_set_phy_power(hw, true);
2930         } else {
2931                 /* Turn on the laser */
2932                 ixgbe_enable_tx_laser(hw);
2933                 ixgbe_dev_link_update(dev, 0);
2934         }
2935
2936         return 0;
2937 }
2938
2939 /*
2940  * Set device link down: disable tx.
2941  */
2942 static int
2943 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2944 {
2945         struct ixgbe_hw *hw =
2946                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2947         if (hw->mac.type == ixgbe_mac_82599EB) {
2948 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2949                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2950                         /* Not suported in bypass mode */
2951                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2952                                      "by device id 0x%x", hw->device_id);
2953                         return -ENOTSUP;
2954                 }
2955 #endif
2956         }
2957
2958         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2959                 /* Turn off the copper */
2960                 ixgbe_set_phy_power(hw, false);
2961         } else {
2962                 /* Turn off the laser */
2963                 ixgbe_disable_tx_laser(hw);
2964                 ixgbe_dev_link_update(dev, 0);
2965         }
2966
2967         return 0;
2968 }
2969
2970 /*
2971  * Reset and stop device.
2972  */
2973 static int
2974 ixgbe_dev_close(struct rte_eth_dev *dev)
2975 {
2976         struct ixgbe_hw *hw =
2977                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2978         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2979         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2980         int retries = 0;
2981         int ret;
2982
2983         PMD_INIT_FUNC_TRACE();
2984         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2985                 return 0;
2986
2987         ixgbe_pf_reset_hw(hw);
2988
2989         ret = ixgbe_dev_stop(dev);
2990
2991         ixgbe_dev_free_queues(dev);
2992
2993         ixgbe_disable_pcie_master(hw);
2994
2995         /* reprogram the RAR[0] in case user changed it. */
2996         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2997
2998         /* Unlock any pending hardware semaphore */
2999         ixgbe_swfw_lock_reset(hw);
3000
3001         /* disable uio intr before callback unregister */
3002         rte_intr_disable(intr_handle);
3003
3004         do {
3005                 ret = rte_intr_callback_unregister(intr_handle,
3006                                 ixgbe_dev_interrupt_handler, dev);
3007                 if (ret >= 0 || ret == -ENOENT) {
3008                         break;
3009                 } else if (ret != -EAGAIN) {
3010                         PMD_INIT_LOG(ERR,
3011                                 "intr callback unregister failed: %d",
3012                                 ret);
3013                 }
3014                 rte_delay_ms(100);
3015         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3016
3017         /* cancel the delay handler before remove dev */
3018         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3019
3020         /* uninitialize PF if max_vfs not zero */
3021         ixgbe_pf_host_uninit(dev);
3022
3023         /* remove all the fdir filters & hash */
3024         ixgbe_fdir_filter_uninit(dev);
3025
3026         /* remove all the L2 tunnel filters & hash */
3027         ixgbe_l2_tn_filter_uninit(dev);
3028
3029         /* Remove all ntuple filters of the device */
3030         ixgbe_ntuple_filter_uninit(dev);
3031
3032         /* clear all the filters list */
3033         ixgbe_filterlist_flush();
3034
3035         /* Remove all Traffic Manager configuration */
3036         ixgbe_tm_conf_uninit(dev);
3037
3038 #ifdef RTE_LIB_SECURITY
3039         rte_free(dev->security_ctx);
3040 #endif
3041
3042         return ret;
3043 }
3044
3045 /*
3046  * Reset PF device.
3047  */
3048 static int
3049 ixgbe_dev_reset(struct rte_eth_dev *dev)
3050 {
3051         int ret;
3052
3053         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3054          * its VF to make them align with it. The detailed notification
3055          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3056          * To avoid unexpected behavior in VF, currently reset of PF with
3057          * SR-IOV activation is not supported. It might be supported later.
3058          */
3059         if (dev->data->sriov.active)
3060                 return -ENOTSUP;
3061
3062         ret = eth_ixgbe_dev_uninit(dev);
3063         if (ret)
3064                 return ret;
3065
3066         ret = eth_ixgbe_dev_init(dev, NULL);
3067
3068         return ret;
3069 }
3070
3071 static void
3072 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3073                            struct ixgbe_hw_stats *hw_stats,
3074                            struct ixgbe_macsec_stats *macsec_stats,
3075                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3076                            uint64_t *total_qprc, uint64_t *total_qprdc)
3077 {
3078         uint32_t bprc, lxon, lxoff, total;
3079         uint32_t delta_gprc = 0;
3080         unsigned i;
3081         /* Workaround for RX byte count not including CRC bytes when CRC
3082          * strip is enabled. CRC bytes are removed from counters when crc_strip
3083          * is disabled.
3084          */
3085         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3086                         IXGBE_HLREG0_RXCRCSTRP);
3087
3088         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3089         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3090         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3091         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3092
3093         for (i = 0; i < 8; i++) {
3094                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3095
3096                 /* global total per queue */
3097                 hw_stats->mpc[i] += mp;
3098                 /* Running comprehensive total for stats display */
3099                 *total_missed_rx += hw_stats->mpc[i];
3100                 if (hw->mac.type == ixgbe_mac_82598EB) {
3101                         hw_stats->rnbc[i] +=
3102                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3103                         hw_stats->pxonrxc[i] +=
3104                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3105                         hw_stats->pxoffrxc[i] +=
3106                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3107                 } else {
3108                         hw_stats->pxonrxc[i] +=
3109                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3110                         hw_stats->pxoffrxc[i] +=
3111                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3112                         hw_stats->pxon2offc[i] +=
3113                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3114                 }
3115                 hw_stats->pxontxc[i] +=
3116                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3117                 hw_stats->pxofftxc[i] +=
3118                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3119         }
3120         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3121                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3122                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3123                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3124
3125                 delta_gprc += delta_qprc;
3126
3127                 hw_stats->qprc[i] += delta_qprc;
3128                 hw_stats->qptc[i] += delta_qptc;
3129
3130                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3131                 hw_stats->qbrc[i] +=
3132                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3133                 if (crc_strip == 0)
3134                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3135
3136                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3137                 hw_stats->qbtc[i] +=
3138                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3139
3140                 hw_stats->qprdc[i] += delta_qprdc;
3141                 *total_qprdc += hw_stats->qprdc[i];
3142
3143                 *total_qprc += hw_stats->qprc[i];
3144                 *total_qbrc += hw_stats->qbrc[i];
3145         }
3146         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3147         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3148         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3149
3150         /*
3151          * An errata states that gprc actually counts good + missed packets:
3152          * Workaround to set gprc to summated queue packet receives
3153          */
3154         hw_stats->gprc = *total_qprc;
3155
3156         if (hw->mac.type != ixgbe_mac_82598EB) {
3157                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3158                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3159                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3160                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3161                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3162                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3163                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3164                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3165         } else {
3166                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3167                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3168                 /* 82598 only has a counter in the high register */
3169                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3170                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3171                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3172         }
3173         uint64_t old_tpr = hw_stats->tpr;
3174
3175         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3176         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3177
3178         if (crc_strip == 0)
3179                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3180
3181         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3182         hw_stats->gptc += delta_gptc;
3183         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3184         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3185
3186         /*
3187          * Workaround: mprc hardware is incorrectly counting
3188          * broadcasts, so for now we subtract those.
3189          */
3190         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3191         hw_stats->bprc += bprc;
3192         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3193         if (hw->mac.type == ixgbe_mac_82598EB)
3194                 hw_stats->mprc -= bprc;
3195
3196         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3197         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3198         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3199         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3200         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3201         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3202
3203         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3204         hw_stats->lxontxc += lxon;
3205         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3206         hw_stats->lxofftxc += lxoff;
3207         total = lxon + lxoff;
3208
3209         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3210         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3211         hw_stats->gptc -= total;
3212         hw_stats->mptc -= total;
3213         hw_stats->ptc64 -= total;
3214         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3215
3216         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3217         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3218         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3219         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3220         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3221         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3222         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3223         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3224         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3225         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3226         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3227         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3228         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3229         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3230         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3231         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3232         /* Only read FCOE on 82599 */
3233         if (hw->mac.type != ixgbe_mac_82598EB) {
3234                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3235                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3236                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3237                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3238                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3239         }
3240
3241         /* Flow Director Stats registers */
3242         if (hw->mac.type != ixgbe_mac_82598EB) {
3243                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3244                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3245                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3246                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3247                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3248                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3249                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3250                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3251                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3252                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3253         }
3254         /* MACsec Stats registers */
3255         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3256         macsec_stats->out_pkts_encrypted +=
3257                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3258         macsec_stats->out_pkts_protected +=
3259                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3260         macsec_stats->out_octets_encrypted +=
3261                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3262         macsec_stats->out_octets_protected +=
3263                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3264         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3265         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3266         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3267         macsec_stats->in_pkts_unknownsci +=
3268                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3269         macsec_stats->in_octets_decrypted +=
3270                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3271         macsec_stats->in_octets_validated +=
3272                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3273         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3274         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3275         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3276         for (i = 0; i < 2; i++) {
3277                 macsec_stats->in_pkts_ok +=
3278                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3279                 macsec_stats->in_pkts_invalid +=
3280                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3281                 macsec_stats->in_pkts_notvalid +=
3282                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3283         }
3284         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3285         macsec_stats->in_pkts_notusingsa +=
3286                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3287 }
3288
3289 /*
3290  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3291  */
3292 static int
3293 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3294 {
3295         struct ixgbe_hw *hw =
3296                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3297         struct ixgbe_hw_stats *hw_stats =
3298                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3299         struct ixgbe_macsec_stats *macsec_stats =
3300                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3301                                 dev->data->dev_private);
3302         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3303         unsigned i;
3304
3305         total_missed_rx = 0;
3306         total_qbrc = 0;
3307         total_qprc = 0;
3308         total_qprdc = 0;
3309
3310         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3311                         &total_qbrc, &total_qprc, &total_qprdc);
3312
3313         if (stats == NULL)
3314                 return -EINVAL;
3315
3316         /* Fill out the rte_eth_stats statistics structure */
3317         stats->ipackets = total_qprc;
3318         stats->ibytes = total_qbrc;
3319         stats->opackets = hw_stats->gptc;
3320         stats->obytes = hw_stats->gotc;
3321
3322         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3323                 stats->q_ipackets[i] = hw_stats->qprc[i];
3324                 stats->q_opackets[i] = hw_stats->qptc[i];
3325                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3326                 stats->q_obytes[i] = hw_stats->qbtc[i];
3327                 stats->q_errors[i] = hw_stats->qprdc[i];
3328         }
3329
3330         /* Rx Errors */
3331         stats->imissed  = total_missed_rx;
3332         stats->ierrors  = hw_stats->crcerrs +
3333                           hw_stats->mspdc +
3334                           hw_stats->rlec +
3335                           hw_stats->ruc +
3336                           hw_stats->roc +
3337                           hw_stats->illerrc +
3338                           hw_stats->errbc +
3339                           hw_stats->rfc +
3340                           hw_stats->fccrc +
3341                           hw_stats->fclast;
3342
3343         /*
3344          * 82599 errata, UDP frames with a 0 checksum can be marked as checksum
3345          * errors.
3346          */
3347         if (hw->mac.type != ixgbe_mac_82599EB)
3348                 stats->ierrors += hw_stats->xec;
3349
3350         /* Tx Errors */
3351         stats->oerrors  = 0;
3352         return 0;
3353 }
3354
3355 static int
3356 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3357 {
3358         struct ixgbe_hw_stats *stats =
3359                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3360
3361         /* HW registers are cleared on read */
3362         ixgbe_dev_stats_get(dev, NULL);
3363
3364         /* Reset software totals */
3365         memset(stats, 0, sizeof(*stats));
3366
3367         return 0;
3368 }
3369
3370 /* This function calculates the number of xstats based on the current config */
3371 static unsigned
3372 ixgbe_xstats_calc_num(void) {
3373         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3374                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3375                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3376 }
3377
3378 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3379         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3380 {
3381         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3382         unsigned stat, i, count;
3383
3384         if (xstats_names != NULL) {
3385                 count = 0;
3386
3387                 /* Note: limit >= cnt_stats checked upstream
3388                  * in rte_eth_xstats_names()
3389                  */
3390
3391                 /* Extended stats from ixgbe_hw_stats */
3392                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3393                         strlcpy(xstats_names[count].name,
3394                                 rte_ixgbe_stats_strings[i].name,
3395                                 sizeof(xstats_names[count].name));
3396                         count++;
3397                 }
3398
3399                 /* MACsec Stats */
3400                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3401                         strlcpy(xstats_names[count].name,
3402                                 rte_ixgbe_macsec_strings[i].name,
3403                                 sizeof(xstats_names[count].name));
3404                         count++;
3405                 }
3406
3407                 /* RX Priority Stats */
3408                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3409                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3410                                 snprintf(xstats_names[count].name,
3411                                         sizeof(xstats_names[count].name),
3412                                         "rx_priority%u_%s", i,
3413                                         rte_ixgbe_rxq_strings[stat].name);
3414                                 count++;
3415                         }
3416                 }
3417
3418                 /* TX Priority Stats */
3419                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3420                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3421                                 snprintf(xstats_names[count].name,
3422                                         sizeof(xstats_names[count].name),
3423                                         "tx_priority%u_%s", i,
3424                                         rte_ixgbe_txq_strings[stat].name);
3425                                 count++;
3426                         }
3427                 }
3428         }
3429         return cnt_stats;
3430 }
3431
3432 static int ixgbe_dev_xstats_get_names_by_id(
3433         struct rte_eth_dev *dev,
3434         struct rte_eth_xstat_name *xstats_names,
3435         const uint64_t *ids,
3436         unsigned int limit)
3437 {
3438         if (!ids) {
3439                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3440                 unsigned int stat, i, count;
3441
3442                 if (xstats_names != NULL) {
3443                         count = 0;
3444
3445                         /* Note: limit >= cnt_stats checked upstream
3446                          * in rte_eth_xstats_names()
3447                          */
3448
3449                         /* Extended stats from ixgbe_hw_stats */
3450                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3451                                 strlcpy(xstats_names[count].name,
3452                                         rte_ixgbe_stats_strings[i].name,
3453                                         sizeof(xstats_names[count].name));
3454                                 count++;
3455                         }
3456
3457                         /* MACsec Stats */
3458                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3459                                 strlcpy(xstats_names[count].name,
3460                                         rte_ixgbe_macsec_strings[i].name,
3461                                         sizeof(xstats_names[count].name));
3462                                 count++;
3463                         }
3464
3465                         /* RX Priority Stats */
3466                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3467                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3468                                         snprintf(xstats_names[count].name,
3469                                             sizeof(xstats_names[count].name),
3470                                             "rx_priority%u_%s", i,
3471                                             rte_ixgbe_rxq_strings[stat].name);
3472                                         count++;
3473                                 }
3474                         }
3475
3476                         /* TX Priority Stats */
3477                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3478                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3479                                         snprintf(xstats_names[count].name,
3480                                             sizeof(xstats_names[count].name),
3481                                             "tx_priority%u_%s", i,
3482                                             rte_ixgbe_txq_strings[stat].name);
3483                                         count++;
3484                                 }
3485                         }
3486                 }
3487                 return cnt_stats;
3488         }
3489
3490         uint16_t i;
3491         uint16_t size = ixgbe_xstats_calc_num();
3492         struct rte_eth_xstat_name xstats_names_copy[size];
3493
3494         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3495                         size);
3496
3497         for (i = 0; i < limit; i++) {
3498                 if (ids[i] >= size) {
3499                         PMD_INIT_LOG(ERR, "id value isn't valid");
3500                         return -1;
3501                 }
3502                 strcpy(xstats_names[i].name,
3503                                 xstats_names_copy[ids[i]].name);
3504         }
3505         return limit;
3506 }
3507
3508 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3509         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3510 {
3511         unsigned i;
3512
3513         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3514                 return -ENOMEM;
3515
3516         if (xstats_names != NULL)
3517                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3518                         strlcpy(xstats_names[i].name,
3519                                 rte_ixgbevf_stats_strings[i].name,
3520                                 sizeof(xstats_names[i].name));
3521         return IXGBEVF_NB_XSTATS;
3522 }
3523
3524 static int
3525 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3526                                          unsigned n)
3527 {
3528         struct ixgbe_hw *hw =
3529                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3530         struct ixgbe_hw_stats *hw_stats =
3531                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3532         struct ixgbe_macsec_stats *macsec_stats =
3533                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3534                                 dev->data->dev_private);
3535         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3536         unsigned i, stat, count = 0;
3537
3538         count = ixgbe_xstats_calc_num();
3539
3540         if (n < count)
3541                 return count;
3542
3543         total_missed_rx = 0;
3544         total_qbrc = 0;
3545         total_qprc = 0;
3546         total_qprdc = 0;
3547
3548         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3549                         &total_qbrc, &total_qprc, &total_qprdc);
3550
3551         /* If this is a reset xstats is NULL, and we have cleared the
3552          * registers by reading them.
3553          */
3554         if (!xstats)
3555                 return 0;
3556
3557         /* Extended stats from ixgbe_hw_stats */
3558         count = 0;
3559         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3560                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3561                                 rte_ixgbe_stats_strings[i].offset);
3562                 xstats[count].id = count;
3563                 count++;
3564         }
3565
3566         /* MACsec Stats */
3567         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3568                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3569                                 rte_ixgbe_macsec_strings[i].offset);
3570                 xstats[count].id = count;
3571                 count++;
3572         }
3573
3574         /* RX Priority Stats */
3575         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3576                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3577                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3578                                         rte_ixgbe_rxq_strings[stat].offset +
3579                                         (sizeof(uint64_t) * i));
3580                         xstats[count].id = count;
3581                         count++;
3582                 }
3583         }
3584
3585         /* TX Priority Stats */
3586         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3587                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3588                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3589                                         rte_ixgbe_txq_strings[stat].offset +
3590                                         (sizeof(uint64_t) * i));
3591                         xstats[count].id = count;
3592                         count++;
3593                 }
3594         }
3595         return count;
3596 }
3597
3598 static int
3599 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3600                 uint64_t *values, unsigned int n)
3601 {
3602         if (!ids) {
3603                 struct ixgbe_hw *hw =
3604                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3605                 struct ixgbe_hw_stats *hw_stats =
3606                                 IXGBE_DEV_PRIVATE_TO_STATS(
3607                                                 dev->data->dev_private);
3608                 struct ixgbe_macsec_stats *macsec_stats =
3609                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3610                                         dev->data->dev_private);
3611                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3612                 unsigned int i, stat, count = 0;
3613
3614                 count = ixgbe_xstats_calc_num();
3615
3616                 if (!ids && n < count)
3617                         return count;
3618
3619                 total_missed_rx = 0;
3620                 total_qbrc = 0;
3621                 total_qprc = 0;
3622                 total_qprdc = 0;
3623
3624                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3625                                 &total_missed_rx, &total_qbrc, &total_qprc,
3626                                 &total_qprdc);
3627
3628                 /* If this is a reset xstats is NULL, and we have cleared the
3629                  * registers by reading them.
3630                  */
3631                 if (!ids && !values)
3632                         return 0;
3633
3634                 /* Extended stats from ixgbe_hw_stats */
3635                 count = 0;
3636                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3637                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3638                                         rte_ixgbe_stats_strings[i].offset);
3639                         count++;
3640                 }
3641
3642                 /* MACsec Stats */
3643                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3644                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3645                                         rte_ixgbe_macsec_strings[i].offset);
3646                         count++;
3647                 }
3648
3649                 /* RX Priority Stats */
3650                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3651                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3652                                 values[count] =
3653                                         *(uint64_t *)(((char *)hw_stats) +
3654                                         rte_ixgbe_rxq_strings[stat].offset +
3655                                         (sizeof(uint64_t) * i));
3656                                 count++;
3657                         }
3658                 }
3659
3660                 /* TX Priority Stats */
3661                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3662                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3663                                 values[count] =
3664                                         *(uint64_t *)(((char *)hw_stats) +
3665                                         rte_ixgbe_txq_strings[stat].offset +
3666                                         (sizeof(uint64_t) * i));
3667                                 count++;
3668                         }
3669                 }
3670                 return count;
3671         }
3672
3673         uint16_t i;
3674         uint16_t size = ixgbe_xstats_calc_num();
3675         uint64_t values_copy[size];
3676
3677         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3678
3679         for (i = 0; i < n; i++) {
3680                 if (ids[i] >= size) {
3681                         PMD_INIT_LOG(ERR, "id value isn't valid");
3682                         return -1;
3683                 }
3684                 values[i] = values_copy[ids[i]];
3685         }
3686         return n;
3687 }
3688
3689 static int
3690 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3691 {
3692         struct ixgbe_hw_stats *stats =
3693                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3694         struct ixgbe_macsec_stats *macsec_stats =
3695                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3696                                 dev->data->dev_private);
3697
3698         unsigned count = ixgbe_xstats_calc_num();
3699
3700         /* HW registers are cleared on read */
3701         ixgbe_dev_xstats_get(dev, NULL, count);
3702
3703         /* Reset software totals */
3704         memset(stats, 0, sizeof(*stats));
3705         memset(macsec_stats, 0, sizeof(*macsec_stats));
3706
3707         return 0;
3708 }
3709
3710 static void
3711 ixgbevf_update_stats(struct rte_eth_dev *dev)
3712 {
3713         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3714         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3715                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3716
3717         /* Good Rx packet, include VF loopback */
3718         UPDATE_VF_STAT(IXGBE_VFGPRC,
3719             hw_stats->last_vfgprc, hw_stats->vfgprc);
3720
3721         /* Good Rx octets, include VF loopback */
3722         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3723             hw_stats->last_vfgorc, hw_stats->vfgorc);
3724
3725         /* Good Tx packet, include VF loopback */
3726         UPDATE_VF_STAT(IXGBE_VFGPTC,
3727             hw_stats->last_vfgptc, hw_stats->vfgptc);
3728
3729         /* Good Tx octets, include VF loopback */
3730         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3731             hw_stats->last_vfgotc, hw_stats->vfgotc);
3732
3733         /* Rx Multicst Packet */
3734         UPDATE_VF_STAT(IXGBE_VFMPRC,
3735             hw_stats->last_vfmprc, hw_stats->vfmprc);
3736 }
3737
3738 static int
3739 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3740                        unsigned n)
3741 {
3742         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3743                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3744         unsigned i;
3745
3746         if (n < IXGBEVF_NB_XSTATS)
3747                 return IXGBEVF_NB_XSTATS;
3748
3749         ixgbevf_update_stats(dev);
3750
3751         if (!xstats)
3752                 return 0;
3753
3754         /* Extended stats */
3755         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3756                 xstats[i].id = i;
3757                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3758                         rte_ixgbevf_stats_strings[i].offset);
3759         }
3760
3761         return IXGBEVF_NB_XSTATS;
3762 }
3763
3764 static int
3765 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3766 {
3767         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3768                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3769
3770         ixgbevf_update_stats(dev);
3771
3772         if (stats == NULL)
3773                 return -EINVAL;
3774
3775         stats->ipackets = hw_stats->vfgprc;
3776         stats->ibytes = hw_stats->vfgorc;
3777         stats->opackets = hw_stats->vfgptc;
3778         stats->obytes = hw_stats->vfgotc;
3779         return 0;
3780 }
3781
3782 static int
3783 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3784 {
3785         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3786                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3787
3788         /* Sync HW register to the last stats */
3789         ixgbevf_dev_stats_get(dev, NULL);
3790
3791         /* reset HW current stats*/
3792         hw_stats->vfgprc = 0;
3793         hw_stats->vfgorc = 0;
3794         hw_stats->vfgptc = 0;
3795         hw_stats->vfgotc = 0;
3796         hw_stats->vfmprc = 0;
3797
3798         return 0;
3799 }
3800
3801 static int
3802 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3803 {
3804         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3805         u16 eeprom_verh, eeprom_verl;
3806         u32 etrack_id;
3807         int ret;
3808
3809         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3810         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3811
3812         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3813         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3814         if (ret < 0)
3815                 return -EINVAL;
3816
3817         ret += 1; /* add the size of '\0' */
3818         if (fw_size < (size_t)ret)
3819                 return ret;
3820         else
3821                 return 0;
3822 }
3823
3824 static int
3825 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3826 {
3827         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3828         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3829         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3830
3831         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3832         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3833         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3834                 /*
3835                  * When DCB/VT is off, maximum number of queues changes,
3836                  * except for 82598EB, which remains constant.
3837                  */
3838                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3839                                 hw->mac.type != ixgbe_mac_82598EB)
3840                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3841         }
3842         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3843         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3844         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3845         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3846         dev_info->max_vfs = pci_dev->max_vfs;
3847         if (hw->mac.type == ixgbe_mac_82598EB)
3848                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3849         else
3850                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3851         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3852         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3853         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3854         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3855         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3856                                      dev_info->rx_queue_offload_capa);
3857         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3858         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3859
3860         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3861                 .rx_thresh = {
3862                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3863                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3864                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3865                 },
3866                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3867                 .rx_drop_en = 0,
3868                 .offloads = 0,
3869         };
3870
3871         dev_info->default_txconf = (struct rte_eth_txconf) {
3872                 .tx_thresh = {
3873                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3874                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3875                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3876                 },
3877                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3878                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3879                 .offloads = 0,
3880         };
3881
3882         dev_info->rx_desc_lim = rx_desc_lim;
3883         dev_info->tx_desc_lim = tx_desc_lim;
3884
3885         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3886         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3887         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3888
3889         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3890         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3891                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3892                 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3893                         ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3894
3895         if (hw->mac.type == ixgbe_mac_X540 ||
3896             hw->mac.type == ixgbe_mac_X540_vf ||
3897             hw->mac.type == ixgbe_mac_X550 ||
3898             hw->mac.type == ixgbe_mac_X550_vf) {
3899                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3900         }
3901         if (hw->mac.type == ixgbe_mac_X550) {
3902                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3903                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3904         }
3905
3906         /* Driver-preferred Rx/Tx parameters */
3907         dev_info->default_rxportconf.burst_size = 32;
3908         dev_info->default_txportconf.burst_size = 32;
3909         dev_info->default_rxportconf.nb_queues = 1;
3910         dev_info->default_txportconf.nb_queues = 1;
3911         dev_info->default_rxportconf.ring_size = 256;
3912         dev_info->default_txportconf.ring_size = 256;
3913
3914         return 0;
3915 }
3916
3917 static const uint32_t *
3918 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3919 {
3920         static const uint32_t ptypes[] = {
3921                 /* For non-vec functions,
3922                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3923                  * for vec functions,
3924                  * refers to _recv_raw_pkts_vec().
3925                  */
3926                 RTE_PTYPE_L2_ETHER,
3927                 RTE_PTYPE_L3_IPV4,
3928                 RTE_PTYPE_L3_IPV4_EXT,
3929                 RTE_PTYPE_L3_IPV6,
3930                 RTE_PTYPE_L3_IPV6_EXT,
3931                 RTE_PTYPE_L4_SCTP,
3932                 RTE_PTYPE_L4_TCP,
3933                 RTE_PTYPE_L4_UDP,
3934                 RTE_PTYPE_TUNNEL_IP,
3935                 RTE_PTYPE_INNER_L3_IPV6,
3936                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3937                 RTE_PTYPE_INNER_L4_TCP,
3938                 RTE_PTYPE_INNER_L4_UDP,
3939                 RTE_PTYPE_UNKNOWN
3940         };
3941
3942         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3943             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3944             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3945             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3946                 return ptypes;
3947
3948 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON)
3949         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3950             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3951                 return ptypes;
3952 #endif
3953         return NULL;
3954 }
3955
3956 static int
3957 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3958                      struct rte_eth_dev_info *dev_info)
3959 {
3960         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3961         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3962
3963         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3964         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3965         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3966         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3967         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3968         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3969         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3970         dev_info->max_vfs = pci_dev->max_vfs;
3971         if (hw->mac.type == ixgbe_mac_82598EB)
3972                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3973         else
3974                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3975         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3976         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3977                                      dev_info->rx_queue_offload_capa);
3978         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3979         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3980         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3981         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3982         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3983
3984         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3985                 .rx_thresh = {
3986                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3987                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3988                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3989                 },
3990                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3991                 .rx_drop_en = 0,
3992                 .offloads = 0,
3993         };
3994
3995         dev_info->default_txconf = (struct rte_eth_txconf) {
3996                 .tx_thresh = {
3997                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3998                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3999                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
4000                 },
4001                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
4002                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
4003                 .offloads = 0,
4004         };
4005
4006         dev_info->rx_desc_lim = rx_desc_lim;
4007         dev_info->tx_desc_lim = tx_desc_lim;
4008
4009         return 0;
4010 }
4011
4012 static int
4013 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4014                    bool *link_up, int wait_to_complete)
4015 {
4016         struct ixgbe_adapter *adapter = container_of(hw,
4017                                                      struct ixgbe_adapter, hw);
4018         struct ixgbe_mbx_info *mbx = &hw->mbx;
4019         struct ixgbe_mac_info *mac = &hw->mac;
4020         uint32_t links_reg, in_msg;
4021         int ret_val = 0;
4022
4023         /* If we were hit with a reset drop the link */
4024         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4025                 mac->get_link_status = true;
4026
4027         if (!mac->get_link_status)
4028                 goto out;
4029
4030         /* if link status is down no point in checking to see if pf is up */
4031         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4032         if (!(links_reg & IXGBE_LINKS_UP))
4033                 goto out;
4034
4035         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4036          * before the link status is correct
4037          */
4038         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4039                 int i;
4040
4041                 for (i = 0; i < 5; i++) {
4042                         rte_delay_us(100);
4043                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4044
4045                         if (!(links_reg & IXGBE_LINKS_UP))
4046                                 goto out;
4047                 }
4048         }
4049
4050         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4051         case IXGBE_LINKS_SPEED_10G_82599:
4052                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4053                 if (hw->mac.type >= ixgbe_mac_X550) {
4054                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4055                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4056                 }
4057                 break;
4058         case IXGBE_LINKS_SPEED_1G_82599:
4059                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4060                 break;
4061         case IXGBE_LINKS_SPEED_100_82599:
4062                 *speed = IXGBE_LINK_SPEED_100_FULL;
4063                 if (hw->mac.type == ixgbe_mac_X550) {
4064                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4065                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4066                 }
4067                 break;
4068         case IXGBE_LINKS_SPEED_10_X550EM_A:
4069                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4070                 /* Since Reserved in older MAC's */
4071                 if (hw->mac.type >= ixgbe_mac_X550)
4072                         *speed = IXGBE_LINK_SPEED_10_FULL;
4073                 break;
4074         default:
4075                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4076         }
4077
4078         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4079                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4080                         mac->get_link_status = true;
4081                 else
4082                         mac->get_link_status = false;
4083
4084                 goto out;
4085         }
4086
4087         /* if the read failed it could just be a mailbox collision, best wait
4088          * until we are called again and don't report an error
4089          */
4090         if (mbx->ops.read(hw, &in_msg, 1, 0))
4091                 goto out;
4092
4093         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4094                 /* msg is not CTS and is NACK we must have lost CTS status */
4095                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4096                         mac->get_link_status = false;
4097                 goto out;
4098         }
4099
4100         /* the pf is talking, if we timed out in the past we reinit */
4101         if (!mbx->timeout) {
4102                 ret_val = -1;
4103                 goto out;
4104         }
4105
4106         /* if we passed all the tests above then the link is up and we no
4107          * longer need to check for link
4108          */
4109         mac->get_link_status = false;
4110
4111 out:
4112         *link_up = !mac->get_link_status;
4113         return ret_val;
4114 }
4115
4116 /*
4117  * If @timeout_ms was 0, it means that it will not return until link complete.
4118  * It returns 1 on complete, return 0 on timeout.
4119  */
4120 static int
4121 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4122 {
4123 #define WARNING_TIMEOUT    9000 /* 9s  in total */
4124         struct ixgbe_adapter *ad = dev->data->dev_private;
4125         uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4126
4127         while (rte_atomic32_read(&ad->link_thread_running)) {
4128                 msec_delay(1);
4129                 timeout--;
4130
4131                 if (timeout_ms) {
4132                         if (!timeout)
4133                                 return 0;
4134                 } else if (!timeout) {
4135                         /* It will not return until link complete */
4136                         timeout = WARNING_TIMEOUT;
4137                         PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4138                 }
4139         }
4140
4141         return 1;
4142 }
4143
4144 static void *
4145 ixgbe_dev_setup_link_thread_handler(void *param)
4146 {
4147         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4148         struct ixgbe_adapter *ad = dev->data->dev_private;
4149         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4150         struct ixgbe_interrupt *intr =
4151                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4152         u32 speed;
4153         bool autoneg = false;
4154
4155         pthread_detach(pthread_self());
4156         speed = hw->phy.autoneg_advertised;
4157         if (!speed)
4158                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4159
4160         ixgbe_setup_link(hw, speed, true);
4161
4162         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4163         rte_atomic32_clear(&ad->link_thread_running);
4164         return NULL;
4165 }
4166
4167 /*
4168  * In freebsd environment, nic_uio drivers do not support interrupts,
4169  * rte_intr_callback_register() will fail to register interrupts.
4170  * We can not make link status to change from down to up by interrupt
4171  * callback. So we need to wait for the controller to acquire link
4172  * when ports start.
4173  * It returns 0 on link up.
4174  */
4175 static int
4176 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4177 {
4178 #ifdef RTE_EXEC_ENV_FREEBSD
4179         int err, i;
4180         bool link_up = false;
4181         uint32_t speed = 0;
4182         const int nb_iter = 25;
4183
4184         for (i = 0; i < nb_iter; i++) {
4185                 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4186                 if (err)
4187                         return err;
4188                 if (link_up)
4189                         return 0;
4190                 msec_delay(200);
4191         }
4192
4193         return 0;
4194 #else
4195         RTE_SET_USED(hw);
4196         return 0;
4197 #endif
4198 }
4199
4200 /* return 0 means link status changed, -1 means not changed */
4201 int
4202 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4203                             int wait_to_complete, int vf)
4204 {
4205         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4206         struct ixgbe_adapter *ad = dev->data->dev_private;
4207         struct rte_eth_link link;
4208         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4209         struct ixgbe_interrupt *intr =
4210                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4211         bool link_up;
4212         int diag;
4213         int wait = 1;
4214         u32 esdp_reg;
4215
4216         memset(&link, 0, sizeof(link));
4217         link.link_status = ETH_LINK_DOWN;
4218         link.link_speed = ETH_SPEED_NUM_NONE;
4219         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4220         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4221                         ETH_LINK_SPEED_FIXED);
4222
4223         hw->mac.get_link_status = true;
4224
4225         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4226                 return rte_eth_linkstatus_set(dev, &link);
4227
4228         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4229         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4230                 wait = 0;
4231
4232 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4233 #ifdef RTE_EXEC_ENV_FREEBSD
4234         wait = 1;
4235 #endif
4236
4237         if (vf)
4238                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4239         else
4240                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4241
4242         if (diag != 0) {
4243                 link.link_speed = ETH_SPEED_NUM_100M;
4244                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4245                 return rte_eth_linkstatus_set(dev, &link);
4246         }
4247
4248         if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4249                 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4250                 if ((esdp_reg & IXGBE_ESDP_SDP3))
4251                         link_up = 0;
4252         }
4253
4254         if (link_up == 0) {
4255                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4256                         ixgbe_dev_wait_setup_link_complete(dev, 0);
4257                         if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4258                                 /* To avoid race condition between threads, set
4259                                  * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4260                                  * when there is no link thread running.
4261                                  */
4262                                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4263                                 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4264                                         "ixgbe-link-handler",
4265                                         NULL,
4266                                         ixgbe_dev_setup_link_thread_handler,
4267                                         dev) < 0) {
4268                                         PMD_DRV_LOG(ERR,
4269                                                 "Create link thread failed!");
4270                                         rte_atomic32_clear(&ad->link_thread_running);
4271                                 }
4272                         } else {
4273                                 PMD_DRV_LOG(ERR,
4274                                         "Other link thread is running now!");
4275                         }
4276                 }
4277                 return rte_eth_linkstatus_set(dev, &link);
4278         }
4279
4280         link.link_status = ETH_LINK_UP;
4281         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4282
4283         switch (link_speed) {
4284         default:
4285         case IXGBE_LINK_SPEED_UNKNOWN:
4286                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
4287                 break;
4288
4289         case IXGBE_LINK_SPEED_10_FULL:
4290                 link.link_speed = ETH_SPEED_NUM_10M;
4291                 break;
4292
4293         case IXGBE_LINK_SPEED_100_FULL:
4294                 link.link_speed = ETH_SPEED_NUM_100M;
4295                 break;
4296
4297         case IXGBE_LINK_SPEED_1GB_FULL:
4298                 link.link_speed = ETH_SPEED_NUM_1G;
4299                 break;
4300
4301         case IXGBE_LINK_SPEED_2_5GB_FULL:
4302                 link.link_speed = ETH_SPEED_NUM_2_5G;
4303                 break;
4304
4305         case IXGBE_LINK_SPEED_5GB_FULL:
4306                 link.link_speed = ETH_SPEED_NUM_5G;
4307                 break;
4308
4309         case IXGBE_LINK_SPEED_10GB_FULL:
4310                 link.link_speed = ETH_SPEED_NUM_10G;
4311                 break;
4312         }
4313
4314         return rte_eth_linkstatus_set(dev, &link);
4315 }
4316
4317 static int
4318 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4319 {
4320         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4321 }
4322
4323 static int
4324 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4325 {
4326         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4327 }
4328
4329 static int
4330 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4331 {
4332         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4333         uint32_t fctrl;
4334
4335         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4336         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4337         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4338
4339         return 0;
4340 }
4341
4342 static int
4343 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4344 {
4345         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4346         uint32_t fctrl;
4347
4348         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4349         fctrl &= (~IXGBE_FCTRL_UPE);
4350         if (dev->data->all_multicast == 1)
4351                 fctrl |= IXGBE_FCTRL_MPE;
4352         else
4353                 fctrl &= (~IXGBE_FCTRL_MPE);
4354         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4355
4356         return 0;
4357 }
4358
4359 static int
4360 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4361 {
4362         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4363         uint32_t fctrl;
4364
4365         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4366         fctrl |= IXGBE_FCTRL_MPE;
4367         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4368
4369         return 0;
4370 }
4371
4372 static int
4373 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4374 {
4375         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4376         uint32_t fctrl;
4377
4378         if (dev->data->promiscuous == 1)
4379                 return 0; /* must remain in all_multicast mode */
4380
4381         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4382         fctrl &= (~IXGBE_FCTRL_MPE);
4383         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4384
4385         return 0;
4386 }
4387
4388 /**
4389  * It clears the interrupt causes and enables the interrupt.
4390  * It will be called once only during nic initialized.
4391  *
4392  * @param dev
4393  *  Pointer to struct rte_eth_dev.
4394  * @param on
4395  *  Enable or Disable.
4396  *
4397  * @return
4398  *  - On success, zero.
4399  *  - On failure, a negative value.
4400  */
4401 static int
4402 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4403 {
4404         struct ixgbe_interrupt *intr =
4405                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4406
4407         ixgbe_dev_link_status_print(dev);
4408         if (on)
4409                 intr->mask |= IXGBE_EICR_LSC;
4410         else
4411                 intr->mask &= ~IXGBE_EICR_LSC;
4412
4413         return 0;
4414 }
4415
4416 /**
4417  * It clears the interrupt causes and enables the interrupt.
4418  * It will be called once only during nic initialized.
4419  *
4420  * @param dev
4421  *  Pointer to struct rte_eth_dev.
4422  *
4423  * @return
4424  *  - On success, zero.
4425  *  - On failure, a negative value.
4426  */
4427 static int
4428 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4429 {
4430         struct ixgbe_interrupt *intr =
4431                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4432
4433         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4434
4435         return 0;
4436 }
4437
4438 /**
4439  * It clears the interrupt causes and enables the interrupt.
4440  * It will be called once only during nic initialized.
4441  *
4442  * @param dev
4443  *  Pointer to struct rte_eth_dev.
4444  *
4445  * @return
4446  *  - On success, zero.
4447  *  - On failure, a negative value.
4448  */
4449 static int
4450 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4451 {
4452         struct ixgbe_interrupt *intr =
4453                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4454
4455         intr->mask |= IXGBE_EICR_LINKSEC;
4456
4457         return 0;
4458 }
4459
4460 /*
4461  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4462  *
4463  * @param dev
4464  *  Pointer to struct rte_eth_dev.
4465  *
4466  * @return
4467  *  - On success, zero.
4468  *  - On failure, a negative value.
4469  */
4470 static int
4471 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4472 {
4473         uint32_t eicr;
4474         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4475         struct ixgbe_interrupt *intr =
4476                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4477
4478         /* clear all cause mask */
4479         ixgbe_disable_intr(hw);
4480
4481         /* read-on-clear nic registers here */
4482         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4483         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4484
4485         intr->flags = 0;
4486
4487         /* set flag for async link update */
4488         if (eicr & IXGBE_EICR_LSC)
4489                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4490
4491         if (eicr & IXGBE_EICR_MAILBOX)
4492                 intr->flags |= IXGBE_FLAG_MAILBOX;
4493
4494         if (eicr & IXGBE_EICR_LINKSEC)
4495                 intr->flags |= IXGBE_FLAG_MACSEC;
4496
4497         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4498             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4499             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4500                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4501
4502         return 0;
4503 }
4504
4505 /**
4506  * It gets and then prints the link status.
4507  *
4508  * @param dev
4509  *  Pointer to struct rte_eth_dev.
4510  *
4511  * @return
4512  *  - On success, zero.
4513  *  - On failure, a negative value.
4514  */
4515 static void
4516 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4517 {
4518         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4519         struct rte_eth_link link;
4520
4521         rte_eth_linkstatus_get(dev, &link);
4522
4523         if (link.link_status) {
4524                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4525                                         (int)(dev->data->port_id),
4526                                         (unsigned)link.link_speed,
4527                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4528                                         "full-duplex" : "half-duplex");
4529         } else {
4530                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4531                                 (int)(dev->data->port_id));
4532         }
4533         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4534                                 pci_dev->addr.domain,
4535                                 pci_dev->addr.bus,
4536                                 pci_dev->addr.devid,
4537                                 pci_dev->addr.function);
4538 }
4539
4540 /*
4541  * It executes link_update after knowing an interrupt occurred.
4542  *
4543  * @param dev
4544  *  Pointer to struct rte_eth_dev.
4545  *
4546  * @return
4547  *  - On success, zero.
4548  *  - On failure, a negative value.
4549  */
4550 static int
4551 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4552 {
4553         struct ixgbe_interrupt *intr =
4554                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4555         int64_t timeout;
4556         struct ixgbe_hw *hw =
4557                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4558
4559         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4560
4561         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4562                 ixgbe_pf_mbx_process(dev);
4563                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4564         }
4565
4566         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4567                 ixgbe_handle_lasi(hw);
4568                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4569         }
4570
4571         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4572                 struct rte_eth_link link;
4573
4574                 /* get the link status before link update, for predicting later */
4575                 rte_eth_linkstatus_get(dev, &link);
4576
4577                 ixgbe_dev_link_update(dev, 0);
4578
4579                 /* likely to up */
4580                 if (!link.link_status)
4581                         /* handle it 1 sec later, wait it being stable */
4582                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4583                 /* likely to down */
4584                 else
4585                         /* handle it 4 sec later, wait it being stable */
4586                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4587
4588                 ixgbe_dev_link_status_print(dev);
4589                 if (rte_eal_alarm_set(timeout * 1000,
4590                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4591                         PMD_DRV_LOG(ERR, "Error setting alarm");
4592                 else {
4593                         /* remember original mask */
4594                         intr->mask_original = intr->mask;
4595                         /* only disable lsc interrupt */
4596                         intr->mask &= ~IXGBE_EIMS_LSC;
4597                 }
4598         }
4599
4600         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4601         ixgbe_enable_intr(dev);
4602
4603         return 0;
4604 }
4605
4606 /**
4607  * Interrupt handler which shall be registered for alarm callback for delayed
4608  * handling specific interrupt to wait for the stable nic state. As the
4609  * NIC interrupt state is not stable for ixgbe after link is just down,
4610  * it needs to wait 4 seconds to get the stable status.
4611  *
4612  * @param handle
4613  *  Pointer to interrupt handle.
4614  * @param param
4615  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4616  *
4617  * @return
4618  *  void
4619  */
4620 static void
4621 ixgbe_dev_interrupt_delayed_handler(void *param)
4622 {
4623         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4624         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4625         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4626         struct ixgbe_interrupt *intr =
4627                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4628         struct ixgbe_hw *hw =
4629                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4630         uint32_t eicr;
4631
4632         ixgbe_disable_intr(hw);
4633
4634         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4635         if (eicr & IXGBE_EICR_MAILBOX)
4636                 ixgbe_pf_mbx_process(dev);
4637
4638         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4639                 ixgbe_handle_lasi(hw);
4640                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4641         }
4642
4643         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4644                 ixgbe_dev_link_update(dev, 0);
4645                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4646                 ixgbe_dev_link_status_print(dev);
4647                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4648         }
4649
4650         if (intr->flags & IXGBE_FLAG_MACSEC) {
4651                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL);
4652                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4653         }
4654
4655         /* restore original mask */
4656         intr->mask = intr->mask_original;
4657         intr->mask_original = 0;
4658
4659         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4660         ixgbe_enable_intr(dev);
4661         rte_intr_ack(intr_handle);
4662 }
4663
4664 /**
4665  * Interrupt handler triggered by NIC  for handling
4666  * specific interrupt.
4667  *
4668  * @param handle
4669  *  Pointer to interrupt handle.
4670  * @param param
4671  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4672  *
4673  * @return
4674  *  void
4675  */
4676 static void
4677 ixgbe_dev_interrupt_handler(void *param)
4678 {
4679         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4680
4681         ixgbe_dev_interrupt_get_status(dev);
4682         ixgbe_dev_interrupt_action(dev);
4683 }
4684
4685 static int
4686 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4687 {
4688         struct ixgbe_hw *hw;
4689
4690         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4691         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4692 }
4693
4694 static int
4695 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4696 {
4697         struct ixgbe_hw *hw;
4698
4699         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4700         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4701 }
4702
4703 static int
4704 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4705 {
4706         struct ixgbe_hw *hw;
4707         uint32_t mflcn_reg;
4708         uint32_t fccfg_reg;
4709         int rx_pause;
4710         int tx_pause;
4711
4712         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4713
4714         fc_conf->pause_time = hw->fc.pause_time;
4715         fc_conf->high_water = hw->fc.high_water[0];
4716         fc_conf->low_water = hw->fc.low_water[0];
4717         fc_conf->send_xon = hw->fc.send_xon;
4718         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4719
4720         /*
4721          * Return rx_pause status according to actual setting of
4722          * MFLCN register.
4723          */
4724         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4725         if (mflcn_reg & IXGBE_MFLCN_PMCF)
4726                 fc_conf->mac_ctrl_frame_fwd = 1;
4727         else
4728                 fc_conf->mac_ctrl_frame_fwd = 0;
4729
4730         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4731                 rx_pause = 1;
4732         else
4733                 rx_pause = 0;
4734
4735         /*
4736          * Return tx_pause status according to actual setting of
4737          * FCCFG register.
4738          */
4739         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4740         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4741                 tx_pause = 1;
4742         else
4743                 tx_pause = 0;
4744
4745         if (rx_pause && tx_pause)
4746                 fc_conf->mode = RTE_FC_FULL;
4747         else if (rx_pause)
4748                 fc_conf->mode = RTE_FC_RX_PAUSE;
4749         else if (tx_pause)
4750                 fc_conf->mode = RTE_FC_TX_PAUSE;
4751         else
4752                 fc_conf->mode = RTE_FC_NONE;
4753
4754         return 0;
4755 }
4756
4757 static int
4758 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4759 {
4760         struct ixgbe_hw *hw;
4761         struct ixgbe_adapter *adapter = dev->data->dev_private;
4762         int err;
4763         uint32_t rx_buf_size;
4764         uint32_t max_high_water;
4765         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4766                 ixgbe_fc_none,
4767                 ixgbe_fc_rx_pause,
4768                 ixgbe_fc_tx_pause,
4769                 ixgbe_fc_full
4770         };
4771
4772         PMD_INIT_FUNC_TRACE();
4773
4774         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4775         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4776         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4777
4778         /*
4779          * At least reserve one Ethernet frame for watermark
4780          * high_water/low_water in kilo bytes for ixgbe
4781          */
4782         max_high_water = (rx_buf_size -
4783                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4784         if ((fc_conf->high_water > max_high_water) ||
4785                 (fc_conf->high_water < fc_conf->low_water)) {
4786                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4787                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4788                 return -EINVAL;
4789         }
4790
4791         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4792         hw->fc.pause_time     = fc_conf->pause_time;
4793         hw->fc.high_water[0]  = fc_conf->high_water;
4794         hw->fc.low_water[0]   = fc_conf->low_water;
4795         hw->fc.send_xon       = fc_conf->send_xon;
4796         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4797         adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4798
4799         err = ixgbe_flow_ctrl_enable(dev, hw);
4800         if (err < 0) {
4801                 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4802                 return -EIO;
4803         }
4804         return err;
4805 }
4806
4807 /**
4808  *  ixgbe_pfc_enable_generic - Enable flow control
4809  *  @hw: pointer to hardware structure
4810  *  @tc_num: traffic class number
4811  *  Enable flow control according to the current settings.
4812  */
4813 static int
4814 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4815 {
4816         int ret_val = 0;
4817         uint32_t mflcn_reg, fccfg_reg;
4818         uint32_t reg;
4819         uint32_t fcrtl, fcrth;
4820         uint8_t i;
4821         uint8_t nb_rx_en;
4822
4823         /* Validate the water mark configuration */
4824         if (!hw->fc.pause_time) {
4825                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4826                 goto out;
4827         }
4828
4829         /* Low water mark of zero causes XOFF floods */
4830         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4831                  /* High/Low water can not be 0 */
4832                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4833                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4834                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4835                         goto out;
4836                 }
4837
4838                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4839                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4840                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4841                         goto out;
4842                 }
4843         }
4844         /* Negotiate the fc mode to use */
4845         ixgbe_fc_autoneg(hw);
4846
4847         /* Disable any previous flow control settings */
4848         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4849         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4850
4851         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4852         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4853
4854         switch (hw->fc.current_mode) {
4855         case ixgbe_fc_none:
4856                 /*
4857                  * If the count of enabled RX Priority Flow control >1,
4858                  * and the TX pause can not be disabled
4859                  */
4860                 nb_rx_en = 0;
4861                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4862                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4863                         if (reg & IXGBE_FCRTH_FCEN)
4864                                 nb_rx_en++;
4865                 }
4866                 if (nb_rx_en > 1)
4867                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4868                 break;
4869         case ixgbe_fc_rx_pause:
4870                 /*
4871                  * Rx Flow control is enabled and Tx Flow control is
4872                  * disabled by software override. Since there really
4873                  * isn't a way to advertise that we are capable of RX
4874                  * Pause ONLY, we will advertise that we support both
4875                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4876                  * disable the adapter's ability to send PAUSE frames.
4877                  */
4878                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4879                 /*
4880                  * If the count of enabled RX Priority Flow control >1,
4881                  * and the TX pause can not be disabled
4882                  */
4883                 nb_rx_en = 0;
4884                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4885                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4886                         if (reg & IXGBE_FCRTH_FCEN)
4887                                 nb_rx_en++;
4888                 }
4889                 if (nb_rx_en > 1)
4890                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4891                 break;
4892         case ixgbe_fc_tx_pause:
4893                 /*
4894                  * Tx Flow control is enabled, and Rx Flow control is
4895                  * disabled by software override.
4896                  */
4897                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4898                 break;
4899         case ixgbe_fc_full:
4900                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4901                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4902                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4903                 break;
4904         default:
4905                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4906                 ret_val = IXGBE_ERR_CONFIG;
4907                 goto out;
4908         }
4909
4910         /* Set 802.3x based flow control settings. */
4911         mflcn_reg |= IXGBE_MFLCN_DPF;
4912         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4913         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4914
4915         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4916         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4917                 hw->fc.high_water[tc_num]) {
4918                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4919                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4920                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4921         } else {
4922                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4923                 /*
4924                  * In order to prevent Tx hangs when the internal Tx
4925                  * switch is enabled we must set the high water mark
4926                  * to the maximum FCRTH value.  This allows the Tx
4927                  * switch to function even under heavy Rx workloads.
4928                  */
4929                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4930         }
4931         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4932
4933         /* Configure pause time (2 TCs per register) */
4934         reg = hw->fc.pause_time * 0x00010001;
4935         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4936                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4937
4938         /* Configure flow control refresh threshold value */
4939         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4940
4941 out:
4942         return ret_val;
4943 }
4944
4945 static int
4946 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4947 {
4948         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4949         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4950
4951         if (hw->mac.type != ixgbe_mac_82598EB) {
4952                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4953         }
4954         return ret_val;
4955 }
4956
4957 static int
4958 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4959 {
4960         int err;
4961         uint32_t rx_buf_size;
4962         uint32_t max_high_water;
4963         uint8_t tc_num;
4964         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4965         struct ixgbe_hw *hw =
4966                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4967         struct ixgbe_dcb_config *dcb_config =
4968                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4969
4970         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4971                 ixgbe_fc_none,
4972                 ixgbe_fc_rx_pause,
4973                 ixgbe_fc_tx_pause,
4974                 ixgbe_fc_full
4975         };
4976
4977         PMD_INIT_FUNC_TRACE();
4978
4979         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4980         tc_num = map[pfc_conf->priority];
4981         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4982         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4983         /*
4984          * At least reserve one Ethernet frame for watermark
4985          * high_water/low_water in kilo bytes for ixgbe
4986          */
4987         max_high_water = (rx_buf_size -
4988                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4989         if ((pfc_conf->fc.high_water > max_high_water) ||
4990             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4991                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4992                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4993                 return -EINVAL;
4994         }
4995
4996         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4997         hw->fc.pause_time = pfc_conf->fc.pause_time;
4998         hw->fc.send_xon = pfc_conf->fc.send_xon;
4999         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
5000         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
5001
5002         err = ixgbe_dcb_pfc_enable(dev, tc_num);
5003
5004         /* Not negotiated is not an error case */
5005         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5006                 return 0;
5007
5008         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5009         return -EIO;
5010 }
5011
5012 static int
5013 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5014                           struct rte_eth_rss_reta_entry64 *reta_conf,
5015                           uint16_t reta_size)
5016 {
5017         uint16_t i, sp_reta_size;
5018         uint8_t j, mask;
5019         uint32_t reta, r;
5020         uint16_t idx, shift;
5021         struct ixgbe_adapter *adapter = dev->data->dev_private;
5022         struct rte_eth_dev_data *dev_data = dev->data;
5023         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5024         uint32_t reta_reg;
5025
5026         PMD_INIT_FUNC_TRACE();
5027
5028         if (!dev_data->dev_started) {
5029                 PMD_DRV_LOG(ERR,
5030                         "port %d must be started before rss reta update",
5031                          dev_data->port_id);
5032                 return -EIO;
5033         }
5034
5035         if (!ixgbe_rss_update_sp(hw->mac.type)) {
5036                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5037                         "NIC.");
5038                 return -ENOTSUP;
5039         }
5040
5041         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5042         if (reta_size != sp_reta_size) {
5043                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5044                         "(%d) doesn't match the number hardware can supported "
5045                         "(%d)", reta_size, sp_reta_size);
5046                 return -EINVAL;
5047         }
5048
5049         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5050                 idx = i / RTE_RETA_GROUP_SIZE;
5051                 shift = i % RTE_RETA_GROUP_SIZE;
5052                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5053                                                 IXGBE_4_BIT_MASK);
5054                 if (!mask)
5055                         continue;
5056                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5057                 if (mask == IXGBE_4_BIT_MASK)
5058                         r = 0;
5059                 else
5060                         r = IXGBE_READ_REG(hw, reta_reg);
5061                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5062                         if (mask & (0x1 << j))
5063                                 reta |= reta_conf[idx].reta[shift + j] <<
5064                                                         (CHAR_BIT * j);
5065                         else
5066                                 reta |= r & (IXGBE_8_BIT_MASK <<
5067                                                 (CHAR_BIT * j));
5068                 }
5069                 IXGBE_WRITE_REG(hw, reta_reg, reta);
5070         }
5071         adapter->rss_reta_updated = 1;
5072
5073         return 0;
5074 }
5075
5076 static int
5077 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5078                          struct rte_eth_rss_reta_entry64 *reta_conf,
5079                          uint16_t reta_size)
5080 {
5081         uint16_t i, sp_reta_size;
5082         uint8_t j, mask;
5083         uint32_t reta;
5084         uint16_t idx, shift;
5085         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5086         uint32_t reta_reg;
5087
5088         PMD_INIT_FUNC_TRACE();
5089         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5090         if (reta_size != sp_reta_size) {
5091                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5092                         "(%d) doesn't match the number hardware can supported "
5093                         "(%d)", reta_size, sp_reta_size);
5094                 return -EINVAL;
5095         }
5096
5097         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5098                 idx = i / RTE_RETA_GROUP_SIZE;
5099                 shift = i % RTE_RETA_GROUP_SIZE;
5100                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5101                                                 IXGBE_4_BIT_MASK);
5102                 if (!mask)
5103                         continue;
5104
5105                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5106                 reta = IXGBE_READ_REG(hw, reta_reg);
5107                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5108                         if (mask & (0x1 << j))
5109                                 reta_conf[idx].reta[shift + j] =
5110                                         ((reta >> (CHAR_BIT * j)) &
5111                                                 IXGBE_8_BIT_MASK);
5112                 }
5113         }
5114
5115         return 0;
5116 }
5117
5118 static int
5119 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5120                                 uint32_t index, uint32_t pool)
5121 {
5122         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5123         uint32_t enable_addr = 1;
5124
5125         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5126                              pool, enable_addr);
5127 }
5128
5129 static void
5130 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5131 {
5132         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5133
5134         ixgbe_clear_rar(hw, index);
5135 }
5136
5137 static int
5138 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5139 {
5140         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5141
5142         ixgbe_remove_rar(dev, 0);
5143         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5144
5145         return 0;
5146 }
5147
5148 static bool
5149 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5150 {
5151         if (strcmp(dev->device->driver->name, drv->driver.name))
5152                 return false;
5153
5154         return true;
5155 }
5156
5157 bool
5158 is_ixgbe_supported(struct rte_eth_dev *dev)
5159 {
5160         return is_device_supported(dev, &rte_ixgbe_pmd);
5161 }
5162
5163 static int
5164 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5165 {
5166         uint32_t hlreg0;
5167         uint32_t maxfrs;
5168         struct ixgbe_hw *hw;
5169         struct rte_eth_dev_info dev_info;
5170         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5171         struct rte_eth_dev_data *dev_data = dev->data;
5172         int ret;
5173
5174         ret = ixgbe_dev_info_get(dev, &dev_info);
5175         if (ret != 0)
5176                 return ret;
5177
5178         /* check that mtu is within the allowed range */
5179         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5180                 return -EINVAL;
5181
5182         /* If device is started, refuse mtu that requires the support of
5183          * scattered packets when this feature has not been enabled before.
5184          */
5185         if (dev_data->dev_started && !dev_data->scattered_rx &&
5186             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5187              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5188                 PMD_INIT_LOG(ERR, "Stop port first.");
5189                 return -EINVAL;
5190         }
5191
5192         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5193         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5194
5195         /* switch to jumbo mode if needed */
5196         if (frame_size > IXGBE_ETH_MAX_LEN) {
5197                 dev->data->dev_conf.rxmode.offloads |=
5198                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5199                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5200         } else {
5201                 dev->data->dev_conf.rxmode.offloads &=
5202                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5203                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5204         }
5205         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5206
5207         /* update max frame size */
5208         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5209
5210         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5211         maxfrs &= 0x0000FFFF;
5212         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5213         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5214
5215         return 0;
5216 }
5217
5218 /*
5219  * Virtual Function operations
5220  */
5221 static void
5222 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5223 {
5224         struct ixgbe_interrupt *intr =
5225                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5226         struct ixgbe_hw *hw =
5227                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5228
5229         PMD_INIT_FUNC_TRACE();
5230
5231         /* Clear interrupt mask to stop from interrupts being generated */
5232         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5233
5234         IXGBE_WRITE_FLUSH(hw);
5235
5236         /* Clear mask value. */
5237         intr->mask = 0;
5238 }
5239
5240 static void
5241 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5242 {
5243         struct ixgbe_interrupt *intr =
5244                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5245         struct ixgbe_hw *hw =
5246                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5247
5248         PMD_INIT_FUNC_TRACE();
5249
5250         /* VF enable interrupt autoclean */
5251         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5252         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5253         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5254
5255         IXGBE_WRITE_FLUSH(hw);
5256
5257         /* Save IXGBE_VTEIMS value to mask. */
5258         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5259 }
5260
5261 static int
5262 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5263 {
5264         struct rte_eth_conf *conf = &dev->data->dev_conf;
5265         struct ixgbe_adapter *adapter = dev->data->dev_private;
5266
5267         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5268                      dev->data->port_id);
5269
5270         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5271                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5272
5273         /*
5274          * VF has no ability to enable/disable HW CRC
5275          * Keep the persistent behavior the same as Host PF
5276          */
5277 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5278         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5279                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5280                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5281         }
5282 #else
5283         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5284                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5285                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5286         }
5287 #endif
5288
5289         /*
5290          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5291          * allocation or vector Rx preconditions we will reset it.
5292          */
5293         adapter->rx_bulk_alloc_allowed = true;
5294         adapter->rx_vec_allowed = true;
5295
5296         return 0;
5297 }
5298
5299 static int
5300 ixgbevf_dev_start(struct rte_eth_dev *dev)
5301 {
5302         struct ixgbe_hw *hw =
5303                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5304         uint32_t intr_vector = 0;
5305         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5306         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5307
5308         int err, mask = 0;
5309
5310         PMD_INIT_FUNC_TRACE();
5311
5312         /* Stop the link setup handler before resetting the HW. */
5313         ixgbe_dev_wait_setup_link_complete(dev, 0);
5314
5315         err = hw->mac.ops.reset_hw(hw);
5316
5317         /**
5318          * In this case, reuses the MAC address assigned by VF
5319          * initialization.
5320          */
5321         if (err != IXGBE_SUCCESS && err != IXGBE_ERR_INVALID_MAC_ADDR) {
5322                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5323                 return err;
5324         }
5325
5326         hw->mac.get_link_status = true;
5327
5328         /* negotiate mailbox API version to use with the PF. */
5329         ixgbevf_negotiate_api(hw);
5330
5331         ixgbevf_dev_tx_init(dev);
5332
5333         /* This can fail when allocating mbufs for descriptor rings */
5334         err = ixgbevf_dev_rx_init(dev);
5335         if (err) {
5336                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5337                 ixgbe_dev_clear_queues(dev);
5338                 return err;
5339         }
5340
5341         /* Set vfta */
5342         ixgbevf_set_vfta_all(dev, 1);
5343
5344         /* Set HW strip */
5345         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5346                 ETH_VLAN_EXTEND_MASK;
5347         err = ixgbevf_vlan_offload_config(dev, mask);
5348         if (err) {
5349                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5350                 ixgbe_dev_clear_queues(dev);
5351                 return err;
5352         }
5353
5354         ixgbevf_dev_rxtx_start(dev);
5355
5356         /* check and configure queue intr-vector mapping */
5357         if (rte_intr_cap_multiple(intr_handle) &&
5358             dev->data->dev_conf.intr_conf.rxq) {
5359                 /* According to datasheet, only vector 0/1/2 can be used,
5360                  * now only one vector is used for Rx queue
5361                  */
5362                 intr_vector = 1;
5363                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5364                         return -1;
5365         }
5366
5367         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5368                 intr_handle->intr_vec =
5369                         rte_zmalloc("intr_vec",
5370                                     dev->data->nb_rx_queues * sizeof(int), 0);
5371                 if (intr_handle->intr_vec == NULL) {
5372                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5373                                      " intr_vec", dev->data->nb_rx_queues);
5374                         return -ENOMEM;
5375                 }
5376         }
5377         ixgbevf_configure_msix(dev);
5378
5379         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5380          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5381          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5382          * is not cleared, it will fail when following rte_intr_enable( ) tries
5383          * to map Rx queue interrupt to other VFIO vectors.
5384          * So clear uio/vfio intr/evevnfd first to avoid failure.
5385          */
5386         rte_intr_disable(intr_handle);
5387
5388         rte_intr_enable(intr_handle);
5389
5390         /* Re-enable interrupt for VF */
5391         ixgbevf_intr_enable(dev);
5392
5393         /*
5394          * Update link status right before return, because it may
5395          * start link configuration process in a separate thread.
5396          */
5397         ixgbevf_dev_link_update(dev, 0);
5398
5399         hw->adapter_stopped = false;
5400
5401         return 0;
5402 }
5403
5404 static int
5405 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5406 {
5407         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5408         struct ixgbe_adapter *adapter = dev->data->dev_private;
5409         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5410         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5411
5412         if (hw->adapter_stopped)
5413                 return 0;
5414
5415         PMD_INIT_FUNC_TRACE();
5416
5417         ixgbe_dev_wait_setup_link_complete(dev, 0);
5418
5419         ixgbevf_intr_disable(dev);
5420
5421         dev->data->dev_started = 0;
5422         hw->adapter_stopped = 1;
5423         ixgbe_stop_adapter(hw);
5424
5425         /*
5426           * Clear what we set, but we still keep shadow_vfta to
5427           * restore after device starts
5428           */
5429         ixgbevf_set_vfta_all(dev, 0);
5430
5431         /* Clear stored conf */
5432         dev->data->scattered_rx = 0;
5433
5434         ixgbe_dev_clear_queues(dev);
5435
5436         /* Clean datapath event and queue/vec mapping */
5437         rte_intr_efd_disable(intr_handle);
5438         if (intr_handle->intr_vec != NULL) {
5439                 rte_free(intr_handle->intr_vec);
5440                 intr_handle->intr_vec = NULL;
5441         }
5442
5443         adapter->rss_reta_updated = 0;
5444
5445         return 0;
5446 }
5447
5448 static int
5449 ixgbevf_dev_close(struct rte_eth_dev *dev)
5450 {
5451         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5452         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5453         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5454         int ret;
5455
5456         PMD_INIT_FUNC_TRACE();
5457         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5458                 return 0;
5459
5460         ixgbe_reset_hw(hw);
5461
5462         ret = ixgbevf_dev_stop(dev);
5463
5464         ixgbe_dev_free_queues(dev);
5465
5466         /**
5467          * Remove the VF MAC address ro ensure
5468          * that the VF traffic goes to the PF
5469          * after stop, close and detach of the VF
5470          **/
5471         ixgbevf_remove_mac_addr(dev, 0);
5472
5473         rte_intr_disable(intr_handle);
5474         rte_intr_callback_unregister(intr_handle,
5475                                      ixgbevf_dev_interrupt_handler, dev);
5476
5477         return ret;
5478 }
5479
5480 /*
5481  * Reset VF device
5482  */
5483 static int
5484 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5485 {
5486         int ret;
5487
5488         ret = eth_ixgbevf_dev_uninit(dev);
5489         if (ret)
5490                 return ret;
5491
5492         ret = eth_ixgbevf_dev_init(dev);
5493
5494         return ret;
5495 }
5496
5497 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5498 {
5499         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5500         struct ixgbe_vfta *shadow_vfta =
5501                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5502         int i = 0, j = 0, vfta = 0, mask = 1;
5503
5504         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5505                 vfta = shadow_vfta->vfta[i];
5506                 if (vfta) {
5507                         mask = 1;
5508                         for (j = 0; j < 32; j++) {
5509                                 if (vfta & mask)
5510                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5511                                                        on, false);
5512                                 mask <<= 1;
5513                         }
5514                 }
5515         }
5516
5517 }
5518
5519 static int
5520 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5521 {
5522         struct ixgbe_hw *hw =
5523                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5524         struct ixgbe_vfta *shadow_vfta =
5525                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5526         uint32_t vid_idx = 0;
5527         uint32_t vid_bit = 0;
5528         int ret = 0;
5529
5530         PMD_INIT_FUNC_TRACE();
5531
5532         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5533         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5534         if (ret) {
5535                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5536                 return ret;
5537         }
5538         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5539         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5540
5541         /* Save what we set and retore it after device reset */
5542         if (on)
5543                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5544         else
5545                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5546
5547         return 0;
5548 }
5549
5550 static void
5551 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5552 {
5553         struct ixgbe_hw *hw =
5554                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5555         uint32_t ctrl;
5556
5557         PMD_INIT_FUNC_TRACE();
5558
5559         if (queue >= hw->mac.max_rx_queues)
5560                 return;
5561
5562         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5563         if (on)
5564                 ctrl |= IXGBE_RXDCTL_VME;
5565         else
5566                 ctrl &= ~IXGBE_RXDCTL_VME;
5567         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5568
5569         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5570 }
5571
5572 static int
5573 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5574 {
5575         struct ixgbe_rx_queue *rxq;
5576         uint16_t i;
5577         int on = 0;
5578
5579         /* VF function only support hw strip feature, others are not support */
5580         if (mask & ETH_VLAN_STRIP_MASK) {
5581                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5582                         rxq = dev->data->rx_queues[i];
5583                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5584                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5585                 }
5586         }
5587
5588         return 0;
5589 }
5590
5591 static int
5592 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5593 {
5594         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5595
5596         ixgbevf_vlan_offload_config(dev, mask);
5597
5598         return 0;
5599 }
5600
5601 int
5602 ixgbe_vt_check(struct ixgbe_hw *hw)
5603 {
5604         uint32_t reg_val;
5605
5606         /* if Virtualization Technology is enabled */
5607         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5608         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5609                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5610                 return -1;
5611         }
5612
5613         return 0;
5614 }
5615
5616 static uint32_t
5617 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5618 {
5619         uint32_t vector = 0;
5620
5621         switch (hw->mac.mc_filter_type) {
5622         case 0:   /* use bits [47:36] of the address */
5623                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5624                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5625                 break;
5626         case 1:   /* use bits [46:35] of the address */
5627                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5628                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5629                 break;
5630         case 2:   /* use bits [45:34] of the address */
5631                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5632                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5633                 break;
5634         case 3:   /* use bits [43:32] of the address */
5635                 vector = ((uc_addr->addr_bytes[4]) |
5636                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5637                 break;
5638         default:  /* Invalid mc_filter_type */
5639                 break;
5640         }
5641
5642         /* vector can only be 12-bits or boundary will be exceeded */
5643         vector &= 0xFFF;
5644         return vector;
5645 }
5646
5647 static int
5648 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5649                         struct rte_ether_addr *mac_addr, uint8_t on)
5650 {
5651         uint32_t vector;
5652         uint32_t uta_idx;
5653         uint32_t reg_val;
5654         uint32_t uta_shift;
5655         uint32_t rc;
5656         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5657         const uint32_t ixgbe_uta_bit_shift = 5;
5658         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5659         const uint32_t bit1 = 0x1;
5660
5661         struct ixgbe_hw *hw =
5662                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5663         struct ixgbe_uta_info *uta_info =
5664                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5665
5666         /* The UTA table only exists on 82599 hardware and newer */
5667         if (hw->mac.type < ixgbe_mac_82599EB)
5668                 return -ENOTSUP;
5669
5670         vector = ixgbe_uta_vector(hw, mac_addr);
5671         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5672         uta_shift = vector & ixgbe_uta_bit_mask;
5673
5674         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5675         if (rc == on)
5676                 return 0;
5677
5678         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5679         if (on) {
5680                 uta_info->uta_in_use++;
5681                 reg_val |= (bit1 << uta_shift);
5682                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5683         } else {
5684                 uta_info->uta_in_use--;
5685                 reg_val &= ~(bit1 << uta_shift);
5686                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5687         }
5688
5689         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5690
5691         if (uta_info->uta_in_use > 0)
5692                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5693                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5694         else
5695                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5696
5697         return 0;
5698 }
5699
5700 static int
5701 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5702 {
5703         int i;
5704         struct ixgbe_hw *hw =
5705                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5706         struct ixgbe_uta_info *uta_info =
5707                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5708
5709         /* The UTA table only exists on 82599 hardware and newer */
5710         if (hw->mac.type < ixgbe_mac_82599EB)
5711                 return -ENOTSUP;
5712
5713         if (on) {
5714                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5715                         uta_info->uta_shadow[i] = ~0;
5716                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5717                 }
5718         } else {
5719                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5720                         uta_info->uta_shadow[i] = 0;
5721                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5722                 }
5723         }
5724         return 0;
5725
5726 }
5727
5728 uint32_t
5729 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5730 {
5731         uint32_t new_val = orig_val;
5732
5733         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5734                 new_val |= IXGBE_VMOLR_AUPE;
5735         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5736                 new_val |= IXGBE_VMOLR_ROMPE;
5737         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5738                 new_val |= IXGBE_VMOLR_ROPE;
5739         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5740                 new_val |= IXGBE_VMOLR_BAM;
5741         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5742                 new_val |= IXGBE_VMOLR_MPE;
5743
5744         return new_val;
5745 }
5746
5747 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5748 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5749 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5750 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5751 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5752         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5753         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5754
5755 static int
5756 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5757                       struct rte_eth_mirror_conf *mirror_conf,
5758                       uint8_t rule_id, uint8_t on)
5759 {
5760         uint32_t mr_ctl, vlvf;
5761         uint32_t mp_lsb = 0;
5762         uint32_t mv_msb = 0;
5763         uint32_t mv_lsb = 0;
5764         uint32_t mp_msb = 0;
5765         uint8_t i = 0;
5766         int reg_index = 0;
5767         uint64_t vlan_mask = 0;
5768
5769         const uint8_t pool_mask_offset = 32;
5770         const uint8_t vlan_mask_offset = 32;
5771         const uint8_t dst_pool_offset = 8;
5772         const uint8_t rule_mr_offset  = 4;
5773         const uint8_t mirror_rule_mask = 0x0F;
5774
5775         struct ixgbe_mirror_info *mr_info =
5776                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5777         struct ixgbe_hw *hw =
5778                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5779         uint8_t mirror_type = 0;
5780
5781         if (ixgbe_vt_check(hw) < 0)
5782                 return -ENOTSUP;
5783
5784         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5785                 return -EINVAL;
5786
5787         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5788                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5789                             mirror_conf->rule_type);
5790                 return -EINVAL;
5791         }
5792
5793         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5794                 mirror_type |= IXGBE_MRCTL_VLME;
5795                 /* Check if vlan id is valid and find conresponding VLAN ID
5796                  * index in VLVF
5797                  */
5798                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5799                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5800                                 /* search vlan id related pool vlan filter
5801                                  * index
5802                                  */
5803                                 reg_index = ixgbe_find_vlvf_slot(
5804                                                 hw,
5805                                                 mirror_conf->vlan.vlan_id[i],
5806                                                 false);
5807                                 if (reg_index < 0)
5808                                         return -EINVAL;
5809                                 vlvf = IXGBE_READ_REG(hw,
5810                                                       IXGBE_VLVF(reg_index));
5811                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5812                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5813                                       mirror_conf->vlan.vlan_id[i]))
5814                                         vlan_mask |= (1ULL << reg_index);
5815                                 else
5816                                         return -EINVAL;
5817                         }
5818                 }
5819
5820                 if (on) {
5821                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5822                         mv_msb = vlan_mask >> vlan_mask_offset;
5823
5824                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5825                                                 mirror_conf->vlan.vlan_mask;
5826                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5827                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5828                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5829                                                 mirror_conf->vlan.vlan_id[i];
5830                         }
5831                 } else {
5832                         mv_lsb = 0;
5833                         mv_msb = 0;
5834                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5835                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5836                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5837                 }
5838         }
5839
5840         /**
5841          * if enable pool mirror, write related pool mask register,if disable
5842          * pool mirror, clear PFMRVM register
5843          */
5844         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5845                 mirror_type |= IXGBE_MRCTL_VPME;
5846                 if (on) {
5847                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5848                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5849                         mr_info->mr_conf[rule_id].pool_mask =
5850                                         mirror_conf->pool_mask;
5851
5852                 } else {
5853                         mp_lsb = 0;
5854                         mp_msb = 0;
5855                         mr_info->mr_conf[rule_id].pool_mask = 0;
5856                 }
5857         }
5858         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5859                 mirror_type |= IXGBE_MRCTL_UPME;
5860         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5861                 mirror_type |= IXGBE_MRCTL_DPME;
5862
5863         /* read  mirror control register and recalculate it */
5864         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5865
5866         if (on) {
5867                 mr_ctl |= mirror_type;
5868                 mr_ctl &= mirror_rule_mask;
5869                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5870         } else {
5871                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5872         }
5873
5874         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5875         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5876
5877         /* write mirrror control  register */
5878         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5879
5880         /* write pool mirrror control  register */
5881         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5882                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5883                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5884                                 mp_msb);
5885         }
5886         /* write VLAN mirrror control  register */
5887         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5888                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5889                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5890                                 mv_msb);
5891         }
5892
5893         return 0;
5894 }
5895
5896 static int
5897 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5898 {
5899         int mr_ctl = 0;
5900         uint32_t lsb_val = 0;
5901         uint32_t msb_val = 0;
5902         const uint8_t rule_mr_offset = 4;
5903
5904         struct ixgbe_hw *hw =
5905                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5906         struct ixgbe_mirror_info *mr_info =
5907                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5908
5909         if (ixgbe_vt_check(hw) < 0)
5910                 return -ENOTSUP;
5911
5912         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5913                 return -EINVAL;
5914
5915         memset(&mr_info->mr_conf[rule_id], 0,
5916                sizeof(struct rte_eth_mirror_conf));
5917
5918         /* clear PFVMCTL register */
5919         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5920
5921         /* clear pool mask register */
5922         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5923         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5924
5925         /* clear vlan mask register */
5926         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5927         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5928
5929         return 0;
5930 }
5931
5932 static int
5933 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5934 {
5935         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5936         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5937         struct ixgbe_interrupt *intr =
5938                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5939         struct ixgbe_hw *hw =
5940                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5941         uint32_t vec = IXGBE_MISC_VEC_ID;
5942
5943         if (rte_intr_allow_others(intr_handle))
5944                 vec = IXGBE_RX_VEC_START;
5945         intr->mask |= (1 << vec);
5946         RTE_SET_USED(queue_id);
5947         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5948
5949         rte_intr_ack(intr_handle);
5950
5951         return 0;
5952 }
5953
5954 static int
5955 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5956 {
5957         struct ixgbe_interrupt *intr =
5958                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5959         struct ixgbe_hw *hw =
5960                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5961         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5962         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5963         uint32_t vec = IXGBE_MISC_VEC_ID;
5964
5965         if (rte_intr_allow_others(intr_handle))
5966                 vec = IXGBE_RX_VEC_START;
5967         intr->mask &= ~(1 << vec);
5968         RTE_SET_USED(queue_id);
5969         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5970
5971         return 0;
5972 }
5973
5974 static int
5975 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5976 {
5977         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5978         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5979         uint32_t mask;
5980         struct ixgbe_hw *hw =
5981                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5982         struct ixgbe_interrupt *intr =
5983                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5984
5985         if (queue_id < 16) {
5986                 ixgbe_disable_intr(hw);
5987                 intr->mask |= (1 << queue_id);
5988                 ixgbe_enable_intr(dev);
5989         } else if (queue_id < 32) {
5990                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5991                 mask &= (1 << queue_id);
5992                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5993         } else if (queue_id < 64) {
5994                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5995                 mask &= (1 << (queue_id - 32));
5996                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5997         }
5998         rte_intr_ack(intr_handle);
5999
6000         return 0;
6001 }
6002
6003 static int
6004 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
6005 {
6006         uint32_t mask;
6007         struct ixgbe_hw *hw =
6008                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6009         struct ixgbe_interrupt *intr =
6010                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
6011
6012         if (queue_id < 16) {
6013                 ixgbe_disable_intr(hw);
6014                 intr->mask &= ~(1 << queue_id);
6015                 ixgbe_enable_intr(dev);
6016         } else if (queue_id < 32) {
6017                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
6018                 mask &= ~(1 << queue_id);
6019                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6020         } else if (queue_id < 64) {
6021                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6022                 mask &= ~(1 << (queue_id - 32));
6023                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6024         }
6025
6026         return 0;
6027 }
6028
6029 static void
6030 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6031                      uint8_t queue, uint8_t msix_vector)
6032 {
6033         uint32_t tmp, idx;
6034
6035         if (direction == -1) {
6036                 /* other causes */
6037                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6038                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
6039                 tmp &= ~0xFF;
6040                 tmp |= msix_vector;
6041                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6042         } else {
6043                 /* rx or tx cause */
6044                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6045                 idx = ((16 * (queue & 1)) + (8 * direction));
6046                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6047                 tmp &= ~(0xFF << idx);
6048                 tmp |= (msix_vector << idx);
6049                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6050         }
6051 }
6052
6053 /**
6054  * set the IVAR registers, mapping interrupt causes to vectors
6055  * @param hw
6056  *  pointer to ixgbe_hw struct
6057  * @direction
6058  *  0 for Rx, 1 for Tx, -1 for other causes
6059  * @queue
6060  *  queue to map the corresponding interrupt to
6061  * @msix_vector
6062  *  the vector to map to the corresponding queue
6063  */
6064 static void
6065 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6066                    uint8_t queue, uint8_t msix_vector)
6067 {
6068         uint32_t tmp, idx;
6069
6070         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6071         if (hw->mac.type == ixgbe_mac_82598EB) {
6072                 if (direction == -1)
6073                         direction = 0;
6074                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6075                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6076                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6077                 tmp |= (msix_vector << (8 * (queue & 0x3)));
6078                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6079         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6080                         (hw->mac.type == ixgbe_mac_X540) ||
6081                         (hw->mac.type == ixgbe_mac_X550) ||
6082                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
6083                 if (direction == -1) {
6084                         /* other causes */
6085                         idx = ((queue & 1) * 8);
6086                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6087                         tmp &= ~(0xFF << idx);
6088                         tmp |= (msix_vector << idx);
6089                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6090                 } else {
6091                         /* rx or tx causes */
6092                         idx = ((16 * (queue & 1)) + (8 * direction));
6093                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6094                         tmp &= ~(0xFF << idx);
6095                         tmp |= (msix_vector << idx);
6096                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6097                 }
6098         }
6099 }
6100
6101 static void
6102 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6103 {
6104         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6105         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6106         struct ixgbe_hw *hw =
6107                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6108         uint32_t q_idx;
6109         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6110         uint32_t base = IXGBE_MISC_VEC_ID;
6111
6112         /* Configure VF other cause ivar */
6113         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6114
6115         /* won't configure msix register if no mapping is done
6116          * between intr vector and event fd.
6117          */
6118         if (!rte_intr_dp_is_en(intr_handle))
6119                 return;
6120
6121         if (rte_intr_allow_others(intr_handle)) {
6122                 base = IXGBE_RX_VEC_START;
6123                 vector_idx = IXGBE_RX_VEC_START;
6124         }
6125
6126         /* Configure all RX queues of VF */
6127         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6128                 /* Force all queue use vector 0,
6129                  * as IXGBE_VF_MAXMSIVECOTR = 1
6130                  */
6131                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6132                 intr_handle->intr_vec[q_idx] = vector_idx;
6133                 if (vector_idx < base + intr_handle->nb_efd - 1)
6134                         vector_idx++;
6135         }
6136
6137         /* As RX queue setting above show, all queues use the vector 0.
6138          * Set only the ITR value of IXGBE_MISC_VEC_ID.
6139          */
6140         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6141                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6142                         | IXGBE_EITR_CNT_WDIS);
6143 }
6144
6145 /**
6146  * Sets up the hardware to properly generate MSI-X interrupts
6147  * @hw
6148  *  board private structure
6149  */
6150 static void
6151 ixgbe_configure_msix(struct rte_eth_dev *dev)
6152 {
6153         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6154         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6155         struct ixgbe_hw *hw =
6156                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6157         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6158         uint32_t vec = IXGBE_MISC_VEC_ID;
6159         uint32_t mask;
6160         uint32_t gpie;
6161
6162         /* won't configure msix register if no mapping is done
6163          * between intr vector and event fd
6164          * but if misx has been enabled already, need to configure
6165          * auto clean, auto mask and throttling.
6166          */
6167         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6168         if (!rte_intr_dp_is_en(intr_handle) &&
6169             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6170                 return;
6171
6172         if (rte_intr_allow_others(intr_handle))
6173                 vec = base = IXGBE_RX_VEC_START;
6174
6175         /* setup GPIE for MSI-x mode */
6176         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6177         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6178                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6179         /* auto clearing and auto setting corresponding bits in EIMS
6180          * when MSI-X interrupt is triggered
6181          */
6182         if (hw->mac.type == ixgbe_mac_82598EB) {
6183                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6184         } else {
6185                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6186                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6187         }
6188         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6189
6190         /* Populate the IVAR table and set the ITR values to the
6191          * corresponding register.
6192          */
6193         if (rte_intr_dp_is_en(intr_handle)) {
6194                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6195                         queue_id++) {
6196                         /* by default, 1:1 mapping */
6197                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6198                         intr_handle->intr_vec[queue_id] = vec;
6199                         if (vec < base + intr_handle->nb_efd - 1)
6200                                 vec++;
6201                 }
6202
6203                 switch (hw->mac.type) {
6204                 case ixgbe_mac_82598EB:
6205                         ixgbe_set_ivar_map(hw, -1,
6206                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6207                                            IXGBE_MISC_VEC_ID);
6208                         break;
6209                 case ixgbe_mac_82599EB:
6210                 case ixgbe_mac_X540:
6211                 case ixgbe_mac_X550:
6212                 case ixgbe_mac_X550EM_x:
6213                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6214                         break;
6215                 default:
6216                         break;
6217                 }
6218         }
6219         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6220                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6221                         | IXGBE_EITR_CNT_WDIS);
6222
6223         /* set up to autoclear timer, and the vectors */
6224         mask = IXGBE_EIMS_ENABLE_MASK;
6225         mask &= ~(IXGBE_EIMS_OTHER |
6226                   IXGBE_EIMS_MAILBOX |
6227                   IXGBE_EIMS_LSC);
6228
6229         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6230 }
6231
6232 int
6233 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6234                            uint16_t queue_idx, uint16_t tx_rate)
6235 {
6236         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6237         struct rte_eth_rxmode *rxmode;
6238         uint32_t rf_dec, rf_int;
6239         uint32_t bcnrc_val;
6240         uint16_t link_speed = dev->data->dev_link.link_speed;
6241
6242         if (queue_idx >= hw->mac.max_tx_queues)
6243                 return -EINVAL;
6244
6245         if (tx_rate != 0) {
6246                 /* Calculate the rate factor values to set */
6247                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6248                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6249                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6250
6251                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6252                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6253                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6254                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6255         } else {
6256                 bcnrc_val = 0;
6257         }
6258
6259         rxmode = &dev->data->dev_conf.rxmode;
6260         /*
6261          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6262          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6263          * set as 0x4.
6264          */
6265         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6266             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6267                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6268                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6269         else
6270                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6271                         IXGBE_MMW_SIZE_DEFAULT);
6272
6273         /* Set RTTBCNRC of queue X */
6274         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6275         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6276         IXGBE_WRITE_FLUSH(hw);
6277
6278         return 0;
6279 }
6280
6281 static int
6282 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6283                      __rte_unused uint32_t index,
6284                      __rte_unused uint32_t pool)
6285 {
6286         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6287         int diag;
6288
6289         /*
6290          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6291          * operation. Trap this case to avoid exhausting the [very limited]
6292          * set of PF resources used to store VF MAC addresses.
6293          */
6294         if (memcmp(hw->mac.perm_addr, mac_addr,
6295                         sizeof(struct rte_ether_addr)) == 0)
6296                 return -1;
6297         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6298         if (diag != 0)
6299                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6300                             RTE_ETHER_ADDR_PRT_FMT " - diag=%d",
6301                             RTE_ETHER_ADDR_BYTES(mac_addr), diag);
6302         return diag;
6303 }
6304
6305 static void
6306 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6307 {
6308         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6309         struct rte_ether_addr *perm_addr =
6310                 (struct rte_ether_addr *)hw->mac.perm_addr;
6311         struct rte_ether_addr *mac_addr;
6312         uint32_t i;
6313         int diag;
6314
6315         /*
6316          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6317          * not support the deletion of a given MAC address.
6318          * Instead, it imposes to delete all MAC addresses, then to add again
6319          * all MAC addresses with the exception of the one to be deleted.
6320          */
6321         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6322
6323         /*
6324          * Add again all MAC addresses, with the exception of the deleted one
6325          * and of the permanent MAC address.
6326          */
6327         for (i = 0, mac_addr = dev->data->mac_addrs;
6328              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6329                 /* Skip the deleted MAC address */
6330                 if (i == index)
6331                         continue;
6332                 /* Skip NULL MAC addresses */
6333                 if (rte_is_zero_ether_addr(mac_addr))
6334                         continue;
6335                 /* Skip the permanent MAC address */
6336                 if (memcmp(perm_addr, mac_addr,
6337                                 sizeof(struct rte_ether_addr)) == 0)
6338                         continue;
6339                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6340                 if (diag != 0)
6341                         PMD_DRV_LOG(ERR,
6342                                     "Adding again MAC address "
6343                                      RTE_ETHER_ADDR_PRT_FMT " failed "
6344                                     "diag=%d", RTE_ETHER_ADDR_BYTES(mac_addr),
6345                                     diag);
6346         }
6347 }
6348
6349 static int
6350 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6351                         struct rte_ether_addr *addr)
6352 {
6353         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6354
6355         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6356
6357         return 0;
6358 }
6359
6360 int
6361 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6362                         struct rte_eth_syn_filter *filter,
6363                         bool add)
6364 {
6365         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6366         struct ixgbe_filter_info *filter_info =
6367                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6368         uint32_t syn_info;
6369         uint32_t synqf;
6370
6371         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6372                 return -EINVAL;
6373
6374         syn_info = filter_info->syn_info;
6375
6376         if (add) {
6377                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6378                         return -EINVAL;
6379                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6380                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6381
6382                 if (filter->hig_pri)
6383                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6384                 else
6385                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6386         } else {
6387                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6388                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6389                         return -ENOENT;
6390                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6391         }
6392
6393         filter_info->syn_info = synqf;
6394         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6395         IXGBE_WRITE_FLUSH(hw);
6396         return 0;
6397 }
6398
6399
6400 static inline enum ixgbe_5tuple_protocol
6401 convert_protocol_type(uint8_t protocol_value)
6402 {
6403         if (protocol_value == IPPROTO_TCP)
6404                 return IXGBE_FILTER_PROTOCOL_TCP;
6405         else if (protocol_value == IPPROTO_UDP)
6406                 return IXGBE_FILTER_PROTOCOL_UDP;
6407         else if (protocol_value == IPPROTO_SCTP)
6408                 return IXGBE_FILTER_PROTOCOL_SCTP;
6409         else
6410                 return IXGBE_FILTER_PROTOCOL_NONE;
6411 }
6412
6413 /* inject a 5-tuple filter to HW */
6414 static inline void
6415 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6416                            struct ixgbe_5tuple_filter *filter)
6417 {
6418         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6419         int i;
6420         uint32_t ftqf, sdpqf;
6421         uint32_t l34timir = 0;
6422         uint8_t mask = 0xff;
6423
6424         i = filter->index;
6425
6426         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6427                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6428         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6429
6430         ftqf = (uint32_t)(filter->filter_info.proto &
6431                 IXGBE_FTQF_PROTOCOL_MASK);
6432         ftqf |= (uint32_t)((filter->filter_info.priority &
6433                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6434         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6435                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6436         if (filter->filter_info.dst_ip_mask == 0)
6437                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6438         if (filter->filter_info.src_port_mask == 0)
6439                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6440         if (filter->filter_info.dst_port_mask == 0)
6441                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6442         if (filter->filter_info.proto_mask == 0)
6443                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6444         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6445         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6446         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6447
6448         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6449         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6450         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6451         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6452
6453         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6454         l34timir |= (uint32_t)(filter->queue <<
6455                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6456         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6457 }
6458
6459 /*
6460  * add a 5tuple filter
6461  *
6462  * @param
6463  * dev: Pointer to struct rte_eth_dev.
6464  * index: the index the filter allocates.
6465  * filter: ponter to the filter that will be added.
6466  * rx_queue: the queue id the filter assigned to.
6467  *
6468  * @return
6469  *    - On success, zero.
6470  *    - On failure, a negative value.
6471  */
6472 static int
6473 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6474                         struct ixgbe_5tuple_filter *filter)
6475 {
6476         struct ixgbe_filter_info *filter_info =
6477                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6478         int i, idx, shift;
6479
6480         /*
6481          * look for an unused 5tuple filter index,
6482          * and insert the filter to list.
6483          */
6484         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6485                 idx = i / (sizeof(uint32_t) * NBBY);
6486                 shift = i % (sizeof(uint32_t) * NBBY);
6487                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6488                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6489                         filter->index = i;
6490                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6491                                           filter,
6492                                           entries);
6493                         break;
6494                 }
6495         }
6496         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6497                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6498                 return -ENOSYS;
6499         }
6500
6501         ixgbe_inject_5tuple_filter(dev, filter);
6502
6503         return 0;
6504 }
6505
6506 /*
6507  * remove a 5tuple filter
6508  *
6509  * @param
6510  * dev: Pointer to struct rte_eth_dev.
6511  * filter: the pointer of the filter will be removed.
6512  */
6513 static void
6514 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6515                         struct ixgbe_5tuple_filter *filter)
6516 {
6517         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6518         struct ixgbe_filter_info *filter_info =
6519                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6520         uint16_t index = filter->index;
6521
6522         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6523                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6524         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6525         rte_free(filter);
6526
6527         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6528         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6529         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6530         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6531         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6532 }
6533
6534 static int
6535 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6536 {
6537         struct ixgbe_hw *hw;
6538         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6539         struct rte_eth_dev_data *dev_data = dev->data;
6540
6541         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6542
6543         if (mtu < RTE_ETHER_MIN_MTU ||
6544                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6545                 return -EINVAL;
6546
6547         /* If device is started, refuse mtu that requires the support of
6548          * scattered packets when this feature has not been enabled before.
6549          */
6550         if (dev_data->dev_started && !dev_data->scattered_rx &&
6551             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6552              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6553                 PMD_INIT_LOG(ERR, "Stop port first.");
6554                 return -EINVAL;
6555         }
6556
6557         /*
6558          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6559          * request of the version 2.0 of the mailbox API.
6560          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6561          * of the mailbox API.
6562          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6563          * prior to 3.11.33 which contains the following change:
6564          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6565          */
6566         if (ixgbevf_rlpml_set_vf(hw, max_frame))
6567                 return -EINVAL;
6568
6569         /* update max frame size */
6570         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6571         return 0;
6572 }
6573
6574 static inline struct ixgbe_5tuple_filter *
6575 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6576                         struct ixgbe_5tuple_filter_info *key)
6577 {
6578         struct ixgbe_5tuple_filter *it;
6579
6580         TAILQ_FOREACH(it, filter_list, entries) {
6581                 if (memcmp(key, &it->filter_info,
6582                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6583                         return it;
6584                 }
6585         }
6586         return NULL;
6587 }
6588
6589 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6590 static inline int
6591 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6592                         struct ixgbe_5tuple_filter_info *filter_info)
6593 {
6594         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6595                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6596                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6597                 return -EINVAL;
6598
6599         switch (filter->dst_ip_mask) {
6600         case UINT32_MAX:
6601                 filter_info->dst_ip_mask = 0;
6602                 filter_info->dst_ip = filter->dst_ip;
6603                 break;
6604         case 0:
6605                 filter_info->dst_ip_mask = 1;
6606                 break;
6607         default:
6608                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6609                 return -EINVAL;
6610         }
6611
6612         switch (filter->src_ip_mask) {
6613         case UINT32_MAX:
6614                 filter_info->src_ip_mask = 0;
6615                 filter_info->src_ip = filter->src_ip;
6616                 break;
6617         case 0:
6618                 filter_info->src_ip_mask = 1;
6619                 break;
6620         default:
6621                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6622                 return -EINVAL;
6623         }
6624
6625         switch (filter->dst_port_mask) {
6626         case UINT16_MAX:
6627                 filter_info->dst_port_mask = 0;
6628                 filter_info->dst_port = filter->dst_port;
6629                 break;
6630         case 0:
6631                 filter_info->dst_port_mask = 1;
6632                 break;
6633         default:
6634                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6635                 return -EINVAL;
6636         }
6637
6638         switch (filter->src_port_mask) {
6639         case UINT16_MAX:
6640                 filter_info->src_port_mask = 0;
6641                 filter_info->src_port = filter->src_port;
6642                 break;
6643         case 0:
6644                 filter_info->src_port_mask = 1;
6645                 break;
6646         default:
6647                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6648                 return -EINVAL;
6649         }
6650
6651         switch (filter->proto_mask) {
6652         case UINT8_MAX:
6653                 filter_info->proto_mask = 0;
6654                 filter_info->proto =
6655                         convert_protocol_type(filter->proto);
6656                 break;
6657         case 0:
6658                 filter_info->proto_mask = 1;
6659                 break;
6660         default:
6661                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6662                 return -EINVAL;
6663         }
6664
6665         filter_info->priority = (uint8_t)filter->priority;
6666         return 0;
6667 }
6668
6669 /*
6670  * add or delete a ntuple filter
6671  *
6672  * @param
6673  * dev: Pointer to struct rte_eth_dev.
6674  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6675  * add: if true, add filter, if false, remove filter
6676  *
6677  * @return
6678  *    - On success, zero.
6679  *    - On failure, a negative value.
6680  */
6681 int
6682 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6683                         struct rte_eth_ntuple_filter *ntuple_filter,
6684                         bool add)
6685 {
6686         struct ixgbe_filter_info *filter_info =
6687                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6688         struct ixgbe_5tuple_filter_info filter_5tuple;
6689         struct ixgbe_5tuple_filter *filter;
6690         int ret;
6691
6692         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6693                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6694                 return -EINVAL;
6695         }
6696
6697         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6698         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6699         if (ret < 0)
6700                 return ret;
6701
6702         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6703                                          &filter_5tuple);
6704         if (filter != NULL && add) {
6705                 PMD_DRV_LOG(ERR, "filter exists.");
6706                 return -EEXIST;
6707         }
6708         if (filter == NULL && !add) {
6709                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6710                 return -ENOENT;
6711         }
6712
6713         if (add) {
6714                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6715                                 sizeof(struct ixgbe_5tuple_filter), 0);
6716                 if (filter == NULL)
6717                         return -ENOMEM;
6718                 rte_memcpy(&filter->filter_info,
6719                                  &filter_5tuple,
6720                                  sizeof(struct ixgbe_5tuple_filter_info));
6721                 filter->queue = ntuple_filter->queue;
6722                 ret = ixgbe_add_5tuple_filter(dev, filter);
6723                 if (ret < 0) {
6724                         rte_free(filter);
6725                         return ret;
6726                 }
6727         } else
6728                 ixgbe_remove_5tuple_filter(dev, filter);
6729
6730         return 0;
6731 }
6732
6733 int
6734 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6735                         struct rte_eth_ethertype_filter *filter,
6736                         bool add)
6737 {
6738         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6739         struct ixgbe_filter_info *filter_info =
6740                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6741         uint32_t etqf = 0;
6742         uint32_t etqs = 0;
6743         int ret;
6744         struct ixgbe_ethertype_filter ethertype_filter;
6745
6746         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6747                 return -EINVAL;
6748
6749         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6750                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6751                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6752                         " ethertype filter.", filter->ether_type);
6753                 return -EINVAL;
6754         }
6755
6756         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6757                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6758                 return -EINVAL;
6759         }
6760         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6761                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6762                 return -EINVAL;
6763         }
6764
6765         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6766         if (ret >= 0 && add) {
6767                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6768                             filter->ether_type);
6769                 return -EEXIST;
6770         }
6771         if (ret < 0 && !add) {
6772                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6773                             filter->ether_type);
6774                 return -ENOENT;
6775         }
6776
6777         if (add) {
6778                 etqf = IXGBE_ETQF_FILTER_EN;
6779                 etqf |= (uint32_t)filter->ether_type;
6780                 etqs |= (uint32_t)((filter->queue <<
6781                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6782                                     IXGBE_ETQS_RX_QUEUE);
6783                 etqs |= IXGBE_ETQS_QUEUE_EN;
6784
6785                 ethertype_filter.ethertype = filter->ether_type;
6786                 ethertype_filter.etqf = etqf;
6787                 ethertype_filter.etqs = etqs;
6788                 ethertype_filter.conf = FALSE;
6789                 ret = ixgbe_ethertype_filter_insert(filter_info,
6790                                                     &ethertype_filter);
6791                 if (ret < 0) {
6792                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6793                         return -ENOSPC;
6794                 }
6795         } else {
6796                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6797                 if (ret < 0)
6798                         return -ENOSYS;
6799         }
6800         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6801         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6802         IXGBE_WRITE_FLUSH(hw);
6803
6804         return 0;
6805 }
6806
6807 static int
6808 ixgbe_dev_flow_ops_get(__rte_unused struct rte_eth_dev *dev,
6809                        const struct rte_flow_ops **ops)
6810 {
6811         *ops = &ixgbe_flow_ops;
6812         return 0;
6813 }
6814
6815 static u8 *
6816 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
6817                         u8 **mc_addr_ptr, u32 *vmdq)
6818 {
6819         u8 *mc_addr;
6820
6821         *vmdq = 0;
6822         mc_addr = *mc_addr_ptr;
6823         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6824         return mc_addr;
6825 }
6826
6827 static int
6828 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6829                           struct rte_ether_addr *mc_addr_set,
6830                           uint32_t nb_mc_addr)
6831 {
6832         struct ixgbe_hw *hw;
6833         u8 *mc_addr_list;
6834
6835         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6836         mc_addr_list = (u8 *)mc_addr_set;
6837         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6838                                          ixgbe_dev_addr_list_itr, TRUE);
6839 }
6840
6841 static uint64_t
6842 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6843 {
6844         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6845         uint64_t systime_cycles;
6846
6847         switch (hw->mac.type) {
6848         case ixgbe_mac_X550:
6849         case ixgbe_mac_X550EM_x:
6850         case ixgbe_mac_X550EM_a:
6851                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6852                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6853                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6854                                 * NSEC_PER_SEC;
6855                 break;
6856         default:
6857                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6858                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6859                                 << 32;
6860         }
6861
6862         return systime_cycles;
6863 }
6864
6865 static uint64_t
6866 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6867 {
6868         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6869         uint64_t rx_tstamp_cycles;
6870
6871         switch (hw->mac.type) {
6872         case ixgbe_mac_X550:
6873         case ixgbe_mac_X550EM_x:
6874         case ixgbe_mac_X550EM_a:
6875                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6876                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6877                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6878                                 * NSEC_PER_SEC;
6879                 break;
6880         default:
6881                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6882                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6883                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6884                                 << 32;
6885         }
6886
6887         return rx_tstamp_cycles;
6888 }
6889
6890 static uint64_t
6891 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6892 {
6893         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6894         uint64_t tx_tstamp_cycles;
6895
6896         switch (hw->mac.type) {
6897         case ixgbe_mac_X550:
6898         case ixgbe_mac_X550EM_x:
6899         case ixgbe_mac_X550EM_a:
6900                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6901                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6902                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6903                                 * NSEC_PER_SEC;
6904                 break;
6905         default:
6906                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6907                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6908                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6909                                 << 32;
6910         }
6911
6912         return tx_tstamp_cycles;
6913 }
6914
6915 static void
6916 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6917 {
6918         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6919         struct ixgbe_adapter *adapter = dev->data->dev_private;
6920         struct rte_eth_link link;
6921         uint32_t incval = 0;
6922         uint32_t shift = 0;
6923
6924         /* Get current link speed. */
6925         ixgbe_dev_link_update(dev, 1);
6926         rte_eth_linkstatus_get(dev, &link);
6927
6928         switch (link.link_speed) {
6929         case ETH_SPEED_NUM_100M:
6930                 incval = IXGBE_INCVAL_100;
6931                 shift = IXGBE_INCVAL_SHIFT_100;
6932                 break;
6933         case ETH_SPEED_NUM_1G:
6934                 incval = IXGBE_INCVAL_1GB;
6935                 shift = IXGBE_INCVAL_SHIFT_1GB;
6936                 break;
6937         case ETH_SPEED_NUM_10G:
6938         default:
6939                 incval = IXGBE_INCVAL_10GB;
6940                 shift = IXGBE_INCVAL_SHIFT_10GB;
6941                 break;
6942         }
6943
6944         switch (hw->mac.type) {
6945         case ixgbe_mac_X550:
6946         case ixgbe_mac_X550EM_x:
6947         case ixgbe_mac_X550EM_a:
6948                 /* Independent of link speed. */
6949                 incval = 1;
6950                 /* Cycles read will be interpreted as ns. */
6951                 shift = 0;
6952                 /* Fall-through */
6953         case ixgbe_mac_X540:
6954                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6955                 break;
6956         case ixgbe_mac_82599EB:
6957                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6958                 shift -= IXGBE_INCVAL_SHIFT_82599;
6959                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6960                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6961                 break;
6962         default:
6963                 /* Not supported. */
6964                 return;
6965         }
6966
6967         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6968         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6969         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6970
6971         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6972         adapter->systime_tc.cc_shift = shift;
6973         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6974
6975         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6976         adapter->rx_tstamp_tc.cc_shift = shift;
6977         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6978
6979         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6980         adapter->tx_tstamp_tc.cc_shift = shift;
6981         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6982 }
6983
6984 static int
6985 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6986 {
6987         struct ixgbe_adapter *adapter = dev->data->dev_private;
6988
6989         adapter->systime_tc.nsec += delta;
6990         adapter->rx_tstamp_tc.nsec += delta;
6991         adapter->tx_tstamp_tc.nsec += delta;
6992
6993         return 0;
6994 }
6995
6996 static int
6997 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6998 {
6999         uint64_t ns;
7000         struct ixgbe_adapter *adapter = dev->data->dev_private;
7001
7002         ns = rte_timespec_to_ns(ts);
7003         /* Set the timecounters to a new value. */
7004         adapter->systime_tc.nsec = ns;
7005         adapter->rx_tstamp_tc.nsec = ns;
7006         adapter->tx_tstamp_tc.nsec = ns;
7007
7008         return 0;
7009 }
7010
7011 static int
7012 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7013 {
7014         uint64_t ns, systime_cycles;
7015         struct ixgbe_adapter *adapter = dev->data->dev_private;
7016
7017         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7018         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7019         *ts = rte_ns_to_timespec(ns);
7020
7021         return 0;
7022 }
7023
7024 static int
7025 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7026 {
7027         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7028         uint32_t tsync_ctl;
7029         uint32_t tsauxc;
7030
7031         /* Stop the timesync system time. */
7032         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7033         /* Reset the timesync system time value. */
7034         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7035         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7036
7037         /* Enable system time for platforms where it isn't on by default. */
7038         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7039         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7040         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7041
7042         ixgbe_start_timecounters(dev);
7043
7044         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7045         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7046                         (RTE_ETHER_TYPE_1588 |
7047                          IXGBE_ETQF_FILTER_EN |
7048                          IXGBE_ETQF_1588));
7049
7050         /* Enable timestamping of received PTP packets. */
7051         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7052         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7053         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7054
7055         /* Enable timestamping of transmitted PTP packets. */
7056         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7057         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7058         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7059
7060         IXGBE_WRITE_FLUSH(hw);
7061
7062         return 0;
7063 }
7064
7065 static int
7066 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7067 {
7068         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7069         uint32_t tsync_ctl;
7070
7071         /* Disable timestamping of transmitted PTP packets. */
7072         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7073         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7074         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7075
7076         /* Disable timestamping of received PTP packets. */
7077         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7078         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7079         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7080
7081         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7082         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7083
7084         /* Stop incrementating the System Time registers. */
7085         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7086
7087         return 0;
7088 }
7089
7090 static int
7091 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7092                                  struct timespec *timestamp,
7093                                  uint32_t flags __rte_unused)
7094 {
7095         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7096         struct ixgbe_adapter *adapter = dev->data->dev_private;
7097         uint32_t tsync_rxctl;
7098         uint64_t rx_tstamp_cycles;
7099         uint64_t ns;
7100
7101         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7102         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7103                 return -EINVAL;
7104
7105         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7106         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7107         *timestamp = rte_ns_to_timespec(ns);
7108
7109         return  0;
7110 }
7111
7112 static int
7113 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7114                                  struct timespec *timestamp)
7115 {
7116         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7117         struct ixgbe_adapter *adapter = dev->data->dev_private;
7118         uint32_t tsync_txctl;
7119         uint64_t tx_tstamp_cycles;
7120         uint64_t ns;
7121
7122         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7123         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7124                 return -EINVAL;
7125
7126         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7127         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7128         *timestamp = rte_ns_to_timespec(ns);
7129
7130         return 0;
7131 }
7132
7133 static int
7134 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7135 {
7136         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7137         int count = 0;
7138         int g_ind = 0;
7139         const struct reg_info *reg_group;
7140         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7141                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7142
7143         while ((reg_group = reg_set[g_ind++]))
7144                 count += ixgbe_regs_group_count(reg_group);
7145
7146         return count;
7147 }
7148
7149 static int
7150 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7151 {
7152         int count = 0;
7153         int g_ind = 0;
7154         const struct reg_info *reg_group;
7155
7156         while ((reg_group = ixgbevf_regs[g_ind++]))
7157                 count += ixgbe_regs_group_count(reg_group);
7158
7159         return count;
7160 }
7161
7162 static int
7163 ixgbe_get_regs(struct rte_eth_dev *dev,
7164               struct rte_dev_reg_info *regs)
7165 {
7166         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7167         uint32_t *data = regs->data;
7168         int g_ind = 0;
7169         int count = 0;
7170         const struct reg_info *reg_group;
7171         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7172                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7173
7174         if (data == NULL) {
7175                 regs->length = ixgbe_get_reg_length(dev);
7176                 regs->width = sizeof(uint32_t);
7177                 return 0;
7178         }
7179
7180         /* Support only full register dump */
7181         if ((regs->length == 0) ||
7182             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7183                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7184                         hw->device_id;
7185                 while ((reg_group = reg_set[g_ind++]))
7186                         count += ixgbe_read_regs_group(dev, &data[count],
7187                                 reg_group);
7188                 return 0;
7189         }
7190
7191         return -ENOTSUP;
7192 }
7193
7194 static int
7195 ixgbevf_get_regs(struct rte_eth_dev *dev,
7196                 struct rte_dev_reg_info *regs)
7197 {
7198         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7199         uint32_t *data = regs->data;
7200         int g_ind = 0;
7201         int count = 0;
7202         const struct reg_info *reg_group;
7203
7204         if (data == NULL) {
7205                 regs->length = ixgbevf_get_reg_length(dev);
7206                 regs->width = sizeof(uint32_t);
7207                 return 0;
7208         }
7209
7210         /* Support only full register dump */
7211         if ((regs->length == 0) ||
7212             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7213                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7214                         hw->device_id;
7215                 while ((reg_group = ixgbevf_regs[g_ind++]))
7216                         count += ixgbe_read_regs_group(dev, &data[count],
7217                                                       reg_group);
7218                 return 0;
7219         }
7220
7221         return -ENOTSUP;
7222 }
7223
7224 static int
7225 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7226 {
7227         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7228
7229         /* Return unit is byte count */
7230         return hw->eeprom.word_size * 2;
7231 }
7232
7233 static int
7234 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7235                 struct rte_dev_eeprom_info *in_eeprom)
7236 {
7237         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7238         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7239         uint16_t *data = in_eeprom->data;
7240         int first, length;
7241
7242         first = in_eeprom->offset >> 1;
7243         length = in_eeprom->length >> 1;
7244         if ((first > hw->eeprom.word_size) ||
7245             ((first + length) > hw->eeprom.word_size))
7246                 return -EINVAL;
7247
7248         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7249
7250         return eeprom->ops.read_buffer(hw, first, length, data);
7251 }
7252
7253 static int
7254 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7255                 struct rte_dev_eeprom_info *in_eeprom)
7256 {
7257         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7258         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7259         uint16_t *data = in_eeprom->data;
7260         int first, length;
7261
7262         first = in_eeprom->offset >> 1;
7263         length = in_eeprom->length >> 1;
7264         if ((first > hw->eeprom.word_size) ||
7265             ((first + length) > hw->eeprom.word_size))
7266                 return -EINVAL;
7267
7268         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7269
7270         return eeprom->ops.write_buffer(hw,  first, length, data);
7271 }
7272
7273 static int
7274 ixgbe_get_module_info(struct rte_eth_dev *dev,
7275                       struct rte_eth_dev_module_info *modinfo)
7276 {
7277         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7278         uint32_t status;
7279         uint8_t sff8472_rev, addr_mode;
7280         bool page_swap = false;
7281
7282         /* Check whether we support SFF-8472 or not */
7283         status = hw->phy.ops.read_i2c_eeprom(hw,
7284                                              IXGBE_SFF_SFF_8472_COMP,
7285                                              &sff8472_rev);
7286         if (status != 0)
7287                 return -EIO;
7288
7289         /* addressing mode is not supported */
7290         status = hw->phy.ops.read_i2c_eeprom(hw,
7291                                              IXGBE_SFF_SFF_8472_SWAP,
7292                                              &addr_mode);
7293         if (status != 0)
7294                 return -EIO;
7295
7296         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7297                 PMD_DRV_LOG(ERR,
7298                             "Address change required to access page 0xA2, "
7299                             "but not supported. Please report the module "
7300                             "type to the driver maintainers.");
7301                 page_swap = true;
7302         }
7303
7304         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7305                 /* We have a SFP, but it does not support SFF-8472 */
7306                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7307                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7308         } else {
7309                 /* We have a SFP which supports a revision of SFF-8472. */
7310                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7311                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7312         }
7313
7314         return 0;
7315 }
7316
7317 static int
7318 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7319                         struct rte_dev_eeprom_info *info)
7320 {
7321         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7322         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7323         uint8_t databyte = 0xFF;
7324         uint8_t *data = info->data;
7325         uint32_t i = 0;
7326
7327         for (i = info->offset; i < info->offset + info->length; i++) {
7328                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7329                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7330                 else
7331                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7332
7333                 if (status != 0)
7334                         return -EIO;
7335
7336                 data[i - info->offset] = databyte;
7337         }
7338
7339         return 0;
7340 }
7341
7342 uint16_t
7343 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7344         switch (mac_type) {
7345         case ixgbe_mac_X550:
7346         case ixgbe_mac_X550EM_x:
7347         case ixgbe_mac_X550EM_a:
7348                 return ETH_RSS_RETA_SIZE_512;
7349         case ixgbe_mac_X550_vf:
7350         case ixgbe_mac_X550EM_x_vf:
7351         case ixgbe_mac_X550EM_a_vf:
7352                 return ETH_RSS_RETA_SIZE_64;
7353         case ixgbe_mac_X540_vf:
7354         case ixgbe_mac_82599_vf:
7355                 return 0;
7356         default:
7357                 return ETH_RSS_RETA_SIZE_128;
7358         }
7359 }
7360
7361 uint32_t
7362 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7363         switch (mac_type) {
7364         case ixgbe_mac_X550:
7365         case ixgbe_mac_X550EM_x:
7366         case ixgbe_mac_X550EM_a:
7367                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7368                         return IXGBE_RETA(reta_idx >> 2);
7369                 else
7370                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7371         case ixgbe_mac_X550_vf:
7372         case ixgbe_mac_X550EM_x_vf:
7373         case ixgbe_mac_X550EM_a_vf:
7374                 return IXGBE_VFRETA(reta_idx >> 2);
7375         default:
7376                 return IXGBE_RETA(reta_idx >> 2);
7377         }
7378 }
7379
7380 uint32_t
7381 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7382         switch (mac_type) {
7383         case ixgbe_mac_X550_vf:
7384         case ixgbe_mac_X550EM_x_vf:
7385         case ixgbe_mac_X550EM_a_vf:
7386                 return IXGBE_VFMRQC;
7387         default:
7388                 return IXGBE_MRQC;
7389         }
7390 }
7391
7392 uint32_t
7393 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7394         switch (mac_type) {
7395         case ixgbe_mac_X550_vf:
7396         case ixgbe_mac_X550EM_x_vf:
7397         case ixgbe_mac_X550EM_a_vf:
7398                 return IXGBE_VFRSSRK(i);
7399         default:
7400                 return IXGBE_RSSRK(i);
7401         }
7402 }
7403
7404 bool
7405 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7406         switch (mac_type) {
7407         case ixgbe_mac_82599_vf:
7408         case ixgbe_mac_X540_vf:
7409                 return 0;
7410         default:
7411                 return 1;
7412         }
7413 }
7414
7415 static int
7416 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7417                         struct rte_eth_dcb_info *dcb_info)
7418 {
7419         struct ixgbe_dcb_config *dcb_config =
7420                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7421         struct ixgbe_dcb_tc_config *tc;
7422         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7423         uint8_t nb_tcs;
7424         uint8_t i, j;
7425
7426         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7427                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7428         else
7429                 dcb_info->nb_tcs = 1;
7430
7431         tc_queue = &dcb_info->tc_queue;
7432         nb_tcs = dcb_info->nb_tcs;
7433
7434         if (dcb_config->vt_mode) { /* vt is enabled*/
7435                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7436                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7437                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7438                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7439                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7440                         for (j = 0; j < nb_tcs; j++) {
7441                                 tc_queue->tc_rxq[0][j].base = j;
7442                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7443                                 tc_queue->tc_txq[0][j].base = j;
7444                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7445                         }
7446                 } else {
7447                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7448                                 for (j = 0; j < nb_tcs; j++) {
7449                                         tc_queue->tc_rxq[i][j].base =
7450                                                 i * nb_tcs + j;
7451                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7452                                         tc_queue->tc_txq[i][j].base =
7453                                                 i * nb_tcs + j;
7454                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7455                                 }
7456                         }
7457                 }
7458         } else { /* vt is disabled*/
7459                 struct rte_eth_dcb_rx_conf *rx_conf =
7460                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7461                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7462                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7463                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7464                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7465                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7466                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7467                         }
7468                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7469                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7470                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7471                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7472                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7473                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7474                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7475                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7476                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7477                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7478                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7479                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7480                         }
7481                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7482                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7483                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7484                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7485                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7486                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7487                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7488                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7489                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7490                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7491                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7492                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7493                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7494                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7495                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7496                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7497                 }
7498         }
7499         for (i = 0; i < dcb_info->nb_tcs; i++) {
7500                 tc = &dcb_config->tc_config[i];
7501                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7502         }
7503         return 0;
7504 }
7505
7506 /* Update e-tag ether type */
7507 static int
7508 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7509                             uint16_t ether_type)
7510 {
7511         uint32_t etag_etype;
7512
7513         if (hw->mac.type != ixgbe_mac_X550 &&
7514             hw->mac.type != ixgbe_mac_X550EM_x &&
7515             hw->mac.type != ixgbe_mac_X550EM_a) {
7516                 return -ENOTSUP;
7517         }
7518
7519         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7520         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7521         etag_etype |= ether_type;
7522         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7523         IXGBE_WRITE_FLUSH(hw);
7524
7525         return 0;
7526 }
7527
7528 /* Enable e-tag tunnel */
7529 static int
7530 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7531 {
7532         uint32_t etag_etype;
7533
7534         if (hw->mac.type != ixgbe_mac_X550 &&
7535             hw->mac.type != ixgbe_mac_X550EM_x &&
7536             hw->mac.type != ixgbe_mac_X550EM_a) {
7537                 return -ENOTSUP;
7538         }
7539
7540         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7541         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7542         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7543         IXGBE_WRITE_FLUSH(hw);
7544
7545         return 0;
7546 }
7547
7548 static int
7549 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7550                        struct ixgbe_l2_tunnel_conf *l2_tunnel)
7551 {
7552         int ret = 0;
7553         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7554         uint32_t i, rar_entries;
7555         uint32_t rar_low, rar_high;
7556
7557         if (hw->mac.type != ixgbe_mac_X550 &&
7558             hw->mac.type != ixgbe_mac_X550EM_x &&
7559             hw->mac.type != ixgbe_mac_X550EM_a) {
7560                 return -ENOTSUP;
7561         }
7562
7563         rar_entries = ixgbe_get_num_rx_addrs(hw);
7564
7565         for (i = 1; i < rar_entries; i++) {
7566                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7567                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7568                 if ((rar_high & IXGBE_RAH_AV) &&
7569                     (rar_high & IXGBE_RAH_ADTYPE) &&
7570                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7571                      l2_tunnel->tunnel_id)) {
7572                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7573                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7574
7575                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7576
7577                         return ret;
7578                 }
7579         }
7580
7581         return ret;
7582 }
7583
7584 static int
7585 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7586                        struct ixgbe_l2_tunnel_conf *l2_tunnel)
7587 {
7588         int ret = 0;
7589         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7590         uint32_t i, rar_entries;
7591         uint32_t rar_low, rar_high;
7592
7593         if (hw->mac.type != ixgbe_mac_X550 &&
7594             hw->mac.type != ixgbe_mac_X550EM_x &&
7595             hw->mac.type != ixgbe_mac_X550EM_a) {
7596                 return -ENOTSUP;
7597         }
7598
7599         /* One entry for one tunnel. Try to remove potential existing entry. */
7600         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7601
7602         rar_entries = ixgbe_get_num_rx_addrs(hw);
7603
7604         for (i = 1; i < rar_entries; i++) {
7605                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7606                 if (rar_high & IXGBE_RAH_AV) {
7607                         continue;
7608                 } else {
7609                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7610                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7611                         rar_low = l2_tunnel->tunnel_id;
7612
7613                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7614                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7615
7616                         return ret;
7617                 }
7618         }
7619
7620         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7621                      " Please remove a rule before adding a new one.");
7622         return -EINVAL;
7623 }
7624
7625 static inline struct ixgbe_l2_tn_filter *
7626 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7627                           struct ixgbe_l2_tn_key *key)
7628 {
7629         int ret;
7630
7631         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7632         if (ret < 0)
7633                 return NULL;
7634
7635         return l2_tn_info->hash_map[ret];
7636 }
7637
7638 static inline int
7639 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7640                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7641 {
7642         int ret;
7643
7644         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7645                                &l2_tn_filter->key);
7646
7647         if (ret < 0) {
7648                 PMD_DRV_LOG(ERR,
7649                             "Failed to insert L2 tunnel filter"
7650                             " to hash table %d!",
7651                             ret);
7652                 return ret;
7653         }
7654
7655         l2_tn_info->hash_map[ret] = l2_tn_filter;
7656
7657         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7658
7659         return 0;
7660 }
7661
7662 static inline int
7663 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7664                           struct ixgbe_l2_tn_key *key)
7665 {
7666         int ret;
7667         struct ixgbe_l2_tn_filter *l2_tn_filter;
7668
7669         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7670
7671         if (ret < 0) {
7672                 PMD_DRV_LOG(ERR,
7673                             "No such L2 tunnel filter to delete %d!",
7674                             ret);
7675                 return ret;
7676         }
7677
7678         l2_tn_filter = l2_tn_info->hash_map[ret];
7679         l2_tn_info->hash_map[ret] = NULL;
7680
7681         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7682         rte_free(l2_tn_filter);
7683
7684         return 0;
7685 }
7686
7687 /* Add l2 tunnel filter */
7688 int
7689 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7690                                struct ixgbe_l2_tunnel_conf *l2_tunnel,
7691                                bool restore)
7692 {
7693         int ret;
7694         struct ixgbe_l2_tn_info *l2_tn_info =
7695                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7696         struct ixgbe_l2_tn_key key;
7697         struct ixgbe_l2_tn_filter *node;
7698
7699         if (!restore) {
7700                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7701                 key.tn_id = l2_tunnel->tunnel_id;
7702
7703                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7704
7705                 if (node) {
7706                         PMD_DRV_LOG(ERR,
7707                                     "The L2 tunnel filter already exists!");
7708                         return -EINVAL;
7709                 }
7710
7711                 node = rte_zmalloc("ixgbe_l2_tn",
7712                                    sizeof(struct ixgbe_l2_tn_filter),
7713                                    0);
7714                 if (!node)
7715                         return -ENOMEM;
7716
7717                 rte_memcpy(&node->key,
7718                                  &key,
7719                                  sizeof(struct ixgbe_l2_tn_key));
7720                 node->pool = l2_tunnel->pool;
7721                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7722                 if (ret < 0) {
7723                         rte_free(node);
7724                         return ret;
7725                 }
7726         }
7727
7728         switch (l2_tunnel->l2_tunnel_type) {
7729         case RTE_L2_TUNNEL_TYPE_E_TAG:
7730                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7731                 break;
7732         default:
7733                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7734                 ret = -EINVAL;
7735                 break;
7736         }
7737
7738         if ((!restore) && (ret < 0))
7739                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7740
7741         return ret;
7742 }
7743
7744 /* Delete l2 tunnel filter */
7745 int
7746 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7747                                struct ixgbe_l2_tunnel_conf *l2_tunnel)
7748 {
7749         int ret;
7750         struct ixgbe_l2_tn_info *l2_tn_info =
7751                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7752         struct ixgbe_l2_tn_key key;
7753
7754         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7755         key.tn_id = l2_tunnel->tunnel_id;
7756         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7757         if (ret < 0)
7758                 return ret;
7759
7760         switch (l2_tunnel->l2_tunnel_type) {
7761         case RTE_L2_TUNNEL_TYPE_E_TAG:
7762                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7763                 break;
7764         default:
7765                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7766                 ret = -EINVAL;
7767                 break;
7768         }
7769
7770         return ret;
7771 }
7772
7773 static int
7774 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7775 {
7776         int ret = 0;
7777         uint32_t ctrl;
7778         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7779
7780         if (hw->mac.type != ixgbe_mac_X550 &&
7781             hw->mac.type != ixgbe_mac_X550EM_x &&
7782             hw->mac.type != ixgbe_mac_X550EM_a) {
7783                 return -ENOTSUP;
7784         }
7785
7786         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7787         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7788         if (en)
7789                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7790         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7791
7792         return ret;
7793 }
7794
7795 static int
7796 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7797                         uint16_t port)
7798 {
7799         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7800         IXGBE_WRITE_FLUSH(hw);
7801
7802         return 0;
7803 }
7804
7805 /* There's only one register for VxLAN UDP port.
7806  * So, we cannot add several ports. Will update it.
7807  */
7808 static int
7809 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7810                      uint16_t port)
7811 {
7812         if (port == 0) {
7813                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7814                 return -EINVAL;
7815         }
7816
7817         return ixgbe_update_vxlan_port(hw, port);
7818 }
7819
7820 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7821  * UDP port, it must have a value.
7822  * So, will reset it to the original value 0.
7823  */
7824 static int
7825 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7826                      uint16_t port)
7827 {
7828         uint16_t cur_port;
7829
7830         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7831
7832         if (cur_port != port) {
7833                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7834                 return -EINVAL;
7835         }
7836
7837         return ixgbe_update_vxlan_port(hw, 0);
7838 }
7839
7840 /* Add UDP tunneling port */
7841 static int
7842 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7843                               struct rte_eth_udp_tunnel *udp_tunnel)
7844 {
7845         int ret = 0;
7846         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7847
7848         if (hw->mac.type != ixgbe_mac_X550 &&
7849             hw->mac.type != ixgbe_mac_X550EM_x &&
7850             hw->mac.type != ixgbe_mac_X550EM_a) {
7851                 return -ENOTSUP;
7852         }
7853
7854         if (udp_tunnel == NULL)
7855                 return -EINVAL;
7856
7857         switch (udp_tunnel->prot_type) {
7858         case RTE_TUNNEL_TYPE_VXLAN:
7859                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7860                 break;
7861
7862         case RTE_TUNNEL_TYPE_GENEVE:
7863         case RTE_TUNNEL_TYPE_TEREDO:
7864                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7865                 ret = -EINVAL;
7866                 break;
7867
7868         default:
7869                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7870                 ret = -EINVAL;
7871                 break;
7872         }
7873
7874         return ret;
7875 }
7876
7877 /* Remove UDP tunneling port */
7878 static int
7879 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7880                               struct rte_eth_udp_tunnel *udp_tunnel)
7881 {
7882         int ret = 0;
7883         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7884
7885         if (hw->mac.type != ixgbe_mac_X550 &&
7886             hw->mac.type != ixgbe_mac_X550EM_x &&
7887             hw->mac.type != ixgbe_mac_X550EM_a) {
7888                 return -ENOTSUP;
7889         }
7890
7891         if (udp_tunnel == NULL)
7892                 return -EINVAL;
7893
7894         switch (udp_tunnel->prot_type) {
7895         case RTE_TUNNEL_TYPE_VXLAN:
7896                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7897                 break;
7898         case RTE_TUNNEL_TYPE_GENEVE:
7899         case RTE_TUNNEL_TYPE_TEREDO:
7900                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7901                 ret = -EINVAL;
7902                 break;
7903         default:
7904                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7905                 ret = -EINVAL;
7906                 break;
7907         }
7908
7909         return ret;
7910 }
7911
7912 static int
7913 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
7914 {
7915         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7916         int ret;
7917
7918         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
7919         case IXGBE_SUCCESS:
7920                 ret = 0;
7921                 break;
7922         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7923                 ret = -ENOTSUP;
7924                 break;
7925         default:
7926                 ret = -EAGAIN;
7927                 break;
7928         }
7929
7930         return ret;
7931 }
7932
7933 static int
7934 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
7935 {
7936         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7937         int ret;
7938
7939         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
7940         case IXGBE_SUCCESS:
7941                 ret = 0;
7942                 break;
7943         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7944                 ret = -ENOTSUP;
7945                 break;
7946         default:
7947                 ret = -EAGAIN;
7948                 break;
7949         }
7950
7951         return ret;
7952 }
7953
7954 static int
7955 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7956 {
7957         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7958         int ret;
7959         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
7960
7961         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
7962         case IXGBE_SUCCESS:
7963                 ret = 0;
7964                 break;
7965         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7966                 ret = -ENOTSUP;
7967                 break;
7968         default:
7969                 ret = -EAGAIN;
7970                 break;
7971         }
7972
7973         return ret;
7974 }
7975
7976 static int
7977 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7978 {
7979         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7980         int ret;
7981
7982         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
7983         case IXGBE_SUCCESS:
7984                 ret = 0;
7985                 break;
7986         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7987                 ret = -ENOTSUP;
7988                 break;
7989         default:
7990                 ret = -EAGAIN;
7991                 break;
7992         }
7993
7994         return ret;
7995 }
7996
7997 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7998 {
7999         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8000         u32 in_msg = 0;
8001
8002         /* peek the message first */
8003         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8004
8005         /* PF reset VF event */
8006         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8007                 /* dummy mbx read to ack pf */
8008                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8009                         return;
8010                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8011                                              NULL);
8012         }
8013 }
8014
8015 static int
8016 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8017 {
8018         uint32_t eicr;
8019         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8020         struct ixgbe_interrupt *intr =
8021                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8022         ixgbevf_intr_disable(dev);
8023
8024         /* read-on-clear nic registers here */
8025         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8026         intr->flags = 0;
8027
8028         /* only one misc vector supported - mailbox */
8029         eicr &= IXGBE_VTEICR_MASK;
8030         if (eicr == IXGBE_MISC_VEC_ID)
8031                 intr->flags |= IXGBE_FLAG_MAILBOX;
8032
8033         return 0;
8034 }
8035
8036 static int
8037 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8038 {
8039         struct ixgbe_interrupt *intr =
8040                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8041
8042         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8043                 ixgbevf_mbx_process(dev);
8044                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8045         }
8046
8047         ixgbevf_intr_enable(dev);
8048
8049         return 0;
8050 }
8051
8052 static void
8053 ixgbevf_dev_interrupt_handler(void *param)
8054 {
8055         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8056
8057         ixgbevf_dev_interrupt_get_status(dev);
8058         ixgbevf_dev_interrupt_action(dev);
8059 }
8060
8061 /**
8062  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8063  *  @hw: pointer to hardware structure
8064  *
8065  *  Stops the transmit data path and waits for the HW to internally empty
8066  *  the Tx security block
8067  **/
8068 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8069 {
8070 #define IXGBE_MAX_SECTX_POLL 40
8071
8072         int i;
8073         int sectxreg;
8074
8075         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8076         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8077         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8078         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8079                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8080                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8081                         break;
8082                 /* Use interrupt-safe sleep just in case */
8083                 usec_delay(1000);
8084         }
8085
8086         /* For informational purposes only */
8087         if (i >= IXGBE_MAX_SECTX_POLL)
8088                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8089                          "path fully disabled.  Continuing with init.");
8090
8091         return IXGBE_SUCCESS;
8092 }
8093
8094 /**
8095  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8096  *  @hw: pointer to hardware structure
8097  *
8098  *  Enables the transmit data path.
8099  **/
8100 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8101 {
8102         uint32_t sectxreg;
8103
8104         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8105         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8106         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8107         IXGBE_WRITE_FLUSH(hw);
8108
8109         return IXGBE_SUCCESS;
8110 }
8111
8112 /* restore n-tuple filter */
8113 static inline void
8114 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8115 {
8116         struct ixgbe_filter_info *filter_info =
8117                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8118         struct ixgbe_5tuple_filter *node;
8119
8120         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8121                 ixgbe_inject_5tuple_filter(dev, node);
8122         }
8123 }
8124
8125 /* restore ethernet type filter */
8126 static inline void
8127 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8128 {
8129         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8130         struct ixgbe_filter_info *filter_info =
8131                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8132         int i;
8133
8134         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8135                 if (filter_info->ethertype_mask & (1 << i)) {
8136                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8137                                         filter_info->ethertype_filters[i].etqf);
8138                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8139                                         filter_info->ethertype_filters[i].etqs);
8140                         IXGBE_WRITE_FLUSH(hw);
8141                 }
8142         }
8143 }
8144
8145 /* restore SYN filter */
8146 static inline void
8147 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8148 {
8149         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8150         struct ixgbe_filter_info *filter_info =
8151                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8152         uint32_t synqf;
8153
8154         synqf = filter_info->syn_info;
8155
8156         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8157                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8158                 IXGBE_WRITE_FLUSH(hw);
8159         }
8160 }
8161
8162 /* restore L2 tunnel filter */
8163 static inline void
8164 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8165 {
8166         struct ixgbe_l2_tn_info *l2_tn_info =
8167                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8168         struct ixgbe_l2_tn_filter *node;
8169         struct ixgbe_l2_tunnel_conf l2_tn_conf;
8170
8171         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8172                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8173                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8174                 l2_tn_conf.pool           = node->pool;
8175                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8176         }
8177 }
8178
8179 /* restore rss filter */
8180 static inline void
8181 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8182 {
8183         struct ixgbe_filter_info *filter_info =
8184                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8185
8186         if (filter_info->rss_info.conf.queue_num)
8187                 ixgbe_config_rss_filter(dev,
8188                         &filter_info->rss_info, TRUE);
8189 }
8190
8191 static int
8192 ixgbe_filter_restore(struct rte_eth_dev *dev)
8193 {
8194         ixgbe_ntuple_filter_restore(dev);
8195         ixgbe_ethertype_filter_restore(dev);
8196         ixgbe_syn_filter_restore(dev);
8197         ixgbe_fdir_filter_restore(dev);
8198         ixgbe_l2_tn_filter_restore(dev);
8199         ixgbe_rss_filter_restore(dev);
8200
8201         return 0;
8202 }
8203
8204 static void
8205 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8206 {
8207         struct ixgbe_l2_tn_info *l2_tn_info =
8208                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8209         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8210
8211         if (l2_tn_info->e_tag_en)
8212                 (void)ixgbe_e_tag_enable(hw);
8213
8214         if (l2_tn_info->e_tag_fwd_en)
8215                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8216
8217         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8218 }
8219
8220 /* remove all the n-tuple filters */
8221 void
8222 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8223 {
8224         struct ixgbe_filter_info *filter_info =
8225                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8226         struct ixgbe_5tuple_filter *p_5tuple;
8227
8228         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8229                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8230 }
8231
8232 /* remove all the ether type filters */
8233 void
8234 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8235 {
8236         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8237         struct ixgbe_filter_info *filter_info =
8238                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8239         int i;
8240
8241         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8242                 if (filter_info->ethertype_mask & (1 << i) &&
8243                     !filter_info->ethertype_filters[i].conf) {
8244                         (void)ixgbe_ethertype_filter_remove(filter_info,
8245                                                             (uint8_t)i);
8246                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8247                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8248                         IXGBE_WRITE_FLUSH(hw);
8249                 }
8250         }
8251 }
8252
8253 /* remove the SYN filter */
8254 void
8255 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8256 {
8257         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8258         struct ixgbe_filter_info *filter_info =
8259                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8260
8261         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8262                 filter_info->syn_info = 0;
8263
8264                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8265                 IXGBE_WRITE_FLUSH(hw);
8266         }
8267 }
8268
8269 /* remove all the L2 tunnel filters */
8270 int
8271 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8272 {
8273         struct ixgbe_l2_tn_info *l2_tn_info =
8274                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8275         struct ixgbe_l2_tn_filter *l2_tn_filter;
8276         struct ixgbe_l2_tunnel_conf l2_tn_conf;
8277         int ret = 0;
8278
8279         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8280                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8281                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8282                 l2_tn_conf.pool           = l2_tn_filter->pool;
8283                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8284                 if (ret < 0)
8285                         return ret;
8286         }
8287
8288         return 0;
8289 }
8290
8291 void
8292 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8293                                 struct ixgbe_macsec_setting *macsec_setting)
8294 {
8295         struct ixgbe_macsec_setting *macsec =
8296                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8297
8298         macsec->offload_en = macsec_setting->offload_en;
8299         macsec->encrypt_en = macsec_setting->encrypt_en;
8300         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8301 }
8302
8303 void
8304 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8305 {
8306         struct ixgbe_macsec_setting *macsec =
8307                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8308
8309         macsec->offload_en = 0;
8310         macsec->encrypt_en = 0;
8311         macsec->replayprotect_en = 0;
8312 }
8313
8314 void
8315 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8316                                 struct ixgbe_macsec_setting *macsec_setting)
8317 {
8318         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8319         uint32_t ctrl;
8320         uint8_t en = macsec_setting->encrypt_en;
8321         uint8_t rp = macsec_setting->replayprotect_en;
8322
8323         /**
8324          * Workaround:
8325          * As no ixgbe_disable_sec_rx_path equivalent is
8326          * implemented for tx in the base code, and we are
8327          * not allowed to modify the base code in DPDK, so
8328          * just call the hand-written one directly for now.
8329          * The hardware support has been checked by
8330          * ixgbe_disable_sec_rx_path().
8331          */
8332         ixgbe_disable_sec_tx_path_generic(hw);
8333
8334         /* Enable Ethernet CRC (required by MACsec offload) */
8335         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8336         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8337         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8338
8339         /* Enable the TX and RX crypto engines */
8340         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8341         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8342         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8343
8344         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8345         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8346         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8347
8348         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8349         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8350         ctrl |= 0x3;
8351         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8352
8353         /* Enable SA lookup */
8354         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8355         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8356         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8357                      IXGBE_LSECTXCTRL_AUTH;
8358         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8359         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8360         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8361         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8362
8363         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8364         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8365         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8366         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8367         if (rp)
8368                 ctrl |= IXGBE_LSECRXCTRL_RP;
8369         else
8370                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8371         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8372
8373         /* Start the data paths */
8374         ixgbe_enable_sec_rx_path(hw);
8375         /**
8376          * Workaround:
8377          * As no ixgbe_enable_sec_rx_path equivalent is
8378          * implemented for tx in the base code, and we are
8379          * not allowed to modify the base code in DPDK, so
8380          * just call the hand-written one directly for now.
8381          */
8382         ixgbe_enable_sec_tx_path_generic(hw);
8383 }
8384
8385 void
8386 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
8387 {
8388         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8389         uint32_t ctrl;
8390
8391         /**
8392          * Workaround:
8393          * As no ixgbe_disable_sec_rx_path equivalent is
8394          * implemented for tx in the base code, and we are
8395          * not allowed to modify the base code in DPDK, so
8396          * just call the hand-written one directly for now.
8397          * The hardware support has been checked by
8398          * ixgbe_disable_sec_rx_path().
8399          */
8400         ixgbe_disable_sec_tx_path_generic(hw);
8401
8402         /* Disable the TX and RX crypto engines */
8403         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8404         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8405         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8406
8407         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8408         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8409         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8410
8411         /* Disable SA lookup */
8412         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8413         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8414         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8415         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8416
8417         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8418         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8419         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8420         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8421
8422         /* Start the data paths */
8423         ixgbe_enable_sec_rx_path(hw);
8424         /**
8425          * Workaround:
8426          * As no ixgbe_enable_sec_rx_path equivalent is
8427          * implemented for tx in the base code, and we are
8428          * not allowed to modify the base code in DPDK, so
8429          * just call the hand-written one directly for now.
8430          */
8431         ixgbe_enable_sec_tx_path_generic(hw);
8432 }
8433
8434 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8435 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8436 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8437 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8438 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8439 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8440 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
8441                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
8442
8443 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_init, init, NOTICE);
8444 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_driver, driver, NOTICE);
8445
8446 #ifdef RTE_ETHDEV_DEBUG_RX
8447 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_rx, rx, DEBUG);
8448 #endif
8449 #ifdef RTE_ETHDEV_DEBUG_TX
8450 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_tx, tx, DEBUG);
8451 #endif