1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
13 #include <netinet/in.h>
14 #include <rte_byteorder.h>
15 #include <rte_common.h>
16 #include <rte_cycles.h>
18 #include <rte_interrupts.h>
20 #include <rte_debug.h>
22 #include <rte_bus_pci.h>
23 #include <rte_branch_prediction.h>
24 #include <rte_memory.h>
26 #include <rte_alarm.h>
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_ethdev_pci.h>
30 #include <rte_malloc.h>
31 #include <rte_random.h>
33 #include <rte_hash_crc.h>
34 #ifdef RTE_LIBRTE_SECURITY
35 #include <rte_security_driver.h>
38 #include "ixgbe_logs.h"
39 #include "base/ixgbe_api.h"
40 #include "base/ixgbe_vf.h"
41 #include "base/ixgbe_common.h"
42 #include "ixgbe_ethdev.h"
43 #include "ixgbe_bypass.h"
44 #include "ixgbe_rxtx.h"
45 #include "base/ixgbe_type.h"
46 #include "base/ixgbe_phy.h"
47 #include "ixgbe_regs.h"
50 * High threshold controlling when to start sending XOFF frames. Must be at
51 * least 8 bytes less than receive packet buffer size. This value is in units
54 #define IXGBE_FC_HI 0x80
57 * Low threshold controlling when to start sending XON frames. This value is
58 * in units of 1024 bytes.
60 #define IXGBE_FC_LO 0x40
62 /* Default minimum inter-interrupt interval for EITR configuration */
63 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
65 /* Timer value included in XOFF frames. */
66 #define IXGBE_FC_PAUSE 0x680
68 /*Default value of Max Rx Queue*/
69 #define IXGBE_MAX_RX_QUEUE_NUM 128
71 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
72 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
73 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
75 #define IXGBE_MMW_SIZE_DEFAULT 0x4
76 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
77 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
80 * Default values for RX/TX configuration
82 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
83 #define IXGBE_DEFAULT_RX_PTHRESH 8
84 #define IXGBE_DEFAULT_RX_HTHRESH 8
85 #define IXGBE_DEFAULT_RX_WTHRESH 0
87 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
88 #define IXGBE_DEFAULT_TX_PTHRESH 32
89 #define IXGBE_DEFAULT_TX_HTHRESH 0
90 #define IXGBE_DEFAULT_TX_WTHRESH 0
91 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
93 /* Bit shift and mask */
94 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
95 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
96 #define IXGBE_8_BIT_WIDTH CHAR_BIT
97 #define IXGBE_8_BIT_MASK UINT8_MAX
99 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
101 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
103 #define IXGBE_HKEY_MAX_INDEX 10
105 /* Additional timesync values. */
106 #define NSEC_PER_SEC 1000000000L
107 #define IXGBE_INCVAL_10GB 0x66666666
108 #define IXGBE_INCVAL_1GB 0x40000000
109 #define IXGBE_INCVAL_100 0x50000000
110 #define IXGBE_INCVAL_SHIFT_10GB 28
111 #define IXGBE_INCVAL_SHIFT_1GB 24
112 #define IXGBE_INCVAL_SHIFT_100 21
113 #define IXGBE_INCVAL_SHIFT_82599 7
114 #define IXGBE_INCPER_SHIFT_82599 24
116 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
118 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
119 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
120 #define DEFAULT_ETAG_ETYPE 0x893f
121 #define IXGBE_ETAG_ETYPE 0x00005084
122 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
123 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
124 #define IXGBE_RAH_ADTYPE 0x40000000
125 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
126 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
127 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
128 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
129 #define IXGBE_QDE_STRIP_TAG 0x00000004
130 #define IXGBE_VTEICR_MASK 0x07
132 #define IXGBE_EXVET_VET_EXT_SHIFT 16
133 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
135 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
136 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
137 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
138 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
139 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
140 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
141 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
142 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
143 static int ixgbe_dev_start(struct rte_eth_dev *dev);
144 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
145 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
146 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
147 static void ixgbe_dev_close(struct rte_eth_dev *dev);
148 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
149 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
150 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
151 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
152 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
153 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
154 int wait_to_complete);
155 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
156 struct rte_eth_stats *stats);
157 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
158 struct rte_eth_xstat *xstats, unsigned n);
159 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
160 struct rte_eth_xstat *xstats, unsigned n);
162 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
163 uint64_t *values, unsigned int n);
164 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
165 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
166 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
167 struct rte_eth_xstat_name *xstats_names,
169 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
170 struct rte_eth_xstat_name *xstats_names, unsigned limit);
171 static int ixgbe_dev_xstats_get_names_by_id(
172 struct rte_eth_dev *dev,
173 struct rte_eth_xstat_name *xstats_names,
176 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
180 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
182 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
183 struct rte_eth_dev_info *dev_info);
184 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
185 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
186 struct rte_eth_dev_info *dev_info);
187 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
189 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
190 uint16_t vlan_id, int on);
191 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
192 enum rte_vlan_type vlan_type,
194 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
195 uint16_t queue, bool on);
196 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
198 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
199 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
200 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
201 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
202 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
204 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
205 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
206 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
207 struct rte_eth_fc_conf *fc_conf);
208 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
209 struct rte_eth_fc_conf *fc_conf);
210 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
211 struct rte_eth_pfc_conf *pfc_conf);
212 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
213 struct rte_eth_rss_reta_entry64 *reta_conf,
215 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
216 struct rte_eth_rss_reta_entry64 *reta_conf,
218 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
219 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
220 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
221 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
222 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
223 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
224 struct rte_intr_handle *handle);
225 static void ixgbe_dev_interrupt_handler(void *param);
226 static void ixgbe_dev_interrupt_delayed_handler(void *param);
227 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
228 uint32_t index, uint32_t pool);
229 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
230 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
231 struct ether_addr *mac_addr);
232 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
233 static bool is_device_supported(struct rte_eth_dev *dev,
234 struct rte_pci_driver *drv);
236 /* For Virtual Function support */
237 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
238 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
239 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
240 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
241 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
242 int wait_to_complete);
243 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
244 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
245 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
246 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
247 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
248 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
249 struct rte_eth_stats *stats);
250 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
251 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
252 uint16_t vlan_id, int on);
253 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
254 uint16_t queue, int on);
255 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
256 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
257 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
259 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
261 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
262 uint8_t queue, uint8_t msix_vector);
263 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
264 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
265 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
267 /* For Eth VMDQ APIs support */
268 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
269 ether_addr * mac_addr, uint8_t on);
270 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
271 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
272 struct rte_eth_mirror_conf *mirror_conf,
273 uint8_t rule_id, uint8_t on);
274 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
276 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
278 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
280 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
281 uint8_t queue, uint8_t msix_vector);
282 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
284 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
285 struct ether_addr *mac_addr,
286 uint32_t index, uint32_t pool);
287 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
288 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
289 struct ether_addr *mac_addr);
290 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
291 struct rte_eth_syn_filter *filter);
292 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
293 enum rte_filter_op filter_op,
295 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
296 struct ixgbe_5tuple_filter *filter);
297 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
298 struct ixgbe_5tuple_filter *filter);
299 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
300 enum rte_filter_op filter_op,
302 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
303 struct rte_eth_ntuple_filter *filter);
304 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
305 enum rte_filter_op filter_op,
307 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
308 struct rte_eth_ethertype_filter *filter);
309 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
310 enum rte_filter_type filter_type,
311 enum rte_filter_op filter_op,
313 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
315 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
316 struct ether_addr *mc_addr_set,
317 uint32_t nb_mc_addr);
318 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
319 struct rte_eth_dcb_info *dcb_info);
321 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
322 static int ixgbe_get_regs(struct rte_eth_dev *dev,
323 struct rte_dev_reg_info *regs);
324 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
325 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
326 struct rte_dev_eeprom_info *eeprom);
327 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
328 struct rte_dev_eeprom_info *eeprom);
330 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
331 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
332 struct rte_dev_reg_info *regs);
334 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
335 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
336 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
337 struct timespec *timestamp,
339 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
340 struct timespec *timestamp);
341 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
342 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
343 struct timespec *timestamp);
344 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
345 const struct timespec *timestamp);
346 static void ixgbevf_dev_interrupt_handler(void *param);
348 static int ixgbe_dev_l2_tunnel_eth_type_conf
349 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
350 static int ixgbe_dev_l2_tunnel_offload_set
351 (struct rte_eth_dev *dev,
352 struct rte_eth_l2_tunnel_conf *l2_tunnel,
355 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
356 enum rte_filter_op filter_op,
359 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
360 struct rte_eth_udp_tunnel *udp_tunnel);
361 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
362 struct rte_eth_udp_tunnel *udp_tunnel);
363 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
364 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
367 * Define VF Stats MACRO for Non "cleared on read" register
369 #define UPDATE_VF_STAT(reg, last, cur) \
371 uint32_t latest = IXGBE_READ_REG(hw, reg); \
372 cur += (latest - last) & UINT_MAX; \
376 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
378 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
379 u64 new_msb = IXGBE_READ_REG(hw, msb); \
380 u64 latest = ((new_msb << 32) | new_lsb); \
381 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
385 #define IXGBE_SET_HWSTRIP(h, q) do {\
386 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
387 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
388 (h)->bitmap[idx] |= 1 << bit;\
391 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
392 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
393 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
394 (h)->bitmap[idx] &= ~(1 << bit);\
397 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
398 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
399 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
400 (r) = (h)->bitmap[idx] >> bit & 1;\
403 int ixgbe_logtype_init;
404 int ixgbe_logtype_driver;
407 * The set of PCI devices this driver supports
409 static const struct rte_pci_id pci_id_ixgbe_map[] = {
410 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
411 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
412 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
413 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
414 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
415 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
416 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
417 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
418 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
419 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
420 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
421 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
422 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
423 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
424 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
425 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
458 #ifdef RTE_LIBRTE_IXGBE_BYPASS
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
461 { .vendor_id = 0, /* sentinel */ },
465 * The set of PCI devices this driver supports (for 82599 VF)
467 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
478 { .vendor_id = 0, /* sentinel */ },
481 static const struct rte_eth_desc_lim rx_desc_lim = {
482 .nb_max = IXGBE_MAX_RING_DESC,
483 .nb_min = IXGBE_MIN_RING_DESC,
484 .nb_align = IXGBE_RXD_ALIGN,
487 static const struct rte_eth_desc_lim tx_desc_lim = {
488 .nb_max = IXGBE_MAX_RING_DESC,
489 .nb_min = IXGBE_MIN_RING_DESC,
490 .nb_align = IXGBE_TXD_ALIGN,
491 .nb_seg_max = IXGBE_TX_MAX_SEG,
492 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
495 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
496 .dev_configure = ixgbe_dev_configure,
497 .dev_start = ixgbe_dev_start,
498 .dev_stop = ixgbe_dev_stop,
499 .dev_set_link_up = ixgbe_dev_set_link_up,
500 .dev_set_link_down = ixgbe_dev_set_link_down,
501 .dev_close = ixgbe_dev_close,
502 .dev_reset = ixgbe_dev_reset,
503 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
504 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
505 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
506 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
507 .link_update = ixgbe_dev_link_update,
508 .stats_get = ixgbe_dev_stats_get,
509 .xstats_get = ixgbe_dev_xstats_get,
510 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
511 .stats_reset = ixgbe_dev_stats_reset,
512 .xstats_reset = ixgbe_dev_xstats_reset,
513 .xstats_get_names = ixgbe_dev_xstats_get_names,
514 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
515 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
516 .fw_version_get = ixgbe_fw_version_get,
517 .dev_infos_get = ixgbe_dev_info_get,
518 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
519 .mtu_set = ixgbe_dev_mtu_set,
520 .vlan_filter_set = ixgbe_vlan_filter_set,
521 .vlan_tpid_set = ixgbe_vlan_tpid_set,
522 .vlan_offload_set = ixgbe_vlan_offload_set,
523 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
524 .rx_queue_start = ixgbe_dev_rx_queue_start,
525 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
526 .tx_queue_start = ixgbe_dev_tx_queue_start,
527 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
528 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
529 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
530 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
531 .rx_queue_release = ixgbe_dev_rx_queue_release,
532 .rx_queue_count = ixgbe_dev_rx_queue_count,
533 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
534 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
535 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
536 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
537 .tx_queue_release = ixgbe_dev_tx_queue_release,
538 .dev_led_on = ixgbe_dev_led_on,
539 .dev_led_off = ixgbe_dev_led_off,
540 .flow_ctrl_get = ixgbe_flow_ctrl_get,
541 .flow_ctrl_set = ixgbe_flow_ctrl_set,
542 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
543 .mac_addr_add = ixgbe_add_rar,
544 .mac_addr_remove = ixgbe_remove_rar,
545 .mac_addr_set = ixgbe_set_default_mac_addr,
546 .uc_hash_table_set = ixgbe_uc_hash_table_set,
547 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
548 .mirror_rule_set = ixgbe_mirror_rule_set,
549 .mirror_rule_reset = ixgbe_mirror_rule_reset,
550 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
551 .reta_update = ixgbe_dev_rss_reta_update,
552 .reta_query = ixgbe_dev_rss_reta_query,
553 .rss_hash_update = ixgbe_dev_rss_hash_update,
554 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
555 .filter_ctrl = ixgbe_dev_filter_ctrl,
556 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
557 .rxq_info_get = ixgbe_rxq_info_get,
558 .txq_info_get = ixgbe_txq_info_get,
559 .timesync_enable = ixgbe_timesync_enable,
560 .timesync_disable = ixgbe_timesync_disable,
561 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
562 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
563 .get_reg = ixgbe_get_regs,
564 .get_eeprom_length = ixgbe_get_eeprom_length,
565 .get_eeprom = ixgbe_get_eeprom,
566 .set_eeprom = ixgbe_set_eeprom,
567 .get_dcb_info = ixgbe_dev_get_dcb_info,
568 .timesync_adjust_time = ixgbe_timesync_adjust_time,
569 .timesync_read_time = ixgbe_timesync_read_time,
570 .timesync_write_time = ixgbe_timesync_write_time,
571 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
572 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
573 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
574 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
575 .tm_ops_get = ixgbe_tm_ops_get,
579 * dev_ops for virtual function, bare necessities for basic vf
580 * operation have been implemented
582 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
583 .dev_configure = ixgbevf_dev_configure,
584 .dev_start = ixgbevf_dev_start,
585 .dev_stop = ixgbevf_dev_stop,
586 .link_update = ixgbevf_dev_link_update,
587 .stats_get = ixgbevf_dev_stats_get,
588 .xstats_get = ixgbevf_dev_xstats_get,
589 .stats_reset = ixgbevf_dev_stats_reset,
590 .xstats_reset = ixgbevf_dev_stats_reset,
591 .xstats_get_names = ixgbevf_dev_xstats_get_names,
592 .dev_close = ixgbevf_dev_close,
593 .dev_reset = ixgbevf_dev_reset,
594 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
595 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
596 .dev_infos_get = ixgbevf_dev_info_get,
597 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
598 .mtu_set = ixgbevf_dev_set_mtu,
599 .vlan_filter_set = ixgbevf_vlan_filter_set,
600 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
601 .vlan_offload_set = ixgbevf_vlan_offload_set,
602 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
603 .rx_queue_release = ixgbe_dev_rx_queue_release,
604 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
605 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
606 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
607 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
608 .tx_queue_release = ixgbe_dev_tx_queue_release,
609 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
610 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
611 .mac_addr_add = ixgbevf_add_mac_addr,
612 .mac_addr_remove = ixgbevf_remove_mac_addr,
613 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
614 .rxq_info_get = ixgbe_rxq_info_get,
615 .txq_info_get = ixgbe_txq_info_get,
616 .mac_addr_set = ixgbevf_set_default_mac_addr,
617 .get_reg = ixgbevf_get_regs,
618 .reta_update = ixgbe_dev_rss_reta_update,
619 .reta_query = ixgbe_dev_rss_reta_query,
620 .rss_hash_update = ixgbe_dev_rss_hash_update,
621 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
624 /* store statistics names and its offset in stats structure */
625 struct rte_ixgbe_xstats_name_off {
626 char name[RTE_ETH_XSTATS_NAME_SIZE];
630 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
631 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
632 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
633 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
634 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
635 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
636 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
637 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
638 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
639 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
640 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
641 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
642 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
643 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
644 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
645 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
647 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
649 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
650 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
651 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
652 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
653 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
654 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
655 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
656 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
657 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
658 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
659 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
660 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
661 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
662 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
663 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
664 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
665 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
667 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
669 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
670 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
671 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
672 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
674 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
676 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
678 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
680 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
682 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
684 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
687 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
688 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
689 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
691 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
692 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
693 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
694 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
695 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
697 {"rx_fcoe_no_direct_data_placement_ext_buff",
698 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
700 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
702 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
704 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
706 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
708 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
711 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
712 sizeof(rte_ixgbe_stats_strings[0]))
714 /* MACsec statistics */
715 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
716 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
718 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
719 out_pkts_encrypted)},
720 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
721 out_pkts_protected)},
722 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
723 out_octets_encrypted)},
724 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
725 out_octets_protected)},
726 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
728 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
730 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
732 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
733 in_pkts_unknownsci)},
734 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
735 in_octets_decrypted)},
736 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
737 in_octets_validated)},
738 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
740 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
742 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
744 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
746 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
748 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
750 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
752 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
753 in_pkts_notusingsa)},
756 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
757 sizeof(rte_ixgbe_macsec_strings[0]))
759 /* Per-queue statistics */
760 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
761 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
762 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
763 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
764 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
767 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
768 sizeof(rte_ixgbe_rxq_strings[0]))
769 #define IXGBE_NB_RXQ_PRIO_VALUES 8
771 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
772 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
773 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
774 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
778 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
779 sizeof(rte_ixgbe_txq_strings[0]))
780 #define IXGBE_NB_TXQ_PRIO_VALUES 8
782 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
783 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
786 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
787 sizeof(rte_ixgbevf_stats_strings[0]))
790 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
793 ixgbe_is_sfp(struct ixgbe_hw *hw)
795 switch (hw->phy.type) {
796 case ixgbe_phy_sfp_avago:
797 case ixgbe_phy_sfp_ftl:
798 case ixgbe_phy_sfp_intel:
799 case ixgbe_phy_sfp_unknown:
800 case ixgbe_phy_sfp_passive_tyco:
801 case ixgbe_phy_sfp_passive_unknown:
808 static inline int32_t
809 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
814 status = ixgbe_reset_hw(hw);
816 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
817 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
818 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
819 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
820 IXGBE_WRITE_FLUSH(hw);
822 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
823 status = IXGBE_SUCCESS;
828 ixgbe_enable_intr(struct rte_eth_dev *dev)
830 struct ixgbe_interrupt *intr =
831 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
832 struct ixgbe_hw *hw =
833 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
835 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
836 IXGBE_WRITE_FLUSH(hw);
840 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
843 ixgbe_disable_intr(struct ixgbe_hw *hw)
845 PMD_INIT_FUNC_TRACE();
847 if (hw->mac.type == ixgbe_mac_82598EB) {
848 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
850 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
851 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
852 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
854 IXGBE_WRITE_FLUSH(hw);
858 * This function resets queue statistics mapping registers.
859 * From Niantic datasheet, Initialization of Statistics section:
860 * "...if software requires the queue counters, the RQSMR and TQSM registers
861 * must be re-programmed following a device reset.
864 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
868 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
869 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
870 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
876 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
881 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
882 #define NB_QMAP_FIELDS_PER_QSM_REG 4
883 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
885 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
886 struct ixgbe_stat_mapping_registers *stat_mappings =
887 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
888 uint32_t qsmr_mask = 0;
889 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
893 if ((hw->mac.type != ixgbe_mac_82599EB) &&
894 (hw->mac.type != ixgbe_mac_X540) &&
895 (hw->mac.type != ixgbe_mac_X550) &&
896 (hw->mac.type != ixgbe_mac_X550EM_x) &&
897 (hw->mac.type != ixgbe_mac_X550EM_a))
900 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
901 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
904 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
905 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
906 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
909 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
911 /* Now clear any previous stat_idx set */
912 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
914 stat_mappings->tqsm[n] &= ~clearing_mask;
916 stat_mappings->rqsmr[n] &= ~clearing_mask;
918 q_map = (uint32_t)stat_idx;
919 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
920 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
922 stat_mappings->tqsm[n] |= qsmr_mask;
924 stat_mappings->rqsmr[n] |= qsmr_mask;
926 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
927 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
929 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
930 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
932 /* Now write the mapping in the appropriate register */
934 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
935 stat_mappings->rqsmr[n], n);
936 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
938 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
939 stat_mappings->tqsm[n], n);
940 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
946 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
948 struct ixgbe_stat_mapping_registers *stat_mappings =
949 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
950 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
953 /* write whatever was in stat mapping table to the NIC */
954 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
956 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
959 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
964 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
967 struct ixgbe_dcb_tc_config *tc;
968 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
970 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
971 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
972 for (i = 0; i < dcb_max_tc; i++) {
973 tc = &dcb_config->tc_config[i];
974 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
975 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
976 (uint8_t)(100/dcb_max_tc + (i & 1));
977 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
978 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
979 (uint8_t)(100/dcb_max_tc + (i & 1));
980 tc->pfc = ixgbe_dcb_pfc_disabled;
983 /* Initialize default user to priority mapping, UPx->TC0 */
984 tc = &dcb_config->tc_config[0];
985 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
986 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
987 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
988 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
989 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
991 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
992 dcb_config->pfc_mode_enable = false;
993 dcb_config->vt_mode = true;
994 dcb_config->round_robin_enable = false;
995 /* support all DCB capabilities in 82599 */
996 dcb_config->support.capabilities = 0xFF;
998 /*we only support 4 Tcs for X540, X550 */
999 if (hw->mac.type == ixgbe_mac_X540 ||
1000 hw->mac.type == ixgbe_mac_X550 ||
1001 hw->mac.type == ixgbe_mac_X550EM_x ||
1002 hw->mac.type == ixgbe_mac_X550EM_a) {
1003 dcb_config->num_tcs.pg_tcs = 4;
1004 dcb_config->num_tcs.pfc_tcs = 4;
1009 * Ensure that all locks are released before first NVM or PHY access
1012 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1017 * Phy lock should not fail in this early stage. If this is the case,
1018 * it is due to an improper exit of the application.
1019 * So force the release of the faulty lock. Release of common lock
1020 * is done automatically by swfw_sync function.
1022 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1023 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1024 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1026 ixgbe_release_swfw_semaphore(hw, mask);
1029 * These ones are more tricky since they are common to all ports; but
1030 * swfw_sync retries last long enough (1s) to be almost sure that if
1031 * lock can not be taken it is due to an improper lock of the
1034 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1035 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1036 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1038 ixgbe_release_swfw_semaphore(hw, mask);
1042 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1043 * It returns 0 on success.
1046 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1048 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1049 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1050 struct ixgbe_hw *hw =
1051 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1052 struct ixgbe_vfta *shadow_vfta =
1053 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1054 struct ixgbe_hwstrip *hwstrip =
1055 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1056 struct ixgbe_dcb_config *dcb_config =
1057 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1058 struct ixgbe_filter_info *filter_info =
1059 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1060 struct ixgbe_bw_conf *bw_conf =
1061 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1066 PMD_INIT_FUNC_TRACE();
1068 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1069 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1070 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1071 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1074 * For secondary processes, we don't initialise any further as primary
1075 * has already done this work. Only check we don't need a different
1076 * RX and TX function.
1078 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1079 struct ixgbe_tx_queue *txq;
1080 /* TX queue function in primary, set by last queue initialized
1081 * Tx queue may not initialized by primary process
1083 if (eth_dev->data->tx_queues) {
1084 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1085 ixgbe_set_tx_function(eth_dev, txq);
1087 /* Use default TX function if we get here */
1088 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1089 "Using default TX function.");
1092 ixgbe_set_rx_function(eth_dev);
1097 rte_eth_copy_pci_info(eth_dev, pci_dev);
1099 /* Vendor and Device ID need to be set before init of shared code */
1100 hw->device_id = pci_dev->id.device_id;
1101 hw->vendor_id = pci_dev->id.vendor_id;
1102 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1103 hw->allow_unsupported_sfp = 1;
1105 /* Initialize the shared code (base driver) */
1106 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1107 diag = ixgbe_bypass_init_shared_code(hw);
1109 diag = ixgbe_init_shared_code(hw);
1110 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1112 if (diag != IXGBE_SUCCESS) {
1113 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1117 /* pick up the PCI bus settings for reporting later */
1118 ixgbe_get_bus_info(hw);
1120 /* Unlock any pending hardware semaphore */
1121 ixgbe_swfw_lock_reset(hw);
1123 #ifdef RTE_LIBRTE_SECURITY
1124 /* Initialize security_ctx only for primary process*/
1125 if (ixgbe_ipsec_ctx_create(eth_dev))
1129 /* Initialize DCB configuration*/
1130 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1131 ixgbe_dcb_init(hw, dcb_config);
1132 /* Get Hardware Flow Control setting */
1133 hw->fc.requested_mode = ixgbe_fc_full;
1134 hw->fc.current_mode = ixgbe_fc_full;
1135 hw->fc.pause_time = IXGBE_FC_PAUSE;
1136 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1137 hw->fc.low_water[i] = IXGBE_FC_LO;
1138 hw->fc.high_water[i] = IXGBE_FC_HI;
1140 hw->fc.send_xon = 1;
1142 /* Make sure we have a good EEPROM before we read from it */
1143 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1144 if (diag != IXGBE_SUCCESS) {
1145 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1149 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1150 diag = ixgbe_bypass_init_hw(hw);
1152 diag = ixgbe_init_hw(hw);
1153 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1156 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1157 * is called too soon after the kernel driver unbinding/binding occurs.
1158 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1159 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1160 * also called. See ixgbe_identify_phy_82599(). The reason for the
1161 * failure is not known, and only occuts when virtualisation features
1162 * are disabled in the bios. A delay of 100ms was found to be enough by
1163 * trial-and-error, and is doubled to be safe.
1165 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1167 diag = ixgbe_init_hw(hw);
1170 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1171 diag = IXGBE_SUCCESS;
1173 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1174 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1175 "LOM. Please be aware there may be issues associated "
1176 "with your hardware.");
1177 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1178 "please contact your Intel or hardware representative "
1179 "who provided you with this hardware.");
1180 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1181 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1183 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1187 /* Reset the hw statistics */
1188 ixgbe_dev_stats_reset(eth_dev);
1190 /* disable interrupt */
1191 ixgbe_disable_intr(hw);
1193 /* reset mappings for queue statistics hw counters*/
1194 ixgbe_reset_qstat_mappings(hw);
1196 /* Allocate memory for storing MAC addresses */
1197 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1198 hw->mac.num_rar_entries, 0);
1199 if (eth_dev->data->mac_addrs == NULL) {
1201 "Failed to allocate %u bytes needed to store "
1203 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1206 /* Copy the permanent MAC address */
1207 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1208 ð_dev->data->mac_addrs[0]);
1210 /* Allocate memory for storing hash filter MAC addresses */
1211 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1212 IXGBE_VMDQ_NUM_UC_MAC, 0);
1213 if (eth_dev->data->hash_mac_addrs == NULL) {
1215 "Failed to allocate %d bytes needed to store MAC addresses",
1216 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1220 /* initialize the vfta */
1221 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1223 /* initialize the hw strip bitmap*/
1224 memset(hwstrip, 0, sizeof(*hwstrip));
1226 /* initialize PF if max_vfs not zero */
1227 ixgbe_pf_host_init(eth_dev);
1229 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1230 /* let hardware know driver is loaded */
1231 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1232 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1233 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1234 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1235 IXGBE_WRITE_FLUSH(hw);
1237 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1238 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1239 (int) hw->mac.type, (int) hw->phy.type,
1240 (int) hw->phy.sfp_type);
1242 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1243 (int) hw->mac.type, (int) hw->phy.type);
1245 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1246 eth_dev->data->port_id, pci_dev->id.vendor_id,
1247 pci_dev->id.device_id);
1249 rte_intr_callback_register(intr_handle,
1250 ixgbe_dev_interrupt_handler, eth_dev);
1252 /* enable uio/vfio intr/eventfd mapping */
1253 rte_intr_enable(intr_handle);
1255 /* enable support intr */
1256 ixgbe_enable_intr(eth_dev);
1258 /* initialize filter info */
1259 memset(filter_info, 0,
1260 sizeof(struct ixgbe_filter_info));
1262 /* initialize 5tuple filter list */
1263 TAILQ_INIT(&filter_info->fivetuple_list);
1265 /* initialize flow director filter list & hash */
1266 ixgbe_fdir_filter_init(eth_dev);
1268 /* initialize l2 tunnel filter list & hash */
1269 ixgbe_l2_tn_filter_init(eth_dev);
1271 /* initialize flow filter lists */
1272 ixgbe_filterlist_init();
1274 /* initialize bandwidth configuration info */
1275 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1277 /* initialize Traffic Manager configuration */
1278 ixgbe_tm_conf_init(eth_dev);
1284 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1286 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1287 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1288 struct ixgbe_hw *hw;
1292 PMD_INIT_FUNC_TRACE();
1294 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1297 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1299 if (hw->adapter_stopped == 0)
1300 ixgbe_dev_close(eth_dev);
1302 eth_dev->dev_ops = NULL;
1303 eth_dev->rx_pkt_burst = NULL;
1304 eth_dev->tx_pkt_burst = NULL;
1306 /* Unlock any pending hardware semaphore */
1307 ixgbe_swfw_lock_reset(hw);
1309 /* disable uio intr before callback unregister */
1310 rte_intr_disable(intr_handle);
1313 ret = rte_intr_callback_unregister(intr_handle,
1314 ixgbe_dev_interrupt_handler, eth_dev);
1317 } else if (ret != -EAGAIN) {
1319 "intr callback unregister failed: %d",
1324 } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1326 /* uninitialize PF if max_vfs not zero */
1327 ixgbe_pf_host_uninit(eth_dev);
1329 rte_free(eth_dev->data->mac_addrs);
1330 eth_dev->data->mac_addrs = NULL;
1332 rte_free(eth_dev->data->hash_mac_addrs);
1333 eth_dev->data->hash_mac_addrs = NULL;
1335 /* remove all the fdir filters & hash */
1336 ixgbe_fdir_filter_uninit(eth_dev);
1338 /* remove all the L2 tunnel filters & hash */
1339 ixgbe_l2_tn_filter_uninit(eth_dev);
1341 /* Remove all ntuple filters of the device */
1342 ixgbe_ntuple_filter_uninit(eth_dev);
1344 /* clear all the filters list */
1345 ixgbe_filterlist_flush();
1347 /* Remove all Traffic Manager configuration */
1348 ixgbe_tm_conf_uninit(eth_dev);
1350 #ifdef RTE_LIBRTE_SECURITY
1351 rte_free(eth_dev->security_ctx);
1357 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1359 struct ixgbe_filter_info *filter_info =
1360 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1361 struct ixgbe_5tuple_filter *p_5tuple;
1363 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1364 TAILQ_REMOVE(&filter_info->fivetuple_list,
1369 memset(filter_info->fivetuple_mask, 0,
1370 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1375 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1377 struct ixgbe_hw_fdir_info *fdir_info =
1378 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1379 struct ixgbe_fdir_filter *fdir_filter;
1381 if (fdir_info->hash_map)
1382 rte_free(fdir_info->hash_map);
1383 if (fdir_info->hash_handle)
1384 rte_hash_free(fdir_info->hash_handle);
1386 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1387 TAILQ_REMOVE(&fdir_info->fdir_list,
1390 rte_free(fdir_filter);
1396 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1398 struct ixgbe_l2_tn_info *l2_tn_info =
1399 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1400 struct ixgbe_l2_tn_filter *l2_tn_filter;
1402 if (l2_tn_info->hash_map)
1403 rte_free(l2_tn_info->hash_map);
1404 if (l2_tn_info->hash_handle)
1405 rte_hash_free(l2_tn_info->hash_handle);
1407 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1408 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1411 rte_free(l2_tn_filter);
1417 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1419 struct ixgbe_hw_fdir_info *fdir_info =
1420 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1421 char fdir_hash_name[RTE_HASH_NAMESIZE];
1422 struct rte_hash_parameters fdir_hash_params = {
1423 .name = fdir_hash_name,
1424 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1425 .key_len = sizeof(union ixgbe_atr_input),
1426 .hash_func = rte_hash_crc,
1427 .hash_func_init_val = 0,
1428 .socket_id = rte_socket_id(),
1431 TAILQ_INIT(&fdir_info->fdir_list);
1432 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1433 "fdir_%s", eth_dev->device->name);
1434 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1435 if (!fdir_info->hash_handle) {
1436 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1439 fdir_info->hash_map = rte_zmalloc("ixgbe",
1440 sizeof(struct ixgbe_fdir_filter *) *
1441 IXGBE_MAX_FDIR_FILTER_NUM,
1443 if (!fdir_info->hash_map) {
1445 "Failed to allocate memory for fdir hash map!");
1448 fdir_info->mask_added = FALSE;
1453 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1455 struct ixgbe_l2_tn_info *l2_tn_info =
1456 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1457 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1458 struct rte_hash_parameters l2_tn_hash_params = {
1459 .name = l2_tn_hash_name,
1460 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1461 .key_len = sizeof(struct ixgbe_l2_tn_key),
1462 .hash_func = rte_hash_crc,
1463 .hash_func_init_val = 0,
1464 .socket_id = rte_socket_id(),
1467 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1468 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1469 "l2_tn_%s", eth_dev->device->name);
1470 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1471 if (!l2_tn_info->hash_handle) {
1472 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1475 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1476 sizeof(struct ixgbe_l2_tn_filter *) *
1477 IXGBE_MAX_L2_TN_FILTER_NUM,
1479 if (!l2_tn_info->hash_map) {
1481 "Failed to allocate memory for L2 TN hash map!");
1484 l2_tn_info->e_tag_en = FALSE;
1485 l2_tn_info->e_tag_fwd_en = FALSE;
1486 l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1491 * Negotiate mailbox API version with the PF.
1492 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1493 * Then we try to negotiate starting with the most recent one.
1494 * If all negotiation attempts fail, then we will proceed with
1495 * the default one (ixgbe_mbox_api_10).
1498 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1502 /* start with highest supported, proceed down */
1503 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1510 i != RTE_DIM(sup_ver) &&
1511 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1517 generate_random_mac_addr(struct ether_addr *mac_addr)
1521 /* Set Organizationally Unique Identifier (OUI) prefix. */
1522 mac_addr->addr_bytes[0] = 0x00;
1523 mac_addr->addr_bytes[1] = 0x09;
1524 mac_addr->addr_bytes[2] = 0xC0;
1525 /* Force indication of locally assigned MAC address. */
1526 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1527 /* Generate the last 3 bytes of the MAC address with a random number. */
1528 random = rte_rand();
1529 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1533 * Virtual Function device init
1536 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1540 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1541 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1542 struct ixgbe_hw *hw =
1543 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1544 struct ixgbe_vfta *shadow_vfta =
1545 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1546 struct ixgbe_hwstrip *hwstrip =
1547 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1548 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1550 PMD_INIT_FUNC_TRACE();
1552 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1553 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1554 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1556 /* for secondary processes, we don't initialise any further as primary
1557 * has already done this work. Only check we don't need a different
1560 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1561 struct ixgbe_tx_queue *txq;
1562 /* TX queue function in primary, set by last queue initialized
1563 * Tx queue may not initialized by primary process
1565 if (eth_dev->data->tx_queues) {
1566 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1567 ixgbe_set_tx_function(eth_dev, txq);
1569 /* Use default TX function if we get here */
1570 PMD_INIT_LOG(NOTICE,
1571 "No TX queues configured yet. Using default TX function.");
1574 ixgbe_set_rx_function(eth_dev);
1579 rte_eth_copy_pci_info(eth_dev, pci_dev);
1581 hw->device_id = pci_dev->id.device_id;
1582 hw->vendor_id = pci_dev->id.vendor_id;
1583 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1585 /* initialize the vfta */
1586 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1588 /* initialize the hw strip bitmap*/
1589 memset(hwstrip, 0, sizeof(*hwstrip));
1591 /* Initialize the shared code (base driver) */
1592 diag = ixgbe_init_shared_code(hw);
1593 if (diag != IXGBE_SUCCESS) {
1594 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1598 /* init_mailbox_params */
1599 hw->mbx.ops.init_params(hw);
1601 /* Reset the hw statistics */
1602 ixgbevf_dev_stats_reset(eth_dev);
1604 /* Disable the interrupts for VF */
1605 ixgbevf_intr_disable(hw);
1607 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1608 diag = hw->mac.ops.reset_hw(hw);
1611 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1612 * the underlying PF driver has not assigned a MAC address to the VF.
1613 * In this case, assign a random MAC address.
1615 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1616 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1620 /* negotiate mailbox API version to use with the PF. */
1621 ixgbevf_negotiate_api(hw);
1623 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1624 ixgbevf_get_queues(hw, &tcs, &tc);
1626 /* Allocate memory for storing MAC addresses */
1627 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1628 hw->mac.num_rar_entries, 0);
1629 if (eth_dev->data->mac_addrs == NULL) {
1631 "Failed to allocate %u bytes needed to store "
1633 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1637 /* Generate a random MAC address, if none was assigned by PF. */
1638 if (is_zero_ether_addr(perm_addr)) {
1639 generate_random_mac_addr(perm_addr);
1640 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1642 rte_free(eth_dev->data->mac_addrs);
1643 eth_dev->data->mac_addrs = NULL;
1646 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1647 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1648 "%02x:%02x:%02x:%02x:%02x:%02x",
1649 perm_addr->addr_bytes[0],
1650 perm_addr->addr_bytes[1],
1651 perm_addr->addr_bytes[2],
1652 perm_addr->addr_bytes[3],
1653 perm_addr->addr_bytes[4],
1654 perm_addr->addr_bytes[5]);
1657 /* Copy the permanent MAC address */
1658 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1660 /* reset the hardware with the new settings */
1661 diag = hw->mac.ops.start_hw(hw);
1667 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1671 rte_intr_callback_register(intr_handle,
1672 ixgbevf_dev_interrupt_handler, eth_dev);
1673 rte_intr_enable(intr_handle);
1674 ixgbevf_intr_enable(hw);
1676 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1677 eth_dev->data->port_id, pci_dev->id.vendor_id,
1678 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1683 /* Virtual Function device uninit */
1686 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1688 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1689 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1690 struct ixgbe_hw *hw;
1692 PMD_INIT_FUNC_TRACE();
1694 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1697 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1699 if (hw->adapter_stopped == 0)
1700 ixgbevf_dev_close(eth_dev);
1702 eth_dev->dev_ops = NULL;
1703 eth_dev->rx_pkt_burst = NULL;
1704 eth_dev->tx_pkt_burst = NULL;
1706 /* Disable the interrupts for VF */
1707 ixgbevf_intr_disable(hw);
1709 rte_free(eth_dev->data->mac_addrs);
1710 eth_dev->data->mac_addrs = NULL;
1712 rte_intr_disable(intr_handle);
1713 rte_intr_callback_unregister(intr_handle,
1714 ixgbevf_dev_interrupt_handler, eth_dev);
1719 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1720 struct rte_pci_device *pci_dev)
1722 return rte_eth_dev_pci_generic_probe(pci_dev,
1723 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1726 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1728 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1731 static struct rte_pci_driver rte_ixgbe_pmd = {
1732 .id_table = pci_id_ixgbe_map,
1733 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1734 RTE_PCI_DRV_IOVA_AS_VA,
1735 .probe = eth_ixgbe_pci_probe,
1736 .remove = eth_ixgbe_pci_remove,
1739 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1740 struct rte_pci_device *pci_dev)
1742 return rte_eth_dev_pci_generic_probe(pci_dev,
1743 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1746 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1748 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1752 * virtual function driver struct
1754 static struct rte_pci_driver rte_ixgbevf_pmd = {
1755 .id_table = pci_id_ixgbevf_map,
1756 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1757 .probe = eth_ixgbevf_pci_probe,
1758 .remove = eth_ixgbevf_pci_remove,
1762 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1764 struct ixgbe_hw *hw =
1765 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1766 struct ixgbe_vfta *shadow_vfta =
1767 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1772 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1773 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1774 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1779 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1781 /* update local VFTA copy */
1782 shadow_vfta->vfta[vid_idx] = vfta;
1788 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1791 ixgbe_vlan_hw_strip_enable(dev, queue);
1793 ixgbe_vlan_hw_strip_disable(dev, queue);
1797 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1798 enum rte_vlan_type vlan_type,
1801 struct ixgbe_hw *hw =
1802 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1807 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1808 qinq &= IXGBE_DMATXCTL_GDV;
1810 switch (vlan_type) {
1811 case ETH_VLAN_TYPE_INNER:
1813 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1814 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1815 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1816 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1817 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1818 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1819 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1822 PMD_DRV_LOG(ERR, "Inner type is not supported"
1826 case ETH_VLAN_TYPE_OUTER:
1828 /* Only the high 16-bits is valid */
1829 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1830 IXGBE_EXVET_VET_EXT_SHIFT);
1832 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1833 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1834 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1835 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1836 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1837 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1838 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1844 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1852 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1854 struct ixgbe_hw *hw =
1855 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1858 PMD_INIT_FUNC_TRACE();
1860 /* Filter Table Disable */
1861 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1862 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1864 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1868 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1870 struct ixgbe_hw *hw =
1871 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872 struct ixgbe_vfta *shadow_vfta =
1873 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1877 PMD_INIT_FUNC_TRACE();
1879 /* Filter Table Enable */
1880 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1881 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1882 vlnctrl |= IXGBE_VLNCTRL_VFE;
1884 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1886 /* write whatever is in local vfta copy */
1887 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1888 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1892 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1894 struct ixgbe_hwstrip *hwstrip =
1895 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1896 struct ixgbe_rx_queue *rxq;
1898 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1902 IXGBE_SET_HWSTRIP(hwstrip, queue);
1904 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1906 if (queue >= dev->data->nb_rx_queues)
1909 rxq = dev->data->rx_queues[queue];
1912 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1914 rxq->vlan_flags = PKT_RX_VLAN;
1918 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1920 struct ixgbe_hw *hw =
1921 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1924 PMD_INIT_FUNC_TRACE();
1926 if (hw->mac.type == ixgbe_mac_82598EB) {
1927 /* No queue level support */
1928 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1932 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1933 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1934 ctrl &= ~IXGBE_RXDCTL_VME;
1935 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1937 /* record those setting for HW strip per queue */
1938 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1942 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1944 struct ixgbe_hw *hw =
1945 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1948 PMD_INIT_FUNC_TRACE();
1950 if (hw->mac.type == ixgbe_mac_82598EB) {
1951 /* No queue level supported */
1952 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1956 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1957 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1958 ctrl |= IXGBE_RXDCTL_VME;
1959 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1961 /* record those setting for HW strip per queue */
1962 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1966 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1968 struct ixgbe_hw *hw =
1969 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1972 struct ixgbe_rx_queue *rxq;
1974 PMD_INIT_FUNC_TRACE();
1976 if (hw->mac.type == ixgbe_mac_82598EB) {
1977 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1978 ctrl &= ~IXGBE_VLNCTRL_VME;
1979 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1981 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1982 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1983 rxq = dev->data->rx_queues[i];
1984 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1985 ctrl &= ~IXGBE_RXDCTL_VME;
1986 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1988 /* record those setting for HW strip per queue */
1989 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1995 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1997 struct ixgbe_hw *hw =
1998 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2001 struct ixgbe_rx_queue *rxq;
2003 PMD_INIT_FUNC_TRACE();
2005 if (hw->mac.type == ixgbe_mac_82598EB) {
2006 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2007 ctrl |= IXGBE_VLNCTRL_VME;
2008 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2010 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2011 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2012 rxq = dev->data->rx_queues[i];
2013 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2014 ctrl |= IXGBE_RXDCTL_VME;
2015 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2017 /* record those setting for HW strip per queue */
2018 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2024 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2026 struct ixgbe_hw *hw =
2027 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2030 PMD_INIT_FUNC_TRACE();
2032 /* DMATXCTRL: Geric Double VLAN Disable */
2033 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2034 ctrl &= ~IXGBE_DMATXCTL_GDV;
2035 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2037 /* CTRL_EXT: Global Double VLAN Disable */
2038 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2039 ctrl &= ~IXGBE_EXTENDED_VLAN;
2040 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2045 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2047 struct ixgbe_hw *hw =
2048 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2051 PMD_INIT_FUNC_TRACE();
2053 /* DMATXCTRL: Geric Double VLAN Enable */
2054 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2055 ctrl |= IXGBE_DMATXCTL_GDV;
2056 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2058 /* CTRL_EXT: Global Double VLAN Enable */
2059 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2060 ctrl |= IXGBE_EXTENDED_VLAN;
2061 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2063 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2064 if (hw->mac.type == ixgbe_mac_X550 ||
2065 hw->mac.type == ixgbe_mac_X550EM_x ||
2066 hw->mac.type == ixgbe_mac_X550EM_a) {
2067 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2068 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2069 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2073 * VET EXT field in the EXVET register = 0x8100 by default
2074 * So no need to change. Same to VT field of DMATXCTL register
2079 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2081 if (mask & ETH_VLAN_STRIP_MASK) {
2082 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2083 ixgbe_vlan_hw_strip_enable_all(dev);
2085 ixgbe_vlan_hw_strip_disable_all(dev);
2088 if (mask & ETH_VLAN_FILTER_MASK) {
2089 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2090 ixgbe_vlan_hw_filter_enable(dev);
2092 ixgbe_vlan_hw_filter_disable(dev);
2095 if (mask & ETH_VLAN_EXTEND_MASK) {
2096 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2097 ixgbe_vlan_hw_extend_enable(dev);
2099 ixgbe_vlan_hw_extend_disable(dev);
2106 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2108 struct ixgbe_hw *hw =
2109 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2110 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2111 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2113 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2114 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2118 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2120 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2125 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2128 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2134 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2135 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2136 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2137 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2142 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2144 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2145 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2146 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2147 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2149 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2150 /* check multi-queue mode */
2151 switch (dev_conf->rxmode.mq_mode) {
2152 case ETH_MQ_RX_VMDQ_DCB:
2153 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2155 case ETH_MQ_RX_VMDQ_DCB_RSS:
2156 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2157 PMD_INIT_LOG(ERR, "SRIOV active,"
2158 " unsupported mq_mode rx %d.",
2159 dev_conf->rxmode.mq_mode);
2162 case ETH_MQ_RX_VMDQ_RSS:
2163 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2164 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2165 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2166 PMD_INIT_LOG(ERR, "SRIOV is active,"
2167 " invalid queue number"
2168 " for VMDQ RSS, allowed"
2169 " value are 1, 2 or 4.");
2173 case ETH_MQ_RX_VMDQ_ONLY:
2174 case ETH_MQ_RX_NONE:
2175 /* if nothing mq mode configure, use default scheme */
2176 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2178 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2179 /* SRIOV only works in VMDq enable mode */
2180 PMD_INIT_LOG(ERR, "SRIOV is active,"
2181 " wrong mq_mode rx %d.",
2182 dev_conf->rxmode.mq_mode);
2186 switch (dev_conf->txmode.mq_mode) {
2187 case ETH_MQ_TX_VMDQ_DCB:
2188 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2189 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2191 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2192 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2196 /* check valid queue number */
2197 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2198 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2199 PMD_INIT_LOG(ERR, "SRIOV is active,"
2200 " nb_rx_q=%d nb_tx_q=%d queue number"
2201 " must be less than or equal to %d.",
2203 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2207 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2208 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2212 /* check configuration for vmdb+dcb mode */
2213 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2214 const struct rte_eth_vmdq_dcb_conf *conf;
2216 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2217 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2218 IXGBE_VMDQ_DCB_NB_QUEUES);
2221 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2222 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2223 conf->nb_queue_pools == ETH_32_POOLS)) {
2224 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2225 " nb_queue_pools must be %d or %d.",
2226 ETH_16_POOLS, ETH_32_POOLS);
2230 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2231 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2233 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2234 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2235 IXGBE_VMDQ_DCB_NB_QUEUES);
2238 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2239 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2240 conf->nb_queue_pools == ETH_32_POOLS)) {
2241 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2242 " nb_queue_pools != %d and"
2243 " nb_queue_pools != %d.",
2244 ETH_16_POOLS, ETH_32_POOLS);
2249 /* For DCB mode check our configuration before we go further */
2250 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2251 const struct rte_eth_dcb_rx_conf *conf;
2253 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2254 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2255 IXGBE_DCB_NB_QUEUES);
2258 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2259 if (!(conf->nb_tcs == ETH_4_TCS ||
2260 conf->nb_tcs == ETH_8_TCS)) {
2261 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2262 " and nb_tcs != %d.",
2263 ETH_4_TCS, ETH_8_TCS);
2268 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2269 const struct rte_eth_dcb_tx_conf *conf;
2271 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2272 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2273 IXGBE_DCB_NB_QUEUES);
2276 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2277 if (!(conf->nb_tcs == ETH_4_TCS ||
2278 conf->nb_tcs == ETH_8_TCS)) {
2279 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2280 " and nb_tcs != %d.",
2281 ETH_4_TCS, ETH_8_TCS);
2287 * When DCB/VT is off, maximum number of queues changes,
2288 * except for 82598EB, which remains constant.
2290 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2291 hw->mac.type != ixgbe_mac_82598EB) {
2292 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2294 "Neither VT nor DCB are enabled, "
2296 IXGBE_NONE_MODE_TX_NB_QUEUES);
2305 ixgbe_dev_configure(struct rte_eth_dev *dev)
2307 struct ixgbe_interrupt *intr =
2308 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2309 struct ixgbe_adapter *adapter =
2310 (struct ixgbe_adapter *)dev->data->dev_private;
2313 PMD_INIT_FUNC_TRACE();
2314 /* multipe queue mode checking */
2315 ret = ixgbe_check_mq_mode(dev);
2317 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2322 /* set flag to update link status after init */
2323 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2326 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2327 * allocation or vector Rx preconditions we will reset it.
2329 adapter->rx_bulk_alloc_allowed = true;
2330 adapter->rx_vec_allowed = true;
2336 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2338 struct ixgbe_hw *hw =
2339 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2340 struct ixgbe_interrupt *intr =
2341 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2344 /* only set up it on X550EM_X */
2345 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2346 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2347 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2348 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2349 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2350 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2355 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2356 uint16_t tx_rate, uint64_t q_msk)
2358 struct ixgbe_hw *hw;
2359 struct ixgbe_vf_info *vfinfo;
2360 struct rte_eth_link link;
2361 uint8_t nb_q_per_pool;
2362 uint32_t queue_stride;
2363 uint32_t queue_idx, idx = 0, vf_idx;
2365 uint16_t total_rate = 0;
2366 struct rte_pci_device *pci_dev;
2368 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2369 rte_eth_link_get_nowait(dev->data->port_id, &link);
2371 if (vf >= pci_dev->max_vfs)
2374 if (tx_rate > link.link_speed)
2380 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2381 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2382 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2383 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2384 queue_idx = vf * queue_stride;
2385 queue_end = queue_idx + nb_q_per_pool - 1;
2386 if (queue_end >= hw->mac.max_tx_queues)
2390 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2393 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2395 total_rate += vfinfo[vf_idx].tx_rate[idx];
2401 /* Store tx_rate for this vf. */
2402 for (idx = 0; idx < nb_q_per_pool; idx++) {
2403 if (((uint64_t)0x1 << idx) & q_msk) {
2404 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2405 vfinfo[vf].tx_rate[idx] = tx_rate;
2406 total_rate += tx_rate;
2410 if (total_rate > dev->data->dev_link.link_speed) {
2411 /* Reset stored TX rate of the VF if it causes exceed
2414 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2418 /* Set RTTBCNRC of each queue/pool for vf X */
2419 for (; queue_idx <= queue_end; queue_idx++) {
2421 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2429 * Configure device link speed and setup link.
2430 * It returns 0 on success.
2433 ixgbe_dev_start(struct rte_eth_dev *dev)
2435 struct ixgbe_hw *hw =
2436 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2437 struct ixgbe_vf_info *vfinfo =
2438 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2439 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2440 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2441 uint32_t intr_vector = 0;
2442 int err, link_up = 0, negotiate = 0;
2447 uint32_t *link_speeds;
2448 struct ixgbe_tm_conf *tm_conf =
2449 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2451 PMD_INIT_FUNC_TRACE();
2453 /* IXGBE devices don't support:
2454 * - half duplex (checked afterwards for valid speeds)
2455 * - fixed speed: TODO implement
2457 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2459 "Invalid link_speeds for port %u, fix speed not supported",
2460 dev->data->port_id);
2464 /* disable uio/vfio intr/eventfd mapping */
2465 rte_intr_disable(intr_handle);
2468 hw->adapter_stopped = 0;
2469 ixgbe_stop_adapter(hw);
2471 /* reinitialize adapter
2472 * this calls reset and start
2474 status = ixgbe_pf_reset_hw(hw);
2477 hw->mac.ops.start_hw(hw);
2478 hw->mac.get_link_status = true;
2480 /* configure PF module if SRIOV enabled */
2481 ixgbe_pf_host_configure(dev);
2483 ixgbe_dev_phy_intr_setup(dev);
2485 /* check and configure queue intr-vector mapping */
2486 if ((rte_intr_cap_multiple(intr_handle) ||
2487 !RTE_ETH_DEV_SRIOV(dev).active) &&
2488 dev->data->dev_conf.intr_conf.rxq != 0) {
2489 intr_vector = dev->data->nb_rx_queues;
2490 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2491 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2492 IXGBE_MAX_INTR_QUEUE_NUM);
2495 if (rte_intr_efd_enable(intr_handle, intr_vector))
2499 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2500 intr_handle->intr_vec =
2501 rte_zmalloc("intr_vec",
2502 dev->data->nb_rx_queues * sizeof(int), 0);
2503 if (intr_handle->intr_vec == NULL) {
2504 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2505 " intr_vec", dev->data->nb_rx_queues);
2510 /* confiugre msix for sleep until rx interrupt */
2511 ixgbe_configure_msix(dev);
2513 /* initialize transmission unit */
2514 ixgbe_dev_tx_init(dev);
2516 /* This can fail when allocating mbufs for descriptor rings */
2517 err = ixgbe_dev_rx_init(dev);
2519 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2523 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2524 ETH_VLAN_EXTEND_MASK;
2525 err = ixgbe_vlan_offload_set(dev, mask);
2527 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2531 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2532 /* Enable vlan filtering for VMDq */
2533 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2536 /* Configure DCB hw */
2537 ixgbe_configure_dcb(dev);
2539 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2540 err = ixgbe_fdir_configure(dev);
2545 /* Restore vf rate limit */
2546 if (vfinfo != NULL) {
2547 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2548 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2549 if (vfinfo[vf].tx_rate[idx] != 0)
2550 ixgbe_set_vf_rate_limit(
2552 vfinfo[vf].tx_rate[idx],
2556 ixgbe_restore_statistics_mapping(dev);
2558 err = ixgbe_dev_rxtx_start(dev);
2560 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2564 /* Skip link setup if loopback mode is enabled for 82599. */
2565 if (hw->mac.type == ixgbe_mac_82599EB &&
2566 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2567 goto skip_link_setup;
2569 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2570 err = hw->mac.ops.setup_sfp(hw);
2575 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2576 /* Turn on the copper */
2577 ixgbe_set_phy_power(hw, true);
2579 /* Turn on the laser */
2580 ixgbe_enable_tx_laser(hw);
2583 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2586 dev->data->dev_link.link_status = link_up;
2588 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2592 link_speeds = &dev->data->dev_conf.link_speeds;
2593 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2594 ETH_LINK_SPEED_10G)) {
2595 PMD_INIT_LOG(ERR, "Invalid link setting");
2600 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2601 switch (hw->mac.type) {
2602 case ixgbe_mac_82598EB:
2603 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2605 case ixgbe_mac_82599EB:
2606 case ixgbe_mac_X540:
2607 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2609 case ixgbe_mac_X550:
2610 case ixgbe_mac_X550EM_x:
2611 case ixgbe_mac_X550EM_a:
2612 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2615 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2618 if (*link_speeds & ETH_LINK_SPEED_10G)
2619 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2620 if (*link_speeds & ETH_LINK_SPEED_1G)
2621 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2622 if (*link_speeds & ETH_LINK_SPEED_100M)
2623 speed |= IXGBE_LINK_SPEED_100_FULL;
2626 err = ixgbe_setup_link(hw, speed, link_up);
2632 if (rte_intr_allow_others(intr_handle)) {
2633 /* check if lsc interrupt is enabled */
2634 if (dev->data->dev_conf.intr_conf.lsc != 0)
2635 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2637 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2638 ixgbe_dev_macsec_interrupt_setup(dev);
2640 rte_intr_callback_unregister(intr_handle,
2641 ixgbe_dev_interrupt_handler, dev);
2642 if (dev->data->dev_conf.intr_conf.lsc != 0)
2643 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2644 " no intr multiplex");
2647 /* check if rxq interrupt is enabled */
2648 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2649 rte_intr_dp_is_en(intr_handle))
2650 ixgbe_dev_rxq_interrupt_setup(dev);
2652 /* enable uio/vfio intr/eventfd mapping */
2653 rte_intr_enable(intr_handle);
2655 /* resume enabled intr since hw reset */
2656 ixgbe_enable_intr(dev);
2657 ixgbe_l2_tunnel_conf(dev);
2658 ixgbe_filter_restore(dev);
2660 if (tm_conf->root && !tm_conf->committed)
2661 PMD_DRV_LOG(WARNING,
2662 "please call hierarchy_commit() "
2663 "before starting the port");
2668 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2669 ixgbe_dev_clear_queues(dev);
2674 * Stop device: disable rx and tx functions to allow for reconfiguring.
2677 ixgbe_dev_stop(struct rte_eth_dev *dev)
2679 struct rte_eth_link link;
2680 struct ixgbe_hw *hw =
2681 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2682 struct ixgbe_vf_info *vfinfo =
2683 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2684 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2685 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2687 struct ixgbe_tm_conf *tm_conf =
2688 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2690 PMD_INIT_FUNC_TRACE();
2692 /* disable interrupts */
2693 ixgbe_disable_intr(hw);
2696 ixgbe_pf_reset_hw(hw);
2697 hw->adapter_stopped = 0;
2700 ixgbe_stop_adapter(hw);
2702 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2703 vfinfo[vf].clear_to_send = false;
2705 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2706 /* Turn off the copper */
2707 ixgbe_set_phy_power(hw, false);
2709 /* Turn off the laser */
2710 ixgbe_disable_tx_laser(hw);
2713 ixgbe_dev_clear_queues(dev);
2715 /* Clear stored conf */
2716 dev->data->scattered_rx = 0;
2719 /* Clear recorded link status */
2720 memset(&link, 0, sizeof(link));
2721 rte_eth_linkstatus_set(dev, &link);
2723 if (!rte_intr_allow_others(intr_handle))
2724 /* resume to the default handler */
2725 rte_intr_callback_register(intr_handle,
2726 ixgbe_dev_interrupt_handler,
2729 /* Clean datapath event and queue/vec mapping */
2730 rte_intr_efd_disable(intr_handle);
2731 if (intr_handle->intr_vec != NULL) {
2732 rte_free(intr_handle->intr_vec);
2733 intr_handle->intr_vec = NULL;
2736 /* reset hierarchy commit */
2737 tm_conf->committed = false;
2741 * Set device link up: enable tx.
2744 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2746 struct ixgbe_hw *hw =
2747 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2748 if (hw->mac.type == ixgbe_mac_82599EB) {
2749 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2750 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2751 /* Not suported in bypass mode */
2752 PMD_INIT_LOG(ERR, "Set link up is not supported "
2753 "by device id 0x%x", hw->device_id);
2759 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2760 /* Turn on the copper */
2761 ixgbe_set_phy_power(hw, true);
2763 /* Turn on the laser */
2764 ixgbe_enable_tx_laser(hw);
2771 * Set device link down: disable tx.
2774 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2776 struct ixgbe_hw *hw =
2777 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2778 if (hw->mac.type == ixgbe_mac_82599EB) {
2779 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2780 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2781 /* Not suported in bypass mode */
2782 PMD_INIT_LOG(ERR, "Set link down is not supported "
2783 "by device id 0x%x", hw->device_id);
2789 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2790 /* Turn off the copper */
2791 ixgbe_set_phy_power(hw, false);
2793 /* Turn off the laser */
2794 ixgbe_disable_tx_laser(hw);
2801 * Reset and stop device.
2804 ixgbe_dev_close(struct rte_eth_dev *dev)
2806 struct ixgbe_hw *hw =
2807 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2809 PMD_INIT_FUNC_TRACE();
2811 ixgbe_pf_reset_hw(hw);
2813 ixgbe_dev_stop(dev);
2814 hw->adapter_stopped = 1;
2816 ixgbe_dev_free_queues(dev);
2818 ixgbe_disable_pcie_master(hw);
2820 /* reprogram the RAR[0] in case user changed it. */
2821 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2828 ixgbe_dev_reset(struct rte_eth_dev *dev)
2832 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2833 * its VF to make them align with it. The detailed notification
2834 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2835 * To avoid unexpected behavior in VF, currently reset of PF with
2836 * SR-IOV activation is not supported. It might be supported later.
2838 if (dev->data->sriov.active)
2841 ret = eth_ixgbe_dev_uninit(dev);
2845 ret = eth_ixgbe_dev_init(dev);
2851 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2852 struct ixgbe_hw_stats *hw_stats,
2853 struct ixgbe_macsec_stats *macsec_stats,
2854 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2855 uint64_t *total_qprc, uint64_t *total_qprdc)
2857 uint32_t bprc, lxon, lxoff, total;
2858 uint32_t delta_gprc = 0;
2860 /* Workaround for RX byte count not including CRC bytes when CRC
2861 * strip is enabled. CRC bytes are removed from counters when crc_strip
2864 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2865 IXGBE_HLREG0_RXCRCSTRP);
2867 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2868 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2869 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2870 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2872 for (i = 0; i < 8; i++) {
2873 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2875 /* global total per queue */
2876 hw_stats->mpc[i] += mp;
2877 /* Running comprehensive total for stats display */
2878 *total_missed_rx += hw_stats->mpc[i];
2879 if (hw->mac.type == ixgbe_mac_82598EB) {
2880 hw_stats->rnbc[i] +=
2881 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2882 hw_stats->pxonrxc[i] +=
2883 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2884 hw_stats->pxoffrxc[i] +=
2885 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2887 hw_stats->pxonrxc[i] +=
2888 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2889 hw_stats->pxoffrxc[i] +=
2890 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2891 hw_stats->pxon2offc[i] +=
2892 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2894 hw_stats->pxontxc[i] +=
2895 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2896 hw_stats->pxofftxc[i] +=
2897 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2899 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2900 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2901 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2902 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2904 delta_gprc += delta_qprc;
2906 hw_stats->qprc[i] += delta_qprc;
2907 hw_stats->qptc[i] += delta_qptc;
2909 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2910 hw_stats->qbrc[i] +=
2911 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2913 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2915 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2916 hw_stats->qbtc[i] +=
2917 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2919 hw_stats->qprdc[i] += delta_qprdc;
2920 *total_qprdc += hw_stats->qprdc[i];
2922 *total_qprc += hw_stats->qprc[i];
2923 *total_qbrc += hw_stats->qbrc[i];
2925 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2926 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2927 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2930 * An errata states that gprc actually counts good + missed packets:
2931 * Workaround to set gprc to summated queue packet receives
2933 hw_stats->gprc = *total_qprc;
2935 if (hw->mac.type != ixgbe_mac_82598EB) {
2936 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2937 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2938 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2939 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2940 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2941 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2942 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2943 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2945 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2946 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2947 /* 82598 only has a counter in the high register */
2948 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2949 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2950 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2952 uint64_t old_tpr = hw_stats->tpr;
2954 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2955 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2958 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2960 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2961 hw_stats->gptc += delta_gptc;
2962 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2963 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2966 * Workaround: mprc hardware is incorrectly counting
2967 * broadcasts, so for now we subtract those.
2969 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2970 hw_stats->bprc += bprc;
2971 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2972 if (hw->mac.type == ixgbe_mac_82598EB)
2973 hw_stats->mprc -= bprc;
2975 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2976 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2977 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2978 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2979 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2980 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2982 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2983 hw_stats->lxontxc += lxon;
2984 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2985 hw_stats->lxofftxc += lxoff;
2986 total = lxon + lxoff;
2988 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2989 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2990 hw_stats->gptc -= total;
2991 hw_stats->mptc -= total;
2992 hw_stats->ptc64 -= total;
2993 hw_stats->gotc -= total * ETHER_MIN_LEN;
2995 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2996 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2997 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2998 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2999 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3000 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3001 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3002 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3003 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3004 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3005 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3006 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3007 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3008 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3009 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3010 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3011 /* Only read FCOE on 82599 */
3012 if (hw->mac.type != ixgbe_mac_82598EB) {
3013 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3014 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3015 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3016 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3017 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3020 /* Flow Director Stats registers */
3021 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3022 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3024 /* MACsec Stats registers */
3025 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3026 macsec_stats->out_pkts_encrypted +=
3027 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3028 macsec_stats->out_pkts_protected +=
3029 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3030 macsec_stats->out_octets_encrypted +=
3031 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3032 macsec_stats->out_octets_protected +=
3033 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3034 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3035 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3036 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3037 macsec_stats->in_pkts_unknownsci +=
3038 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3039 macsec_stats->in_octets_decrypted +=
3040 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3041 macsec_stats->in_octets_validated +=
3042 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3043 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3044 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3045 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3046 for (i = 0; i < 2; i++) {
3047 macsec_stats->in_pkts_ok +=
3048 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3049 macsec_stats->in_pkts_invalid +=
3050 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3051 macsec_stats->in_pkts_notvalid +=
3052 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3054 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3055 macsec_stats->in_pkts_notusingsa +=
3056 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3060 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3063 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3065 struct ixgbe_hw *hw =
3066 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3067 struct ixgbe_hw_stats *hw_stats =
3068 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3069 struct ixgbe_macsec_stats *macsec_stats =
3070 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3071 dev->data->dev_private);
3072 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3075 total_missed_rx = 0;
3080 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3081 &total_qbrc, &total_qprc, &total_qprdc);
3086 /* Fill out the rte_eth_stats statistics structure */
3087 stats->ipackets = total_qprc;
3088 stats->ibytes = total_qbrc;
3089 stats->opackets = hw_stats->gptc;
3090 stats->obytes = hw_stats->gotc;
3092 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3093 stats->q_ipackets[i] = hw_stats->qprc[i];
3094 stats->q_opackets[i] = hw_stats->qptc[i];
3095 stats->q_ibytes[i] = hw_stats->qbrc[i];
3096 stats->q_obytes[i] = hw_stats->qbtc[i];
3097 stats->q_errors[i] = hw_stats->qprdc[i];
3101 stats->imissed = total_missed_rx;
3102 stats->ierrors = hw_stats->crcerrs +
3119 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3121 struct ixgbe_hw_stats *stats =
3122 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3124 /* HW registers are cleared on read */
3125 ixgbe_dev_stats_get(dev, NULL);
3127 /* Reset software totals */
3128 memset(stats, 0, sizeof(*stats));
3131 /* This function calculates the number of xstats based on the current config */
3133 ixgbe_xstats_calc_num(void) {
3134 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3135 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3136 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3139 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3140 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3142 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3143 unsigned stat, i, count;
3145 if (xstats_names != NULL) {
3148 /* Note: limit >= cnt_stats checked upstream
3149 * in rte_eth_xstats_names()
3152 /* Extended stats from ixgbe_hw_stats */
3153 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3154 snprintf(xstats_names[count].name,
3155 sizeof(xstats_names[count].name),
3157 rte_ixgbe_stats_strings[i].name);
3162 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3163 snprintf(xstats_names[count].name,
3164 sizeof(xstats_names[count].name),
3166 rte_ixgbe_macsec_strings[i].name);
3170 /* RX Priority Stats */
3171 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3172 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3173 snprintf(xstats_names[count].name,
3174 sizeof(xstats_names[count].name),
3175 "rx_priority%u_%s", i,
3176 rte_ixgbe_rxq_strings[stat].name);
3181 /* TX Priority Stats */
3182 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3183 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3184 snprintf(xstats_names[count].name,
3185 sizeof(xstats_names[count].name),
3186 "tx_priority%u_%s", i,
3187 rte_ixgbe_txq_strings[stat].name);
3195 static int ixgbe_dev_xstats_get_names_by_id(
3196 struct rte_eth_dev *dev,
3197 struct rte_eth_xstat_name *xstats_names,
3198 const uint64_t *ids,
3202 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3203 unsigned int stat, i, count;
3205 if (xstats_names != NULL) {
3208 /* Note: limit >= cnt_stats checked upstream
3209 * in rte_eth_xstats_names()
3212 /* Extended stats from ixgbe_hw_stats */
3213 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3214 snprintf(xstats_names[count].name,
3215 sizeof(xstats_names[count].name),
3217 rte_ixgbe_stats_strings[i].name);
3222 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3223 snprintf(xstats_names[count].name,
3224 sizeof(xstats_names[count].name),
3226 rte_ixgbe_macsec_strings[i].name);
3230 /* RX Priority Stats */
3231 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3232 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3233 snprintf(xstats_names[count].name,
3234 sizeof(xstats_names[count].name),
3235 "rx_priority%u_%s", i,
3236 rte_ixgbe_rxq_strings[stat].name);
3241 /* TX Priority Stats */
3242 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3243 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3244 snprintf(xstats_names[count].name,
3245 sizeof(xstats_names[count].name),
3246 "tx_priority%u_%s", i,
3247 rte_ixgbe_txq_strings[stat].name);
3256 uint16_t size = ixgbe_xstats_calc_num();
3257 struct rte_eth_xstat_name xstats_names_copy[size];
3259 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3262 for (i = 0; i < limit; i++) {
3263 if (ids[i] >= size) {
3264 PMD_INIT_LOG(ERR, "id value isn't valid");
3267 strcpy(xstats_names[i].name,
3268 xstats_names_copy[ids[i]].name);
3273 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3274 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3278 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3281 if (xstats_names != NULL)
3282 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3283 snprintf(xstats_names[i].name,
3284 sizeof(xstats_names[i].name),
3285 "%s", rte_ixgbevf_stats_strings[i].name);
3286 return IXGBEVF_NB_XSTATS;
3290 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3293 struct ixgbe_hw *hw =
3294 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3295 struct ixgbe_hw_stats *hw_stats =
3296 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3297 struct ixgbe_macsec_stats *macsec_stats =
3298 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3299 dev->data->dev_private);
3300 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3301 unsigned i, stat, count = 0;
3303 count = ixgbe_xstats_calc_num();
3308 total_missed_rx = 0;
3313 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3314 &total_qbrc, &total_qprc, &total_qprdc);
3316 /* If this is a reset xstats is NULL, and we have cleared the
3317 * registers by reading them.
3322 /* Extended stats from ixgbe_hw_stats */
3324 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3325 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3326 rte_ixgbe_stats_strings[i].offset);
3327 xstats[count].id = count;
3332 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3333 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3334 rte_ixgbe_macsec_strings[i].offset);
3335 xstats[count].id = count;
3339 /* RX Priority Stats */
3340 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3341 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3342 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3343 rte_ixgbe_rxq_strings[stat].offset +
3344 (sizeof(uint64_t) * i));
3345 xstats[count].id = count;
3350 /* TX Priority Stats */
3351 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3352 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3353 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3354 rte_ixgbe_txq_strings[stat].offset +
3355 (sizeof(uint64_t) * i));
3356 xstats[count].id = count;
3364 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3365 uint64_t *values, unsigned int n)
3368 struct ixgbe_hw *hw =
3369 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3370 struct ixgbe_hw_stats *hw_stats =
3371 IXGBE_DEV_PRIVATE_TO_STATS(
3372 dev->data->dev_private);
3373 struct ixgbe_macsec_stats *macsec_stats =
3374 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3375 dev->data->dev_private);
3376 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3377 unsigned int i, stat, count = 0;
3379 count = ixgbe_xstats_calc_num();
3381 if (!ids && n < count)
3384 total_missed_rx = 0;
3389 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3390 &total_missed_rx, &total_qbrc, &total_qprc,
3393 /* If this is a reset xstats is NULL, and we have cleared the
3394 * registers by reading them.
3396 if (!ids && !values)
3399 /* Extended stats from ixgbe_hw_stats */
3401 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3402 values[count] = *(uint64_t *)(((char *)hw_stats) +
3403 rte_ixgbe_stats_strings[i].offset);
3408 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3409 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3410 rte_ixgbe_macsec_strings[i].offset);
3414 /* RX Priority Stats */
3415 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3416 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3418 *(uint64_t *)(((char *)hw_stats) +
3419 rte_ixgbe_rxq_strings[stat].offset +
3420 (sizeof(uint64_t) * i));
3425 /* TX Priority Stats */
3426 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3427 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3429 *(uint64_t *)(((char *)hw_stats) +
3430 rte_ixgbe_txq_strings[stat].offset +
3431 (sizeof(uint64_t) * i));
3439 uint16_t size = ixgbe_xstats_calc_num();
3440 uint64_t values_copy[size];
3442 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3444 for (i = 0; i < n; i++) {
3445 if (ids[i] >= size) {
3446 PMD_INIT_LOG(ERR, "id value isn't valid");
3449 values[i] = values_copy[ids[i]];
3455 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3457 struct ixgbe_hw_stats *stats =
3458 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3459 struct ixgbe_macsec_stats *macsec_stats =
3460 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3461 dev->data->dev_private);
3463 unsigned count = ixgbe_xstats_calc_num();
3465 /* HW registers are cleared on read */
3466 ixgbe_dev_xstats_get(dev, NULL, count);
3468 /* Reset software totals */
3469 memset(stats, 0, sizeof(*stats));
3470 memset(macsec_stats, 0, sizeof(*macsec_stats));
3474 ixgbevf_update_stats(struct rte_eth_dev *dev)
3476 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3477 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3478 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3480 /* Good Rx packet, include VF loopback */
3481 UPDATE_VF_STAT(IXGBE_VFGPRC,
3482 hw_stats->last_vfgprc, hw_stats->vfgprc);
3484 /* Good Rx octets, include VF loopback */
3485 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3486 hw_stats->last_vfgorc, hw_stats->vfgorc);
3488 /* Good Tx packet, include VF loopback */
3489 UPDATE_VF_STAT(IXGBE_VFGPTC,
3490 hw_stats->last_vfgptc, hw_stats->vfgptc);
3492 /* Good Tx octets, include VF loopback */
3493 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3494 hw_stats->last_vfgotc, hw_stats->vfgotc);
3496 /* Rx Multicst Packet */
3497 UPDATE_VF_STAT(IXGBE_VFMPRC,
3498 hw_stats->last_vfmprc, hw_stats->vfmprc);
3502 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3505 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3506 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3509 if (n < IXGBEVF_NB_XSTATS)
3510 return IXGBEVF_NB_XSTATS;
3512 ixgbevf_update_stats(dev);
3517 /* Extended stats */
3518 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3520 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3521 rte_ixgbevf_stats_strings[i].offset);
3524 return IXGBEVF_NB_XSTATS;
3528 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3530 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3531 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3533 ixgbevf_update_stats(dev);
3538 stats->ipackets = hw_stats->vfgprc;
3539 stats->ibytes = hw_stats->vfgorc;
3540 stats->opackets = hw_stats->vfgptc;
3541 stats->obytes = hw_stats->vfgotc;
3546 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3548 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3549 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3551 /* Sync HW register to the last stats */
3552 ixgbevf_dev_stats_get(dev, NULL);
3554 /* reset HW current stats*/
3555 hw_stats->vfgprc = 0;
3556 hw_stats->vfgorc = 0;
3557 hw_stats->vfgptc = 0;
3558 hw_stats->vfgotc = 0;
3562 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3564 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3565 u16 eeprom_verh, eeprom_verl;
3569 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3570 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3572 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3573 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3575 ret += 1; /* add the size of '\0' */
3576 if (fw_size < (u32)ret)
3583 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3585 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3586 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3587 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3589 dev_info->pci_dev = pci_dev;
3590 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3591 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3592 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3594 * When DCB/VT is off, maximum number of queues changes,
3595 * except for 82598EB, which remains constant.
3597 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3598 hw->mac.type != ixgbe_mac_82598EB)
3599 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3601 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3602 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3603 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3604 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3605 dev_info->max_vfs = pci_dev->max_vfs;
3606 if (hw->mac.type == ixgbe_mac_82598EB)
3607 dev_info->max_vmdq_pools = ETH_16_POOLS;
3609 dev_info->max_vmdq_pools = ETH_64_POOLS;
3610 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3611 dev_info->rx_offload_capa =
3612 DEV_RX_OFFLOAD_VLAN_STRIP |
3613 DEV_RX_OFFLOAD_IPV4_CKSUM |
3614 DEV_RX_OFFLOAD_UDP_CKSUM |
3615 DEV_RX_OFFLOAD_TCP_CKSUM |
3616 DEV_RX_OFFLOAD_CRC_STRIP;
3619 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3622 if ((hw->mac.type == ixgbe_mac_82599EB ||
3623 hw->mac.type == ixgbe_mac_X540) &&
3624 !RTE_ETH_DEV_SRIOV(dev).active)
3625 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3627 if (hw->mac.type == ixgbe_mac_82599EB ||
3628 hw->mac.type == ixgbe_mac_X540)
3629 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3631 if (hw->mac.type == ixgbe_mac_X550 ||
3632 hw->mac.type == ixgbe_mac_X550EM_x ||
3633 hw->mac.type == ixgbe_mac_X550EM_a)
3634 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3636 dev_info->tx_offload_capa =
3637 DEV_TX_OFFLOAD_VLAN_INSERT |
3638 DEV_TX_OFFLOAD_IPV4_CKSUM |
3639 DEV_TX_OFFLOAD_UDP_CKSUM |
3640 DEV_TX_OFFLOAD_TCP_CKSUM |
3641 DEV_TX_OFFLOAD_SCTP_CKSUM |
3642 DEV_TX_OFFLOAD_TCP_TSO;
3644 if (hw->mac.type == ixgbe_mac_82599EB ||
3645 hw->mac.type == ixgbe_mac_X540)
3646 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3648 if (hw->mac.type == ixgbe_mac_X550 ||
3649 hw->mac.type == ixgbe_mac_X550EM_x ||
3650 hw->mac.type == ixgbe_mac_X550EM_a)
3651 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3653 #ifdef RTE_LIBRTE_SECURITY
3654 if (dev->security_ctx) {
3655 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_SECURITY;
3656 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
3660 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3662 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3663 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3664 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3666 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3670 dev_info->default_txconf = (struct rte_eth_txconf) {
3672 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3673 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3674 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3676 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3677 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3678 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3679 ETH_TXQ_FLAGS_NOOFFLOADS,
3682 dev_info->rx_desc_lim = rx_desc_lim;
3683 dev_info->tx_desc_lim = tx_desc_lim;
3685 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3686 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3687 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3689 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3690 if (hw->mac.type == ixgbe_mac_X540 ||
3691 hw->mac.type == ixgbe_mac_X540_vf ||
3692 hw->mac.type == ixgbe_mac_X550 ||
3693 hw->mac.type == ixgbe_mac_X550_vf) {
3694 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3696 if (hw->mac.type == ixgbe_mac_X550) {
3697 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3698 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3702 static const uint32_t *
3703 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3705 static const uint32_t ptypes[] = {
3706 /* For non-vec functions,
3707 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3708 * for vec functions,
3709 * refers to _recv_raw_pkts_vec().
3713 RTE_PTYPE_L3_IPV4_EXT,
3715 RTE_PTYPE_L3_IPV6_EXT,
3719 RTE_PTYPE_TUNNEL_IP,
3720 RTE_PTYPE_INNER_L3_IPV6,
3721 RTE_PTYPE_INNER_L3_IPV6_EXT,
3722 RTE_PTYPE_INNER_L4_TCP,
3723 RTE_PTYPE_INNER_L4_UDP,
3727 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3728 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3729 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3730 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3733 #if defined(RTE_ARCH_X86)
3734 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3735 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3742 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3743 struct rte_eth_dev_info *dev_info)
3745 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3746 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3748 dev_info->pci_dev = pci_dev;
3749 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3750 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3751 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3752 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3753 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3754 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3755 dev_info->max_vfs = pci_dev->max_vfs;
3756 if (hw->mac.type == ixgbe_mac_82598EB)
3757 dev_info->max_vmdq_pools = ETH_16_POOLS;
3759 dev_info->max_vmdq_pools = ETH_64_POOLS;
3760 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3761 DEV_RX_OFFLOAD_IPV4_CKSUM |
3762 DEV_RX_OFFLOAD_UDP_CKSUM |
3763 DEV_RX_OFFLOAD_TCP_CKSUM |
3764 DEV_RX_OFFLOAD_CRC_STRIP;
3765 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3766 DEV_TX_OFFLOAD_IPV4_CKSUM |
3767 DEV_TX_OFFLOAD_UDP_CKSUM |
3768 DEV_TX_OFFLOAD_TCP_CKSUM |
3769 DEV_TX_OFFLOAD_SCTP_CKSUM |
3770 DEV_TX_OFFLOAD_TCP_TSO;
3772 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3774 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3775 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3776 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3778 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3782 dev_info->default_txconf = (struct rte_eth_txconf) {
3784 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3785 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3786 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3788 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3789 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3790 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3791 ETH_TXQ_FLAGS_NOOFFLOADS,
3794 dev_info->rx_desc_lim = rx_desc_lim;
3795 dev_info->tx_desc_lim = tx_desc_lim;
3799 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3800 int *link_up, int wait_to_complete)
3803 * for a quick link status checking, wait_to_compelet == 0,
3804 * skip PF link status checking
3806 bool no_pflink_check = wait_to_complete == 0;
3807 struct ixgbe_mbx_info *mbx = &hw->mbx;
3808 struct ixgbe_mac_info *mac = &hw->mac;
3809 uint32_t links_reg, in_msg;
3812 /* If we were hit with a reset drop the link */
3813 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3814 mac->get_link_status = true;
3816 if (!mac->get_link_status)
3819 /* if link status is down no point in checking to see if pf is up */
3820 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3821 if (!(links_reg & IXGBE_LINKS_UP))
3824 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3825 * before the link status is correct
3827 if (mac->type == ixgbe_mac_82599_vf) {
3830 for (i = 0; i < 5; i++) {
3832 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3834 if (!(links_reg & IXGBE_LINKS_UP))
3839 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3840 case IXGBE_LINKS_SPEED_10G_82599:
3841 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3842 if (hw->mac.type >= ixgbe_mac_X550) {
3843 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3844 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3847 case IXGBE_LINKS_SPEED_1G_82599:
3848 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3850 case IXGBE_LINKS_SPEED_100_82599:
3851 *speed = IXGBE_LINK_SPEED_100_FULL;
3852 if (hw->mac.type == ixgbe_mac_X550) {
3853 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3854 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3857 case IXGBE_LINKS_SPEED_10_X550EM_A:
3858 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3859 /* Since Reserved in older MAC's */
3860 if (hw->mac.type >= ixgbe_mac_X550)
3861 *speed = IXGBE_LINK_SPEED_10_FULL;
3864 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3867 if (no_pflink_check) {
3868 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3869 mac->get_link_status = true;
3871 mac->get_link_status = false;
3875 /* if the read failed it could just be a mailbox collision, best wait
3876 * until we are called again and don't report an error
3878 if (mbx->ops.read(hw, &in_msg, 1, 0))
3881 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3882 /* msg is not CTS and is NACK we must have lost CTS status */
3883 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3888 /* the pf is talking, if we timed out in the past we reinit */
3889 if (!mbx->timeout) {
3894 /* if we passed all the tests above then the link is up and we no
3895 * longer need to check for link
3897 mac->get_link_status = false;
3900 *link_up = !mac->get_link_status;
3904 /* return 0 means link status changed, -1 means not changed */
3906 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3907 int wait_to_complete, int vf)
3909 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3910 struct rte_eth_link link;
3911 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3912 struct ixgbe_interrupt *intr =
3913 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3918 bool autoneg = false;
3920 memset(&link, 0, sizeof(link));
3921 link.link_status = ETH_LINK_DOWN;
3922 link.link_speed = 0;
3923 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3924 link.link_autoneg = ETH_LINK_AUTONEG;
3926 hw->mac.get_link_status = true;
3928 if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3929 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3930 speed = hw->phy.autoneg_advertised;
3932 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3933 ixgbe_setup_link(hw, speed, true);
3936 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3937 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3941 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3943 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3946 link.link_speed = ETH_SPEED_NUM_100M;
3947 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3948 return rte_eth_linkstatus_set(dev, &link);
3952 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3953 return rte_eth_linkstatus_set(dev, &link);
3956 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3957 link.link_status = ETH_LINK_UP;
3958 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3960 switch (link_speed) {
3962 case IXGBE_LINK_SPEED_UNKNOWN:
3963 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3964 link.link_speed = ETH_SPEED_NUM_100M;
3967 case IXGBE_LINK_SPEED_100_FULL:
3968 link.link_speed = ETH_SPEED_NUM_100M;
3971 case IXGBE_LINK_SPEED_1GB_FULL:
3972 link.link_speed = ETH_SPEED_NUM_1G;
3975 case IXGBE_LINK_SPEED_2_5GB_FULL:
3976 link.link_speed = ETH_SPEED_NUM_2_5G;
3979 case IXGBE_LINK_SPEED_5GB_FULL:
3980 link.link_speed = ETH_SPEED_NUM_5G;
3983 case IXGBE_LINK_SPEED_10GB_FULL:
3984 link.link_speed = ETH_SPEED_NUM_10G;
3988 return rte_eth_linkstatus_set(dev, &link);
3992 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3994 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
3998 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4000 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4004 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4006 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4009 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4010 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4011 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4015 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4017 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4020 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4021 fctrl &= (~IXGBE_FCTRL_UPE);
4022 if (dev->data->all_multicast == 1)
4023 fctrl |= IXGBE_FCTRL_MPE;
4025 fctrl &= (~IXGBE_FCTRL_MPE);
4026 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4030 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4032 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4035 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4036 fctrl |= IXGBE_FCTRL_MPE;
4037 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4041 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4043 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4046 if (dev->data->promiscuous == 1)
4047 return; /* must remain in all_multicast mode */
4049 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4050 fctrl &= (~IXGBE_FCTRL_MPE);
4051 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4055 * It clears the interrupt causes and enables the interrupt.
4056 * It will be called once only during nic initialized.
4059 * Pointer to struct rte_eth_dev.
4061 * Enable or Disable.
4064 * - On success, zero.
4065 * - On failure, a negative value.
4068 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4070 struct ixgbe_interrupt *intr =
4071 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4073 ixgbe_dev_link_status_print(dev);
4075 intr->mask |= IXGBE_EICR_LSC;
4077 intr->mask &= ~IXGBE_EICR_LSC;
4083 * It clears the interrupt causes and enables the interrupt.
4084 * It will be called once only during nic initialized.
4087 * Pointer to struct rte_eth_dev.
4090 * - On success, zero.
4091 * - On failure, a negative value.
4094 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4096 struct ixgbe_interrupt *intr =
4097 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4099 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4105 * It clears the interrupt causes and enables the interrupt.
4106 * It will be called once only during nic initialized.
4109 * Pointer to struct rte_eth_dev.
4112 * - On success, zero.
4113 * - On failure, a negative value.
4116 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4118 struct ixgbe_interrupt *intr =
4119 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4121 intr->mask |= IXGBE_EICR_LINKSEC;
4127 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4130 * Pointer to struct rte_eth_dev.
4133 * - On success, zero.
4134 * - On failure, a negative value.
4137 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4140 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4141 struct ixgbe_interrupt *intr =
4142 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4144 /* clear all cause mask */
4145 ixgbe_disable_intr(hw);
4147 /* read-on-clear nic registers here */
4148 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4149 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4153 /* set flag for async link update */
4154 if (eicr & IXGBE_EICR_LSC)
4155 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4157 if (eicr & IXGBE_EICR_MAILBOX)
4158 intr->flags |= IXGBE_FLAG_MAILBOX;
4160 if (eicr & IXGBE_EICR_LINKSEC)
4161 intr->flags |= IXGBE_FLAG_MACSEC;
4163 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4164 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4165 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4166 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4172 * It gets and then prints the link status.
4175 * Pointer to struct rte_eth_dev.
4178 * - On success, zero.
4179 * - On failure, a negative value.
4182 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4184 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4185 struct rte_eth_link link;
4187 rte_eth_linkstatus_get(dev, &link);
4189 if (link.link_status) {
4190 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4191 (int)(dev->data->port_id),
4192 (unsigned)link.link_speed,
4193 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4194 "full-duplex" : "half-duplex");
4196 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4197 (int)(dev->data->port_id));
4199 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4200 pci_dev->addr.domain,
4202 pci_dev->addr.devid,
4203 pci_dev->addr.function);
4207 * It executes link_update after knowing an interrupt occurred.
4210 * Pointer to struct rte_eth_dev.
4213 * - On success, zero.
4214 * - On failure, a negative value.
4217 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4218 struct rte_intr_handle *intr_handle)
4220 struct ixgbe_interrupt *intr =
4221 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4223 struct ixgbe_hw *hw =
4224 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4226 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4228 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4229 ixgbe_pf_mbx_process(dev);
4230 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4233 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4234 ixgbe_handle_lasi(hw);
4235 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4238 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4239 struct rte_eth_link link;
4241 /* get the link status before link update, for predicting later */
4242 rte_eth_linkstatus_get(dev, &link);
4244 ixgbe_dev_link_update(dev, 0);
4247 if (!link.link_status)
4248 /* handle it 1 sec later, wait it being stable */
4249 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4250 /* likely to down */
4252 /* handle it 4 sec later, wait it being stable */
4253 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4255 ixgbe_dev_link_status_print(dev);
4256 if (rte_eal_alarm_set(timeout * 1000,
4257 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4258 PMD_DRV_LOG(ERR, "Error setting alarm");
4260 /* remember original mask */
4261 intr->mask_original = intr->mask;
4262 /* only disable lsc interrupt */
4263 intr->mask &= ~IXGBE_EIMS_LSC;
4267 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4268 ixgbe_enable_intr(dev);
4269 rte_intr_enable(intr_handle);
4275 * Interrupt handler which shall be registered for alarm callback for delayed
4276 * handling specific interrupt to wait for the stable nic state. As the
4277 * NIC interrupt state is not stable for ixgbe after link is just down,
4278 * it needs to wait 4 seconds to get the stable status.
4281 * Pointer to interrupt handle.
4283 * The address of parameter (struct rte_eth_dev *) regsitered before.
4289 ixgbe_dev_interrupt_delayed_handler(void *param)
4291 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4292 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4293 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4294 struct ixgbe_interrupt *intr =
4295 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4296 struct ixgbe_hw *hw =
4297 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4300 ixgbe_disable_intr(hw);
4302 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4303 if (eicr & IXGBE_EICR_MAILBOX)
4304 ixgbe_pf_mbx_process(dev);
4306 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4307 ixgbe_handle_lasi(hw);
4308 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4311 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4312 ixgbe_dev_link_update(dev, 0);
4313 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4314 ixgbe_dev_link_status_print(dev);
4315 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4319 if (intr->flags & IXGBE_FLAG_MACSEC) {
4320 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4322 intr->flags &= ~IXGBE_FLAG_MACSEC;
4325 /* restore original mask */
4326 intr->mask = intr->mask_original;
4327 intr->mask_original = 0;
4329 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4330 ixgbe_enable_intr(dev);
4331 rte_intr_enable(intr_handle);
4335 * Interrupt handler triggered by NIC for handling
4336 * specific interrupt.
4339 * Pointer to interrupt handle.
4341 * The address of parameter (struct rte_eth_dev *) regsitered before.
4347 ixgbe_dev_interrupt_handler(void *param)
4349 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4351 ixgbe_dev_interrupt_get_status(dev);
4352 ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4356 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4358 struct ixgbe_hw *hw;
4360 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4361 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4365 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4367 struct ixgbe_hw *hw;
4369 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4370 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4374 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4376 struct ixgbe_hw *hw;
4382 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4384 fc_conf->pause_time = hw->fc.pause_time;
4385 fc_conf->high_water = hw->fc.high_water[0];
4386 fc_conf->low_water = hw->fc.low_water[0];
4387 fc_conf->send_xon = hw->fc.send_xon;
4388 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4391 * Return rx_pause status according to actual setting of
4394 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4395 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4401 * Return tx_pause status according to actual setting of
4404 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4405 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4410 if (rx_pause && tx_pause)
4411 fc_conf->mode = RTE_FC_FULL;
4413 fc_conf->mode = RTE_FC_RX_PAUSE;
4415 fc_conf->mode = RTE_FC_TX_PAUSE;
4417 fc_conf->mode = RTE_FC_NONE;
4423 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4425 struct ixgbe_hw *hw;
4427 uint32_t rx_buf_size;
4428 uint32_t max_high_water;
4430 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4437 PMD_INIT_FUNC_TRACE();
4439 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4440 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4441 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4444 * At least reserve one Ethernet frame for watermark
4445 * high_water/low_water in kilo bytes for ixgbe
4447 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4448 if ((fc_conf->high_water > max_high_water) ||
4449 (fc_conf->high_water < fc_conf->low_water)) {
4450 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4451 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4455 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4456 hw->fc.pause_time = fc_conf->pause_time;
4457 hw->fc.high_water[0] = fc_conf->high_water;
4458 hw->fc.low_water[0] = fc_conf->low_water;
4459 hw->fc.send_xon = fc_conf->send_xon;
4460 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4462 err = ixgbe_fc_enable(hw);
4464 /* Not negotiated is not an error case */
4465 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4467 /* check if we want to forward MAC frames - driver doesn't have native
4468 * capability to do that, so we'll write the registers ourselves */
4470 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4472 /* set or clear MFLCN.PMCF bit depending on configuration */
4473 if (fc_conf->mac_ctrl_frame_fwd != 0)
4474 mflcn |= IXGBE_MFLCN_PMCF;
4476 mflcn &= ~IXGBE_MFLCN_PMCF;
4478 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4479 IXGBE_WRITE_FLUSH(hw);
4484 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4489 * ixgbe_pfc_enable_generic - Enable flow control
4490 * @hw: pointer to hardware structure
4491 * @tc_num: traffic class number
4492 * Enable flow control according to the current settings.
4495 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4498 uint32_t mflcn_reg, fccfg_reg;
4500 uint32_t fcrtl, fcrth;
4504 /* Validate the water mark configuration */
4505 if (!hw->fc.pause_time) {
4506 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4510 /* Low water mark of zero causes XOFF floods */
4511 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4512 /* High/Low water can not be 0 */
4513 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4514 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4515 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4519 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4520 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4521 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4525 /* Negotiate the fc mode to use */
4526 ixgbe_fc_autoneg(hw);
4528 /* Disable any previous flow control settings */
4529 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4530 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4532 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4533 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4535 switch (hw->fc.current_mode) {
4538 * If the count of enabled RX Priority Flow control >1,
4539 * and the TX pause can not be disabled
4542 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4543 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4544 if (reg & IXGBE_FCRTH_FCEN)
4548 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4550 case ixgbe_fc_rx_pause:
4552 * Rx Flow control is enabled and Tx Flow control is
4553 * disabled by software override. Since there really
4554 * isn't a way to advertise that we are capable of RX
4555 * Pause ONLY, we will advertise that we support both
4556 * symmetric and asymmetric Rx PAUSE. Later, we will
4557 * disable the adapter's ability to send PAUSE frames.
4559 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4561 * If the count of enabled RX Priority Flow control >1,
4562 * and the TX pause can not be disabled
4565 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4566 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4567 if (reg & IXGBE_FCRTH_FCEN)
4571 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4573 case ixgbe_fc_tx_pause:
4575 * Tx Flow control is enabled, and Rx Flow control is
4576 * disabled by software override.
4578 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4581 /* Flow control (both Rx and Tx) is enabled by SW override. */
4582 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4583 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4586 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4587 ret_val = IXGBE_ERR_CONFIG;
4591 /* Set 802.3x based flow control settings. */
4592 mflcn_reg |= IXGBE_MFLCN_DPF;
4593 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4594 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4596 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4597 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4598 hw->fc.high_water[tc_num]) {
4599 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4600 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4601 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4603 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4605 * In order to prevent Tx hangs when the internal Tx
4606 * switch is enabled we must set the high water mark
4607 * to the maximum FCRTH value. This allows the Tx
4608 * switch to function even under heavy Rx workloads.
4610 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4612 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4614 /* Configure pause time (2 TCs per register) */
4615 reg = hw->fc.pause_time * 0x00010001;
4616 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4617 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4619 /* Configure flow control refresh threshold value */
4620 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4627 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4629 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4630 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4632 if (hw->mac.type != ixgbe_mac_82598EB) {
4633 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4639 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4642 uint32_t rx_buf_size;
4643 uint32_t max_high_water;
4645 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4646 struct ixgbe_hw *hw =
4647 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4648 struct ixgbe_dcb_config *dcb_config =
4649 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4651 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4658 PMD_INIT_FUNC_TRACE();
4660 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4661 tc_num = map[pfc_conf->priority];
4662 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4663 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4665 * At least reserve one Ethernet frame for watermark
4666 * high_water/low_water in kilo bytes for ixgbe
4668 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4669 if ((pfc_conf->fc.high_water > max_high_water) ||
4670 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4671 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4672 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4676 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4677 hw->fc.pause_time = pfc_conf->fc.pause_time;
4678 hw->fc.send_xon = pfc_conf->fc.send_xon;
4679 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4680 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4682 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4684 /* Not negotiated is not an error case */
4685 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4688 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4693 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4694 struct rte_eth_rss_reta_entry64 *reta_conf,
4697 uint16_t i, sp_reta_size;
4700 uint16_t idx, shift;
4701 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4704 PMD_INIT_FUNC_TRACE();
4706 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4707 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4712 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4713 if (reta_size != sp_reta_size) {
4714 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4715 "(%d) doesn't match the number hardware can supported "
4716 "(%d)", reta_size, sp_reta_size);
4720 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4721 idx = i / RTE_RETA_GROUP_SIZE;
4722 shift = i % RTE_RETA_GROUP_SIZE;
4723 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4727 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4728 if (mask == IXGBE_4_BIT_MASK)
4731 r = IXGBE_READ_REG(hw, reta_reg);
4732 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4733 if (mask & (0x1 << j))
4734 reta |= reta_conf[idx].reta[shift + j] <<
4737 reta |= r & (IXGBE_8_BIT_MASK <<
4740 IXGBE_WRITE_REG(hw, reta_reg, reta);
4747 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4748 struct rte_eth_rss_reta_entry64 *reta_conf,
4751 uint16_t i, sp_reta_size;
4754 uint16_t idx, shift;
4755 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4758 PMD_INIT_FUNC_TRACE();
4759 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4760 if (reta_size != sp_reta_size) {
4761 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4762 "(%d) doesn't match the number hardware can supported "
4763 "(%d)", reta_size, sp_reta_size);
4767 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4768 idx = i / RTE_RETA_GROUP_SIZE;
4769 shift = i % RTE_RETA_GROUP_SIZE;
4770 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4775 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4776 reta = IXGBE_READ_REG(hw, reta_reg);
4777 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4778 if (mask & (0x1 << j))
4779 reta_conf[idx].reta[shift + j] =
4780 ((reta >> (CHAR_BIT * j)) &
4789 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4790 uint32_t index, uint32_t pool)
4792 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4793 uint32_t enable_addr = 1;
4795 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4800 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4802 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4804 ixgbe_clear_rar(hw, index);
4808 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4810 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4812 ixgbe_remove_rar(dev, 0);
4814 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4818 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4820 if (strcmp(dev->device->driver->name, drv->driver.name))
4827 is_ixgbe_supported(struct rte_eth_dev *dev)
4829 return is_device_supported(dev, &rte_ixgbe_pmd);
4833 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4837 struct ixgbe_hw *hw;
4838 struct rte_eth_dev_info dev_info;
4839 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4840 struct rte_eth_dev_data *dev_data = dev->data;
4842 ixgbe_dev_info_get(dev, &dev_info);
4844 /* check that mtu is within the allowed range */
4845 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4848 /* If device is started, refuse mtu that requires the support of
4849 * scattered packets when this feature has not been enabled before.
4851 if (dev_data->dev_started && !dev_data->scattered_rx &&
4852 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4853 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4854 PMD_INIT_LOG(ERR, "Stop port first.");
4858 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4859 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4861 /* switch to jumbo mode if needed */
4862 if (frame_size > ETHER_MAX_LEN) {
4863 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4864 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4866 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4867 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4869 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4871 /* update max frame size */
4872 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4874 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4875 maxfrs &= 0x0000FFFF;
4876 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4877 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4883 * Virtual Function operations
4886 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4888 PMD_INIT_FUNC_TRACE();
4890 /* Clear interrupt mask to stop from interrupts being generated */
4891 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4893 IXGBE_WRITE_FLUSH(hw);
4897 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4899 PMD_INIT_FUNC_TRACE();
4901 /* VF enable interrupt autoclean */
4902 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4903 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4904 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4906 IXGBE_WRITE_FLUSH(hw);
4910 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4912 struct rte_eth_conf *conf = &dev->data->dev_conf;
4913 struct ixgbe_adapter *adapter =
4914 (struct ixgbe_adapter *)dev->data->dev_private;
4916 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4917 dev->data->port_id);
4920 * VF has no ability to enable/disable HW CRC
4921 * Keep the persistent behavior the same as Host PF
4923 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4924 if (!conf->rxmode.hw_strip_crc) {
4925 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4926 conf->rxmode.hw_strip_crc = 1;
4929 if (conf->rxmode.hw_strip_crc) {
4930 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4931 conf->rxmode.hw_strip_crc = 0;
4936 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4937 * allocation or vector Rx preconditions we will reset it.
4939 adapter->rx_bulk_alloc_allowed = true;
4940 adapter->rx_vec_allowed = true;
4946 ixgbevf_dev_start(struct rte_eth_dev *dev)
4948 struct ixgbe_hw *hw =
4949 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4950 uint32_t intr_vector = 0;
4951 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4952 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4956 PMD_INIT_FUNC_TRACE();
4958 err = hw->mac.ops.reset_hw(hw);
4960 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
4963 hw->mac.get_link_status = true;
4965 /* negotiate mailbox API version to use with the PF. */
4966 ixgbevf_negotiate_api(hw);
4968 ixgbevf_dev_tx_init(dev);
4970 /* This can fail when allocating mbufs for descriptor rings */
4971 err = ixgbevf_dev_rx_init(dev);
4973 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4974 ixgbe_dev_clear_queues(dev);
4979 ixgbevf_set_vfta_all(dev, 1);
4982 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4983 ETH_VLAN_EXTEND_MASK;
4984 err = ixgbevf_vlan_offload_set(dev, mask);
4986 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
4987 ixgbe_dev_clear_queues(dev);
4991 ixgbevf_dev_rxtx_start(dev);
4993 /* check and configure queue intr-vector mapping */
4994 if (rte_intr_cap_multiple(intr_handle) &&
4995 dev->data->dev_conf.intr_conf.rxq) {
4996 /* According to datasheet, only vector 0/1/2 can be used,
4997 * now only one vector is used for Rx queue
5000 if (rte_intr_efd_enable(intr_handle, intr_vector))
5004 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5005 intr_handle->intr_vec =
5006 rte_zmalloc("intr_vec",
5007 dev->data->nb_rx_queues * sizeof(int), 0);
5008 if (intr_handle->intr_vec == NULL) {
5009 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5010 " intr_vec", dev->data->nb_rx_queues);
5014 ixgbevf_configure_msix(dev);
5016 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5017 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5018 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5019 * is not cleared, it will fail when following rte_intr_enable( ) tries
5020 * to map Rx queue interrupt to other VFIO vectors.
5021 * So clear uio/vfio intr/evevnfd first to avoid failure.
5023 rte_intr_disable(intr_handle);
5025 rte_intr_enable(intr_handle);
5027 /* Re-enable interrupt for VF */
5028 ixgbevf_intr_enable(hw);
5034 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5036 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5037 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5038 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5040 PMD_INIT_FUNC_TRACE();
5042 ixgbevf_intr_disable(hw);
5044 hw->adapter_stopped = 1;
5045 ixgbe_stop_adapter(hw);
5048 * Clear what we set, but we still keep shadow_vfta to
5049 * restore after device starts
5051 ixgbevf_set_vfta_all(dev, 0);
5053 /* Clear stored conf */
5054 dev->data->scattered_rx = 0;
5056 ixgbe_dev_clear_queues(dev);
5058 /* Clean datapath event and queue/vec mapping */
5059 rte_intr_efd_disable(intr_handle);
5060 if (intr_handle->intr_vec != NULL) {
5061 rte_free(intr_handle->intr_vec);
5062 intr_handle->intr_vec = NULL;
5067 ixgbevf_dev_close(struct rte_eth_dev *dev)
5069 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5071 PMD_INIT_FUNC_TRACE();
5075 ixgbevf_dev_stop(dev);
5077 ixgbe_dev_free_queues(dev);
5080 * Remove the VF MAC address ro ensure
5081 * that the VF traffic goes to the PF
5082 * after stop, close and detach of the VF
5084 ixgbevf_remove_mac_addr(dev, 0);
5091 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5095 ret = eth_ixgbevf_dev_uninit(dev);
5099 ret = eth_ixgbevf_dev_init(dev);
5104 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5106 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5107 struct ixgbe_vfta *shadow_vfta =
5108 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5109 int i = 0, j = 0, vfta = 0, mask = 1;
5111 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5112 vfta = shadow_vfta->vfta[i];
5115 for (j = 0; j < 32; j++) {
5117 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5127 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5129 struct ixgbe_hw *hw =
5130 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5131 struct ixgbe_vfta *shadow_vfta =
5132 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5133 uint32_t vid_idx = 0;
5134 uint32_t vid_bit = 0;
5137 PMD_INIT_FUNC_TRACE();
5139 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5140 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5142 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5145 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5146 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5148 /* Save what we set and retore it after device reset */
5150 shadow_vfta->vfta[vid_idx] |= vid_bit;
5152 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5158 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5160 struct ixgbe_hw *hw =
5161 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5164 PMD_INIT_FUNC_TRACE();
5166 if (queue >= hw->mac.max_rx_queues)
5169 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5171 ctrl |= IXGBE_RXDCTL_VME;
5173 ctrl &= ~IXGBE_RXDCTL_VME;
5174 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5176 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5180 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5182 struct ixgbe_hw *hw =
5183 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5187 /* VF function only support hw strip feature, others are not support */
5188 if (mask & ETH_VLAN_STRIP_MASK) {
5189 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5191 for (i = 0; i < hw->mac.max_rx_queues; i++)
5192 ixgbevf_vlan_strip_queue_set(dev, i, on);
5199 ixgbe_vt_check(struct ixgbe_hw *hw)
5203 /* if Virtualization Technology is enabled */
5204 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5205 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5206 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5214 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5216 uint32_t vector = 0;
5218 switch (hw->mac.mc_filter_type) {
5219 case 0: /* use bits [47:36] of the address */
5220 vector = ((uc_addr->addr_bytes[4] >> 4) |
5221 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5223 case 1: /* use bits [46:35] of the address */
5224 vector = ((uc_addr->addr_bytes[4] >> 3) |
5225 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5227 case 2: /* use bits [45:34] of the address */
5228 vector = ((uc_addr->addr_bytes[4] >> 2) |
5229 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5231 case 3: /* use bits [43:32] of the address */
5232 vector = ((uc_addr->addr_bytes[4]) |
5233 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5235 default: /* Invalid mc_filter_type */
5239 /* vector can only be 12-bits or boundary will be exceeded */
5245 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5253 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5254 const uint32_t ixgbe_uta_bit_shift = 5;
5255 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5256 const uint32_t bit1 = 0x1;
5258 struct ixgbe_hw *hw =
5259 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5260 struct ixgbe_uta_info *uta_info =
5261 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5263 /* The UTA table only exists on 82599 hardware and newer */
5264 if (hw->mac.type < ixgbe_mac_82599EB)
5267 vector = ixgbe_uta_vector(hw, mac_addr);
5268 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5269 uta_shift = vector & ixgbe_uta_bit_mask;
5271 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5275 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5277 uta_info->uta_in_use++;
5278 reg_val |= (bit1 << uta_shift);
5279 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5281 uta_info->uta_in_use--;
5282 reg_val &= ~(bit1 << uta_shift);
5283 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5286 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5288 if (uta_info->uta_in_use > 0)
5289 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5290 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5292 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5298 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5301 struct ixgbe_hw *hw =
5302 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5303 struct ixgbe_uta_info *uta_info =
5304 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5306 /* The UTA table only exists on 82599 hardware and newer */
5307 if (hw->mac.type < ixgbe_mac_82599EB)
5311 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5312 uta_info->uta_shadow[i] = ~0;
5313 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5316 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5317 uta_info->uta_shadow[i] = 0;
5318 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5326 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5328 uint32_t new_val = orig_val;
5330 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5331 new_val |= IXGBE_VMOLR_AUPE;
5332 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5333 new_val |= IXGBE_VMOLR_ROMPE;
5334 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5335 new_val |= IXGBE_VMOLR_ROPE;
5336 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5337 new_val |= IXGBE_VMOLR_BAM;
5338 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5339 new_val |= IXGBE_VMOLR_MPE;
5344 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5345 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5346 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5347 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5348 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5349 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5350 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5353 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5354 struct rte_eth_mirror_conf *mirror_conf,
5355 uint8_t rule_id, uint8_t on)
5357 uint32_t mr_ctl, vlvf;
5358 uint32_t mp_lsb = 0;
5359 uint32_t mv_msb = 0;
5360 uint32_t mv_lsb = 0;
5361 uint32_t mp_msb = 0;
5364 uint64_t vlan_mask = 0;
5366 const uint8_t pool_mask_offset = 32;
5367 const uint8_t vlan_mask_offset = 32;
5368 const uint8_t dst_pool_offset = 8;
5369 const uint8_t rule_mr_offset = 4;
5370 const uint8_t mirror_rule_mask = 0x0F;
5372 struct ixgbe_mirror_info *mr_info =
5373 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5374 struct ixgbe_hw *hw =
5375 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5376 uint8_t mirror_type = 0;
5378 if (ixgbe_vt_check(hw) < 0)
5381 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5384 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5385 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5386 mirror_conf->rule_type);
5390 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5391 mirror_type |= IXGBE_MRCTL_VLME;
5392 /* Check if vlan id is valid and find conresponding VLAN ID
5395 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5396 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5397 /* search vlan id related pool vlan filter
5400 reg_index = ixgbe_find_vlvf_slot(
5402 mirror_conf->vlan.vlan_id[i],
5406 vlvf = IXGBE_READ_REG(hw,
5407 IXGBE_VLVF(reg_index));
5408 if ((vlvf & IXGBE_VLVF_VIEN) &&
5409 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5410 mirror_conf->vlan.vlan_id[i]))
5411 vlan_mask |= (1ULL << reg_index);
5418 mv_lsb = vlan_mask & 0xFFFFFFFF;
5419 mv_msb = vlan_mask >> vlan_mask_offset;
5421 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5422 mirror_conf->vlan.vlan_mask;
5423 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5424 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5425 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5426 mirror_conf->vlan.vlan_id[i];
5431 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5432 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5433 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5438 * if enable pool mirror, write related pool mask register,if disable
5439 * pool mirror, clear PFMRVM register
5441 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5442 mirror_type |= IXGBE_MRCTL_VPME;
5444 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5445 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5446 mr_info->mr_conf[rule_id].pool_mask =
5447 mirror_conf->pool_mask;
5452 mr_info->mr_conf[rule_id].pool_mask = 0;
5455 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5456 mirror_type |= IXGBE_MRCTL_UPME;
5457 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5458 mirror_type |= IXGBE_MRCTL_DPME;
5460 /* read mirror control register and recalculate it */
5461 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5464 mr_ctl |= mirror_type;
5465 mr_ctl &= mirror_rule_mask;
5466 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5468 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5471 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5472 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5474 /* write mirrror control register */
5475 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5477 /* write pool mirrror control register */
5478 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5479 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5480 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5483 /* write VLAN mirrror control register */
5484 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5485 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5486 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5494 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5497 uint32_t lsb_val = 0;
5498 uint32_t msb_val = 0;
5499 const uint8_t rule_mr_offset = 4;
5501 struct ixgbe_hw *hw =
5502 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5503 struct ixgbe_mirror_info *mr_info =
5504 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5506 if (ixgbe_vt_check(hw) < 0)
5509 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5512 memset(&mr_info->mr_conf[rule_id], 0,
5513 sizeof(struct rte_eth_mirror_conf));
5515 /* clear PFVMCTL register */
5516 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5518 /* clear pool mask register */
5519 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5520 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5522 /* clear vlan mask register */
5523 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5524 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5530 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5532 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5533 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5535 struct ixgbe_hw *hw =
5536 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5537 uint32_t vec = IXGBE_MISC_VEC_ID;
5539 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5540 if (rte_intr_allow_others(intr_handle))
5541 vec = IXGBE_RX_VEC_START;
5543 RTE_SET_USED(queue_id);
5544 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5546 rte_intr_enable(intr_handle);
5552 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5555 struct ixgbe_hw *hw =
5556 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5557 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5558 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5559 uint32_t vec = IXGBE_MISC_VEC_ID;
5561 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5562 if (rte_intr_allow_others(intr_handle))
5563 vec = IXGBE_RX_VEC_START;
5564 mask &= ~(1 << vec);
5565 RTE_SET_USED(queue_id);
5566 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5572 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5574 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5575 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5577 struct ixgbe_hw *hw =
5578 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5579 struct ixgbe_interrupt *intr =
5580 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5582 if (queue_id < 16) {
5583 ixgbe_disable_intr(hw);
5584 intr->mask |= (1 << queue_id);
5585 ixgbe_enable_intr(dev);
5586 } else if (queue_id < 32) {
5587 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5588 mask &= (1 << queue_id);
5589 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5590 } else if (queue_id < 64) {
5591 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5592 mask &= (1 << (queue_id - 32));
5593 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5595 rte_intr_enable(intr_handle);
5601 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5604 struct ixgbe_hw *hw =
5605 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5606 struct ixgbe_interrupt *intr =
5607 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5609 if (queue_id < 16) {
5610 ixgbe_disable_intr(hw);
5611 intr->mask &= ~(1 << queue_id);
5612 ixgbe_enable_intr(dev);
5613 } else if (queue_id < 32) {
5614 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5615 mask &= ~(1 << queue_id);
5616 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5617 } else if (queue_id < 64) {
5618 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5619 mask &= ~(1 << (queue_id - 32));
5620 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5627 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5628 uint8_t queue, uint8_t msix_vector)
5632 if (direction == -1) {
5634 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5635 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5638 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5640 /* rx or tx cause */
5641 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5642 idx = ((16 * (queue & 1)) + (8 * direction));
5643 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5644 tmp &= ~(0xFF << idx);
5645 tmp |= (msix_vector << idx);
5646 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5651 * set the IVAR registers, mapping interrupt causes to vectors
5653 * pointer to ixgbe_hw struct
5655 * 0 for Rx, 1 for Tx, -1 for other causes
5657 * queue to map the corresponding interrupt to
5659 * the vector to map to the corresponding queue
5662 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5663 uint8_t queue, uint8_t msix_vector)
5667 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5668 if (hw->mac.type == ixgbe_mac_82598EB) {
5669 if (direction == -1)
5671 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5672 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5673 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5674 tmp |= (msix_vector << (8 * (queue & 0x3)));
5675 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5676 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5677 (hw->mac.type == ixgbe_mac_X540) ||
5678 (hw->mac.type == ixgbe_mac_X550)) {
5679 if (direction == -1) {
5681 idx = ((queue & 1) * 8);
5682 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5683 tmp &= ~(0xFF << idx);
5684 tmp |= (msix_vector << idx);
5685 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5687 /* rx or tx causes */
5688 idx = ((16 * (queue & 1)) + (8 * direction));
5689 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5690 tmp &= ~(0xFF << idx);
5691 tmp |= (msix_vector << idx);
5692 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5698 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5700 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5701 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5702 struct ixgbe_hw *hw =
5703 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5705 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5706 uint32_t base = IXGBE_MISC_VEC_ID;
5708 /* Configure VF other cause ivar */
5709 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5711 /* won't configure msix register if no mapping is done
5712 * between intr vector and event fd.
5714 if (!rte_intr_dp_is_en(intr_handle))
5717 if (rte_intr_allow_others(intr_handle)) {
5718 base = IXGBE_RX_VEC_START;
5719 vector_idx = IXGBE_RX_VEC_START;
5722 /* Configure all RX queues of VF */
5723 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5724 /* Force all queue use vector 0,
5725 * as IXGBE_VF_MAXMSIVECOTR = 1
5727 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5728 intr_handle->intr_vec[q_idx] = vector_idx;
5729 if (vector_idx < base + intr_handle->nb_efd - 1)
5735 * Sets up the hardware to properly generate MSI-X interrupts
5737 * board private structure
5740 ixgbe_configure_msix(struct rte_eth_dev *dev)
5742 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5743 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5744 struct ixgbe_hw *hw =
5745 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5746 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5747 uint32_t vec = IXGBE_MISC_VEC_ID;
5751 /* won't configure msix register if no mapping is done
5752 * between intr vector and event fd
5754 if (!rte_intr_dp_is_en(intr_handle))
5757 if (rte_intr_allow_others(intr_handle))
5758 vec = base = IXGBE_RX_VEC_START;
5760 /* setup GPIE for MSI-x mode */
5761 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5762 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5763 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5764 /* auto clearing and auto setting corresponding bits in EIMS
5765 * when MSI-X interrupt is triggered
5767 if (hw->mac.type == ixgbe_mac_82598EB) {
5768 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5770 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5771 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5773 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5775 /* Populate the IVAR table and set the ITR values to the
5776 * corresponding register.
5778 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5780 /* by default, 1:1 mapping */
5781 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5782 intr_handle->intr_vec[queue_id] = vec;
5783 if (vec < base + intr_handle->nb_efd - 1)
5787 switch (hw->mac.type) {
5788 case ixgbe_mac_82598EB:
5789 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5792 case ixgbe_mac_82599EB:
5793 case ixgbe_mac_X540:
5794 case ixgbe_mac_X550:
5795 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5800 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5801 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5803 /* set up to autoclear timer, and the vectors */
5804 mask = IXGBE_EIMS_ENABLE_MASK;
5805 mask &= ~(IXGBE_EIMS_OTHER |
5806 IXGBE_EIMS_MAILBOX |
5809 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5813 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5814 uint16_t queue_idx, uint16_t tx_rate)
5816 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5817 uint32_t rf_dec, rf_int;
5819 uint16_t link_speed = dev->data->dev_link.link_speed;
5821 if (queue_idx >= hw->mac.max_tx_queues)
5825 /* Calculate the rate factor values to set */
5826 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5827 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5828 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5830 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5831 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5832 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5833 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5839 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5840 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5843 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5844 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5845 IXGBE_MAX_JUMBO_FRAME_SIZE))
5846 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5847 IXGBE_MMW_SIZE_JUMBO_FRAME);
5849 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5850 IXGBE_MMW_SIZE_DEFAULT);
5852 /* Set RTTBCNRC of queue X */
5853 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5854 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5855 IXGBE_WRITE_FLUSH(hw);
5861 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5862 __attribute__((unused)) uint32_t index,
5863 __attribute__((unused)) uint32_t pool)
5865 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5869 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5870 * operation. Trap this case to avoid exhausting the [very limited]
5871 * set of PF resources used to store VF MAC addresses.
5873 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5875 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5877 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5878 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5879 mac_addr->addr_bytes[0],
5880 mac_addr->addr_bytes[1],
5881 mac_addr->addr_bytes[2],
5882 mac_addr->addr_bytes[3],
5883 mac_addr->addr_bytes[4],
5884 mac_addr->addr_bytes[5],
5890 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5892 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5893 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5894 struct ether_addr *mac_addr;
5899 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5900 * not support the deletion of a given MAC address.
5901 * Instead, it imposes to delete all MAC addresses, then to add again
5902 * all MAC addresses with the exception of the one to be deleted.
5904 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5907 * Add again all MAC addresses, with the exception of the deleted one
5908 * and of the permanent MAC address.
5910 for (i = 0, mac_addr = dev->data->mac_addrs;
5911 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5912 /* Skip the deleted MAC address */
5915 /* Skip NULL MAC addresses */
5916 if (is_zero_ether_addr(mac_addr))
5918 /* Skip the permanent MAC address */
5919 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5921 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5924 "Adding again MAC address "
5925 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5927 mac_addr->addr_bytes[0],
5928 mac_addr->addr_bytes[1],
5929 mac_addr->addr_bytes[2],
5930 mac_addr->addr_bytes[3],
5931 mac_addr->addr_bytes[4],
5932 mac_addr->addr_bytes[5],
5938 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5940 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5942 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5946 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5947 struct rte_eth_syn_filter *filter,
5950 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5951 struct ixgbe_filter_info *filter_info =
5952 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5956 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5959 syn_info = filter_info->syn_info;
5962 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5964 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5965 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5967 if (filter->hig_pri)
5968 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5970 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5972 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5973 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5975 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5978 filter_info->syn_info = synqf;
5979 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5980 IXGBE_WRITE_FLUSH(hw);
5985 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5986 struct rte_eth_syn_filter *filter)
5988 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5989 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5991 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5992 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5993 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6000 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6001 enum rte_filter_op filter_op,
6004 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6007 MAC_TYPE_FILTER_SUP(hw->mac.type);
6009 if (filter_op == RTE_ETH_FILTER_NOP)
6013 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6018 switch (filter_op) {
6019 case RTE_ETH_FILTER_ADD:
6020 ret = ixgbe_syn_filter_set(dev,
6021 (struct rte_eth_syn_filter *)arg,
6024 case RTE_ETH_FILTER_DELETE:
6025 ret = ixgbe_syn_filter_set(dev,
6026 (struct rte_eth_syn_filter *)arg,
6029 case RTE_ETH_FILTER_GET:
6030 ret = ixgbe_syn_filter_get(dev,
6031 (struct rte_eth_syn_filter *)arg);
6034 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6043 static inline enum ixgbe_5tuple_protocol
6044 convert_protocol_type(uint8_t protocol_value)
6046 if (protocol_value == IPPROTO_TCP)
6047 return IXGBE_FILTER_PROTOCOL_TCP;
6048 else if (protocol_value == IPPROTO_UDP)
6049 return IXGBE_FILTER_PROTOCOL_UDP;
6050 else if (protocol_value == IPPROTO_SCTP)
6051 return IXGBE_FILTER_PROTOCOL_SCTP;
6053 return IXGBE_FILTER_PROTOCOL_NONE;
6056 /* inject a 5-tuple filter to HW */
6058 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6059 struct ixgbe_5tuple_filter *filter)
6061 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6063 uint32_t ftqf, sdpqf;
6064 uint32_t l34timir = 0;
6065 uint8_t mask = 0xff;
6069 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6070 IXGBE_SDPQF_DSTPORT_SHIFT);
6071 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6073 ftqf = (uint32_t)(filter->filter_info.proto &
6074 IXGBE_FTQF_PROTOCOL_MASK);
6075 ftqf |= (uint32_t)((filter->filter_info.priority &
6076 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6077 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6078 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6079 if (filter->filter_info.dst_ip_mask == 0)
6080 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6081 if (filter->filter_info.src_port_mask == 0)
6082 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6083 if (filter->filter_info.dst_port_mask == 0)
6084 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6085 if (filter->filter_info.proto_mask == 0)
6086 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6087 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6088 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6089 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6091 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6092 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6093 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6094 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6096 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6097 l34timir |= (uint32_t)(filter->queue <<
6098 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6099 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6103 * add a 5tuple filter
6106 * dev: Pointer to struct rte_eth_dev.
6107 * index: the index the filter allocates.
6108 * filter: ponter to the filter that will be added.
6109 * rx_queue: the queue id the filter assigned to.
6112 * - On success, zero.
6113 * - On failure, a negative value.
6116 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6117 struct ixgbe_5tuple_filter *filter)
6119 struct ixgbe_filter_info *filter_info =
6120 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6124 * look for an unused 5tuple filter index,
6125 * and insert the filter to list.
6127 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6128 idx = i / (sizeof(uint32_t) * NBBY);
6129 shift = i % (sizeof(uint32_t) * NBBY);
6130 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6131 filter_info->fivetuple_mask[idx] |= 1 << shift;
6133 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6139 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6140 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6144 ixgbe_inject_5tuple_filter(dev, filter);
6150 * remove a 5tuple filter
6153 * dev: Pointer to struct rte_eth_dev.
6154 * filter: the pointer of the filter will be removed.
6157 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6158 struct ixgbe_5tuple_filter *filter)
6160 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6161 struct ixgbe_filter_info *filter_info =
6162 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6163 uint16_t index = filter->index;
6165 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6166 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6167 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6170 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6171 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6172 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6173 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6174 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6178 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6180 struct ixgbe_hw *hw;
6181 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6182 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6184 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6186 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6189 /* refuse mtu that requires the support of scattered packets when this
6190 * feature has not been enabled before.
6192 if (!rx_conf->enable_scatter &&
6193 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6194 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6198 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6199 * request of the version 2.0 of the mailbox API.
6200 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6201 * of the mailbox API.
6202 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6203 * prior to 3.11.33 which contains the following change:
6204 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6206 ixgbevf_rlpml_set_vf(hw, max_frame);
6208 /* update max frame size */
6209 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6213 static inline struct ixgbe_5tuple_filter *
6214 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6215 struct ixgbe_5tuple_filter_info *key)
6217 struct ixgbe_5tuple_filter *it;
6219 TAILQ_FOREACH(it, filter_list, entries) {
6220 if (memcmp(key, &it->filter_info,
6221 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6228 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6230 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6231 struct ixgbe_5tuple_filter_info *filter_info)
6233 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6234 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6235 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6238 switch (filter->dst_ip_mask) {
6240 filter_info->dst_ip_mask = 0;
6241 filter_info->dst_ip = filter->dst_ip;
6244 filter_info->dst_ip_mask = 1;
6247 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6251 switch (filter->src_ip_mask) {
6253 filter_info->src_ip_mask = 0;
6254 filter_info->src_ip = filter->src_ip;
6257 filter_info->src_ip_mask = 1;
6260 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6264 switch (filter->dst_port_mask) {
6266 filter_info->dst_port_mask = 0;
6267 filter_info->dst_port = filter->dst_port;
6270 filter_info->dst_port_mask = 1;
6273 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6277 switch (filter->src_port_mask) {
6279 filter_info->src_port_mask = 0;
6280 filter_info->src_port = filter->src_port;
6283 filter_info->src_port_mask = 1;
6286 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6290 switch (filter->proto_mask) {
6292 filter_info->proto_mask = 0;
6293 filter_info->proto =
6294 convert_protocol_type(filter->proto);
6297 filter_info->proto_mask = 1;
6300 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6304 filter_info->priority = (uint8_t)filter->priority;
6309 * add or delete a ntuple filter
6312 * dev: Pointer to struct rte_eth_dev.
6313 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6314 * add: if true, add filter, if false, remove filter
6317 * - On success, zero.
6318 * - On failure, a negative value.
6321 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6322 struct rte_eth_ntuple_filter *ntuple_filter,
6325 struct ixgbe_filter_info *filter_info =
6326 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6327 struct ixgbe_5tuple_filter_info filter_5tuple;
6328 struct ixgbe_5tuple_filter *filter;
6331 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6332 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6336 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6337 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6341 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6343 if (filter != NULL && add) {
6344 PMD_DRV_LOG(ERR, "filter exists.");
6347 if (filter == NULL && !add) {
6348 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6353 filter = rte_zmalloc("ixgbe_5tuple_filter",
6354 sizeof(struct ixgbe_5tuple_filter), 0);
6357 rte_memcpy(&filter->filter_info,
6359 sizeof(struct ixgbe_5tuple_filter_info));
6360 filter->queue = ntuple_filter->queue;
6361 ret = ixgbe_add_5tuple_filter(dev, filter);
6367 ixgbe_remove_5tuple_filter(dev, filter);
6373 * get a ntuple filter
6376 * dev: Pointer to struct rte_eth_dev.
6377 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6380 * - On success, zero.
6381 * - On failure, a negative value.
6384 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6385 struct rte_eth_ntuple_filter *ntuple_filter)
6387 struct ixgbe_filter_info *filter_info =
6388 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6389 struct ixgbe_5tuple_filter_info filter_5tuple;
6390 struct ixgbe_5tuple_filter *filter;
6393 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6394 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6398 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6399 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6403 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6405 if (filter == NULL) {
6406 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6409 ntuple_filter->queue = filter->queue;
6414 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6415 * @dev: pointer to rte_eth_dev structure
6416 * @filter_op:operation will be taken.
6417 * @arg: a pointer to specific structure corresponding to the filter_op
6420 * - On success, zero.
6421 * - On failure, a negative value.
6424 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6425 enum rte_filter_op filter_op,
6428 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6431 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6433 if (filter_op == RTE_ETH_FILTER_NOP)
6437 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6442 switch (filter_op) {
6443 case RTE_ETH_FILTER_ADD:
6444 ret = ixgbe_add_del_ntuple_filter(dev,
6445 (struct rte_eth_ntuple_filter *)arg,
6448 case RTE_ETH_FILTER_DELETE:
6449 ret = ixgbe_add_del_ntuple_filter(dev,
6450 (struct rte_eth_ntuple_filter *)arg,
6453 case RTE_ETH_FILTER_GET:
6454 ret = ixgbe_get_ntuple_filter(dev,
6455 (struct rte_eth_ntuple_filter *)arg);
6458 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6466 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6467 struct rte_eth_ethertype_filter *filter,
6470 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6471 struct ixgbe_filter_info *filter_info =
6472 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6476 struct ixgbe_ethertype_filter ethertype_filter;
6478 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6481 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6482 filter->ether_type == ETHER_TYPE_IPv6) {
6483 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6484 " ethertype filter.", filter->ether_type);
6488 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6489 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6492 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6493 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6497 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6498 if (ret >= 0 && add) {
6499 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6500 filter->ether_type);
6503 if (ret < 0 && !add) {
6504 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6505 filter->ether_type);
6510 etqf = IXGBE_ETQF_FILTER_EN;
6511 etqf |= (uint32_t)filter->ether_type;
6512 etqs |= (uint32_t)((filter->queue <<
6513 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6514 IXGBE_ETQS_RX_QUEUE);
6515 etqs |= IXGBE_ETQS_QUEUE_EN;
6517 ethertype_filter.ethertype = filter->ether_type;
6518 ethertype_filter.etqf = etqf;
6519 ethertype_filter.etqs = etqs;
6520 ethertype_filter.conf = FALSE;
6521 ret = ixgbe_ethertype_filter_insert(filter_info,
6524 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6528 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6532 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6533 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6534 IXGBE_WRITE_FLUSH(hw);
6540 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6541 struct rte_eth_ethertype_filter *filter)
6543 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6544 struct ixgbe_filter_info *filter_info =
6545 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6546 uint32_t etqf, etqs;
6549 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6551 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6552 filter->ether_type);
6556 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6557 if (etqf & IXGBE_ETQF_FILTER_EN) {
6558 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6559 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6561 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6562 IXGBE_ETQS_RX_QUEUE_SHIFT;
6569 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6570 * @dev: pointer to rte_eth_dev structure
6571 * @filter_op:operation will be taken.
6572 * @arg: a pointer to specific structure corresponding to the filter_op
6575 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6576 enum rte_filter_op filter_op,
6579 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6582 MAC_TYPE_FILTER_SUP(hw->mac.type);
6584 if (filter_op == RTE_ETH_FILTER_NOP)
6588 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6593 switch (filter_op) {
6594 case RTE_ETH_FILTER_ADD:
6595 ret = ixgbe_add_del_ethertype_filter(dev,
6596 (struct rte_eth_ethertype_filter *)arg,
6599 case RTE_ETH_FILTER_DELETE:
6600 ret = ixgbe_add_del_ethertype_filter(dev,
6601 (struct rte_eth_ethertype_filter *)arg,
6604 case RTE_ETH_FILTER_GET:
6605 ret = ixgbe_get_ethertype_filter(dev,
6606 (struct rte_eth_ethertype_filter *)arg);
6609 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6617 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6618 enum rte_filter_type filter_type,
6619 enum rte_filter_op filter_op,
6624 switch (filter_type) {
6625 case RTE_ETH_FILTER_NTUPLE:
6626 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6628 case RTE_ETH_FILTER_ETHERTYPE:
6629 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6631 case RTE_ETH_FILTER_SYN:
6632 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6634 case RTE_ETH_FILTER_FDIR:
6635 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6637 case RTE_ETH_FILTER_L2_TUNNEL:
6638 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6640 case RTE_ETH_FILTER_GENERIC:
6641 if (filter_op != RTE_ETH_FILTER_GET)
6643 *(const void **)arg = &ixgbe_flow_ops;
6646 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6656 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6657 u8 **mc_addr_ptr, u32 *vmdq)
6662 mc_addr = *mc_addr_ptr;
6663 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6668 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6669 struct ether_addr *mc_addr_set,
6670 uint32_t nb_mc_addr)
6672 struct ixgbe_hw *hw;
6675 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6676 mc_addr_list = (u8 *)mc_addr_set;
6677 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6678 ixgbe_dev_addr_list_itr, TRUE);
6682 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6684 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6685 uint64_t systime_cycles;
6687 switch (hw->mac.type) {
6688 case ixgbe_mac_X550:
6689 case ixgbe_mac_X550EM_x:
6690 case ixgbe_mac_X550EM_a:
6691 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6692 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6693 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6697 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6698 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6702 return systime_cycles;
6706 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6708 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6709 uint64_t rx_tstamp_cycles;
6711 switch (hw->mac.type) {
6712 case ixgbe_mac_X550:
6713 case ixgbe_mac_X550EM_x:
6714 case ixgbe_mac_X550EM_a:
6715 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6716 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6717 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6721 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6722 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6723 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6727 return rx_tstamp_cycles;
6731 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6733 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6734 uint64_t tx_tstamp_cycles;
6736 switch (hw->mac.type) {
6737 case ixgbe_mac_X550:
6738 case ixgbe_mac_X550EM_x:
6739 case ixgbe_mac_X550EM_a:
6740 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6741 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6742 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6746 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6747 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6748 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6752 return tx_tstamp_cycles;
6756 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6758 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6759 struct ixgbe_adapter *adapter =
6760 (struct ixgbe_adapter *)dev->data->dev_private;
6761 struct rte_eth_link link;
6762 uint32_t incval = 0;
6765 /* Get current link speed. */
6766 ixgbe_dev_link_update(dev, 1);
6767 rte_eth_linkstatus_get(dev, &link);
6769 switch (link.link_speed) {
6770 case ETH_SPEED_NUM_100M:
6771 incval = IXGBE_INCVAL_100;
6772 shift = IXGBE_INCVAL_SHIFT_100;
6774 case ETH_SPEED_NUM_1G:
6775 incval = IXGBE_INCVAL_1GB;
6776 shift = IXGBE_INCVAL_SHIFT_1GB;
6778 case ETH_SPEED_NUM_10G:
6780 incval = IXGBE_INCVAL_10GB;
6781 shift = IXGBE_INCVAL_SHIFT_10GB;
6785 switch (hw->mac.type) {
6786 case ixgbe_mac_X550:
6787 case ixgbe_mac_X550EM_x:
6788 case ixgbe_mac_X550EM_a:
6789 /* Independent of link speed. */
6791 /* Cycles read will be interpreted as ns. */
6794 case ixgbe_mac_X540:
6795 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6797 case ixgbe_mac_82599EB:
6798 incval >>= IXGBE_INCVAL_SHIFT_82599;
6799 shift -= IXGBE_INCVAL_SHIFT_82599;
6800 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6801 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6804 /* Not supported. */
6808 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6809 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6810 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6812 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6813 adapter->systime_tc.cc_shift = shift;
6814 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6816 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6817 adapter->rx_tstamp_tc.cc_shift = shift;
6818 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6820 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6821 adapter->tx_tstamp_tc.cc_shift = shift;
6822 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6826 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6828 struct ixgbe_adapter *adapter =
6829 (struct ixgbe_adapter *)dev->data->dev_private;
6831 adapter->systime_tc.nsec += delta;
6832 adapter->rx_tstamp_tc.nsec += delta;
6833 adapter->tx_tstamp_tc.nsec += delta;
6839 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6842 struct ixgbe_adapter *adapter =
6843 (struct ixgbe_adapter *)dev->data->dev_private;
6845 ns = rte_timespec_to_ns(ts);
6846 /* Set the timecounters to a new value. */
6847 adapter->systime_tc.nsec = ns;
6848 adapter->rx_tstamp_tc.nsec = ns;
6849 adapter->tx_tstamp_tc.nsec = ns;
6855 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6857 uint64_t ns, systime_cycles;
6858 struct ixgbe_adapter *adapter =
6859 (struct ixgbe_adapter *)dev->data->dev_private;
6861 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6862 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6863 *ts = rte_ns_to_timespec(ns);
6869 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6871 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6875 /* Stop the timesync system time. */
6876 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6877 /* Reset the timesync system time value. */
6878 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6879 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6881 /* Enable system time for platforms where it isn't on by default. */
6882 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6883 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6884 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6886 ixgbe_start_timecounters(dev);
6888 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6889 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6891 IXGBE_ETQF_FILTER_EN |
6894 /* Enable timestamping of received PTP packets. */
6895 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6896 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6897 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6899 /* Enable timestamping of transmitted PTP packets. */
6900 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6901 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6902 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6904 IXGBE_WRITE_FLUSH(hw);
6910 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6912 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6915 /* Disable timestamping of transmitted PTP packets. */
6916 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6917 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6918 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6920 /* Disable timestamping of received PTP packets. */
6921 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6922 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6923 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6925 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6926 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6928 /* Stop incrementating the System Time registers. */
6929 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6935 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6936 struct timespec *timestamp,
6937 uint32_t flags __rte_unused)
6939 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6940 struct ixgbe_adapter *adapter =
6941 (struct ixgbe_adapter *)dev->data->dev_private;
6942 uint32_t tsync_rxctl;
6943 uint64_t rx_tstamp_cycles;
6946 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6947 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6950 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6951 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6952 *timestamp = rte_ns_to_timespec(ns);
6958 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6959 struct timespec *timestamp)
6961 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6962 struct ixgbe_adapter *adapter =
6963 (struct ixgbe_adapter *)dev->data->dev_private;
6964 uint32_t tsync_txctl;
6965 uint64_t tx_tstamp_cycles;
6968 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6969 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6972 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6973 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6974 *timestamp = rte_ns_to_timespec(ns);
6980 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6982 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6985 const struct reg_info *reg_group;
6986 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6987 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6989 while ((reg_group = reg_set[g_ind++]))
6990 count += ixgbe_regs_group_count(reg_group);
6996 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7000 const struct reg_info *reg_group;
7002 while ((reg_group = ixgbevf_regs[g_ind++]))
7003 count += ixgbe_regs_group_count(reg_group);
7009 ixgbe_get_regs(struct rte_eth_dev *dev,
7010 struct rte_dev_reg_info *regs)
7012 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7013 uint32_t *data = regs->data;
7016 const struct reg_info *reg_group;
7017 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7018 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7021 regs->length = ixgbe_get_reg_length(dev);
7022 regs->width = sizeof(uint32_t);
7026 /* Support only full register dump */
7027 if ((regs->length == 0) ||
7028 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7029 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7031 while ((reg_group = reg_set[g_ind++]))
7032 count += ixgbe_read_regs_group(dev, &data[count],
7041 ixgbevf_get_regs(struct rte_eth_dev *dev,
7042 struct rte_dev_reg_info *regs)
7044 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7045 uint32_t *data = regs->data;
7048 const struct reg_info *reg_group;
7051 regs->length = ixgbevf_get_reg_length(dev);
7052 regs->width = sizeof(uint32_t);
7056 /* Support only full register dump */
7057 if ((regs->length == 0) ||
7058 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7059 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7061 while ((reg_group = ixgbevf_regs[g_ind++]))
7062 count += ixgbe_read_regs_group(dev, &data[count],
7071 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7073 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7075 /* Return unit is byte count */
7076 return hw->eeprom.word_size * 2;
7080 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7081 struct rte_dev_eeprom_info *in_eeprom)
7083 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7084 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7085 uint16_t *data = in_eeprom->data;
7088 first = in_eeprom->offset >> 1;
7089 length = in_eeprom->length >> 1;
7090 if ((first > hw->eeprom.word_size) ||
7091 ((first + length) > hw->eeprom.word_size))
7094 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7096 return eeprom->ops.read_buffer(hw, first, length, data);
7100 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7101 struct rte_dev_eeprom_info *in_eeprom)
7103 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7104 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7105 uint16_t *data = in_eeprom->data;
7108 first = in_eeprom->offset >> 1;
7109 length = in_eeprom->length >> 1;
7110 if ((first > hw->eeprom.word_size) ||
7111 ((first + length) > hw->eeprom.word_size))
7114 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7116 return eeprom->ops.write_buffer(hw, first, length, data);
7120 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7122 case ixgbe_mac_X550:
7123 case ixgbe_mac_X550EM_x:
7124 case ixgbe_mac_X550EM_a:
7125 return ETH_RSS_RETA_SIZE_512;
7126 case ixgbe_mac_X550_vf:
7127 case ixgbe_mac_X550EM_x_vf:
7128 case ixgbe_mac_X550EM_a_vf:
7129 return ETH_RSS_RETA_SIZE_64;
7131 return ETH_RSS_RETA_SIZE_128;
7136 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7138 case ixgbe_mac_X550:
7139 case ixgbe_mac_X550EM_x:
7140 case ixgbe_mac_X550EM_a:
7141 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7142 return IXGBE_RETA(reta_idx >> 2);
7144 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7145 case ixgbe_mac_X550_vf:
7146 case ixgbe_mac_X550EM_x_vf:
7147 case ixgbe_mac_X550EM_a_vf:
7148 return IXGBE_VFRETA(reta_idx >> 2);
7150 return IXGBE_RETA(reta_idx >> 2);
7155 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7157 case ixgbe_mac_X550_vf:
7158 case ixgbe_mac_X550EM_x_vf:
7159 case ixgbe_mac_X550EM_a_vf:
7160 return IXGBE_VFMRQC;
7167 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7169 case ixgbe_mac_X550_vf:
7170 case ixgbe_mac_X550EM_x_vf:
7171 case ixgbe_mac_X550EM_a_vf:
7172 return IXGBE_VFRSSRK(i);
7174 return IXGBE_RSSRK(i);
7179 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7181 case ixgbe_mac_82599_vf:
7182 case ixgbe_mac_X540_vf:
7190 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7191 struct rte_eth_dcb_info *dcb_info)
7193 struct ixgbe_dcb_config *dcb_config =
7194 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7195 struct ixgbe_dcb_tc_config *tc;
7196 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7200 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7201 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7203 dcb_info->nb_tcs = 1;
7205 tc_queue = &dcb_info->tc_queue;
7206 nb_tcs = dcb_info->nb_tcs;
7208 if (dcb_config->vt_mode) { /* vt is enabled*/
7209 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7210 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7211 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7212 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7213 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7214 for (j = 0; j < nb_tcs; j++) {
7215 tc_queue->tc_rxq[0][j].base = j;
7216 tc_queue->tc_rxq[0][j].nb_queue = 1;
7217 tc_queue->tc_txq[0][j].base = j;
7218 tc_queue->tc_txq[0][j].nb_queue = 1;
7221 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7222 for (j = 0; j < nb_tcs; j++) {
7223 tc_queue->tc_rxq[i][j].base =
7225 tc_queue->tc_rxq[i][j].nb_queue = 1;
7226 tc_queue->tc_txq[i][j].base =
7228 tc_queue->tc_txq[i][j].nb_queue = 1;
7232 } else { /* vt is disabled*/
7233 struct rte_eth_dcb_rx_conf *rx_conf =
7234 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7235 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7236 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7237 if (dcb_info->nb_tcs == ETH_4_TCS) {
7238 for (i = 0; i < dcb_info->nb_tcs; i++) {
7239 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7240 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7242 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7243 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7244 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7245 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7246 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7247 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7248 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7249 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7250 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7251 for (i = 0; i < dcb_info->nb_tcs; i++) {
7252 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7253 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7255 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7256 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7257 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7258 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7259 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7260 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7261 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7262 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7263 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7264 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7265 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7266 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7267 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7268 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7269 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7270 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7273 for (i = 0; i < dcb_info->nb_tcs; i++) {
7274 tc = &dcb_config->tc_config[i];
7275 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7280 /* Update e-tag ether type */
7282 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7283 uint16_t ether_type)
7285 uint32_t etag_etype;
7287 if (hw->mac.type != ixgbe_mac_X550 &&
7288 hw->mac.type != ixgbe_mac_X550EM_x &&
7289 hw->mac.type != ixgbe_mac_X550EM_a) {
7293 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7294 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7295 etag_etype |= ether_type;
7296 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7297 IXGBE_WRITE_FLUSH(hw);
7302 /* Config l2 tunnel ether type */
7304 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7305 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7308 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7309 struct ixgbe_l2_tn_info *l2_tn_info =
7310 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7312 if (l2_tunnel == NULL)
7315 switch (l2_tunnel->l2_tunnel_type) {
7316 case RTE_L2_TUNNEL_TYPE_E_TAG:
7317 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7318 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7321 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7329 /* Enable e-tag tunnel */
7331 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7333 uint32_t etag_etype;
7335 if (hw->mac.type != ixgbe_mac_X550 &&
7336 hw->mac.type != ixgbe_mac_X550EM_x &&
7337 hw->mac.type != ixgbe_mac_X550EM_a) {
7341 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7342 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7343 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7344 IXGBE_WRITE_FLUSH(hw);
7349 /* Enable l2 tunnel */
7351 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7352 enum rte_eth_tunnel_type l2_tunnel_type)
7355 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7356 struct ixgbe_l2_tn_info *l2_tn_info =
7357 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7359 switch (l2_tunnel_type) {
7360 case RTE_L2_TUNNEL_TYPE_E_TAG:
7361 l2_tn_info->e_tag_en = TRUE;
7362 ret = ixgbe_e_tag_enable(hw);
7365 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7373 /* Disable e-tag tunnel */
7375 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7377 uint32_t etag_etype;
7379 if (hw->mac.type != ixgbe_mac_X550 &&
7380 hw->mac.type != ixgbe_mac_X550EM_x &&
7381 hw->mac.type != ixgbe_mac_X550EM_a) {
7385 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7386 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7387 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7388 IXGBE_WRITE_FLUSH(hw);
7393 /* Disable l2 tunnel */
7395 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7396 enum rte_eth_tunnel_type l2_tunnel_type)
7399 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7400 struct ixgbe_l2_tn_info *l2_tn_info =
7401 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7403 switch (l2_tunnel_type) {
7404 case RTE_L2_TUNNEL_TYPE_E_TAG:
7405 l2_tn_info->e_tag_en = FALSE;
7406 ret = ixgbe_e_tag_disable(hw);
7409 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7418 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7419 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7422 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7423 uint32_t i, rar_entries;
7424 uint32_t rar_low, rar_high;
7426 if (hw->mac.type != ixgbe_mac_X550 &&
7427 hw->mac.type != ixgbe_mac_X550EM_x &&
7428 hw->mac.type != ixgbe_mac_X550EM_a) {
7432 rar_entries = ixgbe_get_num_rx_addrs(hw);
7434 for (i = 1; i < rar_entries; i++) {
7435 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7436 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7437 if ((rar_high & IXGBE_RAH_AV) &&
7438 (rar_high & IXGBE_RAH_ADTYPE) &&
7439 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7440 l2_tunnel->tunnel_id)) {
7441 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7442 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7444 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7454 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7455 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7458 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7459 uint32_t i, rar_entries;
7460 uint32_t rar_low, rar_high;
7462 if (hw->mac.type != ixgbe_mac_X550 &&
7463 hw->mac.type != ixgbe_mac_X550EM_x &&
7464 hw->mac.type != ixgbe_mac_X550EM_a) {
7468 /* One entry for one tunnel. Try to remove potential existing entry. */
7469 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7471 rar_entries = ixgbe_get_num_rx_addrs(hw);
7473 for (i = 1; i < rar_entries; i++) {
7474 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7475 if (rar_high & IXGBE_RAH_AV) {
7478 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7479 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7480 rar_low = l2_tunnel->tunnel_id;
7482 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7483 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7489 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7490 " Please remove a rule before adding a new one.");
7494 static inline struct ixgbe_l2_tn_filter *
7495 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7496 struct ixgbe_l2_tn_key *key)
7500 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7504 return l2_tn_info->hash_map[ret];
7508 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7509 struct ixgbe_l2_tn_filter *l2_tn_filter)
7513 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7514 &l2_tn_filter->key);
7518 "Failed to insert L2 tunnel filter"
7519 " to hash table %d!",
7524 l2_tn_info->hash_map[ret] = l2_tn_filter;
7526 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7532 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7533 struct ixgbe_l2_tn_key *key)
7536 struct ixgbe_l2_tn_filter *l2_tn_filter;
7538 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7542 "No such L2 tunnel filter to delete %d!",
7547 l2_tn_filter = l2_tn_info->hash_map[ret];
7548 l2_tn_info->hash_map[ret] = NULL;
7550 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7551 rte_free(l2_tn_filter);
7556 /* Add l2 tunnel filter */
7558 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7559 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7563 struct ixgbe_l2_tn_info *l2_tn_info =
7564 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7565 struct ixgbe_l2_tn_key key;
7566 struct ixgbe_l2_tn_filter *node;
7569 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7570 key.tn_id = l2_tunnel->tunnel_id;
7572 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7576 "The L2 tunnel filter already exists!");
7580 node = rte_zmalloc("ixgbe_l2_tn",
7581 sizeof(struct ixgbe_l2_tn_filter),
7586 rte_memcpy(&node->key,
7588 sizeof(struct ixgbe_l2_tn_key));
7589 node->pool = l2_tunnel->pool;
7590 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7597 switch (l2_tunnel->l2_tunnel_type) {
7598 case RTE_L2_TUNNEL_TYPE_E_TAG:
7599 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7602 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7607 if ((!restore) && (ret < 0))
7608 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7613 /* Delete l2 tunnel filter */
7615 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7616 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7619 struct ixgbe_l2_tn_info *l2_tn_info =
7620 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7621 struct ixgbe_l2_tn_key key;
7623 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7624 key.tn_id = l2_tunnel->tunnel_id;
7625 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7629 switch (l2_tunnel->l2_tunnel_type) {
7630 case RTE_L2_TUNNEL_TYPE_E_TAG:
7631 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7634 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7643 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7644 * @dev: pointer to rte_eth_dev structure
7645 * @filter_op:operation will be taken.
7646 * @arg: a pointer to specific structure corresponding to the filter_op
7649 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7650 enum rte_filter_op filter_op,
7655 if (filter_op == RTE_ETH_FILTER_NOP)
7659 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7664 switch (filter_op) {
7665 case RTE_ETH_FILTER_ADD:
7666 ret = ixgbe_dev_l2_tunnel_filter_add
7668 (struct rte_eth_l2_tunnel_conf *)arg,
7671 case RTE_ETH_FILTER_DELETE:
7672 ret = ixgbe_dev_l2_tunnel_filter_del
7674 (struct rte_eth_l2_tunnel_conf *)arg);
7677 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7685 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7689 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7691 if (hw->mac.type != ixgbe_mac_X550 &&
7692 hw->mac.type != ixgbe_mac_X550EM_x &&
7693 hw->mac.type != ixgbe_mac_X550EM_a) {
7697 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7698 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7700 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7701 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7706 /* Enable l2 tunnel forwarding */
7708 ixgbe_dev_l2_tunnel_forwarding_enable
7709 (struct rte_eth_dev *dev,
7710 enum rte_eth_tunnel_type l2_tunnel_type)
7712 struct ixgbe_l2_tn_info *l2_tn_info =
7713 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7716 switch (l2_tunnel_type) {
7717 case RTE_L2_TUNNEL_TYPE_E_TAG:
7718 l2_tn_info->e_tag_fwd_en = TRUE;
7719 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7722 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7730 /* Disable l2 tunnel forwarding */
7732 ixgbe_dev_l2_tunnel_forwarding_disable
7733 (struct rte_eth_dev *dev,
7734 enum rte_eth_tunnel_type l2_tunnel_type)
7736 struct ixgbe_l2_tn_info *l2_tn_info =
7737 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7740 switch (l2_tunnel_type) {
7741 case RTE_L2_TUNNEL_TYPE_E_TAG:
7742 l2_tn_info->e_tag_fwd_en = FALSE;
7743 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7746 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7755 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7756 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7759 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7761 uint32_t vmtir, vmvir;
7762 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7764 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7766 "VF id %u should be less than %u",
7772 if (hw->mac.type != ixgbe_mac_X550 &&
7773 hw->mac.type != ixgbe_mac_X550EM_x &&
7774 hw->mac.type != ixgbe_mac_X550EM_a) {
7779 vmtir = l2_tunnel->tunnel_id;
7783 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7785 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7786 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7788 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7789 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7794 /* Enable l2 tunnel tag insertion */
7796 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7797 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7801 switch (l2_tunnel->l2_tunnel_type) {
7802 case RTE_L2_TUNNEL_TYPE_E_TAG:
7803 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7806 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7814 /* Disable l2 tunnel tag insertion */
7816 ixgbe_dev_l2_tunnel_insertion_disable
7817 (struct rte_eth_dev *dev,
7818 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7822 switch (l2_tunnel->l2_tunnel_type) {
7823 case RTE_L2_TUNNEL_TYPE_E_TAG:
7824 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7827 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7836 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7841 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7843 if (hw->mac.type != ixgbe_mac_X550 &&
7844 hw->mac.type != ixgbe_mac_X550EM_x &&
7845 hw->mac.type != ixgbe_mac_X550EM_a) {
7849 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7851 qde |= IXGBE_QDE_STRIP_TAG;
7853 qde &= ~IXGBE_QDE_STRIP_TAG;
7854 qde &= ~IXGBE_QDE_READ;
7855 qde |= IXGBE_QDE_WRITE;
7856 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7861 /* Enable l2 tunnel tag stripping */
7863 ixgbe_dev_l2_tunnel_stripping_enable
7864 (struct rte_eth_dev *dev,
7865 enum rte_eth_tunnel_type l2_tunnel_type)
7869 switch (l2_tunnel_type) {
7870 case RTE_L2_TUNNEL_TYPE_E_TAG:
7871 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7874 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7882 /* Disable l2 tunnel tag stripping */
7884 ixgbe_dev_l2_tunnel_stripping_disable
7885 (struct rte_eth_dev *dev,
7886 enum rte_eth_tunnel_type l2_tunnel_type)
7890 switch (l2_tunnel_type) {
7891 case RTE_L2_TUNNEL_TYPE_E_TAG:
7892 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7895 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7903 /* Enable/disable l2 tunnel offload functions */
7905 ixgbe_dev_l2_tunnel_offload_set
7906 (struct rte_eth_dev *dev,
7907 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7913 if (l2_tunnel == NULL)
7917 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7919 ret = ixgbe_dev_l2_tunnel_enable(
7921 l2_tunnel->l2_tunnel_type);
7923 ret = ixgbe_dev_l2_tunnel_disable(
7925 l2_tunnel->l2_tunnel_type);
7928 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7930 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7934 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7939 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7941 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7943 l2_tunnel->l2_tunnel_type);
7945 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7947 l2_tunnel->l2_tunnel_type);
7950 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7952 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7954 l2_tunnel->l2_tunnel_type);
7956 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7958 l2_tunnel->l2_tunnel_type);
7965 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7968 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7969 IXGBE_WRITE_FLUSH(hw);
7974 /* There's only one register for VxLAN UDP port.
7975 * So, we cannot add several ports. Will update it.
7978 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7982 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7986 return ixgbe_update_vxlan_port(hw, port);
7989 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7990 * UDP port, it must have a value.
7991 * So, will reset it to the original value 0.
7994 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7999 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8001 if (cur_port != port) {
8002 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8006 return ixgbe_update_vxlan_port(hw, 0);
8009 /* Add UDP tunneling port */
8011 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8012 struct rte_eth_udp_tunnel *udp_tunnel)
8015 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8017 if (hw->mac.type != ixgbe_mac_X550 &&
8018 hw->mac.type != ixgbe_mac_X550EM_x &&
8019 hw->mac.type != ixgbe_mac_X550EM_a) {
8023 if (udp_tunnel == NULL)
8026 switch (udp_tunnel->prot_type) {
8027 case RTE_TUNNEL_TYPE_VXLAN:
8028 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8031 case RTE_TUNNEL_TYPE_GENEVE:
8032 case RTE_TUNNEL_TYPE_TEREDO:
8033 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8038 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8046 /* Remove UDP tunneling port */
8048 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8049 struct rte_eth_udp_tunnel *udp_tunnel)
8052 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8054 if (hw->mac.type != ixgbe_mac_X550 &&
8055 hw->mac.type != ixgbe_mac_X550EM_x &&
8056 hw->mac.type != ixgbe_mac_X550EM_a) {
8060 if (udp_tunnel == NULL)
8063 switch (udp_tunnel->prot_type) {
8064 case RTE_TUNNEL_TYPE_VXLAN:
8065 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8067 case RTE_TUNNEL_TYPE_GENEVE:
8068 case RTE_TUNNEL_TYPE_TEREDO:
8069 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8073 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8082 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8084 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8086 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8090 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8092 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8094 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8097 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8099 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8102 /* peek the message first */
8103 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8105 /* PF reset VF event */
8106 if (in_msg == IXGBE_PF_CONTROL_MSG) {
8107 /* dummy mbx read to ack pf */
8108 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8110 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8116 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8119 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8120 struct ixgbe_interrupt *intr =
8121 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8122 ixgbevf_intr_disable(hw);
8124 /* read-on-clear nic registers here */
8125 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8128 /* only one misc vector supported - mailbox */
8129 eicr &= IXGBE_VTEICR_MASK;
8130 if (eicr == IXGBE_MISC_VEC_ID)
8131 intr->flags |= IXGBE_FLAG_MAILBOX;
8137 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8139 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8140 struct ixgbe_interrupt *intr =
8141 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8143 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8144 ixgbevf_mbx_process(dev);
8145 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8148 ixgbevf_intr_enable(hw);
8154 ixgbevf_dev_interrupt_handler(void *param)
8156 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8158 ixgbevf_dev_interrupt_get_status(dev);
8159 ixgbevf_dev_interrupt_action(dev);
8163 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8164 * @hw: pointer to hardware structure
8166 * Stops the transmit data path and waits for the HW to internally empty
8167 * the Tx security block
8169 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8171 #define IXGBE_MAX_SECTX_POLL 40
8176 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8177 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8178 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8179 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8180 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8181 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8183 /* Use interrupt-safe sleep just in case */
8187 /* For informational purposes only */
8188 if (i >= IXGBE_MAX_SECTX_POLL)
8189 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8190 "path fully disabled. Continuing with init.");
8192 return IXGBE_SUCCESS;
8196 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8197 * @hw: pointer to hardware structure
8199 * Enables the transmit data path.
8201 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8205 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8206 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8207 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8208 IXGBE_WRITE_FLUSH(hw);
8210 return IXGBE_SUCCESS;
8213 /* restore n-tuple filter */
8215 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8217 struct ixgbe_filter_info *filter_info =
8218 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8219 struct ixgbe_5tuple_filter *node;
8221 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8222 ixgbe_inject_5tuple_filter(dev, node);
8226 /* restore ethernet type filter */
8228 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8230 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8231 struct ixgbe_filter_info *filter_info =
8232 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8235 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8236 if (filter_info->ethertype_mask & (1 << i)) {
8237 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8238 filter_info->ethertype_filters[i].etqf);
8239 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8240 filter_info->ethertype_filters[i].etqs);
8241 IXGBE_WRITE_FLUSH(hw);
8246 /* restore SYN filter */
8248 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8250 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8251 struct ixgbe_filter_info *filter_info =
8252 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8255 synqf = filter_info->syn_info;
8257 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8258 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8259 IXGBE_WRITE_FLUSH(hw);
8263 /* restore L2 tunnel filter */
8265 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8267 struct ixgbe_l2_tn_info *l2_tn_info =
8268 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8269 struct ixgbe_l2_tn_filter *node;
8270 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8272 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8273 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8274 l2_tn_conf.tunnel_id = node->key.tn_id;
8275 l2_tn_conf.pool = node->pool;
8276 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8280 /* restore rss filter */
8282 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8284 struct ixgbe_filter_info *filter_info =
8285 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8287 if (filter_info->rss_info.num)
8288 ixgbe_config_rss_filter(dev,
8289 &filter_info->rss_info, TRUE);
8293 ixgbe_filter_restore(struct rte_eth_dev *dev)
8295 ixgbe_ntuple_filter_restore(dev);
8296 ixgbe_ethertype_filter_restore(dev);
8297 ixgbe_syn_filter_restore(dev);
8298 ixgbe_fdir_filter_restore(dev);
8299 ixgbe_l2_tn_filter_restore(dev);
8300 ixgbe_rss_filter_restore(dev);
8306 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8308 struct ixgbe_l2_tn_info *l2_tn_info =
8309 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8310 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8312 if (l2_tn_info->e_tag_en)
8313 (void)ixgbe_e_tag_enable(hw);
8315 if (l2_tn_info->e_tag_fwd_en)
8316 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8318 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8321 /* remove all the n-tuple filters */
8323 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8325 struct ixgbe_filter_info *filter_info =
8326 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8327 struct ixgbe_5tuple_filter *p_5tuple;
8329 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8330 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8333 /* remove all the ether type filters */
8335 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8337 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8338 struct ixgbe_filter_info *filter_info =
8339 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8342 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8343 if (filter_info->ethertype_mask & (1 << i) &&
8344 !filter_info->ethertype_filters[i].conf) {
8345 (void)ixgbe_ethertype_filter_remove(filter_info,
8347 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8348 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8349 IXGBE_WRITE_FLUSH(hw);
8354 /* remove the SYN filter */
8356 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8358 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8359 struct ixgbe_filter_info *filter_info =
8360 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8362 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8363 filter_info->syn_info = 0;
8365 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8366 IXGBE_WRITE_FLUSH(hw);
8370 /* remove all the L2 tunnel filters */
8372 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8374 struct ixgbe_l2_tn_info *l2_tn_info =
8375 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8376 struct ixgbe_l2_tn_filter *l2_tn_filter;
8377 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8380 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8381 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8382 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8383 l2_tn_conf.pool = l2_tn_filter->pool;
8384 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8392 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8393 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8394 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8395 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8396 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8397 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8399 RTE_INIT(ixgbe_init_log);
8401 ixgbe_init_log(void)
8403 ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8404 if (ixgbe_logtype_init >= 0)
8405 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8406 ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8407 if (ixgbe_logtype_driver >= 0)
8408 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);