drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_eal.h>
  26 #include <rte_alarm.h>
  27 #include <rte_ether.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_malloc.h>
  31 #include <rte_random.h>
  32 #include <rte_dev.h>
  33 #include <rte_hash_crc.h>
  34 #ifdef RTE_LIBRTE_SECURITY
  35 #include <rte_security_driver.h>
  36 #endif
  37
  38 #include "ixgbe_logs.h"
  39 #include "base/ixgbe_api.h"
  40 #include "base/ixgbe_vf.h"
  41 #include "base/ixgbe_common.h"
  42 #include "ixgbe_ethdev.h"
  43 #include "ixgbe_bypass.h"
  44 #include "ixgbe_rxtx.h"
  45 #include "base/ixgbe_type.h"
  46 #include "base/ixgbe_phy.h"
  47 #include "ixgbe_regs.h"
  48
  49 /*
  50  * High threshold controlling when to start sending XOFF frames. Must be at
  51  * least 8 bytes less than receive packet buffer size. This value is in units
  52  * of 1024 bytes.
  53  */
  54 #define IXGBE_FC_HI    0x80
  55
  56 /*
  57  * Low threshold controlling when to start sending XON frames. This value is
  58  * in units of 1024 bytes.
  59  */
  60 #define IXGBE_FC_LO    0x40
  61
  62 /* Default minimum inter-interrupt interval for EITR configuration */
  63 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  64
  65 /* Timer value included in XOFF frames. */
  66 #define IXGBE_FC_PAUSE 0x680
  67
  68 /*Default value of Max Rx Queue*/
  69 #define IXGBE_MAX_RX_QUEUE_NUM 128
  70
  71 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  72 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  73 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  74
  75 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  76 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  77 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  78
  79 /*
  80  *  Default values for RX/TX configuration
  81  */
  82 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  83 #define IXGBE_DEFAULT_RX_PTHRESH      8
  84 #define IXGBE_DEFAULT_RX_HTHRESH      8
  85 #define IXGBE_DEFAULT_RX_WTHRESH      0
  86
  87 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  88 #define IXGBE_DEFAULT_TX_PTHRESH      32
  89 #define IXGBE_DEFAULT_TX_HTHRESH      0
  90 #define IXGBE_DEFAULT_TX_WTHRESH      0
  91 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  92
  93 /* Bit shift and mask */
  94 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  95 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  96 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  97 #define IXGBE_8_BIT_MASK   UINT8_MAX
  98
  99 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 100
 101 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 102
 103 #define IXGBE_HKEY_MAX_INDEX 10
 104
 105 /* Additional timesync values. */
 106 #define NSEC_PER_SEC             1000000000L
 107 #define IXGBE_INCVAL_10GB        0x66666666
 108 #define IXGBE_INCVAL_1GB         0x40000000
 109 #define IXGBE_INCVAL_100         0x50000000
 110 #define IXGBE_INCVAL_SHIFT_10GB  28
 111 #define IXGBE_INCVAL_SHIFT_1GB   24
 112 #define IXGBE_INCVAL_SHIFT_100   21
 113 #define IXGBE_INCVAL_SHIFT_82599 7
 114 #define IXGBE_INCPER_SHIFT_82599 24
 115
 116 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 117
 118 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 119 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 120 #define DEFAULT_ETAG_ETYPE                     0x893f
 121 #define IXGBE_ETAG_ETYPE                       0x00005084
 122 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 123 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 124 #define IXGBE_RAH_ADTYPE                       0x40000000
 125 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 126 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 127 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 128 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 129 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 130 #define IXGBE_VTEICR_MASK                      0x07
 131
 132 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 133 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 134
 135 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 136 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 137 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 138 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 139 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 143 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 145 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 148 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 149 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 151 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 152 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 154                                 int wait_to_complete);
 155 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 156                                 struct rte_eth_stats *stats);
 157 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 158                                 struct rte_eth_xstat *xstats, unsigned n);
 159 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 160                                   struct rte_eth_xstat *xstats, unsigned n);
 161 static int
 162 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 163                 uint64_t *values, unsigned int n);
 164 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 165 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 166 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 167         struct rte_eth_xstat_name *xstats_names,
 168         unsigned int size);
 169 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 171 static int ixgbe_dev_xstats_get_names_by_id(
 172         struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names,
 174         const uint64_t *ids,
 175         unsigned int limit);
 176 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 177                                              uint16_t queue_id,
 178                                              uint8_t stat_idx,
 179                                              uint8_t is_rx);
 180 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 181                                  size_t fw_size);
 182 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 183                                struct rte_eth_dev_info *dev_info);
 184 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 185 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 186                                  struct rte_eth_dev_info *dev_info);
 187 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 188
 189 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 190                 uint16_t vlan_id, int on);
 191 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 192                                enum rte_vlan_type vlan_type,
 193                                uint16_t tpid_id);
 194 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 195                 uint16_t queue, bool on);
 196 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 197                 int on);
 198 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 199 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 200 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 201 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 202 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 203
 204 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 205 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 206 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 207                                struct rte_eth_fc_conf *fc_conf);
 208 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 209                                struct rte_eth_fc_conf *fc_conf);
 210 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 211                 struct rte_eth_pfc_conf *pfc_conf);
 212 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 213                         struct rte_eth_rss_reta_entry64 *reta_conf,
 214                         uint16_t reta_size);
 215 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 216                         struct rte_eth_rss_reta_entry64 *reta_conf,
 217                         uint16_t reta_size);
 218 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 220 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 221 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 222 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 223 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 224                                       struct rte_intr_handle *handle);
 225 static void ixgbe_dev_interrupt_handler(void *param);
 226 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 227 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 228                          uint32_t index, uint32_t pool);
 229 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 230 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 231                                            struct ether_addr *mac_addr);
 232 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 233 static bool is_device_supported(struct rte_eth_dev *dev,
 234                                 struct rte_pci_driver *drv);
 235
 236 /* For Virtual Function support */
 237 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 238 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 239 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 240 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 241 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 242                                    int wait_to_complete);
 243 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 244 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 245 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 246 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 247 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 248 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 249                 struct rte_eth_stats *stats);
 250 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 251 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 252                 uint16_t vlan_id, int on);
 253 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 254                 uint16_t queue, int on);
 255 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 256 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 257 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 258                                             uint16_t queue_id);
 259 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 260                                              uint16_t queue_id);
 261 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 262                                  uint8_t queue, uint8_t msix_vector);
 263 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 264 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 265 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 266
 267 /* For Eth VMDQ APIs support */
 268 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 269                 ether_addr * mac_addr, uint8_t on);
 270 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 271 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 272                 struct rte_eth_mirror_conf *mirror_conf,
 273                 uint8_t rule_id, uint8_t on);
 274 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 275                 uint8_t rule_id);
 276 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 277                                           uint16_t queue_id);
 278 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 279                                            uint16_t queue_id);
 280 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 281                                uint8_t queue, uint8_t msix_vector);
 282 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 283
 284 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 285                                 struct ether_addr *mac_addr,
 286                                 uint32_t index, uint32_t pool);
 287 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 288 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 289                                              struct ether_addr *mac_addr);
 290 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 291                         struct rte_eth_syn_filter *filter);
 292 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 293                         enum rte_filter_op filter_op,
 294                         void *arg);
 295 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 296                         struct ixgbe_5tuple_filter *filter);
 297 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 298                         struct ixgbe_5tuple_filter *filter);
 299 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 300                                 enum rte_filter_op filter_op,
 301                                 void *arg);
 302 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 303                         struct rte_eth_ntuple_filter *filter);
 304 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 305                                 enum rte_filter_op filter_op,
 306                                 void *arg);
 307 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 308                         struct rte_eth_ethertype_filter *filter);
 309 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 310                      enum rte_filter_type filter_type,
 311                      enum rte_filter_op filter_op,
 312                      void *arg);
 313 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 314
 315 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 316                                       struct ether_addr *mc_addr_set,
 317                                       uint32_t nb_mc_addr);
 318 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 319                                    struct rte_eth_dcb_info *dcb_info);
 320
 321 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 322 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 323                             struct rte_dev_reg_info *regs);
 324 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 325 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 326                                 struct rte_dev_eeprom_info *eeprom);
 327 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 328                                 struct rte_dev_eeprom_info *eeprom);
 329
 330 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 331 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 332                                 struct rte_dev_reg_info *regs);
 333
 334 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 335 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 336 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 337                                             struct timespec *timestamp,
 338                                             uint32_t flags);
 339 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 340                                             struct timespec *timestamp);
 341 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 342 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 343                                    struct timespec *timestamp);
 344 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 345                                    const struct timespec *timestamp);
 346 static void ixgbevf_dev_interrupt_handler(void *param);
 347
 348 static int ixgbe_dev_l2_tunnel_eth_type_conf
 349         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 350 static int ixgbe_dev_l2_tunnel_offload_set
 351         (struct rte_eth_dev *dev,
 352          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 353          uint32_t mask,
 354          uint8_t en);
 355 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 356                                              enum rte_filter_op filter_op,
 357                                              void *arg);
 358
 359 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 360                                          struct rte_eth_udp_tunnel *udp_tunnel);
 361 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 362                                          struct rte_eth_udp_tunnel *udp_tunnel);
 363 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 364 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 365
 366 /*
 367  * Define VF Stats MACRO for Non "cleared on read" register
 368  */
 369 #define UPDATE_VF_STAT(reg, last, cur)                          \
 370 {                                                               \
 371         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 372         cur += (latest - last) & UINT_MAX;                      \
 373         last = latest;                                          \
 374 }
 375
 376 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 377 {                                                                \
 378         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 379         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 380         u64 latest = ((new_msb << 32) | new_lsb);                \
 381         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 382         last = latest;                                           \
 383 }
 384
 385 #define IXGBE_SET_HWSTRIP(h, q) do {\
 386                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 387                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 388                 (h)->bitmap[idx] |= 1 << bit;\
 389         } while (0)
 390
 391 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 392                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 393                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 394                 (h)->bitmap[idx] &= ~(1 << bit);\
 395         } while (0)
 396
 397 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 398                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 399                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 400                 (r) = (h)->bitmap[idx] >> bit & 1;\
 401         } while (0)
 402
 403 int ixgbe_logtype_init;
 404 int ixgbe_logtype_driver;
 405
 406 /*
 407  * The set of PCI devices this driver supports
 408  */
 409 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 410         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 411         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 458 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 460 #endif
 461         { .vendor_id = 0, /* sentinel */ },
 462 };
 463
 464 /*
 465  * The set of PCI devices this driver supports (for 82599 VF)
 466  */
 467 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 478         { .vendor_id = 0, /* sentinel */ },
 479 };
 480
 481 static const struct rte_eth_desc_lim rx_desc_lim = {
 482         .nb_max = IXGBE_MAX_RING_DESC,
 483         .nb_min = IXGBE_MIN_RING_DESC,
 484         .nb_align = IXGBE_RXD_ALIGN,
 485 };
 486
 487 static const struct rte_eth_desc_lim tx_desc_lim = {
 488         .nb_max = IXGBE_MAX_RING_DESC,
 489         .nb_min = IXGBE_MIN_RING_DESC,
 490         .nb_align = IXGBE_TXD_ALIGN,
 491         .nb_seg_max = IXGBE_TX_MAX_SEG,
 492         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 493 };
 494
 495 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 496         .dev_configure        = ixgbe_dev_configure,
 497         .dev_start            = ixgbe_dev_start,
 498         .dev_stop             = ixgbe_dev_stop,
 499         .dev_set_link_up    = ixgbe_dev_set_link_up,
 500         .dev_set_link_down  = ixgbe_dev_set_link_down,
 501         .dev_close            = ixgbe_dev_close,
 502         .dev_reset            = ixgbe_dev_reset,
 503         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 504         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 505         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 506         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 507         .link_update          = ixgbe_dev_link_update,
 508         .stats_get            = ixgbe_dev_stats_get,
 509         .xstats_get           = ixgbe_dev_xstats_get,
 510         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 511         .stats_reset          = ixgbe_dev_stats_reset,
 512         .xstats_reset         = ixgbe_dev_xstats_reset,
 513         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 514         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 515         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 516         .fw_version_get       = ixgbe_fw_version_get,
 517         .dev_infos_get        = ixgbe_dev_info_get,
 518         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 519         .mtu_set              = ixgbe_dev_mtu_set,
 520         .vlan_filter_set      = ixgbe_vlan_filter_set,
 521         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 522         .vlan_offload_set     = ixgbe_vlan_offload_set,
 523         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 524         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 525         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 526         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 527         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 528         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 529         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 530         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 531         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 532         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 533         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 534         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 535         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 536         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 537         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 538         .dev_led_on           = ixgbe_dev_led_on,
 539         .dev_led_off          = ixgbe_dev_led_off,
 540         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 541         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 542         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 543         .mac_addr_add         = ixgbe_add_rar,
 544         .mac_addr_remove      = ixgbe_remove_rar,
 545         .mac_addr_set         = ixgbe_set_default_mac_addr,
 546         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 547         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 548         .mirror_rule_set      = ixgbe_mirror_rule_set,
 549         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 550         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 551         .reta_update          = ixgbe_dev_rss_reta_update,
 552         .reta_query           = ixgbe_dev_rss_reta_query,
 553         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 554         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 555         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 556         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 557         .rxq_info_get         = ixgbe_rxq_info_get,
 558         .txq_info_get         = ixgbe_txq_info_get,
 559         .timesync_enable      = ixgbe_timesync_enable,
 560         .timesync_disable     = ixgbe_timesync_disable,
 561         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 562         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 563         .get_reg              = ixgbe_get_regs,
 564         .get_eeprom_length    = ixgbe_get_eeprom_length,
 565         .get_eeprom           = ixgbe_get_eeprom,
 566         .set_eeprom           = ixgbe_set_eeprom,
 567         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 568         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 569         .timesync_read_time   = ixgbe_timesync_read_time,
 570         .timesync_write_time  = ixgbe_timesync_write_time,
 571         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 572         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 573         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 574         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 575         .tm_ops_get           = ixgbe_tm_ops_get,
 576 };
 577
 578 /*
 579  * dev_ops for virtual function, bare necessities for basic vf
 580  * operation have been implemented
 581  */
 582 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 583         .dev_configure        = ixgbevf_dev_configure,
 584         .dev_start            = ixgbevf_dev_start,
 585         .dev_stop             = ixgbevf_dev_stop,
 586         .link_update          = ixgbevf_dev_link_update,
 587         .stats_get            = ixgbevf_dev_stats_get,
 588         .xstats_get           = ixgbevf_dev_xstats_get,
 589         .stats_reset          = ixgbevf_dev_stats_reset,
 590         .xstats_reset         = ixgbevf_dev_stats_reset,
 591         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 592         .dev_close            = ixgbevf_dev_close,
 593         .dev_reset            = ixgbevf_dev_reset,
 594         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 595         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 596         .dev_infos_get        = ixgbevf_dev_info_get,
 597         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 598         .mtu_set              = ixgbevf_dev_set_mtu,
 599         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 600         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 601         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 602         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 603         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 604         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 605         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 606         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 607         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 608         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 609         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 610         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 611         .mac_addr_add         = ixgbevf_add_mac_addr,
 612         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 613         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 614         .rxq_info_get         = ixgbe_rxq_info_get,
 615         .txq_info_get         = ixgbe_txq_info_get,
 616         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 617         .get_reg              = ixgbevf_get_regs,
 618         .reta_update          = ixgbe_dev_rss_reta_update,
 619         .reta_query           = ixgbe_dev_rss_reta_query,
 620         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 621         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 622 };
 623
 624 /* store statistics names and its offset in stats structure */
 625 struct rte_ixgbe_xstats_name_off {
 626         char name[RTE_ETH_XSTATS_NAME_SIZE];
 627         unsigned offset;
 628 };
 629
 630 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 631         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 632         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 633         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 634         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 635         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 636         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 637         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 638         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 639         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 640         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 641         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 642         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 643         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 644         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 645         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 646                 prc1023)},
 647         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 648                 prc1522)},
 649         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 650         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 651         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 652         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 653         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 654         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 655         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 656         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 657         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 658         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 659         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 660         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 661         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 662         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 663         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 664         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 665         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 666                 ptc1023)},
 667         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 668                 ptc1522)},
 669         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 670         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 671         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 672         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 673
 674         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 675                 fdirustat_add)},
 676         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 677                 fdirustat_remove)},
 678         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 679                 fdirfstat_fadd)},
 680         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 681                 fdirfstat_fremove)},
 682         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 683                 fdirmatch)},
 684         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 685                 fdirmiss)},
 686
 687         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 688         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 689         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 690                 fclast)},
 691         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 692         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 693         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 694         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 695         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 696                 fcoe_noddp)},
 697         {"rx_fcoe_no_direct_data_placement_ext_buff",
 698                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 699
 700         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 701                 lxontxc)},
 702         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 703                 lxonrxc)},
 704         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 705                 lxofftxc)},
 706         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 707                 lxoffrxc)},
 708         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 709 };
 710
 711 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 712                            sizeof(rte_ixgbe_stats_strings[0]))
 713
 714 /* MACsec statistics */
 715 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 716         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 717                 out_pkts_untagged)},
 718         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 719                 out_pkts_encrypted)},
 720         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 721                 out_pkts_protected)},
 722         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 723                 out_octets_encrypted)},
 724         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 725                 out_octets_protected)},
 726         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 727                 in_pkts_untagged)},
 728         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 729                 in_pkts_badtag)},
 730         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 731                 in_pkts_nosci)},
 732         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 733                 in_pkts_unknownsci)},
 734         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 735                 in_octets_decrypted)},
 736         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 737                 in_octets_validated)},
 738         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 739                 in_pkts_unchecked)},
 740         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 741                 in_pkts_delayed)},
 742         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 743                 in_pkts_late)},
 744         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 745                 in_pkts_ok)},
 746         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 747                 in_pkts_invalid)},
 748         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 749                 in_pkts_notvalid)},
 750         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_unusedsa)},
 752         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_notusingsa)},
 754 };
 755
 756 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 757                            sizeof(rte_ixgbe_macsec_strings[0]))
 758
 759 /* Per-queue statistics */
 760 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 761         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 762         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 763         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 764         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 765 };
 766
 767 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 768                            sizeof(rte_ixgbe_rxq_strings[0]))
 769 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 770
 771 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 772         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 773         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 774         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 775                 pxon2offc)},
 776 };
 777
 778 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 779                            sizeof(rte_ixgbe_txq_strings[0]))
 780 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 781
 782 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 783         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 784 };
 785
 786 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 787                 sizeof(rte_ixgbevf_stats_strings[0]))
 788
 789 /*
 790  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 791  */
 792 static inline int
 793 ixgbe_is_sfp(struct ixgbe_hw *hw)
 794 {
 795         switch (hw->phy.type) {
 796         case ixgbe_phy_sfp_avago:
 797         case ixgbe_phy_sfp_ftl:
 798         case ixgbe_phy_sfp_intel:
 799         case ixgbe_phy_sfp_unknown:
 800         case ixgbe_phy_sfp_passive_tyco:
 801         case ixgbe_phy_sfp_passive_unknown:
 802                 return 1;
 803         default:
 804                 return 0;
 805         }
 806 }
 807
 808 static inline int32_t
 809 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 810 {
 811         uint32_t ctrl_ext;
 812         int32_t status;
 813
 814         status = ixgbe_reset_hw(hw);
 815
 816         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 817         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 818         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 819         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 820         IXGBE_WRITE_FLUSH(hw);
 821
 822         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 823                 status = IXGBE_SUCCESS;
 824         return status;
 825 }
 826
 827 static inline void
 828 ixgbe_enable_intr(struct rte_eth_dev *dev)
 829 {
 830         struct ixgbe_interrupt *intr =
 831                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 832         struct ixgbe_hw *hw =
 833                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 834
 835         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 836         IXGBE_WRITE_FLUSH(hw);
 837 }
 838
 839 /*
 840  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 841  */
 842 static void
 843 ixgbe_disable_intr(struct ixgbe_hw *hw)
 844 {
 845         PMD_INIT_FUNC_TRACE();
 846
 847         if (hw->mac.type == ixgbe_mac_82598EB) {
 848                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 849         } else {
 850                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 851                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 852                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 853         }
 854         IXGBE_WRITE_FLUSH(hw);
 855 }
 856
 857 /*
 858  * This function resets queue statistics mapping registers.
 859  * From Niantic datasheet, Initialization of Statistics section:
 860  * "...if software requires the queue counters, the RQSMR and TQSM registers
 861  * must be re-programmed following a device reset.
 862  */
 863 static void
 864 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 865 {
 866         uint32_t i;
 867
 868         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 869                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 870                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 871         }
 872 }
 873
 874
 875 static int
 876 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 877                                   uint16_t queue_id,
 878                                   uint8_t stat_idx,
 879                                   uint8_t is_rx)
 880 {
 881 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 882 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 883 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 884
 885         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 886         struct ixgbe_stat_mapping_registers *stat_mappings =
 887                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 888         uint32_t qsmr_mask = 0;
 889         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 890         uint32_t q_map;
 891         uint8_t n, offset;
 892
 893         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 894                 (hw->mac.type != ixgbe_mac_X540) &&
 895                 (hw->mac.type != ixgbe_mac_X550) &&
 896                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 897                 (hw->mac.type != ixgbe_mac_X550EM_a))
 898                 return -ENOSYS;
 899
 900         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 901                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 902                      queue_id, stat_idx);
 903
 904         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 905         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 906                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 907                 return -EIO;
 908         }
 909         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 910
 911         /* Now clear any previous stat_idx set */
 912         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 913         if (!is_rx)
 914                 stat_mappings->tqsm[n] &= ~clearing_mask;
 915         else
 916                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 917
 918         q_map = (uint32_t)stat_idx;
 919         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 920         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 921         if (!is_rx)
 922                 stat_mappings->tqsm[n] |= qsmr_mask;
 923         else
 924                 stat_mappings->rqsmr[n] |= qsmr_mask;
 925
 926         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 927                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 928                      queue_id, stat_idx);
 929         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 930                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 931
 932         /* Now write the mapping in the appropriate register */
 933         if (is_rx) {
 934                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 935                              stat_mappings->rqsmr[n], n);
 936                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 937         } else {
 938                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 939                              stat_mappings->tqsm[n], n);
 940                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 941         }
 942         return 0;
 943 }
 944
 945 static void
 946 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 947 {
 948         struct ixgbe_stat_mapping_registers *stat_mappings =
 949                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 950         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 951         int i;
 952
 953         /* write whatever was in stat mapping table to the NIC */
 954         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 955                 /* rx */
 956                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 957
 958                 /* tx */
 959                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 960         }
 961 }
 962
 963 static void
 964 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 965 {
 966         uint8_t i;
 967         struct ixgbe_dcb_tc_config *tc;
 968         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 969
 970         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 971         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 972         for (i = 0; i < dcb_max_tc; i++) {
 973                 tc = &dcb_config->tc_config[i];
 974                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 975                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 976                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 977                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 978                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 979                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 980                 tc->pfc = ixgbe_dcb_pfc_disabled;
 981         }
 982
 983         /* Initialize default user to priority mapping, UPx->TC0 */
 984         tc = &dcb_config->tc_config[0];
 985         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 986         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 987         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 988                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 989                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 990         }
 991         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 992         dcb_config->pfc_mode_enable = false;
 993         dcb_config->vt_mode = true;
 994         dcb_config->round_robin_enable = false;
 995         /* support all DCB capabilities in 82599 */
 996         dcb_config->support.capabilities = 0xFF;
 997
 998         /*we only support 4 Tcs for X540, X550 */
 999         if (hw->mac.type == ixgbe_mac_X540 ||
1000                 hw->mac.type == ixgbe_mac_X550 ||
1001                 hw->mac.type == ixgbe_mac_X550EM_x ||
1002                 hw->mac.type == ixgbe_mac_X550EM_a) {
1003                 dcb_config->num_tcs.pg_tcs = 4;
1004                 dcb_config->num_tcs.pfc_tcs = 4;
1005         }
1006 }
1007
1008 /*
1009  * Ensure that all locks are released before first NVM or PHY access
1010  */
1011 static void
1012 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1013 {
1014         uint16_t mask;
1015
1016         /*
1017          * Phy lock should not fail in this early stage. If this is the case,
1018          * it is due to an improper exit of the application.
1019          * So force the release of the faulty lock. Release of common lock
1020          * is done automatically by swfw_sync function.
1021          */
1022         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1023         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1024                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1025         }
1026         ixgbe_release_swfw_semaphore(hw, mask);
1027
1028         /*
1029          * These ones are more tricky since they are common to all ports; but
1030          * swfw_sync retries last long enough (1s) to be almost sure that if
1031          * lock can not be taken it is due to an improper lock of the
1032          * semaphore.
1033          */
1034         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1035         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1036                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1037         }
1038         ixgbe_release_swfw_semaphore(hw, mask);
1039 }
1040
1041 /*
1042  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1043  * It returns 0 on success.
1044  */
1045 static int
1046 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1047 {
1048         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1049         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1050         struct ixgbe_hw *hw =
1051                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1052         struct ixgbe_vfta *shadow_vfta =
1053                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1054         struct ixgbe_hwstrip *hwstrip =
1055                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1056         struct ixgbe_dcb_config *dcb_config =
1057                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1058         struct ixgbe_filter_info *filter_info =
1059                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1060         struct ixgbe_bw_conf *bw_conf =
1061                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1062         uint32_t ctrl_ext;
1063         uint16_t csum;
1064         int diag, i;
1065
1066         PMD_INIT_FUNC_TRACE();
1067
1068         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1069         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1070         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1071         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1072
1073         /*
1074          * For secondary processes, we don't initialise any further as primary
1075          * has already done this work. Only check we don't need a different
1076          * RX and TX function.
1077          */
1078         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1079                 struct ixgbe_tx_queue *txq;
1080                 /* TX queue function in primary, set by last queue initialized
1081                  * Tx queue may not initialized by primary process
1082                  */
1083                 if (eth_dev->data->tx_queues) {
1084                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1085                         ixgbe_set_tx_function(eth_dev, txq);
1086                 } else {
1087                         /* Use default TX function if we get here */
1088                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1089                                      "Using default TX function.");
1090                 }
1091
1092                 ixgbe_set_rx_function(eth_dev);
1093
1094                 return 0;
1095         }
1096
1097         rte_eth_copy_pci_info(eth_dev, pci_dev);
1098
1099         /* Vendor and Device ID need to be set before init of shared code */
1100         hw->device_id = pci_dev->id.device_id;
1101         hw->vendor_id = pci_dev->id.vendor_id;
1102         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1103         hw->allow_unsupported_sfp = 1;
1104
1105         /* Initialize the shared code (base driver) */
1106 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1107         diag = ixgbe_bypass_init_shared_code(hw);
1108 #else
1109         diag = ixgbe_init_shared_code(hw);
1110 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1111
1112         if (diag != IXGBE_SUCCESS) {
1113                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1114                 return -EIO;
1115         }
1116
1117         /* pick up the PCI bus settings for reporting later */
1118         ixgbe_get_bus_info(hw);
1119
1120         /* Unlock any pending hardware semaphore */
1121         ixgbe_swfw_lock_reset(hw);
1122
1123 #ifdef RTE_LIBRTE_SECURITY
1124         /* Initialize security_ctx only for primary process*/
1125         if (ixgbe_ipsec_ctx_create(eth_dev))
1126                 return -ENOMEM;
1127 #endif
1128
1129         /* Initialize DCB configuration*/
1130         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1131         ixgbe_dcb_init(hw, dcb_config);
1132         /* Get Hardware Flow Control setting */
1133         hw->fc.requested_mode = ixgbe_fc_full;
1134         hw->fc.current_mode = ixgbe_fc_full;
1135         hw->fc.pause_time = IXGBE_FC_PAUSE;
1136         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1137                 hw->fc.low_water[i] = IXGBE_FC_LO;
1138                 hw->fc.high_water[i] = IXGBE_FC_HI;
1139         }
1140         hw->fc.send_xon = 1;
1141
1142         /* Make sure we have a good EEPROM before we read from it */
1143         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1144         if (diag != IXGBE_SUCCESS) {
1145                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1146                 return -EIO;
1147         }
1148
1149 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1150         diag = ixgbe_bypass_init_hw(hw);
1151 #else
1152         diag = ixgbe_init_hw(hw);
1153 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1154
1155         /*
1156          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1157          * is called too soon after the kernel driver unbinding/binding occurs.
1158          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1159          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1160          * also called. See ixgbe_identify_phy_82599(). The reason for the
1161          * failure is not known, and only occuts when virtualisation features
1162          * are disabled in the bios. A delay of 100ms  was found to be enough by
1163          * trial-and-error, and is doubled to be safe.
1164          */
1165         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1166                 rte_delay_ms(200);
1167                 diag = ixgbe_init_hw(hw);
1168         }
1169
1170         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1171                 diag = IXGBE_SUCCESS;
1172
1173         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1174                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1175                              "LOM.  Please be aware there may be issues associated "
1176                              "with your hardware.");
1177                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1178                              "please contact your Intel or hardware representative "
1179                              "who provided you with this hardware.");
1180         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1181                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1182         if (diag) {
1183                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1184                 return -EIO;
1185         }
1186
1187         /* Reset the hw statistics */
1188         ixgbe_dev_stats_reset(eth_dev);
1189
1190         /* disable interrupt */
1191         ixgbe_disable_intr(hw);
1192
1193         /* reset mappings for queue statistics hw counters*/
1194         ixgbe_reset_qstat_mappings(hw);
1195
1196         /* Allocate memory for storing MAC addresses */
1197         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1198                                                hw->mac.num_rar_entries, 0);
1199         if (eth_dev->data->mac_addrs == NULL) {
1200                 PMD_INIT_LOG(ERR,
1201                              "Failed to allocate %u bytes needed to store "
1202                              "MAC addresses",
1203                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1204                 return -ENOMEM;
1205         }
1206         /* Copy the permanent MAC address */
1207         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1208                         &eth_dev->data->mac_addrs[0]);
1209
1210         /* Allocate memory for storing hash filter MAC addresses */
1211         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1212                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1213         if (eth_dev->data->hash_mac_addrs == NULL) {
1214                 PMD_INIT_LOG(ERR,
1215                              "Failed to allocate %d bytes needed to store MAC addresses",
1216                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1217                 return -ENOMEM;
1218         }
1219
1220         /* initialize the vfta */
1221         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1222
1223         /* initialize the hw strip bitmap*/
1224         memset(hwstrip, 0, sizeof(*hwstrip));
1225
1226         /* initialize PF if max_vfs not zero */
1227         ixgbe_pf_host_init(eth_dev);
1228
1229         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1230         /* let hardware know driver is loaded */
1231         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1232         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1233         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1234         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1235         IXGBE_WRITE_FLUSH(hw);
1236
1237         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1238                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1239                              (int) hw->mac.type, (int) hw->phy.type,
1240                              (int) hw->phy.sfp_type);
1241         else
1242                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1243                              (int) hw->mac.type, (int) hw->phy.type);
1244
1245         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1246                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1247                      pci_dev->id.device_id);
1248
1249         rte_intr_callback_register(intr_handle,
1250                                    ixgbe_dev_interrupt_handler, eth_dev);
1251
1252         /* enable uio/vfio intr/eventfd mapping */
1253         rte_intr_enable(intr_handle);
1254
1255         /* enable support intr */
1256         ixgbe_enable_intr(eth_dev);
1257
1258         /* initialize filter info */
1259         memset(filter_info, 0,
1260                sizeof(struct ixgbe_filter_info));
1261
1262         /* initialize 5tuple filter list */
1263         TAILQ_INIT(&filter_info->fivetuple_list);
1264
1265         /* initialize flow director filter list & hash */
1266         ixgbe_fdir_filter_init(eth_dev);
1267
1268         /* initialize l2 tunnel filter list & hash */
1269         ixgbe_l2_tn_filter_init(eth_dev);
1270
1271         /* initialize flow filter lists */
1272         ixgbe_filterlist_init();
1273
1274         /* initialize bandwidth configuration info */
1275         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1276
1277         /* initialize Traffic Manager configuration */
1278         ixgbe_tm_conf_init(eth_dev);
1279
1280         return 0;
1281 }
1282
1283 static int
1284 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1285 {
1286         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1287         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1288         struct ixgbe_hw *hw;
1289         int retries = 0;
1290         int ret;
1291
1292         PMD_INIT_FUNC_TRACE();
1293
1294         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1295                 return -EPERM;
1296
1297         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1298
1299         if (hw->adapter_stopped == 0)
1300                 ixgbe_dev_close(eth_dev);
1301
1302         eth_dev->dev_ops = NULL;
1303         eth_dev->rx_pkt_burst = NULL;
1304         eth_dev->tx_pkt_burst = NULL;
1305
1306         /* Unlock any pending hardware semaphore */
1307         ixgbe_swfw_lock_reset(hw);
1308
1309         /* disable uio intr before callback unregister */
1310         rte_intr_disable(intr_handle);
1311
1312         do {
1313                 ret = rte_intr_callback_unregister(intr_handle,
1314                                 ixgbe_dev_interrupt_handler, eth_dev);
1315                 if (ret >= 0) {
1316                         break;
1317                 } else if (ret != -EAGAIN) {
1318                         PMD_INIT_LOG(ERR,
1319                                 "intr callback unregister failed: %d",
1320                                 ret);
1321                         return ret;
1322                 }
1323                 rte_delay_ms(100);
1324         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1325
1326         /* uninitialize PF if max_vfs not zero */
1327         ixgbe_pf_host_uninit(eth_dev);
1328
1329         rte_free(eth_dev->data->mac_addrs);
1330         eth_dev->data->mac_addrs = NULL;
1331
1332         rte_free(eth_dev->data->hash_mac_addrs);
1333         eth_dev->data->hash_mac_addrs = NULL;
1334
1335         /* remove all the fdir filters & hash */
1336         ixgbe_fdir_filter_uninit(eth_dev);
1337
1338         /* remove all the L2 tunnel filters & hash */
1339         ixgbe_l2_tn_filter_uninit(eth_dev);
1340
1341         /* Remove all ntuple filters of the device */
1342         ixgbe_ntuple_filter_uninit(eth_dev);
1343
1344         /* clear all the filters list */
1345         ixgbe_filterlist_flush();
1346
1347         /* Remove all Traffic Manager configuration */
1348         ixgbe_tm_conf_uninit(eth_dev);
1349
1350 #ifdef RTE_LIBRTE_SECURITY
1351         rte_free(eth_dev->security_ctx);
1352 #endif
1353
1354         return 0;
1355 }
1356
1357 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1358 {
1359         struct ixgbe_filter_info *filter_info =
1360                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1361         struct ixgbe_5tuple_filter *p_5tuple;
1362
1363         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1364                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1365                              p_5tuple,
1366                              entries);
1367                 rte_free(p_5tuple);
1368         }
1369         memset(filter_info->fivetuple_mask, 0,
1370                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1371
1372         return 0;
1373 }
1374
1375 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1376 {
1377         struct ixgbe_hw_fdir_info *fdir_info =
1378                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1379         struct ixgbe_fdir_filter *fdir_filter;
1380
1381                 if (fdir_info->hash_map)
1382                 rte_free(fdir_info->hash_map);
1383         if (fdir_info->hash_handle)
1384                 rte_hash_free(fdir_info->hash_handle);
1385
1386         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1387                 TAILQ_REMOVE(&fdir_info->fdir_list,
1388                              fdir_filter,
1389                              entries);
1390                 rte_free(fdir_filter);
1391         }
1392
1393         return 0;
1394 }
1395
1396 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1397 {
1398         struct ixgbe_l2_tn_info *l2_tn_info =
1399                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1400         struct ixgbe_l2_tn_filter *l2_tn_filter;
1401
1402         if (l2_tn_info->hash_map)
1403                 rte_free(l2_tn_info->hash_map);
1404         if (l2_tn_info->hash_handle)
1405                 rte_hash_free(l2_tn_info->hash_handle);
1406
1407         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1408                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1409                              l2_tn_filter,
1410                              entries);
1411                 rte_free(l2_tn_filter);
1412         }
1413
1414         return 0;
1415 }
1416
1417 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1418 {
1419         struct ixgbe_hw_fdir_info *fdir_info =
1420                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1421         char fdir_hash_name[RTE_HASH_NAMESIZE];
1422         struct rte_hash_parameters fdir_hash_params = {
1423                 .name = fdir_hash_name,
1424                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1425                 .key_len = sizeof(union ixgbe_atr_input),
1426                 .hash_func = rte_hash_crc,
1427                 .hash_func_init_val = 0,
1428                 .socket_id = rte_socket_id(),
1429         };
1430
1431         TAILQ_INIT(&fdir_info->fdir_list);
1432         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1433                  "fdir_%s", eth_dev->device->name);
1434         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1435         if (!fdir_info->hash_handle) {
1436                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1437                 return -EINVAL;
1438         }
1439         fdir_info->hash_map = rte_zmalloc("ixgbe",
1440                                           sizeof(struct ixgbe_fdir_filter *) *
1441                                           IXGBE_MAX_FDIR_FILTER_NUM,
1442                                           0);
1443         if (!fdir_info->hash_map) {
1444                 PMD_INIT_LOG(ERR,
1445                              "Failed to allocate memory for fdir hash map!");
1446                 return -ENOMEM;
1447         }
1448         fdir_info->mask_added = FALSE;
1449
1450         return 0;
1451 }
1452
1453 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1454 {
1455         struct ixgbe_l2_tn_info *l2_tn_info =
1456                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1457         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1458         struct rte_hash_parameters l2_tn_hash_params = {
1459                 .name = l2_tn_hash_name,
1460                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1461                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1462                 .hash_func = rte_hash_crc,
1463                 .hash_func_init_val = 0,
1464                 .socket_id = rte_socket_id(),
1465         };
1466
1467         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1468         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1469                  "l2_tn_%s", eth_dev->device->name);
1470         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1471         if (!l2_tn_info->hash_handle) {
1472                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1473                 return -EINVAL;
1474         }
1475         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1476                                    sizeof(struct ixgbe_l2_tn_filter *) *
1477                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1478                                    0);
1479         if (!l2_tn_info->hash_map) {
1480                 PMD_INIT_LOG(ERR,
1481                         "Failed to allocate memory for L2 TN hash map!");
1482                 return -ENOMEM;
1483         }
1484         l2_tn_info->e_tag_en = FALSE;
1485         l2_tn_info->e_tag_fwd_en = FALSE;
1486         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1487
1488         return 0;
1489 }
1490 /*
1491  * Negotiate mailbox API version with the PF.
1492  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1493  * Then we try to negotiate starting with the most recent one.
1494  * If all negotiation attempts fail, then we will proceed with
1495  * the default one (ixgbe_mbox_api_10).
1496  */
1497 static void
1498 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1499 {
1500         int32_t i;
1501
1502         /* start with highest supported, proceed down */
1503         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1504                 ixgbe_mbox_api_12,
1505                 ixgbe_mbox_api_11,
1506                 ixgbe_mbox_api_10,
1507         };
1508
1509         for (i = 0;
1510                         i != RTE_DIM(sup_ver) &&
1511                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1512                         i++)
1513                 ;
1514 }
1515
1516 static void
1517 generate_random_mac_addr(struct ether_addr *mac_addr)
1518 {
1519         uint64_t random;
1520
1521         /* Set Organizationally Unique Identifier (OUI) prefix. */
1522         mac_addr->addr_bytes[0] = 0x00;
1523         mac_addr->addr_bytes[1] = 0x09;
1524         mac_addr->addr_bytes[2] = 0xC0;
1525         /* Force indication of locally assigned MAC address. */
1526         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1527         /* Generate the last 3 bytes of the MAC address with a random number. */
1528         random = rte_rand();
1529         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1530 }
1531
1532 /*
1533  * Virtual Function device init
1534  */
1535 static int
1536 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1537 {
1538         int diag;
1539         uint32_t tc, tcs;
1540         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1541         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1542         struct ixgbe_hw *hw =
1543                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1544         struct ixgbe_vfta *shadow_vfta =
1545                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1546         struct ixgbe_hwstrip *hwstrip =
1547                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1548         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1549
1550         PMD_INIT_FUNC_TRACE();
1551
1552         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1553         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1554         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1555
1556         /* for secondary processes, we don't initialise any further as primary
1557          * has already done this work. Only check we don't need a different
1558          * RX function
1559          */
1560         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1561                 struct ixgbe_tx_queue *txq;
1562                 /* TX queue function in primary, set by last queue initialized
1563                  * Tx queue may not initialized by primary process
1564                  */
1565                 if (eth_dev->data->tx_queues) {
1566                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1567                         ixgbe_set_tx_function(eth_dev, txq);
1568                 } else {
1569                         /* Use default TX function if we get here */
1570                         PMD_INIT_LOG(NOTICE,
1571                                      "No TX queues configured yet. Using default TX function.");
1572                 }
1573
1574                 ixgbe_set_rx_function(eth_dev);
1575
1576                 return 0;
1577         }
1578
1579         rte_eth_copy_pci_info(eth_dev, pci_dev);
1580
1581         hw->device_id = pci_dev->id.device_id;
1582         hw->vendor_id = pci_dev->id.vendor_id;
1583         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1584
1585         /* initialize the vfta */
1586         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1587
1588         /* initialize the hw strip bitmap*/
1589         memset(hwstrip, 0, sizeof(*hwstrip));
1590
1591         /* Initialize the shared code (base driver) */
1592         diag = ixgbe_init_shared_code(hw);
1593         if (diag != IXGBE_SUCCESS) {
1594                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1595                 return -EIO;
1596         }
1597
1598         /* init_mailbox_params */
1599         hw->mbx.ops.init_params(hw);
1600
1601         /* Reset the hw statistics */
1602         ixgbevf_dev_stats_reset(eth_dev);
1603
1604         /* Disable the interrupts for VF */
1605         ixgbevf_intr_disable(hw);
1606
1607         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1608         diag = hw->mac.ops.reset_hw(hw);
1609
1610         /*
1611          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1612          * the underlying PF driver has not assigned a MAC address to the VF.
1613          * In this case, assign a random MAC address.
1614          */
1615         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1616                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1617                 return diag;
1618         }
1619
1620         /* negotiate mailbox API version to use with the PF. */
1621         ixgbevf_negotiate_api(hw);
1622
1623         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1624         ixgbevf_get_queues(hw, &tcs, &tc);
1625
1626         /* Allocate memory for storing MAC addresses */
1627         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1628                                                hw->mac.num_rar_entries, 0);
1629         if (eth_dev->data->mac_addrs == NULL) {
1630                 PMD_INIT_LOG(ERR,
1631                              "Failed to allocate %u bytes needed to store "
1632                              "MAC addresses",
1633                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1634                 return -ENOMEM;
1635         }
1636
1637         /* Generate a random MAC address, if none was assigned by PF. */
1638         if (is_zero_ether_addr(perm_addr)) {
1639                 generate_random_mac_addr(perm_addr);
1640                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1641                 if (diag) {
1642                         rte_free(eth_dev->data->mac_addrs);
1643                         eth_dev->data->mac_addrs = NULL;
1644                         return diag;
1645                 }
1646                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1647                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1648                              "%02x:%02x:%02x:%02x:%02x:%02x",
1649                              perm_addr->addr_bytes[0],
1650                              perm_addr->addr_bytes[1],
1651                              perm_addr->addr_bytes[2],
1652                              perm_addr->addr_bytes[3],
1653                              perm_addr->addr_bytes[4],
1654                              perm_addr->addr_bytes[5]);
1655         }
1656
1657         /* Copy the permanent MAC address */
1658         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1659
1660         /* reset the hardware with the new settings */
1661         diag = hw->mac.ops.start_hw(hw);
1662         switch (diag) {
1663         case  0:
1664                 break;
1665
1666         default:
1667                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1668                 return -EIO;
1669         }
1670
1671         rte_intr_callback_register(intr_handle,
1672                                    ixgbevf_dev_interrupt_handler, eth_dev);
1673         rte_intr_enable(intr_handle);
1674         ixgbevf_intr_enable(hw);
1675
1676         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1677                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1678                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1679
1680         return 0;
1681 }
1682
1683 /* Virtual Function device uninit */
1684
1685 static int
1686 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1687 {
1688         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1689         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1690         struct ixgbe_hw *hw;
1691
1692         PMD_INIT_FUNC_TRACE();
1693
1694         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1695                 return -EPERM;
1696
1697         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1698
1699         if (hw->adapter_stopped == 0)
1700                 ixgbevf_dev_close(eth_dev);
1701
1702         eth_dev->dev_ops = NULL;
1703         eth_dev->rx_pkt_burst = NULL;
1704         eth_dev->tx_pkt_burst = NULL;
1705
1706         /* Disable the interrupts for VF */
1707         ixgbevf_intr_disable(hw);
1708
1709         rte_free(eth_dev->data->mac_addrs);
1710         eth_dev->data->mac_addrs = NULL;
1711
1712         rte_intr_disable(intr_handle);
1713         rte_intr_callback_unregister(intr_handle,
1714                                      ixgbevf_dev_interrupt_handler, eth_dev);
1715
1716         return 0;
1717 }
1718
1719 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1720         struct rte_pci_device *pci_dev)
1721 {
1722         return rte_eth_dev_pci_generic_probe(pci_dev,
1723                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1724 }
1725
1726 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1727 {
1728         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1729 }
1730
1731 static struct rte_pci_driver rte_ixgbe_pmd = {
1732         .id_table = pci_id_ixgbe_map,
1733         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1734                      RTE_PCI_DRV_IOVA_AS_VA,
1735         .probe = eth_ixgbe_pci_probe,
1736         .remove = eth_ixgbe_pci_remove,
1737 };
1738
1739 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1740         struct rte_pci_device *pci_dev)
1741 {
1742         return rte_eth_dev_pci_generic_probe(pci_dev,
1743                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1744 }
1745
1746 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1747 {
1748         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1749 }
1750
1751 /*
1752  * virtual function driver struct
1753  */
1754 static struct rte_pci_driver rte_ixgbevf_pmd = {
1755         .id_table = pci_id_ixgbevf_map,
1756         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1757         .probe = eth_ixgbevf_pci_probe,
1758         .remove = eth_ixgbevf_pci_remove,
1759 };
1760
1761 static int
1762 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1763 {
1764         struct ixgbe_hw *hw =
1765                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1766         struct ixgbe_vfta *shadow_vfta =
1767                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1768         uint32_t vfta;
1769         uint32_t vid_idx;
1770         uint32_t vid_bit;
1771
1772         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1773         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1774         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1775         if (on)
1776                 vfta |= vid_bit;
1777         else
1778                 vfta &= ~vid_bit;
1779         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1780
1781         /* update local VFTA copy */
1782         shadow_vfta->vfta[vid_idx] = vfta;
1783
1784         return 0;
1785 }
1786
1787 static void
1788 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1789 {
1790         if (on)
1791                 ixgbe_vlan_hw_strip_enable(dev, queue);
1792         else
1793                 ixgbe_vlan_hw_strip_disable(dev, queue);
1794 }
1795
1796 static int
1797 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1798                     enum rte_vlan_type vlan_type,
1799                     uint16_t tpid)
1800 {
1801         struct ixgbe_hw *hw =
1802                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1803         int ret = 0;
1804         uint32_t reg;
1805         uint32_t qinq;
1806
1807         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1808         qinq &= IXGBE_DMATXCTL_GDV;
1809
1810         switch (vlan_type) {
1811         case ETH_VLAN_TYPE_INNER:
1812                 if (qinq) {
1813                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1814                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1815                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1816                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1817                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1818                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1819                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1820                 } else {
1821                         ret = -ENOTSUP;
1822                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1823                                     " by single VLAN");
1824                 }
1825                 break;
1826         case ETH_VLAN_TYPE_OUTER:
1827                 if (qinq) {
1828                         /* Only the high 16-bits is valid */
1829                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1830                                         IXGBE_EXVET_VET_EXT_SHIFT);
1831                 } else {
1832                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1833                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1834                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1835                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1836                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1837                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1838                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1839                 }
1840
1841                 break;
1842         default:
1843                 ret = -EINVAL;
1844                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1845                 break;
1846         }
1847
1848         return ret;
1849 }
1850
1851 void
1852 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1853 {
1854         struct ixgbe_hw *hw =
1855                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1856         uint32_t vlnctrl;
1857
1858         PMD_INIT_FUNC_TRACE();
1859
1860         /* Filter Table Disable */
1861         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1862         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1863
1864         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1865 }
1866
1867 void
1868 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1869 {
1870         struct ixgbe_hw *hw =
1871                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872         struct ixgbe_vfta *shadow_vfta =
1873                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1874         uint32_t vlnctrl;
1875         uint16_t i;
1876
1877         PMD_INIT_FUNC_TRACE();
1878
1879         /* Filter Table Enable */
1880         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1881         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1882         vlnctrl |= IXGBE_VLNCTRL_VFE;
1883
1884         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1885
1886         /* write whatever is in local vfta copy */
1887         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1888                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1889 }
1890
1891 static void
1892 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1893 {
1894         struct ixgbe_hwstrip *hwstrip =
1895                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1896         struct ixgbe_rx_queue *rxq;
1897
1898         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1899                 return;
1900
1901         if (on)
1902                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1903         else
1904                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1905
1906         if (queue >= dev->data->nb_rx_queues)
1907                 return;
1908
1909         rxq = dev->data->rx_queues[queue];
1910
1911         if (on)
1912                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1913         else
1914                 rxq->vlan_flags = PKT_RX_VLAN;
1915 }
1916
1917 static void
1918 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1919 {
1920         struct ixgbe_hw *hw =
1921                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         uint32_t ctrl;
1923
1924         PMD_INIT_FUNC_TRACE();
1925
1926         if (hw->mac.type == ixgbe_mac_82598EB) {
1927                 /* No queue level support */
1928                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1929                 return;
1930         }
1931
1932         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1933         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1934         ctrl &= ~IXGBE_RXDCTL_VME;
1935         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1936
1937         /* record those setting for HW strip per queue */
1938         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1939 }
1940
1941 static void
1942 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1943 {
1944         struct ixgbe_hw *hw =
1945                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1946         uint32_t ctrl;
1947
1948         PMD_INIT_FUNC_TRACE();
1949
1950         if (hw->mac.type == ixgbe_mac_82598EB) {
1951                 /* No queue level supported */
1952                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1953                 return;
1954         }
1955
1956         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1957         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1958         ctrl |= IXGBE_RXDCTL_VME;
1959         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1960
1961         /* record those setting for HW strip per queue */
1962         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1963 }
1964
1965 void
1966 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1967 {
1968         struct ixgbe_hw *hw =
1969                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1970         uint32_t ctrl;
1971         uint16_t i;
1972         struct ixgbe_rx_queue *rxq;
1973
1974         PMD_INIT_FUNC_TRACE();
1975
1976         if (hw->mac.type == ixgbe_mac_82598EB) {
1977                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1978                 ctrl &= ~IXGBE_VLNCTRL_VME;
1979                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1980         } else {
1981                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1982                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1983                         rxq = dev->data->rx_queues[i];
1984                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1985                         ctrl &= ~IXGBE_RXDCTL_VME;
1986                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1987
1988                         /* record those setting for HW strip per queue */
1989                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1990                 }
1991         }
1992 }
1993
1994 void
1995 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1996 {
1997         struct ixgbe_hw *hw =
1998                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1999         uint32_t ctrl;
2000         uint16_t i;
2001         struct ixgbe_rx_queue *rxq;
2002
2003         PMD_INIT_FUNC_TRACE();
2004
2005         if (hw->mac.type == ixgbe_mac_82598EB) {
2006                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2007                 ctrl |= IXGBE_VLNCTRL_VME;
2008                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2009         } else {
2010                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2011                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2012                         rxq = dev->data->rx_queues[i];
2013                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2014                         ctrl |= IXGBE_RXDCTL_VME;
2015                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2016
2017                         /* record those setting for HW strip per queue */
2018                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2019                 }
2020         }
2021 }
2022
2023 static void
2024 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2025 {
2026         struct ixgbe_hw *hw =
2027                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2028         uint32_t ctrl;
2029
2030         PMD_INIT_FUNC_TRACE();
2031
2032         /* DMATXCTRL: Geric Double VLAN Disable */
2033         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2034         ctrl &= ~IXGBE_DMATXCTL_GDV;
2035         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2036
2037         /* CTRL_EXT: Global Double VLAN Disable */
2038         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2039         ctrl &= ~IXGBE_EXTENDED_VLAN;
2040         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2041
2042 }
2043
2044 static void
2045 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2046 {
2047         struct ixgbe_hw *hw =
2048                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2049         uint32_t ctrl;
2050
2051         PMD_INIT_FUNC_TRACE();
2052
2053         /* DMATXCTRL: Geric Double VLAN Enable */
2054         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2055         ctrl |= IXGBE_DMATXCTL_GDV;
2056         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2057
2058         /* CTRL_EXT: Global Double VLAN Enable */
2059         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2060         ctrl |= IXGBE_EXTENDED_VLAN;
2061         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2062
2063         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2064         if (hw->mac.type == ixgbe_mac_X550 ||
2065             hw->mac.type == ixgbe_mac_X550EM_x ||
2066             hw->mac.type == ixgbe_mac_X550EM_a) {
2067                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2068                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2069                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2070         }
2071
2072         /*
2073          * VET EXT field in the EXVET register = 0x8100 by default
2074          * So no need to change. Same to VT field of DMATXCTL register
2075          */
2076 }
2077
2078 static int
2079 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2080 {
2081         if (mask & ETH_VLAN_STRIP_MASK) {
2082                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2083                         ixgbe_vlan_hw_strip_enable_all(dev);
2084                 else
2085                         ixgbe_vlan_hw_strip_disable_all(dev);
2086         }
2087
2088         if (mask & ETH_VLAN_FILTER_MASK) {
2089                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2090                         ixgbe_vlan_hw_filter_enable(dev);
2091                 else
2092                         ixgbe_vlan_hw_filter_disable(dev);
2093         }
2094
2095         if (mask & ETH_VLAN_EXTEND_MASK) {
2096                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2097                         ixgbe_vlan_hw_extend_enable(dev);
2098                 else
2099                         ixgbe_vlan_hw_extend_disable(dev);
2100         }
2101
2102         return 0;
2103 }
2104
2105 static void
2106 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2107 {
2108         struct ixgbe_hw *hw =
2109                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2110         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2111         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2112
2113         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2114         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2115 }
2116
2117 static int
2118 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2119 {
2120         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2121
2122         switch (nb_rx_q) {
2123         case 1:
2124         case 2:
2125                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2126                 break;
2127         case 4:
2128                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2129                 break;
2130         default:
2131                 return -EINVAL;
2132         }
2133
2134         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2135                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2136         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2137                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2138         return 0;
2139 }
2140
2141 static int
2142 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2143 {
2144         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2145         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2146         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2147         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2148
2149         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2150                 /* check multi-queue mode */
2151                 switch (dev_conf->rxmode.mq_mode) {
2152                 case ETH_MQ_RX_VMDQ_DCB:
2153                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2154                         break;
2155                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2156                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2157                         PMD_INIT_LOG(ERR, "SRIOV active,"
2158                                         " unsupported mq_mode rx %d.",
2159                                         dev_conf->rxmode.mq_mode);
2160                         return -EINVAL;
2161                 case ETH_MQ_RX_RSS:
2162                 case ETH_MQ_RX_VMDQ_RSS:
2163                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2164                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2165                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2166                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2167                                                 " invalid queue number"
2168                                                 " for VMDQ RSS, allowed"
2169                                                 " value are 1, 2 or 4.");
2170                                         return -EINVAL;
2171                                 }
2172                         break;
2173                 case ETH_MQ_RX_VMDQ_ONLY:
2174                 case ETH_MQ_RX_NONE:
2175                         /* if nothing mq mode configure, use default scheme */
2176                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2177                         break;
2178                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2179                         /* SRIOV only works in VMDq enable mode */
2180                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2181                                         " wrong mq_mode rx %d.",
2182                                         dev_conf->rxmode.mq_mode);
2183                         return -EINVAL;
2184                 }
2185
2186                 switch (dev_conf->txmode.mq_mode) {
2187                 case ETH_MQ_TX_VMDQ_DCB:
2188                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2189                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2190                         break;
2191                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2192                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2193                         break;
2194                 }
2195
2196                 /* check valid queue number */
2197                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2198                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2199                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2200                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2201                                         " must be less than or equal to %d.",
2202                                         nb_rx_q, nb_tx_q,
2203                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2204                         return -EINVAL;
2205                 }
2206         } else {
2207                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2208                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2209                                           " not supported.");
2210                         return -EINVAL;
2211                 }
2212                 /* check configuration for vmdb+dcb mode */
2213                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2214                         const struct rte_eth_vmdq_dcb_conf *conf;
2215
2216                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2217                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2218                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2219                                 return -EINVAL;
2220                         }
2221                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2222                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2223                                conf->nb_queue_pools == ETH_32_POOLS)) {
2224                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2225                                                 " nb_queue_pools must be %d or %d.",
2226                                                 ETH_16_POOLS, ETH_32_POOLS);
2227                                 return -EINVAL;
2228                         }
2229                 }
2230                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2231                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2232
2233                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2234                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2235                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2236                                 return -EINVAL;
2237                         }
2238                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2239                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2240                                conf->nb_queue_pools == ETH_32_POOLS)) {
2241                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2242                                                 " nb_queue_pools != %d and"
2243                                                 " nb_queue_pools != %d.",
2244                                                 ETH_16_POOLS, ETH_32_POOLS);
2245                                 return -EINVAL;
2246                         }
2247                 }
2248
2249                 /* For DCB mode check our configuration before we go further */
2250                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2251                         const struct rte_eth_dcb_rx_conf *conf;
2252
2253                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2254                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2255                                                  IXGBE_DCB_NB_QUEUES);
2256                                 return -EINVAL;
2257                         }
2258                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2259                         if (!(conf->nb_tcs == ETH_4_TCS ||
2260                                conf->nb_tcs == ETH_8_TCS)) {
2261                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2262                                                 " and nb_tcs != %d.",
2263                                                 ETH_4_TCS, ETH_8_TCS);
2264                                 return -EINVAL;
2265                         }
2266                 }
2267
2268                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2269                         const struct rte_eth_dcb_tx_conf *conf;
2270
2271                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2272                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2273                                                  IXGBE_DCB_NB_QUEUES);
2274                                 return -EINVAL;
2275                         }
2276                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2277                         if (!(conf->nb_tcs == ETH_4_TCS ||
2278                                conf->nb_tcs == ETH_8_TCS)) {
2279                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2280                                                 " and nb_tcs != %d.",
2281                                                 ETH_4_TCS, ETH_8_TCS);
2282                                 return -EINVAL;
2283                         }
2284                 }
2285
2286                 /*
2287                  * When DCB/VT is off, maximum number of queues changes,
2288                  * except for 82598EB, which remains constant.
2289                  */
2290                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2291                                 hw->mac.type != ixgbe_mac_82598EB) {
2292                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2293                                 PMD_INIT_LOG(ERR,
2294                                              "Neither VT nor DCB are enabled, "
2295                                              "nb_tx_q > %d.",
2296                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2297                                 return -EINVAL;
2298                         }
2299                 }
2300         }
2301         return 0;
2302 }
2303
2304 static int
2305 ixgbe_dev_configure(struct rte_eth_dev *dev)
2306 {
2307         struct ixgbe_interrupt *intr =
2308                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2309         struct ixgbe_adapter *adapter =
2310                 (struct ixgbe_adapter *)dev->data->dev_private;
2311         int ret;
2312
2313         PMD_INIT_FUNC_TRACE();
2314         /* multipe queue mode checking */
2315         ret  = ixgbe_check_mq_mode(dev);
2316         if (ret != 0) {
2317                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2318                             ret);
2319                 return ret;
2320         }
2321
2322         /* set flag to update link status after init */
2323         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2324
2325         /*
2326          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2327          * allocation or vector Rx preconditions we will reset it.
2328          */
2329         adapter->rx_bulk_alloc_allowed = true;
2330         adapter->rx_vec_allowed = true;
2331
2332         return 0;
2333 }
2334
2335 static void
2336 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2337 {
2338         struct ixgbe_hw *hw =
2339                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2340         struct ixgbe_interrupt *intr =
2341                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2342         uint32_t gpie;
2343
2344         /* only set up it on X550EM_X */
2345         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2346                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2347                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2348                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2349                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2350                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2351         }
2352 }
2353
2354 int
2355 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2356                         uint16_t tx_rate, uint64_t q_msk)
2357 {
2358         struct ixgbe_hw *hw;
2359         struct ixgbe_vf_info *vfinfo;
2360         struct rte_eth_link link;
2361         uint8_t  nb_q_per_pool;
2362         uint32_t queue_stride;
2363         uint32_t queue_idx, idx = 0, vf_idx;
2364         uint32_t queue_end;
2365         uint16_t total_rate = 0;
2366         struct rte_pci_device *pci_dev;
2367
2368         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2369         rte_eth_link_get_nowait(dev->data->port_id, &link);
2370
2371         if (vf >= pci_dev->max_vfs)
2372                 return -EINVAL;
2373
2374         if (tx_rate > link.link_speed)
2375                 return -EINVAL;
2376
2377         if (q_msk == 0)
2378                 return 0;
2379
2380         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2381         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2382         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2383         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2384         queue_idx = vf * queue_stride;
2385         queue_end = queue_idx + nb_q_per_pool - 1;
2386         if (queue_end >= hw->mac.max_tx_queues)
2387                 return -EINVAL;
2388
2389         if (vfinfo) {
2390                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2391                         if (vf_idx == vf)
2392                                 continue;
2393                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2394                                 idx++)
2395                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2396                 }
2397         } else {
2398                 return -EINVAL;
2399         }
2400
2401         /* Store tx_rate for this vf. */
2402         for (idx = 0; idx < nb_q_per_pool; idx++) {
2403                 if (((uint64_t)0x1 << idx) & q_msk) {
2404                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2405                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2406                         total_rate += tx_rate;
2407                 }
2408         }
2409
2410         if (total_rate > dev->data->dev_link.link_speed) {
2411                 /* Reset stored TX rate of the VF if it causes exceed
2412                  * link speed.
2413                  */
2414                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2415                 return -EINVAL;
2416         }
2417
2418         /* Set RTTBCNRC of each queue/pool for vf X  */
2419         for (; queue_idx <= queue_end; queue_idx++) {
2420                 if (0x1 & q_msk)
2421                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2422                 q_msk = q_msk >> 1;
2423         }
2424
2425         return 0;
2426 }
2427
2428 /*
2429  * Configure device link speed and setup link.
2430  * It returns 0 on success.
2431  */
2432 static int
2433 ixgbe_dev_start(struct rte_eth_dev *dev)
2434 {
2435         struct ixgbe_hw *hw =
2436                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2437         struct ixgbe_vf_info *vfinfo =
2438                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2439         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2440         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2441         uint32_t intr_vector = 0;
2442         int err, link_up = 0, negotiate = 0;
2443         uint32_t speed = 0;
2444         int mask = 0;
2445         int status;
2446         uint16_t vf, idx;
2447         uint32_t *link_speeds;
2448         struct ixgbe_tm_conf *tm_conf =
2449                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2450
2451         PMD_INIT_FUNC_TRACE();
2452
2453         /* IXGBE devices don't support:
2454         *    - half duplex (checked afterwards for valid speeds)
2455         *    - fixed speed: TODO implement
2456         */
2457         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2458                 PMD_INIT_LOG(ERR,
2459                 "Invalid link_speeds for port %u, fix speed not supported",
2460                                 dev->data->port_id);
2461                 return -EINVAL;
2462         }
2463
2464         /* disable uio/vfio intr/eventfd mapping */
2465         rte_intr_disable(intr_handle);
2466
2467         /* stop adapter */
2468         hw->adapter_stopped = 0;
2469         ixgbe_stop_adapter(hw);
2470
2471         /* reinitialize adapter
2472          * this calls reset and start
2473          */
2474         status = ixgbe_pf_reset_hw(hw);
2475         if (status != 0)
2476                 return -1;
2477         hw->mac.ops.start_hw(hw);
2478         hw->mac.get_link_status = true;
2479
2480         /* configure PF module if SRIOV enabled */
2481         ixgbe_pf_host_configure(dev);
2482
2483         ixgbe_dev_phy_intr_setup(dev);
2484
2485         /* check and configure queue intr-vector mapping */
2486         if ((rte_intr_cap_multiple(intr_handle) ||
2487              !RTE_ETH_DEV_SRIOV(dev).active) &&
2488             dev->data->dev_conf.intr_conf.rxq != 0) {
2489                 intr_vector = dev->data->nb_rx_queues;
2490                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2491                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2492                                         IXGBE_MAX_INTR_QUEUE_NUM);
2493                         return -ENOTSUP;
2494                 }
2495                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2496                         return -1;
2497         }
2498
2499         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2500                 intr_handle->intr_vec =
2501                         rte_zmalloc("intr_vec",
2502                                     dev->data->nb_rx_queues * sizeof(int), 0);
2503                 if (intr_handle->intr_vec == NULL) {
2504                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2505                                      " intr_vec", dev->data->nb_rx_queues);
2506                         return -ENOMEM;
2507                 }
2508         }
2509
2510         /* confiugre msix for sleep until rx interrupt */
2511         ixgbe_configure_msix(dev);
2512
2513         /* initialize transmission unit */
2514         ixgbe_dev_tx_init(dev);
2515
2516         /* This can fail when allocating mbufs for descriptor rings */
2517         err = ixgbe_dev_rx_init(dev);
2518         if (err) {
2519                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2520                 goto error;
2521         }
2522
2523         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2524                 ETH_VLAN_EXTEND_MASK;
2525         err = ixgbe_vlan_offload_set(dev, mask);
2526         if (err) {
2527                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2528                 goto error;
2529         }
2530
2531         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2532                 /* Enable vlan filtering for VMDq */
2533                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2534         }
2535
2536         /* Configure DCB hw */
2537         ixgbe_configure_dcb(dev);
2538
2539         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2540                 err = ixgbe_fdir_configure(dev);
2541                 if (err)
2542                         goto error;
2543         }
2544
2545         /* Restore vf rate limit */
2546         if (vfinfo != NULL) {
2547                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2548                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2549                                 if (vfinfo[vf].tx_rate[idx] != 0)
2550                                         ixgbe_set_vf_rate_limit(
2551                                                 dev, vf,
2552                                                 vfinfo[vf].tx_rate[idx],
2553                                                 1 << idx);
2554         }
2555
2556         ixgbe_restore_statistics_mapping(dev);
2557
2558         err = ixgbe_dev_rxtx_start(dev);
2559         if (err < 0) {
2560                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2561                 goto error;
2562         }
2563
2564         /* Skip link setup if loopback mode is enabled for 82599. */
2565         if (hw->mac.type == ixgbe_mac_82599EB &&
2566                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2567                 goto skip_link_setup;
2568
2569         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2570                 err = hw->mac.ops.setup_sfp(hw);
2571                 if (err)
2572                         goto error;
2573         }
2574
2575         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2576                 /* Turn on the copper */
2577                 ixgbe_set_phy_power(hw, true);
2578         } else {
2579                 /* Turn on the laser */
2580                 ixgbe_enable_tx_laser(hw);
2581         }
2582
2583         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2584         if (err)
2585                 goto error;
2586         dev->data->dev_link.link_status = link_up;
2587
2588         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2589         if (err)
2590                 goto error;
2591
2592         link_speeds = &dev->data->dev_conf.link_speeds;
2593         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2594                         ETH_LINK_SPEED_10G)) {
2595                 PMD_INIT_LOG(ERR, "Invalid link setting");
2596                 goto error;
2597         }
2598
2599         speed = 0x0;
2600         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2601                 switch (hw->mac.type) {
2602                 case ixgbe_mac_82598EB:
2603                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2604                         break;
2605                 case ixgbe_mac_82599EB:
2606                 case ixgbe_mac_X540:
2607                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2608                         break;
2609                 case ixgbe_mac_X550:
2610                 case ixgbe_mac_X550EM_x:
2611                 case ixgbe_mac_X550EM_a:
2612                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2613                         break;
2614                 default:
2615                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2616                 }
2617         } else {
2618                 if (*link_speeds & ETH_LINK_SPEED_10G)
2619                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2620                 if (*link_speeds & ETH_LINK_SPEED_1G)
2621                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2622                 if (*link_speeds & ETH_LINK_SPEED_100M)
2623                         speed |= IXGBE_LINK_SPEED_100_FULL;
2624         }
2625
2626         err = ixgbe_setup_link(hw, speed, link_up);
2627         if (err)
2628                 goto error;
2629
2630 skip_link_setup:
2631
2632         if (rte_intr_allow_others(intr_handle)) {
2633                 /* check if lsc interrupt is enabled */
2634                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2635                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2636                 else
2637                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2638                 ixgbe_dev_macsec_interrupt_setup(dev);
2639         } else {
2640                 rte_intr_callback_unregister(intr_handle,
2641                                              ixgbe_dev_interrupt_handler, dev);
2642                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2643                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2644                                      " no intr multiplex");
2645         }
2646
2647         /* check if rxq interrupt is enabled */
2648         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2649             rte_intr_dp_is_en(intr_handle))
2650                 ixgbe_dev_rxq_interrupt_setup(dev);
2651
2652         /* enable uio/vfio intr/eventfd mapping */
2653         rte_intr_enable(intr_handle);
2654
2655         /* resume enabled intr since hw reset */
2656         ixgbe_enable_intr(dev);
2657         ixgbe_l2_tunnel_conf(dev);
2658         ixgbe_filter_restore(dev);
2659
2660         if (tm_conf->root && !tm_conf->committed)
2661                 PMD_DRV_LOG(WARNING,
2662                             "please call hierarchy_commit() "
2663                             "before starting the port");
2664
2665         return 0;
2666
2667 error:
2668         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2669         ixgbe_dev_clear_queues(dev);
2670         return -EIO;
2671 }
2672
2673 /*
2674  * Stop device: disable rx and tx functions to allow for reconfiguring.
2675  */
2676 static void
2677 ixgbe_dev_stop(struct rte_eth_dev *dev)
2678 {
2679         struct rte_eth_link link;
2680         struct ixgbe_hw *hw =
2681                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2682         struct ixgbe_vf_info *vfinfo =
2683                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2684         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2685         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2686         int vf;
2687         struct ixgbe_tm_conf *tm_conf =
2688                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2689
2690         PMD_INIT_FUNC_TRACE();
2691
2692         /* disable interrupts */
2693         ixgbe_disable_intr(hw);
2694
2695         /* reset the NIC */
2696         ixgbe_pf_reset_hw(hw);
2697         hw->adapter_stopped = 0;
2698
2699         /* stop adapter */
2700         ixgbe_stop_adapter(hw);
2701
2702         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2703                 vfinfo[vf].clear_to_send = false;
2704
2705         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2706                 /* Turn off the copper */
2707                 ixgbe_set_phy_power(hw, false);
2708         } else {
2709                 /* Turn off the laser */
2710                 ixgbe_disable_tx_laser(hw);
2711         }
2712
2713         ixgbe_dev_clear_queues(dev);
2714
2715         /* Clear stored conf */
2716         dev->data->scattered_rx = 0;
2717         dev->data->lro = 0;
2718
2719         /* Clear recorded link status */
2720         memset(&link, 0, sizeof(link));
2721         rte_eth_linkstatus_set(dev, &link);
2722
2723         if (!rte_intr_allow_others(intr_handle))
2724                 /* resume to the default handler */
2725                 rte_intr_callback_register(intr_handle,
2726                                            ixgbe_dev_interrupt_handler,
2727                                            (void *)dev);
2728
2729         /* Clean datapath event and queue/vec mapping */
2730         rte_intr_efd_disable(intr_handle);
2731         if (intr_handle->intr_vec != NULL) {
2732                 rte_free(intr_handle->intr_vec);
2733                 intr_handle->intr_vec = NULL;
2734         }
2735
2736         /* reset hierarchy commit */
2737         tm_conf->committed = false;
2738 }
2739
2740 /*
2741  * Set device link up: enable tx.
2742  */
2743 static int
2744 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2745 {
2746         struct ixgbe_hw *hw =
2747                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2748         if (hw->mac.type == ixgbe_mac_82599EB) {
2749 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2750                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2751                         /* Not suported in bypass mode */
2752                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2753                                      "by device id 0x%x", hw->device_id);
2754                         return -ENOTSUP;
2755                 }
2756 #endif
2757         }
2758
2759         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2760                 /* Turn on the copper */
2761                 ixgbe_set_phy_power(hw, true);
2762         } else {
2763                 /* Turn on the laser */
2764                 ixgbe_enable_tx_laser(hw);
2765         }
2766
2767         return 0;
2768 }
2769
2770 /*
2771  * Set device link down: disable tx.
2772  */
2773 static int
2774 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2775 {
2776         struct ixgbe_hw *hw =
2777                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2778         if (hw->mac.type == ixgbe_mac_82599EB) {
2779 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2780                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2781                         /* Not suported in bypass mode */
2782                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2783                                      "by device id 0x%x", hw->device_id);
2784                         return -ENOTSUP;
2785                 }
2786 #endif
2787         }
2788
2789         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2790                 /* Turn off the copper */
2791                 ixgbe_set_phy_power(hw, false);
2792         } else {
2793                 /* Turn off the laser */
2794                 ixgbe_disable_tx_laser(hw);
2795         }
2796
2797         return 0;
2798 }
2799
2800 /*
2801  * Reset and stop device.
2802  */
2803 static void
2804 ixgbe_dev_close(struct rte_eth_dev *dev)
2805 {
2806         struct ixgbe_hw *hw =
2807                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2808
2809         PMD_INIT_FUNC_TRACE();
2810
2811         ixgbe_pf_reset_hw(hw);
2812
2813         ixgbe_dev_stop(dev);
2814         hw->adapter_stopped = 1;
2815
2816         ixgbe_dev_free_queues(dev);
2817
2818         ixgbe_disable_pcie_master(hw);
2819
2820         /* reprogram the RAR[0] in case user changed it. */
2821         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2822 }
2823
2824 /*
2825  * Reset PF device.
2826  */
2827 static int
2828 ixgbe_dev_reset(struct rte_eth_dev *dev)
2829 {
2830         int ret;
2831
2832         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2833          * its VF to make them align with it. The detailed notification
2834          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2835          * To avoid unexpected behavior in VF, currently reset of PF with
2836          * SR-IOV activation is not supported. It might be supported later.
2837          */
2838         if (dev->data->sriov.active)
2839                 return -ENOTSUP;
2840
2841         ret = eth_ixgbe_dev_uninit(dev);
2842         if (ret)
2843                 return ret;
2844
2845         ret = eth_ixgbe_dev_init(dev);
2846
2847         return ret;
2848 }
2849
2850 static void
2851 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2852                            struct ixgbe_hw_stats *hw_stats,
2853                            struct ixgbe_macsec_stats *macsec_stats,
2854                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2855                            uint64_t *total_qprc, uint64_t *total_qprdc)
2856 {
2857         uint32_t bprc, lxon, lxoff, total;
2858         uint32_t delta_gprc = 0;
2859         unsigned i;
2860         /* Workaround for RX byte count not including CRC bytes when CRC
2861          * strip is enabled. CRC bytes are removed from counters when crc_strip
2862          * is disabled.
2863          */
2864         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2865                         IXGBE_HLREG0_RXCRCSTRP);
2866
2867         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2868         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2869         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2870         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2871
2872         for (i = 0; i < 8; i++) {
2873                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2874
2875                 /* global total per queue */
2876                 hw_stats->mpc[i] += mp;
2877                 /* Running comprehensive total for stats display */
2878                 *total_missed_rx += hw_stats->mpc[i];
2879                 if (hw->mac.type == ixgbe_mac_82598EB) {
2880                         hw_stats->rnbc[i] +=
2881                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2882                         hw_stats->pxonrxc[i] +=
2883                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2884                         hw_stats->pxoffrxc[i] +=
2885                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2886                 } else {
2887                         hw_stats->pxonrxc[i] +=
2888                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2889                         hw_stats->pxoffrxc[i] +=
2890                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2891                         hw_stats->pxon2offc[i] +=
2892                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2893                 }
2894                 hw_stats->pxontxc[i] +=
2895                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2896                 hw_stats->pxofftxc[i] +=
2897                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2898         }
2899         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2900                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2901                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2902                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2903
2904                 delta_gprc += delta_qprc;
2905
2906                 hw_stats->qprc[i] += delta_qprc;
2907                 hw_stats->qptc[i] += delta_qptc;
2908
2909                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2910                 hw_stats->qbrc[i] +=
2911                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2912                 if (crc_strip == 0)
2913                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2914
2915                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2916                 hw_stats->qbtc[i] +=
2917                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2918
2919                 hw_stats->qprdc[i] += delta_qprdc;
2920                 *total_qprdc += hw_stats->qprdc[i];
2921
2922                 *total_qprc += hw_stats->qprc[i];
2923                 *total_qbrc += hw_stats->qbrc[i];
2924         }
2925         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2926         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2927         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2928
2929         /*
2930          * An errata states that gprc actually counts good + missed packets:
2931          * Workaround to set gprc to summated queue packet receives
2932          */
2933         hw_stats->gprc = *total_qprc;
2934
2935         if (hw->mac.type != ixgbe_mac_82598EB) {
2936                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2937                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2938                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2939                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2940                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2941                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2942                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2943                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2944         } else {
2945                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2946                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2947                 /* 82598 only has a counter in the high register */
2948                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2949                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2950                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2951         }
2952         uint64_t old_tpr = hw_stats->tpr;
2953
2954         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2955         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2956
2957         if (crc_strip == 0)
2958                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2959
2960         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2961         hw_stats->gptc += delta_gptc;
2962         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2963         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2964
2965         /*
2966          * Workaround: mprc hardware is incorrectly counting
2967          * broadcasts, so for now we subtract those.
2968          */
2969         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2970         hw_stats->bprc += bprc;
2971         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2972         if (hw->mac.type == ixgbe_mac_82598EB)
2973                 hw_stats->mprc -= bprc;
2974
2975         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2976         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2977         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2978         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2979         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2980         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2981
2982         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2983         hw_stats->lxontxc += lxon;
2984         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2985         hw_stats->lxofftxc += lxoff;
2986         total = lxon + lxoff;
2987
2988         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2989         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2990         hw_stats->gptc -= total;
2991         hw_stats->mptc -= total;
2992         hw_stats->ptc64 -= total;
2993         hw_stats->gotc -= total * ETHER_MIN_LEN;
2994
2995         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2996         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2997         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2998         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2999         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3000         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3001         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3002         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3003         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3004         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3005         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3006         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3007         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3008         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3009         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3010         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3011         /* Only read FCOE on 82599 */
3012         if (hw->mac.type != ixgbe_mac_82598EB) {
3013                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3014                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3015                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3016                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3017                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3018         }
3019
3020         /* Flow Director Stats registers */
3021         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3022         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3023
3024         /* MACsec Stats registers */
3025         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3026         macsec_stats->out_pkts_encrypted +=
3027                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3028         macsec_stats->out_pkts_protected +=
3029                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3030         macsec_stats->out_octets_encrypted +=
3031                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3032         macsec_stats->out_octets_protected +=
3033                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3034         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3035         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3036         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3037         macsec_stats->in_pkts_unknownsci +=
3038                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3039         macsec_stats->in_octets_decrypted +=
3040                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3041         macsec_stats->in_octets_validated +=
3042                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3043         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3044         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3045         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3046         for (i = 0; i < 2; i++) {
3047                 macsec_stats->in_pkts_ok +=
3048                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3049                 macsec_stats->in_pkts_invalid +=
3050                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3051                 macsec_stats->in_pkts_notvalid +=
3052                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3053         }
3054         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3055         macsec_stats->in_pkts_notusingsa +=
3056                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3057 }
3058
3059 /*
3060  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3061  */
3062 static int
3063 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3064 {
3065         struct ixgbe_hw *hw =
3066                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3067         struct ixgbe_hw_stats *hw_stats =
3068                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3069         struct ixgbe_macsec_stats *macsec_stats =
3070                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3071                                 dev->data->dev_private);
3072         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3073         unsigned i;
3074
3075         total_missed_rx = 0;
3076         total_qbrc = 0;
3077         total_qprc = 0;
3078         total_qprdc = 0;
3079
3080         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3081                         &total_qbrc, &total_qprc, &total_qprdc);
3082
3083         if (stats == NULL)
3084                 return -EINVAL;
3085
3086         /* Fill out the rte_eth_stats statistics structure */
3087         stats->ipackets = total_qprc;
3088         stats->ibytes = total_qbrc;
3089         stats->opackets = hw_stats->gptc;
3090         stats->obytes = hw_stats->gotc;
3091
3092         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3093                 stats->q_ipackets[i] = hw_stats->qprc[i];
3094                 stats->q_opackets[i] = hw_stats->qptc[i];
3095                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3096                 stats->q_obytes[i] = hw_stats->qbtc[i];
3097                 stats->q_errors[i] = hw_stats->qprdc[i];
3098         }
3099
3100         /* Rx Errors */
3101         stats->imissed  = total_missed_rx;
3102         stats->ierrors  = hw_stats->crcerrs +
3103                           hw_stats->mspdc +
3104                           hw_stats->rlec +
3105                           hw_stats->ruc +
3106                           hw_stats->roc +
3107                           hw_stats->illerrc +
3108                           hw_stats->errbc +
3109                           hw_stats->rfc +
3110                           hw_stats->fccrc +
3111                           hw_stats->fclast;
3112
3113         /* Tx Errors */
3114         stats->oerrors  = 0;
3115         return 0;
3116 }
3117
3118 static void
3119 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3120 {
3121         struct ixgbe_hw_stats *stats =
3122                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3123
3124         /* HW registers are cleared on read */
3125         ixgbe_dev_stats_get(dev, NULL);
3126
3127         /* Reset software totals */
3128         memset(stats, 0, sizeof(*stats));
3129 }
3130
3131 /* This function calculates the number of xstats based on the current config */
3132 static unsigned
3133 ixgbe_xstats_calc_num(void) {
3134         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3135                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3136                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3137 }
3138
3139 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3140         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3141 {
3142         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3143         unsigned stat, i, count;
3144
3145         if (xstats_names != NULL) {
3146                 count = 0;
3147
3148                 /* Note: limit >= cnt_stats checked upstream
3149                  * in rte_eth_xstats_names()
3150                  */
3151
3152                 /* Extended stats from ixgbe_hw_stats */
3153                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3154                         snprintf(xstats_names[count].name,
3155                                 sizeof(xstats_names[count].name),
3156                                 "%s",
3157                                 rte_ixgbe_stats_strings[i].name);
3158                         count++;
3159                 }
3160
3161                 /* MACsec Stats */
3162                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3163                         snprintf(xstats_names[count].name,
3164                                 sizeof(xstats_names[count].name),
3165                                 "%s",
3166                                 rte_ixgbe_macsec_strings[i].name);
3167                         count++;
3168                 }
3169
3170                 /* RX Priority Stats */
3171                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3172                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3173                                 snprintf(xstats_names[count].name,
3174                                         sizeof(xstats_names[count].name),
3175                                         "rx_priority%u_%s", i,
3176                                         rte_ixgbe_rxq_strings[stat].name);
3177                                 count++;
3178                         }
3179                 }
3180
3181                 /* TX Priority Stats */
3182                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3183                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3184                                 snprintf(xstats_names[count].name,
3185                                         sizeof(xstats_names[count].name),
3186                                         "tx_priority%u_%s", i,
3187                                         rte_ixgbe_txq_strings[stat].name);
3188                                 count++;
3189                         }
3190                 }
3191         }
3192         return cnt_stats;
3193 }
3194
3195 static int ixgbe_dev_xstats_get_names_by_id(
3196         struct rte_eth_dev *dev,
3197         struct rte_eth_xstat_name *xstats_names,
3198         const uint64_t *ids,
3199         unsigned int limit)
3200 {
3201         if (!ids) {
3202                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3203                 unsigned int stat, i, count;
3204
3205                 if (xstats_names != NULL) {
3206                         count = 0;
3207
3208                         /* Note: limit >= cnt_stats checked upstream
3209                          * in rte_eth_xstats_names()
3210                          */
3211
3212                         /* Extended stats from ixgbe_hw_stats */
3213                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3214                                 snprintf(xstats_names[count].name,
3215                                         sizeof(xstats_names[count].name),
3216                                         "%s",
3217                                         rte_ixgbe_stats_strings[i].name);
3218                                 count++;
3219                         }
3220
3221                         /* MACsec Stats */
3222                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3223                                 snprintf(xstats_names[count].name,
3224                                         sizeof(xstats_names[count].name),
3225                                         "%s",
3226                                         rte_ixgbe_macsec_strings[i].name);
3227                                 count++;
3228                         }
3229
3230                         /* RX Priority Stats */
3231                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3232                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3233                                         snprintf(xstats_names[count].name,
3234                                             sizeof(xstats_names[count].name),
3235                                             "rx_priority%u_%s", i,
3236                                             rte_ixgbe_rxq_strings[stat].name);
3237                                         count++;
3238                                 }
3239                         }
3240
3241                         /* TX Priority Stats */
3242                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3243                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3244                                         snprintf(xstats_names[count].name,
3245                                             sizeof(xstats_names[count].name),
3246                                             "tx_priority%u_%s", i,
3247                                             rte_ixgbe_txq_strings[stat].name);
3248                                         count++;
3249                                 }
3250                         }
3251                 }
3252                 return cnt_stats;
3253         }
3254
3255         uint16_t i;
3256         uint16_t size = ixgbe_xstats_calc_num();
3257         struct rte_eth_xstat_name xstats_names_copy[size];
3258
3259         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3260                         size);
3261
3262         for (i = 0; i < limit; i++) {
3263                 if (ids[i] >= size) {
3264                         PMD_INIT_LOG(ERR, "id value isn't valid");
3265                         return -1;
3266                 }
3267                 strcpy(xstats_names[i].name,
3268                                 xstats_names_copy[ids[i]].name);
3269         }
3270         return limit;
3271 }
3272
3273 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3274         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3275 {
3276         unsigned i;
3277
3278         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3279                 return -ENOMEM;
3280
3281         if (xstats_names != NULL)
3282                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3283                         snprintf(xstats_names[i].name,
3284                                 sizeof(xstats_names[i].name),
3285                                 "%s", rte_ixgbevf_stats_strings[i].name);
3286         return IXGBEVF_NB_XSTATS;
3287 }
3288
3289 static int
3290 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3291                                          unsigned n)
3292 {
3293         struct ixgbe_hw *hw =
3294                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3295         struct ixgbe_hw_stats *hw_stats =
3296                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3297         struct ixgbe_macsec_stats *macsec_stats =
3298                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3299                                 dev->data->dev_private);
3300         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3301         unsigned i, stat, count = 0;
3302
3303         count = ixgbe_xstats_calc_num();
3304
3305         if (n < count)
3306                 return count;
3307
3308         total_missed_rx = 0;
3309         total_qbrc = 0;
3310         total_qprc = 0;
3311         total_qprdc = 0;
3312
3313         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3314                         &total_qbrc, &total_qprc, &total_qprdc);
3315
3316         /* If this is a reset xstats is NULL, and we have cleared the
3317          * registers by reading them.
3318          */
3319         if (!xstats)
3320                 return 0;
3321
3322         /* Extended stats from ixgbe_hw_stats */
3323         count = 0;
3324         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3325                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3326                                 rte_ixgbe_stats_strings[i].offset);
3327                 xstats[count].id = count;
3328                 count++;
3329         }
3330
3331         /* MACsec Stats */
3332         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3333                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3334                                 rte_ixgbe_macsec_strings[i].offset);
3335                 xstats[count].id = count;
3336                 count++;
3337         }
3338
3339         /* RX Priority Stats */
3340         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3341                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3342                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3343                                         rte_ixgbe_rxq_strings[stat].offset +
3344                                         (sizeof(uint64_t) * i));
3345                         xstats[count].id = count;
3346                         count++;
3347                 }
3348         }
3349
3350         /* TX Priority Stats */
3351         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3352                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3353                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3354                                         rte_ixgbe_txq_strings[stat].offset +
3355                                         (sizeof(uint64_t) * i));
3356                         xstats[count].id = count;
3357                         count++;
3358                 }
3359         }
3360         return count;
3361 }
3362
3363 static int
3364 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3365                 uint64_t *values, unsigned int n)
3366 {
3367         if (!ids) {
3368                 struct ixgbe_hw *hw =
3369                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3370                 struct ixgbe_hw_stats *hw_stats =
3371                                 IXGBE_DEV_PRIVATE_TO_STATS(
3372                                                 dev->data->dev_private);
3373                 struct ixgbe_macsec_stats *macsec_stats =
3374                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3375                                         dev->data->dev_private);
3376                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3377                 unsigned int i, stat, count = 0;
3378
3379                 count = ixgbe_xstats_calc_num();
3380
3381                 if (!ids && n < count)
3382                         return count;
3383
3384                 total_missed_rx = 0;
3385                 total_qbrc = 0;
3386                 total_qprc = 0;
3387                 total_qprdc = 0;
3388
3389                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3390                                 &total_missed_rx, &total_qbrc, &total_qprc,
3391                                 &total_qprdc);
3392
3393                 /* If this is a reset xstats is NULL, and we have cleared the
3394                  * registers by reading them.
3395                  */
3396                 if (!ids && !values)
3397                         return 0;
3398
3399                 /* Extended stats from ixgbe_hw_stats */
3400                 count = 0;
3401                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3402                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3403                                         rte_ixgbe_stats_strings[i].offset);
3404                         count++;
3405                 }
3406
3407                 /* MACsec Stats */
3408                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3409                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3410                                         rte_ixgbe_macsec_strings[i].offset);
3411                         count++;
3412                 }
3413
3414                 /* RX Priority Stats */
3415                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3416                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3417                                 values[count] =
3418                                         *(uint64_t *)(((char *)hw_stats) +
3419                                         rte_ixgbe_rxq_strings[stat].offset +
3420                                         (sizeof(uint64_t) * i));
3421                                 count++;
3422                         }
3423                 }
3424
3425                 /* TX Priority Stats */
3426                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3427                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3428                                 values[count] =
3429                                         *(uint64_t *)(((char *)hw_stats) +
3430                                         rte_ixgbe_txq_strings[stat].offset +
3431                                         (sizeof(uint64_t) * i));
3432                                 count++;
3433                         }
3434                 }
3435                 return count;
3436         }
3437
3438         uint16_t i;
3439         uint16_t size = ixgbe_xstats_calc_num();
3440         uint64_t values_copy[size];
3441
3442         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3443
3444         for (i = 0; i < n; i++) {
3445                 if (ids[i] >= size) {
3446                         PMD_INIT_LOG(ERR, "id value isn't valid");
3447                         return -1;
3448                 }
3449                 values[i] = values_copy[ids[i]];
3450         }
3451         return n;
3452 }
3453
3454 static void
3455 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3456 {
3457         struct ixgbe_hw_stats *stats =
3458                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3459         struct ixgbe_macsec_stats *macsec_stats =
3460                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3461                                 dev->data->dev_private);
3462
3463         unsigned count = ixgbe_xstats_calc_num();
3464
3465         /* HW registers are cleared on read */
3466         ixgbe_dev_xstats_get(dev, NULL, count);
3467
3468         /* Reset software totals */
3469         memset(stats, 0, sizeof(*stats));
3470         memset(macsec_stats, 0, sizeof(*macsec_stats));
3471 }
3472
3473 static void
3474 ixgbevf_update_stats(struct rte_eth_dev *dev)
3475 {
3476         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3477         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3478                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3479
3480         /* Good Rx packet, include VF loopback */
3481         UPDATE_VF_STAT(IXGBE_VFGPRC,
3482             hw_stats->last_vfgprc, hw_stats->vfgprc);
3483
3484         /* Good Rx octets, include VF loopback */
3485         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3486             hw_stats->last_vfgorc, hw_stats->vfgorc);
3487
3488         /* Good Tx packet, include VF loopback */
3489         UPDATE_VF_STAT(IXGBE_VFGPTC,
3490             hw_stats->last_vfgptc, hw_stats->vfgptc);
3491
3492         /* Good Tx octets, include VF loopback */
3493         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3494             hw_stats->last_vfgotc, hw_stats->vfgotc);
3495
3496         /* Rx Multicst Packet */
3497         UPDATE_VF_STAT(IXGBE_VFMPRC,
3498             hw_stats->last_vfmprc, hw_stats->vfmprc);
3499 }
3500
3501 static int
3502 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3503                        unsigned n)
3504 {
3505         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3506                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3507         unsigned i;
3508
3509         if (n < IXGBEVF_NB_XSTATS)
3510                 return IXGBEVF_NB_XSTATS;
3511
3512         ixgbevf_update_stats(dev);
3513
3514         if (!xstats)
3515                 return 0;
3516
3517         /* Extended stats */
3518         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3519                 xstats[i].id = i;
3520                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3521                         rte_ixgbevf_stats_strings[i].offset);
3522         }
3523
3524         return IXGBEVF_NB_XSTATS;
3525 }
3526
3527 static int
3528 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3529 {
3530         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3531                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3532
3533         ixgbevf_update_stats(dev);
3534
3535         if (stats == NULL)
3536                 return -EINVAL;
3537
3538         stats->ipackets = hw_stats->vfgprc;
3539         stats->ibytes = hw_stats->vfgorc;
3540         stats->opackets = hw_stats->vfgptc;
3541         stats->obytes = hw_stats->vfgotc;
3542         return 0;
3543 }
3544
3545 static void
3546 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3547 {
3548         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3549                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3550
3551         /* Sync HW register to the last stats */
3552         ixgbevf_dev_stats_get(dev, NULL);
3553
3554         /* reset HW current stats*/
3555         hw_stats->vfgprc = 0;
3556         hw_stats->vfgorc = 0;
3557         hw_stats->vfgptc = 0;
3558         hw_stats->vfgotc = 0;
3559 }
3560
3561 static int
3562 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3563 {
3564         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3565         u16 eeprom_verh, eeprom_verl;
3566         u32 etrack_id;
3567         int ret;
3568
3569         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3570         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3571
3572         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3573         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3574
3575         ret += 1; /* add the size of '\0' */
3576         if (fw_size < (u32)ret)
3577                 return ret;
3578         else
3579                 return 0;
3580 }
3581
3582 static void
3583 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3584 {
3585         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3586         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3587         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3588
3589         dev_info->pci_dev = pci_dev;
3590         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3591         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3592         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3593                 /*
3594                  * When DCB/VT is off, maximum number of queues changes,
3595                  * except for 82598EB, which remains constant.
3596                  */
3597                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3598                                 hw->mac.type != ixgbe_mac_82598EB)
3599                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3600         }
3601         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3602         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3603         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3604         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3605         dev_info->max_vfs = pci_dev->max_vfs;
3606         if (hw->mac.type == ixgbe_mac_82598EB)
3607                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3608         else
3609                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3610         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3611         dev_info->rx_offload_capa =
3612                 DEV_RX_OFFLOAD_VLAN_STRIP |
3613                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3614                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3615                 DEV_RX_OFFLOAD_TCP_CKSUM  |
3616                 DEV_RX_OFFLOAD_CRC_STRIP;
3617
3618         /*
3619          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3620          * mode.
3621          */
3622         if ((hw->mac.type == ixgbe_mac_82599EB ||
3623              hw->mac.type == ixgbe_mac_X540) &&
3624             !RTE_ETH_DEV_SRIOV(dev).active)
3625                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3626
3627         if (hw->mac.type == ixgbe_mac_82599EB ||
3628             hw->mac.type == ixgbe_mac_X540)
3629                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3630
3631         if (hw->mac.type == ixgbe_mac_X550 ||
3632             hw->mac.type == ixgbe_mac_X550EM_x ||
3633             hw->mac.type == ixgbe_mac_X550EM_a)
3634                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3635
3636         dev_info->tx_offload_capa =
3637                 DEV_TX_OFFLOAD_VLAN_INSERT |
3638                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3639                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3640                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3641                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3642                 DEV_TX_OFFLOAD_TCP_TSO;
3643
3644         if (hw->mac.type == ixgbe_mac_82599EB ||
3645             hw->mac.type == ixgbe_mac_X540)
3646                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3647
3648         if (hw->mac.type == ixgbe_mac_X550 ||
3649             hw->mac.type == ixgbe_mac_X550EM_x ||
3650             hw->mac.type == ixgbe_mac_X550EM_a)
3651                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3652
3653 #ifdef RTE_LIBRTE_SECURITY
3654         if (dev->security_ctx) {
3655                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_SECURITY;
3656                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
3657         }
3658 #endif
3659
3660         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3661                 .rx_thresh = {
3662                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3663                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3664                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3665                 },
3666                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3667                 .rx_drop_en = 0,
3668         };
3669
3670         dev_info->default_txconf = (struct rte_eth_txconf) {
3671                 .tx_thresh = {
3672                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3673                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3674                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3675                 },
3676                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3677                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3678                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3679                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3680         };
3681
3682         dev_info->rx_desc_lim = rx_desc_lim;
3683         dev_info->tx_desc_lim = tx_desc_lim;
3684
3685         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3686         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3687         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3688
3689         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3690         if (hw->mac.type == ixgbe_mac_X540 ||
3691             hw->mac.type == ixgbe_mac_X540_vf ||
3692             hw->mac.type == ixgbe_mac_X550 ||
3693             hw->mac.type == ixgbe_mac_X550_vf) {
3694                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3695         }
3696         if (hw->mac.type == ixgbe_mac_X550) {
3697                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3698                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3699         }
3700 }
3701
3702 static const uint32_t *
3703 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3704 {
3705         static const uint32_t ptypes[] = {
3706                 /* For non-vec functions,
3707                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3708                  * for vec functions,
3709                  * refers to _recv_raw_pkts_vec().
3710                  */
3711                 RTE_PTYPE_L2_ETHER,
3712                 RTE_PTYPE_L3_IPV4,
3713                 RTE_PTYPE_L3_IPV4_EXT,
3714                 RTE_PTYPE_L3_IPV6,
3715                 RTE_PTYPE_L3_IPV6_EXT,
3716                 RTE_PTYPE_L4_SCTP,
3717                 RTE_PTYPE_L4_TCP,
3718                 RTE_PTYPE_L4_UDP,
3719                 RTE_PTYPE_TUNNEL_IP,
3720                 RTE_PTYPE_INNER_L3_IPV6,
3721                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3722                 RTE_PTYPE_INNER_L4_TCP,
3723                 RTE_PTYPE_INNER_L4_UDP,
3724                 RTE_PTYPE_UNKNOWN
3725         };
3726
3727         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3728             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3729             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3730             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3731                 return ptypes;
3732
3733 #if defined(RTE_ARCH_X86)
3734         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3735             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3736                 return ptypes;
3737 #endif
3738         return NULL;
3739 }
3740
3741 static void
3742 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3743                      struct rte_eth_dev_info *dev_info)
3744 {
3745         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3746         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3747
3748         dev_info->pci_dev = pci_dev;
3749         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3750         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3751         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3752         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3753         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3754         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3755         dev_info->max_vfs = pci_dev->max_vfs;
3756         if (hw->mac.type == ixgbe_mac_82598EB)
3757                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3758         else
3759                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3760         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3761                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3762                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3763                                 DEV_RX_OFFLOAD_TCP_CKSUM  |
3764                                 DEV_RX_OFFLOAD_CRC_STRIP;
3765         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3766                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3767                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3768                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3769                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3770                                 DEV_TX_OFFLOAD_TCP_TSO;
3771
3772         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3773                 .rx_thresh = {
3774                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3775                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3776                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3777                 },
3778                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3779                 .rx_drop_en = 0,
3780         };
3781
3782         dev_info->default_txconf = (struct rte_eth_txconf) {
3783                 .tx_thresh = {
3784                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3785                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3786                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3787                 },
3788                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3789                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3790                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3791                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3792         };
3793
3794         dev_info->rx_desc_lim = rx_desc_lim;
3795         dev_info->tx_desc_lim = tx_desc_lim;
3796 }
3797
3798 static int
3799 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3800                    int *link_up, int wait_to_complete)
3801 {
3802         /**
3803          * for a quick link status checking, wait_to_compelet == 0,
3804          * skip PF link status checking
3805          */
3806         bool no_pflink_check = wait_to_complete == 0;
3807         struct ixgbe_mbx_info *mbx = &hw->mbx;
3808         struct ixgbe_mac_info *mac = &hw->mac;
3809         uint32_t links_reg, in_msg;
3810         int ret_val = 0;
3811
3812         /* If we were hit with a reset drop the link */
3813         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3814                 mac->get_link_status = true;
3815
3816         if (!mac->get_link_status)
3817                 goto out;
3818
3819         /* if link status is down no point in checking to see if pf is up */
3820         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3821         if (!(links_reg & IXGBE_LINKS_UP))
3822                 goto out;
3823
3824         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3825          * before the link status is correct
3826          */
3827         if (mac->type == ixgbe_mac_82599_vf) {
3828                 int i;
3829
3830                 for (i = 0; i < 5; i++) {
3831                         rte_delay_us(100);
3832                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3833
3834                         if (!(links_reg & IXGBE_LINKS_UP))
3835                                 goto out;
3836                 }
3837         }
3838
3839         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3840         case IXGBE_LINKS_SPEED_10G_82599:
3841                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3842                 if (hw->mac.type >= ixgbe_mac_X550) {
3843                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3844                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3845                 }
3846                 break;
3847         case IXGBE_LINKS_SPEED_1G_82599:
3848                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3849                 break;
3850         case IXGBE_LINKS_SPEED_100_82599:
3851                 *speed = IXGBE_LINK_SPEED_100_FULL;
3852                 if (hw->mac.type == ixgbe_mac_X550) {
3853                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3854                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3855                 }
3856                 break;
3857         case IXGBE_LINKS_SPEED_10_X550EM_A:
3858                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3859                 /* Since Reserved in older MAC's */
3860                 if (hw->mac.type >= ixgbe_mac_X550)
3861                         *speed = IXGBE_LINK_SPEED_10_FULL;
3862                 break;
3863         default:
3864                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3865         }
3866
3867         if (no_pflink_check) {
3868                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3869                         mac->get_link_status = true;
3870                 else
3871                         mac->get_link_status = false;
3872
3873                 goto out;
3874         }
3875         /* if the read failed it could just be a mailbox collision, best wait
3876          * until we are called again and don't report an error
3877          */
3878         if (mbx->ops.read(hw, &in_msg, 1, 0))
3879                 goto out;
3880
3881         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3882                 /* msg is not CTS and is NACK we must have lost CTS status */
3883                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3884                         ret_val = -1;
3885                 goto out;
3886         }
3887
3888         /* the pf is talking, if we timed out in the past we reinit */
3889         if (!mbx->timeout) {
3890                 ret_val = -1;
3891                 goto out;
3892         }
3893
3894         /* if we passed all the tests above then the link is up and we no
3895          * longer need to check for link
3896          */
3897         mac->get_link_status = false;
3898
3899 out:
3900         *link_up = !mac->get_link_status;
3901         return ret_val;
3902 }
3903
3904 /* return 0 means link status changed, -1 means not changed */
3905 static int
3906 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3907                             int wait_to_complete, int vf)
3908 {
3909         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3910         struct rte_eth_link link;
3911         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3912         struct ixgbe_interrupt *intr =
3913                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3914         int link_up;
3915         int diag;
3916         u32 speed = 0;
3917         int wait = 1;
3918         bool autoneg = false;
3919
3920         memset(&link, 0, sizeof(link));
3921         link.link_status = ETH_LINK_DOWN;
3922         link.link_speed = 0;
3923         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3924         link.link_autoneg = ETH_LINK_AUTONEG;
3925
3926         hw->mac.get_link_status = true;
3927
3928         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3929                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3930                 speed = hw->phy.autoneg_advertised;
3931                 if (!speed)
3932                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3933                 ixgbe_setup_link(hw, speed, true);
3934         }
3935
3936         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3937         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3938                 wait = 0;
3939
3940         if (vf)
3941                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3942         else
3943                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3944
3945         if (diag != 0) {
3946                 link.link_speed = ETH_SPEED_NUM_100M;
3947                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3948                 return rte_eth_linkstatus_set(dev, &link);
3949         }
3950
3951         if (link_up == 0) {
3952                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3953                 return rte_eth_linkstatus_set(dev, &link);
3954         }
3955
3956         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3957         link.link_status = ETH_LINK_UP;
3958         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3959
3960         switch (link_speed) {
3961         default:
3962         case IXGBE_LINK_SPEED_UNKNOWN:
3963                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3964                 link.link_speed = ETH_SPEED_NUM_100M;
3965                 break;
3966
3967         case IXGBE_LINK_SPEED_100_FULL:
3968                 link.link_speed = ETH_SPEED_NUM_100M;
3969                 break;
3970
3971         case IXGBE_LINK_SPEED_1GB_FULL:
3972                 link.link_speed = ETH_SPEED_NUM_1G;
3973                 break;
3974
3975         case IXGBE_LINK_SPEED_2_5GB_FULL:
3976                 link.link_speed = ETH_SPEED_NUM_2_5G;
3977                 break;
3978
3979         case IXGBE_LINK_SPEED_5GB_FULL:
3980                 link.link_speed = ETH_SPEED_NUM_5G;
3981                 break;
3982
3983         case IXGBE_LINK_SPEED_10GB_FULL:
3984                 link.link_speed = ETH_SPEED_NUM_10G;
3985                 break;
3986         }
3987
3988         return rte_eth_linkstatus_set(dev, &link);
3989 }
3990
3991 static int
3992 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3993 {
3994         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
3995 }
3996
3997 static int
3998 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3999 {
4000         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4001 }
4002
4003 static void
4004 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4005 {
4006         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4007         uint32_t fctrl;
4008
4009         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4010         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4011         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4012 }
4013
4014 static void
4015 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4016 {
4017         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4018         uint32_t fctrl;
4019
4020         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4021         fctrl &= (~IXGBE_FCTRL_UPE);
4022         if (dev->data->all_multicast == 1)
4023                 fctrl |= IXGBE_FCTRL_MPE;
4024         else
4025                 fctrl &= (~IXGBE_FCTRL_MPE);
4026         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4027 }
4028
4029 static void
4030 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4031 {
4032         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4033         uint32_t fctrl;
4034
4035         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4036         fctrl |= IXGBE_FCTRL_MPE;
4037         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4038 }
4039
4040 static void
4041 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4042 {
4043         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4044         uint32_t fctrl;
4045
4046         if (dev->data->promiscuous == 1)
4047                 return; /* must remain in all_multicast mode */
4048
4049         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4050         fctrl &= (~IXGBE_FCTRL_MPE);
4051         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4052 }
4053
4054 /**
4055  * It clears the interrupt causes and enables the interrupt.
4056  * It will be called once only during nic initialized.
4057  *
4058  * @param dev
4059  *  Pointer to struct rte_eth_dev.
4060  * @param on
4061  *  Enable or Disable.
4062  *
4063  * @return
4064  *  - On success, zero.
4065  *  - On failure, a negative value.
4066  */
4067 static int
4068 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4069 {
4070         struct ixgbe_interrupt *intr =
4071                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4072
4073         ixgbe_dev_link_status_print(dev);
4074         if (on)
4075                 intr->mask |= IXGBE_EICR_LSC;
4076         else
4077                 intr->mask &= ~IXGBE_EICR_LSC;
4078
4079         return 0;
4080 }
4081
4082 /**
4083  * It clears the interrupt causes and enables the interrupt.
4084  * It will be called once only during nic initialized.
4085  *
4086  * @param dev
4087  *  Pointer to struct rte_eth_dev.
4088  *
4089  * @return
4090  *  - On success, zero.
4091  *  - On failure, a negative value.
4092  */
4093 static int
4094 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4095 {
4096         struct ixgbe_interrupt *intr =
4097                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4098
4099         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4100
4101         return 0;
4102 }
4103
4104 /**
4105  * It clears the interrupt causes and enables the interrupt.
4106  * It will be called once only during nic initialized.
4107  *
4108  * @param dev
4109  *  Pointer to struct rte_eth_dev.
4110  *
4111  * @return
4112  *  - On success, zero.
4113  *  - On failure, a negative value.
4114  */
4115 static int
4116 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4117 {
4118         struct ixgbe_interrupt *intr =
4119                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4120
4121         intr->mask |= IXGBE_EICR_LINKSEC;
4122
4123         return 0;
4124 }
4125
4126 /*
4127  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4128  *
4129  * @param dev
4130  *  Pointer to struct rte_eth_dev.
4131  *
4132  * @return
4133  *  - On success, zero.
4134  *  - On failure, a negative value.
4135  */
4136 static int
4137 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4138 {
4139         uint32_t eicr;
4140         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4141         struct ixgbe_interrupt *intr =
4142                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4143
4144         /* clear all cause mask */
4145         ixgbe_disable_intr(hw);
4146
4147         /* read-on-clear nic registers here */
4148         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4149         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4150
4151         intr->flags = 0;
4152
4153         /* set flag for async link update */
4154         if (eicr & IXGBE_EICR_LSC)
4155                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4156
4157         if (eicr & IXGBE_EICR_MAILBOX)
4158                 intr->flags |= IXGBE_FLAG_MAILBOX;
4159
4160         if (eicr & IXGBE_EICR_LINKSEC)
4161                 intr->flags |= IXGBE_FLAG_MACSEC;
4162
4163         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4164             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4165             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4166                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4167
4168         return 0;
4169 }
4170
4171 /**
4172  * It gets and then prints the link status.
4173  *
4174  * @param dev
4175  *  Pointer to struct rte_eth_dev.
4176  *
4177  * @return
4178  *  - On success, zero.
4179  *  - On failure, a negative value.
4180  */
4181 static void
4182 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4183 {
4184         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4185         struct rte_eth_link link;
4186
4187         rte_eth_linkstatus_get(dev, &link);
4188
4189         if (link.link_status) {
4190                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4191                                         (int)(dev->data->port_id),
4192                                         (unsigned)link.link_speed,
4193                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4194                                         "full-duplex" : "half-duplex");
4195         } else {
4196                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4197                                 (int)(dev->data->port_id));
4198         }
4199         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4200                                 pci_dev->addr.domain,
4201                                 pci_dev->addr.bus,
4202                                 pci_dev->addr.devid,
4203                                 pci_dev->addr.function);
4204 }
4205
4206 /*
4207  * It executes link_update after knowing an interrupt occurred.
4208  *
4209  * @param dev
4210  *  Pointer to struct rte_eth_dev.
4211  *
4212  * @return
4213  *  - On success, zero.
4214  *  - On failure, a negative value.
4215  */
4216 static int
4217 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4218                            struct rte_intr_handle *intr_handle)
4219 {
4220         struct ixgbe_interrupt *intr =
4221                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4222         int64_t timeout;
4223         struct ixgbe_hw *hw =
4224                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4225
4226         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4227
4228         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4229                 ixgbe_pf_mbx_process(dev);
4230                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4231         }
4232
4233         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4234                 ixgbe_handle_lasi(hw);
4235                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4236         }
4237
4238         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4239                 struct rte_eth_link link;
4240
4241                 /* get the link status before link update, for predicting later */
4242                 rte_eth_linkstatus_get(dev, &link);
4243
4244                 ixgbe_dev_link_update(dev, 0);
4245
4246                 /* likely to up */
4247                 if (!link.link_status)
4248                         /* handle it 1 sec later, wait it being stable */
4249                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4250                 /* likely to down */
4251                 else
4252                         /* handle it 4 sec later, wait it being stable */
4253                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4254
4255                 ixgbe_dev_link_status_print(dev);
4256                 if (rte_eal_alarm_set(timeout * 1000,
4257                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4258                         PMD_DRV_LOG(ERR, "Error setting alarm");
4259                 else {
4260                         /* remember original mask */
4261                         intr->mask_original = intr->mask;
4262                         /* only disable lsc interrupt */
4263                         intr->mask &= ~IXGBE_EIMS_LSC;
4264                 }
4265         }
4266
4267         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4268         ixgbe_enable_intr(dev);
4269         rte_intr_enable(intr_handle);
4270
4271         return 0;
4272 }
4273
4274 /**
4275  * Interrupt handler which shall be registered for alarm callback for delayed
4276  * handling specific interrupt to wait for the stable nic state. As the
4277  * NIC interrupt state is not stable for ixgbe after link is just down,
4278  * it needs to wait 4 seconds to get the stable status.
4279  *
4280  * @param handle
4281  *  Pointer to interrupt handle.
4282  * @param param
4283  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4284  *
4285  * @return
4286  *  void
4287  */
4288 static void
4289 ixgbe_dev_interrupt_delayed_handler(void *param)
4290 {
4291         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4292         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4293         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4294         struct ixgbe_interrupt *intr =
4295                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4296         struct ixgbe_hw *hw =
4297                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4298         uint32_t eicr;
4299
4300         ixgbe_disable_intr(hw);
4301
4302         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4303         if (eicr & IXGBE_EICR_MAILBOX)
4304                 ixgbe_pf_mbx_process(dev);
4305
4306         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4307                 ixgbe_handle_lasi(hw);
4308                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4309         }
4310
4311         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4312                 ixgbe_dev_link_update(dev, 0);
4313                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4314                 ixgbe_dev_link_status_print(dev);
4315                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4316                                               NULL);
4317         }
4318
4319         if (intr->flags & IXGBE_FLAG_MACSEC) {
4320                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4321                                               NULL);
4322                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4323         }
4324
4325         /* restore original mask */
4326         intr->mask = intr->mask_original;
4327         intr->mask_original = 0;
4328
4329         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4330         ixgbe_enable_intr(dev);
4331         rte_intr_enable(intr_handle);
4332 }
4333
4334 /**
4335  * Interrupt handler triggered by NIC  for handling
4336  * specific interrupt.
4337  *
4338  * @param handle
4339  *  Pointer to interrupt handle.
4340  * @param param
4341  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4342  *
4343  * @return
4344  *  void
4345  */
4346 static void
4347 ixgbe_dev_interrupt_handler(void *param)
4348 {
4349         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4350
4351         ixgbe_dev_interrupt_get_status(dev);
4352         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4353 }
4354
4355 static int
4356 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4357 {
4358         struct ixgbe_hw *hw;
4359
4360         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4361         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4362 }
4363
4364 static int
4365 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4366 {
4367         struct ixgbe_hw *hw;
4368
4369         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4370         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4371 }
4372
4373 static int
4374 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4375 {
4376         struct ixgbe_hw *hw;
4377         uint32_t mflcn_reg;
4378         uint32_t fccfg_reg;
4379         int rx_pause;
4380         int tx_pause;
4381
4382         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4383
4384         fc_conf->pause_time = hw->fc.pause_time;
4385         fc_conf->high_water = hw->fc.high_water[0];
4386         fc_conf->low_water = hw->fc.low_water[0];
4387         fc_conf->send_xon = hw->fc.send_xon;
4388         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4389
4390         /*
4391          * Return rx_pause status according to actual setting of
4392          * MFLCN register.
4393          */
4394         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4395         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4396                 rx_pause = 1;
4397         else
4398                 rx_pause = 0;
4399
4400         /*
4401          * Return tx_pause status according to actual setting of
4402          * FCCFG register.
4403          */
4404         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4405         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4406                 tx_pause = 1;
4407         else
4408                 tx_pause = 0;
4409
4410         if (rx_pause && tx_pause)
4411                 fc_conf->mode = RTE_FC_FULL;
4412         else if (rx_pause)
4413                 fc_conf->mode = RTE_FC_RX_PAUSE;
4414         else if (tx_pause)
4415                 fc_conf->mode = RTE_FC_TX_PAUSE;
4416         else
4417                 fc_conf->mode = RTE_FC_NONE;
4418
4419         return 0;
4420 }
4421
4422 static int
4423 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4424 {
4425         struct ixgbe_hw *hw;
4426         int err;
4427         uint32_t rx_buf_size;
4428         uint32_t max_high_water;
4429         uint32_t mflcn;
4430         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4431                 ixgbe_fc_none,
4432                 ixgbe_fc_rx_pause,
4433                 ixgbe_fc_tx_pause,
4434                 ixgbe_fc_full
4435         };
4436
4437         PMD_INIT_FUNC_TRACE();
4438
4439         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4440         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4441         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4442
4443         /*
4444          * At least reserve one Ethernet frame for watermark
4445          * high_water/low_water in kilo bytes for ixgbe
4446          */
4447         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4448         if ((fc_conf->high_water > max_high_water) ||
4449                 (fc_conf->high_water < fc_conf->low_water)) {
4450                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4451                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4452                 return -EINVAL;
4453         }
4454
4455         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4456         hw->fc.pause_time     = fc_conf->pause_time;
4457         hw->fc.high_water[0]  = fc_conf->high_water;
4458         hw->fc.low_water[0]   = fc_conf->low_water;
4459         hw->fc.send_xon       = fc_conf->send_xon;
4460         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4461
4462         err = ixgbe_fc_enable(hw);
4463
4464         /* Not negotiated is not an error case */
4465         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4466
4467                 /* check if we want to forward MAC frames - driver doesn't have native
4468                  * capability to do that, so we'll write the registers ourselves */
4469
4470                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4471
4472                 /* set or clear MFLCN.PMCF bit depending on configuration */
4473                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4474                         mflcn |= IXGBE_MFLCN_PMCF;
4475                 else
4476                         mflcn &= ~IXGBE_MFLCN_PMCF;
4477
4478                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4479                 IXGBE_WRITE_FLUSH(hw);
4480
4481                 return 0;
4482         }
4483
4484         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4485         return -EIO;
4486 }
4487
4488 /**
4489  *  ixgbe_pfc_enable_generic - Enable flow control
4490  *  @hw: pointer to hardware structure
4491  *  @tc_num: traffic class number
4492  *  Enable flow control according to the current settings.
4493  */
4494 static int
4495 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4496 {
4497         int ret_val = 0;
4498         uint32_t mflcn_reg, fccfg_reg;
4499         uint32_t reg;
4500         uint32_t fcrtl, fcrth;
4501         uint8_t i;
4502         uint8_t nb_rx_en;
4503
4504         /* Validate the water mark configuration */
4505         if (!hw->fc.pause_time) {
4506                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4507                 goto out;
4508         }
4509
4510         /* Low water mark of zero causes XOFF floods */
4511         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4512                  /* High/Low water can not be 0 */
4513                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4514                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4515                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4516                         goto out;
4517                 }
4518
4519                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4520                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4521                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4522                         goto out;
4523                 }
4524         }
4525         /* Negotiate the fc mode to use */
4526         ixgbe_fc_autoneg(hw);
4527
4528         /* Disable any previous flow control settings */
4529         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4530         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4531
4532         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4533         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4534
4535         switch (hw->fc.current_mode) {
4536         case ixgbe_fc_none:
4537                 /*
4538                  * If the count of enabled RX Priority Flow control >1,
4539                  * and the TX pause can not be disabled
4540                  */
4541                 nb_rx_en = 0;
4542                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4543                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4544                         if (reg & IXGBE_FCRTH_FCEN)
4545                                 nb_rx_en++;
4546                 }
4547                 if (nb_rx_en > 1)
4548                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4549                 break;
4550         case ixgbe_fc_rx_pause:
4551                 /*
4552                  * Rx Flow control is enabled and Tx Flow control is
4553                  * disabled by software override. Since there really
4554                  * isn't a way to advertise that we are capable of RX
4555                  * Pause ONLY, we will advertise that we support both
4556                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4557                  * disable the adapter's ability to send PAUSE frames.
4558                  */
4559                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4560                 /*
4561                  * If the count of enabled RX Priority Flow control >1,
4562                  * and the TX pause can not be disabled
4563                  */
4564                 nb_rx_en = 0;
4565                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4566                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4567                         if (reg & IXGBE_FCRTH_FCEN)
4568                                 nb_rx_en++;
4569                 }
4570                 if (nb_rx_en > 1)
4571                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4572                 break;
4573         case ixgbe_fc_tx_pause:
4574                 /*
4575                  * Tx Flow control is enabled, and Rx Flow control is
4576                  * disabled by software override.
4577                  */
4578                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4579                 break;
4580         case ixgbe_fc_full:
4581                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4582                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4583                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4584                 break;
4585         default:
4586                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4587                 ret_val = IXGBE_ERR_CONFIG;
4588                 goto out;
4589         }
4590
4591         /* Set 802.3x based flow control settings. */
4592         mflcn_reg |= IXGBE_MFLCN_DPF;
4593         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4594         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4595
4596         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4597         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4598                 hw->fc.high_water[tc_num]) {
4599                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4600                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4601                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4602         } else {
4603                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4604                 /*
4605                  * In order to prevent Tx hangs when the internal Tx
4606                  * switch is enabled we must set the high water mark
4607                  * to the maximum FCRTH value.  This allows the Tx
4608                  * switch to function even under heavy Rx workloads.
4609                  */
4610                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4611         }
4612         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4613
4614         /* Configure pause time (2 TCs per register) */
4615         reg = hw->fc.pause_time * 0x00010001;
4616         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4617                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4618
4619         /* Configure flow control refresh threshold value */
4620         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4621
4622 out:
4623         return ret_val;
4624 }
4625
4626 static int
4627 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4628 {
4629         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4630         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4631
4632         if (hw->mac.type != ixgbe_mac_82598EB) {
4633                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4634         }
4635         return ret_val;
4636 }
4637
4638 static int
4639 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4640 {
4641         int err;
4642         uint32_t rx_buf_size;
4643         uint32_t max_high_water;
4644         uint8_t tc_num;
4645         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4646         struct ixgbe_hw *hw =
4647                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4648         struct ixgbe_dcb_config *dcb_config =
4649                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4650
4651         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4652                 ixgbe_fc_none,
4653                 ixgbe_fc_rx_pause,
4654                 ixgbe_fc_tx_pause,
4655                 ixgbe_fc_full
4656         };
4657
4658         PMD_INIT_FUNC_TRACE();
4659
4660         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4661         tc_num = map[pfc_conf->priority];
4662         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4663         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4664         /*
4665          * At least reserve one Ethernet frame for watermark
4666          * high_water/low_water in kilo bytes for ixgbe
4667          */
4668         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4669         if ((pfc_conf->fc.high_water > max_high_water) ||
4670             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4671                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4672                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4673                 return -EINVAL;
4674         }
4675
4676         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4677         hw->fc.pause_time = pfc_conf->fc.pause_time;
4678         hw->fc.send_xon = pfc_conf->fc.send_xon;
4679         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4680         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4681
4682         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4683
4684         /* Not negotiated is not an error case */
4685         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4686                 return 0;
4687
4688         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4689         return -EIO;
4690 }
4691
4692 static int
4693 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4694                           struct rte_eth_rss_reta_entry64 *reta_conf,
4695                           uint16_t reta_size)
4696 {
4697         uint16_t i, sp_reta_size;
4698         uint8_t j, mask;
4699         uint32_t reta, r;
4700         uint16_t idx, shift;
4701         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4702         uint32_t reta_reg;
4703
4704         PMD_INIT_FUNC_TRACE();
4705
4706         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4707                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4708                         "NIC.");
4709                 return -ENOTSUP;
4710         }
4711
4712         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4713         if (reta_size != sp_reta_size) {
4714                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4715                         "(%d) doesn't match the number hardware can supported "
4716                         "(%d)", reta_size, sp_reta_size);
4717                 return -EINVAL;
4718         }
4719
4720         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4721                 idx = i / RTE_RETA_GROUP_SIZE;
4722                 shift = i % RTE_RETA_GROUP_SIZE;
4723                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4724                                                 IXGBE_4_BIT_MASK);
4725                 if (!mask)
4726                         continue;
4727                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4728                 if (mask == IXGBE_4_BIT_MASK)
4729                         r = 0;
4730                 else
4731                         r = IXGBE_READ_REG(hw, reta_reg);
4732                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4733                         if (mask & (0x1 << j))
4734                                 reta |= reta_conf[idx].reta[shift + j] <<
4735                                                         (CHAR_BIT * j);
4736                         else
4737                                 reta |= r & (IXGBE_8_BIT_MASK <<
4738                                                 (CHAR_BIT * j));
4739                 }
4740                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4741         }
4742
4743         return 0;
4744 }
4745
4746 static int
4747 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4748                          struct rte_eth_rss_reta_entry64 *reta_conf,
4749                          uint16_t reta_size)
4750 {
4751         uint16_t i, sp_reta_size;
4752         uint8_t j, mask;
4753         uint32_t reta;
4754         uint16_t idx, shift;
4755         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4756         uint32_t reta_reg;
4757
4758         PMD_INIT_FUNC_TRACE();
4759         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4760         if (reta_size != sp_reta_size) {
4761                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4762                         "(%d) doesn't match the number hardware can supported "
4763                         "(%d)", reta_size, sp_reta_size);
4764                 return -EINVAL;
4765         }
4766
4767         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4768                 idx = i / RTE_RETA_GROUP_SIZE;
4769                 shift = i % RTE_RETA_GROUP_SIZE;
4770                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4771                                                 IXGBE_4_BIT_MASK);
4772                 if (!mask)
4773                         continue;
4774
4775                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4776                 reta = IXGBE_READ_REG(hw, reta_reg);
4777                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4778                         if (mask & (0x1 << j))
4779                                 reta_conf[idx].reta[shift + j] =
4780                                         ((reta >> (CHAR_BIT * j)) &
4781                                                 IXGBE_8_BIT_MASK);
4782                 }
4783         }
4784
4785         return 0;
4786 }
4787
4788 static int
4789 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4790                                 uint32_t index, uint32_t pool)
4791 {
4792         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4793         uint32_t enable_addr = 1;
4794
4795         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4796                              pool, enable_addr);
4797 }
4798
4799 static void
4800 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4801 {
4802         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4803
4804         ixgbe_clear_rar(hw, index);
4805 }
4806
4807 static void
4808 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4809 {
4810         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4811
4812         ixgbe_remove_rar(dev, 0);
4813
4814         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4815 }
4816
4817 static bool
4818 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4819 {
4820         if (strcmp(dev->device->driver->name, drv->driver.name))
4821                 return false;
4822
4823         return true;
4824 }
4825
4826 bool
4827 is_ixgbe_supported(struct rte_eth_dev *dev)
4828 {
4829         return is_device_supported(dev, &rte_ixgbe_pmd);
4830 }
4831
4832 static int
4833 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4834 {
4835         uint32_t hlreg0;
4836         uint32_t maxfrs;
4837         struct ixgbe_hw *hw;
4838         struct rte_eth_dev_info dev_info;
4839         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4840         struct rte_eth_dev_data *dev_data = dev->data;
4841
4842         ixgbe_dev_info_get(dev, &dev_info);
4843
4844         /* check that mtu is within the allowed range */
4845         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4846                 return -EINVAL;
4847
4848         /* If device is started, refuse mtu that requires the support of
4849          * scattered packets when this feature has not been enabled before.
4850          */
4851         if (dev_data->dev_started && !dev_data->scattered_rx &&
4852             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4853              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4854                 PMD_INIT_LOG(ERR, "Stop port first.");
4855                 return -EINVAL;
4856         }
4857
4858         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4859         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4860
4861         /* switch to jumbo mode if needed */
4862         if (frame_size > ETHER_MAX_LEN) {
4863                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4864                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4865         } else {
4866                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4867                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4868         }
4869         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4870
4871         /* update max frame size */
4872         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4873
4874         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4875         maxfrs &= 0x0000FFFF;
4876         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4877         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4878
4879         return 0;
4880 }
4881
4882 /*
4883  * Virtual Function operations
4884  */
4885 static void
4886 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4887 {
4888         PMD_INIT_FUNC_TRACE();
4889
4890         /* Clear interrupt mask to stop from interrupts being generated */
4891         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4892
4893         IXGBE_WRITE_FLUSH(hw);
4894 }
4895
4896 static void
4897 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4898 {
4899         PMD_INIT_FUNC_TRACE();
4900
4901         /* VF enable interrupt autoclean */
4902         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4903         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4904         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4905
4906         IXGBE_WRITE_FLUSH(hw);
4907 }
4908
4909 static int
4910 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4911 {
4912         struct rte_eth_conf *conf = &dev->data->dev_conf;
4913         struct ixgbe_adapter *adapter =
4914                         (struct ixgbe_adapter *)dev->data->dev_private;
4915
4916         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4917                      dev->data->port_id);
4918
4919         /*
4920          * VF has no ability to enable/disable HW CRC
4921          * Keep the persistent behavior the same as Host PF
4922          */
4923 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4924         if (!conf->rxmode.hw_strip_crc) {
4925                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4926                 conf->rxmode.hw_strip_crc = 1;
4927         }
4928 #else
4929         if (conf->rxmode.hw_strip_crc) {
4930                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4931                 conf->rxmode.hw_strip_crc = 0;
4932         }
4933 #endif
4934
4935         /*
4936          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4937          * allocation or vector Rx preconditions we will reset it.
4938          */
4939         adapter->rx_bulk_alloc_allowed = true;
4940         adapter->rx_vec_allowed = true;
4941
4942         return 0;
4943 }
4944
4945 static int
4946 ixgbevf_dev_start(struct rte_eth_dev *dev)
4947 {
4948         struct ixgbe_hw *hw =
4949                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4950         uint32_t intr_vector = 0;
4951         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4952         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4953
4954         int err, mask = 0;
4955
4956         PMD_INIT_FUNC_TRACE();
4957
4958         err = hw->mac.ops.reset_hw(hw);
4959         if (err) {
4960                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
4961                 return err;
4962         }
4963         hw->mac.get_link_status = true;
4964
4965         /* negotiate mailbox API version to use with the PF. */
4966         ixgbevf_negotiate_api(hw);
4967
4968         ixgbevf_dev_tx_init(dev);
4969
4970         /* This can fail when allocating mbufs for descriptor rings */
4971         err = ixgbevf_dev_rx_init(dev);
4972         if (err) {
4973                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4974                 ixgbe_dev_clear_queues(dev);
4975                 return err;
4976         }
4977
4978         /* Set vfta */
4979         ixgbevf_set_vfta_all(dev, 1);
4980
4981         /* Set HW strip */
4982         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4983                 ETH_VLAN_EXTEND_MASK;
4984         err = ixgbevf_vlan_offload_set(dev, mask);
4985         if (err) {
4986                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
4987                 ixgbe_dev_clear_queues(dev);
4988                 return err;
4989         }
4990
4991         ixgbevf_dev_rxtx_start(dev);
4992
4993         /* check and configure queue intr-vector mapping */
4994         if (rte_intr_cap_multiple(intr_handle) &&
4995             dev->data->dev_conf.intr_conf.rxq) {
4996                 /* According to datasheet, only vector 0/1/2 can be used,
4997                  * now only one vector is used for Rx queue
4998                  */
4999                 intr_vector = 1;
5000                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5001                         return -1;
5002         }
5003
5004         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5005                 intr_handle->intr_vec =
5006                         rte_zmalloc("intr_vec",
5007                                     dev->data->nb_rx_queues * sizeof(int), 0);
5008                 if (intr_handle->intr_vec == NULL) {
5009                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5010                                      " intr_vec", dev->data->nb_rx_queues);
5011                         return -ENOMEM;
5012                 }
5013         }
5014         ixgbevf_configure_msix(dev);
5015
5016         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5017          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5018          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5019          * is not cleared, it will fail when following rte_intr_enable( ) tries
5020          * to map Rx queue interrupt to other VFIO vectors.
5021          * So clear uio/vfio intr/evevnfd first to avoid failure.
5022          */
5023         rte_intr_disable(intr_handle);
5024
5025         rte_intr_enable(intr_handle);
5026
5027         /* Re-enable interrupt for VF */
5028         ixgbevf_intr_enable(hw);
5029
5030         return 0;
5031 }
5032
5033 static void
5034 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5035 {
5036         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5037         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5038         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5039
5040         PMD_INIT_FUNC_TRACE();
5041
5042         ixgbevf_intr_disable(hw);
5043
5044         hw->adapter_stopped = 1;
5045         ixgbe_stop_adapter(hw);
5046
5047         /*
5048           * Clear what we set, but we still keep shadow_vfta to
5049           * restore after device starts
5050           */
5051         ixgbevf_set_vfta_all(dev, 0);
5052
5053         /* Clear stored conf */
5054         dev->data->scattered_rx = 0;
5055
5056         ixgbe_dev_clear_queues(dev);
5057
5058         /* Clean datapath event and queue/vec mapping */
5059         rte_intr_efd_disable(intr_handle);
5060         if (intr_handle->intr_vec != NULL) {
5061                 rte_free(intr_handle->intr_vec);
5062                 intr_handle->intr_vec = NULL;
5063         }
5064 }
5065
5066 static void
5067 ixgbevf_dev_close(struct rte_eth_dev *dev)
5068 {
5069         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5070
5071         PMD_INIT_FUNC_TRACE();
5072
5073         ixgbe_reset_hw(hw);
5074
5075         ixgbevf_dev_stop(dev);
5076
5077         ixgbe_dev_free_queues(dev);
5078
5079         /**
5080          * Remove the VF MAC address ro ensure
5081          * that the VF traffic goes to the PF
5082          * after stop, close and detach of the VF
5083          **/
5084         ixgbevf_remove_mac_addr(dev, 0);
5085 }
5086
5087 /*
5088  * Reset VF device
5089  */
5090 static int
5091 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5092 {
5093         int ret;
5094
5095         ret = eth_ixgbevf_dev_uninit(dev);
5096         if (ret)
5097                 return ret;
5098
5099         ret = eth_ixgbevf_dev_init(dev);
5100
5101         return ret;
5102 }
5103
5104 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5105 {
5106         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5107         struct ixgbe_vfta *shadow_vfta =
5108                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5109         int i = 0, j = 0, vfta = 0, mask = 1;
5110
5111         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5112                 vfta = shadow_vfta->vfta[i];
5113                 if (vfta) {
5114                         mask = 1;
5115                         for (j = 0; j < 32; j++) {
5116                                 if (vfta & mask)
5117                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5118                                                        on, false);
5119                                 mask <<= 1;
5120                         }
5121                 }
5122         }
5123
5124 }
5125
5126 static int
5127 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5128 {
5129         struct ixgbe_hw *hw =
5130                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5131         struct ixgbe_vfta *shadow_vfta =
5132                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5133         uint32_t vid_idx = 0;
5134         uint32_t vid_bit = 0;
5135         int ret = 0;
5136
5137         PMD_INIT_FUNC_TRACE();
5138
5139         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5140         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5141         if (ret) {
5142                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5143                 return ret;
5144         }
5145         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5146         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5147
5148         /* Save what we set and retore it after device reset */
5149         if (on)
5150                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5151         else
5152                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5153
5154         return 0;
5155 }
5156
5157 static void
5158 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5159 {
5160         struct ixgbe_hw *hw =
5161                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5162         uint32_t ctrl;
5163
5164         PMD_INIT_FUNC_TRACE();
5165
5166         if (queue >= hw->mac.max_rx_queues)
5167                 return;
5168
5169         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5170         if (on)
5171                 ctrl |= IXGBE_RXDCTL_VME;
5172         else
5173                 ctrl &= ~IXGBE_RXDCTL_VME;
5174         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5175
5176         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5177 }
5178
5179 static int
5180 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5181 {
5182         struct ixgbe_hw *hw =
5183                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5184         uint16_t i;
5185         int on = 0;
5186
5187         /* VF function only support hw strip feature, others are not support */
5188         if (mask & ETH_VLAN_STRIP_MASK) {
5189                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5190
5191                 for (i = 0; i < hw->mac.max_rx_queues; i++)
5192                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5193         }
5194
5195         return 0;
5196 }
5197
5198 int
5199 ixgbe_vt_check(struct ixgbe_hw *hw)
5200 {
5201         uint32_t reg_val;
5202
5203         /* if Virtualization Technology is enabled */
5204         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5205         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5206                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5207                 return -1;
5208         }
5209
5210         return 0;
5211 }
5212
5213 static uint32_t
5214 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5215 {
5216         uint32_t vector = 0;
5217
5218         switch (hw->mac.mc_filter_type) {
5219         case 0:   /* use bits [47:36] of the address */
5220                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5221                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5222                 break;
5223         case 1:   /* use bits [46:35] of the address */
5224                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5225                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5226                 break;
5227         case 2:   /* use bits [45:34] of the address */
5228                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5229                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5230                 break;
5231         case 3:   /* use bits [43:32] of the address */
5232                 vector = ((uc_addr->addr_bytes[4]) |
5233                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5234                 break;
5235         default:  /* Invalid mc_filter_type */
5236                 break;
5237         }
5238
5239         /* vector can only be 12-bits or boundary will be exceeded */
5240         vector &= 0xFFF;
5241         return vector;
5242 }
5243
5244 static int
5245 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5246                         uint8_t on)
5247 {
5248         uint32_t vector;
5249         uint32_t uta_idx;
5250         uint32_t reg_val;
5251         uint32_t uta_shift;
5252         uint32_t rc;
5253         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5254         const uint32_t ixgbe_uta_bit_shift = 5;
5255         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5256         const uint32_t bit1 = 0x1;
5257
5258         struct ixgbe_hw *hw =
5259                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5260         struct ixgbe_uta_info *uta_info =
5261                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5262
5263         /* The UTA table only exists on 82599 hardware and newer */
5264         if (hw->mac.type < ixgbe_mac_82599EB)
5265                 return -ENOTSUP;
5266
5267         vector = ixgbe_uta_vector(hw, mac_addr);
5268         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5269         uta_shift = vector & ixgbe_uta_bit_mask;
5270
5271         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5272         if (rc == on)
5273                 return 0;
5274
5275         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5276         if (on) {
5277                 uta_info->uta_in_use++;
5278                 reg_val |= (bit1 << uta_shift);
5279                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5280         } else {
5281                 uta_info->uta_in_use--;
5282                 reg_val &= ~(bit1 << uta_shift);
5283                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5284         }
5285
5286         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5287
5288         if (uta_info->uta_in_use > 0)
5289                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5290                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5291         else
5292                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5293
5294         return 0;
5295 }
5296
5297 static int
5298 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5299 {
5300         int i;
5301         struct ixgbe_hw *hw =
5302                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5303         struct ixgbe_uta_info *uta_info =
5304                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5305
5306         /* The UTA table only exists on 82599 hardware and newer */
5307         if (hw->mac.type < ixgbe_mac_82599EB)
5308                 return -ENOTSUP;
5309
5310         if (on) {
5311                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5312                         uta_info->uta_shadow[i] = ~0;
5313                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5314                 }
5315         } else {
5316                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5317                         uta_info->uta_shadow[i] = 0;
5318                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5319                 }
5320         }
5321         return 0;
5322
5323 }
5324
5325 uint32_t
5326 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5327 {
5328         uint32_t new_val = orig_val;
5329
5330         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5331                 new_val |= IXGBE_VMOLR_AUPE;
5332         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5333                 new_val |= IXGBE_VMOLR_ROMPE;
5334         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5335                 new_val |= IXGBE_VMOLR_ROPE;
5336         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5337                 new_val |= IXGBE_VMOLR_BAM;
5338         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5339                 new_val |= IXGBE_VMOLR_MPE;
5340
5341         return new_val;
5342 }
5343
5344 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5345 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5346 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5347 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5348 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5349         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5350         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5351
5352 static int
5353 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5354                       struct rte_eth_mirror_conf *mirror_conf,
5355                       uint8_t rule_id, uint8_t on)
5356 {
5357         uint32_t mr_ctl, vlvf;
5358         uint32_t mp_lsb = 0;
5359         uint32_t mv_msb = 0;
5360         uint32_t mv_lsb = 0;
5361         uint32_t mp_msb = 0;
5362         uint8_t i = 0;
5363         int reg_index = 0;
5364         uint64_t vlan_mask = 0;
5365
5366         const uint8_t pool_mask_offset = 32;
5367         const uint8_t vlan_mask_offset = 32;
5368         const uint8_t dst_pool_offset = 8;
5369         const uint8_t rule_mr_offset  = 4;
5370         const uint8_t mirror_rule_mask = 0x0F;
5371
5372         struct ixgbe_mirror_info *mr_info =
5373                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5374         struct ixgbe_hw *hw =
5375                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5376         uint8_t mirror_type = 0;
5377
5378         if (ixgbe_vt_check(hw) < 0)
5379                 return -ENOTSUP;
5380
5381         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5382                 return -EINVAL;
5383
5384         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5385                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5386                             mirror_conf->rule_type);
5387                 return -EINVAL;
5388         }
5389
5390         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5391                 mirror_type |= IXGBE_MRCTL_VLME;
5392                 /* Check if vlan id is valid and find conresponding VLAN ID
5393                  * index in VLVF
5394                  */
5395                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5396                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5397                                 /* search vlan id related pool vlan filter
5398                                  * index
5399                                  */
5400                                 reg_index = ixgbe_find_vlvf_slot(
5401                                                 hw,
5402                                                 mirror_conf->vlan.vlan_id[i],
5403                                                 false);
5404                                 if (reg_index < 0)
5405                                         return -EINVAL;
5406                                 vlvf = IXGBE_READ_REG(hw,
5407                                                       IXGBE_VLVF(reg_index));
5408                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5409                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5410                                       mirror_conf->vlan.vlan_id[i]))
5411                                         vlan_mask |= (1ULL << reg_index);
5412                                 else
5413                                         return -EINVAL;
5414                         }
5415                 }
5416
5417                 if (on) {
5418                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5419                         mv_msb = vlan_mask >> vlan_mask_offset;
5420
5421                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5422                                                 mirror_conf->vlan.vlan_mask;
5423                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5424                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5425                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5426                                                 mirror_conf->vlan.vlan_id[i];
5427                         }
5428                 } else {
5429                         mv_lsb = 0;
5430                         mv_msb = 0;
5431                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5432                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5433                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5434                 }
5435         }
5436
5437         /**
5438          * if enable pool mirror, write related pool mask register,if disable
5439          * pool mirror, clear PFMRVM register
5440          */
5441         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5442                 mirror_type |= IXGBE_MRCTL_VPME;
5443                 if (on) {
5444                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5445                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5446                         mr_info->mr_conf[rule_id].pool_mask =
5447                                         mirror_conf->pool_mask;
5448
5449                 } else {
5450                         mp_lsb = 0;
5451                         mp_msb = 0;
5452                         mr_info->mr_conf[rule_id].pool_mask = 0;
5453                 }
5454         }
5455         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5456                 mirror_type |= IXGBE_MRCTL_UPME;
5457         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5458                 mirror_type |= IXGBE_MRCTL_DPME;
5459
5460         /* read  mirror control register and recalculate it */
5461         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5462
5463         if (on) {
5464                 mr_ctl |= mirror_type;
5465                 mr_ctl &= mirror_rule_mask;
5466                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5467         } else {
5468                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5469         }
5470
5471         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5472         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5473
5474         /* write mirrror control  register */
5475         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5476
5477         /* write pool mirrror control  register */
5478         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5479                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5480                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5481                                 mp_msb);
5482         }
5483         /* write VLAN mirrror control  register */
5484         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5485                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5486                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5487                                 mv_msb);
5488         }
5489
5490         return 0;
5491 }
5492
5493 static int
5494 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5495 {
5496         int mr_ctl = 0;
5497         uint32_t lsb_val = 0;
5498         uint32_t msb_val = 0;
5499         const uint8_t rule_mr_offset = 4;
5500
5501         struct ixgbe_hw *hw =
5502                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5503         struct ixgbe_mirror_info *mr_info =
5504                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5505
5506         if (ixgbe_vt_check(hw) < 0)
5507                 return -ENOTSUP;
5508
5509         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5510                 return -EINVAL;
5511
5512         memset(&mr_info->mr_conf[rule_id], 0,
5513                sizeof(struct rte_eth_mirror_conf));
5514
5515         /* clear PFVMCTL register */
5516         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5517
5518         /* clear pool mask register */
5519         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5520         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5521
5522         /* clear vlan mask register */
5523         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5524         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5525
5526         return 0;
5527 }
5528
5529 static int
5530 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5531 {
5532         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5533         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5534         uint32_t mask;
5535         struct ixgbe_hw *hw =
5536                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5537         uint32_t vec = IXGBE_MISC_VEC_ID;
5538
5539         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5540         if (rte_intr_allow_others(intr_handle))
5541                 vec = IXGBE_RX_VEC_START;
5542         mask |= (1 << vec);
5543         RTE_SET_USED(queue_id);
5544         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5545
5546         rte_intr_enable(intr_handle);
5547
5548         return 0;
5549 }
5550
5551 static int
5552 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5553 {
5554         uint32_t mask;
5555         struct ixgbe_hw *hw =
5556                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5557         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5558         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5559         uint32_t vec = IXGBE_MISC_VEC_ID;
5560
5561         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5562         if (rte_intr_allow_others(intr_handle))
5563                 vec = IXGBE_RX_VEC_START;
5564         mask &= ~(1 << vec);
5565         RTE_SET_USED(queue_id);
5566         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5567
5568         return 0;
5569 }
5570
5571 static int
5572 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5573 {
5574         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5575         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5576         uint32_t mask;
5577         struct ixgbe_hw *hw =
5578                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5579         struct ixgbe_interrupt *intr =
5580                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5581
5582         if (queue_id < 16) {
5583                 ixgbe_disable_intr(hw);
5584                 intr->mask |= (1 << queue_id);
5585                 ixgbe_enable_intr(dev);
5586         } else if (queue_id < 32) {
5587                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5588                 mask &= (1 << queue_id);
5589                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5590         } else if (queue_id < 64) {
5591                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5592                 mask &= (1 << (queue_id - 32));
5593                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5594         }
5595         rte_intr_enable(intr_handle);
5596
5597         return 0;
5598 }
5599
5600 static int
5601 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5602 {
5603         uint32_t mask;
5604         struct ixgbe_hw *hw =
5605                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5606         struct ixgbe_interrupt *intr =
5607                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5608
5609         if (queue_id < 16) {
5610                 ixgbe_disable_intr(hw);
5611                 intr->mask &= ~(1 << queue_id);
5612                 ixgbe_enable_intr(dev);
5613         } else if (queue_id < 32) {
5614                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5615                 mask &= ~(1 << queue_id);
5616                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5617         } else if (queue_id < 64) {
5618                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5619                 mask &= ~(1 << (queue_id - 32));
5620                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5621         }
5622
5623         return 0;
5624 }
5625
5626 static void
5627 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5628                      uint8_t queue, uint8_t msix_vector)
5629 {
5630         uint32_t tmp, idx;
5631
5632         if (direction == -1) {
5633                 /* other causes */
5634                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5635                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5636                 tmp &= ~0xFF;
5637                 tmp |= msix_vector;
5638                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5639         } else {
5640                 /* rx or tx cause */
5641                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5642                 idx = ((16 * (queue & 1)) + (8 * direction));
5643                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5644                 tmp &= ~(0xFF << idx);
5645                 tmp |= (msix_vector << idx);
5646                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5647         }
5648 }
5649
5650 /**
5651  * set the IVAR registers, mapping interrupt causes to vectors
5652  * @param hw
5653  *  pointer to ixgbe_hw struct
5654  * @direction
5655  *  0 for Rx, 1 for Tx, -1 for other causes
5656  * @queue
5657  *  queue to map the corresponding interrupt to
5658  * @msix_vector
5659  *  the vector to map to the corresponding queue
5660  */
5661 static void
5662 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5663                    uint8_t queue, uint8_t msix_vector)
5664 {
5665         uint32_t tmp, idx;
5666
5667         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5668         if (hw->mac.type == ixgbe_mac_82598EB) {
5669                 if (direction == -1)
5670                         direction = 0;
5671                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5672                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5673                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5674                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5675                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5676         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5677                         (hw->mac.type == ixgbe_mac_X540) ||
5678                         (hw->mac.type == ixgbe_mac_X550)) {
5679                 if (direction == -1) {
5680                         /* other causes */
5681                         idx = ((queue & 1) * 8);
5682                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5683                         tmp &= ~(0xFF << idx);
5684                         tmp |= (msix_vector << idx);
5685                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5686                 } else {
5687                         /* rx or tx causes */
5688                         idx = ((16 * (queue & 1)) + (8 * direction));
5689                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5690                         tmp &= ~(0xFF << idx);
5691                         tmp |= (msix_vector << idx);
5692                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5693                 }
5694         }
5695 }
5696
5697 static void
5698 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5699 {
5700         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5701         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5702         struct ixgbe_hw *hw =
5703                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5704         uint32_t q_idx;
5705         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5706         uint32_t base = IXGBE_MISC_VEC_ID;
5707
5708         /* Configure VF other cause ivar */
5709         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5710
5711         /* won't configure msix register if no mapping is done
5712          * between intr vector and event fd.
5713          */
5714         if (!rte_intr_dp_is_en(intr_handle))
5715                 return;
5716
5717         if (rte_intr_allow_others(intr_handle)) {
5718                 base = IXGBE_RX_VEC_START;
5719                 vector_idx = IXGBE_RX_VEC_START;
5720         }
5721
5722         /* Configure all RX queues of VF */
5723         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5724                 /* Force all queue use vector 0,
5725                  * as IXGBE_VF_MAXMSIVECOTR = 1
5726                  */
5727                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5728                 intr_handle->intr_vec[q_idx] = vector_idx;
5729                 if (vector_idx < base + intr_handle->nb_efd - 1)
5730                         vector_idx++;
5731         }
5732 }
5733
5734 /**
5735  * Sets up the hardware to properly generate MSI-X interrupts
5736  * @hw
5737  *  board private structure
5738  */
5739 static void
5740 ixgbe_configure_msix(struct rte_eth_dev *dev)
5741 {
5742         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5743         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5744         struct ixgbe_hw *hw =
5745                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5746         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5747         uint32_t vec = IXGBE_MISC_VEC_ID;
5748         uint32_t mask;
5749         uint32_t gpie;
5750
5751         /* won't configure msix register if no mapping is done
5752          * between intr vector and event fd
5753          */
5754         if (!rte_intr_dp_is_en(intr_handle))
5755                 return;
5756
5757         if (rte_intr_allow_others(intr_handle))
5758                 vec = base = IXGBE_RX_VEC_START;
5759
5760         /* setup GPIE for MSI-x mode */
5761         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5762         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5763                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5764         /* auto clearing and auto setting corresponding bits in EIMS
5765          * when MSI-X interrupt is triggered
5766          */
5767         if (hw->mac.type == ixgbe_mac_82598EB) {
5768                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5769         } else {
5770                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5771                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5772         }
5773         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5774
5775         /* Populate the IVAR table and set the ITR values to the
5776          * corresponding register.
5777          */
5778         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5779              queue_id++) {
5780                 /* by default, 1:1 mapping */
5781                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5782                 intr_handle->intr_vec[queue_id] = vec;
5783                 if (vec < base + intr_handle->nb_efd - 1)
5784                         vec++;
5785         }
5786
5787         switch (hw->mac.type) {
5788         case ixgbe_mac_82598EB:
5789                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5790                                    IXGBE_MISC_VEC_ID);
5791                 break;
5792         case ixgbe_mac_82599EB:
5793         case ixgbe_mac_X540:
5794         case ixgbe_mac_X550:
5795                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5796                 break;
5797         default:
5798                 break;
5799         }
5800         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5801                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5802
5803         /* set up to autoclear timer, and the vectors */
5804         mask = IXGBE_EIMS_ENABLE_MASK;
5805         mask &= ~(IXGBE_EIMS_OTHER |
5806                   IXGBE_EIMS_MAILBOX |
5807                   IXGBE_EIMS_LSC);
5808
5809         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5810 }
5811
5812 int
5813 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5814                            uint16_t queue_idx, uint16_t tx_rate)
5815 {
5816         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5817         uint32_t rf_dec, rf_int;
5818         uint32_t bcnrc_val;
5819         uint16_t link_speed = dev->data->dev_link.link_speed;
5820
5821         if (queue_idx >= hw->mac.max_tx_queues)
5822                 return -EINVAL;
5823
5824         if (tx_rate != 0) {
5825                 /* Calculate the rate factor values to set */
5826                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5827                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5828                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5829
5830                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5831                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5832                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5833                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5834         } else {
5835                 bcnrc_val = 0;
5836         }
5837
5838         /*
5839          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5840          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5841          * set as 0x4.
5842          */
5843         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5844                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5845                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5846                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5847                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5848         else
5849                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5850                         IXGBE_MMW_SIZE_DEFAULT);
5851
5852         /* Set RTTBCNRC of queue X */
5853         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5854         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5855         IXGBE_WRITE_FLUSH(hw);
5856
5857         return 0;
5858 }
5859
5860 static int
5861 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5862                      __attribute__((unused)) uint32_t index,
5863                      __attribute__((unused)) uint32_t pool)
5864 {
5865         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5866         int diag;
5867
5868         /*
5869          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5870          * operation. Trap this case to avoid exhausting the [very limited]
5871          * set of PF resources used to store VF MAC addresses.
5872          */
5873         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5874                 return -1;
5875         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5876         if (diag != 0)
5877                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5878                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5879                             mac_addr->addr_bytes[0],
5880                             mac_addr->addr_bytes[1],
5881                             mac_addr->addr_bytes[2],
5882                             mac_addr->addr_bytes[3],
5883                             mac_addr->addr_bytes[4],
5884                             mac_addr->addr_bytes[5],
5885                             diag);
5886         return diag;
5887 }
5888
5889 static void
5890 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5891 {
5892         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5893         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5894         struct ether_addr *mac_addr;
5895         uint32_t i;
5896         int diag;
5897
5898         /*
5899          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5900          * not support the deletion of a given MAC address.
5901          * Instead, it imposes to delete all MAC addresses, then to add again
5902          * all MAC addresses with the exception of the one to be deleted.
5903          */
5904         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5905
5906         /*
5907          * Add again all MAC addresses, with the exception of the deleted one
5908          * and of the permanent MAC address.
5909          */
5910         for (i = 0, mac_addr = dev->data->mac_addrs;
5911              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5912                 /* Skip the deleted MAC address */
5913                 if (i == index)
5914                         continue;
5915                 /* Skip NULL MAC addresses */
5916                 if (is_zero_ether_addr(mac_addr))
5917                         continue;
5918                 /* Skip the permanent MAC address */
5919                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5920                         continue;
5921                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5922                 if (diag != 0)
5923                         PMD_DRV_LOG(ERR,
5924                                     "Adding again MAC address "
5925                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5926                                     "diag=%d",
5927                                     mac_addr->addr_bytes[0],
5928                                     mac_addr->addr_bytes[1],
5929                                     mac_addr->addr_bytes[2],
5930                                     mac_addr->addr_bytes[3],
5931                                     mac_addr->addr_bytes[4],
5932                                     mac_addr->addr_bytes[5],
5933                                     diag);
5934         }
5935 }
5936
5937 static void
5938 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5939 {
5940         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5941
5942         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5943 }
5944
5945 int
5946 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5947                         struct rte_eth_syn_filter *filter,
5948                         bool add)
5949 {
5950         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5951         struct ixgbe_filter_info *filter_info =
5952                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5953         uint32_t syn_info;
5954         uint32_t synqf;
5955
5956         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5957                 return -EINVAL;
5958
5959         syn_info = filter_info->syn_info;
5960
5961         if (add) {
5962                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5963                         return -EINVAL;
5964                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5965                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5966
5967                 if (filter->hig_pri)
5968                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5969                 else
5970                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5971         } else {
5972                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5973                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5974                         return -ENOENT;
5975                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5976         }
5977
5978         filter_info->syn_info = synqf;
5979         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5980         IXGBE_WRITE_FLUSH(hw);
5981         return 0;
5982 }
5983
5984 static int
5985 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5986                         struct rte_eth_syn_filter *filter)
5987 {
5988         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5989         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5990
5991         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5992                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5993                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5994                 return 0;
5995         }
5996         return -ENOENT;
5997 }
5998
5999 static int
6000 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6001                         enum rte_filter_op filter_op,
6002                         void *arg)
6003 {
6004         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6005         int ret;
6006
6007         MAC_TYPE_FILTER_SUP(hw->mac.type);
6008
6009         if (filter_op == RTE_ETH_FILTER_NOP)
6010                 return 0;
6011
6012         if (arg == NULL) {
6013                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6014                             filter_op);
6015                 return -EINVAL;
6016         }
6017
6018         switch (filter_op) {
6019         case RTE_ETH_FILTER_ADD:
6020                 ret = ixgbe_syn_filter_set(dev,
6021                                 (struct rte_eth_syn_filter *)arg,
6022                                 TRUE);
6023                 break;
6024         case RTE_ETH_FILTER_DELETE:
6025                 ret = ixgbe_syn_filter_set(dev,
6026                                 (struct rte_eth_syn_filter *)arg,
6027                                 FALSE);
6028                 break;
6029         case RTE_ETH_FILTER_GET:
6030                 ret = ixgbe_syn_filter_get(dev,
6031                                 (struct rte_eth_syn_filter *)arg);
6032                 break;
6033         default:
6034                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6035                 ret = -EINVAL;
6036                 break;
6037         }
6038
6039         return ret;
6040 }
6041
6042
6043 static inline enum ixgbe_5tuple_protocol
6044 convert_protocol_type(uint8_t protocol_value)
6045 {
6046         if (protocol_value == IPPROTO_TCP)
6047                 return IXGBE_FILTER_PROTOCOL_TCP;
6048         else if (protocol_value == IPPROTO_UDP)
6049                 return IXGBE_FILTER_PROTOCOL_UDP;
6050         else if (protocol_value == IPPROTO_SCTP)
6051                 return IXGBE_FILTER_PROTOCOL_SCTP;
6052         else
6053                 return IXGBE_FILTER_PROTOCOL_NONE;
6054 }
6055
6056 /* inject a 5-tuple filter to HW */
6057 static inline void
6058 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6059                            struct ixgbe_5tuple_filter *filter)
6060 {
6061         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6062         int i;
6063         uint32_t ftqf, sdpqf;
6064         uint32_t l34timir = 0;
6065         uint8_t mask = 0xff;
6066
6067         i = filter->index;
6068
6069         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6070                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6071         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6072
6073         ftqf = (uint32_t)(filter->filter_info.proto &
6074                 IXGBE_FTQF_PROTOCOL_MASK);
6075         ftqf |= (uint32_t)((filter->filter_info.priority &
6076                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6077         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6078                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6079         if (filter->filter_info.dst_ip_mask == 0)
6080                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6081         if (filter->filter_info.src_port_mask == 0)
6082                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6083         if (filter->filter_info.dst_port_mask == 0)
6084                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6085         if (filter->filter_info.proto_mask == 0)
6086                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6087         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6088         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6089         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6090
6091         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6092         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6093         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6094         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6095
6096         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6097         l34timir |= (uint32_t)(filter->queue <<
6098                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6099         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6100 }
6101
6102 /*
6103  * add a 5tuple filter
6104  *
6105  * @param
6106  * dev: Pointer to struct rte_eth_dev.
6107  * index: the index the filter allocates.
6108  * filter: ponter to the filter that will be added.
6109  * rx_queue: the queue id the filter assigned to.
6110  *
6111  * @return
6112  *    - On success, zero.
6113  *    - On failure, a negative value.
6114  */
6115 static int
6116 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6117                         struct ixgbe_5tuple_filter *filter)
6118 {
6119         struct ixgbe_filter_info *filter_info =
6120                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6121         int i, idx, shift;
6122
6123         /*
6124          * look for an unused 5tuple filter index,
6125          * and insert the filter to list.
6126          */
6127         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6128                 idx = i / (sizeof(uint32_t) * NBBY);
6129                 shift = i % (sizeof(uint32_t) * NBBY);
6130                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6131                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6132                         filter->index = i;
6133                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6134                                           filter,
6135                                           entries);
6136                         break;
6137                 }
6138         }
6139         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6140                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6141                 return -ENOSYS;
6142         }
6143
6144         ixgbe_inject_5tuple_filter(dev, filter);
6145
6146         return 0;
6147 }
6148
6149 /*
6150  * remove a 5tuple filter
6151  *
6152  * @param
6153  * dev: Pointer to struct rte_eth_dev.
6154  * filter: the pointer of the filter will be removed.
6155  */
6156 static void
6157 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6158                         struct ixgbe_5tuple_filter *filter)
6159 {
6160         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6161         struct ixgbe_filter_info *filter_info =
6162                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6163         uint16_t index = filter->index;
6164
6165         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6166                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6167         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6168         rte_free(filter);
6169
6170         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6171         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6172         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6173         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6174         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6175 }
6176
6177 static int
6178 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6179 {
6180         struct ixgbe_hw *hw;
6181         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6182         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6183
6184         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6185
6186         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6187                 return -EINVAL;
6188
6189         /* refuse mtu that requires the support of scattered packets when this
6190          * feature has not been enabled before.
6191          */
6192         if (!rx_conf->enable_scatter &&
6193             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6194              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6195                 return -EINVAL;
6196
6197         /*
6198          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6199          * request of the version 2.0 of the mailbox API.
6200          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6201          * of the mailbox API.
6202          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6203          * prior to 3.11.33 which contains the following change:
6204          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6205          */
6206         ixgbevf_rlpml_set_vf(hw, max_frame);
6207
6208         /* update max frame size */
6209         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6210         return 0;
6211 }
6212
6213 static inline struct ixgbe_5tuple_filter *
6214 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6215                         struct ixgbe_5tuple_filter_info *key)
6216 {
6217         struct ixgbe_5tuple_filter *it;
6218
6219         TAILQ_FOREACH(it, filter_list, entries) {
6220                 if (memcmp(key, &it->filter_info,
6221                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6222                         return it;
6223                 }
6224         }
6225         return NULL;
6226 }
6227
6228 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6229 static inline int
6230 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6231                         struct ixgbe_5tuple_filter_info *filter_info)
6232 {
6233         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6234                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6235                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6236                 return -EINVAL;
6237
6238         switch (filter->dst_ip_mask) {
6239         case UINT32_MAX:
6240                 filter_info->dst_ip_mask = 0;
6241                 filter_info->dst_ip = filter->dst_ip;
6242                 break;
6243         case 0:
6244                 filter_info->dst_ip_mask = 1;
6245                 break;
6246         default:
6247                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6248                 return -EINVAL;
6249         }
6250
6251         switch (filter->src_ip_mask) {
6252         case UINT32_MAX:
6253                 filter_info->src_ip_mask = 0;
6254                 filter_info->src_ip = filter->src_ip;
6255                 break;
6256         case 0:
6257                 filter_info->src_ip_mask = 1;
6258                 break;
6259         default:
6260                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6261                 return -EINVAL;
6262         }
6263
6264         switch (filter->dst_port_mask) {
6265         case UINT16_MAX:
6266                 filter_info->dst_port_mask = 0;
6267                 filter_info->dst_port = filter->dst_port;
6268                 break;
6269         case 0:
6270                 filter_info->dst_port_mask = 1;
6271                 break;
6272         default:
6273                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6274                 return -EINVAL;
6275         }
6276
6277         switch (filter->src_port_mask) {
6278         case UINT16_MAX:
6279                 filter_info->src_port_mask = 0;
6280                 filter_info->src_port = filter->src_port;
6281                 break;
6282         case 0:
6283                 filter_info->src_port_mask = 1;
6284                 break;
6285         default:
6286                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6287                 return -EINVAL;
6288         }
6289
6290         switch (filter->proto_mask) {
6291         case UINT8_MAX:
6292                 filter_info->proto_mask = 0;
6293                 filter_info->proto =
6294                         convert_protocol_type(filter->proto);
6295                 break;
6296         case 0:
6297                 filter_info->proto_mask = 1;
6298                 break;
6299         default:
6300                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6301                 return -EINVAL;
6302         }
6303
6304         filter_info->priority = (uint8_t)filter->priority;
6305         return 0;
6306 }
6307
6308 /*
6309  * add or delete a ntuple filter
6310  *
6311  * @param
6312  * dev: Pointer to struct rte_eth_dev.
6313  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6314  * add: if true, add filter, if false, remove filter
6315  *
6316  * @return
6317  *    - On success, zero.
6318  *    - On failure, a negative value.
6319  */
6320 int
6321 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6322                         struct rte_eth_ntuple_filter *ntuple_filter,
6323                         bool add)
6324 {
6325         struct ixgbe_filter_info *filter_info =
6326                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6327         struct ixgbe_5tuple_filter_info filter_5tuple;
6328         struct ixgbe_5tuple_filter *filter;
6329         int ret;
6330
6331         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6332                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6333                 return -EINVAL;
6334         }
6335
6336         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6337         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6338         if (ret < 0)
6339                 return ret;
6340
6341         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6342                                          &filter_5tuple);
6343         if (filter != NULL && add) {
6344                 PMD_DRV_LOG(ERR, "filter exists.");
6345                 return -EEXIST;
6346         }
6347         if (filter == NULL && !add) {
6348                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6349                 return -ENOENT;
6350         }
6351
6352         if (add) {
6353                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6354                                 sizeof(struct ixgbe_5tuple_filter), 0);
6355                 if (filter == NULL)
6356                         return -ENOMEM;
6357                 rte_memcpy(&filter->filter_info,
6358                                  &filter_5tuple,
6359                                  sizeof(struct ixgbe_5tuple_filter_info));
6360                 filter->queue = ntuple_filter->queue;
6361                 ret = ixgbe_add_5tuple_filter(dev, filter);
6362                 if (ret < 0) {
6363                         rte_free(filter);
6364                         return ret;
6365                 }
6366         } else
6367                 ixgbe_remove_5tuple_filter(dev, filter);
6368
6369         return 0;
6370 }
6371
6372 /*
6373  * get a ntuple filter
6374  *
6375  * @param
6376  * dev: Pointer to struct rte_eth_dev.
6377  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6378  *
6379  * @return
6380  *    - On success, zero.
6381  *    - On failure, a negative value.
6382  */
6383 static int
6384 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6385                         struct rte_eth_ntuple_filter *ntuple_filter)
6386 {
6387         struct ixgbe_filter_info *filter_info =
6388                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6389         struct ixgbe_5tuple_filter_info filter_5tuple;
6390         struct ixgbe_5tuple_filter *filter;
6391         int ret;
6392
6393         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6394                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6395                 return -EINVAL;
6396         }
6397
6398         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6399         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6400         if (ret < 0)
6401                 return ret;
6402
6403         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6404                                          &filter_5tuple);
6405         if (filter == NULL) {
6406                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6407                 return -ENOENT;
6408         }
6409         ntuple_filter->queue = filter->queue;
6410         return 0;
6411 }
6412
6413 /*
6414  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6415  * @dev: pointer to rte_eth_dev structure
6416  * @filter_op:operation will be taken.
6417  * @arg: a pointer to specific structure corresponding to the filter_op
6418  *
6419  * @return
6420  *    - On success, zero.
6421  *    - On failure, a negative value.
6422  */
6423 static int
6424 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6425                                 enum rte_filter_op filter_op,
6426                                 void *arg)
6427 {
6428         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6429         int ret;
6430
6431         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6432
6433         if (filter_op == RTE_ETH_FILTER_NOP)
6434                 return 0;
6435
6436         if (arg == NULL) {
6437                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6438                             filter_op);
6439                 return -EINVAL;
6440         }
6441
6442         switch (filter_op) {
6443         case RTE_ETH_FILTER_ADD:
6444                 ret = ixgbe_add_del_ntuple_filter(dev,
6445                         (struct rte_eth_ntuple_filter *)arg,
6446                         TRUE);
6447                 break;
6448         case RTE_ETH_FILTER_DELETE:
6449                 ret = ixgbe_add_del_ntuple_filter(dev,
6450                         (struct rte_eth_ntuple_filter *)arg,
6451                         FALSE);
6452                 break;
6453         case RTE_ETH_FILTER_GET:
6454                 ret = ixgbe_get_ntuple_filter(dev,
6455                         (struct rte_eth_ntuple_filter *)arg);
6456                 break;
6457         default:
6458                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6459                 ret = -EINVAL;
6460                 break;
6461         }
6462         return ret;
6463 }
6464
6465 int
6466 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6467                         struct rte_eth_ethertype_filter *filter,
6468                         bool add)
6469 {
6470         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6471         struct ixgbe_filter_info *filter_info =
6472                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6473         uint32_t etqf = 0;
6474         uint32_t etqs = 0;
6475         int ret;
6476         struct ixgbe_ethertype_filter ethertype_filter;
6477
6478         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6479                 return -EINVAL;
6480
6481         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6482                 filter->ether_type == ETHER_TYPE_IPv6) {
6483                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6484                         " ethertype filter.", filter->ether_type);
6485                 return -EINVAL;
6486         }
6487
6488         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6489                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6490                 return -EINVAL;
6491         }
6492         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6493                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6494                 return -EINVAL;
6495         }
6496
6497         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6498         if (ret >= 0 && add) {
6499                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6500                             filter->ether_type);
6501                 return -EEXIST;
6502         }
6503         if (ret < 0 && !add) {
6504                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6505                             filter->ether_type);
6506                 return -ENOENT;
6507         }
6508
6509         if (add) {
6510                 etqf = IXGBE_ETQF_FILTER_EN;
6511                 etqf |= (uint32_t)filter->ether_type;
6512                 etqs |= (uint32_t)((filter->queue <<
6513                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6514                                     IXGBE_ETQS_RX_QUEUE);
6515                 etqs |= IXGBE_ETQS_QUEUE_EN;
6516
6517                 ethertype_filter.ethertype = filter->ether_type;
6518                 ethertype_filter.etqf = etqf;
6519                 ethertype_filter.etqs = etqs;
6520                 ethertype_filter.conf = FALSE;
6521                 ret = ixgbe_ethertype_filter_insert(filter_info,
6522                                                     &ethertype_filter);
6523                 if (ret < 0) {
6524                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6525                         return -ENOSPC;
6526                 }
6527         } else {
6528                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6529                 if (ret < 0)
6530                         return -ENOSYS;
6531         }
6532         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6533         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6534         IXGBE_WRITE_FLUSH(hw);
6535
6536         return 0;
6537 }
6538
6539 static int
6540 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6541                         struct rte_eth_ethertype_filter *filter)
6542 {
6543         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6544         struct ixgbe_filter_info *filter_info =
6545                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6546         uint32_t etqf, etqs;
6547         int ret;
6548
6549         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6550         if (ret < 0) {
6551                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6552                             filter->ether_type);
6553                 return -ENOENT;
6554         }
6555
6556         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6557         if (etqf & IXGBE_ETQF_FILTER_EN) {
6558                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6559                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6560                 filter->flags = 0;
6561                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6562                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6563                 return 0;
6564         }
6565         return -ENOENT;
6566 }
6567
6568 /*
6569  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6570  * @dev: pointer to rte_eth_dev structure
6571  * @filter_op:operation will be taken.
6572  * @arg: a pointer to specific structure corresponding to the filter_op
6573  */
6574 static int
6575 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6576                                 enum rte_filter_op filter_op,
6577                                 void *arg)
6578 {
6579         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6580         int ret;
6581
6582         MAC_TYPE_FILTER_SUP(hw->mac.type);
6583
6584         if (filter_op == RTE_ETH_FILTER_NOP)
6585                 return 0;
6586
6587         if (arg == NULL) {
6588                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6589                             filter_op);
6590                 return -EINVAL;
6591         }
6592
6593         switch (filter_op) {
6594         case RTE_ETH_FILTER_ADD:
6595                 ret = ixgbe_add_del_ethertype_filter(dev,
6596                         (struct rte_eth_ethertype_filter *)arg,
6597                         TRUE);
6598                 break;
6599         case RTE_ETH_FILTER_DELETE:
6600                 ret = ixgbe_add_del_ethertype_filter(dev,
6601                         (struct rte_eth_ethertype_filter *)arg,
6602                         FALSE);
6603                 break;
6604         case RTE_ETH_FILTER_GET:
6605                 ret = ixgbe_get_ethertype_filter(dev,
6606                         (struct rte_eth_ethertype_filter *)arg);
6607                 break;
6608         default:
6609                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6610                 ret = -EINVAL;
6611                 break;
6612         }
6613         return ret;
6614 }
6615
6616 static int
6617 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6618                      enum rte_filter_type filter_type,
6619                      enum rte_filter_op filter_op,
6620                      void *arg)
6621 {
6622         int ret = 0;
6623
6624         switch (filter_type) {
6625         case RTE_ETH_FILTER_NTUPLE:
6626                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6627                 break;
6628         case RTE_ETH_FILTER_ETHERTYPE:
6629                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6630                 break;
6631         case RTE_ETH_FILTER_SYN:
6632                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6633                 break;
6634         case RTE_ETH_FILTER_FDIR:
6635                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6636                 break;
6637         case RTE_ETH_FILTER_L2_TUNNEL:
6638                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6639                 break;
6640         case RTE_ETH_FILTER_GENERIC:
6641                 if (filter_op != RTE_ETH_FILTER_GET)
6642                         return -EINVAL;
6643                 *(const void **)arg = &ixgbe_flow_ops;
6644                 break;
6645         default:
6646                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6647                                                         filter_type);
6648                 ret = -EINVAL;
6649                 break;
6650         }
6651
6652         return ret;
6653 }
6654
6655 static u8 *
6656 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6657                         u8 **mc_addr_ptr, u32 *vmdq)
6658 {
6659         u8 *mc_addr;
6660
6661         *vmdq = 0;
6662         mc_addr = *mc_addr_ptr;
6663         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6664         return mc_addr;
6665 }
6666
6667 static int
6668 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6669                           struct ether_addr *mc_addr_set,
6670                           uint32_t nb_mc_addr)
6671 {
6672         struct ixgbe_hw *hw;
6673         u8 *mc_addr_list;
6674
6675         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6676         mc_addr_list = (u8 *)mc_addr_set;
6677         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6678                                          ixgbe_dev_addr_list_itr, TRUE);
6679 }
6680
6681 static uint64_t
6682 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6683 {
6684         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6685         uint64_t systime_cycles;
6686
6687         switch (hw->mac.type) {
6688         case ixgbe_mac_X550:
6689         case ixgbe_mac_X550EM_x:
6690         case ixgbe_mac_X550EM_a:
6691                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6692                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6693                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6694                                 * NSEC_PER_SEC;
6695                 break;
6696         default:
6697                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6698                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6699                                 << 32;
6700         }
6701
6702         return systime_cycles;
6703 }
6704
6705 static uint64_t
6706 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6707 {
6708         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6709         uint64_t rx_tstamp_cycles;
6710
6711         switch (hw->mac.type) {
6712         case ixgbe_mac_X550:
6713         case ixgbe_mac_X550EM_x:
6714         case ixgbe_mac_X550EM_a:
6715                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6716                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6717                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6718                                 * NSEC_PER_SEC;
6719                 break;
6720         default:
6721                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6722                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6723                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6724                                 << 32;
6725         }
6726
6727         return rx_tstamp_cycles;
6728 }
6729
6730 static uint64_t
6731 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6732 {
6733         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6734         uint64_t tx_tstamp_cycles;
6735
6736         switch (hw->mac.type) {
6737         case ixgbe_mac_X550:
6738         case ixgbe_mac_X550EM_x:
6739         case ixgbe_mac_X550EM_a:
6740                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6741                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6742                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6743                                 * NSEC_PER_SEC;
6744                 break;
6745         default:
6746                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6747                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6748                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6749                                 << 32;
6750         }
6751
6752         return tx_tstamp_cycles;
6753 }
6754
6755 static void
6756 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6757 {
6758         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6759         struct ixgbe_adapter *adapter =
6760                 (struct ixgbe_adapter *)dev->data->dev_private;
6761         struct rte_eth_link link;
6762         uint32_t incval = 0;
6763         uint32_t shift = 0;
6764
6765         /* Get current link speed. */
6766         ixgbe_dev_link_update(dev, 1);
6767         rte_eth_linkstatus_get(dev, &link);
6768
6769         switch (link.link_speed) {
6770         case ETH_SPEED_NUM_100M:
6771                 incval = IXGBE_INCVAL_100;
6772                 shift = IXGBE_INCVAL_SHIFT_100;
6773                 break;
6774         case ETH_SPEED_NUM_1G:
6775                 incval = IXGBE_INCVAL_1GB;
6776                 shift = IXGBE_INCVAL_SHIFT_1GB;
6777                 break;
6778         case ETH_SPEED_NUM_10G:
6779         default:
6780                 incval = IXGBE_INCVAL_10GB;
6781                 shift = IXGBE_INCVAL_SHIFT_10GB;
6782                 break;
6783         }
6784
6785         switch (hw->mac.type) {
6786         case ixgbe_mac_X550:
6787         case ixgbe_mac_X550EM_x:
6788         case ixgbe_mac_X550EM_a:
6789                 /* Independent of link speed. */
6790                 incval = 1;
6791                 /* Cycles read will be interpreted as ns. */
6792                 shift = 0;
6793                 /* Fall-through */
6794         case ixgbe_mac_X540:
6795                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6796                 break;
6797         case ixgbe_mac_82599EB:
6798                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6799                 shift -= IXGBE_INCVAL_SHIFT_82599;
6800                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6801                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6802                 break;
6803         default:
6804                 /* Not supported. */
6805                 return;
6806         }
6807
6808         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6809         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6810         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6811
6812         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6813         adapter->systime_tc.cc_shift = shift;
6814         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6815
6816         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6817         adapter->rx_tstamp_tc.cc_shift = shift;
6818         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6819
6820         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6821         adapter->tx_tstamp_tc.cc_shift = shift;
6822         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6823 }
6824
6825 static int
6826 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6827 {
6828         struct ixgbe_adapter *adapter =
6829                         (struct ixgbe_adapter *)dev->data->dev_private;
6830
6831         adapter->systime_tc.nsec += delta;
6832         adapter->rx_tstamp_tc.nsec += delta;
6833         adapter->tx_tstamp_tc.nsec += delta;
6834
6835         return 0;
6836 }
6837
6838 static int
6839 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6840 {
6841         uint64_t ns;
6842         struct ixgbe_adapter *adapter =
6843                         (struct ixgbe_adapter *)dev->data->dev_private;
6844
6845         ns = rte_timespec_to_ns(ts);
6846         /* Set the timecounters to a new value. */
6847         adapter->systime_tc.nsec = ns;
6848         adapter->rx_tstamp_tc.nsec = ns;
6849         adapter->tx_tstamp_tc.nsec = ns;
6850
6851         return 0;
6852 }
6853
6854 static int
6855 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6856 {
6857         uint64_t ns, systime_cycles;
6858         struct ixgbe_adapter *adapter =
6859                         (struct ixgbe_adapter *)dev->data->dev_private;
6860
6861         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6862         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6863         *ts = rte_ns_to_timespec(ns);
6864
6865         return 0;
6866 }
6867
6868 static int
6869 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6870 {
6871         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6872         uint32_t tsync_ctl;
6873         uint32_t tsauxc;
6874
6875         /* Stop the timesync system time. */
6876         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6877         /* Reset the timesync system time value. */
6878         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6879         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6880
6881         /* Enable system time for platforms where it isn't on by default. */
6882         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6883         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6884         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6885
6886         ixgbe_start_timecounters(dev);
6887
6888         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6889         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6890                         (ETHER_TYPE_1588 |
6891                          IXGBE_ETQF_FILTER_EN |
6892                          IXGBE_ETQF_1588));
6893
6894         /* Enable timestamping of received PTP packets. */
6895         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6896         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6897         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6898
6899         /* Enable timestamping of transmitted PTP packets. */
6900         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6901         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6902         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6903
6904         IXGBE_WRITE_FLUSH(hw);
6905
6906         return 0;
6907 }
6908
6909 static int
6910 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6911 {
6912         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6913         uint32_t tsync_ctl;
6914
6915         /* Disable timestamping of transmitted PTP packets. */
6916         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6917         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6918         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6919
6920         /* Disable timestamping of received PTP packets. */
6921         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6922         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6923         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6924
6925         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6926         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6927
6928         /* Stop incrementating the System Time registers. */
6929         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6930
6931         return 0;
6932 }
6933
6934 static int
6935 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6936                                  struct timespec *timestamp,
6937                                  uint32_t flags __rte_unused)
6938 {
6939         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6940         struct ixgbe_adapter *adapter =
6941                 (struct ixgbe_adapter *)dev->data->dev_private;
6942         uint32_t tsync_rxctl;
6943         uint64_t rx_tstamp_cycles;
6944         uint64_t ns;
6945
6946         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6947         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6948                 return -EINVAL;
6949
6950         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6951         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6952         *timestamp = rte_ns_to_timespec(ns);
6953
6954         return  0;
6955 }
6956
6957 static int
6958 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6959                                  struct timespec *timestamp)
6960 {
6961         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6962         struct ixgbe_adapter *adapter =
6963                 (struct ixgbe_adapter *)dev->data->dev_private;
6964         uint32_t tsync_txctl;
6965         uint64_t tx_tstamp_cycles;
6966         uint64_t ns;
6967
6968         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6969         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6970                 return -EINVAL;
6971
6972         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6973         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6974         *timestamp = rte_ns_to_timespec(ns);
6975
6976         return 0;
6977 }
6978
6979 static int
6980 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6981 {
6982         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6983         int count = 0;
6984         int g_ind = 0;
6985         const struct reg_info *reg_group;
6986         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6987                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6988
6989         while ((reg_group = reg_set[g_ind++]))
6990                 count += ixgbe_regs_group_count(reg_group);
6991
6992         return count;
6993 }
6994
6995 static int
6996 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6997 {
6998         int count = 0;
6999         int g_ind = 0;
7000         const struct reg_info *reg_group;
7001
7002         while ((reg_group = ixgbevf_regs[g_ind++]))
7003                 count += ixgbe_regs_group_count(reg_group);
7004
7005         return count;
7006 }
7007
7008 static int
7009 ixgbe_get_regs(struct rte_eth_dev *dev,
7010               struct rte_dev_reg_info *regs)
7011 {
7012         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7013         uint32_t *data = regs->data;
7014         int g_ind = 0;
7015         int count = 0;
7016         const struct reg_info *reg_group;
7017         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7018                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7019
7020         if (data == NULL) {
7021                 regs->length = ixgbe_get_reg_length(dev);
7022                 regs->width = sizeof(uint32_t);
7023                 return 0;
7024         }
7025
7026         /* Support only full register dump */
7027         if ((regs->length == 0) ||
7028             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7029                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7030                         hw->device_id;
7031                 while ((reg_group = reg_set[g_ind++]))
7032                         count += ixgbe_read_regs_group(dev, &data[count],
7033                                 reg_group);
7034                 return 0;
7035         }
7036
7037         return -ENOTSUP;
7038 }
7039
7040 static int
7041 ixgbevf_get_regs(struct rte_eth_dev *dev,
7042                 struct rte_dev_reg_info *regs)
7043 {
7044         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7045         uint32_t *data = regs->data;
7046         int g_ind = 0;
7047         int count = 0;
7048         const struct reg_info *reg_group;
7049
7050         if (data == NULL) {
7051                 regs->length = ixgbevf_get_reg_length(dev);
7052                 regs->width = sizeof(uint32_t);
7053                 return 0;
7054         }
7055
7056         /* Support only full register dump */
7057         if ((regs->length == 0) ||
7058             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7059                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7060                         hw->device_id;
7061                 while ((reg_group = ixgbevf_regs[g_ind++]))
7062                         count += ixgbe_read_regs_group(dev, &data[count],
7063                                                       reg_group);
7064                 return 0;
7065         }
7066
7067         return -ENOTSUP;
7068 }
7069
7070 static int
7071 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7072 {
7073         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7074
7075         /* Return unit is byte count */
7076         return hw->eeprom.word_size * 2;
7077 }
7078
7079 static int
7080 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7081                 struct rte_dev_eeprom_info *in_eeprom)
7082 {
7083         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7084         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7085         uint16_t *data = in_eeprom->data;
7086         int first, length;
7087
7088         first = in_eeprom->offset >> 1;
7089         length = in_eeprom->length >> 1;
7090         if ((first > hw->eeprom.word_size) ||
7091             ((first + length) > hw->eeprom.word_size))
7092                 return -EINVAL;
7093
7094         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7095
7096         return eeprom->ops.read_buffer(hw, first, length, data);
7097 }
7098
7099 static int
7100 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7101                 struct rte_dev_eeprom_info *in_eeprom)
7102 {
7103         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7104         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7105         uint16_t *data = in_eeprom->data;
7106         int first, length;
7107
7108         first = in_eeprom->offset >> 1;
7109         length = in_eeprom->length >> 1;
7110         if ((first > hw->eeprom.word_size) ||
7111             ((first + length) > hw->eeprom.word_size))
7112                 return -EINVAL;
7113
7114         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7115
7116         return eeprom->ops.write_buffer(hw,  first, length, data);
7117 }
7118
7119 uint16_t
7120 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7121         switch (mac_type) {
7122         case ixgbe_mac_X550:
7123         case ixgbe_mac_X550EM_x:
7124         case ixgbe_mac_X550EM_a:
7125                 return ETH_RSS_RETA_SIZE_512;
7126         case ixgbe_mac_X550_vf:
7127         case ixgbe_mac_X550EM_x_vf:
7128         case ixgbe_mac_X550EM_a_vf:
7129                 return ETH_RSS_RETA_SIZE_64;
7130         default:
7131                 return ETH_RSS_RETA_SIZE_128;
7132         }
7133 }
7134
7135 uint32_t
7136 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7137         switch (mac_type) {
7138         case ixgbe_mac_X550:
7139         case ixgbe_mac_X550EM_x:
7140         case ixgbe_mac_X550EM_a:
7141                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7142                         return IXGBE_RETA(reta_idx >> 2);
7143                 else
7144                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7145         case ixgbe_mac_X550_vf:
7146         case ixgbe_mac_X550EM_x_vf:
7147         case ixgbe_mac_X550EM_a_vf:
7148                 return IXGBE_VFRETA(reta_idx >> 2);
7149         default:
7150                 return IXGBE_RETA(reta_idx >> 2);
7151         }
7152 }
7153
7154 uint32_t
7155 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7156         switch (mac_type) {
7157         case ixgbe_mac_X550_vf:
7158         case ixgbe_mac_X550EM_x_vf:
7159         case ixgbe_mac_X550EM_a_vf:
7160                 return IXGBE_VFMRQC;
7161         default:
7162                 return IXGBE_MRQC;
7163         }
7164 }
7165
7166 uint32_t
7167 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7168         switch (mac_type) {
7169         case ixgbe_mac_X550_vf:
7170         case ixgbe_mac_X550EM_x_vf:
7171         case ixgbe_mac_X550EM_a_vf:
7172                 return IXGBE_VFRSSRK(i);
7173         default:
7174                 return IXGBE_RSSRK(i);
7175         }
7176 }
7177
7178 bool
7179 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7180         switch (mac_type) {
7181         case ixgbe_mac_82599_vf:
7182         case ixgbe_mac_X540_vf:
7183                 return 0;
7184         default:
7185                 return 1;
7186         }
7187 }
7188
7189 static int
7190 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7191                         struct rte_eth_dcb_info *dcb_info)
7192 {
7193         struct ixgbe_dcb_config *dcb_config =
7194                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7195         struct ixgbe_dcb_tc_config *tc;
7196         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7197         uint8_t nb_tcs;
7198         uint8_t i, j;
7199
7200         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7201                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7202         else
7203                 dcb_info->nb_tcs = 1;
7204
7205         tc_queue = &dcb_info->tc_queue;
7206         nb_tcs = dcb_info->nb_tcs;
7207
7208         if (dcb_config->vt_mode) { /* vt is enabled*/
7209                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7210                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7211                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7212                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7213                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7214                         for (j = 0; j < nb_tcs; j++) {
7215                                 tc_queue->tc_rxq[0][j].base = j;
7216                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7217                                 tc_queue->tc_txq[0][j].base = j;
7218                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7219                         }
7220                 } else {
7221                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7222                                 for (j = 0; j < nb_tcs; j++) {
7223                                         tc_queue->tc_rxq[i][j].base =
7224                                                 i * nb_tcs + j;
7225                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7226                                         tc_queue->tc_txq[i][j].base =
7227                                                 i * nb_tcs + j;
7228                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7229                                 }
7230                         }
7231                 }
7232         } else { /* vt is disabled*/
7233                 struct rte_eth_dcb_rx_conf *rx_conf =
7234                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7235                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7236                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7237                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7238                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7239                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7240                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7241                         }
7242                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7243                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7244                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7245                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7246                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7247                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7248                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7249                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7250                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7251                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7252                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7253                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7254                         }
7255                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7256                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7257                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7258                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7259                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7260                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7261                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7262                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7263                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7264                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7265                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7266                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7267                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7268                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7269                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7270                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7271                 }
7272         }
7273         for (i = 0; i < dcb_info->nb_tcs; i++) {
7274                 tc = &dcb_config->tc_config[i];
7275                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7276         }
7277         return 0;
7278 }
7279
7280 /* Update e-tag ether type */
7281 static int
7282 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7283                             uint16_t ether_type)
7284 {
7285         uint32_t etag_etype;
7286
7287         if (hw->mac.type != ixgbe_mac_X550 &&
7288             hw->mac.type != ixgbe_mac_X550EM_x &&
7289             hw->mac.type != ixgbe_mac_X550EM_a) {
7290                 return -ENOTSUP;
7291         }
7292
7293         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7294         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7295         etag_etype |= ether_type;
7296         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7297         IXGBE_WRITE_FLUSH(hw);
7298
7299         return 0;
7300 }
7301
7302 /* Config l2 tunnel ether type */
7303 static int
7304 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7305                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7306 {
7307         int ret = 0;
7308         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7309         struct ixgbe_l2_tn_info *l2_tn_info =
7310                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7311
7312         if (l2_tunnel == NULL)
7313                 return -EINVAL;
7314
7315         switch (l2_tunnel->l2_tunnel_type) {
7316         case RTE_L2_TUNNEL_TYPE_E_TAG:
7317                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7318                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7319                 break;
7320         default:
7321                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7322                 ret = -EINVAL;
7323                 break;
7324         }
7325
7326         return ret;
7327 }
7328
7329 /* Enable e-tag tunnel */
7330 static int
7331 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7332 {
7333         uint32_t etag_etype;
7334
7335         if (hw->mac.type != ixgbe_mac_X550 &&
7336             hw->mac.type != ixgbe_mac_X550EM_x &&
7337             hw->mac.type != ixgbe_mac_X550EM_a) {
7338                 return -ENOTSUP;
7339         }
7340
7341         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7342         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7343         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7344         IXGBE_WRITE_FLUSH(hw);
7345
7346         return 0;
7347 }
7348
7349 /* Enable l2 tunnel */
7350 static int
7351 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7352                            enum rte_eth_tunnel_type l2_tunnel_type)
7353 {
7354         int ret = 0;
7355         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7356         struct ixgbe_l2_tn_info *l2_tn_info =
7357                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7358
7359         switch (l2_tunnel_type) {
7360         case RTE_L2_TUNNEL_TYPE_E_TAG:
7361                 l2_tn_info->e_tag_en = TRUE;
7362                 ret = ixgbe_e_tag_enable(hw);
7363                 break;
7364         default:
7365                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7366                 ret = -EINVAL;
7367                 break;
7368         }
7369
7370         return ret;
7371 }
7372
7373 /* Disable e-tag tunnel */
7374 static int
7375 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7376 {
7377         uint32_t etag_etype;
7378
7379         if (hw->mac.type != ixgbe_mac_X550 &&
7380             hw->mac.type != ixgbe_mac_X550EM_x &&
7381             hw->mac.type != ixgbe_mac_X550EM_a) {
7382                 return -ENOTSUP;
7383         }
7384
7385         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7386         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7387         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7388         IXGBE_WRITE_FLUSH(hw);
7389
7390         return 0;
7391 }
7392
7393 /* Disable l2 tunnel */
7394 static int
7395 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7396                             enum rte_eth_tunnel_type l2_tunnel_type)
7397 {
7398         int ret = 0;
7399         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7400         struct ixgbe_l2_tn_info *l2_tn_info =
7401                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7402
7403         switch (l2_tunnel_type) {
7404         case RTE_L2_TUNNEL_TYPE_E_TAG:
7405                 l2_tn_info->e_tag_en = FALSE;
7406                 ret = ixgbe_e_tag_disable(hw);
7407                 break;
7408         default:
7409                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7410                 ret = -EINVAL;
7411                 break;
7412         }
7413
7414         return ret;
7415 }
7416
7417 static int
7418 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7419                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7420 {
7421         int ret = 0;
7422         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7423         uint32_t i, rar_entries;
7424         uint32_t rar_low, rar_high;
7425
7426         if (hw->mac.type != ixgbe_mac_X550 &&
7427             hw->mac.type != ixgbe_mac_X550EM_x &&
7428             hw->mac.type != ixgbe_mac_X550EM_a) {
7429                 return -ENOTSUP;
7430         }
7431
7432         rar_entries = ixgbe_get_num_rx_addrs(hw);
7433
7434         for (i = 1; i < rar_entries; i++) {
7435                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7436                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7437                 if ((rar_high & IXGBE_RAH_AV) &&
7438                     (rar_high & IXGBE_RAH_ADTYPE) &&
7439                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7440                      l2_tunnel->tunnel_id)) {
7441                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7442                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7443
7444                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7445
7446                         return ret;
7447                 }
7448         }
7449
7450         return ret;
7451 }
7452
7453 static int
7454 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7455                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7456 {
7457         int ret = 0;
7458         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7459         uint32_t i, rar_entries;
7460         uint32_t rar_low, rar_high;
7461
7462         if (hw->mac.type != ixgbe_mac_X550 &&
7463             hw->mac.type != ixgbe_mac_X550EM_x &&
7464             hw->mac.type != ixgbe_mac_X550EM_a) {
7465                 return -ENOTSUP;
7466         }
7467
7468         /* One entry for one tunnel. Try to remove potential existing entry. */
7469         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7470
7471         rar_entries = ixgbe_get_num_rx_addrs(hw);
7472
7473         for (i = 1; i < rar_entries; i++) {
7474                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7475                 if (rar_high & IXGBE_RAH_AV) {
7476                         continue;
7477                 } else {
7478                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7479                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7480                         rar_low = l2_tunnel->tunnel_id;
7481
7482                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7483                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7484
7485                         return ret;
7486                 }
7487         }
7488
7489         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7490                      " Please remove a rule before adding a new one.");
7491         return -EINVAL;
7492 }
7493
7494 static inline struct ixgbe_l2_tn_filter *
7495 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7496                           struct ixgbe_l2_tn_key *key)
7497 {
7498         int ret;
7499
7500         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7501         if (ret < 0)
7502                 return NULL;
7503
7504         return l2_tn_info->hash_map[ret];
7505 }
7506
7507 static inline int
7508 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7509                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7510 {
7511         int ret;
7512
7513         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7514                                &l2_tn_filter->key);
7515
7516         if (ret < 0) {
7517                 PMD_DRV_LOG(ERR,
7518                             "Failed to insert L2 tunnel filter"
7519                             " to hash table %d!",
7520                             ret);
7521                 return ret;
7522         }
7523
7524         l2_tn_info->hash_map[ret] = l2_tn_filter;
7525
7526         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7527
7528         return 0;
7529 }
7530
7531 static inline int
7532 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7533                           struct ixgbe_l2_tn_key *key)
7534 {
7535         int ret;
7536         struct ixgbe_l2_tn_filter *l2_tn_filter;
7537
7538         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7539
7540         if (ret < 0) {
7541                 PMD_DRV_LOG(ERR,
7542                             "No such L2 tunnel filter to delete %d!",
7543                             ret);
7544                 return ret;
7545         }
7546
7547         l2_tn_filter = l2_tn_info->hash_map[ret];
7548         l2_tn_info->hash_map[ret] = NULL;
7549
7550         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7551         rte_free(l2_tn_filter);
7552
7553         return 0;
7554 }
7555
7556 /* Add l2 tunnel filter */
7557 int
7558 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7559                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7560                                bool restore)
7561 {
7562         int ret;
7563         struct ixgbe_l2_tn_info *l2_tn_info =
7564                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7565         struct ixgbe_l2_tn_key key;
7566         struct ixgbe_l2_tn_filter *node;
7567
7568         if (!restore) {
7569                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7570                 key.tn_id = l2_tunnel->tunnel_id;
7571
7572                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7573
7574                 if (node) {
7575                         PMD_DRV_LOG(ERR,
7576                                     "The L2 tunnel filter already exists!");
7577                         return -EINVAL;
7578                 }
7579
7580                 node = rte_zmalloc("ixgbe_l2_tn",
7581                                    sizeof(struct ixgbe_l2_tn_filter),
7582                                    0);
7583                 if (!node)
7584                         return -ENOMEM;
7585
7586                 rte_memcpy(&node->key,
7587                                  &key,
7588                                  sizeof(struct ixgbe_l2_tn_key));
7589                 node->pool = l2_tunnel->pool;
7590                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7591                 if (ret < 0) {
7592                         rte_free(node);
7593                         return ret;
7594                 }
7595         }
7596
7597         switch (l2_tunnel->l2_tunnel_type) {
7598         case RTE_L2_TUNNEL_TYPE_E_TAG:
7599                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7600                 break;
7601         default:
7602                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7603                 ret = -EINVAL;
7604                 break;
7605         }
7606
7607         if ((!restore) && (ret < 0))
7608                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7609
7610         return ret;
7611 }
7612
7613 /* Delete l2 tunnel filter */
7614 int
7615 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7616                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7617 {
7618         int ret;
7619         struct ixgbe_l2_tn_info *l2_tn_info =
7620                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7621         struct ixgbe_l2_tn_key key;
7622
7623         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7624         key.tn_id = l2_tunnel->tunnel_id;
7625         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7626         if (ret < 0)
7627                 return ret;
7628
7629         switch (l2_tunnel->l2_tunnel_type) {
7630         case RTE_L2_TUNNEL_TYPE_E_TAG:
7631                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7632                 break;
7633         default:
7634                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7635                 ret = -EINVAL;
7636                 break;
7637         }
7638
7639         return ret;
7640 }
7641
7642 /**
7643  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7644  * @dev: pointer to rte_eth_dev structure
7645  * @filter_op:operation will be taken.
7646  * @arg: a pointer to specific structure corresponding to the filter_op
7647  */
7648 static int
7649 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7650                                   enum rte_filter_op filter_op,
7651                                   void *arg)
7652 {
7653         int ret;
7654
7655         if (filter_op == RTE_ETH_FILTER_NOP)
7656                 return 0;
7657
7658         if (arg == NULL) {
7659                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7660                             filter_op);
7661                 return -EINVAL;
7662         }
7663
7664         switch (filter_op) {
7665         case RTE_ETH_FILTER_ADD:
7666                 ret = ixgbe_dev_l2_tunnel_filter_add
7667                         (dev,
7668                          (struct rte_eth_l2_tunnel_conf *)arg,
7669                          FALSE);
7670                 break;
7671         case RTE_ETH_FILTER_DELETE:
7672                 ret = ixgbe_dev_l2_tunnel_filter_del
7673                         (dev,
7674                          (struct rte_eth_l2_tunnel_conf *)arg);
7675                 break;
7676         default:
7677                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7678                 ret = -EINVAL;
7679                 break;
7680         }
7681         return ret;
7682 }
7683
7684 static int
7685 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7686 {
7687         int ret = 0;
7688         uint32_t ctrl;
7689         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7690
7691         if (hw->mac.type != ixgbe_mac_X550 &&
7692             hw->mac.type != ixgbe_mac_X550EM_x &&
7693             hw->mac.type != ixgbe_mac_X550EM_a) {
7694                 return -ENOTSUP;
7695         }
7696
7697         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7698         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7699         if (en)
7700                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7701         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7702
7703         return ret;
7704 }
7705
7706 /* Enable l2 tunnel forwarding */
7707 static int
7708 ixgbe_dev_l2_tunnel_forwarding_enable
7709         (struct rte_eth_dev *dev,
7710          enum rte_eth_tunnel_type l2_tunnel_type)
7711 {
7712         struct ixgbe_l2_tn_info *l2_tn_info =
7713                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7714         int ret = 0;
7715
7716         switch (l2_tunnel_type) {
7717         case RTE_L2_TUNNEL_TYPE_E_TAG:
7718                 l2_tn_info->e_tag_fwd_en = TRUE;
7719                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7720                 break;
7721         default:
7722                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7723                 ret = -EINVAL;
7724                 break;
7725         }
7726
7727         return ret;
7728 }
7729
7730 /* Disable l2 tunnel forwarding */
7731 static int
7732 ixgbe_dev_l2_tunnel_forwarding_disable
7733         (struct rte_eth_dev *dev,
7734          enum rte_eth_tunnel_type l2_tunnel_type)
7735 {
7736         struct ixgbe_l2_tn_info *l2_tn_info =
7737                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7738         int ret = 0;
7739
7740         switch (l2_tunnel_type) {
7741         case RTE_L2_TUNNEL_TYPE_E_TAG:
7742                 l2_tn_info->e_tag_fwd_en = FALSE;
7743                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7744                 break;
7745         default:
7746                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7747                 ret = -EINVAL;
7748                 break;
7749         }
7750
7751         return ret;
7752 }
7753
7754 static int
7755 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7756                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7757                              bool en)
7758 {
7759         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7760         int ret = 0;
7761         uint32_t vmtir, vmvir;
7762         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7763
7764         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7765                 PMD_DRV_LOG(ERR,
7766                             "VF id %u should be less than %u",
7767                             l2_tunnel->vf_id,
7768                             pci_dev->max_vfs);
7769                 return -EINVAL;
7770         }
7771
7772         if (hw->mac.type != ixgbe_mac_X550 &&
7773             hw->mac.type != ixgbe_mac_X550EM_x &&
7774             hw->mac.type != ixgbe_mac_X550EM_a) {
7775                 return -ENOTSUP;
7776         }
7777
7778         if (en)
7779                 vmtir = l2_tunnel->tunnel_id;
7780         else
7781                 vmtir = 0;
7782
7783         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7784
7785         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7786         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7787         if (en)
7788                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7789         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7790
7791         return ret;
7792 }
7793
7794 /* Enable l2 tunnel tag insertion */
7795 static int
7796 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7797                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7798 {
7799         int ret = 0;
7800
7801         switch (l2_tunnel->l2_tunnel_type) {
7802         case RTE_L2_TUNNEL_TYPE_E_TAG:
7803                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7804                 break;
7805         default:
7806                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7807                 ret = -EINVAL;
7808                 break;
7809         }
7810
7811         return ret;
7812 }
7813
7814 /* Disable l2 tunnel tag insertion */
7815 static int
7816 ixgbe_dev_l2_tunnel_insertion_disable
7817         (struct rte_eth_dev *dev,
7818          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7819 {
7820         int ret = 0;
7821
7822         switch (l2_tunnel->l2_tunnel_type) {
7823         case RTE_L2_TUNNEL_TYPE_E_TAG:
7824                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7825                 break;
7826         default:
7827                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7828                 ret = -EINVAL;
7829                 break;
7830         }
7831
7832         return ret;
7833 }
7834
7835 static int
7836 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7837                              bool en)
7838 {
7839         int ret = 0;
7840         uint32_t qde;
7841         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7842
7843         if (hw->mac.type != ixgbe_mac_X550 &&
7844             hw->mac.type != ixgbe_mac_X550EM_x &&
7845             hw->mac.type != ixgbe_mac_X550EM_a) {
7846                 return -ENOTSUP;
7847         }
7848
7849         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7850         if (en)
7851                 qde |= IXGBE_QDE_STRIP_TAG;
7852         else
7853                 qde &= ~IXGBE_QDE_STRIP_TAG;
7854         qde &= ~IXGBE_QDE_READ;
7855         qde |= IXGBE_QDE_WRITE;
7856         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7857
7858         return ret;
7859 }
7860
7861 /* Enable l2 tunnel tag stripping */
7862 static int
7863 ixgbe_dev_l2_tunnel_stripping_enable
7864         (struct rte_eth_dev *dev,
7865          enum rte_eth_tunnel_type l2_tunnel_type)
7866 {
7867         int ret = 0;
7868
7869         switch (l2_tunnel_type) {
7870         case RTE_L2_TUNNEL_TYPE_E_TAG:
7871                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7872                 break;
7873         default:
7874                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7875                 ret = -EINVAL;
7876                 break;
7877         }
7878
7879         return ret;
7880 }
7881
7882 /* Disable l2 tunnel tag stripping */
7883 static int
7884 ixgbe_dev_l2_tunnel_stripping_disable
7885         (struct rte_eth_dev *dev,
7886          enum rte_eth_tunnel_type l2_tunnel_type)
7887 {
7888         int ret = 0;
7889
7890         switch (l2_tunnel_type) {
7891         case RTE_L2_TUNNEL_TYPE_E_TAG:
7892                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7893                 break;
7894         default:
7895                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7896                 ret = -EINVAL;
7897                 break;
7898         }
7899
7900         return ret;
7901 }
7902
7903 /* Enable/disable l2 tunnel offload functions */
7904 static int
7905 ixgbe_dev_l2_tunnel_offload_set
7906         (struct rte_eth_dev *dev,
7907          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7908          uint32_t mask,
7909          uint8_t en)
7910 {
7911         int ret = 0;
7912
7913         if (l2_tunnel == NULL)
7914                 return -EINVAL;
7915
7916         ret = -EINVAL;
7917         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7918                 if (en)
7919                         ret = ixgbe_dev_l2_tunnel_enable(
7920                                 dev,
7921                                 l2_tunnel->l2_tunnel_type);
7922                 else
7923                         ret = ixgbe_dev_l2_tunnel_disable(
7924                                 dev,
7925                                 l2_tunnel->l2_tunnel_type);
7926         }
7927
7928         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7929                 if (en)
7930                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7931                                 dev,
7932                                 l2_tunnel);
7933                 else
7934                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7935                                 dev,
7936                                 l2_tunnel);
7937         }
7938
7939         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7940                 if (en)
7941                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7942                                 dev,
7943                                 l2_tunnel->l2_tunnel_type);
7944                 else
7945                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7946                                 dev,
7947                                 l2_tunnel->l2_tunnel_type);
7948         }
7949
7950         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7951                 if (en)
7952                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7953                                 dev,
7954                                 l2_tunnel->l2_tunnel_type);
7955                 else
7956                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7957                                 dev,
7958                                 l2_tunnel->l2_tunnel_type);
7959         }
7960
7961         return ret;
7962 }
7963
7964 static int
7965 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7966                         uint16_t port)
7967 {
7968         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7969         IXGBE_WRITE_FLUSH(hw);
7970
7971         return 0;
7972 }
7973
7974 /* There's only one register for VxLAN UDP port.
7975  * So, we cannot add several ports. Will update it.
7976  */
7977 static int
7978 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7979                      uint16_t port)
7980 {
7981         if (port == 0) {
7982                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7983                 return -EINVAL;
7984         }
7985
7986         return ixgbe_update_vxlan_port(hw, port);
7987 }
7988
7989 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7990  * UDP port, it must have a value.
7991  * So, will reset it to the original value 0.
7992  */
7993 static int
7994 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7995                      uint16_t port)
7996 {
7997         uint16_t cur_port;
7998
7999         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8000
8001         if (cur_port != port) {
8002                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8003                 return -EINVAL;
8004         }
8005
8006         return ixgbe_update_vxlan_port(hw, 0);
8007 }
8008
8009 /* Add UDP tunneling port */
8010 static int
8011 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8012                               struct rte_eth_udp_tunnel *udp_tunnel)
8013 {
8014         int ret = 0;
8015         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8016
8017         if (hw->mac.type != ixgbe_mac_X550 &&
8018             hw->mac.type != ixgbe_mac_X550EM_x &&
8019             hw->mac.type != ixgbe_mac_X550EM_a) {
8020                 return -ENOTSUP;
8021         }
8022
8023         if (udp_tunnel == NULL)
8024                 return -EINVAL;
8025
8026         switch (udp_tunnel->prot_type) {
8027         case RTE_TUNNEL_TYPE_VXLAN:
8028                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8029                 break;
8030
8031         case RTE_TUNNEL_TYPE_GENEVE:
8032         case RTE_TUNNEL_TYPE_TEREDO:
8033                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8034                 ret = -EINVAL;
8035                 break;
8036
8037         default:
8038                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8039                 ret = -EINVAL;
8040                 break;
8041         }
8042
8043         return ret;
8044 }
8045
8046 /* Remove UDP tunneling port */
8047 static int
8048 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8049                               struct rte_eth_udp_tunnel *udp_tunnel)
8050 {
8051         int ret = 0;
8052         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8053
8054         if (hw->mac.type != ixgbe_mac_X550 &&
8055             hw->mac.type != ixgbe_mac_X550EM_x &&
8056             hw->mac.type != ixgbe_mac_X550EM_a) {
8057                 return -ENOTSUP;
8058         }
8059
8060         if (udp_tunnel == NULL)
8061                 return -EINVAL;
8062
8063         switch (udp_tunnel->prot_type) {
8064         case RTE_TUNNEL_TYPE_VXLAN:
8065                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8066                 break;
8067         case RTE_TUNNEL_TYPE_GENEVE:
8068         case RTE_TUNNEL_TYPE_TEREDO:
8069                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8070                 ret = -EINVAL;
8071                 break;
8072         default:
8073                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8074                 ret = -EINVAL;
8075                 break;
8076         }
8077
8078         return ret;
8079 }
8080
8081 static void
8082 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8083 {
8084         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8085
8086         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8087 }
8088
8089 static void
8090 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8091 {
8092         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8093
8094         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8095 }
8096
8097 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8098 {
8099         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8100         u32 in_msg = 0;
8101
8102         /* peek the message first */
8103         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8104
8105         /* PF reset VF event */
8106         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8107                 /* dummy mbx read to ack pf */
8108                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8109                         return;
8110                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8111                                               NULL);
8112         }
8113 }
8114
8115 static int
8116 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8117 {
8118         uint32_t eicr;
8119         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8120         struct ixgbe_interrupt *intr =
8121                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8122         ixgbevf_intr_disable(hw);
8123
8124         /* read-on-clear nic registers here */
8125         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8126         intr->flags = 0;
8127
8128         /* only one misc vector supported - mailbox */
8129         eicr &= IXGBE_VTEICR_MASK;
8130         if (eicr == IXGBE_MISC_VEC_ID)
8131                 intr->flags |= IXGBE_FLAG_MAILBOX;
8132
8133         return 0;
8134 }
8135
8136 static int
8137 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8138 {
8139         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8140         struct ixgbe_interrupt *intr =
8141                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8142
8143         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8144                 ixgbevf_mbx_process(dev);
8145                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8146         }
8147
8148         ixgbevf_intr_enable(hw);
8149
8150         return 0;
8151 }
8152
8153 static void
8154 ixgbevf_dev_interrupt_handler(void *param)
8155 {
8156         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8157
8158         ixgbevf_dev_interrupt_get_status(dev);
8159         ixgbevf_dev_interrupt_action(dev);
8160 }
8161
8162 /**
8163  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8164  *  @hw: pointer to hardware structure
8165  *
8166  *  Stops the transmit data path and waits for the HW to internally empty
8167  *  the Tx security block
8168  **/
8169 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8170 {
8171 #define IXGBE_MAX_SECTX_POLL 40
8172
8173         int i;
8174         int sectxreg;
8175
8176         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8177         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8178         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8179         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8180                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8181                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8182                         break;
8183                 /* Use interrupt-safe sleep just in case */
8184                 usec_delay(1000);
8185         }
8186
8187         /* For informational purposes only */
8188         if (i >= IXGBE_MAX_SECTX_POLL)
8189                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8190                          "path fully disabled.  Continuing with init.");
8191
8192         return IXGBE_SUCCESS;
8193 }
8194
8195 /**
8196  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8197  *  @hw: pointer to hardware structure
8198  *
8199  *  Enables the transmit data path.
8200  **/
8201 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8202 {
8203         uint32_t sectxreg;
8204
8205         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8206         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8207         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8208         IXGBE_WRITE_FLUSH(hw);
8209
8210         return IXGBE_SUCCESS;
8211 }
8212
8213 /* restore n-tuple filter */
8214 static inline void
8215 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8216 {
8217         struct ixgbe_filter_info *filter_info =
8218                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8219         struct ixgbe_5tuple_filter *node;
8220
8221         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8222                 ixgbe_inject_5tuple_filter(dev, node);
8223         }
8224 }
8225
8226 /* restore ethernet type filter */
8227 static inline void
8228 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8229 {
8230         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8231         struct ixgbe_filter_info *filter_info =
8232                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8233         int i;
8234
8235         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8236                 if (filter_info->ethertype_mask & (1 << i)) {
8237                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8238                                         filter_info->ethertype_filters[i].etqf);
8239                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8240                                         filter_info->ethertype_filters[i].etqs);
8241                         IXGBE_WRITE_FLUSH(hw);
8242                 }
8243         }
8244 }
8245
8246 /* restore SYN filter */
8247 static inline void
8248 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8249 {
8250         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8251         struct ixgbe_filter_info *filter_info =
8252                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8253         uint32_t synqf;
8254
8255         synqf = filter_info->syn_info;
8256
8257         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8258                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8259                 IXGBE_WRITE_FLUSH(hw);
8260         }
8261 }
8262
8263 /* restore L2 tunnel filter */
8264 static inline void
8265 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8266 {
8267         struct ixgbe_l2_tn_info *l2_tn_info =
8268                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8269         struct ixgbe_l2_tn_filter *node;
8270         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8271
8272         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8273                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8274                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8275                 l2_tn_conf.pool           = node->pool;
8276                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8277         }
8278 }
8279
8280 /* restore rss filter */
8281 static inline void
8282 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8283 {
8284         struct ixgbe_filter_info *filter_info =
8285                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8286
8287         if (filter_info->rss_info.num)
8288                 ixgbe_config_rss_filter(dev,
8289                         &filter_info->rss_info, TRUE);
8290 }
8291
8292 static int
8293 ixgbe_filter_restore(struct rte_eth_dev *dev)
8294 {
8295         ixgbe_ntuple_filter_restore(dev);
8296         ixgbe_ethertype_filter_restore(dev);
8297         ixgbe_syn_filter_restore(dev);
8298         ixgbe_fdir_filter_restore(dev);
8299         ixgbe_l2_tn_filter_restore(dev);
8300         ixgbe_rss_filter_restore(dev);
8301
8302         return 0;
8303 }
8304
8305 static void
8306 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8307 {
8308         struct ixgbe_l2_tn_info *l2_tn_info =
8309                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8310         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8311
8312         if (l2_tn_info->e_tag_en)
8313                 (void)ixgbe_e_tag_enable(hw);
8314
8315         if (l2_tn_info->e_tag_fwd_en)
8316                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8317
8318         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8319 }
8320
8321 /* remove all the n-tuple filters */
8322 void
8323 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8324 {
8325         struct ixgbe_filter_info *filter_info =
8326                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8327         struct ixgbe_5tuple_filter *p_5tuple;
8328
8329         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8330                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8331 }
8332
8333 /* remove all the ether type filters */
8334 void
8335 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8336 {
8337         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8338         struct ixgbe_filter_info *filter_info =
8339                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8340         int i;
8341
8342         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8343                 if (filter_info->ethertype_mask & (1 << i) &&
8344                     !filter_info->ethertype_filters[i].conf) {
8345                         (void)ixgbe_ethertype_filter_remove(filter_info,
8346                                                             (uint8_t)i);
8347                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8348                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8349                         IXGBE_WRITE_FLUSH(hw);
8350                 }
8351         }
8352 }
8353
8354 /* remove the SYN filter */
8355 void
8356 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8357 {
8358         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8359         struct ixgbe_filter_info *filter_info =
8360                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8361
8362         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8363                 filter_info->syn_info = 0;
8364
8365                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8366                 IXGBE_WRITE_FLUSH(hw);
8367         }
8368 }
8369
8370 /* remove all the L2 tunnel filters */
8371 int
8372 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8373 {
8374         struct ixgbe_l2_tn_info *l2_tn_info =
8375                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8376         struct ixgbe_l2_tn_filter *l2_tn_filter;
8377         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8378         int ret = 0;
8379
8380         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8381                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8382                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8383                 l2_tn_conf.pool           = l2_tn_filter->pool;
8384                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8385                 if (ret < 0)
8386                         return ret;
8387         }
8388
8389         return 0;
8390 }
8391
8392 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8393 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8394 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8395 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8396 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8397 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8398
8399 RTE_INIT(ixgbe_init_log);
8400 static void
8401 ixgbe_init_log(void)
8402 {
8403         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8404         if (ixgbe_logtype_init >= 0)
8405                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8406         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8407         if (ixgbe_logtype_driver >= 0)
8408                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8409 }