5ecf12928a3a58ac2878853006eac7a1a1f2fd11
[dpdk.git] / drivers / net / ixgbe / ixgbe_ethdev.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2010-2017 Intel Corporation
3  */
4
5 #include <sys/queue.h>
6 #include <stdio.h>
7 #include <errno.h>
8 #include <stdint.h>
9 #include <string.h>
10 #include <unistd.h>
11 #include <stdarg.h>
12 #include <inttypes.h>
13 #include <netinet/in.h>
14 #include <rte_byteorder.h>
15 #include <rte_common.h>
16 #include <rte_cycles.h>
17
18 #include <rte_interrupts.h>
19 #include <rte_log.h>
20 #include <rte_debug.h>
21 #include <rte_pci.h>
22 #include <rte_bus_pci.h>
23 #include <rte_branch_prediction.h>
24 #include <rte_memory.h>
25 #include <rte_eal.h>
26 #include <rte_alarm.h>
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_ethdev_pci.h>
30 #include <rte_malloc.h>
31 #include <rte_random.h>
32 #include <rte_dev.h>
33 #include <rte_hash_crc.h>
34 #ifdef RTE_LIBRTE_SECURITY
35 #include <rte_security_driver.h>
36 #endif
37
38 #include "ixgbe_logs.h"
39 #include "base/ixgbe_api.h"
40 #include "base/ixgbe_vf.h"
41 #include "base/ixgbe_common.h"
42 #include "ixgbe_ethdev.h"
43 #include "ixgbe_bypass.h"
44 #include "ixgbe_rxtx.h"
45 #include "base/ixgbe_type.h"
46 #include "base/ixgbe_phy.h"
47 #include "ixgbe_regs.h"
48
49 /*
50  * High threshold controlling when to start sending XOFF frames. Must be at
51  * least 8 bytes less than receive packet buffer size. This value is in units
52  * of 1024 bytes.
53  */
54 #define IXGBE_FC_HI    0x80
55
56 /*
57  * Low threshold controlling when to start sending XON frames. This value is
58  * in units of 1024 bytes.
59  */
60 #define IXGBE_FC_LO    0x40
61
62 /* Timer value included in XOFF frames. */
63 #define IXGBE_FC_PAUSE 0x680
64
65 /*Default value of Max Rx Queue*/
66 #define IXGBE_MAX_RX_QUEUE_NUM 128
67
68 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
69 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
70 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
71
72 #define IXGBE_MMW_SIZE_DEFAULT        0x4
73 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
74 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
75
76 /*
77  *  Default values for RX/TX configuration
78  */
79 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
80 #define IXGBE_DEFAULT_RX_PTHRESH      8
81 #define IXGBE_DEFAULT_RX_HTHRESH      8
82 #define IXGBE_DEFAULT_RX_WTHRESH      0
83
84 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
85 #define IXGBE_DEFAULT_TX_PTHRESH      32
86 #define IXGBE_DEFAULT_TX_HTHRESH      0
87 #define IXGBE_DEFAULT_TX_WTHRESH      0
88 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
89
90 /* Bit shift and mask */
91 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
92 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
93 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
94 #define IXGBE_8_BIT_MASK   UINT8_MAX
95
96 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
97
98 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
99
100 /* Additional timesync values. */
101 #define NSEC_PER_SEC             1000000000L
102 #define IXGBE_INCVAL_10GB        0x66666666
103 #define IXGBE_INCVAL_1GB         0x40000000
104 #define IXGBE_INCVAL_100         0x50000000
105 #define IXGBE_INCVAL_SHIFT_10GB  28
106 #define IXGBE_INCVAL_SHIFT_1GB   24
107 #define IXGBE_INCVAL_SHIFT_100   21
108 #define IXGBE_INCVAL_SHIFT_82599 7
109 #define IXGBE_INCPER_SHIFT_82599 24
110
111 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
112
113 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
114 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
115 #define IXGBE_ETAG_ETYPE                       0x00005084
116 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
117 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
118 #define IXGBE_RAH_ADTYPE                       0x40000000
119 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
120 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
121 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
122 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
123 #define IXGBE_QDE_STRIP_TAG                    0x00000004
124 #define IXGBE_VTEICR_MASK                      0x07
125
126 #define IXGBE_EXVET_VET_EXT_SHIFT              16
127 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
128
129 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
130 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
131 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
132 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
133 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
134 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
135 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
136 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
137 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
139 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
140 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
142 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
143 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
144 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
145 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
146 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
147 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
148                                 int wait_to_complete);
149 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
150                                 struct rte_eth_stats *stats);
151 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
152                                 struct rte_eth_xstat *xstats, unsigned n);
153 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
154                                   struct rte_eth_xstat *xstats, unsigned n);
155 static int
156 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
157                 uint64_t *values, unsigned int n);
158 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
159 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
160 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
161         struct rte_eth_xstat_name *xstats_names,
162         unsigned int size);
163 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
164         struct rte_eth_xstat_name *xstats_names, unsigned limit);
165 static int ixgbe_dev_xstats_get_names_by_id(
166         struct rte_eth_dev *dev,
167         struct rte_eth_xstat_name *xstats_names,
168         const uint64_t *ids,
169         unsigned int limit);
170 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
171                                              uint16_t queue_id,
172                                              uint8_t stat_idx,
173                                              uint8_t is_rx);
174 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
175                                  size_t fw_size);
176 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
177                                struct rte_eth_dev_info *dev_info);
178 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
179 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
180                                  struct rte_eth_dev_info *dev_info);
181 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
182
183 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
184                 uint16_t vlan_id, int on);
185 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
186                                enum rte_vlan_type vlan_type,
187                                uint16_t tpid_id);
188 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
189                 uint16_t queue, bool on);
190 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
191                 int on);
192 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
193 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
194 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
195 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
196 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
197
198 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
199 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
200 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
201                                struct rte_eth_fc_conf *fc_conf);
202 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
203                                struct rte_eth_fc_conf *fc_conf);
204 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
205                 struct rte_eth_pfc_conf *pfc_conf);
206 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
207                         struct rte_eth_rss_reta_entry64 *reta_conf,
208                         uint16_t reta_size);
209 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
210                         struct rte_eth_rss_reta_entry64 *reta_conf,
211                         uint16_t reta_size);
212 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
213 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
214 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
215 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
216 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
217 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
218                                       struct rte_intr_handle *handle);
219 static void ixgbe_dev_interrupt_handler(void *param);
220 static void ixgbe_dev_interrupt_delayed_handler(void *param);
221 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
222                          uint32_t index, uint32_t pool);
223 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
224 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
225                                            struct ether_addr *mac_addr);
226 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
227 static bool is_device_supported(struct rte_eth_dev *dev,
228                                 struct rte_pci_driver *drv);
229
230 /* For Virtual Function support */
231 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
232 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
233 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
234 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
235 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
236                                    int wait_to_complete);
237 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
238 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
239 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
240 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
241 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
242 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
243                 struct rte_eth_stats *stats);
244 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
245 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
246                 uint16_t vlan_id, int on);
247 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
248                 uint16_t queue, int on);
249 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
250 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
251 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
252                                             uint16_t queue_id);
253 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
254                                              uint16_t queue_id);
255 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
256                                  uint8_t queue, uint8_t msix_vector);
257 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
258 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
259 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
260
261 /* For Eth VMDQ APIs support */
262 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
263                 ether_addr * mac_addr, uint8_t on);
264 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
265 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
266                 struct rte_eth_mirror_conf *mirror_conf,
267                 uint8_t rule_id, uint8_t on);
268 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
269                 uint8_t rule_id);
270 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
271                                           uint16_t queue_id);
272 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
273                                            uint16_t queue_id);
274 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
275                                uint8_t queue, uint8_t msix_vector);
276 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
277
278 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
279                                 struct ether_addr *mac_addr,
280                                 uint32_t index, uint32_t pool);
281 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
282 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
283                                              struct ether_addr *mac_addr);
284 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
285                         struct rte_eth_syn_filter *filter);
286 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
287                         enum rte_filter_op filter_op,
288                         void *arg);
289 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
290                         struct ixgbe_5tuple_filter *filter);
291 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
292                         struct ixgbe_5tuple_filter *filter);
293 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
294                                 enum rte_filter_op filter_op,
295                                 void *arg);
296 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
297                         struct rte_eth_ntuple_filter *filter);
298 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
299                                 enum rte_filter_op filter_op,
300                                 void *arg);
301 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
302                         struct rte_eth_ethertype_filter *filter);
303 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
304                      enum rte_filter_type filter_type,
305                      enum rte_filter_op filter_op,
306                      void *arg);
307 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
308
309 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
310                                       struct ether_addr *mc_addr_set,
311                                       uint32_t nb_mc_addr);
312 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
313                                    struct rte_eth_dcb_info *dcb_info);
314
315 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
316 static int ixgbe_get_regs(struct rte_eth_dev *dev,
317                             struct rte_dev_reg_info *regs);
318 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
319 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
320                                 struct rte_dev_eeprom_info *eeprom);
321 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
322                                 struct rte_dev_eeprom_info *eeprom);
323
324 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
325                                  struct rte_eth_dev_module_info *modinfo);
326 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
327                                    struct rte_dev_eeprom_info *info);
328
329 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
330 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
331                                 struct rte_dev_reg_info *regs);
332
333 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
334 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
335 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
336                                             struct timespec *timestamp,
337                                             uint32_t flags);
338 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
339                                             struct timespec *timestamp);
340 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
341 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
342                                    struct timespec *timestamp);
343 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
344                                    const struct timespec *timestamp);
345 static void ixgbevf_dev_interrupt_handler(void *param);
346
347 static int ixgbe_dev_l2_tunnel_eth_type_conf
348         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
349 static int ixgbe_dev_l2_tunnel_offload_set
350         (struct rte_eth_dev *dev,
351          struct rte_eth_l2_tunnel_conf *l2_tunnel,
352          uint32_t mask,
353          uint8_t en);
354 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
355                                              enum rte_filter_op filter_op,
356                                              void *arg);
357
358 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
359                                          struct rte_eth_udp_tunnel *udp_tunnel);
360 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
361                                          struct rte_eth_udp_tunnel *udp_tunnel);
362 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
363 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
364
365 /*
366  * Define VF Stats MACRO for Non "cleared on read" register
367  */
368 #define UPDATE_VF_STAT(reg, last, cur)                          \
369 {                                                               \
370         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
371         cur += (latest - last) & UINT_MAX;                      \
372         last = latest;                                          \
373 }
374
375 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
376 {                                                                \
377         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
378         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
379         u64 latest = ((new_msb << 32) | new_lsb);                \
380         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
381         last = latest;                                           \
382 }
383
384 #define IXGBE_SET_HWSTRIP(h, q) do {\
385                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
386                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
387                 (h)->bitmap[idx] |= 1 << bit;\
388         } while (0)
389
390 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
391                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
392                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
393                 (h)->bitmap[idx] &= ~(1 << bit);\
394         } while (0)
395
396 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
397                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
398                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
399                 (r) = (h)->bitmap[idx] >> bit & 1;\
400         } while (0)
401
402 int ixgbe_logtype_init;
403 int ixgbe_logtype_driver;
404
405 /*
406  * The set of PCI devices this driver supports
407  */
408 static const struct rte_pci_id pci_id_ixgbe_map[] = {
409         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
410         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
411         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
457 #ifdef RTE_LIBRTE_IXGBE_BYPASS
458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
459 #endif
460         { .vendor_id = 0, /* sentinel */ },
461 };
462
463 /*
464  * The set of PCI devices this driver supports (for 82599 VF)
465  */
466 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
477         { .vendor_id = 0, /* sentinel */ },
478 };
479
480 static const struct rte_eth_desc_lim rx_desc_lim = {
481         .nb_max = IXGBE_MAX_RING_DESC,
482         .nb_min = IXGBE_MIN_RING_DESC,
483         .nb_align = IXGBE_RXD_ALIGN,
484 };
485
486 static const struct rte_eth_desc_lim tx_desc_lim = {
487         .nb_max = IXGBE_MAX_RING_DESC,
488         .nb_min = IXGBE_MIN_RING_DESC,
489         .nb_align = IXGBE_TXD_ALIGN,
490         .nb_seg_max = IXGBE_TX_MAX_SEG,
491         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
492 };
493
494 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
495         .dev_configure        = ixgbe_dev_configure,
496         .dev_start            = ixgbe_dev_start,
497         .dev_stop             = ixgbe_dev_stop,
498         .dev_set_link_up    = ixgbe_dev_set_link_up,
499         .dev_set_link_down  = ixgbe_dev_set_link_down,
500         .dev_close            = ixgbe_dev_close,
501         .dev_reset            = ixgbe_dev_reset,
502         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
503         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
504         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
505         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
506         .link_update          = ixgbe_dev_link_update,
507         .stats_get            = ixgbe_dev_stats_get,
508         .xstats_get           = ixgbe_dev_xstats_get,
509         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
510         .stats_reset          = ixgbe_dev_stats_reset,
511         .xstats_reset         = ixgbe_dev_xstats_reset,
512         .xstats_get_names     = ixgbe_dev_xstats_get_names,
513         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
514         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
515         .fw_version_get       = ixgbe_fw_version_get,
516         .dev_infos_get        = ixgbe_dev_info_get,
517         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
518         .mtu_set              = ixgbe_dev_mtu_set,
519         .vlan_filter_set      = ixgbe_vlan_filter_set,
520         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
521         .vlan_offload_set     = ixgbe_vlan_offload_set,
522         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
523         .rx_queue_start       = ixgbe_dev_rx_queue_start,
524         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
525         .tx_queue_start       = ixgbe_dev_tx_queue_start,
526         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
527         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
528         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
529         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
530         .rx_queue_release     = ixgbe_dev_rx_queue_release,
531         .rx_queue_count       = ixgbe_dev_rx_queue_count,
532         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
533         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
534         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
535         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
536         .tx_queue_release     = ixgbe_dev_tx_queue_release,
537         .dev_led_on           = ixgbe_dev_led_on,
538         .dev_led_off          = ixgbe_dev_led_off,
539         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
540         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
541         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
542         .mac_addr_add         = ixgbe_add_rar,
543         .mac_addr_remove      = ixgbe_remove_rar,
544         .mac_addr_set         = ixgbe_set_default_mac_addr,
545         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
546         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
547         .mirror_rule_set      = ixgbe_mirror_rule_set,
548         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
549         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
550         .reta_update          = ixgbe_dev_rss_reta_update,
551         .reta_query           = ixgbe_dev_rss_reta_query,
552         .rss_hash_update      = ixgbe_dev_rss_hash_update,
553         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
554         .filter_ctrl          = ixgbe_dev_filter_ctrl,
555         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
556         .rxq_info_get         = ixgbe_rxq_info_get,
557         .txq_info_get         = ixgbe_txq_info_get,
558         .timesync_enable      = ixgbe_timesync_enable,
559         .timesync_disable     = ixgbe_timesync_disable,
560         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
561         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
562         .get_reg              = ixgbe_get_regs,
563         .get_eeprom_length    = ixgbe_get_eeprom_length,
564         .get_eeprom           = ixgbe_get_eeprom,
565         .set_eeprom           = ixgbe_set_eeprom,
566         .get_module_info      = ixgbe_get_module_info,
567         .get_module_eeprom    = ixgbe_get_module_eeprom,
568         .get_dcb_info         = ixgbe_dev_get_dcb_info,
569         .timesync_adjust_time = ixgbe_timesync_adjust_time,
570         .timesync_read_time   = ixgbe_timesync_read_time,
571         .timesync_write_time  = ixgbe_timesync_write_time,
572         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
573         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
574         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
575         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
576         .tm_ops_get           = ixgbe_tm_ops_get,
577 };
578
579 /*
580  * dev_ops for virtual function, bare necessities for basic vf
581  * operation have been implemented
582  */
583 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
584         .dev_configure        = ixgbevf_dev_configure,
585         .dev_start            = ixgbevf_dev_start,
586         .dev_stop             = ixgbevf_dev_stop,
587         .link_update          = ixgbevf_dev_link_update,
588         .stats_get            = ixgbevf_dev_stats_get,
589         .xstats_get           = ixgbevf_dev_xstats_get,
590         .stats_reset          = ixgbevf_dev_stats_reset,
591         .xstats_reset         = ixgbevf_dev_stats_reset,
592         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
593         .dev_close            = ixgbevf_dev_close,
594         .dev_reset            = ixgbevf_dev_reset,
595         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
596         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
597         .dev_infos_get        = ixgbevf_dev_info_get,
598         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
599         .mtu_set              = ixgbevf_dev_set_mtu,
600         .vlan_filter_set      = ixgbevf_vlan_filter_set,
601         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
602         .vlan_offload_set     = ixgbevf_vlan_offload_set,
603         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
604         .rx_queue_release     = ixgbe_dev_rx_queue_release,
605         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
606         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
607         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
608         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
609         .tx_queue_release     = ixgbe_dev_tx_queue_release,
610         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
611         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
612         .mac_addr_add         = ixgbevf_add_mac_addr,
613         .mac_addr_remove      = ixgbevf_remove_mac_addr,
614         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
615         .rxq_info_get         = ixgbe_rxq_info_get,
616         .txq_info_get         = ixgbe_txq_info_get,
617         .mac_addr_set         = ixgbevf_set_default_mac_addr,
618         .get_reg              = ixgbevf_get_regs,
619         .reta_update          = ixgbe_dev_rss_reta_update,
620         .reta_query           = ixgbe_dev_rss_reta_query,
621         .rss_hash_update      = ixgbe_dev_rss_hash_update,
622         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
623 };
624
625 /* store statistics names and its offset in stats structure */
626 struct rte_ixgbe_xstats_name_off {
627         char name[RTE_ETH_XSTATS_NAME_SIZE];
628         unsigned offset;
629 };
630
631 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
632         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
633         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
634         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
635         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
636         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
637         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
638         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
639         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
640         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
641         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
642         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
643         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
644         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
645         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
646         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
647                 prc1023)},
648         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
649                 prc1522)},
650         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
651         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
652         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
653         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
654         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
655         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
656         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
657         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
658         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
659         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
660         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
661         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
662         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
663         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
664         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
665         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
666         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
667                 ptc1023)},
668         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
669                 ptc1522)},
670         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
671         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
672         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
673         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
674
675         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
676                 fdirustat_add)},
677         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
678                 fdirustat_remove)},
679         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
680                 fdirfstat_fadd)},
681         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
682                 fdirfstat_fremove)},
683         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
684                 fdirmatch)},
685         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
686                 fdirmiss)},
687
688         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
689         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
690         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
691                 fclast)},
692         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
693         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
694         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
695         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
696         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
697                 fcoe_noddp)},
698         {"rx_fcoe_no_direct_data_placement_ext_buff",
699                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
700
701         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
702                 lxontxc)},
703         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
704                 lxonrxc)},
705         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
706                 lxofftxc)},
707         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
708                 lxoffrxc)},
709         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
710 };
711
712 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
713                            sizeof(rte_ixgbe_stats_strings[0]))
714
715 /* MACsec statistics */
716 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
717         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
718                 out_pkts_untagged)},
719         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
720                 out_pkts_encrypted)},
721         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
722                 out_pkts_protected)},
723         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
724                 out_octets_encrypted)},
725         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
726                 out_octets_protected)},
727         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
728                 in_pkts_untagged)},
729         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
730                 in_pkts_badtag)},
731         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
732                 in_pkts_nosci)},
733         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
734                 in_pkts_unknownsci)},
735         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
736                 in_octets_decrypted)},
737         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
738                 in_octets_validated)},
739         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
740                 in_pkts_unchecked)},
741         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
742                 in_pkts_delayed)},
743         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
744                 in_pkts_late)},
745         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
746                 in_pkts_ok)},
747         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
748                 in_pkts_invalid)},
749         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
750                 in_pkts_notvalid)},
751         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
752                 in_pkts_unusedsa)},
753         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
754                 in_pkts_notusingsa)},
755 };
756
757 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
758                            sizeof(rte_ixgbe_macsec_strings[0]))
759
760 /* Per-queue statistics */
761 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
762         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
763         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
764         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
765         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
766 };
767
768 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
769                            sizeof(rte_ixgbe_rxq_strings[0]))
770 #define IXGBE_NB_RXQ_PRIO_VALUES 8
771
772 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
773         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
774         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
775         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
776                 pxon2offc)},
777 };
778
779 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
780                            sizeof(rte_ixgbe_txq_strings[0]))
781 #define IXGBE_NB_TXQ_PRIO_VALUES 8
782
783 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
784         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
785 };
786
787 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
788                 sizeof(rte_ixgbevf_stats_strings[0]))
789
790 /*
791  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
792  */
793 static inline int
794 ixgbe_is_sfp(struct ixgbe_hw *hw)
795 {
796         switch (hw->phy.type) {
797         case ixgbe_phy_sfp_avago:
798         case ixgbe_phy_sfp_ftl:
799         case ixgbe_phy_sfp_intel:
800         case ixgbe_phy_sfp_unknown:
801         case ixgbe_phy_sfp_passive_tyco:
802         case ixgbe_phy_sfp_passive_unknown:
803                 return 1;
804         default:
805                 return 0;
806         }
807 }
808
809 static inline int32_t
810 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
811 {
812         uint32_t ctrl_ext;
813         int32_t status;
814
815         status = ixgbe_reset_hw(hw);
816
817         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
818         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
819         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
820         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
821         IXGBE_WRITE_FLUSH(hw);
822
823         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
824                 status = IXGBE_SUCCESS;
825         return status;
826 }
827
828 static inline void
829 ixgbe_enable_intr(struct rte_eth_dev *dev)
830 {
831         struct ixgbe_interrupt *intr =
832                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
833         struct ixgbe_hw *hw =
834                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
835
836         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
837         IXGBE_WRITE_FLUSH(hw);
838 }
839
840 /*
841  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
842  */
843 static void
844 ixgbe_disable_intr(struct ixgbe_hw *hw)
845 {
846         PMD_INIT_FUNC_TRACE();
847
848         if (hw->mac.type == ixgbe_mac_82598EB) {
849                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
850         } else {
851                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
852                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
853                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
854         }
855         IXGBE_WRITE_FLUSH(hw);
856 }
857
858 /*
859  * This function resets queue statistics mapping registers.
860  * From Niantic datasheet, Initialization of Statistics section:
861  * "...if software requires the queue counters, the RQSMR and TQSM registers
862  * must be re-programmed following a device reset.
863  */
864 static void
865 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
866 {
867         uint32_t i;
868
869         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
870                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
871                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
872         }
873 }
874
875
876 static int
877 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
878                                   uint16_t queue_id,
879                                   uint8_t stat_idx,
880                                   uint8_t is_rx)
881 {
882 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
883 #define NB_QMAP_FIELDS_PER_QSM_REG 4
884 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
885
886         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
887         struct ixgbe_stat_mapping_registers *stat_mappings =
888                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
889         uint32_t qsmr_mask = 0;
890         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
891         uint32_t q_map;
892         uint8_t n, offset;
893
894         if ((hw->mac.type != ixgbe_mac_82599EB) &&
895                 (hw->mac.type != ixgbe_mac_X540) &&
896                 (hw->mac.type != ixgbe_mac_X550) &&
897                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
898                 (hw->mac.type != ixgbe_mac_X550EM_a))
899                 return -ENOSYS;
900
901         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
902                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
903                      queue_id, stat_idx);
904
905         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
906         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
907                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
908                 return -EIO;
909         }
910         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
911
912         /* Now clear any previous stat_idx set */
913         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
914         if (!is_rx)
915                 stat_mappings->tqsm[n] &= ~clearing_mask;
916         else
917                 stat_mappings->rqsmr[n] &= ~clearing_mask;
918
919         q_map = (uint32_t)stat_idx;
920         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
921         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
922         if (!is_rx)
923                 stat_mappings->tqsm[n] |= qsmr_mask;
924         else
925                 stat_mappings->rqsmr[n] |= qsmr_mask;
926
927         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
928                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
929                      queue_id, stat_idx);
930         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
931                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
932
933         /* Now write the mapping in the appropriate register */
934         if (is_rx) {
935                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
936                              stat_mappings->rqsmr[n], n);
937                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
938         } else {
939                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
940                              stat_mappings->tqsm[n], n);
941                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
942         }
943         return 0;
944 }
945
946 static void
947 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
948 {
949         struct ixgbe_stat_mapping_registers *stat_mappings =
950                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
951         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
952         int i;
953
954         /* write whatever was in stat mapping table to the NIC */
955         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
956                 /* rx */
957                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
958
959                 /* tx */
960                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
961         }
962 }
963
964 static void
965 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
966 {
967         uint8_t i;
968         struct ixgbe_dcb_tc_config *tc;
969         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
970
971         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
972         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
973         for (i = 0; i < dcb_max_tc; i++) {
974                 tc = &dcb_config->tc_config[i];
975                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
976                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
977                                  (uint8_t)(100/dcb_max_tc + (i & 1));
978                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
979                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
980                                  (uint8_t)(100/dcb_max_tc + (i & 1));
981                 tc->pfc = ixgbe_dcb_pfc_disabled;
982         }
983
984         /* Initialize default user to priority mapping, UPx->TC0 */
985         tc = &dcb_config->tc_config[0];
986         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
987         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
988         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
989                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
990                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
991         }
992         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
993         dcb_config->pfc_mode_enable = false;
994         dcb_config->vt_mode = true;
995         dcb_config->round_robin_enable = false;
996         /* support all DCB capabilities in 82599 */
997         dcb_config->support.capabilities = 0xFF;
998
999         /*we only support 4 Tcs for X540, X550 */
1000         if (hw->mac.type == ixgbe_mac_X540 ||
1001                 hw->mac.type == ixgbe_mac_X550 ||
1002                 hw->mac.type == ixgbe_mac_X550EM_x ||
1003                 hw->mac.type == ixgbe_mac_X550EM_a) {
1004                 dcb_config->num_tcs.pg_tcs = 4;
1005                 dcb_config->num_tcs.pfc_tcs = 4;
1006         }
1007 }
1008
1009 /*
1010  * Ensure that all locks are released before first NVM or PHY access
1011  */
1012 static void
1013 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1014 {
1015         uint16_t mask;
1016
1017         /*
1018          * Phy lock should not fail in this early stage. If this is the case,
1019          * it is due to an improper exit of the application.
1020          * So force the release of the faulty lock. Release of common lock
1021          * is done automatically by swfw_sync function.
1022          */
1023         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1024         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1025                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1026         }
1027         ixgbe_release_swfw_semaphore(hw, mask);
1028
1029         /*
1030          * These ones are more tricky since they are common to all ports; but
1031          * swfw_sync retries last long enough (1s) to be almost sure that if
1032          * lock can not be taken it is due to an improper lock of the
1033          * semaphore.
1034          */
1035         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1036         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1037                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1038         }
1039         ixgbe_release_swfw_semaphore(hw, mask);
1040 }
1041
1042 /*
1043  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1044  * It returns 0 on success.
1045  */
1046 static int
1047 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1048 {
1049         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1050         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1051         struct ixgbe_hw *hw =
1052                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1053         struct ixgbe_vfta *shadow_vfta =
1054                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1055         struct ixgbe_hwstrip *hwstrip =
1056                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1057         struct ixgbe_dcb_config *dcb_config =
1058                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1059         struct ixgbe_filter_info *filter_info =
1060                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1061         struct ixgbe_bw_conf *bw_conf =
1062                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1063         uint32_t ctrl_ext;
1064         uint16_t csum;
1065         int diag, i;
1066
1067         PMD_INIT_FUNC_TRACE();
1068
1069         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1070         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1071         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1072         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1073
1074         /*
1075          * For secondary processes, we don't initialise any further as primary
1076          * has already done this work. Only check we don't need a different
1077          * RX and TX function.
1078          */
1079         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1080                 struct ixgbe_tx_queue *txq;
1081                 /* TX queue function in primary, set by last queue initialized
1082                  * Tx queue may not initialized by primary process
1083                  */
1084                 if (eth_dev->data->tx_queues) {
1085                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1086                         ixgbe_set_tx_function(eth_dev, txq);
1087                 } else {
1088                         /* Use default TX function if we get here */
1089                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1090                                      "Using default TX function.");
1091                 }
1092
1093                 ixgbe_set_rx_function(eth_dev);
1094
1095                 return 0;
1096         }
1097
1098         rte_eth_copy_pci_info(eth_dev, pci_dev);
1099
1100         /* Vendor and Device ID need to be set before init of shared code */
1101         hw->device_id = pci_dev->id.device_id;
1102         hw->vendor_id = pci_dev->id.vendor_id;
1103         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1104         hw->allow_unsupported_sfp = 1;
1105
1106         /* Initialize the shared code (base driver) */
1107 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1108         diag = ixgbe_bypass_init_shared_code(hw);
1109 #else
1110         diag = ixgbe_init_shared_code(hw);
1111 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1112
1113         if (diag != IXGBE_SUCCESS) {
1114                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1115                 return -EIO;
1116         }
1117
1118         /* pick up the PCI bus settings for reporting later */
1119         ixgbe_get_bus_info(hw);
1120
1121         /* Unlock any pending hardware semaphore */
1122         ixgbe_swfw_lock_reset(hw);
1123
1124 #ifdef RTE_LIBRTE_SECURITY
1125         /* Initialize security_ctx only for primary process*/
1126         if (ixgbe_ipsec_ctx_create(eth_dev))
1127                 return -ENOMEM;
1128 #endif
1129
1130         /* Initialize DCB configuration*/
1131         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1132         ixgbe_dcb_init(hw, dcb_config);
1133         /* Get Hardware Flow Control setting */
1134         hw->fc.requested_mode = ixgbe_fc_full;
1135         hw->fc.current_mode = ixgbe_fc_full;
1136         hw->fc.pause_time = IXGBE_FC_PAUSE;
1137         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1138                 hw->fc.low_water[i] = IXGBE_FC_LO;
1139                 hw->fc.high_water[i] = IXGBE_FC_HI;
1140         }
1141         hw->fc.send_xon = 1;
1142
1143         /* Make sure we have a good EEPROM before we read from it */
1144         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1145         if (diag != IXGBE_SUCCESS) {
1146                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1147                 return -EIO;
1148         }
1149
1150 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1151         diag = ixgbe_bypass_init_hw(hw);
1152 #else
1153         diag = ixgbe_init_hw(hw);
1154 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1155
1156         /*
1157          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1158          * is called too soon after the kernel driver unbinding/binding occurs.
1159          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1160          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1161          * also called. See ixgbe_identify_phy_82599(). The reason for the
1162          * failure is not known, and only occuts when virtualisation features
1163          * are disabled in the bios. A delay of 100ms  was found to be enough by
1164          * trial-and-error, and is doubled to be safe.
1165          */
1166         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1167                 rte_delay_ms(200);
1168                 diag = ixgbe_init_hw(hw);
1169         }
1170
1171         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1172                 diag = IXGBE_SUCCESS;
1173
1174         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1175                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1176                              "LOM.  Please be aware there may be issues associated "
1177                              "with your hardware.");
1178                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1179                              "please contact your Intel or hardware representative "
1180                              "who provided you with this hardware.");
1181         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1182                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1183         if (diag) {
1184                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1185                 return -EIO;
1186         }
1187
1188         /* Reset the hw statistics */
1189         ixgbe_dev_stats_reset(eth_dev);
1190
1191         /* disable interrupt */
1192         ixgbe_disable_intr(hw);
1193
1194         /* reset mappings for queue statistics hw counters*/
1195         ixgbe_reset_qstat_mappings(hw);
1196
1197         /* Allocate memory for storing MAC addresses */
1198         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1199                                                hw->mac.num_rar_entries, 0);
1200         if (eth_dev->data->mac_addrs == NULL) {
1201                 PMD_INIT_LOG(ERR,
1202                              "Failed to allocate %u bytes needed to store "
1203                              "MAC addresses",
1204                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1205                 return -ENOMEM;
1206         }
1207         /* Copy the permanent MAC address */
1208         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1209                         &eth_dev->data->mac_addrs[0]);
1210
1211         /* Allocate memory for storing hash filter MAC addresses */
1212         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1213                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1214         if (eth_dev->data->hash_mac_addrs == NULL) {
1215                 PMD_INIT_LOG(ERR,
1216                              "Failed to allocate %d bytes needed to store MAC addresses",
1217                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1218                 return -ENOMEM;
1219         }
1220
1221         /* initialize the vfta */
1222         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1223
1224         /* initialize the hw strip bitmap*/
1225         memset(hwstrip, 0, sizeof(*hwstrip));
1226
1227         /* initialize PF if max_vfs not zero */
1228         ixgbe_pf_host_init(eth_dev);
1229
1230         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1231         /* let hardware know driver is loaded */
1232         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1233         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1234         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1235         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1236         IXGBE_WRITE_FLUSH(hw);
1237
1238         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1239                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1240                              (int) hw->mac.type, (int) hw->phy.type,
1241                              (int) hw->phy.sfp_type);
1242         else
1243                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1244                              (int) hw->mac.type, (int) hw->phy.type);
1245
1246         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1247                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1248                      pci_dev->id.device_id);
1249
1250         rte_intr_callback_register(intr_handle,
1251                                    ixgbe_dev_interrupt_handler, eth_dev);
1252
1253         /* enable uio/vfio intr/eventfd mapping */
1254         rte_intr_enable(intr_handle);
1255
1256         /* enable support intr */
1257         ixgbe_enable_intr(eth_dev);
1258
1259         /* initialize filter info */
1260         memset(filter_info, 0,
1261                sizeof(struct ixgbe_filter_info));
1262
1263         /* initialize 5tuple filter list */
1264         TAILQ_INIT(&filter_info->fivetuple_list);
1265
1266         /* initialize flow director filter list & hash */
1267         ixgbe_fdir_filter_init(eth_dev);
1268
1269         /* initialize l2 tunnel filter list & hash */
1270         ixgbe_l2_tn_filter_init(eth_dev);
1271
1272         /* initialize flow filter lists */
1273         ixgbe_filterlist_init();
1274
1275         /* initialize bandwidth configuration info */
1276         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1277
1278         /* initialize Traffic Manager configuration */
1279         ixgbe_tm_conf_init(eth_dev);
1280
1281         return 0;
1282 }
1283
1284 static int
1285 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1286 {
1287         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1288         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1289         struct ixgbe_hw *hw;
1290         int retries = 0;
1291         int ret;
1292
1293         PMD_INIT_FUNC_TRACE();
1294
1295         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1296                 return -EPERM;
1297
1298         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1299
1300         if (hw->adapter_stopped == 0)
1301                 ixgbe_dev_close(eth_dev);
1302
1303         eth_dev->dev_ops = NULL;
1304         eth_dev->rx_pkt_burst = NULL;
1305         eth_dev->tx_pkt_burst = NULL;
1306
1307         /* Unlock any pending hardware semaphore */
1308         ixgbe_swfw_lock_reset(hw);
1309
1310         /* disable uio intr before callback unregister */
1311         rte_intr_disable(intr_handle);
1312
1313         do {
1314                 ret = rte_intr_callback_unregister(intr_handle,
1315                                 ixgbe_dev_interrupt_handler, eth_dev);
1316                 if (ret >= 0) {
1317                         break;
1318                 } else if (ret != -EAGAIN) {
1319                         PMD_INIT_LOG(ERR,
1320                                 "intr callback unregister failed: %d",
1321                                 ret);
1322                         return ret;
1323                 }
1324                 rte_delay_ms(100);
1325         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1326
1327         /* uninitialize PF if max_vfs not zero */
1328         ixgbe_pf_host_uninit(eth_dev);
1329
1330         rte_free(eth_dev->data->mac_addrs);
1331         eth_dev->data->mac_addrs = NULL;
1332
1333         rte_free(eth_dev->data->hash_mac_addrs);
1334         eth_dev->data->hash_mac_addrs = NULL;
1335
1336         /* remove all the fdir filters & hash */
1337         ixgbe_fdir_filter_uninit(eth_dev);
1338
1339         /* remove all the L2 tunnel filters & hash */
1340         ixgbe_l2_tn_filter_uninit(eth_dev);
1341
1342         /* Remove all ntuple filters of the device */
1343         ixgbe_ntuple_filter_uninit(eth_dev);
1344
1345         /* clear all the filters list */
1346         ixgbe_filterlist_flush();
1347
1348         /* Remove all Traffic Manager configuration */
1349         ixgbe_tm_conf_uninit(eth_dev);
1350
1351 #ifdef RTE_LIBRTE_SECURITY
1352         rte_free(eth_dev->security_ctx);
1353 #endif
1354
1355         return 0;
1356 }
1357
1358 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1359 {
1360         struct ixgbe_filter_info *filter_info =
1361                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1362         struct ixgbe_5tuple_filter *p_5tuple;
1363
1364         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1365                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1366                              p_5tuple,
1367                              entries);
1368                 rte_free(p_5tuple);
1369         }
1370         memset(filter_info->fivetuple_mask, 0,
1371                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1372
1373         return 0;
1374 }
1375
1376 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1377 {
1378         struct ixgbe_hw_fdir_info *fdir_info =
1379                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1380         struct ixgbe_fdir_filter *fdir_filter;
1381
1382                 if (fdir_info->hash_map)
1383                 rte_free(fdir_info->hash_map);
1384         if (fdir_info->hash_handle)
1385                 rte_hash_free(fdir_info->hash_handle);
1386
1387         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1388                 TAILQ_REMOVE(&fdir_info->fdir_list,
1389                              fdir_filter,
1390                              entries);
1391                 rte_free(fdir_filter);
1392         }
1393
1394         return 0;
1395 }
1396
1397 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1398 {
1399         struct ixgbe_l2_tn_info *l2_tn_info =
1400                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1401         struct ixgbe_l2_tn_filter *l2_tn_filter;
1402
1403         if (l2_tn_info->hash_map)
1404                 rte_free(l2_tn_info->hash_map);
1405         if (l2_tn_info->hash_handle)
1406                 rte_hash_free(l2_tn_info->hash_handle);
1407
1408         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1409                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1410                              l2_tn_filter,
1411                              entries);
1412                 rte_free(l2_tn_filter);
1413         }
1414
1415         return 0;
1416 }
1417
1418 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1419 {
1420         struct ixgbe_hw_fdir_info *fdir_info =
1421                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1422         char fdir_hash_name[RTE_HASH_NAMESIZE];
1423         struct rte_hash_parameters fdir_hash_params = {
1424                 .name = fdir_hash_name,
1425                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1426                 .key_len = sizeof(union ixgbe_atr_input),
1427                 .hash_func = rte_hash_crc,
1428                 .hash_func_init_val = 0,
1429                 .socket_id = rte_socket_id(),
1430         };
1431
1432         TAILQ_INIT(&fdir_info->fdir_list);
1433         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1434                  "fdir_%s", eth_dev->device->name);
1435         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1436         if (!fdir_info->hash_handle) {
1437                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1438                 return -EINVAL;
1439         }
1440         fdir_info->hash_map = rte_zmalloc("ixgbe",
1441                                           sizeof(struct ixgbe_fdir_filter *) *
1442                                           IXGBE_MAX_FDIR_FILTER_NUM,
1443                                           0);
1444         if (!fdir_info->hash_map) {
1445                 PMD_INIT_LOG(ERR,
1446                              "Failed to allocate memory for fdir hash map!");
1447                 return -ENOMEM;
1448         }
1449         fdir_info->mask_added = FALSE;
1450
1451         return 0;
1452 }
1453
1454 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1455 {
1456         struct ixgbe_l2_tn_info *l2_tn_info =
1457                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1458         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1459         struct rte_hash_parameters l2_tn_hash_params = {
1460                 .name = l2_tn_hash_name,
1461                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1462                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1463                 .hash_func = rte_hash_crc,
1464                 .hash_func_init_val = 0,
1465                 .socket_id = rte_socket_id(),
1466         };
1467
1468         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1469         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1470                  "l2_tn_%s", eth_dev->device->name);
1471         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1472         if (!l2_tn_info->hash_handle) {
1473                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1474                 return -EINVAL;
1475         }
1476         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1477                                    sizeof(struct ixgbe_l2_tn_filter *) *
1478                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1479                                    0);
1480         if (!l2_tn_info->hash_map) {
1481                 PMD_INIT_LOG(ERR,
1482                         "Failed to allocate memory for L2 TN hash map!");
1483                 return -ENOMEM;
1484         }
1485         l2_tn_info->e_tag_en = FALSE;
1486         l2_tn_info->e_tag_fwd_en = FALSE;
1487         l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG;
1488
1489         return 0;
1490 }
1491 /*
1492  * Negotiate mailbox API version with the PF.
1493  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1494  * Then we try to negotiate starting with the most recent one.
1495  * If all negotiation attempts fail, then we will proceed with
1496  * the default one (ixgbe_mbox_api_10).
1497  */
1498 static void
1499 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1500 {
1501         int32_t i;
1502
1503         /* start with highest supported, proceed down */
1504         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1505                 ixgbe_mbox_api_12,
1506                 ixgbe_mbox_api_11,
1507                 ixgbe_mbox_api_10,
1508         };
1509
1510         for (i = 0;
1511                         i != RTE_DIM(sup_ver) &&
1512                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1513                         i++)
1514                 ;
1515 }
1516
1517 static void
1518 generate_random_mac_addr(struct ether_addr *mac_addr)
1519 {
1520         uint64_t random;
1521
1522         /* Set Organizationally Unique Identifier (OUI) prefix. */
1523         mac_addr->addr_bytes[0] = 0x00;
1524         mac_addr->addr_bytes[1] = 0x09;
1525         mac_addr->addr_bytes[2] = 0xC0;
1526         /* Force indication of locally assigned MAC address. */
1527         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1528         /* Generate the last 3 bytes of the MAC address with a random number. */
1529         random = rte_rand();
1530         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1531 }
1532
1533 /*
1534  * Virtual Function device init
1535  */
1536 static int
1537 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1538 {
1539         int diag;
1540         uint32_t tc, tcs;
1541         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1542         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1543         struct ixgbe_hw *hw =
1544                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1545         struct ixgbe_vfta *shadow_vfta =
1546                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1547         struct ixgbe_hwstrip *hwstrip =
1548                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1549         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1550
1551         PMD_INIT_FUNC_TRACE();
1552
1553         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1554         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1555         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1556
1557         /* for secondary processes, we don't initialise any further as primary
1558          * has already done this work. Only check we don't need a different
1559          * RX function
1560          */
1561         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1562                 struct ixgbe_tx_queue *txq;
1563                 /* TX queue function in primary, set by last queue initialized
1564                  * Tx queue may not initialized by primary process
1565                  */
1566                 if (eth_dev->data->tx_queues) {
1567                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1568                         ixgbe_set_tx_function(eth_dev, txq);
1569                 } else {
1570                         /* Use default TX function if we get here */
1571                         PMD_INIT_LOG(NOTICE,
1572                                      "No TX queues configured yet. Using default TX function.");
1573                 }
1574
1575                 ixgbe_set_rx_function(eth_dev);
1576
1577                 return 0;
1578         }
1579
1580         rte_eth_copy_pci_info(eth_dev, pci_dev);
1581
1582         hw->device_id = pci_dev->id.device_id;
1583         hw->vendor_id = pci_dev->id.vendor_id;
1584         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1585
1586         /* initialize the vfta */
1587         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1588
1589         /* initialize the hw strip bitmap*/
1590         memset(hwstrip, 0, sizeof(*hwstrip));
1591
1592         /* Initialize the shared code (base driver) */
1593         diag = ixgbe_init_shared_code(hw);
1594         if (diag != IXGBE_SUCCESS) {
1595                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1596                 return -EIO;
1597         }
1598
1599         /* init_mailbox_params */
1600         hw->mbx.ops.init_params(hw);
1601
1602         /* Reset the hw statistics */
1603         ixgbevf_dev_stats_reset(eth_dev);
1604
1605         /* Disable the interrupts for VF */
1606         ixgbevf_intr_disable(eth_dev);
1607
1608         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1609         diag = hw->mac.ops.reset_hw(hw);
1610
1611         /*
1612          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1613          * the underlying PF driver has not assigned a MAC address to the VF.
1614          * In this case, assign a random MAC address.
1615          */
1616         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1617                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1618                 return diag;
1619         }
1620
1621         /* negotiate mailbox API version to use with the PF. */
1622         ixgbevf_negotiate_api(hw);
1623
1624         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1625         ixgbevf_get_queues(hw, &tcs, &tc);
1626
1627         /* Allocate memory for storing MAC addresses */
1628         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1629                                                hw->mac.num_rar_entries, 0);
1630         if (eth_dev->data->mac_addrs == NULL) {
1631                 PMD_INIT_LOG(ERR,
1632                              "Failed to allocate %u bytes needed to store "
1633                              "MAC addresses",
1634                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1635                 return -ENOMEM;
1636         }
1637
1638         /* Generate a random MAC address, if none was assigned by PF. */
1639         if (is_zero_ether_addr(perm_addr)) {
1640                 generate_random_mac_addr(perm_addr);
1641                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1642                 if (diag) {
1643                         rte_free(eth_dev->data->mac_addrs);
1644                         eth_dev->data->mac_addrs = NULL;
1645                         return diag;
1646                 }
1647                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1648                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1649                              "%02x:%02x:%02x:%02x:%02x:%02x",
1650                              perm_addr->addr_bytes[0],
1651                              perm_addr->addr_bytes[1],
1652                              perm_addr->addr_bytes[2],
1653                              perm_addr->addr_bytes[3],
1654                              perm_addr->addr_bytes[4],
1655                              perm_addr->addr_bytes[5]);
1656         }
1657
1658         /* Copy the permanent MAC address */
1659         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1660
1661         /* reset the hardware with the new settings */
1662         diag = hw->mac.ops.start_hw(hw);
1663         switch (diag) {
1664         case  0:
1665                 break;
1666
1667         default:
1668                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1669                 return -EIO;
1670         }
1671
1672         rte_intr_callback_register(intr_handle,
1673                                    ixgbevf_dev_interrupt_handler, eth_dev);
1674         rte_intr_enable(intr_handle);
1675         ixgbevf_intr_enable(eth_dev);
1676
1677         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1678                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1679                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1680
1681         return 0;
1682 }
1683
1684 /* Virtual Function device uninit */
1685
1686 static int
1687 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1688 {
1689         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1690         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1691         struct ixgbe_hw *hw;
1692
1693         PMD_INIT_FUNC_TRACE();
1694
1695         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1696                 return -EPERM;
1697
1698         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1699
1700         if (hw->adapter_stopped == 0)
1701                 ixgbevf_dev_close(eth_dev);
1702
1703         eth_dev->dev_ops = NULL;
1704         eth_dev->rx_pkt_burst = NULL;
1705         eth_dev->tx_pkt_burst = NULL;
1706
1707         /* Disable the interrupts for VF */
1708         ixgbevf_intr_disable(eth_dev);
1709
1710         rte_free(eth_dev->data->mac_addrs);
1711         eth_dev->data->mac_addrs = NULL;
1712
1713         rte_intr_disable(intr_handle);
1714         rte_intr_callback_unregister(intr_handle,
1715                                      ixgbevf_dev_interrupt_handler, eth_dev);
1716
1717         return 0;
1718 }
1719
1720 static int
1721 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1722                 struct rte_pci_device *pci_dev)
1723 {
1724         char name[RTE_ETH_NAME_MAX_LEN];
1725         struct rte_eth_dev *pf_ethdev;
1726         struct rte_eth_devargs eth_da;
1727         int i, retval;
1728
1729         if (pci_dev->device.devargs) {
1730                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1731                                 &eth_da);
1732                 if (retval)
1733                         return retval;
1734         } else
1735                 memset(&eth_da, 0, sizeof(eth_da));
1736
1737         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1738                 sizeof(struct ixgbe_adapter),
1739                 eth_dev_pci_specific_init, pci_dev,
1740                 eth_ixgbe_dev_init, NULL);
1741
1742         if (retval || eth_da.nb_representor_ports < 1)
1743                 return retval;
1744
1745         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1746         if (pf_ethdev == NULL)
1747                 return -ENODEV;
1748
1749         /* probe VF representor ports */
1750         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1751                 struct ixgbe_vf_info *vfinfo;
1752                 struct ixgbe_vf_representor representor;
1753
1754                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1755                         pf_ethdev->data->dev_private);
1756                 if (vfinfo == NULL) {
1757                         PMD_DRV_LOG(ERR,
1758                                 "no virtual functions supported by PF");
1759                         break;
1760                 }
1761
1762                 representor.vf_id = eth_da.representor_ports[i];
1763                 representor.switch_domain_id = vfinfo->switch_domain_id;
1764                 representor.pf_ethdev = pf_ethdev;
1765
1766                 /* representor port net_bdf_port */
1767                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1768                         pci_dev->device.name,
1769                         eth_da.representor_ports[i]);
1770
1771                 retval = rte_eth_dev_create(&pci_dev->device, name,
1772                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1773                         ixgbe_vf_representor_init, &representor);
1774
1775                 if (retval)
1776                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1777                                 "representor %s.", name);
1778         }
1779
1780         return 0;
1781 }
1782
1783 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1784 {
1785         struct rte_eth_dev *ethdev;
1786
1787         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1788         if (!ethdev)
1789                 return -ENODEV;
1790
1791         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1792                 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1793         else
1794                 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1795 }
1796
1797 static struct rte_pci_driver rte_ixgbe_pmd = {
1798         .id_table = pci_id_ixgbe_map,
1799         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1800                      RTE_PCI_DRV_IOVA_AS_VA,
1801         .probe = eth_ixgbe_pci_probe,
1802         .remove = eth_ixgbe_pci_remove,
1803 };
1804
1805 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1806         struct rte_pci_device *pci_dev)
1807 {
1808         return rte_eth_dev_pci_generic_probe(pci_dev,
1809                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1810 }
1811
1812 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1813 {
1814         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1815 }
1816
1817 /*
1818  * virtual function driver struct
1819  */
1820 static struct rte_pci_driver rte_ixgbevf_pmd = {
1821         .id_table = pci_id_ixgbevf_map,
1822         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1823         .probe = eth_ixgbevf_pci_probe,
1824         .remove = eth_ixgbevf_pci_remove,
1825 };
1826
1827 static int
1828 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1829 {
1830         struct ixgbe_hw *hw =
1831                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1832         struct ixgbe_vfta *shadow_vfta =
1833                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1834         uint32_t vfta;
1835         uint32_t vid_idx;
1836         uint32_t vid_bit;
1837
1838         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1839         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1840         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1841         if (on)
1842                 vfta |= vid_bit;
1843         else
1844                 vfta &= ~vid_bit;
1845         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1846
1847         /* update local VFTA copy */
1848         shadow_vfta->vfta[vid_idx] = vfta;
1849
1850         return 0;
1851 }
1852
1853 static void
1854 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1855 {
1856         if (on)
1857                 ixgbe_vlan_hw_strip_enable(dev, queue);
1858         else
1859                 ixgbe_vlan_hw_strip_disable(dev, queue);
1860 }
1861
1862 static int
1863 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1864                     enum rte_vlan_type vlan_type,
1865                     uint16_t tpid)
1866 {
1867         struct ixgbe_hw *hw =
1868                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1869         int ret = 0;
1870         uint32_t reg;
1871         uint32_t qinq;
1872
1873         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1874         qinq &= IXGBE_DMATXCTL_GDV;
1875
1876         switch (vlan_type) {
1877         case ETH_VLAN_TYPE_INNER:
1878                 if (qinq) {
1879                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1880                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1881                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1882                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1883                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1884                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1885                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1886                 } else {
1887                         ret = -ENOTSUP;
1888                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1889                                     " by single VLAN");
1890                 }
1891                 break;
1892         case ETH_VLAN_TYPE_OUTER:
1893                 if (qinq) {
1894                         /* Only the high 16-bits is valid */
1895                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1896                                         IXGBE_EXVET_VET_EXT_SHIFT);
1897                 } else {
1898                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1899                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1900                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1901                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1902                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1903                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1904                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1905                 }
1906
1907                 break;
1908         default:
1909                 ret = -EINVAL;
1910                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1911                 break;
1912         }
1913
1914         return ret;
1915 }
1916
1917 void
1918 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1919 {
1920         struct ixgbe_hw *hw =
1921                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         uint32_t vlnctrl;
1923
1924         PMD_INIT_FUNC_TRACE();
1925
1926         /* Filter Table Disable */
1927         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1928         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1929
1930         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1931 }
1932
1933 void
1934 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1935 {
1936         struct ixgbe_hw *hw =
1937                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938         struct ixgbe_vfta *shadow_vfta =
1939                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1940         uint32_t vlnctrl;
1941         uint16_t i;
1942
1943         PMD_INIT_FUNC_TRACE();
1944
1945         /* Filter Table Enable */
1946         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1947         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1948         vlnctrl |= IXGBE_VLNCTRL_VFE;
1949
1950         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1951
1952         /* write whatever is in local vfta copy */
1953         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1954                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1955 }
1956
1957 static void
1958 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1959 {
1960         struct ixgbe_hwstrip *hwstrip =
1961                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1962         struct ixgbe_rx_queue *rxq;
1963
1964         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1965                 return;
1966
1967         if (on)
1968                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1969         else
1970                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1971
1972         if (queue >= dev->data->nb_rx_queues)
1973                 return;
1974
1975         rxq = dev->data->rx_queues[queue];
1976
1977         if (on)
1978                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1979         else
1980                 rxq->vlan_flags = PKT_RX_VLAN;
1981 }
1982
1983 static void
1984 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1985 {
1986         struct ixgbe_hw *hw =
1987                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1988         uint32_t ctrl;
1989
1990         PMD_INIT_FUNC_TRACE();
1991
1992         if (hw->mac.type == ixgbe_mac_82598EB) {
1993                 /* No queue level support */
1994                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1995                 return;
1996         }
1997
1998         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1999         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2000         ctrl &= ~IXGBE_RXDCTL_VME;
2001         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2002
2003         /* record those setting for HW strip per queue */
2004         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2005 }
2006
2007 static void
2008 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2009 {
2010         struct ixgbe_hw *hw =
2011                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2012         uint32_t ctrl;
2013
2014         PMD_INIT_FUNC_TRACE();
2015
2016         if (hw->mac.type == ixgbe_mac_82598EB) {
2017                 /* No queue level supported */
2018                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2019                 return;
2020         }
2021
2022         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2023         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2024         ctrl |= IXGBE_RXDCTL_VME;
2025         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2026
2027         /* record those setting for HW strip per queue */
2028         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2029 }
2030
2031 static void
2032 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2033 {
2034         struct ixgbe_hw *hw =
2035                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2036         uint32_t ctrl;
2037
2038         PMD_INIT_FUNC_TRACE();
2039
2040         /* DMATXCTRL: Geric Double VLAN Disable */
2041         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2042         ctrl &= ~IXGBE_DMATXCTL_GDV;
2043         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2044
2045         /* CTRL_EXT: Global Double VLAN Disable */
2046         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2047         ctrl &= ~IXGBE_EXTENDED_VLAN;
2048         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2049
2050 }
2051
2052 static void
2053 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2054 {
2055         struct ixgbe_hw *hw =
2056                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2057         uint32_t ctrl;
2058
2059         PMD_INIT_FUNC_TRACE();
2060
2061         /* DMATXCTRL: Geric Double VLAN Enable */
2062         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2063         ctrl |= IXGBE_DMATXCTL_GDV;
2064         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2065
2066         /* CTRL_EXT: Global Double VLAN Enable */
2067         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2068         ctrl |= IXGBE_EXTENDED_VLAN;
2069         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2070
2071         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2072         if (hw->mac.type == ixgbe_mac_X550 ||
2073             hw->mac.type == ixgbe_mac_X550EM_x ||
2074             hw->mac.type == ixgbe_mac_X550EM_a) {
2075                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2076                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2077                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2078         }
2079
2080         /*
2081          * VET EXT field in the EXVET register = 0x8100 by default
2082          * So no need to change. Same to VT field of DMATXCTL register
2083          */
2084 }
2085
2086 void
2087 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2088 {
2089         struct ixgbe_hw *hw =
2090                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2091         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2092         uint32_t ctrl;
2093         uint16_t i;
2094         struct ixgbe_rx_queue *rxq;
2095         bool on;
2096
2097         PMD_INIT_FUNC_TRACE();
2098
2099         if (hw->mac.type == ixgbe_mac_82598EB) {
2100                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2101                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2102                         ctrl |= IXGBE_VLNCTRL_VME;
2103                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2104                 } else {
2105                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2106                         ctrl &= ~IXGBE_VLNCTRL_VME;
2107                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2108                 }
2109         } else {
2110                 /*
2111                  * Other 10G NIC, the VLAN strip can be setup
2112                  * per queue in RXDCTL
2113                  */
2114                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2115                         rxq = dev->data->rx_queues[i];
2116                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2117                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2118                                 ctrl |= IXGBE_RXDCTL_VME;
2119                                 on = TRUE;
2120                         } else {
2121                                 ctrl &= ~IXGBE_RXDCTL_VME;
2122                                 on = FALSE;
2123                         }
2124                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2125
2126                         /* record those setting for HW strip per queue */
2127                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2128                 }
2129         }
2130 }
2131
2132 static int
2133 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2134 {
2135         struct rte_eth_rxmode *rxmode;
2136         rxmode = &dev->data->dev_conf.rxmode;
2137
2138         if (mask & ETH_VLAN_STRIP_MASK) {
2139                 ixgbe_vlan_hw_strip_config(dev);
2140         }
2141
2142         if (mask & ETH_VLAN_FILTER_MASK) {
2143                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2144                         ixgbe_vlan_hw_filter_enable(dev);
2145                 else
2146                         ixgbe_vlan_hw_filter_disable(dev);
2147         }
2148
2149         if (mask & ETH_VLAN_EXTEND_MASK) {
2150                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2151                         ixgbe_vlan_hw_extend_enable(dev);
2152                 else
2153                         ixgbe_vlan_hw_extend_disable(dev);
2154         }
2155
2156         return 0;
2157 }
2158
2159 static void
2160 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2161 {
2162         struct ixgbe_hw *hw =
2163                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2164         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2165         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2166
2167         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2168         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2169 }
2170
2171 static int
2172 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2173 {
2174         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2175
2176         switch (nb_rx_q) {
2177         case 1:
2178         case 2:
2179                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2180                 break;
2181         case 4:
2182                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2183                 break;
2184         default:
2185                 return -EINVAL;
2186         }
2187
2188         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2189                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2190         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2191                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2192         return 0;
2193 }
2194
2195 static int
2196 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2197 {
2198         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2199         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2200         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2201         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2202
2203         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2204                 /* check multi-queue mode */
2205                 switch (dev_conf->rxmode.mq_mode) {
2206                 case ETH_MQ_RX_VMDQ_DCB:
2207                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2208                         break;
2209                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2210                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2211                         PMD_INIT_LOG(ERR, "SRIOV active,"
2212                                         " unsupported mq_mode rx %d.",
2213                                         dev_conf->rxmode.mq_mode);
2214                         return -EINVAL;
2215                 case ETH_MQ_RX_RSS:
2216                 case ETH_MQ_RX_VMDQ_RSS:
2217                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2218                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2219                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2220                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2221                                                 " invalid queue number"
2222                                                 " for VMDQ RSS, allowed"
2223                                                 " value are 1, 2 or 4.");
2224                                         return -EINVAL;
2225                                 }
2226                         break;
2227                 case ETH_MQ_RX_VMDQ_ONLY:
2228                 case ETH_MQ_RX_NONE:
2229                         /* if nothing mq mode configure, use default scheme */
2230                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2231                         break;
2232                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2233                         /* SRIOV only works in VMDq enable mode */
2234                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2235                                         " wrong mq_mode rx %d.",
2236                                         dev_conf->rxmode.mq_mode);
2237                         return -EINVAL;
2238                 }
2239
2240                 switch (dev_conf->txmode.mq_mode) {
2241                 case ETH_MQ_TX_VMDQ_DCB:
2242                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2243                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2244                         break;
2245                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2246                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2247                         break;
2248                 }
2249
2250                 /* check valid queue number */
2251                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2252                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2253                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2254                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2255                                         " must be less than or equal to %d.",
2256                                         nb_rx_q, nb_tx_q,
2257                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2258                         return -EINVAL;
2259                 }
2260         } else {
2261                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2262                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2263                                           " not supported.");
2264                         return -EINVAL;
2265                 }
2266                 /* check configuration for vmdb+dcb mode */
2267                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2268                         const struct rte_eth_vmdq_dcb_conf *conf;
2269
2270                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2271                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2272                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2273                                 return -EINVAL;
2274                         }
2275                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2276                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2277                                conf->nb_queue_pools == ETH_32_POOLS)) {
2278                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2279                                                 " nb_queue_pools must be %d or %d.",
2280                                                 ETH_16_POOLS, ETH_32_POOLS);
2281                                 return -EINVAL;
2282                         }
2283                 }
2284                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2285                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2286
2287                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2288                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2289                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2290                                 return -EINVAL;
2291                         }
2292                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2293                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2294                                conf->nb_queue_pools == ETH_32_POOLS)) {
2295                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2296                                                 " nb_queue_pools != %d and"
2297                                                 " nb_queue_pools != %d.",
2298                                                 ETH_16_POOLS, ETH_32_POOLS);
2299                                 return -EINVAL;
2300                         }
2301                 }
2302
2303                 /* For DCB mode check our configuration before we go further */
2304                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2305                         const struct rte_eth_dcb_rx_conf *conf;
2306
2307                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2308                         if (!(conf->nb_tcs == ETH_4_TCS ||
2309                                conf->nb_tcs == ETH_8_TCS)) {
2310                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2311                                                 " and nb_tcs != %d.",
2312                                                 ETH_4_TCS, ETH_8_TCS);
2313                                 return -EINVAL;
2314                         }
2315                 }
2316
2317                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2318                         const struct rte_eth_dcb_tx_conf *conf;
2319
2320                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2321                         if (!(conf->nb_tcs == ETH_4_TCS ||
2322                                conf->nb_tcs == ETH_8_TCS)) {
2323                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2324                                                 " and nb_tcs != %d.",
2325                                                 ETH_4_TCS, ETH_8_TCS);
2326                                 return -EINVAL;
2327                         }
2328                 }
2329
2330                 /*
2331                  * When DCB/VT is off, maximum number of queues changes,
2332                  * except for 82598EB, which remains constant.
2333                  */
2334                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2335                                 hw->mac.type != ixgbe_mac_82598EB) {
2336                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2337                                 PMD_INIT_LOG(ERR,
2338                                              "Neither VT nor DCB are enabled, "
2339                                              "nb_tx_q > %d.",
2340                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2341                                 return -EINVAL;
2342                         }
2343                 }
2344         }
2345         return 0;
2346 }
2347
2348 static int
2349 ixgbe_dev_configure(struct rte_eth_dev *dev)
2350 {
2351         struct ixgbe_interrupt *intr =
2352                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2353         struct ixgbe_adapter *adapter =
2354                 (struct ixgbe_adapter *)dev->data->dev_private;
2355         int ret;
2356
2357         PMD_INIT_FUNC_TRACE();
2358         /* multipe queue mode checking */
2359         ret  = ixgbe_check_mq_mode(dev);
2360         if (ret != 0) {
2361                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2362                             ret);
2363                 return ret;
2364         }
2365
2366         /* set flag to update link status after init */
2367         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2368
2369         /*
2370          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2371          * allocation or vector Rx preconditions we will reset it.
2372          */
2373         adapter->rx_bulk_alloc_allowed = true;
2374         adapter->rx_vec_allowed = true;
2375
2376         return 0;
2377 }
2378
2379 static void
2380 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2381 {
2382         struct ixgbe_hw *hw =
2383                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2384         struct ixgbe_interrupt *intr =
2385                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2386         uint32_t gpie;
2387
2388         /* only set up it on X550EM_X */
2389         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2390                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2391                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2392                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2393                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2394                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2395         }
2396 }
2397
2398 int
2399 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2400                         uint16_t tx_rate, uint64_t q_msk)
2401 {
2402         struct ixgbe_hw *hw;
2403         struct ixgbe_vf_info *vfinfo;
2404         struct rte_eth_link link;
2405         uint8_t  nb_q_per_pool;
2406         uint32_t queue_stride;
2407         uint32_t queue_idx, idx = 0, vf_idx;
2408         uint32_t queue_end;
2409         uint16_t total_rate = 0;
2410         struct rte_pci_device *pci_dev;
2411
2412         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2413         rte_eth_link_get_nowait(dev->data->port_id, &link);
2414
2415         if (vf >= pci_dev->max_vfs)
2416                 return -EINVAL;
2417
2418         if (tx_rate > link.link_speed)
2419                 return -EINVAL;
2420
2421         if (q_msk == 0)
2422                 return 0;
2423
2424         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2425         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2426         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2427         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2428         queue_idx = vf * queue_stride;
2429         queue_end = queue_idx + nb_q_per_pool - 1;
2430         if (queue_end >= hw->mac.max_tx_queues)
2431                 return -EINVAL;
2432
2433         if (vfinfo) {
2434                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2435                         if (vf_idx == vf)
2436                                 continue;
2437                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2438                                 idx++)
2439                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2440                 }
2441         } else {
2442                 return -EINVAL;
2443         }
2444
2445         /* Store tx_rate for this vf. */
2446         for (idx = 0; idx < nb_q_per_pool; idx++) {
2447                 if (((uint64_t)0x1 << idx) & q_msk) {
2448                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2449                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2450                         total_rate += tx_rate;
2451                 }
2452         }
2453
2454         if (total_rate > dev->data->dev_link.link_speed) {
2455                 /* Reset stored TX rate of the VF if it causes exceed
2456                  * link speed.
2457                  */
2458                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2459                 return -EINVAL;
2460         }
2461
2462         /* Set RTTBCNRC of each queue/pool for vf X  */
2463         for (; queue_idx <= queue_end; queue_idx++) {
2464                 if (0x1 & q_msk)
2465                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2466                 q_msk = q_msk >> 1;
2467         }
2468
2469         return 0;
2470 }
2471
2472 /*
2473  * Configure device link speed and setup link.
2474  * It returns 0 on success.
2475  */
2476 static int
2477 ixgbe_dev_start(struct rte_eth_dev *dev)
2478 {
2479         struct ixgbe_hw *hw =
2480                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2481         struct ixgbe_vf_info *vfinfo =
2482                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2483         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2484         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2485         uint32_t intr_vector = 0;
2486         int err, link_up = 0, negotiate = 0;
2487         uint32_t speed = 0;
2488         uint32_t allowed_speeds = 0;
2489         int mask = 0;
2490         int status;
2491         uint16_t vf, idx;
2492         uint32_t *link_speeds;
2493         struct ixgbe_tm_conf *tm_conf =
2494                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2495
2496         PMD_INIT_FUNC_TRACE();
2497
2498         /* IXGBE devices don't support:
2499         *    - half duplex (checked afterwards for valid speeds)
2500         *    - fixed speed: TODO implement
2501         */
2502         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2503                 PMD_INIT_LOG(ERR,
2504                 "Invalid link_speeds for port %u, fix speed not supported",
2505                                 dev->data->port_id);
2506                 return -EINVAL;
2507         }
2508
2509         /* disable uio/vfio intr/eventfd mapping */
2510         rte_intr_disable(intr_handle);
2511
2512         /* stop adapter */
2513         hw->adapter_stopped = 0;
2514         ixgbe_stop_adapter(hw);
2515
2516         /* reinitialize adapter
2517          * this calls reset and start
2518          */
2519         status = ixgbe_pf_reset_hw(hw);
2520         if (status != 0)
2521                 return -1;
2522         hw->mac.ops.start_hw(hw);
2523         hw->mac.get_link_status = true;
2524
2525         /* configure PF module if SRIOV enabled */
2526         ixgbe_pf_host_configure(dev);
2527
2528         ixgbe_dev_phy_intr_setup(dev);
2529
2530         /* check and configure queue intr-vector mapping */
2531         if ((rte_intr_cap_multiple(intr_handle) ||
2532              !RTE_ETH_DEV_SRIOV(dev).active) &&
2533             dev->data->dev_conf.intr_conf.rxq != 0) {
2534                 intr_vector = dev->data->nb_rx_queues;
2535                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2536                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2537                                         IXGBE_MAX_INTR_QUEUE_NUM);
2538                         return -ENOTSUP;
2539                 }
2540                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2541                         return -1;
2542         }
2543
2544         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2545                 intr_handle->intr_vec =
2546                         rte_zmalloc("intr_vec",
2547                                     dev->data->nb_rx_queues * sizeof(int), 0);
2548                 if (intr_handle->intr_vec == NULL) {
2549                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2550                                      " intr_vec", dev->data->nb_rx_queues);
2551                         return -ENOMEM;
2552                 }
2553         }
2554
2555         /* confiugre msix for sleep until rx interrupt */
2556         ixgbe_configure_msix(dev);
2557
2558         /* initialize transmission unit */
2559         ixgbe_dev_tx_init(dev);
2560
2561         /* This can fail when allocating mbufs for descriptor rings */
2562         err = ixgbe_dev_rx_init(dev);
2563         if (err) {
2564                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2565                 goto error;
2566         }
2567
2568         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2569                 ETH_VLAN_EXTEND_MASK;
2570         err = ixgbe_vlan_offload_set(dev, mask);
2571         if (err) {
2572                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2573                 goto error;
2574         }
2575
2576         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2577                 /* Enable vlan filtering for VMDq */
2578                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2579         }
2580
2581         /* Configure DCB hw */
2582         ixgbe_configure_dcb(dev);
2583
2584         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2585                 err = ixgbe_fdir_configure(dev);
2586                 if (err)
2587                         goto error;
2588         }
2589
2590         /* Restore vf rate limit */
2591         if (vfinfo != NULL) {
2592                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2593                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2594                                 if (vfinfo[vf].tx_rate[idx] != 0)
2595                                         ixgbe_set_vf_rate_limit(
2596                                                 dev, vf,
2597                                                 vfinfo[vf].tx_rate[idx],
2598                                                 1 << idx);
2599         }
2600
2601         ixgbe_restore_statistics_mapping(dev);
2602
2603         err = ixgbe_dev_rxtx_start(dev);
2604         if (err < 0) {
2605                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2606                 goto error;
2607         }
2608
2609         /* Skip link setup if loopback mode is enabled for 82599. */
2610         if (hw->mac.type == ixgbe_mac_82599EB &&
2611                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2612                 goto skip_link_setup;
2613
2614         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2615                 err = hw->mac.ops.setup_sfp(hw);
2616                 if (err)
2617                         goto error;
2618         }
2619
2620         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2621                 /* Turn on the copper */
2622                 ixgbe_set_phy_power(hw, true);
2623         } else {
2624                 /* Turn on the laser */
2625                 ixgbe_enable_tx_laser(hw);
2626         }
2627
2628         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2629         if (err)
2630                 goto error;
2631         dev->data->dev_link.link_status = link_up;
2632
2633         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2634         if (err)
2635                 goto error;
2636
2637         switch (hw->mac.type) {
2638         case ixgbe_mac_X550:
2639         case ixgbe_mac_X550EM_x:
2640         case ixgbe_mac_X550EM_a:
2641                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2642                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2643                         ETH_LINK_SPEED_10G;
2644                 break;
2645         default:
2646                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2647                         ETH_LINK_SPEED_10G;
2648         }
2649
2650         link_speeds = &dev->data->dev_conf.link_speeds;
2651         if (*link_speeds & ~allowed_speeds) {
2652                 PMD_INIT_LOG(ERR, "Invalid link setting");
2653                 goto error;
2654         }
2655
2656         speed = 0x0;
2657         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2658                 switch (hw->mac.type) {
2659                 case ixgbe_mac_82598EB:
2660                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2661                         break;
2662                 case ixgbe_mac_82599EB:
2663                 case ixgbe_mac_X540:
2664                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2665                         break;
2666                 case ixgbe_mac_X550:
2667                 case ixgbe_mac_X550EM_x:
2668                 case ixgbe_mac_X550EM_a:
2669                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2670                         break;
2671                 default:
2672                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2673                 }
2674         } else {
2675                 if (*link_speeds & ETH_LINK_SPEED_10G)
2676                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2677                 if (*link_speeds & ETH_LINK_SPEED_5G)
2678                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2679                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2680                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2681                 if (*link_speeds & ETH_LINK_SPEED_1G)
2682                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2683                 if (*link_speeds & ETH_LINK_SPEED_100M)
2684                         speed |= IXGBE_LINK_SPEED_100_FULL;
2685         }
2686
2687         err = ixgbe_setup_link(hw, speed, link_up);
2688         if (err)
2689                 goto error;
2690
2691         ixgbe_dev_link_update(dev, 0);
2692
2693 skip_link_setup:
2694
2695         if (rte_intr_allow_others(intr_handle)) {
2696                 /* check if lsc interrupt is enabled */
2697                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2698                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2699                 else
2700                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2701                 ixgbe_dev_macsec_interrupt_setup(dev);
2702         } else {
2703                 rte_intr_callback_unregister(intr_handle,
2704                                              ixgbe_dev_interrupt_handler, dev);
2705                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2706                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2707                                      " no intr multiplex");
2708         }
2709
2710         /* check if rxq interrupt is enabled */
2711         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2712             rte_intr_dp_is_en(intr_handle))
2713                 ixgbe_dev_rxq_interrupt_setup(dev);
2714
2715         /* enable uio/vfio intr/eventfd mapping */
2716         rte_intr_enable(intr_handle);
2717
2718         /* resume enabled intr since hw reset */
2719         ixgbe_enable_intr(dev);
2720         ixgbe_l2_tunnel_conf(dev);
2721         ixgbe_filter_restore(dev);
2722
2723         if (tm_conf->root && !tm_conf->committed)
2724                 PMD_DRV_LOG(WARNING,
2725                             "please call hierarchy_commit() "
2726                             "before starting the port");
2727
2728         return 0;
2729
2730 error:
2731         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2732         ixgbe_dev_clear_queues(dev);
2733         return -EIO;
2734 }
2735
2736 /*
2737  * Stop device: disable rx and tx functions to allow for reconfiguring.
2738  */
2739 static void
2740 ixgbe_dev_stop(struct rte_eth_dev *dev)
2741 {
2742         struct rte_eth_link link;
2743         struct ixgbe_hw *hw =
2744                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2745         struct ixgbe_vf_info *vfinfo =
2746                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2747         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2748         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2749         int vf;
2750         struct ixgbe_tm_conf *tm_conf =
2751                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2752
2753         PMD_INIT_FUNC_TRACE();
2754
2755         /* disable interrupts */
2756         ixgbe_disable_intr(hw);
2757
2758         /* reset the NIC */
2759         ixgbe_pf_reset_hw(hw);
2760         hw->adapter_stopped = 0;
2761
2762         /* stop adapter */
2763         ixgbe_stop_adapter(hw);
2764
2765         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2766                 vfinfo[vf].clear_to_send = false;
2767
2768         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2769                 /* Turn off the copper */
2770                 ixgbe_set_phy_power(hw, false);
2771         } else {
2772                 /* Turn off the laser */
2773                 ixgbe_disable_tx_laser(hw);
2774         }
2775
2776         ixgbe_dev_clear_queues(dev);
2777
2778         /* Clear stored conf */
2779         dev->data->scattered_rx = 0;
2780         dev->data->lro = 0;
2781
2782         /* Clear recorded link status */
2783         memset(&link, 0, sizeof(link));
2784         rte_eth_linkstatus_set(dev, &link);
2785
2786         if (!rte_intr_allow_others(intr_handle))
2787                 /* resume to the default handler */
2788                 rte_intr_callback_register(intr_handle,
2789                                            ixgbe_dev_interrupt_handler,
2790                                            (void *)dev);
2791
2792         /* Clean datapath event and queue/vec mapping */
2793         rte_intr_efd_disable(intr_handle);
2794         if (intr_handle->intr_vec != NULL) {
2795                 rte_free(intr_handle->intr_vec);
2796                 intr_handle->intr_vec = NULL;
2797         }
2798
2799         /* reset hierarchy commit */
2800         tm_conf->committed = false;
2801 }
2802
2803 /*
2804  * Set device link up: enable tx.
2805  */
2806 static int
2807 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2808 {
2809         struct ixgbe_hw *hw =
2810                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2811         if (hw->mac.type == ixgbe_mac_82599EB) {
2812 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2813                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2814                         /* Not suported in bypass mode */
2815                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2816                                      "by device id 0x%x", hw->device_id);
2817                         return -ENOTSUP;
2818                 }
2819 #endif
2820         }
2821
2822         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2823                 /* Turn on the copper */
2824                 ixgbe_set_phy_power(hw, true);
2825         } else {
2826                 /* Turn on the laser */
2827                 ixgbe_enable_tx_laser(hw);
2828         }
2829
2830         return 0;
2831 }
2832
2833 /*
2834  * Set device link down: disable tx.
2835  */
2836 static int
2837 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2838 {
2839         struct ixgbe_hw *hw =
2840                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2841         if (hw->mac.type == ixgbe_mac_82599EB) {
2842 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2843                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2844                         /* Not suported in bypass mode */
2845                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2846                                      "by device id 0x%x", hw->device_id);
2847                         return -ENOTSUP;
2848                 }
2849 #endif
2850         }
2851
2852         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2853                 /* Turn off the copper */
2854                 ixgbe_set_phy_power(hw, false);
2855         } else {
2856                 /* Turn off the laser */
2857                 ixgbe_disable_tx_laser(hw);
2858         }
2859
2860         return 0;
2861 }
2862
2863 /*
2864  * Reset and stop device.
2865  */
2866 static void
2867 ixgbe_dev_close(struct rte_eth_dev *dev)
2868 {
2869         struct ixgbe_hw *hw =
2870                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2871
2872         PMD_INIT_FUNC_TRACE();
2873
2874         ixgbe_pf_reset_hw(hw);
2875
2876         ixgbe_dev_stop(dev);
2877         hw->adapter_stopped = 1;
2878
2879         ixgbe_dev_free_queues(dev);
2880
2881         ixgbe_disable_pcie_master(hw);
2882
2883         /* reprogram the RAR[0] in case user changed it. */
2884         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2885 }
2886
2887 /*
2888  * Reset PF device.
2889  */
2890 static int
2891 ixgbe_dev_reset(struct rte_eth_dev *dev)
2892 {
2893         int ret;
2894
2895         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2896          * its VF to make them align with it. The detailed notification
2897          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2898          * To avoid unexpected behavior in VF, currently reset of PF with
2899          * SR-IOV activation is not supported. It might be supported later.
2900          */
2901         if (dev->data->sriov.active)
2902                 return -ENOTSUP;
2903
2904         ret = eth_ixgbe_dev_uninit(dev);
2905         if (ret)
2906                 return ret;
2907
2908         ret = eth_ixgbe_dev_init(dev, NULL);
2909
2910         return ret;
2911 }
2912
2913 static void
2914 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2915                            struct ixgbe_hw_stats *hw_stats,
2916                            struct ixgbe_macsec_stats *macsec_stats,
2917                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2918                            uint64_t *total_qprc, uint64_t *total_qprdc)
2919 {
2920         uint32_t bprc, lxon, lxoff, total;
2921         uint32_t delta_gprc = 0;
2922         unsigned i;
2923         /* Workaround for RX byte count not including CRC bytes when CRC
2924          * strip is enabled. CRC bytes are removed from counters when crc_strip
2925          * is disabled.
2926          */
2927         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2928                         IXGBE_HLREG0_RXCRCSTRP);
2929
2930         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2931         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2932         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2933         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2934
2935         for (i = 0; i < 8; i++) {
2936                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2937
2938                 /* global total per queue */
2939                 hw_stats->mpc[i] += mp;
2940                 /* Running comprehensive total for stats display */
2941                 *total_missed_rx += hw_stats->mpc[i];
2942                 if (hw->mac.type == ixgbe_mac_82598EB) {
2943                         hw_stats->rnbc[i] +=
2944                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2945                         hw_stats->pxonrxc[i] +=
2946                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2947                         hw_stats->pxoffrxc[i] +=
2948                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2949                 } else {
2950                         hw_stats->pxonrxc[i] +=
2951                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2952                         hw_stats->pxoffrxc[i] +=
2953                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2954                         hw_stats->pxon2offc[i] +=
2955                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2956                 }
2957                 hw_stats->pxontxc[i] +=
2958                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2959                 hw_stats->pxofftxc[i] +=
2960                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2961         }
2962         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2963                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2964                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2965                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2966
2967                 delta_gprc += delta_qprc;
2968
2969                 hw_stats->qprc[i] += delta_qprc;
2970                 hw_stats->qptc[i] += delta_qptc;
2971
2972                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2973                 hw_stats->qbrc[i] +=
2974                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2975                 if (crc_strip == 0)
2976                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2977
2978                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2979                 hw_stats->qbtc[i] +=
2980                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2981
2982                 hw_stats->qprdc[i] += delta_qprdc;
2983                 *total_qprdc += hw_stats->qprdc[i];
2984
2985                 *total_qprc += hw_stats->qprc[i];
2986                 *total_qbrc += hw_stats->qbrc[i];
2987         }
2988         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2989         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2990         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2991
2992         /*
2993          * An errata states that gprc actually counts good + missed packets:
2994          * Workaround to set gprc to summated queue packet receives
2995          */
2996         hw_stats->gprc = *total_qprc;
2997
2998         if (hw->mac.type != ixgbe_mac_82598EB) {
2999                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3000                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3001                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3002                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3003                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3004                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3005                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3006                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3007         } else {
3008                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3009                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3010                 /* 82598 only has a counter in the high register */
3011                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3012                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3013                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3014         }
3015         uint64_t old_tpr = hw_stats->tpr;
3016
3017         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3018         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3019
3020         if (crc_strip == 0)
3021                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3022
3023         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3024         hw_stats->gptc += delta_gptc;
3025         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3026         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3027
3028         /*
3029          * Workaround: mprc hardware is incorrectly counting
3030          * broadcasts, so for now we subtract those.
3031          */
3032         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3033         hw_stats->bprc += bprc;
3034         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3035         if (hw->mac.type == ixgbe_mac_82598EB)
3036                 hw_stats->mprc -= bprc;
3037
3038         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3039         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3040         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3041         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3042         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3043         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3044
3045         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3046         hw_stats->lxontxc += lxon;
3047         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3048         hw_stats->lxofftxc += lxoff;
3049         total = lxon + lxoff;
3050
3051         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3052         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3053         hw_stats->gptc -= total;
3054         hw_stats->mptc -= total;
3055         hw_stats->ptc64 -= total;
3056         hw_stats->gotc -= total * ETHER_MIN_LEN;
3057
3058         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3059         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3060         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3061         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3062         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3063         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3064         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3065         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3066         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3067         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3068         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3069         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3070         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3071         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3072         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3073         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3074         /* Only read FCOE on 82599 */
3075         if (hw->mac.type != ixgbe_mac_82598EB) {
3076                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3077                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3078                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3079                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3080                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3081         }
3082
3083         /* Flow Director Stats registers */
3084         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3085         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3086
3087         /* MACsec Stats registers */
3088         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3089         macsec_stats->out_pkts_encrypted +=
3090                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3091         macsec_stats->out_pkts_protected +=
3092                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3093         macsec_stats->out_octets_encrypted +=
3094                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3095         macsec_stats->out_octets_protected +=
3096                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3097         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3098         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3099         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3100         macsec_stats->in_pkts_unknownsci +=
3101                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3102         macsec_stats->in_octets_decrypted +=
3103                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3104         macsec_stats->in_octets_validated +=
3105                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3106         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3107         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3108         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3109         for (i = 0; i < 2; i++) {
3110                 macsec_stats->in_pkts_ok +=
3111                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3112                 macsec_stats->in_pkts_invalid +=
3113                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3114                 macsec_stats->in_pkts_notvalid +=
3115                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3116         }
3117         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3118         macsec_stats->in_pkts_notusingsa +=
3119                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3120 }
3121
3122 /*
3123  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3124  */
3125 static int
3126 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3127 {
3128         struct ixgbe_hw *hw =
3129                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3130         struct ixgbe_hw_stats *hw_stats =
3131                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3132         struct ixgbe_macsec_stats *macsec_stats =
3133                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3134                                 dev->data->dev_private);
3135         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3136         unsigned i;
3137
3138         total_missed_rx = 0;
3139         total_qbrc = 0;
3140         total_qprc = 0;
3141         total_qprdc = 0;
3142
3143         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3144                         &total_qbrc, &total_qprc, &total_qprdc);
3145
3146         if (stats == NULL)
3147                 return -EINVAL;
3148
3149         /* Fill out the rte_eth_stats statistics structure */
3150         stats->ipackets = total_qprc;
3151         stats->ibytes = total_qbrc;
3152         stats->opackets = hw_stats->gptc;
3153         stats->obytes = hw_stats->gotc;
3154
3155         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3156                 stats->q_ipackets[i] = hw_stats->qprc[i];
3157                 stats->q_opackets[i] = hw_stats->qptc[i];
3158                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3159                 stats->q_obytes[i] = hw_stats->qbtc[i];
3160                 stats->q_errors[i] = hw_stats->qprdc[i];
3161         }
3162
3163         /* Rx Errors */
3164         stats->imissed  = total_missed_rx;
3165         stats->ierrors  = hw_stats->crcerrs +
3166                           hw_stats->mspdc +
3167                           hw_stats->rlec +
3168                           hw_stats->ruc +
3169                           hw_stats->roc +
3170                           hw_stats->illerrc +
3171                           hw_stats->errbc +
3172                           hw_stats->rfc +
3173                           hw_stats->fccrc +
3174                           hw_stats->fclast;
3175
3176         /* Tx Errors */
3177         stats->oerrors  = 0;
3178         return 0;
3179 }
3180
3181 static void
3182 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3183 {
3184         struct ixgbe_hw_stats *stats =
3185                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3186
3187         /* HW registers are cleared on read */
3188         ixgbe_dev_stats_get(dev, NULL);
3189
3190         /* Reset software totals */
3191         memset(stats, 0, sizeof(*stats));
3192 }
3193
3194 /* This function calculates the number of xstats based on the current config */
3195 static unsigned
3196 ixgbe_xstats_calc_num(void) {
3197         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3198                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3199                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3200 }
3201
3202 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3203         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3204 {
3205         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3206         unsigned stat, i, count;
3207
3208         if (xstats_names != NULL) {
3209                 count = 0;
3210
3211                 /* Note: limit >= cnt_stats checked upstream
3212                  * in rte_eth_xstats_names()
3213                  */
3214
3215                 /* Extended stats from ixgbe_hw_stats */
3216                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3217                         snprintf(xstats_names[count].name,
3218                                 sizeof(xstats_names[count].name),
3219                                 "%s",
3220                                 rte_ixgbe_stats_strings[i].name);
3221                         count++;
3222                 }
3223
3224                 /* MACsec Stats */
3225                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3226                         snprintf(xstats_names[count].name,
3227                                 sizeof(xstats_names[count].name),
3228                                 "%s",
3229                                 rte_ixgbe_macsec_strings[i].name);
3230                         count++;
3231                 }
3232
3233                 /* RX Priority Stats */
3234                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3235                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3236                                 snprintf(xstats_names[count].name,
3237                                         sizeof(xstats_names[count].name),
3238                                         "rx_priority%u_%s", i,
3239                                         rte_ixgbe_rxq_strings[stat].name);
3240                                 count++;
3241                         }
3242                 }
3243
3244                 /* TX Priority Stats */
3245                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3246                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3247                                 snprintf(xstats_names[count].name,
3248                                         sizeof(xstats_names[count].name),
3249                                         "tx_priority%u_%s", i,
3250                                         rte_ixgbe_txq_strings[stat].name);
3251                                 count++;
3252                         }
3253                 }
3254         }
3255         return cnt_stats;
3256 }
3257
3258 static int ixgbe_dev_xstats_get_names_by_id(
3259         struct rte_eth_dev *dev,
3260         struct rte_eth_xstat_name *xstats_names,
3261         const uint64_t *ids,
3262         unsigned int limit)
3263 {
3264         if (!ids) {
3265                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3266                 unsigned int stat, i, count;
3267
3268                 if (xstats_names != NULL) {
3269                         count = 0;
3270
3271                         /* Note: limit >= cnt_stats checked upstream
3272                          * in rte_eth_xstats_names()
3273                          */
3274
3275                         /* Extended stats from ixgbe_hw_stats */
3276                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3277                                 snprintf(xstats_names[count].name,
3278                                         sizeof(xstats_names[count].name),
3279                                         "%s",
3280                                         rte_ixgbe_stats_strings[i].name);
3281                                 count++;
3282                         }
3283
3284                         /* MACsec Stats */
3285                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3286                                 snprintf(xstats_names[count].name,
3287                                         sizeof(xstats_names[count].name),
3288                                         "%s",
3289                                         rte_ixgbe_macsec_strings[i].name);
3290                                 count++;
3291                         }
3292
3293                         /* RX Priority Stats */
3294                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3295                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3296                                         snprintf(xstats_names[count].name,
3297                                             sizeof(xstats_names[count].name),
3298                                             "rx_priority%u_%s", i,
3299                                             rte_ixgbe_rxq_strings[stat].name);
3300                                         count++;
3301                                 }
3302                         }
3303
3304                         /* TX Priority Stats */
3305                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3306                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3307                                         snprintf(xstats_names[count].name,
3308                                             sizeof(xstats_names[count].name),
3309                                             "tx_priority%u_%s", i,
3310                                             rte_ixgbe_txq_strings[stat].name);
3311                                         count++;
3312                                 }
3313                         }
3314                 }
3315                 return cnt_stats;
3316         }
3317
3318         uint16_t i;
3319         uint16_t size = ixgbe_xstats_calc_num();
3320         struct rte_eth_xstat_name xstats_names_copy[size];
3321
3322         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3323                         size);
3324
3325         for (i = 0; i < limit; i++) {
3326                 if (ids[i] >= size) {
3327                         PMD_INIT_LOG(ERR, "id value isn't valid");
3328                         return -1;
3329                 }
3330                 strcpy(xstats_names[i].name,
3331                                 xstats_names_copy[ids[i]].name);
3332         }
3333         return limit;
3334 }
3335
3336 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3337         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3338 {
3339         unsigned i;
3340
3341         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3342                 return -ENOMEM;
3343
3344         if (xstats_names != NULL)
3345                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3346                         snprintf(xstats_names[i].name,
3347                                 sizeof(xstats_names[i].name),
3348                                 "%s", rte_ixgbevf_stats_strings[i].name);
3349         return IXGBEVF_NB_XSTATS;
3350 }
3351
3352 static int
3353 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3354                                          unsigned n)
3355 {
3356         struct ixgbe_hw *hw =
3357                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3358         struct ixgbe_hw_stats *hw_stats =
3359                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3360         struct ixgbe_macsec_stats *macsec_stats =
3361                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3362                                 dev->data->dev_private);
3363         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3364         unsigned i, stat, count = 0;
3365
3366         count = ixgbe_xstats_calc_num();
3367
3368         if (n < count)
3369                 return count;
3370
3371         total_missed_rx = 0;
3372         total_qbrc = 0;
3373         total_qprc = 0;
3374         total_qprdc = 0;
3375
3376         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3377                         &total_qbrc, &total_qprc, &total_qprdc);
3378
3379         /* If this is a reset xstats is NULL, and we have cleared the
3380          * registers by reading them.
3381          */
3382         if (!xstats)
3383                 return 0;
3384
3385         /* Extended stats from ixgbe_hw_stats */
3386         count = 0;
3387         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3388                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3389                                 rte_ixgbe_stats_strings[i].offset);
3390                 xstats[count].id = count;
3391                 count++;
3392         }
3393
3394         /* MACsec Stats */
3395         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3396                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3397                                 rte_ixgbe_macsec_strings[i].offset);
3398                 xstats[count].id = count;
3399                 count++;
3400         }
3401
3402         /* RX Priority Stats */
3403         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3404                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3405                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3406                                         rte_ixgbe_rxq_strings[stat].offset +
3407                                         (sizeof(uint64_t) * i));
3408                         xstats[count].id = count;
3409                         count++;
3410                 }
3411         }
3412
3413         /* TX Priority Stats */
3414         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3415                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3416                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3417                                         rte_ixgbe_txq_strings[stat].offset +
3418                                         (sizeof(uint64_t) * i));
3419                         xstats[count].id = count;
3420                         count++;
3421                 }
3422         }
3423         return count;
3424 }
3425
3426 static int
3427 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3428                 uint64_t *values, unsigned int n)
3429 {
3430         if (!ids) {
3431                 struct ixgbe_hw *hw =
3432                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3433                 struct ixgbe_hw_stats *hw_stats =
3434                                 IXGBE_DEV_PRIVATE_TO_STATS(
3435                                                 dev->data->dev_private);
3436                 struct ixgbe_macsec_stats *macsec_stats =
3437                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3438                                         dev->data->dev_private);
3439                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3440                 unsigned int i, stat, count = 0;
3441
3442                 count = ixgbe_xstats_calc_num();
3443
3444                 if (!ids && n < count)
3445                         return count;
3446
3447                 total_missed_rx = 0;
3448                 total_qbrc = 0;
3449                 total_qprc = 0;
3450                 total_qprdc = 0;
3451
3452                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3453                                 &total_missed_rx, &total_qbrc, &total_qprc,
3454                                 &total_qprdc);
3455
3456                 /* If this is a reset xstats is NULL, and we have cleared the
3457                  * registers by reading them.
3458                  */
3459                 if (!ids && !values)
3460                         return 0;
3461
3462                 /* Extended stats from ixgbe_hw_stats */
3463                 count = 0;
3464                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3465                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3466                                         rte_ixgbe_stats_strings[i].offset);
3467                         count++;
3468                 }
3469
3470                 /* MACsec Stats */
3471                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3472                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3473                                         rte_ixgbe_macsec_strings[i].offset);
3474                         count++;
3475                 }
3476
3477                 /* RX Priority Stats */
3478                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3479                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3480                                 values[count] =
3481                                         *(uint64_t *)(((char *)hw_stats) +
3482                                         rte_ixgbe_rxq_strings[stat].offset +
3483                                         (sizeof(uint64_t) * i));
3484                                 count++;
3485                         }
3486                 }
3487
3488                 /* TX Priority Stats */
3489                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3490                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3491                                 values[count] =
3492                                         *(uint64_t *)(((char *)hw_stats) +
3493                                         rte_ixgbe_txq_strings[stat].offset +
3494                                         (sizeof(uint64_t) * i));
3495                                 count++;
3496                         }
3497                 }
3498                 return count;
3499         }
3500
3501         uint16_t i;
3502         uint16_t size = ixgbe_xstats_calc_num();
3503         uint64_t values_copy[size];
3504
3505         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3506
3507         for (i = 0; i < n; i++) {
3508                 if (ids[i] >= size) {
3509                         PMD_INIT_LOG(ERR, "id value isn't valid");
3510                         return -1;
3511                 }
3512                 values[i] = values_copy[ids[i]];
3513         }
3514         return n;
3515 }
3516
3517 static void
3518 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3519 {
3520         struct ixgbe_hw_stats *stats =
3521                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3522         struct ixgbe_macsec_stats *macsec_stats =
3523                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3524                                 dev->data->dev_private);
3525
3526         unsigned count = ixgbe_xstats_calc_num();
3527
3528         /* HW registers are cleared on read */
3529         ixgbe_dev_xstats_get(dev, NULL, count);
3530
3531         /* Reset software totals */
3532         memset(stats, 0, sizeof(*stats));
3533         memset(macsec_stats, 0, sizeof(*macsec_stats));
3534 }
3535
3536 static void
3537 ixgbevf_update_stats(struct rte_eth_dev *dev)
3538 {
3539         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3540         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3541                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3542
3543         /* Good Rx packet, include VF loopback */
3544         UPDATE_VF_STAT(IXGBE_VFGPRC,
3545             hw_stats->last_vfgprc, hw_stats->vfgprc);
3546
3547         /* Good Rx octets, include VF loopback */
3548         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3549             hw_stats->last_vfgorc, hw_stats->vfgorc);
3550
3551         /* Good Tx packet, include VF loopback */
3552         UPDATE_VF_STAT(IXGBE_VFGPTC,
3553             hw_stats->last_vfgptc, hw_stats->vfgptc);
3554
3555         /* Good Tx octets, include VF loopback */
3556         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3557             hw_stats->last_vfgotc, hw_stats->vfgotc);
3558
3559         /* Rx Multicst Packet */
3560         UPDATE_VF_STAT(IXGBE_VFMPRC,
3561             hw_stats->last_vfmprc, hw_stats->vfmprc);
3562 }
3563
3564 static int
3565 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3566                        unsigned n)
3567 {
3568         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3569                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3570         unsigned i;
3571
3572         if (n < IXGBEVF_NB_XSTATS)
3573                 return IXGBEVF_NB_XSTATS;
3574
3575         ixgbevf_update_stats(dev);
3576
3577         if (!xstats)
3578                 return 0;
3579
3580         /* Extended stats */
3581         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3582                 xstats[i].id = i;
3583                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3584                         rte_ixgbevf_stats_strings[i].offset);
3585         }
3586
3587         return IXGBEVF_NB_XSTATS;
3588 }
3589
3590 static int
3591 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3592 {
3593         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3594                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3595
3596         ixgbevf_update_stats(dev);
3597
3598         if (stats == NULL)
3599                 return -EINVAL;
3600
3601         stats->ipackets = hw_stats->vfgprc;
3602         stats->ibytes = hw_stats->vfgorc;
3603         stats->opackets = hw_stats->vfgptc;
3604         stats->obytes = hw_stats->vfgotc;
3605         return 0;
3606 }
3607
3608 static void
3609 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3610 {
3611         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3612                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3613
3614         /* Sync HW register to the last stats */
3615         ixgbevf_dev_stats_get(dev, NULL);
3616
3617         /* reset HW current stats*/
3618         hw_stats->vfgprc = 0;
3619         hw_stats->vfgorc = 0;
3620         hw_stats->vfgptc = 0;
3621         hw_stats->vfgotc = 0;
3622 }
3623
3624 static int
3625 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3626 {
3627         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3628         u16 eeprom_verh, eeprom_verl;
3629         u32 etrack_id;
3630         int ret;
3631
3632         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3633         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3634
3635         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3636         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3637
3638         ret += 1; /* add the size of '\0' */
3639         if (fw_size < (u32)ret)
3640                 return ret;
3641         else
3642                 return 0;
3643 }
3644
3645 static void
3646 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3647 {
3648         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3649         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3650         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3651
3652         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3653         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3654         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3655                 /*
3656                  * When DCB/VT is off, maximum number of queues changes,
3657                  * except for 82598EB, which remains constant.
3658                  */
3659                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3660                                 hw->mac.type != ixgbe_mac_82598EB)
3661                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3662         }
3663         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3664         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3665         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3666         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3667         dev_info->max_vfs = pci_dev->max_vfs;
3668         if (hw->mac.type == ixgbe_mac_82598EB)
3669                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3670         else
3671                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3672         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3673         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3674         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3675                                      dev_info->rx_queue_offload_capa);
3676         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3677         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3678
3679         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3680                 .rx_thresh = {
3681                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3682                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3683                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3684                 },
3685                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3686                 .rx_drop_en = 0,
3687                 .offloads = 0,
3688         };
3689
3690         dev_info->default_txconf = (struct rte_eth_txconf) {
3691                 .tx_thresh = {
3692                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3693                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3694                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3695                 },
3696                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3697                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3698                 .offloads = 0,
3699         };
3700
3701         dev_info->rx_desc_lim = rx_desc_lim;
3702         dev_info->tx_desc_lim = tx_desc_lim;
3703
3704         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3705         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3706         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3707
3708         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3709         if (hw->mac.type == ixgbe_mac_X540 ||
3710             hw->mac.type == ixgbe_mac_X540_vf ||
3711             hw->mac.type == ixgbe_mac_X550 ||
3712             hw->mac.type == ixgbe_mac_X550_vf) {
3713                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3714         }
3715         if (hw->mac.type == ixgbe_mac_X550) {
3716                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3717                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3718         }
3719 }
3720
3721 static const uint32_t *
3722 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3723 {
3724         static const uint32_t ptypes[] = {
3725                 /* For non-vec functions,
3726                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3727                  * for vec functions,
3728                  * refers to _recv_raw_pkts_vec().
3729                  */
3730                 RTE_PTYPE_L2_ETHER,
3731                 RTE_PTYPE_L3_IPV4,
3732                 RTE_PTYPE_L3_IPV4_EXT,
3733                 RTE_PTYPE_L3_IPV6,
3734                 RTE_PTYPE_L3_IPV6_EXT,
3735                 RTE_PTYPE_L4_SCTP,
3736                 RTE_PTYPE_L4_TCP,
3737                 RTE_PTYPE_L4_UDP,
3738                 RTE_PTYPE_TUNNEL_IP,
3739                 RTE_PTYPE_INNER_L3_IPV6,
3740                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3741                 RTE_PTYPE_INNER_L4_TCP,
3742                 RTE_PTYPE_INNER_L4_UDP,
3743                 RTE_PTYPE_UNKNOWN
3744         };
3745
3746         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3747             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3748             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3749             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3750                 return ptypes;
3751
3752 #if defined(RTE_ARCH_X86)
3753         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3754             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3755                 return ptypes;
3756 #endif
3757         return NULL;
3758 }
3759
3760 static void
3761 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3762                      struct rte_eth_dev_info *dev_info)
3763 {
3764         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3765         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3766
3767         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3768         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3769         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3770         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3771         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3772         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3773         dev_info->max_vfs = pci_dev->max_vfs;
3774         if (hw->mac.type == ixgbe_mac_82598EB)
3775                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3776         else
3777                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3778         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3779         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3780                                      dev_info->rx_queue_offload_capa);
3781         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3782         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3783
3784         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3785                 .rx_thresh = {
3786                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3787                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3788                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3789                 },
3790                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3791                 .rx_drop_en = 0,
3792                 .offloads = 0,
3793         };
3794
3795         dev_info->default_txconf = (struct rte_eth_txconf) {
3796                 .tx_thresh = {
3797                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3798                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3799                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3800                 },
3801                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3802                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3803                 .offloads = 0,
3804         };
3805
3806         dev_info->rx_desc_lim = rx_desc_lim;
3807         dev_info->tx_desc_lim = tx_desc_lim;
3808 }
3809
3810 static int
3811 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3812                    int *link_up, int wait_to_complete)
3813 {
3814         /**
3815          * for a quick link status checking, wait_to_compelet == 0,
3816          * skip PF link status checking
3817          */
3818         bool no_pflink_check = wait_to_complete == 0;
3819         struct ixgbe_mbx_info *mbx = &hw->mbx;
3820         struct ixgbe_mac_info *mac = &hw->mac;
3821         uint32_t links_reg, in_msg;
3822         int ret_val = 0;
3823
3824         /* If we were hit with a reset drop the link */
3825         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3826                 mac->get_link_status = true;
3827
3828         if (!mac->get_link_status)
3829                 goto out;
3830
3831         /* if link status is down no point in checking to see if pf is up */
3832         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3833         if (!(links_reg & IXGBE_LINKS_UP))
3834                 goto out;
3835
3836         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3837          * before the link status is correct
3838          */
3839         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3840                 int i;
3841
3842                 for (i = 0; i < 5; i++) {
3843                         rte_delay_us(100);
3844                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3845
3846                         if (!(links_reg & IXGBE_LINKS_UP))
3847                                 goto out;
3848                 }
3849         }
3850
3851         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3852         case IXGBE_LINKS_SPEED_10G_82599:
3853                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3854                 if (hw->mac.type >= ixgbe_mac_X550) {
3855                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3856                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3857                 }
3858                 break;
3859         case IXGBE_LINKS_SPEED_1G_82599:
3860                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3861                 break;
3862         case IXGBE_LINKS_SPEED_100_82599:
3863                 *speed = IXGBE_LINK_SPEED_100_FULL;
3864                 if (hw->mac.type == ixgbe_mac_X550) {
3865                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3866                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3867                 }
3868                 break;
3869         case IXGBE_LINKS_SPEED_10_X550EM_A:
3870                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3871                 /* Since Reserved in older MAC's */
3872                 if (hw->mac.type >= ixgbe_mac_X550)
3873                         *speed = IXGBE_LINK_SPEED_10_FULL;
3874                 break;
3875         default:
3876                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3877         }
3878
3879         if (no_pflink_check) {
3880                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3881                         mac->get_link_status = true;
3882                 else
3883                         mac->get_link_status = false;
3884
3885                 goto out;
3886         }
3887         /* if the read failed it could just be a mailbox collision, best wait
3888          * until we are called again and don't report an error
3889          */
3890         if (mbx->ops.read(hw, &in_msg, 1, 0))
3891                 goto out;
3892
3893         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3894                 /* msg is not CTS and is NACK we must have lost CTS status */
3895                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3896                         ret_val = -1;
3897                 goto out;
3898         }
3899
3900         /* the pf is talking, if we timed out in the past we reinit */
3901         if (!mbx->timeout) {
3902                 ret_val = -1;
3903                 goto out;
3904         }
3905
3906         /* if we passed all the tests above then the link is up and we no
3907          * longer need to check for link
3908          */
3909         mac->get_link_status = false;
3910
3911 out:
3912         *link_up = !mac->get_link_status;
3913         return ret_val;
3914 }
3915
3916 /* return 0 means link status changed, -1 means not changed */
3917 int
3918 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3919                             int wait_to_complete, int vf)
3920 {
3921         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3922         struct rte_eth_link link;
3923         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3924         struct ixgbe_interrupt *intr =
3925                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3926         int link_up;
3927         int diag;
3928         u32 speed = 0;
3929         int wait = 1;
3930         bool autoneg = false;
3931
3932         memset(&link, 0, sizeof(link));
3933         link.link_status = ETH_LINK_DOWN;
3934         link.link_speed = ETH_SPEED_NUM_NONE;
3935         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3936         link.link_autoneg = ETH_LINK_AUTONEG;
3937
3938         hw->mac.get_link_status = true;
3939
3940         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3941                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3942                 speed = hw->phy.autoneg_advertised;
3943                 if (!speed)
3944                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3945                 ixgbe_setup_link(hw, speed, true);
3946         }
3947
3948         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3949         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3950                 wait = 0;
3951
3952         if (vf)
3953                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3954         else
3955                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3956
3957         if (diag != 0) {
3958                 link.link_speed = ETH_SPEED_NUM_100M;
3959                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3960                 return rte_eth_linkstatus_set(dev, &link);
3961         }
3962
3963         if (link_up == 0) {
3964                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3965                 return rte_eth_linkstatus_set(dev, &link);
3966         }
3967
3968         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3969         link.link_status = ETH_LINK_UP;
3970         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3971
3972         switch (link_speed) {
3973         default:
3974         case IXGBE_LINK_SPEED_UNKNOWN:
3975                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3976                 link.link_speed = ETH_SPEED_NUM_100M;
3977                 break;
3978
3979         case IXGBE_LINK_SPEED_100_FULL:
3980                 link.link_speed = ETH_SPEED_NUM_100M;
3981                 break;
3982
3983         case IXGBE_LINK_SPEED_1GB_FULL:
3984                 link.link_speed = ETH_SPEED_NUM_1G;
3985                 break;
3986
3987         case IXGBE_LINK_SPEED_2_5GB_FULL:
3988                 link.link_speed = ETH_SPEED_NUM_2_5G;
3989                 break;
3990
3991         case IXGBE_LINK_SPEED_5GB_FULL:
3992                 link.link_speed = ETH_SPEED_NUM_5G;
3993                 break;
3994
3995         case IXGBE_LINK_SPEED_10GB_FULL:
3996                 link.link_speed = ETH_SPEED_NUM_10G;
3997                 break;
3998         }
3999
4000         return rte_eth_linkstatus_set(dev, &link);
4001 }
4002
4003 static int
4004 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4005 {
4006         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4007 }
4008
4009 static int
4010 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4011 {
4012         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4013 }
4014
4015 static void
4016 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4017 {
4018         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4019         uint32_t fctrl;
4020
4021         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4022         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4023         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4024 }
4025
4026 static void
4027 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4028 {
4029         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4030         uint32_t fctrl;
4031
4032         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4033         fctrl &= (~IXGBE_FCTRL_UPE);
4034         if (dev->data->all_multicast == 1)
4035                 fctrl |= IXGBE_FCTRL_MPE;
4036         else
4037                 fctrl &= (~IXGBE_FCTRL_MPE);
4038         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4039 }
4040
4041 static void
4042 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4043 {
4044         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4045         uint32_t fctrl;
4046
4047         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4048         fctrl |= IXGBE_FCTRL_MPE;
4049         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4050 }
4051
4052 static void
4053 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4054 {
4055         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4056         uint32_t fctrl;
4057
4058         if (dev->data->promiscuous == 1)
4059                 return; /* must remain in all_multicast mode */
4060
4061         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4062         fctrl &= (~IXGBE_FCTRL_MPE);
4063         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4064 }
4065
4066 /**
4067  * It clears the interrupt causes and enables the interrupt.
4068  * It will be called once only during nic initialized.
4069  *
4070  * @param dev
4071  *  Pointer to struct rte_eth_dev.
4072  * @param on
4073  *  Enable or Disable.
4074  *
4075  * @return
4076  *  - On success, zero.
4077  *  - On failure, a negative value.
4078  */
4079 static int
4080 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4081 {
4082         struct ixgbe_interrupt *intr =
4083                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4084
4085         ixgbe_dev_link_status_print(dev);
4086         if (on)
4087                 intr->mask |= IXGBE_EICR_LSC;
4088         else
4089                 intr->mask &= ~IXGBE_EICR_LSC;
4090
4091         return 0;
4092 }
4093
4094 /**
4095  * It clears the interrupt causes and enables the interrupt.
4096  * It will be called once only during nic initialized.
4097  *
4098  * @param dev
4099  *  Pointer to struct rte_eth_dev.
4100  *
4101  * @return
4102  *  - On success, zero.
4103  *  - On failure, a negative value.
4104  */
4105 static int
4106 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4107 {
4108         struct ixgbe_interrupt *intr =
4109                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4110
4111         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4112
4113         return 0;
4114 }
4115
4116 /**
4117  * It clears the interrupt causes and enables the interrupt.
4118  * It will be called once only during nic initialized.
4119  *
4120  * @param dev
4121  *  Pointer to struct rte_eth_dev.
4122  *
4123  * @return
4124  *  - On success, zero.
4125  *  - On failure, a negative value.
4126  */
4127 static int
4128 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4129 {
4130         struct ixgbe_interrupt *intr =
4131                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4132
4133         intr->mask |= IXGBE_EICR_LINKSEC;
4134
4135         return 0;
4136 }
4137
4138 /*
4139  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4140  *
4141  * @param dev
4142  *  Pointer to struct rte_eth_dev.
4143  *
4144  * @return
4145  *  - On success, zero.
4146  *  - On failure, a negative value.
4147  */
4148 static int
4149 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4150 {
4151         uint32_t eicr;
4152         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4153         struct ixgbe_interrupt *intr =
4154                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4155
4156         /* clear all cause mask */
4157         ixgbe_disable_intr(hw);
4158
4159         /* read-on-clear nic registers here */
4160         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4161         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4162
4163         intr->flags = 0;
4164
4165         /* set flag for async link update */
4166         if (eicr & IXGBE_EICR_LSC)
4167                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4168
4169         if (eicr & IXGBE_EICR_MAILBOX)
4170                 intr->flags |= IXGBE_FLAG_MAILBOX;
4171
4172         if (eicr & IXGBE_EICR_LINKSEC)
4173                 intr->flags |= IXGBE_FLAG_MACSEC;
4174
4175         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4176             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4177             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4178                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4179
4180         return 0;
4181 }
4182
4183 /**
4184  * It gets and then prints the link status.
4185  *
4186  * @param dev
4187  *  Pointer to struct rte_eth_dev.
4188  *
4189  * @return
4190  *  - On success, zero.
4191  *  - On failure, a negative value.
4192  */
4193 static void
4194 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4195 {
4196         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4197         struct rte_eth_link link;
4198
4199         rte_eth_linkstatus_get(dev, &link);
4200
4201         if (link.link_status) {
4202                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4203                                         (int)(dev->data->port_id),
4204                                         (unsigned)link.link_speed,
4205                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4206                                         "full-duplex" : "half-duplex");
4207         } else {
4208                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4209                                 (int)(dev->data->port_id));
4210         }
4211         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4212                                 pci_dev->addr.domain,
4213                                 pci_dev->addr.bus,
4214                                 pci_dev->addr.devid,
4215                                 pci_dev->addr.function);
4216 }
4217
4218 /*
4219  * It executes link_update after knowing an interrupt occurred.
4220  *
4221  * @param dev
4222  *  Pointer to struct rte_eth_dev.
4223  *
4224  * @return
4225  *  - On success, zero.
4226  *  - On failure, a negative value.
4227  */
4228 static int
4229 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4230                            struct rte_intr_handle *intr_handle)
4231 {
4232         struct ixgbe_interrupt *intr =
4233                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4234         int64_t timeout;
4235         struct ixgbe_hw *hw =
4236                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4237
4238         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4239
4240         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4241                 ixgbe_pf_mbx_process(dev);
4242                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4243         }
4244
4245         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4246                 ixgbe_handle_lasi(hw);
4247                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4248         }
4249
4250         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4251                 struct rte_eth_link link;
4252
4253                 /* get the link status before link update, for predicting later */
4254                 rte_eth_linkstatus_get(dev, &link);
4255
4256                 ixgbe_dev_link_update(dev, 0);
4257
4258                 /* likely to up */
4259                 if (!link.link_status)
4260                         /* handle it 1 sec later, wait it being stable */
4261                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4262                 /* likely to down */
4263                 else
4264                         /* handle it 4 sec later, wait it being stable */
4265                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4266
4267                 ixgbe_dev_link_status_print(dev);
4268                 if (rte_eal_alarm_set(timeout * 1000,
4269                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4270                         PMD_DRV_LOG(ERR, "Error setting alarm");
4271                 else {
4272                         /* remember original mask */
4273                         intr->mask_original = intr->mask;
4274                         /* only disable lsc interrupt */
4275                         intr->mask &= ~IXGBE_EIMS_LSC;
4276                 }
4277         }
4278
4279         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4280         ixgbe_enable_intr(dev);
4281         rte_intr_enable(intr_handle);
4282
4283         return 0;
4284 }
4285
4286 /**
4287  * Interrupt handler which shall be registered for alarm callback for delayed
4288  * handling specific interrupt to wait for the stable nic state. As the
4289  * NIC interrupt state is not stable for ixgbe after link is just down,
4290  * it needs to wait 4 seconds to get the stable status.
4291  *
4292  * @param handle
4293  *  Pointer to interrupt handle.
4294  * @param param
4295  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4296  *
4297  * @return
4298  *  void
4299  */
4300 static void
4301 ixgbe_dev_interrupt_delayed_handler(void *param)
4302 {
4303         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4304         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4305         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4306         struct ixgbe_interrupt *intr =
4307                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4308         struct ixgbe_hw *hw =
4309                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4310         uint32_t eicr;
4311
4312         ixgbe_disable_intr(hw);
4313
4314         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4315         if (eicr & IXGBE_EICR_MAILBOX)
4316                 ixgbe_pf_mbx_process(dev);
4317
4318         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4319                 ixgbe_handle_lasi(hw);
4320                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4321         }
4322
4323         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4324                 ixgbe_dev_link_update(dev, 0);
4325                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4326                 ixgbe_dev_link_status_print(dev);
4327                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4328                                               NULL);
4329         }
4330
4331         if (intr->flags & IXGBE_FLAG_MACSEC) {
4332                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4333                                               NULL);
4334                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4335         }
4336
4337         /* restore original mask */
4338         intr->mask = intr->mask_original;
4339         intr->mask_original = 0;
4340
4341         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4342         ixgbe_enable_intr(dev);
4343         rte_intr_enable(intr_handle);
4344 }
4345
4346 /**
4347  * Interrupt handler triggered by NIC  for handling
4348  * specific interrupt.
4349  *
4350  * @param handle
4351  *  Pointer to interrupt handle.
4352  * @param param
4353  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4354  *
4355  * @return
4356  *  void
4357  */
4358 static void
4359 ixgbe_dev_interrupt_handler(void *param)
4360 {
4361         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4362
4363         ixgbe_dev_interrupt_get_status(dev);
4364         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4365 }
4366
4367 static int
4368 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4369 {
4370         struct ixgbe_hw *hw;
4371
4372         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4373         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4374 }
4375
4376 static int
4377 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4378 {
4379         struct ixgbe_hw *hw;
4380
4381         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4382         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4383 }
4384
4385 static int
4386 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4387 {
4388         struct ixgbe_hw *hw;
4389         uint32_t mflcn_reg;
4390         uint32_t fccfg_reg;
4391         int rx_pause;
4392         int tx_pause;
4393
4394         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4395
4396         fc_conf->pause_time = hw->fc.pause_time;
4397         fc_conf->high_water = hw->fc.high_water[0];
4398         fc_conf->low_water = hw->fc.low_water[0];
4399         fc_conf->send_xon = hw->fc.send_xon;
4400         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4401
4402         /*
4403          * Return rx_pause status according to actual setting of
4404          * MFLCN register.
4405          */
4406         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4407         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4408                 rx_pause = 1;
4409         else
4410                 rx_pause = 0;
4411
4412         /*
4413          * Return tx_pause status according to actual setting of
4414          * FCCFG register.
4415          */
4416         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4417         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4418                 tx_pause = 1;
4419         else
4420                 tx_pause = 0;
4421
4422         if (rx_pause && tx_pause)
4423                 fc_conf->mode = RTE_FC_FULL;
4424         else if (rx_pause)
4425                 fc_conf->mode = RTE_FC_RX_PAUSE;
4426         else if (tx_pause)
4427                 fc_conf->mode = RTE_FC_TX_PAUSE;
4428         else
4429                 fc_conf->mode = RTE_FC_NONE;
4430
4431         return 0;
4432 }
4433
4434 static int
4435 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4436 {
4437         struct ixgbe_hw *hw;
4438         int err;
4439         uint32_t rx_buf_size;
4440         uint32_t max_high_water;
4441         uint32_t mflcn;
4442         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4443                 ixgbe_fc_none,
4444                 ixgbe_fc_rx_pause,
4445                 ixgbe_fc_tx_pause,
4446                 ixgbe_fc_full
4447         };
4448
4449         PMD_INIT_FUNC_TRACE();
4450
4451         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4452         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4453         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4454
4455         /*
4456          * At least reserve one Ethernet frame for watermark
4457          * high_water/low_water in kilo bytes for ixgbe
4458          */
4459         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4460         if ((fc_conf->high_water > max_high_water) ||
4461                 (fc_conf->high_water < fc_conf->low_water)) {
4462                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4463                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4464                 return -EINVAL;
4465         }
4466
4467         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4468         hw->fc.pause_time     = fc_conf->pause_time;
4469         hw->fc.high_water[0]  = fc_conf->high_water;
4470         hw->fc.low_water[0]   = fc_conf->low_water;
4471         hw->fc.send_xon       = fc_conf->send_xon;
4472         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4473
4474         err = ixgbe_fc_enable(hw);
4475
4476         /* Not negotiated is not an error case */
4477         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4478
4479                 /* check if we want to forward MAC frames - driver doesn't have native
4480                  * capability to do that, so we'll write the registers ourselves */
4481
4482                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4483
4484                 /* set or clear MFLCN.PMCF bit depending on configuration */
4485                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4486                         mflcn |= IXGBE_MFLCN_PMCF;
4487                 else
4488                         mflcn &= ~IXGBE_MFLCN_PMCF;
4489
4490                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4491                 IXGBE_WRITE_FLUSH(hw);
4492
4493                 return 0;
4494         }
4495
4496         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4497         return -EIO;
4498 }
4499
4500 /**
4501  *  ixgbe_pfc_enable_generic - Enable flow control
4502  *  @hw: pointer to hardware structure
4503  *  @tc_num: traffic class number
4504  *  Enable flow control according to the current settings.
4505  */
4506 static int
4507 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4508 {
4509         int ret_val = 0;
4510         uint32_t mflcn_reg, fccfg_reg;
4511         uint32_t reg;
4512         uint32_t fcrtl, fcrth;
4513         uint8_t i;
4514         uint8_t nb_rx_en;
4515
4516         /* Validate the water mark configuration */
4517         if (!hw->fc.pause_time) {
4518                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4519                 goto out;
4520         }
4521
4522         /* Low water mark of zero causes XOFF floods */
4523         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4524                  /* High/Low water can not be 0 */
4525                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4526                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4527                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4528                         goto out;
4529                 }
4530
4531                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4532                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4533                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4534                         goto out;
4535                 }
4536         }
4537         /* Negotiate the fc mode to use */
4538         ixgbe_fc_autoneg(hw);
4539
4540         /* Disable any previous flow control settings */
4541         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4542         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4543
4544         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4545         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4546
4547         switch (hw->fc.current_mode) {
4548         case ixgbe_fc_none:
4549                 /*
4550                  * If the count of enabled RX Priority Flow control >1,
4551                  * and the TX pause can not be disabled
4552                  */
4553                 nb_rx_en = 0;
4554                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4555                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4556                         if (reg & IXGBE_FCRTH_FCEN)
4557                                 nb_rx_en++;
4558                 }
4559                 if (nb_rx_en > 1)
4560                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4561                 break;
4562         case ixgbe_fc_rx_pause:
4563                 /*
4564                  * Rx Flow control is enabled and Tx Flow control is
4565                  * disabled by software override. Since there really
4566                  * isn't a way to advertise that we are capable of RX
4567                  * Pause ONLY, we will advertise that we support both
4568                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4569                  * disable the adapter's ability to send PAUSE frames.
4570                  */
4571                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4572                 /*
4573                  * If the count of enabled RX Priority Flow control >1,
4574                  * and the TX pause can not be disabled
4575                  */
4576                 nb_rx_en = 0;
4577                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4578                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4579                         if (reg & IXGBE_FCRTH_FCEN)
4580                                 nb_rx_en++;
4581                 }
4582                 if (nb_rx_en > 1)
4583                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4584                 break;
4585         case ixgbe_fc_tx_pause:
4586                 /*
4587                  * Tx Flow control is enabled, and Rx Flow control is
4588                  * disabled by software override.
4589                  */
4590                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4591                 break;
4592         case ixgbe_fc_full:
4593                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4594                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4595                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4596                 break;
4597         default:
4598                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4599                 ret_val = IXGBE_ERR_CONFIG;
4600                 goto out;
4601         }
4602
4603         /* Set 802.3x based flow control settings. */
4604         mflcn_reg |= IXGBE_MFLCN_DPF;
4605         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4606         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4607
4608         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4609         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4610                 hw->fc.high_water[tc_num]) {
4611                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4612                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4613                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4614         } else {
4615                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4616                 /*
4617                  * In order to prevent Tx hangs when the internal Tx
4618                  * switch is enabled we must set the high water mark
4619                  * to the maximum FCRTH value.  This allows the Tx
4620                  * switch to function even under heavy Rx workloads.
4621                  */
4622                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4623         }
4624         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4625
4626         /* Configure pause time (2 TCs per register) */
4627         reg = hw->fc.pause_time * 0x00010001;
4628         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4629                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4630
4631         /* Configure flow control refresh threshold value */
4632         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4633
4634 out:
4635         return ret_val;
4636 }
4637
4638 static int
4639 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4640 {
4641         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4642         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4643
4644         if (hw->mac.type != ixgbe_mac_82598EB) {
4645                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4646         }
4647         return ret_val;
4648 }
4649
4650 static int
4651 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4652 {
4653         int err;
4654         uint32_t rx_buf_size;
4655         uint32_t max_high_water;
4656         uint8_t tc_num;
4657         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4658         struct ixgbe_hw *hw =
4659                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4660         struct ixgbe_dcb_config *dcb_config =
4661                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4662
4663         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4664                 ixgbe_fc_none,
4665                 ixgbe_fc_rx_pause,
4666                 ixgbe_fc_tx_pause,
4667                 ixgbe_fc_full
4668         };
4669
4670         PMD_INIT_FUNC_TRACE();
4671
4672         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4673         tc_num = map[pfc_conf->priority];
4674         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4675         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4676         /*
4677          * At least reserve one Ethernet frame for watermark
4678          * high_water/low_water in kilo bytes for ixgbe
4679          */
4680         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4681         if ((pfc_conf->fc.high_water > max_high_water) ||
4682             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4683                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4684                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4685                 return -EINVAL;
4686         }
4687
4688         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4689         hw->fc.pause_time = pfc_conf->fc.pause_time;
4690         hw->fc.send_xon = pfc_conf->fc.send_xon;
4691         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4692         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4693
4694         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4695
4696         /* Not negotiated is not an error case */
4697         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4698                 return 0;
4699
4700         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4701         return -EIO;
4702 }
4703
4704 static int
4705 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4706                           struct rte_eth_rss_reta_entry64 *reta_conf,
4707                           uint16_t reta_size)
4708 {
4709         uint16_t i, sp_reta_size;
4710         uint8_t j, mask;
4711         uint32_t reta, r;
4712         uint16_t idx, shift;
4713         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4714         uint32_t reta_reg;
4715
4716         PMD_INIT_FUNC_TRACE();
4717
4718         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4719                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4720                         "NIC.");
4721                 return -ENOTSUP;
4722         }
4723
4724         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4725         if (reta_size != sp_reta_size) {
4726                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4727                         "(%d) doesn't match the number hardware can supported "
4728                         "(%d)", reta_size, sp_reta_size);
4729                 return -EINVAL;
4730         }
4731
4732         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4733                 idx = i / RTE_RETA_GROUP_SIZE;
4734                 shift = i % RTE_RETA_GROUP_SIZE;
4735                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4736                                                 IXGBE_4_BIT_MASK);
4737                 if (!mask)
4738                         continue;
4739                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4740                 if (mask == IXGBE_4_BIT_MASK)
4741                         r = 0;
4742                 else
4743                         r = IXGBE_READ_REG(hw, reta_reg);
4744                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4745                         if (mask & (0x1 << j))
4746                                 reta |= reta_conf[idx].reta[shift + j] <<
4747                                                         (CHAR_BIT * j);
4748                         else
4749                                 reta |= r & (IXGBE_8_BIT_MASK <<
4750                                                 (CHAR_BIT * j));
4751                 }
4752                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4753         }
4754
4755         return 0;
4756 }
4757
4758 static int
4759 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4760                          struct rte_eth_rss_reta_entry64 *reta_conf,
4761                          uint16_t reta_size)
4762 {
4763         uint16_t i, sp_reta_size;
4764         uint8_t j, mask;
4765         uint32_t reta;
4766         uint16_t idx, shift;
4767         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4768         uint32_t reta_reg;
4769
4770         PMD_INIT_FUNC_TRACE();
4771         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4772         if (reta_size != sp_reta_size) {
4773                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4774                         "(%d) doesn't match the number hardware can supported "
4775                         "(%d)", reta_size, sp_reta_size);
4776                 return -EINVAL;
4777         }
4778
4779         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4780                 idx = i / RTE_RETA_GROUP_SIZE;
4781                 shift = i % RTE_RETA_GROUP_SIZE;
4782                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4783                                                 IXGBE_4_BIT_MASK);
4784                 if (!mask)
4785                         continue;
4786
4787                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4788                 reta = IXGBE_READ_REG(hw, reta_reg);
4789                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4790                         if (mask & (0x1 << j))
4791                                 reta_conf[idx].reta[shift + j] =
4792                                         ((reta >> (CHAR_BIT * j)) &
4793                                                 IXGBE_8_BIT_MASK);
4794                 }
4795         }
4796
4797         return 0;
4798 }
4799
4800 static int
4801 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4802                                 uint32_t index, uint32_t pool)
4803 {
4804         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4805         uint32_t enable_addr = 1;
4806
4807         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4808                              pool, enable_addr);
4809 }
4810
4811 static void
4812 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4813 {
4814         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4815
4816         ixgbe_clear_rar(hw, index);
4817 }
4818
4819 static int
4820 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4821 {
4822         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4823
4824         ixgbe_remove_rar(dev, 0);
4825         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4826
4827         return 0;
4828 }
4829
4830 static bool
4831 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4832 {
4833         if (strcmp(dev->device->driver->name, drv->driver.name))
4834                 return false;
4835
4836         return true;
4837 }
4838
4839 bool
4840 is_ixgbe_supported(struct rte_eth_dev *dev)
4841 {
4842         return is_device_supported(dev, &rte_ixgbe_pmd);
4843 }
4844
4845 static int
4846 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4847 {
4848         uint32_t hlreg0;
4849         uint32_t maxfrs;
4850         struct ixgbe_hw *hw;
4851         struct rte_eth_dev_info dev_info;
4852         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4853         struct rte_eth_dev_data *dev_data = dev->data;
4854
4855         ixgbe_dev_info_get(dev, &dev_info);
4856
4857         /* check that mtu is within the allowed range */
4858         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4859                 return -EINVAL;
4860
4861         /* If device is started, refuse mtu that requires the support of
4862          * scattered packets when this feature has not been enabled before.
4863          */
4864         if (dev_data->dev_started && !dev_data->scattered_rx &&
4865             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4866              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4867                 PMD_INIT_LOG(ERR, "Stop port first.");
4868                 return -EINVAL;
4869         }
4870
4871         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4872         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4873
4874         /* switch to jumbo mode if needed */
4875         if (frame_size > ETHER_MAX_LEN) {
4876                 dev->data->dev_conf.rxmode.offloads |=
4877                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4878                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4879         } else {
4880                 dev->data->dev_conf.rxmode.offloads &=
4881                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4882                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4883         }
4884         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4885
4886         /* update max frame size */
4887         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4888
4889         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4890         maxfrs &= 0x0000FFFF;
4891         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4892         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4893
4894         return 0;
4895 }
4896
4897 /*
4898  * Virtual Function operations
4899  */
4900 static void
4901 ixgbevf_intr_disable(struct rte_eth_dev *dev)
4902 {
4903         struct ixgbe_interrupt *intr =
4904                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4905         struct ixgbe_hw *hw =
4906                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4907
4908         PMD_INIT_FUNC_TRACE();
4909
4910         /* Clear interrupt mask to stop from interrupts being generated */
4911         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4912
4913         IXGBE_WRITE_FLUSH(hw);
4914
4915         /* Clear mask value. */
4916         intr->mask = 0;
4917 }
4918
4919 static void
4920 ixgbevf_intr_enable(struct rte_eth_dev *dev)
4921 {
4922         struct ixgbe_interrupt *intr =
4923                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4924         struct ixgbe_hw *hw =
4925                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4926
4927         PMD_INIT_FUNC_TRACE();
4928
4929         /* VF enable interrupt autoclean */
4930         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4931         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4932         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4933
4934         IXGBE_WRITE_FLUSH(hw);
4935
4936         /* Save IXGBE_VTEIMS value to mask. */
4937         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
4938 }
4939
4940 static int
4941 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4942 {
4943         struct rte_eth_conf *conf = &dev->data->dev_conf;
4944         struct ixgbe_adapter *adapter =
4945                         (struct ixgbe_adapter *)dev->data->dev_private;
4946
4947         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4948                      dev->data->port_id);
4949
4950         /*
4951          * VF has no ability to enable/disable HW CRC
4952          * Keep the persistent behavior the same as Host PF
4953          */
4954 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4955         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
4956                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4957                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
4958         }
4959 #else
4960         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
4961                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4962                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_CRC_STRIP;
4963         }
4964 #endif
4965
4966         /*
4967          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4968          * allocation or vector Rx preconditions we will reset it.
4969          */
4970         adapter->rx_bulk_alloc_allowed = true;
4971         adapter->rx_vec_allowed = true;
4972
4973         return 0;
4974 }
4975
4976 static int
4977 ixgbevf_dev_start(struct rte_eth_dev *dev)
4978 {
4979         struct ixgbe_hw *hw =
4980                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4981         uint32_t intr_vector = 0;
4982         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4983         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4984
4985         int err, mask = 0;
4986
4987         PMD_INIT_FUNC_TRACE();
4988
4989         err = hw->mac.ops.reset_hw(hw);
4990         if (err) {
4991                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
4992                 return err;
4993         }
4994         hw->mac.get_link_status = true;
4995
4996         /* negotiate mailbox API version to use with the PF. */
4997         ixgbevf_negotiate_api(hw);
4998
4999         ixgbevf_dev_tx_init(dev);
5000
5001         /* This can fail when allocating mbufs for descriptor rings */
5002         err = ixgbevf_dev_rx_init(dev);
5003         if (err) {
5004                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5005                 ixgbe_dev_clear_queues(dev);
5006                 return err;
5007         }
5008
5009         /* Set vfta */
5010         ixgbevf_set_vfta_all(dev, 1);
5011
5012         /* Set HW strip */
5013         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5014                 ETH_VLAN_EXTEND_MASK;
5015         err = ixgbevf_vlan_offload_set(dev, mask);
5016         if (err) {
5017                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5018                 ixgbe_dev_clear_queues(dev);
5019                 return err;
5020         }
5021
5022         ixgbevf_dev_rxtx_start(dev);
5023
5024         ixgbevf_dev_link_update(dev, 0);
5025
5026         /* check and configure queue intr-vector mapping */
5027         if (rte_intr_cap_multiple(intr_handle) &&
5028             dev->data->dev_conf.intr_conf.rxq) {
5029                 /* According to datasheet, only vector 0/1/2 can be used,
5030                  * now only one vector is used for Rx queue
5031                  */
5032                 intr_vector = 1;
5033                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5034                         return -1;
5035         }
5036
5037         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5038                 intr_handle->intr_vec =
5039                         rte_zmalloc("intr_vec",
5040                                     dev->data->nb_rx_queues * sizeof(int), 0);
5041                 if (intr_handle->intr_vec == NULL) {
5042                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5043                                      " intr_vec", dev->data->nb_rx_queues);
5044                         return -ENOMEM;
5045                 }
5046         }
5047         ixgbevf_configure_msix(dev);
5048
5049         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5050          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5051          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5052          * is not cleared, it will fail when following rte_intr_enable( ) tries
5053          * to map Rx queue interrupt to other VFIO vectors.
5054          * So clear uio/vfio intr/evevnfd first to avoid failure.
5055          */
5056         rte_intr_disable(intr_handle);
5057
5058         rte_intr_enable(intr_handle);
5059
5060         /* Re-enable interrupt for VF */
5061         ixgbevf_intr_enable(dev);
5062
5063         return 0;
5064 }
5065
5066 static void
5067 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5068 {
5069         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5070         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5071         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5072
5073         PMD_INIT_FUNC_TRACE();
5074
5075         ixgbevf_intr_disable(dev);
5076
5077         hw->adapter_stopped = 1;
5078         ixgbe_stop_adapter(hw);
5079
5080         /*
5081           * Clear what we set, but we still keep shadow_vfta to
5082           * restore after device starts
5083           */
5084         ixgbevf_set_vfta_all(dev, 0);
5085
5086         /* Clear stored conf */
5087         dev->data->scattered_rx = 0;
5088
5089         ixgbe_dev_clear_queues(dev);
5090
5091         /* Clean datapath event and queue/vec mapping */
5092         rte_intr_efd_disable(intr_handle);
5093         if (intr_handle->intr_vec != NULL) {
5094                 rte_free(intr_handle->intr_vec);
5095                 intr_handle->intr_vec = NULL;
5096         }
5097 }
5098
5099 static void
5100 ixgbevf_dev_close(struct rte_eth_dev *dev)
5101 {
5102         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5103
5104         PMD_INIT_FUNC_TRACE();
5105
5106         ixgbe_reset_hw(hw);
5107
5108         ixgbevf_dev_stop(dev);
5109
5110         ixgbe_dev_free_queues(dev);
5111
5112         /**
5113          * Remove the VF MAC address ro ensure
5114          * that the VF traffic goes to the PF
5115          * after stop, close and detach of the VF
5116          **/
5117         ixgbevf_remove_mac_addr(dev, 0);
5118 }
5119
5120 /*
5121  * Reset VF device
5122  */
5123 static int
5124 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5125 {
5126         int ret;
5127
5128         ret = eth_ixgbevf_dev_uninit(dev);
5129         if (ret)
5130                 return ret;
5131
5132         ret = eth_ixgbevf_dev_init(dev);
5133
5134         return ret;
5135 }
5136
5137 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5138 {
5139         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5140         struct ixgbe_vfta *shadow_vfta =
5141                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5142         int i = 0, j = 0, vfta = 0, mask = 1;
5143
5144         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5145                 vfta = shadow_vfta->vfta[i];
5146                 if (vfta) {
5147                         mask = 1;
5148                         for (j = 0; j < 32; j++) {
5149                                 if (vfta & mask)
5150                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5151                                                        on, false);
5152                                 mask <<= 1;
5153                         }
5154                 }
5155         }
5156
5157 }
5158
5159 static int
5160 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5161 {
5162         struct ixgbe_hw *hw =
5163                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5164         struct ixgbe_vfta *shadow_vfta =
5165                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5166         uint32_t vid_idx = 0;
5167         uint32_t vid_bit = 0;
5168         int ret = 0;
5169
5170         PMD_INIT_FUNC_TRACE();
5171
5172         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5173         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5174         if (ret) {
5175                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5176                 return ret;
5177         }
5178         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5179         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5180
5181         /* Save what we set and retore it after device reset */
5182         if (on)
5183                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5184         else
5185                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5186
5187         return 0;
5188 }
5189
5190 static void
5191 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5192 {
5193         struct ixgbe_hw *hw =
5194                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5195         uint32_t ctrl;
5196
5197         PMD_INIT_FUNC_TRACE();
5198
5199         if (queue >= hw->mac.max_rx_queues)
5200                 return;
5201
5202         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5203         if (on)
5204                 ctrl |= IXGBE_RXDCTL_VME;
5205         else
5206                 ctrl &= ~IXGBE_RXDCTL_VME;
5207         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5208
5209         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5210 }
5211
5212 static int
5213 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5214 {
5215         struct ixgbe_rx_queue *rxq;
5216         uint16_t i;
5217         int on = 0;
5218
5219         /* VF function only support hw strip feature, others are not support */
5220         if (mask & ETH_VLAN_STRIP_MASK) {
5221                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5222                         rxq = dev->data->rx_queues[i];
5223                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5224                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5225                 }
5226         }
5227
5228         return 0;
5229 }
5230
5231 int
5232 ixgbe_vt_check(struct ixgbe_hw *hw)
5233 {
5234         uint32_t reg_val;
5235
5236         /* if Virtualization Technology is enabled */
5237         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5238         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5239                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5240                 return -1;
5241         }
5242
5243         return 0;
5244 }
5245
5246 static uint32_t
5247 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5248 {
5249         uint32_t vector = 0;
5250
5251         switch (hw->mac.mc_filter_type) {
5252         case 0:   /* use bits [47:36] of the address */
5253                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5254                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5255                 break;
5256         case 1:   /* use bits [46:35] of the address */
5257                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5258                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5259                 break;
5260         case 2:   /* use bits [45:34] of the address */
5261                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5262                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5263                 break;
5264         case 3:   /* use bits [43:32] of the address */
5265                 vector = ((uc_addr->addr_bytes[4]) |
5266                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5267                 break;
5268         default:  /* Invalid mc_filter_type */
5269                 break;
5270         }
5271
5272         /* vector can only be 12-bits or boundary will be exceeded */
5273         vector &= 0xFFF;
5274         return vector;
5275 }
5276
5277 static int
5278 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5279                         uint8_t on)
5280 {
5281         uint32_t vector;
5282         uint32_t uta_idx;
5283         uint32_t reg_val;
5284         uint32_t uta_shift;
5285         uint32_t rc;
5286         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5287         const uint32_t ixgbe_uta_bit_shift = 5;
5288         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5289         const uint32_t bit1 = 0x1;
5290
5291         struct ixgbe_hw *hw =
5292                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5293         struct ixgbe_uta_info *uta_info =
5294                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5295
5296         /* The UTA table only exists on 82599 hardware and newer */
5297         if (hw->mac.type < ixgbe_mac_82599EB)
5298                 return -ENOTSUP;
5299
5300         vector = ixgbe_uta_vector(hw, mac_addr);
5301         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5302         uta_shift = vector & ixgbe_uta_bit_mask;
5303
5304         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5305         if (rc == on)
5306                 return 0;
5307
5308         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5309         if (on) {
5310                 uta_info->uta_in_use++;
5311                 reg_val |= (bit1 << uta_shift);
5312                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5313         } else {
5314                 uta_info->uta_in_use--;
5315                 reg_val &= ~(bit1 << uta_shift);
5316                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5317         }
5318
5319         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5320
5321         if (uta_info->uta_in_use > 0)
5322                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5323                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5324         else
5325                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5326
5327         return 0;
5328 }
5329
5330 static int
5331 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5332 {
5333         int i;
5334         struct ixgbe_hw *hw =
5335                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5336         struct ixgbe_uta_info *uta_info =
5337                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5338
5339         /* The UTA table only exists on 82599 hardware and newer */
5340         if (hw->mac.type < ixgbe_mac_82599EB)
5341                 return -ENOTSUP;
5342
5343         if (on) {
5344                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5345                         uta_info->uta_shadow[i] = ~0;
5346                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5347                 }
5348         } else {
5349                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5350                         uta_info->uta_shadow[i] = 0;
5351                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5352                 }
5353         }
5354         return 0;
5355
5356 }
5357
5358 uint32_t
5359 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5360 {
5361         uint32_t new_val = orig_val;
5362
5363         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5364                 new_val |= IXGBE_VMOLR_AUPE;
5365         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5366                 new_val |= IXGBE_VMOLR_ROMPE;
5367         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5368                 new_val |= IXGBE_VMOLR_ROPE;
5369         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5370                 new_val |= IXGBE_VMOLR_BAM;
5371         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5372                 new_val |= IXGBE_VMOLR_MPE;
5373
5374         return new_val;
5375 }
5376
5377 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5378 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5379 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5380 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5381 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5382         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5383         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5384
5385 static int
5386 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5387                       struct rte_eth_mirror_conf *mirror_conf,
5388                       uint8_t rule_id, uint8_t on)
5389 {
5390         uint32_t mr_ctl, vlvf;
5391         uint32_t mp_lsb = 0;
5392         uint32_t mv_msb = 0;
5393         uint32_t mv_lsb = 0;
5394         uint32_t mp_msb = 0;
5395         uint8_t i = 0;
5396         int reg_index = 0;
5397         uint64_t vlan_mask = 0;
5398
5399         const uint8_t pool_mask_offset = 32;
5400         const uint8_t vlan_mask_offset = 32;
5401         const uint8_t dst_pool_offset = 8;
5402         const uint8_t rule_mr_offset  = 4;
5403         const uint8_t mirror_rule_mask = 0x0F;
5404
5405         struct ixgbe_mirror_info *mr_info =
5406                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5407         struct ixgbe_hw *hw =
5408                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5409         uint8_t mirror_type = 0;
5410
5411         if (ixgbe_vt_check(hw) < 0)
5412                 return -ENOTSUP;
5413
5414         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5415                 return -EINVAL;
5416
5417         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5418                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5419                             mirror_conf->rule_type);
5420                 return -EINVAL;
5421         }
5422
5423         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5424                 mirror_type |= IXGBE_MRCTL_VLME;
5425                 /* Check if vlan id is valid and find conresponding VLAN ID
5426                  * index in VLVF
5427                  */
5428                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5429                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5430                                 /* search vlan id related pool vlan filter
5431                                  * index
5432                                  */
5433                                 reg_index = ixgbe_find_vlvf_slot(
5434                                                 hw,
5435                                                 mirror_conf->vlan.vlan_id[i],
5436                                                 false);
5437                                 if (reg_index < 0)
5438                                         return -EINVAL;
5439                                 vlvf = IXGBE_READ_REG(hw,
5440                                                       IXGBE_VLVF(reg_index));
5441                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5442                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5443                                       mirror_conf->vlan.vlan_id[i]))
5444                                         vlan_mask |= (1ULL << reg_index);
5445                                 else
5446                                         return -EINVAL;
5447                         }
5448                 }
5449
5450                 if (on) {
5451                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5452                         mv_msb = vlan_mask >> vlan_mask_offset;
5453
5454                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5455                                                 mirror_conf->vlan.vlan_mask;
5456                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5457                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5458                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5459                                                 mirror_conf->vlan.vlan_id[i];
5460                         }
5461                 } else {
5462                         mv_lsb = 0;
5463                         mv_msb = 0;
5464                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5465                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5466                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5467                 }
5468         }
5469
5470         /**
5471          * if enable pool mirror, write related pool mask register,if disable
5472          * pool mirror, clear PFMRVM register
5473          */
5474         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5475                 mirror_type |= IXGBE_MRCTL_VPME;
5476                 if (on) {
5477                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5478                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5479                         mr_info->mr_conf[rule_id].pool_mask =
5480                                         mirror_conf->pool_mask;
5481
5482                 } else {
5483                         mp_lsb = 0;
5484                         mp_msb = 0;
5485                         mr_info->mr_conf[rule_id].pool_mask = 0;
5486                 }
5487         }
5488         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5489                 mirror_type |= IXGBE_MRCTL_UPME;
5490         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5491                 mirror_type |= IXGBE_MRCTL_DPME;
5492
5493         /* read  mirror control register and recalculate it */
5494         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5495
5496         if (on) {
5497                 mr_ctl |= mirror_type;
5498                 mr_ctl &= mirror_rule_mask;
5499                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5500         } else {
5501                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5502         }
5503
5504         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5505         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5506
5507         /* write mirrror control  register */
5508         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5509
5510         /* write pool mirrror control  register */
5511         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5512                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5513                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5514                                 mp_msb);
5515         }
5516         /* write VLAN mirrror control  register */
5517         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5518                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5519                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5520                                 mv_msb);
5521         }
5522
5523         return 0;
5524 }
5525
5526 static int
5527 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5528 {
5529         int mr_ctl = 0;
5530         uint32_t lsb_val = 0;
5531         uint32_t msb_val = 0;
5532         const uint8_t rule_mr_offset = 4;
5533
5534         struct ixgbe_hw *hw =
5535                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5536         struct ixgbe_mirror_info *mr_info =
5537                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5538
5539         if (ixgbe_vt_check(hw) < 0)
5540                 return -ENOTSUP;
5541
5542         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5543                 return -EINVAL;
5544
5545         memset(&mr_info->mr_conf[rule_id], 0,
5546                sizeof(struct rte_eth_mirror_conf));
5547
5548         /* clear PFVMCTL register */
5549         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5550
5551         /* clear pool mask register */
5552         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5553         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5554
5555         /* clear vlan mask register */
5556         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5557         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5558
5559         return 0;
5560 }
5561
5562 static int
5563 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5564 {
5565         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5566         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5567         struct ixgbe_interrupt *intr =
5568                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5569         struct ixgbe_hw *hw =
5570                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5571         uint32_t vec = IXGBE_MISC_VEC_ID;
5572
5573         if (rte_intr_allow_others(intr_handle))
5574                 vec = IXGBE_RX_VEC_START;
5575         intr->mask |= (1 << vec);
5576         RTE_SET_USED(queue_id);
5577         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5578
5579         rte_intr_enable(intr_handle);
5580
5581         return 0;
5582 }
5583
5584 static int
5585 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5586 {
5587         struct ixgbe_interrupt *intr =
5588                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5589         struct ixgbe_hw *hw =
5590                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5591         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5592         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5593         uint32_t vec = IXGBE_MISC_VEC_ID;
5594
5595         if (rte_intr_allow_others(intr_handle))
5596                 vec = IXGBE_RX_VEC_START;
5597         intr->mask &= ~(1 << vec);
5598         RTE_SET_USED(queue_id);
5599         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5600
5601         return 0;
5602 }
5603
5604 static int
5605 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5606 {
5607         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5608         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5609         uint32_t mask;
5610         struct ixgbe_hw *hw =
5611                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5612         struct ixgbe_interrupt *intr =
5613                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5614
5615         if (queue_id < 16) {
5616                 ixgbe_disable_intr(hw);
5617                 intr->mask |= (1 << queue_id);
5618                 ixgbe_enable_intr(dev);
5619         } else if (queue_id < 32) {
5620                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5621                 mask &= (1 << queue_id);
5622                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5623         } else if (queue_id < 64) {
5624                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5625                 mask &= (1 << (queue_id - 32));
5626                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5627         }
5628         rte_intr_enable(intr_handle);
5629
5630         return 0;
5631 }
5632
5633 static int
5634 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5635 {
5636         uint32_t mask;
5637         struct ixgbe_hw *hw =
5638                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5639         struct ixgbe_interrupt *intr =
5640                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5641
5642         if (queue_id < 16) {
5643                 ixgbe_disable_intr(hw);
5644                 intr->mask &= ~(1 << queue_id);
5645                 ixgbe_enable_intr(dev);
5646         } else if (queue_id < 32) {
5647                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5648                 mask &= ~(1 << queue_id);
5649                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5650         } else if (queue_id < 64) {
5651                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5652                 mask &= ~(1 << (queue_id - 32));
5653                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5654         }
5655
5656         return 0;
5657 }
5658
5659 static void
5660 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5661                      uint8_t queue, uint8_t msix_vector)
5662 {
5663         uint32_t tmp, idx;
5664
5665         if (direction == -1) {
5666                 /* other causes */
5667                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5668                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5669                 tmp &= ~0xFF;
5670                 tmp |= msix_vector;
5671                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5672         } else {
5673                 /* rx or tx cause */
5674                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5675                 idx = ((16 * (queue & 1)) + (8 * direction));
5676                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5677                 tmp &= ~(0xFF << idx);
5678                 tmp |= (msix_vector << idx);
5679                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5680         }
5681 }
5682
5683 /**
5684  * set the IVAR registers, mapping interrupt causes to vectors
5685  * @param hw
5686  *  pointer to ixgbe_hw struct
5687  * @direction
5688  *  0 for Rx, 1 for Tx, -1 for other causes
5689  * @queue
5690  *  queue to map the corresponding interrupt to
5691  * @msix_vector
5692  *  the vector to map to the corresponding queue
5693  */
5694 static void
5695 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5696                    uint8_t queue, uint8_t msix_vector)
5697 {
5698         uint32_t tmp, idx;
5699
5700         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5701         if (hw->mac.type == ixgbe_mac_82598EB) {
5702                 if (direction == -1)
5703                         direction = 0;
5704                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5705                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5706                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5707                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5708                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5709         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5710                         (hw->mac.type == ixgbe_mac_X540) ||
5711                         (hw->mac.type == ixgbe_mac_X550)) {
5712                 if (direction == -1) {
5713                         /* other causes */
5714                         idx = ((queue & 1) * 8);
5715                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5716                         tmp &= ~(0xFF << idx);
5717                         tmp |= (msix_vector << idx);
5718                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5719                 } else {
5720                         /* rx or tx causes */
5721                         idx = ((16 * (queue & 1)) + (8 * direction));
5722                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5723                         tmp &= ~(0xFF << idx);
5724                         tmp |= (msix_vector << idx);
5725                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5726                 }
5727         }
5728 }
5729
5730 static void
5731 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5732 {
5733         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5734         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5735         struct ixgbe_hw *hw =
5736                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5737         uint32_t q_idx;
5738         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5739         uint32_t base = IXGBE_MISC_VEC_ID;
5740
5741         /* Configure VF other cause ivar */
5742         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5743
5744         /* won't configure msix register if no mapping is done
5745          * between intr vector and event fd.
5746          */
5747         if (!rte_intr_dp_is_en(intr_handle))
5748                 return;
5749
5750         if (rte_intr_allow_others(intr_handle)) {
5751                 base = IXGBE_RX_VEC_START;
5752                 vector_idx = IXGBE_RX_VEC_START;
5753         }
5754
5755         /* Configure all RX queues of VF */
5756         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5757                 /* Force all queue use vector 0,
5758                  * as IXGBE_VF_MAXMSIVECOTR = 1
5759                  */
5760                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5761                 intr_handle->intr_vec[q_idx] = vector_idx;
5762                 if (vector_idx < base + intr_handle->nb_efd - 1)
5763                         vector_idx++;
5764         }
5765
5766         /* As RX queue setting above show, all queues use the vector 0.
5767          * Set only the ITR value of IXGBE_MISC_VEC_ID.
5768          */
5769         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5770                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5771                         | IXGBE_EITR_CNT_WDIS);
5772 }
5773
5774 /**
5775  * Sets up the hardware to properly generate MSI-X interrupts
5776  * @hw
5777  *  board private structure
5778  */
5779 static void
5780 ixgbe_configure_msix(struct rte_eth_dev *dev)
5781 {
5782         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5783         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5784         struct ixgbe_hw *hw =
5785                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5786         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5787         uint32_t vec = IXGBE_MISC_VEC_ID;
5788         uint32_t mask;
5789         uint32_t gpie;
5790
5791         /* won't configure msix register if no mapping is done
5792          * between intr vector and event fd
5793          * but if misx has been enabled already, need to configure
5794          * auto clean, auto mask and throttling.
5795          */
5796         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5797         if (!rte_intr_dp_is_en(intr_handle) &&
5798             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
5799                 return;
5800
5801         if (rte_intr_allow_others(intr_handle))
5802                 vec = base = IXGBE_RX_VEC_START;
5803
5804         /* setup GPIE for MSI-x mode */
5805         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5806         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5807                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5808         /* auto clearing and auto setting corresponding bits in EIMS
5809          * when MSI-X interrupt is triggered
5810          */
5811         if (hw->mac.type == ixgbe_mac_82598EB) {
5812                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5813         } else {
5814                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5815                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5816         }
5817         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5818
5819         /* Populate the IVAR table and set the ITR values to the
5820          * corresponding register.
5821          */
5822         if (rte_intr_dp_is_en(intr_handle)) {
5823                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5824                         queue_id++) {
5825                         /* by default, 1:1 mapping */
5826                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5827                         intr_handle->intr_vec[queue_id] = vec;
5828                         if (vec < base + intr_handle->nb_efd - 1)
5829                                 vec++;
5830                 }
5831
5832                 switch (hw->mac.type) {
5833                 case ixgbe_mac_82598EB:
5834                         ixgbe_set_ivar_map(hw, -1,
5835                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
5836                                            IXGBE_MISC_VEC_ID);
5837                         break;
5838                 case ixgbe_mac_82599EB:
5839                 case ixgbe_mac_X540:
5840                 case ixgbe_mac_X550:
5841                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5842                         break;
5843                 default:
5844                         break;
5845                 }
5846         }
5847         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5848                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5849                         | IXGBE_EITR_CNT_WDIS);
5850
5851         /* set up to autoclear timer, and the vectors */
5852         mask = IXGBE_EIMS_ENABLE_MASK;
5853         mask &= ~(IXGBE_EIMS_OTHER |
5854                   IXGBE_EIMS_MAILBOX |
5855                   IXGBE_EIMS_LSC);
5856
5857         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5858 }
5859
5860 int
5861 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5862                            uint16_t queue_idx, uint16_t tx_rate)
5863 {
5864         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5865         struct rte_eth_rxmode *rxmode;
5866         uint32_t rf_dec, rf_int;
5867         uint32_t bcnrc_val;
5868         uint16_t link_speed = dev->data->dev_link.link_speed;
5869
5870         if (queue_idx >= hw->mac.max_tx_queues)
5871                 return -EINVAL;
5872
5873         if (tx_rate != 0) {
5874                 /* Calculate the rate factor values to set */
5875                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5876                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5877                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5878
5879                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5880                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5881                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5882                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5883         } else {
5884                 bcnrc_val = 0;
5885         }
5886
5887         rxmode = &dev->data->dev_conf.rxmode;
5888         /*
5889          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5890          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5891          * set as 0x4.
5892          */
5893         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
5894             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
5895                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5896                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5897         else
5898                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5899                         IXGBE_MMW_SIZE_DEFAULT);
5900
5901         /* Set RTTBCNRC of queue X */
5902         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5903         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5904         IXGBE_WRITE_FLUSH(hw);
5905
5906         return 0;
5907 }
5908
5909 static int
5910 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5911                      __attribute__((unused)) uint32_t index,
5912                      __attribute__((unused)) uint32_t pool)
5913 {
5914         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5915         int diag;
5916
5917         /*
5918          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5919          * operation. Trap this case to avoid exhausting the [very limited]
5920          * set of PF resources used to store VF MAC addresses.
5921          */
5922         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5923                 return -1;
5924         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5925         if (diag != 0)
5926                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5927                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5928                             mac_addr->addr_bytes[0],
5929                             mac_addr->addr_bytes[1],
5930                             mac_addr->addr_bytes[2],
5931                             mac_addr->addr_bytes[3],
5932                             mac_addr->addr_bytes[4],
5933                             mac_addr->addr_bytes[5],
5934                             diag);
5935         return diag;
5936 }
5937
5938 static void
5939 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5940 {
5941         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5942         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5943         struct ether_addr *mac_addr;
5944         uint32_t i;
5945         int diag;
5946
5947         /*
5948          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5949          * not support the deletion of a given MAC address.
5950          * Instead, it imposes to delete all MAC addresses, then to add again
5951          * all MAC addresses with the exception of the one to be deleted.
5952          */
5953         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5954
5955         /*
5956          * Add again all MAC addresses, with the exception of the deleted one
5957          * and of the permanent MAC address.
5958          */
5959         for (i = 0, mac_addr = dev->data->mac_addrs;
5960              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5961                 /* Skip the deleted MAC address */
5962                 if (i == index)
5963                         continue;
5964                 /* Skip NULL MAC addresses */
5965                 if (is_zero_ether_addr(mac_addr))
5966                         continue;
5967                 /* Skip the permanent MAC address */
5968                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5969                         continue;
5970                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5971                 if (diag != 0)
5972                         PMD_DRV_LOG(ERR,
5973                                     "Adding again MAC address "
5974                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5975                                     "diag=%d",
5976                                     mac_addr->addr_bytes[0],
5977                                     mac_addr->addr_bytes[1],
5978                                     mac_addr->addr_bytes[2],
5979                                     mac_addr->addr_bytes[3],
5980                                     mac_addr->addr_bytes[4],
5981                                     mac_addr->addr_bytes[5],
5982                                     diag);
5983         }
5984 }
5985
5986 static int
5987 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5988 {
5989         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5990
5991         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5992
5993         return 0;
5994 }
5995
5996 int
5997 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5998                         struct rte_eth_syn_filter *filter,
5999                         bool add)
6000 {
6001         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6002         struct ixgbe_filter_info *filter_info =
6003                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6004         uint32_t syn_info;
6005         uint32_t synqf;
6006
6007         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6008                 return -EINVAL;
6009
6010         syn_info = filter_info->syn_info;
6011
6012         if (add) {
6013                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6014                         return -EINVAL;
6015                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6016                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6017
6018                 if (filter->hig_pri)
6019                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6020                 else
6021                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6022         } else {
6023                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6024                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6025                         return -ENOENT;
6026                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6027         }
6028
6029         filter_info->syn_info = synqf;
6030         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6031         IXGBE_WRITE_FLUSH(hw);
6032         return 0;
6033 }
6034
6035 static int
6036 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6037                         struct rte_eth_syn_filter *filter)
6038 {
6039         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6040         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6041
6042         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6043                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6044                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6045                 return 0;
6046         }
6047         return -ENOENT;
6048 }
6049
6050 static int
6051 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6052                         enum rte_filter_op filter_op,
6053                         void *arg)
6054 {
6055         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6056         int ret;
6057
6058         MAC_TYPE_FILTER_SUP(hw->mac.type);
6059
6060         if (filter_op == RTE_ETH_FILTER_NOP)
6061                 return 0;
6062
6063         if (arg == NULL) {
6064                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6065                             filter_op);
6066                 return -EINVAL;
6067         }
6068
6069         switch (filter_op) {
6070         case RTE_ETH_FILTER_ADD:
6071                 ret = ixgbe_syn_filter_set(dev,
6072                                 (struct rte_eth_syn_filter *)arg,
6073                                 TRUE);
6074                 break;
6075         case RTE_ETH_FILTER_DELETE:
6076                 ret = ixgbe_syn_filter_set(dev,
6077                                 (struct rte_eth_syn_filter *)arg,
6078                                 FALSE);
6079                 break;
6080         case RTE_ETH_FILTER_GET:
6081                 ret = ixgbe_syn_filter_get(dev,
6082                                 (struct rte_eth_syn_filter *)arg);
6083                 break;
6084         default:
6085                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6086                 ret = -EINVAL;
6087                 break;
6088         }
6089
6090         return ret;
6091 }
6092
6093
6094 static inline enum ixgbe_5tuple_protocol
6095 convert_protocol_type(uint8_t protocol_value)
6096 {
6097         if (protocol_value == IPPROTO_TCP)
6098                 return IXGBE_FILTER_PROTOCOL_TCP;
6099         else if (protocol_value == IPPROTO_UDP)
6100                 return IXGBE_FILTER_PROTOCOL_UDP;
6101         else if (protocol_value == IPPROTO_SCTP)
6102                 return IXGBE_FILTER_PROTOCOL_SCTP;
6103         else
6104                 return IXGBE_FILTER_PROTOCOL_NONE;
6105 }
6106
6107 /* inject a 5-tuple filter to HW */
6108 static inline void
6109 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6110                            struct ixgbe_5tuple_filter *filter)
6111 {
6112         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6113         int i;
6114         uint32_t ftqf, sdpqf;
6115         uint32_t l34timir = 0;
6116         uint8_t mask = 0xff;
6117
6118         i = filter->index;
6119
6120         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6121                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6122         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6123
6124         ftqf = (uint32_t)(filter->filter_info.proto &
6125                 IXGBE_FTQF_PROTOCOL_MASK);
6126         ftqf |= (uint32_t)((filter->filter_info.priority &
6127                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6128         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6129                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6130         if (filter->filter_info.dst_ip_mask == 0)
6131                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6132         if (filter->filter_info.src_port_mask == 0)
6133                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6134         if (filter->filter_info.dst_port_mask == 0)
6135                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6136         if (filter->filter_info.proto_mask == 0)
6137                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6138         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6139         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6140         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6141
6142         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6143         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6144         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6145         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6146
6147         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6148         l34timir |= (uint32_t)(filter->queue <<
6149                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6150         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6151 }
6152
6153 /*
6154  * add a 5tuple filter
6155  *
6156  * @param
6157  * dev: Pointer to struct rte_eth_dev.
6158  * index: the index the filter allocates.
6159  * filter: ponter to the filter that will be added.
6160  * rx_queue: the queue id the filter assigned to.
6161  *
6162  * @return
6163  *    - On success, zero.
6164  *    - On failure, a negative value.
6165  */
6166 static int
6167 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6168                         struct ixgbe_5tuple_filter *filter)
6169 {
6170         struct ixgbe_filter_info *filter_info =
6171                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6172         int i, idx, shift;
6173
6174         /*
6175          * look for an unused 5tuple filter index,
6176          * and insert the filter to list.
6177          */
6178         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6179                 idx = i / (sizeof(uint32_t) * NBBY);
6180                 shift = i % (sizeof(uint32_t) * NBBY);
6181                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6182                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6183                         filter->index = i;
6184                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6185                                           filter,
6186                                           entries);
6187                         break;
6188                 }
6189         }
6190         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6191                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6192                 return -ENOSYS;
6193         }
6194
6195         ixgbe_inject_5tuple_filter(dev, filter);
6196
6197         return 0;
6198 }
6199
6200 /*
6201  * remove a 5tuple filter
6202  *
6203  * @param
6204  * dev: Pointer to struct rte_eth_dev.
6205  * filter: the pointer of the filter will be removed.
6206  */
6207 static void
6208 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6209                         struct ixgbe_5tuple_filter *filter)
6210 {
6211         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6212         struct ixgbe_filter_info *filter_info =
6213                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6214         uint16_t index = filter->index;
6215
6216         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6217                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6218         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6219         rte_free(filter);
6220
6221         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6222         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6223         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6224         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6225         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6226 }
6227
6228 static int
6229 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6230 {
6231         struct ixgbe_hw *hw;
6232         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6233         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6234
6235         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6236
6237         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6238                 return -EINVAL;
6239
6240         /* refuse mtu that requires the support of scattered packets when this
6241          * feature has not been enabled before.
6242          */
6243         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6244             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6245              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6246                 return -EINVAL;
6247
6248         /*
6249          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6250          * request of the version 2.0 of the mailbox API.
6251          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6252          * of the mailbox API.
6253          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6254          * prior to 3.11.33 which contains the following change:
6255          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6256          */
6257         ixgbevf_rlpml_set_vf(hw, max_frame);
6258
6259         /* update max frame size */
6260         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6261         return 0;
6262 }
6263
6264 static inline struct ixgbe_5tuple_filter *
6265 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6266                         struct ixgbe_5tuple_filter_info *key)
6267 {
6268         struct ixgbe_5tuple_filter *it;
6269
6270         TAILQ_FOREACH(it, filter_list, entries) {
6271                 if (memcmp(key, &it->filter_info,
6272                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6273                         return it;
6274                 }
6275         }
6276         return NULL;
6277 }
6278
6279 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6280 static inline int
6281 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6282                         struct ixgbe_5tuple_filter_info *filter_info)
6283 {
6284         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6285                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6286                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6287                 return -EINVAL;
6288
6289         switch (filter->dst_ip_mask) {
6290         case UINT32_MAX:
6291                 filter_info->dst_ip_mask = 0;
6292                 filter_info->dst_ip = filter->dst_ip;
6293                 break;
6294         case 0:
6295                 filter_info->dst_ip_mask = 1;
6296                 break;
6297         default:
6298                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6299                 return -EINVAL;
6300         }
6301
6302         switch (filter->src_ip_mask) {
6303         case UINT32_MAX:
6304                 filter_info->src_ip_mask = 0;
6305                 filter_info->src_ip = filter->src_ip;
6306                 break;
6307         case 0:
6308                 filter_info->src_ip_mask = 1;
6309                 break;
6310         default:
6311                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6312                 return -EINVAL;
6313         }
6314
6315         switch (filter->dst_port_mask) {
6316         case UINT16_MAX:
6317                 filter_info->dst_port_mask = 0;
6318                 filter_info->dst_port = filter->dst_port;
6319                 break;
6320         case 0:
6321                 filter_info->dst_port_mask = 1;
6322                 break;
6323         default:
6324                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6325                 return -EINVAL;
6326         }
6327
6328         switch (filter->src_port_mask) {
6329         case UINT16_MAX:
6330                 filter_info->src_port_mask = 0;
6331                 filter_info->src_port = filter->src_port;
6332                 break;
6333         case 0:
6334                 filter_info->src_port_mask = 1;
6335                 break;
6336         default:
6337                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6338                 return -EINVAL;
6339         }
6340
6341         switch (filter->proto_mask) {
6342         case UINT8_MAX:
6343                 filter_info->proto_mask = 0;
6344                 filter_info->proto =
6345                         convert_protocol_type(filter->proto);
6346                 break;
6347         case 0:
6348                 filter_info->proto_mask = 1;
6349                 break;
6350         default:
6351                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6352                 return -EINVAL;
6353         }
6354
6355         filter_info->priority = (uint8_t)filter->priority;
6356         return 0;
6357 }
6358
6359 /*
6360  * add or delete a ntuple filter
6361  *
6362  * @param
6363  * dev: Pointer to struct rte_eth_dev.
6364  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6365  * add: if true, add filter, if false, remove filter
6366  *
6367  * @return
6368  *    - On success, zero.
6369  *    - On failure, a negative value.
6370  */
6371 int
6372 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6373                         struct rte_eth_ntuple_filter *ntuple_filter,
6374                         bool add)
6375 {
6376         struct ixgbe_filter_info *filter_info =
6377                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6378         struct ixgbe_5tuple_filter_info filter_5tuple;
6379         struct ixgbe_5tuple_filter *filter;
6380         int ret;
6381
6382         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6383                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6384                 return -EINVAL;
6385         }
6386
6387         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6388         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6389         if (ret < 0)
6390                 return ret;
6391
6392         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6393                                          &filter_5tuple);
6394         if (filter != NULL && add) {
6395                 PMD_DRV_LOG(ERR, "filter exists.");
6396                 return -EEXIST;
6397         }
6398         if (filter == NULL && !add) {
6399                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6400                 return -ENOENT;
6401         }
6402
6403         if (add) {
6404                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6405                                 sizeof(struct ixgbe_5tuple_filter), 0);
6406                 if (filter == NULL)
6407                         return -ENOMEM;
6408                 rte_memcpy(&filter->filter_info,
6409                                  &filter_5tuple,
6410                                  sizeof(struct ixgbe_5tuple_filter_info));
6411                 filter->queue = ntuple_filter->queue;
6412                 ret = ixgbe_add_5tuple_filter(dev, filter);
6413                 if (ret < 0) {
6414                         rte_free(filter);
6415                         return ret;
6416                 }
6417         } else
6418                 ixgbe_remove_5tuple_filter(dev, filter);
6419
6420         return 0;
6421 }
6422
6423 /*
6424  * get a ntuple filter
6425  *
6426  * @param
6427  * dev: Pointer to struct rte_eth_dev.
6428  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6429  *
6430  * @return
6431  *    - On success, zero.
6432  *    - On failure, a negative value.
6433  */
6434 static int
6435 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6436                         struct rte_eth_ntuple_filter *ntuple_filter)
6437 {
6438         struct ixgbe_filter_info *filter_info =
6439                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6440         struct ixgbe_5tuple_filter_info filter_5tuple;
6441         struct ixgbe_5tuple_filter *filter;
6442         int ret;
6443
6444         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6445                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6446                 return -EINVAL;
6447         }
6448
6449         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6450         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6451         if (ret < 0)
6452                 return ret;
6453
6454         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6455                                          &filter_5tuple);
6456         if (filter == NULL) {
6457                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6458                 return -ENOENT;
6459         }
6460         ntuple_filter->queue = filter->queue;
6461         return 0;
6462 }
6463
6464 /*
6465  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6466  * @dev: pointer to rte_eth_dev structure
6467  * @filter_op:operation will be taken.
6468  * @arg: a pointer to specific structure corresponding to the filter_op
6469  *
6470  * @return
6471  *    - On success, zero.
6472  *    - On failure, a negative value.
6473  */
6474 static int
6475 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6476                                 enum rte_filter_op filter_op,
6477                                 void *arg)
6478 {
6479         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6480         int ret;
6481
6482         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6483
6484         if (filter_op == RTE_ETH_FILTER_NOP)
6485                 return 0;
6486
6487         if (arg == NULL) {
6488                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6489                             filter_op);
6490                 return -EINVAL;
6491         }
6492
6493         switch (filter_op) {
6494         case RTE_ETH_FILTER_ADD:
6495                 ret = ixgbe_add_del_ntuple_filter(dev,
6496                         (struct rte_eth_ntuple_filter *)arg,
6497                         TRUE);
6498                 break;
6499         case RTE_ETH_FILTER_DELETE:
6500                 ret = ixgbe_add_del_ntuple_filter(dev,
6501                         (struct rte_eth_ntuple_filter *)arg,
6502                         FALSE);
6503                 break;
6504         case RTE_ETH_FILTER_GET:
6505                 ret = ixgbe_get_ntuple_filter(dev,
6506                         (struct rte_eth_ntuple_filter *)arg);
6507                 break;
6508         default:
6509                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6510                 ret = -EINVAL;
6511                 break;
6512         }
6513         return ret;
6514 }
6515
6516 int
6517 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6518                         struct rte_eth_ethertype_filter *filter,
6519                         bool add)
6520 {
6521         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6522         struct ixgbe_filter_info *filter_info =
6523                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6524         uint32_t etqf = 0;
6525         uint32_t etqs = 0;
6526         int ret;
6527         struct ixgbe_ethertype_filter ethertype_filter;
6528
6529         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6530                 return -EINVAL;
6531
6532         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6533                 filter->ether_type == ETHER_TYPE_IPv6) {
6534                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6535                         " ethertype filter.", filter->ether_type);
6536                 return -EINVAL;
6537         }
6538
6539         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6540                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6541                 return -EINVAL;
6542         }
6543         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6544                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6545                 return -EINVAL;
6546         }
6547
6548         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6549         if (ret >= 0 && add) {
6550                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6551                             filter->ether_type);
6552                 return -EEXIST;
6553         }
6554         if (ret < 0 && !add) {
6555                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6556                             filter->ether_type);
6557                 return -ENOENT;
6558         }
6559
6560         if (add) {
6561                 etqf = IXGBE_ETQF_FILTER_EN;
6562                 etqf |= (uint32_t)filter->ether_type;
6563                 etqs |= (uint32_t)((filter->queue <<
6564                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6565                                     IXGBE_ETQS_RX_QUEUE);
6566                 etqs |= IXGBE_ETQS_QUEUE_EN;
6567
6568                 ethertype_filter.ethertype = filter->ether_type;
6569                 ethertype_filter.etqf = etqf;
6570                 ethertype_filter.etqs = etqs;
6571                 ethertype_filter.conf = FALSE;
6572                 ret = ixgbe_ethertype_filter_insert(filter_info,
6573                                                     &ethertype_filter);
6574                 if (ret < 0) {
6575                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6576                         return -ENOSPC;
6577                 }
6578         } else {
6579                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6580                 if (ret < 0)
6581                         return -ENOSYS;
6582         }
6583         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6584         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6585         IXGBE_WRITE_FLUSH(hw);
6586
6587         return 0;
6588 }
6589
6590 static int
6591 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6592                         struct rte_eth_ethertype_filter *filter)
6593 {
6594         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6595         struct ixgbe_filter_info *filter_info =
6596                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6597         uint32_t etqf, etqs;
6598         int ret;
6599
6600         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6601         if (ret < 0) {
6602                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6603                             filter->ether_type);
6604                 return -ENOENT;
6605         }
6606
6607         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6608         if (etqf & IXGBE_ETQF_FILTER_EN) {
6609                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6610                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6611                 filter->flags = 0;
6612                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6613                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6614                 return 0;
6615         }
6616         return -ENOENT;
6617 }
6618
6619 /*
6620  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6621  * @dev: pointer to rte_eth_dev structure
6622  * @filter_op:operation will be taken.
6623  * @arg: a pointer to specific structure corresponding to the filter_op
6624  */
6625 static int
6626 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6627                                 enum rte_filter_op filter_op,
6628                                 void *arg)
6629 {
6630         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6631         int ret;
6632
6633         MAC_TYPE_FILTER_SUP(hw->mac.type);
6634
6635         if (filter_op == RTE_ETH_FILTER_NOP)
6636                 return 0;
6637
6638         if (arg == NULL) {
6639                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6640                             filter_op);
6641                 return -EINVAL;
6642         }
6643
6644         switch (filter_op) {
6645         case RTE_ETH_FILTER_ADD:
6646                 ret = ixgbe_add_del_ethertype_filter(dev,
6647                         (struct rte_eth_ethertype_filter *)arg,
6648                         TRUE);
6649                 break;
6650         case RTE_ETH_FILTER_DELETE:
6651                 ret = ixgbe_add_del_ethertype_filter(dev,
6652                         (struct rte_eth_ethertype_filter *)arg,
6653                         FALSE);
6654                 break;
6655         case RTE_ETH_FILTER_GET:
6656                 ret = ixgbe_get_ethertype_filter(dev,
6657                         (struct rte_eth_ethertype_filter *)arg);
6658                 break;
6659         default:
6660                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6661                 ret = -EINVAL;
6662                 break;
6663         }
6664         return ret;
6665 }
6666
6667 static int
6668 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6669                      enum rte_filter_type filter_type,
6670                      enum rte_filter_op filter_op,
6671                      void *arg)
6672 {
6673         int ret = 0;
6674
6675         switch (filter_type) {
6676         case RTE_ETH_FILTER_NTUPLE:
6677                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6678                 break;
6679         case RTE_ETH_FILTER_ETHERTYPE:
6680                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6681                 break;
6682         case RTE_ETH_FILTER_SYN:
6683                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6684                 break;
6685         case RTE_ETH_FILTER_FDIR:
6686                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6687                 break;
6688         case RTE_ETH_FILTER_L2_TUNNEL:
6689                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6690                 break;
6691         case RTE_ETH_FILTER_GENERIC:
6692                 if (filter_op != RTE_ETH_FILTER_GET)
6693                         return -EINVAL;
6694                 *(const void **)arg = &ixgbe_flow_ops;
6695                 break;
6696         default:
6697                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6698                                                         filter_type);
6699                 ret = -EINVAL;
6700                 break;
6701         }
6702
6703         return ret;
6704 }
6705
6706 static u8 *
6707 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6708                         u8 **mc_addr_ptr, u32 *vmdq)
6709 {
6710         u8 *mc_addr;
6711
6712         *vmdq = 0;
6713         mc_addr = *mc_addr_ptr;
6714         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6715         return mc_addr;
6716 }
6717
6718 static int
6719 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6720                           struct ether_addr *mc_addr_set,
6721                           uint32_t nb_mc_addr)
6722 {
6723         struct ixgbe_hw *hw;
6724         u8 *mc_addr_list;
6725
6726         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6727         mc_addr_list = (u8 *)mc_addr_set;
6728         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6729                                          ixgbe_dev_addr_list_itr, TRUE);
6730 }
6731
6732 static uint64_t
6733 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6734 {
6735         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6736         uint64_t systime_cycles;
6737
6738         switch (hw->mac.type) {
6739         case ixgbe_mac_X550:
6740         case ixgbe_mac_X550EM_x:
6741         case ixgbe_mac_X550EM_a:
6742                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6743                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6744                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6745                                 * NSEC_PER_SEC;
6746                 break;
6747         default:
6748                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6749                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6750                                 << 32;
6751         }
6752
6753         return systime_cycles;
6754 }
6755
6756 static uint64_t
6757 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6758 {
6759         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6760         uint64_t rx_tstamp_cycles;
6761
6762         switch (hw->mac.type) {
6763         case ixgbe_mac_X550:
6764         case ixgbe_mac_X550EM_x:
6765         case ixgbe_mac_X550EM_a:
6766                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6767                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6768                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6769                                 * NSEC_PER_SEC;
6770                 break;
6771         default:
6772                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6773                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6774                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6775                                 << 32;
6776         }
6777
6778         return rx_tstamp_cycles;
6779 }
6780
6781 static uint64_t
6782 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6783 {
6784         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6785         uint64_t tx_tstamp_cycles;
6786
6787         switch (hw->mac.type) {
6788         case ixgbe_mac_X550:
6789         case ixgbe_mac_X550EM_x:
6790         case ixgbe_mac_X550EM_a:
6791                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6792                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6793                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6794                                 * NSEC_PER_SEC;
6795                 break;
6796         default:
6797                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6798                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6799                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6800                                 << 32;
6801         }
6802
6803         return tx_tstamp_cycles;
6804 }
6805
6806 static void
6807 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6808 {
6809         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6810         struct ixgbe_adapter *adapter =
6811                 (struct ixgbe_adapter *)dev->data->dev_private;
6812         struct rte_eth_link link;
6813         uint32_t incval = 0;
6814         uint32_t shift = 0;
6815
6816         /* Get current link speed. */
6817         ixgbe_dev_link_update(dev, 1);
6818         rte_eth_linkstatus_get(dev, &link);
6819
6820         switch (link.link_speed) {
6821         case ETH_SPEED_NUM_100M:
6822                 incval = IXGBE_INCVAL_100;
6823                 shift = IXGBE_INCVAL_SHIFT_100;
6824                 break;
6825         case ETH_SPEED_NUM_1G:
6826                 incval = IXGBE_INCVAL_1GB;
6827                 shift = IXGBE_INCVAL_SHIFT_1GB;
6828                 break;
6829         case ETH_SPEED_NUM_10G:
6830         default:
6831                 incval = IXGBE_INCVAL_10GB;
6832                 shift = IXGBE_INCVAL_SHIFT_10GB;
6833                 break;
6834         }
6835
6836         switch (hw->mac.type) {
6837         case ixgbe_mac_X550:
6838         case ixgbe_mac_X550EM_x:
6839         case ixgbe_mac_X550EM_a:
6840                 /* Independent of link speed. */
6841                 incval = 1;
6842                 /* Cycles read will be interpreted as ns. */
6843                 shift = 0;
6844                 /* Fall-through */
6845         case ixgbe_mac_X540:
6846                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6847                 break;
6848         case ixgbe_mac_82599EB:
6849                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6850                 shift -= IXGBE_INCVAL_SHIFT_82599;
6851                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6852                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6853                 break;
6854         default:
6855                 /* Not supported. */
6856                 return;
6857         }
6858
6859         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6860         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6861         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6862
6863         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6864         adapter->systime_tc.cc_shift = shift;
6865         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6866
6867         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6868         adapter->rx_tstamp_tc.cc_shift = shift;
6869         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6870
6871         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6872         adapter->tx_tstamp_tc.cc_shift = shift;
6873         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6874 }
6875
6876 static int
6877 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6878 {
6879         struct ixgbe_adapter *adapter =
6880                         (struct ixgbe_adapter *)dev->data->dev_private;
6881
6882         adapter->systime_tc.nsec += delta;
6883         adapter->rx_tstamp_tc.nsec += delta;
6884         adapter->tx_tstamp_tc.nsec += delta;
6885
6886         return 0;
6887 }
6888
6889 static int
6890 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6891 {
6892         uint64_t ns;
6893         struct ixgbe_adapter *adapter =
6894                         (struct ixgbe_adapter *)dev->data->dev_private;
6895
6896         ns = rte_timespec_to_ns(ts);
6897         /* Set the timecounters to a new value. */
6898         adapter->systime_tc.nsec = ns;
6899         adapter->rx_tstamp_tc.nsec = ns;
6900         adapter->tx_tstamp_tc.nsec = ns;
6901
6902         return 0;
6903 }
6904
6905 static int
6906 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6907 {
6908         uint64_t ns, systime_cycles;
6909         struct ixgbe_adapter *adapter =
6910                         (struct ixgbe_adapter *)dev->data->dev_private;
6911
6912         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6913         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6914         *ts = rte_ns_to_timespec(ns);
6915
6916         return 0;
6917 }
6918
6919 static int
6920 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6921 {
6922         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6923         uint32_t tsync_ctl;
6924         uint32_t tsauxc;
6925
6926         /* Stop the timesync system time. */
6927         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6928         /* Reset the timesync system time value. */
6929         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6930         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6931
6932         /* Enable system time for platforms where it isn't on by default. */
6933         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6934         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6935         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6936
6937         ixgbe_start_timecounters(dev);
6938
6939         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6940         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6941                         (ETHER_TYPE_1588 |
6942                          IXGBE_ETQF_FILTER_EN |
6943                          IXGBE_ETQF_1588));
6944
6945         /* Enable timestamping of received PTP packets. */
6946         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6947         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6948         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6949
6950         /* Enable timestamping of transmitted PTP packets. */
6951         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6952         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6953         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6954
6955         IXGBE_WRITE_FLUSH(hw);
6956
6957         return 0;
6958 }
6959
6960 static int
6961 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6962 {
6963         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6964         uint32_t tsync_ctl;
6965
6966         /* Disable timestamping of transmitted PTP packets. */
6967         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6968         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6969         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6970
6971         /* Disable timestamping of received PTP packets. */
6972         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6973         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6974         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6975
6976         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6977         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6978
6979         /* Stop incrementating the System Time registers. */
6980         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6981
6982         return 0;
6983 }
6984
6985 static int
6986 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6987                                  struct timespec *timestamp,
6988                                  uint32_t flags __rte_unused)
6989 {
6990         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6991         struct ixgbe_adapter *adapter =
6992                 (struct ixgbe_adapter *)dev->data->dev_private;
6993         uint32_t tsync_rxctl;
6994         uint64_t rx_tstamp_cycles;
6995         uint64_t ns;
6996
6997         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6998         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6999                 return -EINVAL;
7000
7001         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7002         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7003         *timestamp = rte_ns_to_timespec(ns);
7004
7005         return  0;
7006 }
7007
7008 static int
7009 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7010                                  struct timespec *timestamp)
7011 {
7012         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7013         struct ixgbe_adapter *adapter =
7014                 (struct ixgbe_adapter *)dev->data->dev_private;
7015         uint32_t tsync_txctl;
7016         uint64_t tx_tstamp_cycles;
7017         uint64_t ns;
7018
7019         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7020         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7021                 return -EINVAL;
7022
7023         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7024         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7025         *timestamp = rte_ns_to_timespec(ns);
7026
7027         return 0;
7028 }
7029
7030 static int
7031 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7032 {
7033         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7034         int count = 0;
7035         int g_ind = 0;
7036         const struct reg_info *reg_group;
7037         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7038                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7039
7040         while ((reg_group = reg_set[g_ind++]))
7041                 count += ixgbe_regs_group_count(reg_group);
7042
7043         return count;
7044 }
7045
7046 static int
7047 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7048 {
7049         int count = 0;
7050         int g_ind = 0;
7051         const struct reg_info *reg_group;
7052
7053         while ((reg_group = ixgbevf_regs[g_ind++]))
7054                 count += ixgbe_regs_group_count(reg_group);
7055
7056         return count;
7057 }
7058
7059 static int
7060 ixgbe_get_regs(struct rte_eth_dev *dev,
7061               struct rte_dev_reg_info *regs)
7062 {
7063         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7064         uint32_t *data = regs->data;
7065         int g_ind = 0;
7066         int count = 0;
7067         const struct reg_info *reg_group;
7068         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7069                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7070
7071         if (data == NULL) {
7072                 regs->length = ixgbe_get_reg_length(dev);
7073                 regs->width = sizeof(uint32_t);
7074                 return 0;
7075         }
7076
7077         /* Support only full register dump */
7078         if ((regs->length == 0) ||
7079             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7080                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7081                         hw->device_id;
7082                 while ((reg_group = reg_set[g_ind++]))
7083                         count += ixgbe_read_regs_group(dev, &data[count],
7084                                 reg_group);
7085                 return 0;
7086         }
7087
7088         return -ENOTSUP;
7089 }
7090
7091 static int
7092 ixgbevf_get_regs(struct rte_eth_dev *dev,
7093                 struct rte_dev_reg_info *regs)
7094 {
7095         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7096         uint32_t *data = regs->data;
7097         int g_ind = 0;
7098         int count = 0;
7099         const struct reg_info *reg_group;
7100
7101         if (data == NULL) {
7102                 regs->length = ixgbevf_get_reg_length(dev);
7103                 regs->width = sizeof(uint32_t);
7104                 return 0;
7105         }
7106
7107         /* Support only full register dump */
7108         if ((regs->length == 0) ||
7109             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7110                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7111                         hw->device_id;
7112                 while ((reg_group = ixgbevf_regs[g_ind++]))
7113                         count += ixgbe_read_regs_group(dev, &data[count],
7114                                                       reg_group);
7115                 return 0;
7116         }
7117
7118         return -ENOTSUP;
7119 }
7120
7121 static int
7122 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7123 {
7124         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7125
7126         /* Return unit is byte count */
7127         return hw->eeprom.word_size * 2;
7128 }
7129
7130 static int
7131 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7132                 struct rte_dev_eeprom_info *in_eeprom)
7133 {
7134         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7135         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7136         uint16_t *data = in_eeprom->data;
7137         int first, length;
7138
7139         first = in_eeprom->offset >> 1;
7140         length = in_eeprom->length >> 1;
7141         if ((first > hw->eeprom.word_size) ||
7142             ((first + length) > hw->eeprom.word_size))
7143                 return -EINVAL;
7144
7145         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7146
7147         return eeprom->ops.read_buffer(hw, first, length, data);
7148 }
7149
7150 static int
7151 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7152                 struct rte_dev_eeprom_info *in_eeprom)
7153 {
7154         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7155         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7156         uint16_t *data = in_eeprom->data;
7157         int first, length;
7158
7159         first = in_eeprom->offset >> 1;
7160         length = in_eeprom->length >> 1;
7161         if ((first > hw->eeprom.word_size) ||
7162             ((first + length) > hw->eeprom.word_size))
7163                 return -EINVAL;
7164
7165         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7166
7167         return eeprom->ops.write_buffer(hw,  first, length, data);
7168 }
7169
7170 static int
7171 ixgbe_get_module_info(struct rte_eth_dev *dev,
7172                       struct rte_eth_dev_module_info *modinfo)
7173 {
7174         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7175         uint32_t status;
7176         uint8_t sff8472_rev, addr_mode;
7177         bool page_swap = false;
7178
7179         /* Check whether we support SFF-8472 or not */
7180         status = hw->phy.ops.read_i2c_eeprom(hw,
7181                                              IXGBE_SFF_SFF_8472_COMP,
7182                                              &sff8472_rev);
7183         if (status != 0)
7184                 return -EIO;
7185
7186         /* addressing mode is not supported */
7187         status = hw->phy.ops.read_i2c_eeprom(hw,
7188                                              IXGBE_SFF_SFF_8472_SWAP,
7189                                              &addr_mode);
7190         if (status != 0)
7191                 return -EIO;
7192
7193         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7194                 PMD_DRV_LOG(ERR,
7195                             "Address change required to access page 0xA2, "
7196                             "but not supported. Please report the module "
7197                             "type to the driver maintainers.");
7198                 page_swap = true;
7199         }
7200
7201         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7202                 /* We have a SFP, but it does not support SFF-8472 */
7203                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7204                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7205         } else {
7206                 /* We have a SFP which supports a revision of SFF-8472. */
7207                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7208                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7209         }
7210
7211         return 0;
7212 }
7213
7214 static int
7215 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7216                         struct rte_dev_eeprom_info *info)
7217 {
7218         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7219         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7220         uint8_t databyte = 0xFF;
7221         uint8_t *data = info->data;
7222         uint32_t i = 0;
7223
7224         if (info->length == 0)
7225                 return -EINVAL;
7226
7227         for (i = info->offset; i < info->offset + info->length; i++) {
7228                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7229                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7230                 else
7231                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7232
7233                 if (status != 0)
7234                         return -EIO;
7235
7236                 data[i - info->offset] = databyte;
7237         }
7238
7239         return 0;
7240 }
7241
7242 uint16_t
7243 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7244         switch (mac_type) {
7245         case ixgbe_mac_X550:
7246         case ixgbe_mac_X550EM_x:
7247         case ixgbe_mac_X550EM_a:
7248                 return ETH_RSS_RETA_SIZE_512;
7249         case ixgbe_mac_X550_vf:
7250         case ixgbe_mac_X550EM_x_vf:
7251         case ixgbe_mac_X550EM_a_vf:
7252                 return ETH_RSS_RETA_SIZE_64;
7253         default:
7254                 return ETH_RSS_RETA_SIZE_128;
7255         }
7256 }
7257
7258 uint32_t
7259 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7260         switch (mac_type) {
7261         case ixgbe_mac_X550:
7262         case ixgbe_mac_X550EM_x:
7263         case ixgbe_mac_X550EM_a:
7264                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7265                         return IXGBE_RETA(reta_idx >> 2);
7266                 else
7267                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7268         case ixgbe_mac_X550_vf:
7269         case ixgbe_mac_X550EM_x_vf:
7270         case ixgbe_mac_X550EM_a_vf:
7271                 return IXGBE_VFRETA(reta_idx >> 2);
7272         default:
7273                 return IXGBE_RETA(reta_idx >> 2);
7274         }
7275 }
7276
7277 uint32_t
7278 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7279         switch (mac_type) {
7280         case ixgbe_mac_X550_vf:
7281         case ixgbe_mac_X550EM_x_vf:
7282         case ixgbe_mac_X550EM_a_vf:
7283                 return IXGBE_VFMRQC;
7284         default:
7285                 return IXGBE_MRQC;
7286         }
7287 }
7288
7289 uint32_t
7290 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7291         switch (mac_type) {
7292         case ixgbe_mac_X550_vf:
7293         case ixgbe_mac_X550EM_x_vf:
7294         case ixgbe_mac_X550EM_a_vf:
7295                 return IXGBE_VFRSSRK(i);
7296         default:
7297                 return IXGBE_RSSRK(i);
7298         }
7299 }
7300
7301 bool
7302 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7303         switch (mac_type) {
7304         case ixgbe_mac_82599_vf:
7305         case ixgbe_mac_X540_vf:
7306                 return 0;
7307         default:
7308                 return 1;
7309         }
7310 }
7311
7312 static int
7313 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7314                         struct rte_eth_dcb_info *dcb_info)
7315 {
7316         struct ixgbe_dcb_config *dcb_config =
7317                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7318         struct ixgbe_dcb_tc_config *tc;
7319         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7320         uint8_t nb_tcs;
7321         uint8_t i, j;
7322
7323         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7324                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7325         else
7326                 dcb_info->nb_tcs = 1;
7327
7328         tc_queue = &dcb_info->tc_queue;
7329         nb_tcs = dcb_info->nb_tcs;
7330
7331         if (dcb_config->vt_mode) { /* vt is enabled*/
7332                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7333                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7334                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7335                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7336                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7337                         for (j = 0; j < nb_tcs; j++) {
7338                                 tc_queue->tc_rxq[0][j].base = j;
7339                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7340                                 tc_queue->tc_txq[0][j].base = j;
7341                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7342                         }
7343                 } else {
7344                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7345                                 for (j = 0; j < nb_tcs; j++) {
7346                                         tc_queue->tc_rxq[i][j].base =
7347                                                 i * nb_tcs + j;
7348                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7349                                         tc_queue->tc_txq[i][j].base =
7350                                                 i * nb_tcs + j;
7351                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7352                                 }
7353                         }
7354                 }
7355         } else { /* vt is disabled*/
7356                 struct rte_eth_dcb_rx_conf *rx_conf =
7357                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7358                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7359                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7360                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7361                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7362                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7363                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7364                         }
7365                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7366                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7367                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7368                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7369                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7370                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7371                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7372                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7373                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7374                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7375                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7376                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7377                         }
7378                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7379                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7380                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7381                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7382                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7383                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7384                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7385                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7386                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7387                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7388                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7389                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7390                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7391                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7392                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7393                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7394                 }
7395         }
7396         for (i = 0; i < dcb_info->nb_tcs; i++) {
7397                 tc = &dcb_config->tc_config[i];
7398                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7399         }
7400         return 0;
7401 }
7402
7403 /* Update e-tag ether type */
7404 static int
7405 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7406                             uint16_t ether_type)
7407 {
7408         uint32_t etag_etype;
7409
7410         if (hw->mac.type != ixgbe_mac_X550 &&
7411             hw->mac.type != ixgbe_mac_X550EM_x &&
7412             hw->mac.type != ixgbe_mac_X550EM_a) {
7413                 return -ENOTSUP;
7414         }
7415
7416         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7417         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7418         etag_etype |= ether_type;
7419         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7420         IXGBE_WRITE_FLUSH(hw);
7421
7422         return 0;
7423 }
7424
7425 /* Config l2 tunnel ether type */
7426 static int
7427 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7428                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7429 {
7430         int ret = 0;
7431         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7432         struct ixgbe_l2_tn_info *l2_tn_info =
7433                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7434
7435         if (l2_tunnel == NULL)
7436                 return -EINVAL;
7437
7438         switch (l2_tunnel->l2_tunnel_type) {
7439         case RTE_L2_TUNNEL_TYPE_E_TAG:
7440                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7441                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7442                 break;
7443         default:
7444                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7445                 ret = -EINVAL;
7446                 break;
7447         }
7448
7449         return ret;
7450 }
7451
7452 /* Enable e-tag tunnel */
7453 static int
7454 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7455 {
7456         uint32_t etag_etype;
7457
7458         if (hw->mac.type != ixgbe_mac_X550 &&
7459             hw->mac.type != ixgbe_mac_X550EM_x &&
7460             hw->mac.type != ixgbe_mac_X550EM_a) {
7461                 return -ENOTSUP;
7462         }
7463
7464         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7465         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7466         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7467         IXGBE_WRITE_FLUSH(hw);
7468
7469         return 0;
7470 }
7471
7472 /* Enable l2 tunnel */
7473 static int
7474 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7475                            enum rte_eth_tunnel_type l2_tunnel_type)
7476 {
7477         int ret = 0;
7478         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7479         struct ixgbe_l2_tn_info *l2_tn_info =
7480                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7481
7482         switch (l2_tunnel_type) {
7483         case RTE_L2_TUNNEL_TYPE_E_TAG:
7484                 l2_tn_info->e_tag_en = TRUE;
7485                 ret = ixgbe_e_tag_enable(hw);
7486                 break;
7487         default:
7488                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7489                 ret = -EINVAL;
7490                 break;
7491         }
7492
7493         return ret;
7494 }
7495
7496 /* Disable e-tag tunnel */
7497 static int
7498 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7499 {
7500         uint32_t etag_etype;
7501
7502         if (hw->mac.type != ixgbe_mac_X550 &&
7503             hw->mac.type != ixgbe_mac_X550EM_x &&
7504             hw->mac.type != ixgbe_mac_X550EM_a) {
7505                 return -ENOTSUP;
7506         }
7507
7508         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7509         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7510         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7511         IXGBE_WRITE_FLUSH(hw);
7512
7513         return 0;
7514 }
7515
7516 /* Disable l2 tunnel */
7517 static int
7518 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7519                             enum rte_eth_tunnel_type l2_tunnel_type)
7520 {
7521         int ret = 0;
7522         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7523         struct ixgbe_l2_tn_info *l2_tn_info =
7524                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7525
7526         switch (l2_tunnel_type) {
7527         case RTE_L2_TUNNEL_TYPE_E_TAG:
7528                 l2_tn_info->e_tag_en = FALSE;
7529                 ret = ixgbe_e_tag_disable(hw);
7530                 break;
7531         default:
7532                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7533                 ret = -EINVAL;
7534                 break;
7535         }
7536
7537         return ret;
7538 }
7539
7540 static int
7541 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7542                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7543 {
7544         int ret = 0;
7545         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7546         uint32_t i, rar_entries;
7547         uint32_t rar_low, rar_high;
7548
7549         if (hw->mac.type != ixgbe_mac_X550 &&
7550             hw->mac.type != ixgbe_mac_X550EM_x &&
7551             hw->mac.type != ixgbe_mac_X550EM_a) {
7552                 return -ENOTSUP;
7553         }
7554
7555         rar_entries = ixgbe_get_num_rx_addrs(hw);
7556
7557         for (i = 1; i < rar_entries; i++) {
7558                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7559                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7560                 if ((rar_high & IXGBE_RAH_AV) &&
7561                     (rar_high & IXGBE_RAH_ADTYPE) &&
7562                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7563                      l2_tunnel->tunnel_id)) {
7564                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7565                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7566
7567                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7568
7569                         return ret;
7570                 }
7571         }
7572
7573         return ret;
7574 }
7575
7576 static int
7577 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7578                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7579 {
7580         int ret = 0;
7581         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7582         uint32_t i, rar_entries;
7583         uint32_t rar_low, rar_high;
7584
7585         if (hw->mac.type != ixgbe_mac_X550 &&
7586             hw->mac.type != ixgbe_mac_X550EM_x &&
7587             hw->mac.type != ixgbe_mac_X550EM_a) {
7588                 return -ENOTSUP;
7589         }
7590
7591         /* One entry for one tunnel. Try to remove potential existing entry. */
7592         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7593
7594         rar_entries = ixgbe_get_num_rx_addrs(hw);
7595
7596         for (i = 1; i < rar_entries; i++) {
7597                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7598                 if (rar_high & IXGBE_RAH_AV) {
7599                         continue;
7600                 } else {
7601                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7602                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7603                         rar_low = l2_tunnel->tunnel_id;
7604
7605                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7606                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7607
7608                         return ret;
7609                 }
7610         }
7611
7612         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7613                      " Please remove a rule before adding a new one.");
7614         return -EINVAL;
7615 }
7616
7617 static inline struct ixgbe_l2_tn_filter *
7618 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7619                           struct ixgbe_l2_tn_key *key)
7620 {
7621         int ret;
7622
7623         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7624         if (ret < 0)
7625                 return NULL;
7626
7627         return l2_tn_info->hash_map[ret];
7628 }
7629
7630 static inline int
7631 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7632                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7633 {
7634         int ret;
7635
7636         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7637                                &l2_tn_filter->key);
7638
7639         if (ret < 0) {
7640                 PMD_DRV_LOG(ERR,
7641                             "Failed to insert L2 tunnel filter"
7642                             " to hash table %d!",
7643                             ret);
7644                 return ret;
7645         }
7646
7647         l2_tn_info->hash_map[ret] = l2_tn_filter;
7648
7649         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7650
7651         return 0;
7652 }
7653
7654 static inline int
7655 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7656                           struct ixgbe_l2_tn_key *key)
7657 {
7658         int ret;
7659         struct ixgbe_l2_tn_filter *l2_tn_filter;
7660
7661         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7662
7663         if (ret < 0) {
7664                 PMD_DRV_LOG(ERR,
7665                             "No such L2 tunnel filter to delete %d!",
7666                             ret);
7667                 return ret;
7668         }
7669
7670         l2_tn_filter = l2_tn_info->hash_map[ret];
7671         l2_tn_info->hash_map[ret] = NULL;
7672
7673         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7674         rte_free(l2_tn_filter);
7675
7676         return 0;
7677 }
7678
7679 /* Add l2 tunnel filter */
7680 int
7681 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7682                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7683                                bool restore)
7684 {
7685         int ret;
7686         struct ixgbe_l2_tn_info *l2_tn_info =
7687                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7688         struct ixgbe_l2_tn_key key;
7689         struct ixgbe_l2_tn_filter *node;
7690
7691         if (!restore) {
7692                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7693                 key.tn_id = l2_tunnel->tunnel_id;
7694
7695                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7696
7697                 if (node) {
7698                         PMD_DRV_LOG(ERR,
7699                                     "The L2 tunnel filter already exists!");
7700                         return -EINVAL;
7701                 }
7702
7703                 node = rte_zmalloc("ixgbe_l2_tn",
7704                                    sizeof(struct ixgbe_l2_tn_filter),
7705                                    0);
7706                 if (!node)
7707                         return -ENOMEM;
7708
7709                 rte_memcpy(&node->key,
7710                                  &key,
7711                                  sizeof(struct ixgbe_l2_tn_key));
7712                 node->pool = l2_tunnel->pool;
7713                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7714                 if (ret < 0) {
7715                         rte_free(node);
7716                         return ret;
7717                 }
7718         }
7719
7720         switch (l2_tunnel->l2_tunnel_type) {
7721         case RTE_L2_TUNNEL_TYPE_E_TAG:
7722                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7723                 break;
7724         default:
7725                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7726                 ret = -EINVAL;
7727                 break;
7728         }
7729
7730         if ((!restore) && (ret < 0))
7731                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7732
7733         return ret;
7734 }
7735
7736 /* Delete l2 tunnel filter */
7737 int
7738 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7739                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7740 {
7741         int ret;
7742         struct ixgbe_l2_tn_info *l2_tn_info =
7743                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7744         struct ixgbe_l2_tn_key key;
7745
7746         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7747         key.tn_id = l2_tunnel->tunnel_id;
7748         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7749         if (ret < 0)
7750                 return ret;
7751
7752         switch (l2_tunnel->l2_tunnel_type) {
7753         case RTE_L2_TUNNEL_TYPE_E_TAG:
7754                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7755                 break;
7756         default:
7757                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7758                 ret = -EINVAL;
7759                 break;
7760         }
7761
7762         return ret;
7763 }
7764
7765 /**
7766  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7767  * @dev: pointer to rte_eth_dev structure
7768  * @filter_op:operation will be taken.
7769  * @arg: a pointer to specific structure corresponding to the filter_op
7770  */
7771 static int
7772 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7773                                   enum rte_filter_op filter_op,
7774                                   void *arg)
7775 {
7776         int ret;
7777
7778         if (filter_op == RTE_ETH_FILTER_NOP)
7779                 return 0;
7780
7781         if (arg == NULL) {
7782                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7783                             filter_op);
7784                 return -EINVAL;
7785         }
7786
7787         switch (filter_op) {
7788         case RTE_ETH_FILTER_ADD:
7789                 ret = ixgbe_dev_l2_tunnel_filter_add
7790                         (dev,
7791                          (struct rte_eth_l2_tunnel_conf *)arg,
7792                          FALSE);
7793                 break;
7794         case RTE_ETH_FILTER_DELETE:
7795                 ret = ixgbe_dev_l2_tunnel_filter_del
7796                         (dev,
7797                          (struct rte_eth_l2_tunnel_conf *)arg);
7798                 break;
7799         default:
7800                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7801                 ret = -EINVAL;
7802                 break;
7803         }
7804         return ret;
7805 }
7806
7807 static int
7808 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7809 {
7810         int ret = 0;
7811         uint32_t ctrl;
7812         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7813
7814         if (hw->mac.type != ixgbe_mac_X550 &&
7815             hw->mac.type != ixgbe_mac_X550EM_x &&
7816             hw->mac.type != ixgbe_mac_X550EM_a) {
7817                 return -ENOTSUP;
7818         }
7819
7820         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7821         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7822         if (en)
7823                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7824         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7825
7826         return ret;
7827 }
7828
7829 /* Enable l2 tunnel forwarding */
7830 static int
7831 ixgbe_dev_l2_tunnel_forwarding_enable
7832         (struct rte_eth_dev *dev,
7833          enum rte_eth_tunnel_type l2_tunnel_type)
7834 {
7835         struct ixgbe_l2_tn_info *l2_tn_info =
7836                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7837         int ret = 0;
7838
7839         switch (l2_tunnel_type) {
7840         case RTE_L2_TUNNEL_TYPE_E_TAG:
7841                 l2_tn_info->e_tag_fwd_en = TRUE;
7842                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7843                 break;
7844         default:
7845                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7846                 ret = -EINVAL;
7847                 break;
7848         }
7849
7850         return ret;
7851 }
7852
7853 /* Disable l2 tunnel forwarding */
7854 static int
7855 ixgbe_dev_l2_tunnel_forwarding_disable
7856         (struct rte_eth_dev *dev,
7857          enum rte_eth_tunnel_type l2_tunnel_type)
7858 {
7859         struct ixgbe_l2_tn_info *l2_tn_info =
7860                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7861         int ret = 0;
7862
7863         switch (l2_tunnel_type) {
7864         case RTE_L2_TUNNEL_TYPE_E_TAG:
7865                 l2_tn_info->e_tag_fwd_en = FALSE;
7866                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7867                 break;
7868         default:
7869                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7870                 ret = -EINVAL;
7871                 break;
7872         }
7873
7874         return ret;
7875 }
7876
7877 static int
7878 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7879                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7880                              bool en)
7881 {
7882         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7883         int ret = 0;
7884         uint32_t vmtir, vmvir;
7885         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7886
7887         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7888                 PMD_DRV_LOG(ERR,
7889                             "VF id %u should be less than %u",
7890                             l2_tunnel->vf_id,
7891                             pci_dev->max_vfs);
7892                 return -EINVAL;
7893         }
7894
7895         if (hw->mac.type != ixgbe_mac_X550 &&
7896             hw->mac.type != ixgbe_mac_X550EM_x &&
7897             hw->mac.type != ixgbe_mac_X550EM_a) {
7898                 return -ENOTSUP;
7899         }
7900
7901         if (en)
7902                 vmtir = l2_tunnel->tunnel_id;
7903         else
7904                 vmtir = 0;
7905
7906         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7907
7908         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7909         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7910         if (en)
7911                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7912         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7913
7914         return ret;
7915 }
7916
7917 /* Enable l2 tunnel tag insertion */
7918 static int
7919 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7920                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7921 {
7922         int ret = 0;
7923
7924         switch (l2_tunnel->l2_tunnel_type) {
7925         case RTE_L2_TUNNEL_TYPE_E_TAG:
7926                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7927                 break;
7928         default:
7929                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7930                 ret = -EINVAL;
7931                 break;
7932         }
7933
7934         return ret;
7935 }
7936
7937 /* Disable l2 tunnel tag insertion */
7938 static int
7939 ixgbe_dev_l2_tunnel_insertion_disable
7940         (struct rte_eth_dev *dev,
7941          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7942 {
7943         int ret = 0;
7944
7945         switch (l2_tunnel->l2_tunnel_type) {
7946         case RTE_L2_TUNNEL_TYPE_E_TAG:
7947                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7948                 break;
7949         default:
7950                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7951                 ret = -EINVAL;
7952                 break;
7953         }
7954
7955         return ret;
7956 }
7957
7958 static int
7959 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7960                              bool en)
7961 {
7962         int ret = 0;
7963         uint32_t qde;
7964         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7965
7966         if (hw->mac.type != ixgbe_mac_X550 &&
7967             hw->mac.type != ixgbe_mac_X550EM_x &&
7968             hw->mac.type != ixgbe_mac_X550EM_a) {
7969                 return -ENOTSUP;
7970         }
7971
7972         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7973         if (en)
7974                 qde |= IXGBE_QDE_STRIP_TAG;
7975         else
7976                 qde &= ~IXGBE_QDE_STRIP_TAG;
7977         qde &= ~IXGBE_QDE_READ;
7978         qde |= IXGBE_QDE_WRITE;
7979         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7980
7981         return ret;
7982 }
7983
7984 /* Enable l2 tunnel tag stripping */
7985 static int
7986 ixgbe_dev_l2_tunnel_stripping_enable
7987         (struct rte_eth_dev *dev,
7988          enum rte_eth_tunnel_type l2_tunnel_type)
7989 {
7990         int ret = 0;
7991
7992         switch (l2_tunnel_type) {
7993         case RTE_L2_TUNNEL_TYPE_E_TAG:
7994                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7995                 break;
7996         default:
7997                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7998                 ret = -EINVAL;
7999                 break;
8000         }
8001
8002         return ret;
8003 }
8004
8005 /* Disable l2 tunnel tag stripping */
8006 static int
8007 ixgbe_dev_l2_tunnel_stripping_disable
8008         (struct rte_eth_dev *dev,
8009          enum rte_eth_tunnel_type l2_tunnel_type)
8010 {
8011         int ret = 0;
8012
8013         switch (l2_tunnel_type) {
8014         case RTE_L2_TUNNEL_TYPE_E_TAG:
8015                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8016                 break;
8017         default:
8018                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8019                 ret = -EINVAL;
8020                 break;
8021         }
8022
8023         return ret;
8024 }
8025
8026 /* Enable/disable l2 tunnel offload functions */
8027 static int
8028 ixgbe_dev_l2_tunnel_offload_set
8029         (struct rte_eth_dev *dev,
8030          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8031          uint32_t mask,
8032          uint8_t en)
8033 {
8034         int ret = 0;
8035
8036         if (l2_tunnel == NULL)
8037                 return -EINVAL;
8038
8039         ret = -EINVAL;
8040         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8041                 if (en)
8042                         ret = ixgbe_dev_l2_tunnel_enable(
8043                                 dev,
8044                                 l2_tunnel->l2_tunnel_type);
8045                 else
8046                         ret = ixgbe_dev_l2_tunnel_disable(
8047                                 dev,
8048                                 l2_tunnel->l2_tunnel_type);
8049         }
8050
8051         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8052                 if (en)
8053                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8054                                 dev,
8055                                 l2_tunnel);
8056                 else
8057                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8058                                 dev,
8059                                 l2_tunnel);
8060         }
8061
8062         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8063                 if (en)
8064                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8065                                 dev,
8066                                 l2_tunnel->l2_tunnel_type);
8067                 else
8068                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8069                                 dev,
8070                                 l2_tunnel->l2_tunnel_type);
8071         }
8072
8073         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8074                 if (en)
8075                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8076                                 dev,
8077                                 l2_tunnel->l2_tunnel_type);
8078                 else
8079                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8080                                 dev,
8081                                 l2_tunnel->l2_tunnel_type);
8082         }
8083
8084         return ret;
8085 }
8086
8087 static int
8088 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8089                         uint16_t port)
8090 {
8091         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8092         IXGBE_WRITE_FLUSH(hw);
8093
8094         return 0;
8095 }
8096
8097 /* There's only one register for VxLAN UDP port.
8098  * So, we cannot add several ports. Will update it.
8099  */
8100 static int
8101 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8102                      uint16_t port)
8103 {
8104         if (port == 0) {
8105                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8106                 return -EINVAL;
8107         }
8108
8109         return ixgbe_update_vxlan_port(hw, port);
8110 }
8111
8112 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8113  * UDP port, it must have a value.
8114  * So, will reset it to the original value 0.
8115  */
8116 static int
8117 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8118                      uint16_t port)
8119 {
8120         uint16_t cur_port;
8121
8122         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8123
8124         if (cur_port != port) {
8125                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8126                 return -EINVAL;
8127         }
8128
8129         return ixgbe_update_vxlan_port(hw, 0);
8130 }
8131
8132 /* Add UDP tunneling port */
8133 static int
8134 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8135                               struct rte_eth_udp_tunnel *udp_tunnel)
8136 {
8137         int ret = 0;
8138         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8139
8140         if (hw->mac.type != ixgbe_mac_X550 &&
8141             hw->mac.type != ixgbe_mac_X550EM_x &&
8142             hw->mac.type != ixgbe_mac_X550EM_a) {
8143                 return -ENOTSUP;
8144         }
8145
8146         if (udp_tunnel == NULL)
8147                 return -EINVAL;
8148
8149         switch (udp_tunnel->prot_type) {
8150         case RTE_TUNNEL_TYPE_VXLAN:
8151                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8152                 break;
8153
8154         case RTE_TUNNEL_TYPE_GENEVE:
8155         case RTE_TUNNEL_TYPE_TEREDO:
8156                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8157                 ret = -EINVAL;
8158                 break;
8159
8160         default:
8161                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8162                 ret = -EINVAL;
8163                 break;
8164         }
8165
8166         return ret;
8167 }
8168
8169 /* Remove UDP tunneling port */
8170 static int
8171 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8172                               struct rte_eth_udp_tunnel *udp_tunnel)
8173 {
8174         int ret = 0;
8175         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8176
8177         if (hw->mac.type != ixgbe_mac_X550 &&
8178             hw->mac.type != ixgbe_mac_X550EM_x &&
8179             hw->mac.type != ixgbe_mac_X550EM_a) {
8180                 return -ENOTSUP;
8181         }
8182
8183         if (udp_tunnel == NULL)
8184                 return -EINVAL;
8185
8186         switch (udp_tunnel->prot_type) {
8187         case RTE_TUNNEL_TYPE_VXLAN:
8188                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8189                 break;
8190         case RTE_TUNNEL_TYPE_GENEVE:
8191         case RTE_TUNNEL_TYPE_TEREDO:
8192                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8193                 ret = -EINVAL;
8194                 break;
8195         default:
8196                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8197                 ret = -EINVAL;
8198                 break;
8199         }
8200
8201         return ret;
8202 }
8203
8204 static void
8205 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8206 {
8207         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8208
8209         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8210 }
8211
8212 static void
8213 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8214 {
8215         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8216
8217         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8218 }
8219
8220 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8221 {
8222         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8223         u32 in_msg = 0;
8224
8225         /* peek the message first */
8226         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8227
8228         /* PF reset VF event */
8229         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8230                 /* dummy mbx read to ack pf */
8231                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8232                         return;
8233                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8234                                               NULL);
8235         }
8236 }
8237
8238 static int
8239 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8240 {
8241         uint32_t eicr;
8242         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8243         struct ixgbe_interrupt *intr =
8244                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8245         ixgbevf_intr_disable(dev);
8246
8247         /* read-on-clear nic registers here */
8248         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8249         intr->flags = 0;
8250
8251         /* only one misc vector supported - mailbox */
8252         eicr &= IXGBE_VTEICR_MASK;
8253         if (eicr == IXGBE_MISC_VEC_ID)
8254                 intr->flags |= IXGBE_FLAG_MAILBOX;
8255
8256         return 0;
8257 }
8258
8259 static int
8260 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8261 {
8262         struct ixgbe_interrupt *intr =
8263                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8264
8265         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8266                 ixgbevf_mbx_process(dev);
8267                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8268         }
8269
8270         ixgbevf_intr_enable(dev);
8271
8272         return 0;
8273 }
8274
8275 static void
8276 ixgbevf_dev_interrupt_handler(void *param)
8277 {
8278         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8279
8280         ixgbevf_dev_interrupt_get_status(dev);
8281         ixgbevf_dev_interrupt_action(dev);
8282 }
8283
8284 /**
8285  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8286  *  @hw: pointer to hardware structure
8287  *
8288  *  Stops the transmit data path and waits for the HW to internally empty
8289  *  the Tx security block
8290  **/
8291 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8292 {
8293 #define IXGBE_MAX_SECTX_POLL 40
8294
8295         int i;
8296         int sectxreg;
8297
8298         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8299         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8300         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8301         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8302                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8303                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8304                         break;
8305                 /* Use interrupt-safe sleep just in case */
8306                 usec_delay(1000);
8307         }
8308
8309         /* For informational purposes only */
8310         if (i >= IXGBE_MAX_SECTX_POLL)
8311                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8312                          "path fully disabled.  Continuing with init.");
8313
8314         return IXGBE_SUCCESS;
8315 }
8316
8317 /**
8318  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8319  *  @hw: pointer to hardware structure
8320  *
8321  *  Enables the transmit data path.
8322  **/
8323 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8324 {
8325         uint32_t sectxreg;
8326
8327         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8328         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8329         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8330         IXGBE_WRITE_FLUSH(hw);
8331
8332         return IXGBE_SUCCESS;
8333 }
8334
8335 /* restore n-tuple filter */
8336 static inline void
8337 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8338 {
8339         struct ixgbe_filter_info *filter_info =
8340                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8341         struct ixgbe_5tuple_filter *node;
8342
8343         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8344                 ixgbe_inject_5tuple_filter(dev, node);
8345         }
8346 }
8347
8348 /* restore ethernet type filter */
8349 static inline void
8350 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8351 {
8352         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8353         struct ixgbe_filter_info *filter_info =
8354                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8355         int i;
8356
8357         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8358                 if (filter_info->ethertype_mask & (1 << i)) {
8359                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8360                                         filter_info->ethertype_filters[i].etqf);
8361                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8362                                         filter_info->ethertype_filters[i].etqs);
8363                         IXGBE_WRITE_FLUSH(hw);
8364                 }
8365         }
8366 }
8367
8368 /* restore SYN filter */
8369 static inline void
8370 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8371 {
8372         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8373         struct ixgbe_filter_info *filter_info =
8374                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8375         uint32_t synqf;
8376
8377         synqf = filter_info->syn_info;
8378
8379         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8380                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8381                 IXGBE_WRITE_FLUSH(hw);
8382         }
8383 }
8384
8385 /* restore L2 tunnel filter */
8386 static inline void
8387 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8388 {
8389         struct ixgbe_l2_tn_info *l2_tn_info =
8390                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8391         struct ixgbe_l2_tn_filter *node;
8392         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8393
8394         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8395                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8396                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8397                 l2_tn_conf.pool           = node->pool;
8398                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8399         }
8400 }
8401
8402 /* restore rss filter */
8403 static inline void
8404 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8405 {
8406         struct ixgbe_filter_info *filter_info =
8407                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8408
8409         if (filter_info->rss_info.conf.queue_num)
8410                 ixgbe_config_rss_filter(dev,
8411                         &filter_info->rss_info, TRUE);
8412 }
8413
8414 static int
8415 ixgbe_filter_restore(struct rte_eth_dev *dev)
8416 {
8417         ixgbe_ntuple_filter_restore(dev);
8418         ixgbe_ethertype_filter_restore(dev);
8419         ixgbe_syn_filter_restore(dev);
8420         ixgbe_fdir_filter_restore(dev);
8421         ixgbe_l2_tn_filter_restore(dev);
8422         ixgbe_rss_filter_restore(dev);
8423
8424         return 0;
8425 }
8426
8427 static void
8428 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8429 {
8430         struct ixgbe_l2_tn_info *l2_tn_info =
8431                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8432         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8433
8434         if (l2_tn_info->e_tag_en)
8435                 (void)ixgbe_e_tag_enable(hw);
8436
8437         if (l2_tn_info->e_tag_fwd_en)
8438                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8439
8440         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8441 }
8442
8443 /* remove all the n-tuple filters */
8444 void
8445 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8446 {
8447         struct ixgbe_filter_info *filter_info =
8448                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8449         struct ixgbe_5tuple_filter *p_5tuple;
8450
8451         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8452                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8453 }
8454
8455 /* remove all the ether type filters */
8456 void
8457 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8458 {
8459         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8460         struct ixgbe_filter_info *filter_info =
8461                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8462         int i;
8463
8464         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8465                 if (filter_info->ethertype_mask & (1 << i) &&
8466                     !filter_info->ethertype_filters[i].conf) {
8467                         (void)ixgbe_ethertype_filter_remove(filter_info,
8468                                                             (uint8_t)i);
8469                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8470                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8471                         IXGBE_WRITE_FLUSH(hw);
8472                 }
8473         }
8474 }
8475
8476 /* remove the SYN filter */
8477 void
8478 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8479 {
8480         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8481         struct ixgbe_filter_info *filter_info =
8482                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8483
8484         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8485                 filter_info->syn_info = 0;
8486
8487                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8488                 IXGBE_WRITE_FLUSH(hw);
8489         }
8490 }
8491
8492 /* remove all the L2 tunnel filters */
8493 int
8494 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8495 {
8496         struct ixgbe_l2_tn_info *l2_tn_info =
8497                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8498         struct ixgbe_l2_tn_filter *l2_tn_filter;
8499         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8500         int ret = 0;
8501
8502         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8503                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8504                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8505                 l2_tn_conf.pool           = l2_tn_filter->pool;
8506                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8507                 if (ret < 0)
8508                         return ret;
8509         }
8510
8511         return 0;
8512 }
8513
8514 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8515 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8516 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8517 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8518 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8519 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8520
8521 RTE_INIT(ixgbe_init_log);
8522 static void
8523 ixgbe_init_log(void)
8524 {
8525         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8526         if (ixgbe_logtype_init >= 0)
8527                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8528         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8529         if (ixgbe_logtype_driver >= 0)
8530                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8531 }