4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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19 * from this software without specific prior written permission.
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34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
64 #include "ixgbe_logs.h"
65 #include "base/ixgbe_api.h"
66 #include "base/ixgbe_vf.h"
67 #include "base/ixgbe_common.h"
68 #include "ixgbe_ethdev.h"
69 #include "ixgbe_bypass.h"
70 #include "ixgbe_rxtx.h"
71 #include "base/ixgbe_type.h"
72 #include "base/ixgbe_phy.h"
73 #include "ixgbe_regs.h"
76 * High threshold controlling when to start sending XOFF frames. Must be at
77 * least 8 bytes less than receive packet buffer size. This value is in units
80 #define IXGBE_FC_HI 0x80
83 * Low threshold controlling when to start sending XON frames. This value is
84 * in units of 1024 bytes.
86 #define IXGBE_FC_LO 0x40
88 /* Default minimum inter-interrupt interval for EITR configuration */
89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
91 /* Timer value included in XOFF frames. */
92 #define IXGBE_FC_PAUSE 0x680
94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
95 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
96 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
98 #define IXGBE_MMW_SIZE_DEFAULT 0x4
99 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
100 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
103 * Default values for RX/TX configuration
105 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
106 #define IXGBE_DEFAULT_RX_PTHRESH 8
107 #define IXGBE_DEFAULT_RX_HTHRESH 8
108 #define IXGBE_DEFAULT_RX_WTHRESH 0
110 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
111 #define IXGBE_DEFAULT_TX_PTHRESH 32
112 #define IXGBE_DEFAULT_TX_HTHRESH 0
113 #define IXGBE_DEFAULT_TX_WTHRESH 0
114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
116 /* Bit shift and mask */
117 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
118 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
119 #define IXGBE_8_BIT_WIDTH CHAR_BIT
120 #define IXGBE_8_BIT_MASK UINT8_MAX
122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
126 #define IXGBE_HKEY_MAX_INDEX 10
128 /* Additional timesync values. */
129 #define NSEC_PER_SEC 1000000000L
130 #define IXGBE_INCVAL_10GB 0x66666666
131 #define IXGBE_INCVAL_1GB 0x40000000
132 #define IXGBE_INCVAL_100 0x50000000
133 #define IXGBE_INCVAL_SHIFT_10GB 28
134 #define IXGBE_INCVAL_SHIFT_1GB 24
135 #define IXGBE_INCVAL_SHIFT_100 21
136 #define IXGBE_INCVAL_SHIFT_82599 7
137 #define IXGBE_INCPER_SHIFT_82599 24
139 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
141 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
143 #define DEFAULT_ETAG_ETYPE 0x893f
144 #define IXGBE_ETAG_ETYPE 0x00005084
145 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
146 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
147 #define IXGBE_RAH_ADTYPE 0x40000000
148 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
149 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
152 #define IXGBE_QDE_STRIP_TAG 0x00000004
154 enum ixgbevf_xcast_modes {
155 IXGBEVF_XCAST_MODE_NONE = 0,
156 IXGBEVF_XCAST_MODE_MULTI,
157 IXGBEVF_XCAST_MODE_ALLMULTI,
160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
162 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
163 static int ixgbe_dev_start(struct rte_eth_dev *dev);
164 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
165 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
166 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
167 static void ixgbe_dev_close(struct rte_eth_dev *dev);
168 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
169 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
170 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
171 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
172 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
173 int wait_to_complete);
174 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
175 struct rte_eth_stats *stats);
176 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
177 struct rte_eth_xstats *xstats, unsigned n);
178 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
179 struct rte_eth_xstats *xstats, unsigned n);
180 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
181 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
182 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
186 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
187 struct rte_eth_dev_info *dev_info);
188 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
189 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
190 struct rte_eth_dev_info *dev_info);
191 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
193 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
194 uint16_t vlan_id, int on);
195 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
196 enum rte_vlan_type vlan_type,
198 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
199 uint16_t queue, bool on);
200 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
202 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
203 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
204 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
205 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
206 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
208 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
209 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
210 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
211 struct rte_eth_fc_conf *fc_conf);
212 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
213 struct rte_eth_fc_conf *fc_conf);
214 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
215 struct rte_eth_pfc_conf *pfc_conf);
216 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
217 struct rte_eth_rss_reta_entry64 *reta_conf,
219 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
220 struct rte_eth_rss_reta_entry64 *reta_conf,
222 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
223 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
224 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
225 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
226 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
227 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
229 static void ixgbe_dev_interrupt_delayed_handler(void *param);
230 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
231 uint32_t index, uint32_t pool);
232 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
233 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
234 struct ether_addr *mac_addr);
235 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
237 /* For Virtual Function support */
238 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
239 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
240 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
241 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
242 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
243 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
244 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
245 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
246 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
247 struct rte_eth_stats *stats);
248 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
249 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
250 uint16_t vlan_id, int on);
251 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
252 uint16_t queue, int on);
253 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
254 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
255 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
257 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
259 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
260 uint8_t queue, uint8_t msix_vector);
261 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
262 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
263 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
265 /* For Eth VMDQ APIs support */
266 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
267 ether_addr* mac_addr,uint8_t on);
268 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
269 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
270 uint16_t rx_mask, uint8_t on);
271 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
272 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
273 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
274 uint64_t pool_mask,uint8_t vlan_on);
275 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
276 struct rte_eth_mirror_conf *mirror_conf,
277 uint8_t rule_id, uint8_t on);
278 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
280 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
282 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
284 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
285 uint8_t queue, uint8_t msix_vector);
286 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
288 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
289 uint16_t queue_idx, uint16_t tx_rate);
290 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
291 uint16_t tx_rate, uint64_t q_msk);
293 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
294 struct ether_addr *mac_addr,
295 uint32_t index, uint32_t pool);
296 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
297 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
298 struct ether_addr *mac_addr);
299 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
300 struct rte_eth_syn_filter *filter,
302 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
303 struct rte_eth_syn_filter *filter);
304 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
305 enum rte_filter_op filter_op,
307 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
308 struct ixgbe_5tuple_filter *filter);
309 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
310 struct ixgbe_5tuple_filter *filter);
311 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
312 struct rte_eth_ntuple_filter *filter,
314 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
315 enum rte_filter_op filter_op,
317 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
318 struct rte_eth_ntuple_filter *filter);
319 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
320 struct rte_eth_ethertype_filter *filter,
322 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
323 enum rte_filter_op filter_op,
325 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
326 struct rte_eth_ethertype_filter *filter);
327 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
328 enum rte_filter_type filter_type,
329 enum rte_filter_op filter_op,
331 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
333 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
334 struct ether_addr *mc_addr_set,
335 uint32_t nb_mc_addr);
336 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
337 struct rte_eth_dcb_info *dcb_info);
339 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
340 static int ixgbe_get_regs(struct rte_eth_dev *dev,
341 struct rte_dev_reg_info *regs);
342 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
343 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
344 struct rte_dev_eeprom_info *eeprom);
345 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
346 struct rte_dev_eeprom_info *eeprom);
348 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
349 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
350 struct rte_dev_reg_info *regs);
352 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
353 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
354 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
355 struct timespec *timestamp,
357 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
358 struct timespec *timestamp);
359 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
360 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
361 struct timespec *timestamp);
362 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
363 const struct timespec *timestamp);
365 static int ixgbe_dev_l2_tunnel_eth_type_conf
366 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
367 static int ixgbe_dev_l2_tunnel_offload_set
368 (struct rte_eth_dev *dev,
369 struct rte_eth_l2_tunnel_conf *l2_tunnel,
372 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
373 enum rte_filter_op filter_op,
376 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
377 struct rte_eth_udp_tunnel *udp_tunnel);
378 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
379 struct rte_eth_udp_tunnel *udp_tunnel);
382 * Define VF Stats MACRO for Non "cleared on read" register
384 #define UPDATE_VF_STAT(reg, last, cur) \
386 uint32_t latest = IXGBE_READ_REG(hw, reg); \
387 cur += (latest - last) & UINT_MAX; \
391 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
393 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
394 u64 new_msb = IXGBE_READ_REG(hw, msb); \
395 u64 latest = ((new_msb << 32) | new_lsb); \
396 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
400 #define IXGBE_SET_HWSTRIP(h, q) do{\
401 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
402 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
403 (h)->bitmap[idx] |= 1 << bit;\
406 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
407 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
408 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
409 (h)->bitmap[idx] &= ~(1 << bit);\
412 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
413 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
414 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
415 (r) = (h)->bitmap[idx] >> bit & 1;\
419 * The set of PCI devices this driver supports
421 static const struct rte_pci_id pci_id_ixgbe_map[] = {
423 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
424 #include "rte_pci_dev_ids.h"
426 { .vendor_id = 0, /* sentinel */ },
431 * The set of PCI devices this driver supports (for 82599 VF)
433 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
435 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
436 #include "rte_pci_dev_ids.h"
437 { .vendor_id = 0, /* sentinel */ },
441 static const struct rte_eth_desc_lim rx_desc_lim = {
442 .nb_max = IXGBE_MAX_RING_DESC,
443 .nb_min = IXGBE_MIN_RING_DESC,
444 .nb_align = IXGBE_RXD_ALIGN,
447 static const struct rte_eth_desc_lim tx_desc_lim = {
448 .nb_max = IXGBE_MAX_RING_DESC,
449 .nb_min = IXGBE_MIN_RING_DESC,
450 .nb_align = IXGBE_TXD_ALIGN,
453 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
454 .dev_configure = ixgbe_dev_configure,
455 .dev_start = ixgbe_dev_start,
456 .dev_stop = ixgbe_dev_stop,
457 .dev_set_link_up = ixgbe_dev_set_link_up,
458 .dev_set_link_down = ixgbe_dev_set_link_down,
459 .dev_close = ixgbe_dev_close,
460 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
461 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
462 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
463 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
464 .link_update = ixgbe_dev_link_update,
465 .stats_get = ixgbe_dev_stats_get,
466 .xstats_get = ixgbe_dev_xstats_get,
467 .stats_reset = ixgbe_dev_stats_reset,
468 .xstats_reset = ixgbe_dev_xstats_reset,
469 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
470 .dev_infos_get = ixgbe_dev_info_get,
471 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
472 .mtu_set = ixgbe_dev_mtu_set,
473 .vlan_filter_set = ixgbe_vlan_filter_set,
474 .vlan_tpid_set = ixgbe_vlan_tpid_set,
475 .vlan_offload_set = ixgbe_vlan_offload_set,
476 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
477 .rx_queue_start = ixgbe_dev_rx_queue_start,
478 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
479 .tx_queue_start = ixgbe_dev_tx_queue_start,
480 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
481 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
482 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
483 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
484 .rx_queue_release = ixgbe_dev_rx_queue_release,
485 .rx_queue_count = ixgbe_dev_rx_queue_count,
486 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
487 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
488 .tx_queue_release = ixgbe_dev_tx_queue_release,
489 .dev_led_on = ixgbe_dev_led_on,
490 .dev_led_off = ixgbe_dev_led_off,
491 .flow_ctrl_get = ixgbe_flow_ctrl_get,
492 .flow_ctrl_set = ixgbe_flow_ctrl_set,
493 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
494 .mac_addr_add = ixgbe_add_rar,
495 .mac_addr_remove = ixgbe_remove_rar,
496 .mac_addr_set = ixgbe_set_default_mac_addr,
497 .uc_hash_table_set = ixgbe_uc_hash_table_set,
498 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
499 .mirror_rule_set = ixgbe_mirror_rule_set,
500 .mirror_rule_reset = ixgbe_mirror_rule_reset,
501 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
502 .set_vf_rx = ixgbe_set_pool_rx,
503 .set_vf_tx = ixgbe_set_pool_tx,
504 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
505 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
506 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
507 .reta_update = ixgbe_dev_rss_reta_update,
508 .reta_query = ixgbe_dev_rss_reta_query,
509 #ifdef RTE_NIC_BYPASS
510 .bypass_init = ixgbe_bypass_init,
511 .bypass_state_set = ixgbe_bypass_state_store,
512 .bypass_state_show = ixgbe_bypass_state_show,
513 .bypass_event_set = ixgbe_bypass_event_store,
514 .bypass_event_show = ixgbe_bypass_event_show,
515 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
516 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
517 .bypass_ver_show = ixgbe_bypass_ver_show,
518 .bypass_wd_reset = ixgbe_bypass_wd_reset,
519 #endif /* RTE_NIC_BYPASS */
520 .rss_hash_update = ixgbe_dev_rss_hash_update,
521 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
522 .filter_ctrl = ixgbe_dev_filter_ctrl,
523 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
524 .rxq_info_get = ixgbe_rxq_info_get,
525 .txq_info_get = ixgbe_txq_info_get,
526 .timesync_enable = ixgbe_timesync_enable,
527 .timesync_disable = ixgbe_timesync_disable,
528 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
529 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
530 .get_reg_length = ixgbe_get_reg_length,
531 .get_reg = ixgbe_get_regs,
532 .get_eeprom_length = ixgbe_get_eeprom_length,
533 .get_eeprom = ixgbe_get_eeprom,
534 .set_eeprom = ixgbe_set_eeprom,
535 .get_dcb_info = ixgbe_dev_get_dcb_info,
536 .timesync_adjust_time = ixgbe_timesync_adjust_time,
537 .timesync_read_time = ixgbe_timesync_read_time,
538 .timesync_write_time = ixgbe_timesync_write_time,
539 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
540 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
541 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
542 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
546 * dev_ops for virtual function, bare necessities for basic vf
547 * operation have been implemented
549 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
550 .dev_configure = ixgbevf_dev_configure,
551 .dev_start = ixgbevf_dev_start,
552 .dev_stop = ixgbevf_dev_stop,
553 .link_update = ixgbe_dev_link_update,
554 .stats_get = ixgbevf_dev_stats_get,
555 .xstats_get = ixgbevf_dev_xstats_get,
556 .stats_reset = ixgbevf_dev_stats_reset,
557 .xstats_reset = ixgbevf_dev_stats_reset,
558 .dev_close = ixgbevf_dev_close,
559 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
560 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
561 .dev_infos_get = ixgbevf_dev_info_get,
562 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
563 .mtu_set = ixgbevf_dev_set_mtu,
564 .vlan_filter_set = ixgbevf_vlan_filter_set,
565 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
566 .vlan_offload_set = ixgbevf_vlan_offload_set,
567 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
568 .rx_queue_release = ixgbe_dev_rx_queue_release,
569 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
570 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
571 .tx_queue_release = ixgbe_dev_tx_queue_release,
572 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
573 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
574 .mac_addr_add = ixgbevf_add_mac_addr,
575 .mac_addr_remove = ixgbevf_remove_mac_addr,
576 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
577 .rxq_info_get = ixgbe_rxq_info_get,
578 .txq_info_get = ixgbe_txq_info_get,
579 .mac_addr_set = ixgbevf_set_default_mac_addr,
580 .get_reg_length = ixgbevf_get_reg_length,
581 .get_reg = ixgbevf_get_regs,
582 .reta_update = ixgbe_dev_rss_reta_update,
583 .reta_query = ixgbe_dev_rss_reta_query,
584 .rss_hash_update = ixgbe_dev_rss_hash_update,
585 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
588 /* store statistics names and its offset in stats structure */
589 struct rte_ixgbe_xstats_name_off {
590 char name[RTE_ETH_XSTATS_NAME_SIZE];
594 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
595 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
596 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
597 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
598 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
599 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
600 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
601 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
602 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
603 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
604 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
605 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
606 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
607 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
608 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
609 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
611 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
613 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
614 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
615 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
616 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
617 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
618 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
619 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
620 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
621 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
622 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
623 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
624 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
625 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
626 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
627 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
628 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
629 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
631 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
633 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
634 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
635 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
636 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
638 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
640 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
642 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
644 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
646 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
648 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
651 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
652 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
653 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
655 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
656 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
657 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
658 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
659 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
661 {"rx_fcoe_no_direct_data_placement_ext_buff",
662 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
664 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
666 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
668 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
670 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
672 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
675 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
676 sizeof(rte_ixgbe_stats_strings[0]))
678 /* Per-queue statistics */
679 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
680 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
681 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
682 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
683 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
686 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
687 sizeof(rte_ixgbe_rxq_strings[0]))
689 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
690 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
691 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
692 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
696 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
697 sizeof(rte_ixgbe_txq_strings[0]))
699 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
700 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
703 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
704 sizeof(rte_ixgbevf_stats_strings[0]))
707 * Atomically reads the link status information from global
708 * structure rte_eth_dev.
711 * - Pointer to the structure rte_eth_dev to read from.
712 * - Pointer to the buffer to be saved with the link status.
715 * - On success, zero.
716 * - On failure, negative value.
719 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
720 struct rte_eth_link *link)
722 struct rte_eth_link *dst = link;
723 struct rte_eth_link *src = &(dev->data->dev_link);
725 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
726 *(uint64_t *)src) == 0)
733 * Atomically writes the link status information into global
734 * structure rte_eth_dev.
737 * - Pointer to the structure rte_eth_dev to read from.
738 * - Pointer to the buffer to be saved with the link status.
741 * - On success, zero.
742 * - On failure, negative value.
745 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
746 struct rte_eth_link *link)
748 struct rte_eth_link *dst = &(dev->data->dev_link);
749 struct rte_eth_link *src = link;
751 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
752 *(uint64_t *)src) == 0)
759 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
762 ixgbe_is_sfp(struct ixgbe_hw *hw)
764 switch (hw->phy.type) {
765 case ixgbe_phy_sfp_avago:
766 case ixgbe_phy_sfp_ftl:
767 case ixgbe_phy_sfp_intel:
768 case ixgbe_phy_sfp_unknown:
769 case ixgbe_phy_sfp_passive_tyco:
770 case ixgbe_phy_sfp_passive_unknown:
777 static inline int32_t
778 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
783 status = ixgbe_reset_hw(hw);
785 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
786 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
787 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
788 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
789 IXGBE_WRITE_FLUSH(hw);
795 ixgbe_enable_intr(struct rte_eth_dev *dev)
797 struct ixgbe_interrupt *intr =
798 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
799 struct ixgbe_hw *hw =
800 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
802 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
803 IXGBE_WRITE_FLUSH(hw);
807 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
810 ixgbe_disable_intr(struct ixgbe_hw *hw)
812 PMD_INIT_FUNC_TRACE();
814 if (hw->mac.type == ixgbe_mac_82598EB) {
815 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
817 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
818 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
819 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
821 IXGBE_WRITE_FLUSH(hw);
825 * This function resets queue statistics mapping registers.
826 * From Niantic datasheet, Initialization of Statistics section:
827 * "...if software requires the queue counters, the RQSMR and TQSM registers
828 * must be re-programmed following a device reset.
831 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
835 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
836 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
837 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
843 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
848 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
849 #define NB_QMAP_FIELDS_PER_QSM_REG 4
850 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
852 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
853 struct ixgbe_stat_mapping_registers *stat_mappings =
854 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
855 uint32_t qsmr_mask = 0;
856 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
860 if ((hw->mac.type != ixgbe_mac_82599EB) &&
861 (hw->mac.type != ixgbe_mac_X540) &&
862 (hw->mac.type != ixgbe_mac_X550) &&
863 (hw->mac.type != ixgbe_mac_X550EM_x) &&
864 (hw->mac.type != ixgbe_mac_X550EM_a))
867 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
868 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
871 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
872 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
873 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
876 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
878 /* Now clear any previous stat_idx set */
879 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
881 stat_mappings->tqsm[n] &= ~clearing_mask;
883 stat_mappings->rqsmr[n] &= ~clearing_mask;
885 q_map = (uint32_t)stat_idx;
886 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
887 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
889 stat_mappings->tqsm[n] |= qsmr_mask;
891 stat_mappings->rqsmr[n] |= qsmr_mask;
893 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
894 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
896 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
897 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
899 /* Now write the mapping in the appropriate register */
901 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
902 stat_mappings->rqsmr[n], n);
903 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
906 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
907 stat_mappings->tqsm[n], n);
908 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
914 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
916 struct ixgbe_stat_mapping_registers *stat_mappings =
917 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
918 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
921 /* write whatever was in stat mapping table to the NIC */
922 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
924 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
927 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
932 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
935 struct ixgbe_dcb_tc_config *tc;
936 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
938 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
939 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
940 for (i = 0; i < dcb_max_tc; i++) {
941 tc = &dcb_config->tc_config[i];
942 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
943 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
944 (uint8_t)(100/dcb_max_tc + (i & 1));
945 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
946 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
947 (uint8_t)(100/dcb_max_tc + (i & 1));
948 tc->pfc = ixgbe_dcb_pfc_disabled;
951 /* Initialize default user to priority mapping, UPx->TC0 */
952 tc = &dcb_config->tc_config[0];
953 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
954 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
955 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
956 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
957 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
959 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
960 dcb_config->pfc_mode_enable = false;
961 dcb_config->vt_mode = true;
962 dcb_config->round_robin_enable = false;
963 /* support all DCB capabilities in 82599 */
964 dcb_config->support.capabilities = 0xFF;
966 /*we only support 4 Tcs for X540, X550 */
967 if (hw->mac.type == ixgbe_mac_X540 ||
968 hw->mac.type == ixgbe_mac_X550 ||
969 hw->mac.type == ixgbe_mac_X550EM_x ||
970 hw->mac.type == ixgbe_mac_X550EM_a) {
971 dcb_config->num_tcs.pg_tcs = 4;
972 dcb_config->num_tcs.pfc_tcs = 4;
977 * Ensure that all locks are released before first NVM or PHY access
980 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
985 * Phy lock should not fail in this early stage. If this is the case,
986 * it is due to an improper exit of the application.
987 * So force the release of the faulty lock. Release of common lock
988 * is done automatically by swfw_sync function.
990 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
991 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
992 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
994 ixgbe_release_swfw_semaphore(hw, mask);
997 * These ones are more tricky since they are common to all ports; but
998 * swfw_sync retries last long enough (1s) to be almost sure that if
999 * lock can not be taken it is due to an improper lock of the
1002 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1003 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1004 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1006 ixgbe_release_swfw_semaphore(hw, mask);
1010 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1011 * It returns 0 on success.
1014 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1016 struct rte_pci_device *pci_dev;
1017 struct ixgbe_hw *hw =
1018 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1019 struct ixgbe_vfta * shadow_vfta =
1020 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1021 struct ixgbe_hwstrip *hwstrip =
1022 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1023 struct ixgbe_dcb_config *dcb_config =
1024 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1025 struct ixgbe_filter_info *filter_info =
1026 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1031 PMD_INIT_FUNC_TRACE();
1033 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1034 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1035 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1038 * For secondary processes, we don't initialise any further as primary
1039 * has already done this work. Only check we don't need a different
1040 * RX and TX function.
1042 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1043 struct ixgbe_tx_queue *txq;
1044 /* TX queue function in primary, set by last queue initialized
1045 * Tx queue may not initialized by primary process */
1046 if (eth_dev->data->tx_queues) {
1047 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1048 ixgbe_set_tx_function(eth_dev, txq);
1050 /* Use default TX function if we get here */
1051 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1052 "Using default TX function.");
1055 ixgbe_set_rx_function(eth_dev);
1059 pci_dev = eth_dev->pci_dev;
1061 rte_eth_copy_pci_info(eth_dev, pci_dev);
1063 /* Vendor and Device ID need to be set before init of shared code */
1064 hw->device_id = pci_dev->id.device_id;
1065 hw->vendor_id = pci_dev->id.vendor_id;
1066 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1067 hw->allow_unsupported_sfp = 1;
1069 /* Initialize the shared code (base driver) */
1070 #ifdef RTE_NIC_BYPASS
1071 diag = ixgbe_bypass_init_shared_code(hw);
1073 diag = ixgbe_init_shared_code(hw);
1074 #endif /* RTE_NIC_BYPASS */
1076 if (diag != IXGBE_SUCCESS) {
1077 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1081 /* pick up the PCI bus settings for reporting later */
1082 ixgbe_get_bus_info(hw);
1084 /* Unlock any pending hardware semaphore */
1085 ixgbe_swfw_lock_reset(hw);
1087 /* Initialize DCB configuration*/
1088 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1089 ixgbe_dcb_init(hw,dcb_config);
1090 /* Get Hardware Flow Control setting */
1091 hw->fc.requested_mode = ixgbe_fc_full;
1092 hw->fc.current_mode = ixgbe_fc_full;
1093 hw->fc.pause_time = IXGBE_FC_PAUSE;
1094 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1095 hw->fc.low_water[i] = IXGBE_FC_LO;
1096 hw->fc.high_water[i] = IXGBE_FC_HI;
1098 hw->fc.send_xon = 1;
1100 /* Make sure we have a good EEPROM before we read from it */
1101 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1102 if (diag != IXGBE_SUCCESS) {
1103 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1107 #ifdef RTE_NIC_BYPASS
1108 diag = ixgbe_bypass_init_hw(hw);
1110 diag = ixgbe_init_hw(hw);
1111 #endif /* RTE_NIC_BYPASS */
1114 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1115 * is called too soon after the kernel driver unbinding/binding occurs.
1116 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1117 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1118 * also called. See ixgbe_identify_phy_82599(). The reason for the
1119 * failure is not known, and only occuts when virtualisation features
1120 * are disabled in the bios. A delay of 100ms was found to be enough by
1121 * trial-and-error, and is doubled to be safe.
1123 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1125 diag = ixgbe_init_hw(hw);
1128 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1129 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1130 "LOM. Please be aware there may be issues associated "
1131 "with your hardware.");
1132 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1133 "please contact your Intel or hardware representative "
1134 "who provided you with this hardware.");
1135 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1136 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1138 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1142 /* Reset the hw statistics */
1143 ixgbe_dev_stats_reset(eth_dev);
1145 /* disable interrupt */
1146 ixgbe_disable_intr(hw);
1148 /* reset mappings for queue statistics hw counters*/
1149 ixgbe_reset_qstat_mappings(hw);
1151 /* Allocate memory for storing MAC addresses */
1152 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1153 hw->mac.num_rar_entries, 0);
1154 if (eth_dev->data->mac_addrs == NULL) {
1156 "Failed to allocate %u bytes needed to store "
1158 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1161 /* Copy the permanent MAC address */
1162 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1163 ð_dev->data->mac_addrs[0]);
1165 /* Allocate memory for storing hash filter MAC addresses */
1166 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1167 IXGBE_VMDQ_NUM_UC_MAC, 0);
1168 if (eth_dev->data->hash_mac_addrs == NULL) {
1170 "Failed to allocate %d bytes needed to store MAC addresses",
1171 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1175 /* initialize the vfta */
1176 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1178 /* initialize the hw strip bitmap*/
1179 memset(hwstrip, 0, sizeof(*hwstrip));
1181 /* initialize PF if max_vfs not zero */
1182 ixgbe_pf_host_init(eth_dev);
1184 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1185 /* let hardware know driver is loaded */
1186 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1187 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1188 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1189 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1190 IXGBE_WRITE_FLUSH(hw);
1192 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1193 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1194 (int) hw->mac.type, (int) hw->phy.type,
1195 (int) hw->phy.sfp_type);
1197 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1198 (int) hw->mac.type, (int) hw->phy.type);
1200 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1201 eth_dev->data->port_id, pci_dev->id.vendor_id,
1202 pci_dev->id.device_id);
1204 rte_intr_callback_register(&pci_dev->intr_handle,
1205 ixgbe_dev_interrupt_handler,
1208 /* enable uio/vfio intr/eventfd mapping */
1209 rte_intr_enable(&pci_dev->intr_handle);
1211 /* enable support intr */
1212 ixgbe_enable_intr(eth_dev);
1214 /* initialize 5tuple filter list */
1215 TAILQ_INIT(&filter_info->fivetuple_list);
1216 memset(filter_info->fivetuple_mask, 0,
1217 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1223 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1225 struct rte_pci_device *pci_dev;
1226 struct ixgbe_hw *hw;
1228 PMD_INIT_FUNC_TRACE();
1230 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1233 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1234 pci_dev = eth_dev->pci_dev;
1236 if (hw->adapter_stopped == 0)
1237 ixgbe_dev_close(eth_dev);
1239 eth_dev->dev_ops = NULL;
1240 eth_dev->rx_pkt_burst = NULL;
1241 eth_dev->tx_pkt_burst = NULL;
1243 /* Unlock any pending hardware semaphore */
1244 ixgbe_swfw_lock_reset(hw);
1246 /* disable uio intr before callback unregister */
1247 rte_intr_disable(&(pci_dev->intr_handle));
1248 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1249 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1251 /* uninitialize PF if max_vfs not zero */
1252 ixgbe_pf_host_uninit(eth_dev);
1254 rte_free(eth_dev->data->mac_addrs);
1255 eth_dev->data->mac_addrs = NULL;
1257 rte_free(eth_dev->data->hash_mac_addrs);
1258 eth_dev->data->hash_mac_addrs = NULL;
1264 * Negotiate mailbox API version with the PF.
1265 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1266 * Then we try to negotiate starting with the most recent one.
1267 * If all negotiation attempts fail, then we will proceed with
1268 * the default one (ixgbe_mbox_api_10).
1271 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1275 /* start with highest supported, proceed down */
1276 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1283 i != RTE_DIM(sup_ver) &&
1284 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1290 generate_random_mac_addr(struct ether_addr *mac_addr)
1294 /* Set Organizationally Unique Identifier (OUI) prefix. */
1295 mac_addr->addr_bytes[0] = 0x00;
1296 mac_addr->addr_bytes[1] = 0x09;
1297 mac_addr->addr_bytes[2] = 0xC0;
1298 /* Force indication of locally assigned MAC address. */
1299 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1300 /* Generate the last 3 bytes of the MAC address with a random number. */
1301 random = rte_rand();
1302 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1306 * Virtual Function device init
1309 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1313 struct rte_pci_device *pci_dev;
1314 struct ixgbe_hw *hw =
1315 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1316 struct ixgbe_vfta * shadow_vfta =
1317 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1318 struct ixgbe_hwstrip *hwstrip =
1319 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1320 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1322 PMD_INIT_FUNC_TRACE();
1324 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1325 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1326 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1328 /* for secondary processes, we don't initialise any further as primary
1329 * has already done this work. Only check we don't need a different
1331 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1332 struct ixgbe_tx_queue *txq;
1333 /* TX queue function in primary, set by last queue initialized
1334 * Tx queue may not initialized by primary process
1336 if (eth_dev->data->tx_queues) {
1337 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1338 ixgbe_set_tx_function(eth_dev, txq);
1340 /* Use default TX function if we get here */
1341 PMD_INIT_LOG(NOTICE,
1342 "No TX queues configured yet. Using default TX function.");
1345 ixgbe_set_rx_function(eth_dev);
1350 pci_dev = eth_dev->pci_dev;
1352 rte_eth_copy_pci_info(eth_dev, pci_dev);
1354 hw->device_id = pci_dev->id.device_id;
1355 hw->vendor_id = pci_dev->id.vendor_id;
1356 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1358 /* initialize the vfta */
1359 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1361 /* initialize the hw strip bitmap*/
1362 memset(hwstrip, 0, sizeof(*hwstrip));
1364 /* Initialize the shared code (base driver) */
1365 diag = ixgbe_init_shared_code(hw);
1366 if (diag != IXGBE_SUCCESS) {
1367 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1371 /* init_mailbox_params */
1372 hw->mbx.ops.init_params(hw);
1374 /* Reset the hw statistics */
1375 ixgbevf_dev_stats_reset(eth_dev);
1377 /* Disable the interrupts for VF */
1378 ixgbevf_intr_disable(hw);
1380 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1381 diag = hw->mac.ops.reset_hw(hw);
1384 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1385 * the underlying PF driver has not assigned a MAC address to the VF.
1386 * In this case, assign a random MAC address.
1388 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1389 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1393 /* negotiate mailbox API version to use with the PF. */
1394 ixgbevf_negotiate_api(hw);
1396 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1397 ixgbevf_get_queues(hw, &tcs, &tc);
1399 /* Allocate memory for storing MAC addresses */
1400 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1401 hw->mac.num_rar_entries, 0);
1402 if (eth_dev->data->mac_addrs == NULL) {
1404 "Failed to allocate %u bytes needed to store "
1406 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1410 /* Generate a random MAC address, if none was assigned by PF. */
1411 if (is_zero_ether_addr(perm_addr)) {
1412 generate_random_mac_addr(perm_addr);
1413 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1415 rte_free(eth_dev->data->mac_addrs);
1416 eth_dev->data->mac_addrs = NULL;
1419 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1420 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1421 "%02x:%02x:%02x:%02x:%02x:%02x",
1422 perm_addr->addr_bytes[0],
1423 perm_addr->addr_bytes[1],
1424 perm_addr->addr_bytes[2],
1425 perm_addr->addr_bytes[3],
1426 perm_addr->addr_bytes[4],
1427 perm_addr->addr_bytes[5]);
1430 /* Copy the permanent MAC address */
1431 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1433 /* reset the hardware with the new settings */
1434 diag = hw->mac.ops.start_hw(hw);
1440 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1444 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1445 eth_dev->data->port_id, pci_dev->id.vendor_id,
1446 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1451 /* Virtual Function device uninit */
1454 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1456 struct ixgbe_hw *hw;
1458 PMD_INIT_FUNC_TRACE();
1460 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1463 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1465 if (hw->adapter_stopped == 0)
1466 ixgbevf_dev_close(eth_dev);
1468 eth_dev->dev_ops = NULL;
1469 eth_dev->rx_pkt_burst = NULL;
1470 eth_dev->tx_pkt_burst = NULL;
1472 /* Disable the interrupts for VF */
1473 ixgbevf_intr_disable(hw);
1475 rte_free(eth_dev->data->mac_addrs);
1476 eth_dev->data->mac_addrs = NULL;
1481 static struct eth_driver rte_ixgbe_pmd = {
1483 .name = "rte_ixgbe_pmd",
1484 .id_table = pci_id_ixgbe_map,
1485 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1486 RTE_PCI_DRV_DETACHABLE,
1488 .eth_dev_init = eth_ixgbe_dev_init,
1489 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1490 .dev_private_size = sizeof(struct ixgbe_adapter),
1494 * virtual function driver struct
1496 static struct eth_driver rte_ixgbevf_pmd = {
1498 .name = "rte_ixgbevf_pmd",
1499 .id_table = pci_id_ixgbevf_map,
1500 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1502 .eth_dev_init = eth_ixgbevf_dev_init,
1503 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1504 .dev_private_size = sizeof(struct ixgbe_adapter),
1508 * Driver initialization routine.
1509 * Invoked once at EAL init time.
1510 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1513 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1515 PMD_INIT_FUNC_TRACE();
1517 rte_eth_driver_register(&rte_ixgbe_pmd);
1522 * VF Driver initialization routine.
1523 * Invoked one at EAL init time.
1524 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1527 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1529 PMD_INIT_FUNC_TRACE();
1531 rte_eth_driver_register(&rte_ixgbevf_pmd);
1536 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1538 struct ixgbe_hw *hw =
1539 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1540 struct ixgbe_vfta * shadow_vfta =
1541 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1546 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1547 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1548 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1553 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1555 /* update local VFTA copy */
1556 shadow_vfta->vfta[vid_idx] = vfta;
1562 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1565 ixgbe_vlan_hw_strip_enable(dev, queue);
1567 ixgbe_vlan_hw_strip_disable(dev, queue);
1571 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1572 enum rte_vlan_type vlan_type,
1575 struct ixgbe_hw *hw =
1576 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1579 switch (vlan_type) {
1580 case ETH_VLAN_TYPE_INNER:
1581 /* Only the high 16-bits is valid */
1582 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1586 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
1594 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1596 struct ixgbe_hw *hw =
1597 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1600 PMD_INIT_FUNC_TRACE();
1602 /* Filter Table Disable */
1603 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1604 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1606 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1610 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1612 struct ixgbe_hw *hw =
1613 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1614 struct ixgbe_vfta * shadow_vfta =
1615 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1619 PMD_INIT_FUNC_TRACE();
1621 /* Filter Table Enable */
1622 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1623 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1624 vlnctrl |= IXGBE_VLNCTRL_VFE;
1626 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1628 /* write whatever is in local vfta copy */
1629 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1630 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1634 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1636 struct ixgbe_hwstrip *hwstrip =
1637 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1639 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1643 IXGBE_SET_HWSTRIP(hwstrip, queue);
1645 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1649 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1651 struct ixgbe_hw *hw =
1652 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1655 PMD_INIT_FUNC_TRACE();
1657 if (hw->mac.type == ixgbe_mac_82598EB) {
1658 /* No queue level support */
1659 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1663 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1664 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1665 ctrl &= ~IXGBE_RXDCTL_VME;
1666 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1668 /* record those setting for HW strip per queue */
1669 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1673 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1675 struct ixgbe_hw *hw =
1676 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1679 PMD_INIT_FUNC_TRACE();
1681 if (hw->mac.type == ixgbe_mac_82598EB) {
1682 /* No queue level supported */
1683 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1687 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1688 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1689 ctrl |= IXGBE_RXDCTL_VME;
1690 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1692 /* record those setting for HW strip per queue */
1693 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1697 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1699 struct ixgbe_hw *hw =
1700 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1704 PMD_INIT_FUNC_TRACE();
1706 if (hw->mac.type == ixgbe_mac_82598EB) {
1707 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1708 ctrl &= ~IXGBE_VLNCTRL_VME;
1709 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1712 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1713 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1714 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1715 ctrl &= ~IXGBE_RXDCTL_VME;
1716 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1718 /* record those setting for HW strip per queue */
1719 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1725 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1727 struct ixgbe_hw *hw =
1728 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1732 PMD_INIT_FUNC_TRACE();
1734 if (hw->mac.type == ixgbe_mac_82598EB) {
1735 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1736 ctrl |= IXGBE_VLNCTRL_VME;
1737 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1740 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1741 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1742 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1743 ctrl |= IXGBE_RXDCTL_VME;
1744 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1746 /* record those setting for HW strip per queue */
1747 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1753 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1755 struct ixgbe_hw *hw =
1756 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1759 PMD_INIT_FUNC_TRACE();
1761 /* DMATXCTRL: Geric Double VLAN Disable */
1762 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1763 ctrl &= ~IXGBE_DMATXCTL_GDV;
1764 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1766 /* CTRL_EXT: Global Double VLAN Disable */
1767 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1768 ctrl &= ~IXGBE_EXTENDED_VLAN;
1769 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1774 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1776 struct ixgbe_hw *hw =
1777 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1780 PMD_INIT_FUNC_TRACE();
1782 /* DMATXCTRL: Geric Double VLAN Enable */
1783 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1784 ctrl |= IXGBE_DMATXCTL_GDV;
1785 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1787 /* CTRL_EXT: Global Double VLAN Enable */
1788 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1789 ctrl |= IXGBE_EXTENDED_VLAN;
1790 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1792 /* Clear pooling mode of PFVTCTL. It's required by X550. */
1793 if (hw->mac.type == ixgbe_mac_X550 ||
1794 hw->mac.type == ixgbe_mac_X550EM_x ||
1795 hw->mac.type == ixgbe_mac_X550EM_a) {
1796 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1797 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1798 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1802 * VET EXT field in the EXVET register = 0x8100 by default
1803 * So no need to change. Same to VT field of DMATXCTL register
1808 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1810 if (mask & ETH_VLAN_STRIP_MASK) {
1811 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1812 ixgbe_vlan_hw_strip_enable_all(dev);
1814 ixgbe_vlan_hw_strip_disable_all(dev);
1817 if (mask & ETH_VLAN_FILTER_MASK) {
1818 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1819 ixgbe_vlan_hw_filter_enable(dev);
1821 ixgbe_vlan_hw_filter_disable(dev);
1824 if (mask & ETH_VLAN_EXTEND_MASK) {
1825 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1826 ixgbe_vlan_hw_extend_enable(dev);
1828 ixgbe_vlan_hw_extend_disable(dev);
1833 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1835 struct ixgbe_hw *hw =
1836 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1837 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1838 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1839 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1840 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1844 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1849 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1852 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1858 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1859 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1865 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1867 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1868 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1869 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1870 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1872 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1873 /* check multi-queue mode */
1874 switch (dev_conf->rxmode.mq_mode) {
1875 case ETH_MQ_RX_VMDQ_DCB:
1876 case ETH_MQ_RX_VMDQ_DCB_RSS:
1877 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1878 PMD_INIT_LOG(ERR, "SRIOV active,"
1879 " unsupported mq_mode rx %d.",
1880 dev_conf->rxmode.mq_mode);
1883 case ETH_MQ_RX_VMDQ_RSS:
1884 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1885 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1886 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1887 PMD_INIT_LOG(ERR, "SRIOV is active,"
1888 " invalid queue number"
1889 " for VMDQ RSS, allowed"
1890 " value are 1, 2 or 4.");
1894 case ETH_MQ_RX_VMDQ_ONLY:
1895 case ETH_MQ_RX_NONE:
1896 /* if nothing mq mode configure, use default scheme */
1897 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1898 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1899 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1901 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1902 /* SRIOV only works in VMDq enable mode */
1903 PMD_INIT_LOG(ERR, "SRIOV is active,"
1904 " wrong mq_mode rx %d.",
1905 dev_conf->rxmode.mq_mode);
1909 switch (dev_conf->txmode.mq_mode) {
1910 case ETH_MQ_TX_VMDQ_DCB:
1911 /* DCB VMDQ in SRIOV mode, not implement yet */
1912 PMD_INIT_LOG(ERR, "SRIOV is active,"
1913 " unsupported VMDQ mq_mode tx %d.",
1914 dev_conf->txmode.mq_mode);
1916 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1917 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1921 /* check valid queue number */
1922 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1923 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1924 PMD_INIT_LOG(ERR, "SRIOV is active,"
1925 " nb_rx_q=%d nb_tx_q=%d queue number"
1926 " must be less than or equal to %d.",
1928 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1932 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1933 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1937 /* check configuration for vmdb+dcb mode */
1938 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1939 const struct rte_eth_vmdq_dcb_conf *conf;
1941 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1942 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1943 IXGBE_VMDQ_DCB_NB_QUEUES);
1946 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1947 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1948 conf->nb_queue_pools == ETH_32_POOLS)) {
1949 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1950 " nb_queue_pools must be %d or %d.",
1951 ETH_16_POOLS, ETH_32_POOLS);
1955 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1956 const struct rte_eth_vmdq_dcb_tx_conf *conf;
1958 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1959 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1960 IXGBE_VMDQ_DCB_NB_QUEUES);
1963 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1964 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1965 conf->nb_queue_pools == ETH_32_POOLS)) {
1966 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1967 " nb_queue_pools != %d and"
1968 " nb_queue_pools != %d.",
1969 ETH_16_POOLS, ETH_32_POOLS);
1974 /* For DCB mode check our configuration before we go further */
1975 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1976 const struct rte_eth_dcb_rx_conf *conf;
1978 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1979 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1980 IXGBE_DCB_NB_QUEUES);
1983 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1984 if (!(conf->nb_tcs == ETH_4_TCS ||
1985 conf->nb_tcs == ETH_8_TCS)) {
1986 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1987 " and nb_tcs != %d.",
1988 ETH_4_TCS, ETH_8_TCS);
1993 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1994 const struct rte_eth_dcb_tx_conf *conf;
1996 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1997 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1998 IXGBE_DCB_NB_QUEUES);
2001 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2002 if (!(conf->nb_tcs == ETH_4_TCS ||
2003 conf->nb_tcs == ETH_8_TCS)) {
2004 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2005 " and nb_tcs != %d.",
2006 ETH_4_TCS, ETH_8_TCS);
2012 * When DCB/VT is off, maximum number of queues changes,
2013 * except for 82598EB, which remains constant.
2015 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2016 hw->mac.type != ixgbe_mac_82598EB) {
2017 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2019 "Neither VT nor DCB are enabled, "
2021 IXGBE_NONE_MODE_TX_NB_QUEUES);
2030 ixgbe_dev_configure(struct rte_eth_dev *dev)
2032 struct ixgbe_interrupt *intr =
2033 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2034 struct ixgbe_adapter *adapter =
2035 (struct ixgbe_adapter *)dev->data->dev_private;
2038 PMD_INIT_FUNC_TRACE();
2039 /* multipe queue mode checking */
2040 ret = ixgbe_check_mq_mode(dev);
2042 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2047 /* set flag to update link status after init */
2048 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2051 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2052 * allocation or vector Rx preconditions we will reset it.
2054 adapter->rx_bulk_alloc_allowed = true;
2055 adapter->rx_vec_allowed = true;
2061 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2063 struct ixgbe_hw *hw =
2064 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2065 struct ixgbe_interrupt *intr =
2066 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2069 /* only set up it on X550EM_X */
2070 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2071 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2072 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2073 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2074 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2075 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2080 * Configure device link speed and setup link.
2081 * It returns 0 on success.
2084 ixgbe_dev_start(struct rte_eth_dev *dev)
2086 struct ixgbe_hw *hw =
2087 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2088 struct ixgbe_vf_info *vfinfo =
2089 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2090 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2091 uint32_t intr_vector = 0;
2092 int err, link_up = 0, negotiate = 0;
2098 PMD_INIT_FUNC_TRACE();
2100 /* IXGBE devices don't support half duplex */
2101 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
2102 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
2103 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
2104 dev->data->dev_conf.link_duplex,
2105 dev->data->port_id);
2109 /* disable uio/vfio intr/eventfd mapping */
2110 rte_intr_disable(intr_handle);
2113 hw->adapter_stopped = 0;
2114 ixgbe_stop_adapter(hw);
2116 /* reinitialize adapter
2117 * this calls reset and start */
2118 status = ixgbe_pf_reset_hw(hw);
2121 hw->mac.ops.start_hw(hw);
2122 hw->mac.get_link_status = true;
2124 /* configure PF module if SRIOV enabled */
2125 ixgbe_pf_host_configure(dev);
2127 ixgbe_dev_phy_intr_setup(dev);
2129 /* check and configure queue intr-vector mapping */
2130 if ((rte_intr_cap_multiple(intr_handle) ||
2131 !RTE_ETH_DEV_SRIOV(dev).active) &&
2132 dev->data->dev_conf.intr_conf.rxq != 0) {
2133 intr_vector = dev->data->nb_rx_queues;
2134 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2135 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2136 IXGBE_MAX_INTR_QUEUE_NUM);
2139 if (rte_intr_efd_enable(intr_handle, intr_vector))
2143 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2144 intr_handle->intr_vec =
2145 rte_zmalloc("intr_vec",
2146 dev->data->nb_rx_queues * sizeof(int), 0);
2147 if (intr_handle->intr_vec == NULL) {
2148 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2149 " intr_vec\n", dev->data->nb_rx_queues);
2154 /* confiugre msix for sleep until rx interrupt */
2155 ixgbe_configure_msix(dev);
2157 /* initialize transmission unit */
2158 ixgbe_dev_tx_init(dev);
2160 /* This can fail when allocating mbufs for descriptor rings */
2161 err = ixgbe_dev_rx_init(dev);
2163 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2167 err = ixgbe_dev_rxtx_start(dev);
2169 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2173 /* Skip link setup if loopback mode is enabled for 82599. */
2174 if (hw->mac.type == ixgbe_mac_82599EB &&
2175 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2176 goto skip_link_setup;
2178 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2179 err = hw->mac.ops.setup_sfp(hw);
2184 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2185 /* Turn on the copper */
2186 ixgbe_set_phy_power(hw, true);
2188 /* Turn on the laser */
2189 ixgbe_enable_tx_laser(hw);
2192 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2195 dev->data->dev_link.link_status = link_up;
2197 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2201 switch(dev->data->dev_conf.link_speed) {
2202 case ETH_LINK_SPEED_AUTONEG:
2203 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2204 IXGBE_LINK_SPEED_82599_AUTONEG :
2205 IXGBE_LINK_SPEED_82598_AUTONEG;
2207 case ETH_LINK_SPEED_100:
2209 * Invalid for 82598 but error will be detected by
2210 * ixgbe_setup_link()
2212 speed = IXGBE_LINK_SPEED_100_FULL;
2214 case ETH_LINK_SPEED_1000:
2215 speed = IXGBE_LINK_SPEED_1GB_FULL;
2217 case ETH_LINK_SPEED_10000:
2218 speed = IXGBE_LINK_SPEED_10GB_FULL;
2221 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2222 dev->data->dev_conf.link_speed,
2223 dev->data->port_id);
2227 err = ixgbe_setup_link(hw, speed, link_up);
2233 if (rte_intr_allow_others(intr_handle)) {
2234 /* check if lsc interrupt is enabled */
2235 if (dev->data->dev_conf.intr_conf.lsc != 0)
2236 ixgbe_dev_lsc_interrupt_setup(dev);
2238 rte_intr_callback_unregister(intr_handle,
2239 ixgbe_dev_interrupt_handler,
2241 if (dev->data->dev_conf.intr_conf.lsc != 0)
2242 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2243 " no intr multiplex\n");
2246 /* check if rxq interrupt is enabled */
2247 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2248 rte_intr_dp_is_en(intr_handle))
2249 ixgbe_dev_rxq_interrupt_setup(dev);
2251 /* enable uio/vfio intr/eventfd mapping */
2252 rte_intr_enable(intr_handle);
2254 /* resume enabled intr since hw reset */
2255 ixgbe_enable_intr(dev);
2257 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2258 ETH_VLAN_EXTEND_MASK;
2259 ixgbe_vlan_offload_set(dev, mask);
2261 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2262 /* Enable vlan filtering for VMDq */
2263 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2266 /* Configure DCB hw */
2267 ixgbe_configure_dcb(dev);
2269 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2270 err = ixgbe_fdir_configure(dev);
2275 /* Restore vf rate limit */
2276 if (vfinfo != NULL) {
2277 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2278 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2279 if (vfinfo[vf].tx_rate[idx] != 0)
2280 ixgbe_set_vf_rate_limit(dev, vf,
2281 vfinfo[vf].tx_rate[idx],
2285 ixgbe_restore_statistics_mapping(dev);
2290 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2291 ixgbe_dev_clear_queues(dev);
2296 * Stop device: disable rx and tx functions to allow for reconfiguring.
2299 ixgbe_dev_stop(struct rte_eth_dev *dev)
2301 struct rte_eth_link link;
2302 struct ixgbe_hw *hw =
2303 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2304 struct ixgbe_vf_info *vfinfo =
2305 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2306 struct ixgbe_filter_info *filter_info =
2307 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2308 struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2309 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2312 PMD_INIT_FUNC_TRACE();
2314 /* disable interrupts */
2315 ixgbe_disable_intr(hw);
2318 ixgbe_pf_reset_hw(hw);
2319 hw->adapter_stopped = 0;
2322 ixgbe_stop_adapter(hw);
2324 for (vf = 0; vfinfo != NULL &&
2325 vf < dev->pci_dev->max_vfs; vf++)
2326 vfinfo[vf].clear_to_send = false;
2328 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2329 /* Turn off the copper */
2330 ixgbe_set_phy_power(hw, false);
2332 /* Turn off the laser */
2333 ixgbe_disable_tx_laser(hw);
2336 ixgbe_dev_clear_queues(dev);
2338 /* Clear stored conf */
2339 dev->data->scattered_rx = 0;
2342 /* Clear recorded link status */
2343 memset(&link, 0, sizeof(link));
2344 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2346 /* Remove all ntuple filters of the device */
2347 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2348 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2349 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2350 TAILQ_REMOVE(&filter_info->fivetuple_list,
2354 memset(filter_info->fivetuple_mask, 0,
2355 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2357 if (!rte_intr_allow_others(intr_handle))
2358 /* resume to the default handler */
2359 rte_intr_callback_register(intr_handle,
2360 ixgbe_dev_interrupt_handler,
2363 /* Clean datapath event and queue/vec mapping */
2364 rte_intr_efd_disable(intr_handle);
2365 if (intr_handle->intr_vec != NULL) {
2366 rte_free(intr_handle->intr_vec);
2367 intr_handle->intr_vec = NULL;
2372 * Set device link up: enable tx.
2375 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2377 struct ixgbe_hw *hw =
2378 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2379 if (hw->mac.type == ixgbe_mac_82599EB) {
2380 #ifdef RTE_NIC_BYPASS
2381 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2382 /* Not suported in bypass mode */
2383 PMD_INIT_LOG(ERR, "Set link up is not supported "
2384 "by device id 0x%x", hw->device_id);
2390 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2391 /* Turn on the copper */
2392 ixgbe_set_phy_power(hw, true);
2394 /* Turn on the laser */
2395 ixgbe_enable_tx_laser(hw);
2402 * Set device link down: disable tx.
2405 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2407 struct ixgbe_hw *hw =
2408 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2409 if (hw->mac.type == ixgbe_mac_82599EB) {
2410 #ifdef RTE_NIC_BYPASS
2411 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2412 /* Not suported in bypass mode */
2413 PMD_INIT_LOG(ERR, "Set link down is not supported "
2414 "by device id 0x%x", hw->device_id);
2420 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2421 /* Turn off the copper */
2422 ixgbe_set_phy_power(hw, false);
2424 /* Turn off the laser */
2425 ixgbe_disable_tx_laser(hw);
2432 * Reest and stop device.
2435 ixgbe_dev_close(struct rte_eth_dev *dev)
2437 struct ixgbe_hw *hw =
2438 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2440 PMD_INIT_FUNC_TRACE();
2442 ixgbe_pf_reset_hw(hw);
2444 ixgbe_dev_stop(dev);
2445 hw->adapter_stopped = 1;
2447 ixgbe_dev_free_queues(dev);
2449 ixgbe_disable_pcie_master(hw);
2451 /* reprogram the RAR[0] in case user changed it. */
2452 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2456 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2457 struct ixgbe_hw_stats *hw_stats,
2458 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2459 uint64_t *total_qprc, uint64_t *total_qprdc)
2461 uint32_t bprc, lxon, lxoff, total;
2462 uint32_t delta_gprc = 0;
2464 /* Workaround for RX byte count not including CRC bytes when CRC
2465 + * strip is enabled. CRC bytes are removed from counters when crc_strip
2468 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2469 IXGBE_HLREG0_RXCRCSTRP);
2471 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2472 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2473 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2474 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2476 for (i = 0; i < 8; i++) {
2478 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2479 /* global total per queue */
2480 hw_stats->mpc[i] += mp;
2481 /* Running comprehensive total for stats display */
2482 *total_missed_rx += hw_stats->mpc[i];
2483 if (hw->mac.type == ixgbe_mac_82598EB) {
2484 hw_stats->rnbc[i] +=
2485 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2486 hw_stats->pxonrxc[i] +=
2487 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2488 hw_stats->pxoffrxc[i] +=
2489 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2491 hw_stats->pxonrxc[i] +=
2492 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2493 hw_stats->pxoffrxc[i] +=
2494 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2495 hw_stats->pxon2offc[i] +=
2496 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2498 hw_stats->pxontxc[i] +=
2499 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2500 hw_stats->pxofftxc[i] +=
2501 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2503 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2504 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2505 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2506 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2508 delta_gprc += delta_qprc;
2510 hw_stats->qprc[i] += delta_qprc;
2511 hw_stats->qptc[i] += delta_qptc;
2513 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2514 hw_stats->qbrc[i] +=
2515 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2517 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2519 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2520 hw_stats->qbtc[i] +=
2521 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2523 hw_stats->qprdc[i] += delta_qprdc;
2524 *total_qprdc += hw_stats->qprdc[i];
2526 *total_qprc += hw_stats->qprc[i];
2527 *total_qbrc += hw_stats->qbrc[i];
2529 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2530 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2531 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2534 * An errata states that gprc actually counts good + missed packets:
2535 * Workaround to set gprc to summated queue packet receives
2537 hw_stats->gprc = *total_qprc;
2539 if (hw->mac.type != ixgbe_mac_82598EB) {
2540 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2541 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2542 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2543 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2544 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2545 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2546 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2547 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2549 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2550 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2551 /* 82598 only has a counter in the high register */
2552 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2553 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2554 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2556 uint64_t old_tpr = hw_stats->tpr;
2558 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2559 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2562 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2564 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2565 hw_stats->gptc += delta_gptc;
2566 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2567 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2570 * Workaround: mprc hardware is incorrectly counting
2571 * broadcasts, so for now we subtract those.
2573 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2574 hw_stats->bprc += bprc;
2575 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2576 if (hw->mac.type == ixgbe_mac_82598EB)
2577 hw_stats->mprc -= bprc;
2579 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2580 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2581 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2582 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2583 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2584 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2586 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2587 hw_stats->lxontxc += lxon;
2588 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2589 hw_stats->lxofftxc += lxoff;
2590 total = lxon + lxoff;
2592 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2593 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2594 hw_stats->gptc -= total;
2595 hw_stats->mptc -= total;
2596 hw_stats->ptc64 -= total;
2597 hw_stats->gotc -= total * ETHER_MIN_LEN;
2599 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2600 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2601 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2602 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2603 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2604 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2605 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2606 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2607 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2608 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2609 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2610 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2611 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2612 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2613 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2614 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2615 /* Only read FCOE on 82599 */
2616 if (hw->mac.type != ixgbe_mac_82598EB) {
2617 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2618 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2619 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2620 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2621 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2624 /* Flow Director Stats registers */
2625 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2626 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2630 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2633 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2635 struct ixgbe_hw *hw =
2636 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2637 struct ixgbe_hw_stats *hw_stats =
2638 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2639 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2642 total_missed_rx = 0;
2647 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2648 &total_qprc, &total_qprdc);
2653 /* Fill out the rte_eth_stats statistics structure */
2654 stats->ipackets = total_qprc;
2655 stats->ibytes = total_qbrc;
2656 stats->opackets = hw_stats->gptc;
2657 stats->obytes = hw_stats->gotc;
2659 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2660 stats->q_ipackets[i] = hw_stats->qprc[i];
2661 stats->q_opackets[i] = hw_stats->qptc[i];
2662 stats->q_ibytes[i] = hw_stats->qbrc[i];
2663 stats->q_obytes[i] = hw_stats->qbtc[i];
2664 stats->q_errors[i] = hw_stats->qprdc[i];
2668 stats->imissed = total_missed_rx;
2669 stats->ierrors = hw_stats->crcerrs +
2685 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2687 struct ixgbe_hw_stats *stats =
2688 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2690 /* HW registers are cleared on read */
2691 ixgbe_dev_stats_get(dev, NULL);
2693 /* Reset software totals */
2694 memset(stats, 0, sizeof(*stats));
2697 /* This function calculates the number of xstats based on the current config */
2699 ixgbe_xstats_calc_num(void) {
2700 return IXGBE_NB_HW_STATS + (IXGBE_NB_RXQ_PRIO_STATS * 8) +
2701 (IXGBE_NB_TXQ_PRIO_STATS * 8);
2705 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2708 struct ixgbe_hw *hw =
2709 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2710 struct ixgbe_hw_stats *hw_stats =
2711 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2712 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2713 unsigned i, stat, count = 0;
2715 count = ixgbe_xstats_calc_num();
2720 total_missed_rx = 0;
2725 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2726 &total_qprc, &total_qprdc);
2728 /* If this is a reset xstats is NULL, and we have cleared the
2729 * registers by reading them.
2734 /* Extended stats from ixgbe_hw_stats */
2736 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2737 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2738 rte_ixgbe_stats_strings[i].name);
2739 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2740 rte_ixgbe_stats_strings[i].offset);
2744 /* RX Priority Stats */
2745 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2746 for (i = 0; i < 8; i++) {
2747 snprintf(xstats[count].name, sizeof(xstats[count].name),
2748 "rx_priority%u_%s", i,
2749 rte_ixgbe_rxq_strings[stat].name);
2750 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2751 rte_ixgbe_rxq_strings[stat].offset +
2752 (sizeof(uint64_t) * i));
2757 /* TX Priority Stats */
2758 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2759 for (i = 0; i < 8; i++) {
2760 snprintf(xstats[count].name, sizeof(xstats[count].name),
2761 "tx_priority%u_%s", i,
2762 rte_ixgbe_txq_strings[stat].name);
2763 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2764 rte_ixgbe_txq_strings[stat].offset +
2765 (sizeof(uint64_t) * i));
2774 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2776 struct ixgbe_hw_stats *stats =
2777 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2779 unsigned count = ixgbe_xstats_calc_num();
2781 /* HW registers are cleared on read */
2782 ixgbe_dev_xstats_get(dev, NULL, count);
2784 /* Reset software totals */
2785 memset(stats, 0, sizeof(*stats));
2789 ixgbevf_update_stats(struct rte_eth_dev *dev)
2791 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2792 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2793 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2795 /* Good Rx packet, include VF loopback */
2796 UPDATE_VF_STAT(IXGBE_VFGPRC,
2797 hw_stats->last_vfgprc, hw_stats->vfgprc);
2799 /* Good Rx octets, include VF loopback */
2800 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2801 hw_stats->last_vfgorc, hw_stats->vfgorc);
2803 /* Good Tx packet, include VF loopback */
2804 UPDATE_VF_STAT(IXGBE_VFGPTC,
2805 hw_stats->last_vfgptc, hw_stats->vfgptc);
2807 /* Good Tx octets, include VF loopback */
2808 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2809 hw_stats->last_vfgotc, hw_stats->vfgotc);
2811 /* Rx Multicst Packet */
2812 UPDATE_VF_STAT(IXGBE_VFMPRC,
2813 hw_stats->last_vfmprc, hw_stats->vfmprc);
2817 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2820 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2821 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2824 if (n < IXGBEVF_NB_XSTATS)
2825 return IXGBEVF_NB_XSTATS;
2827 ixgbevf_update_stats(dev);
2832 /* Extended stats */
2833 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2834 snprintf(xstats[i].name, sizeof(xstats[i].name),
2835 "%s", rte_ixgbevf_stats_strings[i].name);
2836 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2837 rte_ixgbevf_stats_strings[i].offset);
2840 return IXGBEVF_NB_XSTATS;
2844 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2846 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2847 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2849 ixgbevf_update_stats(dev);
2854 stats->ipackets = hw_stats->vfgprc;
2855 stats->ibytes = hw_stats->vfgorc;
2856 stats->opackets = hw_stats->vfgptc;
2857 stats->obytes = hw_stats->vfgotc;
2858 stats->imcasts = hw_stats->vfmprc;
2859 /* stats->imcasts should be removed as imcasts is deprecated */
2863 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2865 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2866 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2868 /* Sync HW register to the last stats */
2869 ixgbevf_dev_stats_get(dev, NULL);
2871 /* reset HW current stats*/
2872 hw_stats->vfgprc = 0;
2873 hw_stats->vfgorc = 0;
2874 hw_stats->vfgptc = 0;
2875 hw_stats->vfgotc = 0;
2876 hw_stats->vfmprc = 0;
2881 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2883 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2884 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2886 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2887 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2888 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
2890 * When DCB/VT is off, maximum number of queues changes,
2891 * except for 82598EB, which remains constant.
2893 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2894 hw->mac.type != ixgbe_mac_82598EB)
2895 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
2897 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2898 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2899 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2900 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2901 dev_info->max_vfs = dev->pci_dev->max_vfs;
2902 if (hw->mac.type == ixgbe_mac_82598EB)
2903 dev_info->max_vmdq_pools = ETH_16_POOLS;
2905 dev_info->max_vmdq_pools = ETH_64_POOLS;
2906 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2907 dev_info->rx_offload_capa =
2908 DEV_RX_OFFLOAD_VLAN_STRIP |
2909 DEV_RX_OFFLOAD_IPV4_CKSUM |
2910 DEV_RX_OFFLOAD_UDP_CKSUM |
2911 DEV_RX_OFFLOAD_TCP_CKSUM;
2914 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2917 if ((hw->mac.type == ixgbe_mac_82599EB ||
2918 hw->mac.type == ixgbe_mac_X540) &&
2919 !RTE_ETH_DEV_SRIOV(dev).active)
2920 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2922 if (hw->mac.type == ixgbe_mac_X550 ||
2923 hw->mac.type == ixgbe_mac_X550EM_x ||
2924 hw->mac.type == ixgbe_mac_X550EM_a)
2925 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2927 dev_info->tx_offload_capa =
2928 DEV_TX_OFFLOAD_VLAN_INSERT |
2929 DEV_TX_OFFLOAD_IPV4_CKSUM |
2930 DEV_TX_OFFLOAD_UDP_CKSUM |
2931 DEV_TX_OFFLOAD_TCP_CKSUM |
2932 DEV_TX_OFFLOAD_SCTP_CKSUM |
2933 DEV_TX_OFFLOAD_TCP_TSO;
2935 if (hw->mac.type == ixgbe_mac_X550 ||
2936 hw->mac.type == ixgbe_mac_X550EM_x ||
2937 hw->mac.type == ixgbe_mac_X550EM_a)
2938 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2940 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2942 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2943 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2944 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2946 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2950 dev_info->default_txconf = (struct rte_eth_txconf) {
2952 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2953 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2954 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2956 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2957 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2958 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2959 ETH_TXQ_FLAGS_NOOFFLOADS,
2962 dev_info->rx_desc_lim = rx_desc_lim;
2963 dev_info->tx_desc_lim = tx_desc_lim;
2965 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2966 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2967 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2970 static const uint32_t *
2971 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2973 static const uint32_t ptypes[] = {
2974 /* For non-vec functions,
2975 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
2976 * for vec functions,
2977 * refers to _recv_raw_pkts_vec().
2981 RTE_PTYPE_L3_IPV4_EXT,
2983 RTE_PTYPE_L3_IPV6_EXT,
2987 RTE_PTYPE_TUNNEL_IP,
2988 RTE_PTYPE_INNER_L3_IPV6,
2989 RTE_PTYPE_INNER_L3_IPV6_EXT,
2990 RTE_PTYPE_INNER_L4_TCP,
2991 RTE_PTYPE_INNER_L4_UDP,
2995 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
2996 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
2997 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
2998 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3004 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3005 struct rte_eth_dev_info *dev_info)
3007 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3009 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3010 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3011 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3012 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3013 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3014 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3015 dev_info->max_vfs = dev->pci_dev->max_vfs;
3016 if (hw->mac.type == ixgbe_mac_82598EB)
3017 dev_info->max_vmdq_pools = ETH_16_POOLS;
3019 dev_info->max_vmdq_pools = ETH_64_POOLS;
3020 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3021 DEV_RX_OFFLOAD_IPV4_CKSUM |
3022 DEV_RX_OFFLOAD_UDP_CKSUM |
3023 DEV_RX_OFFLOAD_TCP_CKSUM;
3024 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3025 DEV_TX_OFFLOAD_IPV4_CKSUM |
3026 DEV_TX_OFFLOAD_UDP_CKSUM |
3027 DEV_TX_OFFLOAD_TCP_CKSUM |
3028 DEV_TX_OFFLOAD_SCTP_CKSUM |
3029 DEV_TX_OFFLOAD_TCP_TSO;
3031 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3033 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3034 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3035 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3037 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3041 dev_info->default_txconf = (struct rte_eth_txconf) {
3043 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3044 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3045 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3047 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3048 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3049 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3050 ETH_TXQ_FLAGS_NOOFFLOADS,
3053 dev_info->rx_desc_lim = rx_desc_lim;
3054 dev_info->tx_desc_lim = tx_desc_lim;
3057 /* return 0 means link status changed, -1 means not changed */
3059 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3061 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3062 struct rte_eth_link link, old;
3063 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3067 link.link_status = ETH_LINK_DOWN;
3068 link.link_speed = 0;
3069 link.link_duplex = 0;
3070 memset(&old, 0, sizeof(old));
3071 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3073 hw->mac.get_link_status = true;
3075 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3076 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3077 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3079 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3082 link.link_speed = ETH_LINK_SPEED_100;
3083 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3084 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3085 if (link.link_status == old.link_status)
3091 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3092 if (link.link_status == old.link_status)
3096 link.link_status = ETH_LINK_UP;
3097 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3099 switch (link_speed) {
3101 case IXGBE_LINK_SPEED_UNKNOWN:
3102 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3103 link.link_speed = ETH_LINK_SPEED_100;
3106 case IXGBE_LINK_SPEED_100_FULL:
3107 link.link_speed = ETH_LINK_SPEED_100;
3110 case IXGBE_LINK_SPEED_1GB_FULL:
3111 link.link_speed = ETH_LINK_SPEED_1000;
3114 case IXGBE_LINK_SPEED_10GB_FULL:
3115 link.link_speed = ETH_LINK_SPEED_10000;
3118 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3120 if (link.link_status == old.link_status)
3127 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3129 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3132 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3133 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3134 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3138 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3140 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3143 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3144 fctrl &= (~IXGBE_FCTRL_UPE);
3145 if (dev->data->all_multicast == 1)
3146 fctrl |= IXGBE_FCTRL_MPE;
3148 fctrl &= (~IXGBE_FCTRL_MPE);
3149 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3153 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3155 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3158 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3159 fctrl |= IXGBE_FCTRL_MPE;
3160 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3164 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3166 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3169 if (dev->data->promiscuous == 1)
3170 return; /* must remain in all_multicast mode */
3172 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3173 fctrl &= (~IXGBE_FCTRL_MPE);
3174 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3178 * It clears the interrupt causes and enables the interrupt.
3179 * It will be called once only during nic initialized.
3182 * Pointer to struct rte_eth_dev.
3185 * - On success, zero.
3186 * - On failure, a negative value.
3189 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3191 struct ixgbe_interrupt *intr =
3192 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3194 ixgbe_dev_link_status_print(dev);
3195 intr->mask |= IXGBE_EICR_LSC;
3201 * It clears the interrupt causes and enables the interrupt.
3202 * It will be called once only during nic initialized.
3205 * Pointer to struct rte_eth_dev.
3208 * - On success, zero.
3209 * - On failure, a negative value.
3212 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3214 struct ixgbe_interrupt *intr =
3215 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3217 intr->mask |= IXGBE_EICR_RTX_QUEUE;
3223 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3226 * Pointer to struct rte_eth_dev.
3229 * - On success, zero.
3230 * - On failure, a negative value.
3233 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3236 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3237 struct ixgbe_interrupt *intr =
3238 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3240 /* clear all cause mask */
3241 ixgbe_disable_intr(hw);
3243 /* read-on-clear nic registers here */
3244 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3245 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3249 /* set flag for async link update */
3250 if (eicr & IXGBE_EICR_LSC)
3251 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3253 if (eicr & IXGBE_EICR_MAILBOX)
3254 intr->flags |= IXGBE_FLAG_MAILBOX;
3256 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3257 hw->phy.type == ixgbe_phy_x550em_ext_t &&
3258 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3259 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3265 * It gets and then prints the link status.
3268 * Pointer to struct rte_eth_dev.
3271 * - On success, zero.
3272 * - On failure, a negative value.
3275 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3277 struct rte_eth_link link;
3279 memset(&link, 0, sizeof(link));
3280 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3281 if (link.link_status) {
3282 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3283 (int)(dev->data->port_id),
3284 (unsigned)link.link_speed,
3285 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3286 "full-duplex" : "half-duplex");
3288 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3289 (int)(dev->data->port_id));
3291 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3292 dev->pci_dev->addr.domain,
3293 dev->pci_dev->addr.bus,
3294 dev->pci_dev->addr.devid,
3295 dev->pci_dev->addr.function);
3299 * It executes link_update after knowing an interrupt occurred.
3302 * Pointer to struct rte_eth_dev.
3305 * - On success, zero.
3306 * - On failure, a negative value.
3309 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3311 struct ixgbe_interrupt *intr =
3312 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3314 struct rte_eth_link link;
3315 int intr_enable_delay = false;
3316 struct ixgbe_hw *hw =
3317 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3319 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3321 if (intr->flags & IXGBE_FLAG_MAILBOX) {
3322 ixgbe_pf_mbx_process(dev);
3323 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3326 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3327 ixgbe_handle_lasi(hw);
3328 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3331 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3332 /* get the link status before link update, for predicting later */
3333 memset(&link, 0, sizeof(link));
3334 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3336 ixgbe_dev_link_update(dev, 0);
3339 if (!link.link_status)
3340 /* handle it 1 sec later, wait it being stable */
3341 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3342 /* likely to down */
3344 /* handle it 4 sec later, wait it being stable */
3345 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3347 ixgbe_dev_link_status_print(dev);
3349 intr_enable_delay = true;
3352 if (intr_enable_delay) {
3353 if (rte_eal_alarm_set(timeout * 1000,
3354 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3355 PMD_DRV_LOG(ERR, "Error setting alarm");
3357 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3358 ixgbe_enable_intr(dev);
3359 rte_intr_enable(&(dev->pci_dev->intr_handle));
3367 * Interrupt handler which shall be registered for alarm callback for delayed
3368 * handling specific interrupt to wait for the stable nic state. As the
3369 * NIC interrupt state is not stable for ixgbe after link is just down,
3370 * it needs to wait 4 seconds to get the stable status.
3373 * Pointer to interrupt handle.
3375 * The address of parameter (struct rte_eth_dev *) regsitered before.
3381 ixgbe_dev_interrupt_delayed_handler(void *param)
3383 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3384 struct ixgbe_interrupt *intr =
3385 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3386 struct ixgbe_hw *hw =
3387 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3390 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3391 if (eicr & IXGBE_EICR_MAILBOX)
3392 ixgbe_pf_mbx_process(dev);
3394 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3395 ixgbe_handle_lasi(hw);
3396 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3399 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3400 ixgbe_dev_link_update(dev, 0);
3401 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3402 ixgbe_dev_link_status_print(dev);
3403 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3406 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3407 ixgbe_enable_intr(dev);
3408 rte_intr_enable(&(dev->pci_dev->intr_handle));
3412 * Interrupt handler triggered by NIC for handling
3413 * specific interrupt.
3416 * Pointer to interrupt handle.
3418 * The address of parameter (struct rte_eth_dev *) regsitered before.
3424 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3427 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3429 ixgbe_dev_interrupt_get_status(dev);
3430 ixgbe_dev_interrupt_action(dev);
3434 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3436 struct ixgbe_hw *hw;
3438 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3439 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3443 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3445 struct ixgbe_hw *hw;
3447 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3448 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3452 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3454 struct ixgbe_hw *hw;
3460 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3462 fc_conf->pause_time = hw->fc.pause_time;
3463 fc_conf->high_water = hw->fc.high_water[0];
3464 fc_conf->low_water = hw->fc.low_water[0];
3465 fc_conf->send_xon = hw->fc.send_xon;
3466 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3469 * Return rx_pause status according to actual setting of
3472 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3473 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3479 * Return tx_pause status according to actual setting of
3482 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3483 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3488 if (rx_pause && tx_pause)
3489 fc_conf->mode = RTE_FC_FULL;
3491 fc_conf->mode = RTE_FC_RX_PAUSE;
3493 fc_conf->mode = RTE_FC_TX_PAUSE;
3495 fc_conf->mode = RTE_FC_NONE;
3501 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3503 struct ixgbe_hw *hw;
3505 uint32_t rx_buf_size;
3506 uint32_t max_high_water;
3508 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3515 PMD_INIT_FUNC_TRACE();
3517 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3518 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3519 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3522 * At least reserve one Ethernet frame for watermark
3523 * high_water/low_water in kilo bytes for ixgbe
3525 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3526 if ((fc_conf->high_water > max_high_water) ||
3527 (fc_conf->high_water < fc_conf->low_water)) {
3528 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3529 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3533 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3534 hw->fc.pause_time = fc_conf->pause_time;
3535 hw->fc.high_water[0] = fc_conf->high_water;
3536 hw->fc.low_water[0] = fc_conf->low_water;
3537 hw->fc.send_xon = fc_conf->send_xon;
3538 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3540 err = ixgbe_fc_enable(hw);
3542 /* Not negotiated is not an error case */
3543 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3545 /* check if we want to forward MAC frames - driver doesn't have native
3546 * capability to do that, so we'll write the registers ourselves */
3548 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3550 /* set or clear MFLCN.PMCF bit depending on configuration */
3551 if (fc_conf->mac_ctrl_frame_fwd != 0)
3552 mflcn |= IXGBE_MFLCN_PMCF;
3554 mflcn &= ~IXGBE_MFLCN_PMCF;
3556 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3557 IXGBE_WRITE_FLUSH(hw);
3562 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3567 * ixgbe_pfc_enable_generic - Enable flow control
3568 * @hw: pointer to hardware structure
3569 * @tc_num: traffic class number
3570 * Enable flow control according to the current settings.
3573 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3576 uint32_t mflcn_reg, fccfg_reg;
3578 uint32_t fcrtl, fcrth;
3582 /* Validate the water mark configuration */
3583 if (!hw->fc.pause_time) {
3584 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3588 /* Low water mark of zero causes XOFF floods */
3589 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3590 /* High/Low water can not be 0 */
3591 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3592 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3593 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3597 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3598 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3599 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3603 /* Negotiate the fc mode to use */
3604 ixgbe_fc_autoneg(hw);
3606 /* Disable any previous flow control settings */
3607 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3608 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3610 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3611 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3613 switch (hw->fc.current_mode) {
3616 * If the count of enabled RX Priority Flow control >1,
3617 * and the TX pause can not be disabled
3620 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3621 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3622 if (reg & IXGBE_FCRTH_FCEN)
3626 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3628 case ixgbe_fc_rx_pause:
3630 * Rx Flow control is enabled and Tx Flow control is
3631 * disabled by software override. Since there really
3632 * isn't a way to advertise that we are capable of RX
3633 * Pause ONLY, we will advertise that we support both
3634 * symmetric and asymmetric Rx PAUSE. Later, we will
3635 * disable the adapter's ability to send PAUSE frames.
3637 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3639 * If the count of enabled RX Priority Flow control >1,
3640 * and the TX pause can not be disabled
3643 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3644 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3645 if (reg & IXGBE_FCRTH_FCEN)
3649 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3651 case ixgbe_fc_tx_pause:
3653 * Tx Flow control is enabled, and Rx Flow control is
3654 * disabled by software override.
3656 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3659 /* Flow control (both Rx and Tx) is enabled by SW override. */
3660 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3661 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3664 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3665 ret_val = IXGBE_ERR_CONFIG;
3670 /* Set 802.3x based flow control settings. */
3671 mflcn_reg |= IXGBE_MFLCN_DPF;
3672 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3673 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3675 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3676 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3677 hw->fc.high_water[tc_num]) {
3678 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3679 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3680 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3682 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3684 * In order to prevent Tx hangs when the internal Tx
3685 * switch is enabled we must set the high water mark
3686 * to the maximum FCRTH value. This allows the Tx
3687 * switch to function even under heavy Rx workloads.
3689 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3691 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3693 /* Configure pause time (2 TCs per register) */
3694 reg = hw->fc.pause_time * 0x00010001;
3695 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3696 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3698 /* Configure flow control refresh threshold value */
3699 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3706 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3708 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3709 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3711 if (hw->mac.type != ixgbe_mac_82598EB) {
3712 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3718 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3721 uint32_t rx_buf_size;
3722 uint32_t max_high_water;
3724 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3725 struct ixgbe_hw *hw =
3726 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3727 struct ixgbe_dcb_config *dcb_config =
3728 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3730 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3737 PMD_INIT_FUNC_TRACE();
3739 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3740 tc_num = map[pfc_conf->priority];
3741 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3742 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3744 * At least reserve one Ethernet frame for watermark
3745 * high_water/low_water in kilo bytes for ixgbe
3747 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3748 if ((pfc_conf->fc.high_water > max_high_water) ||
3749 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3750 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3751 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3755 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3756 hw->fc.pause_time = pfc_conf->fc.pause_time;
3757 hw->fc.send_xon = pfc_conf->fc.send_xon;
3758 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
3759 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3761 err = ixgbe_dcb_pfc_enable(dev,tc_num);
3763 /* Not negotiated is not an error case */
3764 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3767 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3772 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3773 struct rte_eth_rss_reta_entry64 *reta_conf,
3776 uint16_t i, sp_reta_size;
3779 uint16_t idx, shift;
3780 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3783 PMD_INIT_FUNC_TRACE();
3785 if (!ixgbe_rss_update_sp(hw->mac.type)) {
3786 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3791 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3792 if (reta_size != sp_reta_size) {
3793 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3794 "(%d) doesn't match the number hardware can supported "
3795 "(%d)\n", reta_size, sp_reta_size);
3799 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3800 idx = i / RTE_RETA_GROUP_SIZE;
3801 shift = i % RTE_RETA_GROUP_SIZE;
3802 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3806 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3807 if (mask == IXGBE_4_BIT_MASK)
3810 r = IXGBE_READ_REG(hw, reta_reg);
3811 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3812 if (mask & (0x1 << j))
3813 reta |= reta_conf[idx].reta[shift + j] <<
3816 reta |= r & (IXGBE_8_BIT_MASK <<
3819 IXGBE_WRITE_REG(hw, reta_reg, reta);
3826 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3827 struct rte_eth_rss_reta_entry64 *reta_conf,
3830 uint16_t i, sp_reta_size;
3833 uint16_t idx, shift;
3834 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3837 PMD_INIT_FUNC_TRACE();
3838 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3839 if (reta_size != sp_reta_size) {
3840 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3841 "(%d) doesn't match the number hardware can supported "
3842 "(%d)\n", reta_size, sp_reta_size);
3846 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3847 idx = i / RTE_RETA_GROUP_SIZE;
3848 shift = i % RTE_RETA_GROUP_SIZE;
3849 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3854 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3855 reta = IXGBE_READ_REG(hw, reta_reg);
3856 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3857 if (mask & (0x1 << j))
3858 reta_conf[idx].reta[shift + j] =
3859 ((reta >> (CHAR_BIT * j)) &
3868 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3869 uint32_t index, uint32_t pool)
3871 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3872 uint32_t enable_addr = 1;
3874 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3878 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3880 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3882 ixgbe_clear_rar(hw, index);
3886 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3888 ixgbe_remove_rar(dev, 0);
3890 ixgbe_add_rar(dev, addr, 0, 0);
3894 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3898 struct ixgbe_hw *hw;
3899 struct rte_eth_dev_info dev_info;
3900 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3902 ixgbe_dev_info_get(dev, &dev_info);
3904 /* check that mtu is within the allowed range */
3905 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3908 /* refuse mtu that requires the support of scattered packets when this
3909 * feature has not been enabled before. */
3910 if (!dev->data->scattered_rx &&
3911 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3912 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3915 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3916 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3918 /* switch to jumbo mode if needed */
3919 if (frame_size > ETHER_MAX_LEN) {
3920 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3921 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3923 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3924 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3926 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3928 /* update max frame size */
3929 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3931 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3932 maxfrs &= 0x0000FFFF;
3933 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3934 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3940 * Virtual Function operations
3943 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3945 PMD_INIT_FUNC_TRACE();
3947 /* Clear interrupt mask to stop from interrupts being generated */
3948 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3950 IXGBE_WRITE_FLUSH(hw);
3954 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3956 PMD_INIT_FUNC_TRACE();
3958 /* VF enable interrupt autoclean */
3959 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3960 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3961 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3963 IXGBE_WRITE_FLUSH(hw);
3967 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3969 struct rte_eth_conf* conf = &dev->data->dev_conf;
3970 struct ixgbe_adapter *adapter =
3971 (struct ixgbe_adapter *)dev->data->dev_private;
3973 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3974 dev->data->port_id);
3977 * VF has no ability to enable/disable HW CRC
3978 * Keep the persistent behavior the same as Host PF
3980 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3981 if (!conf->rxmode.hw_strip_crc) {
3982 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3983 conf->rxmode.hw_strip_crc = 1;
3986 if (conf->rxmode.hw_strip_crc) {
3987 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3988 conf->rxmode.hw_strip_crc = 0;
3993 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3994 * allocation or vector Rx preconditions we will reset it.
3996 adapter->rx_bulk_alloc_allowed = true;
3997 adapter->rx_vec_allowed = true;
4003 ixgbevf_dev_start(struct rte_eth_dev *dev)
4005 struct ixgbe_hw *hw =
4006 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4007 uint32_t intr_vector = 0;
4008 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4012 PMD_INIT_FUNC_TRACE();
4014 hw->mac.ops.reset_hw(hw);
4015 hw->mac.get_link_status = true;
4017 /* negotiate mailbox API version to use with the PF. */
4018 ixgbevf_negotiate_api(hw);
4020 ixgbevf_dev_tx_init(dev);
4022 /* This can fail when allocating mbufs for descriptor rings */
4023 err = ixgbevf_dev_rx_init(dev);
4025 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4026 ixgbe_dev_clear_queues(dev);
4031 ixgbevf_set_vfta_all(dev,1);
4034 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
4035 ETH_VLAN_EXTEND_MASK;
4036 ixgbevf_vlan_offload_set(dev, mask);
4038 ixgbevf_dev_rxtx_start(dev);
4040 /* check and configure queue intr-vector mapping */
4041 if (dev->data->dev_conf.intr_conf.rxq != 0) {
4042 intr_vector = dev->data->nb_rx_queues;
4043 if (rte_intr_efd_enable(intr_handle, intr_vector))
4047 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4048 intr_handle->intr_vec =
4049 rte_zmalloc("intr_vec",
4050 dev->data->nb_rx_queues * sizeof(int), 0);
4051 if (intr_handle->intr_vec == NULL) {
4052 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4053 " intr_vec\n", dev->data->nb_rx_queues);
4057 ixgbevf_configure_msix(dev);
4059 rte_intr_enable(intr_handle);
4061 /* Re-enable interrupt for VF */
4062 ixgbevf_intr_enable(hw);
4068 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4070 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4071 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4073 PMD_INIT_FUNC_TRACE();
4075 hw->adapter_stopped = 1;
4076 ixgbe_stop_adapter(hw);
4079 * Clear what we set, but we still keep shadow_vfta to
4080 * restore after device starts
4082 ixgbevf_set_vfta_all(dev,0);
4084 /* Clear stored conf */
4085 dev->data->scattered_rx = 0;
4087 ixgbe_dev_clear_queues(dev);
4089 /* Clean datapath event and queue/vec mapping */
4090 rte_intr_efd_disable(intr_handle);
4091 if (intr_handle->intr_vec != NULL) {
4092 rte_free(intr_handle->intr_vec);
4093 intr_handle->intr_vec = NULL;
4098 ixgbevf_dev_close(struct rte_eth_dev *dev)
4100 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4102 PMD_INIT_FUNC_TRACE();
4106 ixgbevf_dev_stop(dev);
4108 ixgbe_dev_free_queues(dev);
4111 * Remove the VF MAC address ro ensure
4112 * that the VF traffic goes to the PF
4113 * after stop, close and detach of the VF
4115 ixgbevf_remove_mac_addr(dev, 0);
4118 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4120 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4121 struct ixgbe_vfta * shadow_vfta =
4122 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4123 int i = 0, j = 0, vfta = 0, mask = 1;
4125 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
4126 vfta = shadow_vfta->vfta[i];
4129 for (j = 0; j < 32; j++){
4131 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
4140 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4142 struct ixgbe_hw *hw =
4143 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4144 struct ixgbe_vfta * shadow_vfta =
4145 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4146 uint32_t vid_idx = 0;
4147 uint32_t vid_bit = 0;
4150 PMD_INIT_FUNC_TRACE();
4152 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4153 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4155 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4158 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4159 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4161 /* Save what we set and retore it after device reset */
4163 shadow_vfta->vfta[vid_idx] |= vid_bit;
4165 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4171 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4173 struct ixgbe_hw *hw =
4174 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4177 PMD_INIT_FUNC_TRACE();
4179 if (queue >= hw->mac.max_rx_queues)
4182 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4184 ctrl |= IXGBE_RXDCTL_VME;
4186 ctrl &= ~IXGBE_RXDCTL_VME;
4187 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4189 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4193 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4195 struct ixgbe_hw *hw =
4196 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4200 /* VF function only support hw strip feature, others are not support */
4201 if (mask & ETH_VLAN_STRIP_MASK) {
4202 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4204 for (i = 0; i < hw->mac.max_rx_queues; i++)
4205 ixgbevf_vlan_strip_queue_set(dev,i,on);
4210 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4214 /* we only need to do this if VMDq is enabled */
4215 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4216 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4217 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4225 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4227 uint32_t vector = 0;
4228 switch (hw->mac.mc_filter_type) {
4229 case 0: /* use bits [47:36] of the address */
4230 vector = ((uc_addr->addr_bytes[4] >> 4) |
4231 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4233 case 1: /* use bits [46:35] of the address */
4234 vector = ((uc_addr->addr_bytes[4] >> 3) |
4235 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4237 case 2: /* use bits [45:34] of the address */
4238 vector = ((uc_addr->addr_bytes[4] >> 2) |
4239 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4241 case 3: /* use bits [43:32] of the address */
4242 vector = ((uc_addr->addr_bytes[4]) |
4243 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4245 default: /* Invalid mc_filter_type */
4249 /* vector can only be 12-bits or boundary will be exceeded */
4255 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4263 const uint32_t ixgbe_uta_idx_mask = 0x7F;
4264 const uint32_t ixgbe_uta_bit_shift = 5;
4265 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4266 const uint32_t bit1 = 0x1;
4268 struct ixgbe_hw *hw =
4269 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4270 struct ixgbe_uta_info *uta_info =
4271 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4273 /* The UTA table only exists on 82599 hardware and newer */
4274 if (hw->mac.type < ixgbe_mac_82599EB)
4277 vector = ixgbe_uta_vector(hw,mac_addr);
4278 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4279 uta_shift = vector & ixgbe_uta_bit_mask;
4281 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4285 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4287 uta_info->uta_in_use++;
4288 reg_val |= (bit1 << uta_shift);
4289 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4291 uta_info->uta_in_use--;
4292 reg_val &= ~(bit1 << uta_shift);
4293 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4296 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4298 if (uta_info->uta_in_use > 0)
4299 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4300 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4302 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4308 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4311 struct ixgbe_hw *hw =
4312 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4313 struct ixgbe_uta_info *uta_info =
4314 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4316 /* The UTA table only exists on 82599 hardware and newer */
4317 if (hw->mac.type < ixgbe_mac_82599EB)
4321 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4322 uta_info->uta_shadow[i] = ~0;
4323 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4326 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4327 uta_info->uta_shadow[i] = 0;
4328 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4336 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4338 uint32_t new_val = orig_val;
4340 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4341 new_val |= IXGBE_VMOLR_AUPE;
4342 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4343 new_val |= IXGBE_VMOLR_ROMPE;
4344 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4345 new_val |= IXGBE_VMOLR_ROPE;
4346 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4347 new_val |= IXGBE_VMOLR_BAM;
4348 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4349 new_val |= IXGBE_VMOLR_MPE;
4355 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4356 uint16_t rx_mask, uint8_t on)
4360 struct ixgbe_hw *hw =
4361 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4362 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4364 if (hw->mac.type == ixgbe_mac_82598EB) {
4365 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4366 " on 82599 hardware and newer");
4369 if (ixgbe_vmdq_mode_check(hw) < 0)
4372 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4379 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4385 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4389 const uint8_t bit1 = 0x1;
4391 struct ixgbe_hw *hw =
4392 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4394 if (ixgbe_vmdq_mode_check(hw) < 0)
4397 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4398 reg = IXGBE_READ_REG(hw, addr);
4406 IXGBE_WRITE_REG(hw, addr,reg);
4412 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4416 const uint8_t bit1 = 0x1;
4418 struct ixgbe_hw *hw =
4419 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4421 if (ixgbe_vmdq_mode_check(hw) < 0)
4424 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4425 reg = IXGBE_READ_REG(hw, addr);
4433 IXGBE_WRITE_REG(hw, addr,reg);
4439 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4440 uint64_t pool_mask, uint8_t vlan_on)
4444 struct ixgbe_hw *hw =
4445 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4447 if (ixgbe_vmdq_mode_check(hw) < 0)
4449 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4450 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4451 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4460 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
4461 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
4462 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
4463 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
4464 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4465 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4466 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4469 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4470 struct rte_eth_mirror_conf *mirror_conf,
4471 uint8_t rule_id, uint8_t on)
4473 uint32_t mr_ctl,vlvf;
4474 uint32_t mp_lsb = 0;
4475 uint32_t mv_msb = 0;
4476 uint32_t mv_lsb = 0;
4477 uint32_t mp_msb = 0;
4480 uint64_t vlan_mask = 0;
4482 const uint8_t pool_mask_offset = 32;
4483 const uint8_t vlan_mask_offset = 32;
4484 const uint8_t dst_pool_offset = 8;
4485 const uint8_t rule_mr_offset = 4;
4486 const uint8_t mirror_rule_mask= 0x0F;
4488 struct ixgbe_mirror_info *mr_info =
4489 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4490 struct ixgbe_hw *hw =
4491 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4492 uint8_t mirror_type = 0;
4494 if (ixgbe_vmdq_mode_check(hw) < 0)
4497 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4500 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4501 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4502 mirror_conf->rule_type);
4506 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4507 mirror_type |= IXGBE_MRCTL_VLME;
4508 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4509 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4510 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4511 /* search vlan id related pool vlan filter index */
4512 reg_index = ixgbe_find_vlvf_slot(hw,
4513 mirror_conf->vlan.vlan_id[i]);
4516 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4517 if ((vlvf & IXGBE_VLVF_VIEN) &&
4518 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4519 mirror_conf->vlan.vlan_id[i]))
4520 vlan_mask |= (1ULL << reg_index);
4527 mv_lsb = vlan_mask & 0xFFFFFFFF;
4528 mv_msb = vlan_mask >> vlan_mask_offset;
4530 mr_info->mr_conf[rule_id].vlan.vlan_mask =
4531 mirror_conf->vlan.vlan_mask;
4532 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4533 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4534 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4535 mirror_conf->vlan.vlan_id[i];
4540 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4541 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4542 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4547 * if enable pool mirror, write related pool mask register,if disable
4548 * pool mirror, clear PFMRVM register
4550 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4551 mirror_type |= IXGBE_MRCTL_VPME;
4553 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4554 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4555 mr_info->mr_conf[rule_id].pool_mask =
4556 mirror_conf->pool_mask;
4561 mr_info->mr_conf[rule_id].pool_mask = 0;
4564 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4565 mirror_type |= IXGBE_MRCTL_UPME;
4566 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4567 mirror_type |= IXGBE_MRCTL_DPME;
4569 /* read mirror control register and recalculate it */
4570 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4573 mr_ctl |= mirror_type;
4574 mr_ctl &= mirror_rule_mask;
4575 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4577 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4579 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4580 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4582 /* write mirrror control register */
4583 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4585 /* write pool mirrror control register */
4586 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4587 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4588 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4591 /* write VLAN mirrror control register */
4592 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4593 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4594 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4602 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4605 uint32_t lsb_val = 0;
4606 uint32_t msb_val = 0;
4607 const uint8_t rule_mr_offset = 4;
4609 struct ixgbe_hw *hw =
4610 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4611 struct ixgbe_mirror_info *mr_info =
4612 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4614 if (ixgbe_vmdq_mode_check(hw) < 0)
4617 memset(&mr_info->mr_conf[rule_id], 0,
4618 sizeof(struct rte_eth_mirror_conf));
4620 /* clear PFVMCTL register */
4621 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4623 /* clear pool mask register */
4624 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4625 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4627 /* clear vlan mask register */
4628 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4629 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4635 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4638 struct ixgbe_hw *hw =
4639 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4641 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4642 mask |= (1 << IXGBE_MISC_VEC_ID);
4643 RTE_SET_USED(queue_id);
4644 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4646 rte_intr_enable(&dev->pci_dev->intr_handle);
4652 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4655 struct ixgbe_hw *hw =
4656 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4658 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4659 mask &= ~(1 << IXGBE_MISC_VEC_ID);
4660 RTE_SET_USED(queue_id);
4661 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4667 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4670 struct ixgbe_hw *hw =
4671 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4672 struct ixgbe_interrupt *intr =
4673 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4675 if (queue_id < 16) {
4676 ixgbe_disable_intr(hw);
4677 intr->mask |= (1 << queue_id);
4678 ixgbe_enable_intr(dev);
4679 } else if (queue_id < 32) {
4680 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4681 mask &= (1 << queue_id);
4682 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4683 } else if (queue_id < 64) {
4684 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4685 mask &= (1 << (queue_id - 32));
4686 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4688 rte_intr_enable(&dev->pci_dev->intr_handle);
4694 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4697 struct ixgbe_hw *hw =
4698 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4699 struct ixgbe_interrupt *intr =
4700 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4702 if (queue_id < 16) {
4703 ixgbe_disable_intr(hw);
4704 intr->mask &= ~(1 << queue_id);
4705 ixgbe_enable_intr(dev);
4706 } else if (queue_id < 32) {
4707 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4708 mask &= ~(1 << queue_id);
4709 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4710 } else if (queue_id < 64) {
4711 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4712 mask &= ~(1 << (queue_id - 32));
4713 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4720 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4721 uint8_t queue, uint8_t msix_vector)
4725 if (direction == -1) {
4727 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4728 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4731 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4733 /* rx or tx cause */
4734 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4735 idx = ((16 * (queue & 1)) + (8 * direction));
4736 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4737 tmp &= ~(0xFF << idx);
4738 tmp |= (msix_vector << idx);
4739 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4744 * set the IVAR registers, mapping interrupt causes to vectors
4746 * pointer to ixgbe_hw struct
4748 * 0 for Rx, 1 for Tx, -1 for other causes
4750 * queue to map the corresponding interrupt to
4752 * the vector to map to the corresponding queue
4755 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4756 uint8_t queue, uint8_t msix_vector)
4760 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4761 if (hw->mac.type == ixgbe_mac_82598EB) {
4762 if (direction == -1)
4764 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4765 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4766 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4767 tmp |= (msix_vector << (8 * (queue & 0x3)));
4768 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4769 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4770 (hw->mac.type == ixgbe_mac_X540)) {
4771 if (direction == -1) {
4773 idx = ((queue & 1) * 8);
4774 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4775 tmp &= ~(0xFF << idx);
4776 tmp |= (msix_vector << idx);
4777 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4779 /* rx or tx causes */
4780 idx = ((16 * (queue & 1)) + (8 * direction));
4781 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4782 tmp &= ~(0xFF << idx);
4783 tmp |= (msix_vector << idx);
4784 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4790 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4792 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4793 struct ixgbe_hw *hw =
4794 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4796 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4798 /* won't configure msix register if no mapping is done
4799 * between intr vector and event fd.
4801 if (!rte_intr_dp_is_en(intr_handle))
4804 /* Configure all RX queues of VF */
4805 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4806 /* Force all queue use vector 0,
4807 * as IXGBE_VF_MAXMSIVECOTR = 1
4809 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4810 intr_handle->intr_vec[q_idx] = vector_idx;
4813 /* Configure VF other cause ivar */
4814 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4818 * Sets up the hardware to properly generate MSI-X interrupts
4820 * board private structure
4823 ixgbe_configure_msix(struct rte_eth_dev *dev)
4825 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4826 struct ixgbe_hw *hw =
4827 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4828 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4829 uint32_t vec = IXGBE_MISC_VEC_ID;
4833 /* won't configure msix register if no mapping is done
4834 * between intr vector and event fd
4836 if (!rte_intr_dp_is_en(intr_handle))
4839 if (rte_intr_allow_others(intr_handle))
4840 vec = base = IXGBE_RX_VEC_START;
4842 /* setup GPIE for MSI-x mode */
4843 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4844 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4845 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4846 /* auto clearing and auto setting corresponding bits in EIMS
4847 * when MSI-X interrupt is triggered
4849 if (hw->mac.type == ixgbe_mac_82598EB) {
4850 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4852 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4853 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4855 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4857 /* Populate the IVAR table and set the ITR values to the
4858 * corresponding register.
4860 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4862 /* by default, 1:1 mapping */
4863 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4864 intr_handle->intr_vec[queue_id] = vec;
4865 if (vec < base + intr_handle->nb_efd - 1)
4869 switch (hw->mac.type) {
4870 case ixgbe_mac_82598EB:
4871 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4874 case ixgbe_mac_82599EB:
4875 case ixgbe_mac_X540:
4876 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4881 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4882 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4884 /* set up to autoclear timer, and the vectors */
4885 mask = IXGBE_EIMS_ENABLE_MASK;
4886 mask &= ~(IXGBE_EIMS_OTHER |
4887 IXGBE_EIMS_MAILBOX |
4890 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4893 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4894 uint16_t queue_idx, uint16_t tx_rate)
4896 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4897 uint32_t rf_dec, rf_int;
4899 uint16_t link_speed = dev->data->dev_link.link_speed;
4901 if (queue_idx >= hw->mac.max_tx_queues)
4905 /* Calculate the rate factor values to set */
4906 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4907 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4908 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4910 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4911 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4912 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4913 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4919 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4920 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4923 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4924 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4925 IXGBE_MAX_JUMBO_FRAME_SIZE))
4926 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4927 IXGBE_MMW_SIZE_JUMBO_FRAME);
4929 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4930 IXGBE_MMW_SIZE_DEFAULT);
4932 /* Set RTTBCNRC of queue X */
4933 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4934 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4935 IXGBE_WRITE_FLUSH(hw);
4940 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4941 uint16_t tx_rate, uint64_t q_msk)
4943 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4944 struct ixgbe_vf_info *vfinfo =
4945 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4946 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4947 uint32_t queue_stride =
4948 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4949 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4950 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4951 uint16_t total_rate = 0;
4953 if (queue_end >= hw->mac.max_tx_queues)
4956 if (vfinfo != NULL) {
4957 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4960 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4962 total_rate += vfinfo[vf_idx].tx_rate[idx];
4967 /* Store tx_rate for this vf. */
4968 for (idx = 0; idx < nb_q_per_pool; idx++) {
4969 if (((uint64_t)0x1 << idx) & q_msk) {
4970 if (vfinfo[vf].tx_rate[idx] != tx_rate)
4971 vfinfo[vf].tx_rate[idx] = tx_rate;
4972 total_rate += tx_rate;
4976 if (total_rate > dev->data->dev_link.link_speed) {
4978 * Reset stored TX rate of the VF if it causes exceed
4981 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4985 /* Set RTTBCNRC of each queue/pool for vf X */
4986 for (; queue_idx <= queue_end; queue_idx++) {
4988 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4996 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4997 __attribute__((unused)) uint32_t index,
4998 __attribute__((unused)) uint32_t pool)
5000 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5004 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5005 * operation. Trap this case to avoid exhausting the [very limited]
5006 * set of PF resources used to store VF MAC addresses.
5008 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5010 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5013 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5017 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5019 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5020 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5021 struct ether_addr *mac_addr;
5026 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5027 * not support the deletion of a given MAC address.
5028 * Instead, it imposes to delete all MAC addresses, then to add again
5029 * all MAC addresses with the exception of the one to be deleted.
5031 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5034 * Add again all MAC addresses, with the exception of the deleted one
5035 * and of the permanent MAC address.
5037 for (i = 0, mac_addr = dev->data->mac_addrs;
5038 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5039 /* Skip the deleted MAC address */
5042 /* Skip NULL MAC addresses */
5043 if (is_zero_ether_addr(mac_addr))
5045 /* Skip the permanent MAC address */
5046 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5048 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5051 "Adding again MAC address "
5052 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5054 mac_addr->addr_bytes[0],
5055 mac_addr->addr_bytes[1],
5056 mac_addr->addr_bytes[2],
5057 mac_addr->addr_bytes[3],
5058 mac_addr->addr_bytes[4],
5059 mac_addr->addr_bytes[5],
5065 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5067 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5069 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5072 #define MAC_TYPE_FILTER_SUP(type) do {\
5073 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5074 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5075 (type) != ixgbe_mac_X550EM_a)\
5080 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5081 struct rte_eth_syn_filter *filter,
5084 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5087 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5090 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5093 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5095 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5096 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5098 if (filter->hig_pri)
5099 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5101 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5103 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5105 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5107 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5108 IXGBE_WRITE_FLUSH(hw);
5113 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5114 struct rte_eth_syn_filter *filter)
5116 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5117 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5119 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5120 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5121 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5128 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5129 enum rte_filter_op filter_op,
5132 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5135 MAC_TYPE_FILTER_SUP(hw->mac.type);
5137 if (filter_op == RTE_ETH_FILTER_NOP)
5141 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5146 switch (filter_op) {
5147 case RTE_ETH_FILTER_ADD:
5148 ret = ixgbe_syn_filter_set(dev,
5149 (struct rte_eth_syn_filter *)arg,
5152 case RTE_ETH_FILTER_DELETE:
5153 ret = ixgbe_syn_filter_set(dev,
5154 (struct rte_eth_syn_filter *)arg,
5157 case RTE_ETH_FILTER_GET:
5158 ret = ixgbe_syn_filter_get(dev,
5159 (struct rte_eth_syn_filter *)arg);
5162 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5171 static inline enum ixgbe_5tuple_protocol
5172 convert_protocol_type(uint8_t protocol_value)
5174 if (protocol_value == IPPROTO_TCP)
5175 return IXGBE_FILTER_PROTOCOL_TCP;
5176 else if (protocol_value == IPPROTO_UDP)
5177 return IXGBE_FILTER_PROTOCOL_UDP;
5178 else if (protocol_value == IPPROTO_SCTP)
5179 return IXGBE_FILTER_PROTOCOL_SCTP;
5181 return IXGBE_FILTER_PROTOCOL_NONE;
5185 * add a 5tuple filter
5188 * dev: Pointer to struct rte_eth_dev.
5189 * index: the index the filter allocates.
5190 * filter: ponter to the filter that will be added.
5191 * rx_queue: the queue id the filter assigned to.
5194 * - On success, zero.
5195 * - On failure, a negative value.
5198 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5199 struct ixgbe_5tuple_filter *filter)
5201 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5202 struct ixgbe_filter_info *filter_info =
5203 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5205 uint32_t ftqf, sdpqf;
5206 uint32_t l34timir = 0;
5207 uint8_t mask = 0xff;
5210 * look for an unused 5tuple filter index,
5211 * and insert the filter to list.
5213 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5214 idx = i / (sizeof(uint32_t) * NBBY);
5215 shift = i % (sizeof(uint32_t) * NBBY);
5216 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5217 filter_info->fivetuple_mask[idx] |= 1 << shift;
5219 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5225 if (i >= IXGBE_MAX_FTQF_FILTERS) {
5226 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5230 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5231 IXGBE_SDPQF_DSTPORT_SHIFT);
5232 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5234 ftqf = (uint32_t)(filter->filter_info.proto &
5235 IXGBE_FTQF_PROTOCOL_MASK);
5236 ftqf |= (uint32_t)((filter->filter_info.priority &
5237 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5238 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5239 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5240 if (filter->filter_info.dst_ip_mask == 0)
5241 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5242 if (filter->filter_info.src_port_mask == 0)
5243 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5244 if (filter->filter_info.dst_port_mask == 0)
5245 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5246 if (filter->filter_info.proto_mask == 0)
5247 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5248 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5249 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5250 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5252 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5253 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5254 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5255 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5257 l34timir |= IXGBE_L34T_IMIR_RESERVE;
5258 l34timir |= (uint32_t)(filter->queue <<
5259 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5260 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5265 * remove a 5tuple filter
5268 * dev: Pointer to struct rte_eth_dev.
5269 * filter: the pointer of the filter will be removed.
5272 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5273 struct ixgbe_5tuple_filter *filter)
5275 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5276 struct ixgbe_filter_info *filter_info =
5277 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5278 uint16_t index = filter->index;
5280 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5281 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5282 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5285 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5286 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5287 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5288 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5289 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5293 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5295 struct ixgbe_hw *hw;
5296 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5298 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5300 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5303 /* refuse mtu that requires the support of scattered packets when this
5304 * feature has not been enabled before. */
5305 if (!dev->data->scattered_rx &&
5306 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5307 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5311 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5312 * request of the version 2.0 of the mailbox API.
5313 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5314 * of the mailbox API.
5315 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5316 * prior to 3.11.33 which contains the following change:
5317 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5319 ixgbevf_rlpml_set_vf(hw, max_frame);
5321 /* update max frame size */
5322 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5326 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
5327 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5331 static inline struct ixgbe_5tuple_filter *
5332 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5333 struct ixgbe_5tuple_filter_info *key)
5335 struct ixgbe_5tuple_filter *it;
5337 TAILQ_FOREACH(it, filter_list, entries) {
5338 if (memcmp(key, &it->filter_info,
5339 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5346 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5348 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5349 struct ixgbe_5tuple_filter_info *filter_info)
5351 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5352 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5353 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5356 switch (filter->dst_ip_mask) {
5358 filter_info->dst_ip_mask = 0;
5359 filter_info->dst_ip = filter->dst_ip;
5362 filter_info->dst_ip_mask = 1;
5365 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5369 switch (filter->src_ip_mask) {
5371 filter_info->src_ip_mask = 0;
5372 filter_info->src_ip = filter->src_ip;
5375 filter_info->src_ip_mask = 1;
5378 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5382 switch (filter->dst_port_mask) {
5384 filter_info->dst_port_mask = 0;
5385 filter_info->dst_port = filter->dst_port;
5388 filter_info->dst_port_mask = 1;
5391 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5395 switch (filter->src_port_mask) {
5397 filter_info->src_port_mask = 0;
5398 filter_info->src_port = filter->src_port;
5401 filter_info->src_port_mask = 1;
5404 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5408 switch (filter->proto_mask) {
5410 filter_info->proto_mask = 0;
5411 filter_info->proto =
5412 convert_protocol_type(filter->proto);
5415 filter_info->proto_mask = 1;
5418 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5422 filter_info->priority = (uint8_t)filter->priority;
5427 * add or delete a ntuple filter
5430 * dev: Pointer to struct rte_eth_dev.
5431 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5432 * add: if true, add filter, if false, remove filter
5435 * - On success, zero.
5436 * - On failure, a negative value.
5439 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5440 struct rte_eth_ntuple_filter *ntuple_filter,
5443 struct ixgbe_filter_info *filter_info =
5444 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5445 struct ixgbe_5tuple_filter_info filter_5tuple;
5446 struct ixgbe_5tuple_filter *filter;
5449 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5450 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5454 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5455 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5459 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5461 if (filter != NULL && add) {
5462 PMD_DRV_LOG(ERR, "filter exists.");
5465 if (filter == NULL && !add) {
5466 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5471 filter = rte_zmalloc("ixgbe_5tuple_filter",
5472 sizeof(struct ixgbe_5tuple_filter), 0);
5475 (void)rte_memcpy(&filter->filter_info,
5477 sizeof(struct ixgbe_5tuple_filter_info));
5478 filter->queue = ntuple_filter->queue;
5479 ret = ixgbe_add_5tuple_filter(dev, filter);
5485 ixgbe_remove_5tuple_filter(dev, filter);
5491 * get a ntuple filter
5494 * dev: Pointer to struct rte_eth_dev.
5495 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5498 * - On success, zero.
5499 * - On failure, a negative value.
5502 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5503 struct rte_eth_ntuple_filter *ntuple_filter)
5505 struct ixgbe_filter_info *filter_info =
5506 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5507 struct ixgbe_5tuple_filter_info filter_5tuple;
5508 struct ixgbe_5tuple_filter *filter;
5511 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5512 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5516 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5517 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5521 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5523 if (filter == NULL) {
5524 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5527 ntuple_filter->queue = filter->queue;
5532 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5533 * @dev: pointer to rte_eth_dev structure
5534 * @filter_op:operation will be taken.
5535 * @arg: a pointer to specific structure corresponding to the filter_op
5538 * - On success, zero.
5539 * - On failure, a negative value.
5542 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5543 enum rte_filter_op filter_op,
5546 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5549 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5551 if (filter_op == RTE_ETH_FILTER_NOP)
5555 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5560 switch (filter_op) {
5561 case RTE_ETH_FILTER_ADD:
5562 ret = ixgbe_add_del_ntuple_filter(dev,
5563 (struct rte_eth_ntuple_filter *)arg,
5566 case RTE_ETH_FILTER_DELETE:
5567 ret = ixgbe_add_del_ntuple_filter(dev,
5568 (struct rte_eth_ntuple_filter *)arg,
5571 case RTE_ETH_FILTER_GET:
5572 ret = ixgbe_get_ntuple_filter(dev,
5573 (struct rte_eth_ntuple_filter *)arg);
5576 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5584 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5589 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5590 if (filter_info->ethertype_filters[i] == ethertype &&
5591 (filter_info->ethertype_mask & (1 << i)))
5598 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5603 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5604 if (!(filter_info->ethertype_mask & (1 << i))) {
5605 filter_info->ethertype_mask |= 1 << i;
5606 filter_info->ethertype_filters[i] = ethertype;
5614 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5617 if (idx >= IXGBE_MAX_ETQF_FILTERS)
5619 filter_info->ethertype_mask &= ~(1 << idx);
5620 filter_info->ethertype_filters[idx] = 0;
5625 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5626 struct rte_eth_ethertype_filter *filter,
5629 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5630 struct ixgbe_filter_info *filter_info =
5631 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5636 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5639 if (filter->ether_type == ETHER_TYPE_IPv4 ||
5640 filter->ether_type == ETHER_TYPE_IPv6) {
5641 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5642 " ethertype filter.", filter->ether_type);
5646 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5647 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5650 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5651 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5655 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5656 if (ret >= 0 && add) {
5657 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5658 filter->ether_type);
5661 if (ret < 0 && !add) {
5662 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5663 filter->ether_type);
5668 ret = ixgbe_ethertype_filter_insert(filter_info,
5669 filter->ether_type);
5671 PMD_DRV_LOG(ERR, "ethertype filters are full.");
5674 etqf = IXGBE_ETQF_FILTER_EN;
5675 etqf |= (uint32_t)filter->ether_type;
5676 etqs |= (uint32_t)((filter->queue <<
5677 IXGBE_ETQS_RX_QUEUE_SHIFT) &
5678 IXGBE_ETQS_RX_QUEUE);
5679 etqs |= IXGBE_ETQS_QUEUE_EN;
5681 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5685 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5686 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5687 IXGBE_WRITE_FLUSH(hw);
5693 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5694 struct rte_eth_ethertype_filter *filter)
5696 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5697 struct ixgbe_filter_info *filter_info =
5698 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5699 uint32_t etqf, etqs;
5702 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5704 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5705 filter->ether_type);
5709 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5710 if (etqf & IXGBE_ETQF_FILTER_EN) {
5711 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5712 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5714 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5715 IXGBE_ETQS_RX_QUEUE_SHIFT;
5722 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5723 * @dev: pointer to rte_eth_dev structure
5724 * @filter_op:operation will be taken.
5725 * @arg: a pointer to specific structure corresponding to the filter_op
5728 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5729 enum rte_filter_op filter_op,
5732 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5735 MAC_TYPE_FILTER_SUP(hw->mac.type);
5737 if (filter_op == RTE_ETH_FILTER_NOP)
5741 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5746 switch (filter_op) {
5747 case RTE_ETH_FILTER_ADD:
5748 ret = ixgbe_add_del_ethertype_filter(dev,
5749 (struct rte_eth_ethertype_filter *)arg,
5752 case RTE_ETH_FILTER_DELETE:
5753 ret = ixgbe_add_del_ethertype_filter(dev,
5754 (struct rte_eth_ethertype_filter *)arg,
5757 case RTE_ETH_FILTER_GET:
5758 ret = ixgbe_get_ethertype_filter(dev,
5759 (struct rte_eth_ethertype_filter *)arg);
5762 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5770 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5771 enum rte_filter_type filter_type,
5772 enum rte_filter_op filter_op,
5777 switch (filter_type) {
5778 case RTE_ETH_FILTER_NTUPLE:
5779 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5781 case RTE_ETH_FILTER_ETHERTYPE:
5782 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5784 case RTE_ETH_FILTER_SYN:
5785 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5787 case RTE_ETH_FILTER_FDIR:
5788 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5790 case RTE_ETH_FILTER_L2_TUNNEL:
5791 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5794 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5803 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5804 u8 **mc_addr_ptr, u32 *vmdq)
5809 mc_addr = *mc_addr_ptr;
5810 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5815 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5816 struct ether_addr *mc_addr_set,
5817 uint32_t nb_mc_addr)
5819 struct ixgbe_hw *hw;
5822 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5823 mc_addr_list = (u8 *)mc_addr_set;
5824 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5825 ixgbe_dev_addr_list_itr, TRUE);
5829 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5831 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5832 uint64_t systime_cycles;
5834 switch (hw->mac.type) {
5835 case ixgbe_mac_X550:
5836 case ixgbe_mac_X550EM_x:
5837 case ixgbe_mac_X550EM_a:
5838 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5839 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5840 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5844 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5845 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5849 return systime_cycles;
5853 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5855 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5856 uint64_t rx_tstamp_cycles;
5858 switch (hw->mac.type) {
5859 case ixgbe_mac_X550:
5860 case ixgbe_mac_X550EM_x:
5861 case ixgbe_mac_X550EM_a:
5862 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5863 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5864 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5868 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5869 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5870 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5874 return rx_tstamp_cycles;
5878 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5880 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5881 uint64_t tx_tstamp_cycles;
5883 switch (hw->mac.type) {
5884 case ixgbe_mac_X550:
5885 case ixgbe_mac_X550EM_x:
5886 case ixgbe_mac_X550EM_a:
5887 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5888 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5889 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5893 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5894 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5895 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5899 return tx_tstamp_cycles;
5903 ixgbe_start_timecounters(struct rte_eth_dev *dev)
5905 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5906 struct ixgbe_adapter *adapter =
5907 (struct ixgbe_adapter *)dev->data->dev_private;
5908 struct rte_eth_link link;
5909 uint32_t incval = 0;
5912 /* Get current link speed. */
5913 memset(&link, 0, sizeof(link));
5914 ixgbe_dev_link_update(dev, 1);
5915 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
5917 switch (link.link_speed) {
5918 case ETH_LINK_SPEED_100:
5919 incval = IXGBE_INCVAL_100;
5920 shift = IXGBE_INCVAL_SHIFT_100;
5922 case ETH_LINK_SPEED_1000:
5923 incval = IXGBE_INCVAL_1GB;
5924 shift = IXGBE_INCVAL_SHIFT_1GB;
5926 case ETH_LINK_SPEED_10000:
5928 incval = IXGBE_INCVAL_10GB;
5929 shift = IXGBE_INCVAL_SHIFT_10GB;
5933 switch (hw->mac.type) {
5934 case ixgbe_mac_X550:
5935 case ixgbe_mac_X550EM_x:
5936 case ixgbe_mac_X550EM_a:
5937 /* Independent of link speed. */
5939 /* Cycles read will be interpreted as ns. */
5942 case ixgbe_mac_X540:
5943 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
5945 case ixgbe_mac_82599EB:
5946 incval >>= IXGBE_INCVAL_SHIFT_82599;
5947 shift -= IXGBE_INCVAL_SHIFT_82599;
5948 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
5949 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
5952 /* Not supported. */
5956 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5957 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5958 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5960 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5961 adapter->systime_tc.cc_shift = shift;
5962 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5964 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5965 adapter->rx_tstamp_tc.cc_shift = shift;
5966 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5968 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5969 adapter->tx_tstamp_tc.cc_shift = shift;
5970 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5974 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5976 struct ixgbe_adapter *adapter =
5977 (struct ixgbe_adapter *)dev->data->dev_private;
5979 adapter->systime_tc.nsec += delta;
5980 adapter->rx_tstamp_tc.nsec += delta;
5981 adapter->tx_tstamp_tc.nsec += delta;
5987 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5990 struct ixgbe_adapter *adapter =
5991 (struct ixgbe_adapter *)dev->data->dev_private;
5993 ns = rte_timespec_to_ns(ts);
5994 /* Set the timecounters to a new value. */
5995 adapter->systime_tc.nsec = ns;
5996 adapter->rx_tstamp_tc.nsec = ns;
5997 adapter->tx_tstamp_tc.nsec = ns;
6003 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6005 uint64_t ns, systime_cycles;
6006 struct ixgbe_adapter *adapter =
6007 (struct ixgbe_adapter *)dev->data->dev_private;
6009 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6010 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6011 *ts = rte_ns_to_timespec(ns);
6017 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6019 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6023 /* Stop the timesync system time. */
6024 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6025 /* Reset the timesync system time value. */
6026 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6027 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6029 /* Enable system time for platforms where it isn't on by default. */
6030 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6031 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6032 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6034 ixgbe_start_timecounters(dev);
6036 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6037 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6039 IXGBE_ETQF_FILTER_EN |
6042 /* Enable timestamping of received PTP packets. */
6043 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6044 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6045 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6047 /* Enable timestamping of transmitted PTP packets. */
6048 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6049 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6050 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6052 IXGBE_WRITE_FLUSH(hw);
6058 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6060 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6063 /* Disable timestamping of transmitted PTP packets. */
6064 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6065 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6066 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6068 /* Disable timestamping of received PTP packets. */
6069 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6070 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6071 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6073 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6074 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6076 /* Stop incrementating the System Time registers. */
6077 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6083 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6084 struct timespec *timestamp,
6085 uint32_t flags __rte_unused)
6087 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6088 struct ixgbe_adapter *adapter =
6089 (struct ixgbe_adapter *)dev->data->dev_private;
6090 uint32_t tsync_rxctl;
6091 uint64_t rx_tstamp_cycles;
6094 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6095 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6098 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6099 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6100 *timestamp = rte_ns_to_timespec(ns);
6106 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6107 struct timespec *timestamp)
6109 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6110 struct ixgbe_adapter *adapter =
6111 (struct ixgbe_adapter *)dev->data->dev_private;
6112 uint32_t tsync_txctl;
6113 uint64_t tx_tstamp_cycles;
6116 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6117 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6120 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6121 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6122 *timestamp = rte_ns_to_timespec(ns);
6128 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6130 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6133 const struct reg_info *reg_group;
6134 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6135 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6137 while ((reg_group = reg_set[g_ind++]))
6138 count += ixgbe_regs_group_count(reg_group);
6144 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6148 const struct reg_info *reg_group;
6150 while ((reg_group = ixgbevf_regs[g_ind++]))
6151 count += ixgbe_regs_group_count(reg_group);
6157 ixgbe_get_regs(struct rte_eth_dev *dev,
6158 struct rte_dev_reg_info *regs)
6160 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6161 uint32_t *data = regs->data;
6164 const struct reg_info *reg_group;
6165 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6166 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6168 /* Support only full register dump */
6169 if ((regs->length == 0) ||
6170 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6171 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6173 while ((reg_group = reg_set[g_ind++]))
6174 count += ixgbe_read_regs_group(dev, &data[count],
6183 ixgbevf_get_regs(struct rte_eth_dev *dev,
6184 struct rte_dev_reg_info *regs)
6186 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6187 uint32_t *data = regs->data;
6190 const struct reg_info *reg_group;
6192 /* Support only full register dump */
6193 if ((regs->length == 0) ||
6194 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6195 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6197 while ((reg_group = ixgbevf_regs[g_ind++]))
6198 count += ixgbe_read_regs_group(dev, &data[count],
6207 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6209 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6211 /* Return unit is byte count */
6212 return hw->eeprom.word_size * 2;
6216 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6217 struct rte_dev_eeprom_info *in_eeprom)
6219 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6220 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6221 uint16_t *data = in_eeprom->data;
6224 first = in_eeprom->offset >> 1;
6225 length = in_eeprom->length >> 1;
6226 if ((first > hw->eeprom.word_size) ||
6227 ((first + length) > hw->eeprom.word_size))
6230 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6232 return eeprom->ops.read_buffer(hw, first, length, data);
6236 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6237 struct rte_dev_eeprom_info *in_eeprom)
6239 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6240 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6241 uint16_t *data = in_eeprom->data;
6244 first = in_eeprom->offset >> 1;
6245 length = in_eeprom->length >> 1;
6246 if ((first > hw->eeprom.word_size) ||
6247 ((first + length) > hw->eeprom.word_size))
6250 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6252 return eeprom->ops.write_buffer(hw, first, length, data);
6256 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6258 case ixgbe_mac_X550:
6259 case ixgbe_mac_X550EM_x:
6260 case ixgbe_mac_X550EM_a:
6261 return ETH_RSS_RETA_SIZE_512;
6262 case ixgbe_mac_X550_vf:
6263 case ixgbe_mac_X550EM_x_vf:
6264 case ixgbe_mac_X550EM_a_vf:
6265 return ETH_RSS_RETA_SIZE_64;
6267 return ETH_RSS_RETA_SIZE_128;
6272 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6274 case ixgbe_mac_X550:
6275 case ixgbe_mac_X550EM_x:
6276 case ixgbe_mac_X550EM_a:
6277 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6278 return IXGBE_RETA(reta_idx >> 2);
6280 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6281 case ixgbe_mac_X550_vf:
6282 case ixgbe_mac_X550EM_x_vf:
6283 case ixgbe_mac_X550EM_a_vf:
6284 return IXGBE_VFRETA(reta_idx >> 2);
6286 return IXGBE_RETA(reta_idx >> 2);
6291 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6293 case ixgbe_mac_X550_vf:
6294 case ixgbe_mac_X550EM_x_vf:
6295 case ixgbe_mac_X550EM_a_vf:
6296 return IXGBE_VFMRQC;
6303 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6305 case ixgbe_mac_X550_vf:
6306 case ixgbe_mac_X550EM_x_vf:
6307 case ixgbe_mac_X550EM_a_vf:
6308 return IXGBE_VFRSSRK(i);
6310 return IXGBE_RSSRK(i);
6315 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6317 case ixgbe_mac_82599_vf:
6318 case ixgbe_mac_X540_vf:
6326 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6327 struct rte_eth_dcb_info *dcb_info)
6329 struct ixgbe_dcb_config *dcb_config =
6330 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6331 struct ixgbe_dcb_tc_config *tc;
6334 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6335 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6337 dcb_info->nb_tcs = 1;
6339 if (dcb_config->vt_mode) { /* vt is enabled*/
6340 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6341 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6342 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6343 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6344 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6345 for (j = 0; j < dcb_info->nb_tcs; j++) {
6346 dcb_info->tc_queue.tc_rxq[i][j].base =
6347 i * dcb_info->nb_tcs + j;
6348 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6349 dcb_info->tc_queue.tc_txq[i][j].base =
6350 i * dcb_info->nb_tcs + j;
6351 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6354 } else { /* vt is disabled*/
6355 struct rte_eth_dcb_rx_conf *rx_conf =
6356 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6357 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6358 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6359 if (dcb_info->nb_tcs == ETH_4_TCS) {
6360 for (i = 0; i < dcb_info->nb_tcs; i++) {
6361 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6362 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6364 dcb_info->tc_queue.tc_txq[0][0].base = 0;
6365 dcb_info->tc_queue.tc_txq[0][1].base = 64;
6366 dcb_info->tc_queue.tc_txq[0][2].base = 96;
6367 dcb_info->tc_queue.tc_txq[0][3].base = 112;
6368 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6369 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6370 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6371 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6372 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6373 for (i = 0; i < dcb_info->nb_tcs; i++) {
6374 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6375 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6377 dcb_info->tc_queue.tc_txq[0][0].base = 0;
6378 dcb_info->tc_queue.tc_txq[0][1].base = 32;
6379 dcb_info->tc_queue.tc_txq[0][2].base = 64;
6380 dcb_info->tc_queue.tc_txq[0][3].base = 80;
6381 dcb_info->tc_queue.tc_txq[0][4].base = 96;
6382 dcb_info->tc_queue.tc_txq[0][5].base = 104;
6383 dcb_info->tc_queue.tc_txq[0][6].base = 112;
6384 dcb_info->tc_queue.tc_txq[0][7].base = 120;
6385 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6386 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6387 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6388 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6389 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6390 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6391 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6392 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6395 for (i = 0; i < dcb_info->nb_tcs; i++) {
6396 tc = &dcb_config->tc_config[i];
6397 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6402 /* Update e-tag ether type */
6404 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6405 uint16_t ether_type)
6407 uint32_t etag_etype;
6409 if (hw->mac.type != ixgbe_mac_X550 &&
6410 hw->mac.type != ixgbe_mac_X550EM_x &&
6411 hw->mac.type != ixgbe_mac_X550EM_a) {
6415 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6416 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6417 etag_etype |= ether_type;
6418 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6419 IXGBE_WRITE_FLUSH(hw);
6424 /* Config l2 tunnel ether type */
6426 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6427 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6430 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6432 if (l2_tunnel == NULL)
6435 switch (l2_tunnel->l2_tunnel_type) {
6436 case RTE_L2_TUNNEL_TYPE_E_TAG:
6437 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6440 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6448 /* Enable e-tag tunnel */
6450 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6452 uint32_t etag_etype;
6454 if (hw->mac.type != ixgbe_mac_X550 &&
6455 hw->mac.type != ixgbe_mac_X550EM_x &&
6456 hw->mac.type != ixgbe_mac_X550EM_a) {
6460 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6461 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6462 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6463 IXGBE_WRITE_FLUSH(hw);
6468 /* Enable l2 tunnel */
6470 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6471 enum rte_eth_tunnel_type l2_tunnel_type)
6474 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6476 switch (l2_tunnel_type) {
6477 case RTE_L2_TUNNEL_TYPE_E_TAG:
6478 ret = ixgbe_e_tag_enable(hw);
6481 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6489 /* Disable e-tag tunnel */
6491 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6493 uint32_t etag_etype;
6495 if (hw->mac.type != ixgbe_mac_X550 &&
6496 hw->mac.type != ixgbe_mac_X550EM_x &&
6497 hw->mac.type != ixgbe_mac_X550EM_a) {
6501 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6502 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6503 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6504 IXGBE_WRITE_FLUSH(hw);
6509 /* Disable l2 tunnel */
6511 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6512 enum rte_eth_tunnel_type l2_tunnel_type)
6515 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6517 switch (l2_tunnel_type) {
6518 case RTE_L2_TUNNEL_TYPE_E_TAG:
6519 ret = ixgbe_e_tag_disable(hw);
6522 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6531 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6532 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6535 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6536 uint32_t i, rar_entries;
6537 uint32_t rar_low, rar_high;
6539 if (hw->mac.type != ixgbe_mac_X550 &&
6540 hw->mac.type != ixgbe_mac_X550EM_x &&
6541 hw->mac.type != ixgbe_mac_X550EM_a) {
6545 rar_entries = ixgbe_get_num_rx_addrs(hw);
6547 for (i = 1; i < rar_entries; i++) {
6548 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6549 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6550 if ((rar_high & IXGBE_RAH_AV) &&
6551 (rar_high & IXGBE_RAH_ADTYPE) &&
6552 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6553 l2_tunnel->tunnel_id)) {
6554 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6555 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6557 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6567 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6568 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6571 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6572 uint32_t i, rar_entries;
6573 uint32_t rar_low, rar_high;
6575 if (hw->mac.type != ixgbe_mac_X550 &&
6576 hw->mac.type != ixgbe_mac_X550EM_x &&
6577 hw->mac.type != ixgbe_mac_X550EM_a) {
6581 /* One entry for one tunnel. Try to remove potential existing entry. */
6582 ixgbe_e_tag_filter_del(dev, l2_tunnel);
6584 rar_entries = ixgbe_get_num_rx_addrs(hw);
6586 for (i = 1; i < rar_entries; i++) {
6587 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6588 if (rar_high & IXGBE_RAH_AV) {
6591 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6592 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6593 rar_low = l2_tunnel->tunnel_id;
6595 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6596 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6602 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6603 " Please remove a rule before adding a new one.");
6607 /* Add l2 tunnel filter */
6609 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6610 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6614 switch (l2_tunnel->l2_tunnel_type) {
6615 case RTE_L2_TUNNEL_TYPE_E_TAG:
6616 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6619 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6627 /* Delete l2 tunnel filter */
6629 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6630 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6634 switch (l2_tunnel->l2_tunnel_type) {
6635 case RTE_L2_TUNNEL_TYPE_E_TAG:
6636 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6639 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6648 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6649 * @dev: pointer to rte_eth_dev structure
6650 * @filter_op:operation will be taken.
6651 * @arg: a pointer to specific structure corresponding to the filter_op
6654 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6655 enum rte_filter_op filter_op,
6660 if (filter_op == RTE_ETH_FILTER_NOP)
6664 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6669 switch (filter_op) {
6670 case RTE_ETH_FILTER_ADD:
6671 ret = ixgbe_dev_l2_tunnel_filter_add
6673 (struct rte_eth_l2_tunnel_conf *)arg);
6675 case RTE_ETH_FILTER_DELETE:
6676 ret = ixgbe_dev_l2_tunnel_filter_del
6678 (struct rte_eth_l2_tunnel_conf *)arg);
6681 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6689 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6693 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6695 if (hw->mac.type != ixgbe_mac_X550 &&
6696 hw->mac.type != ixgbe_mac_X550EM_x &&
6697 hw->mac.type != ixgbe_mac_X550EM_a) {
6701 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6702 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6704 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6705 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6710 /* Enable l2 tunnel forwarding */
6712 ixgbe_dev_l2_tunnel_forwarding_enable
6713 (struct rte_eth_dev *dev,
6714 enum rte_eth_tunnel_type l2_tunnel_type)
6718 switch (l2_tunnel_type) {
6719 case RTE_L2_TUNNEL_TYPE_E_TAG:
6720 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6723 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6731 /* Disable l2 tunnel forwarding */
6733 ixgbe_dev_l2_tunnel_forwarding_disable
6734 (struct rte_eth_dev *dev,
6735 enum rte_eth_tunnel_type l2_tunnel_type)
6739 switch (l2_tunnel_type) {
6740 case RTE_L2_TUNNEL_TYPE_E_TAG:
6741 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6744 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6753 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6754 struct rte_eth_l2_tunnel_conf *l2_tunnel,
6758 uint32_t vmtir, vmvir;
6759 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6761 if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6763 "VF id %u should be less than %u",
6765 dev->pci_dev->max_vfs);
6769 if (hw->mac.type != ixgbe_mac_X550 &&
6770 hw->mac.type != ixgbe_mac_X550EM_x &&
6771 hw->mac.type != ixgbe_mac_X550EM_a) {
6776 vmtir = l2_tunnel->tunnel_id;
6780 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6782 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6783 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6785 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6786 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6791 /* Enable l2 tunnel tag insertion */
6793 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6794 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6798 switch (l2_tunnel->l2_tunnel_type) {
6799 case RTE_L2_TUNNEL_TYPE_E_TAG:
6800 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6803 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6811 /* Disable l2 tunnel tag insertion */
6813 ixgbe_dev_l2_tunnel_insertion_disable
6814 (struct rte_eth_dev *dev,
6815 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6819 switch (l2_tunnel->l2_tunnel_type) {
6820 case RTE_L2_TUNNEL_TYPE_E_TAG:
6821 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6824 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6833 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6838 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6840 if (hw->mac.type != ixgbe_mac_X550 &&
6841 hw->mac.type != ixgbe_mac_X550EM_x &&
6842 hw->mac.type != ixgbe_mac_X550EM_a) {
6846 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
6848 qde |= IXGBE_QDE_STRIP_TAG;
6850 qde &= ~IXGBE_QDE_STRIP_TAG;
6851 qde &= ~IXGBE_QDE_READ;
6852 qde |= IXGBE_QDE_WRITE;
6853 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
6858 /* Enable l2 tunnel tag stripping */
6860 ixgbe_dev_l2_tunnel_stripping_enable
6861 (struct rte_eth_dev *dev,
6862 enum rte_eth_tunnel_type l2_tunnel_type)
6866 switch (l2_tunnel_type) {
6867 case RTE_L2_TUNNEL_TYPE_E_TAG:
6868 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
6871 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6879 /* Disable l2 tunnel tag stripping */
6881 ixgbe_dev_l2_tunnel_stripping_disable
6882 (struct rte_eth_dev *dev,
6883 enum rte_eth_tunnel_type l2_tunnel_type)
6887 switch (l2_tunnel_type) {
6888 case RTE_L2_TUNNEL_TYPE_E_TAG:
6889 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
6892 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6900 /* Enable/disable l2 tunnel offload functions */
6902 ixgbe_dev_l2_tunnel_offload_set
6903 (struct rte_eth_dev *dev,
6904 struct rte_eth_l2_tunnel_conf *l2_tunnel,
6910 if (l2_tunnel == NULL)
6914 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
6916 ret = ixgbe_dev_l2_tunnel_enable(
6918 l2_tunnel->l2_tunnel_type);
6920 ret = ixgbe_dev_l2_tunnel_disable(
6922 l2_tunnel->l2_tunnel_type);
6925 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
6927 ret = ixgbe_dev_l2_tunnel_insertion_enable(
6931 ret = ixgbe_dev_l2_tunnel_insertion_disable(
6936 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
6938 ret = ixgbe_dev_l2_tunnel_stripping_enable(
6940 l2_tunnel->l2_tunnel_type);
6942 ret = ixgbe_dev_l2_tunnel_stripping_disable(
6944 l2_tunnel->l2_tunnel_type);
6947 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
6949 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
6951 l2_tunnel->l2_tunnel_type);
6953 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
6955 l2_tunnel->l2_tunnel_type);
6962 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
6965 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
6966 IXGBE_WRITE_FLUSH(hw);
6971 /* There's only one register for VxLAN UDP port.
6972 * So, we cannot add several ports. Will update it.
6975 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
6979 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
6983 return ixgbe_update_vxlan_port(hw, port);
6986 /* We cannot delete the VxLAN port. For there's a register for VxLAN
6987 * UDP port, it must have a value.
6988 * So, will reset it to the original value 0.
6991 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
6996 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
6998 if (cur_port != port) {
6999 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7003 return ixgbe_update_vxlan_port(hw, 0);
7006 /* Add UDP tunneling port */
7008 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7009 struct rte_eth_udp_tunnel *udp_tunnel)
7012 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7014 if (hw->mac.type != ixgbe_mac_X550 &&
7015 hw->mac.type != ixgbe_mac_X550EM_x &&
7016 hw->mac.type != ixgbe_mac_X550EM_a) {
7020 if (udp_tunnel == NULL)
7023 switch (udp_tunnel->prot_type) {
7024 case RTE_TUNNEL_TYPE_VXLAN:
7025 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7028 case RTE_TUNNEL_TYPE_GENEVE:
7029 case RTE_TUNNEL_TYPE_TEREDO:
7030 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7035 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7043 /* Remove UDP tunneling port */
7045 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7046 struct rte_eth_udp_tunnel *udp_tunnel)
7049 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7051 if (hw->mac.type != ixgbe_mac_X550 &&
7052 hw->mac.type != ixgbe_mac_X550EM_x &&
7053 hw->mac.type != ixgbe_mac_X550EM_a) {
7057 if (udp_tunnel == NULL)
7060 switch (udp_tunnel->prot_type) {
7061 case RTE_TUNNEL_TYPE_VXLAN:
7062 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7064 case RTE_TUNNEL_TYPE_GENEVE:
7065 case RTE_TUNNEL_TYPE_TEREDO:
7066 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7070 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7078 /* ixgbevf_update_xcast_mode - Update Multicast mode
7079 * @hw: pointer to the HW structure
7080 * @netdev: pointer to net device structure
7081 * @xcast_mode: new multicast mode
7083 * Updates the Multicast Mode of VF.
7085 static int ixgbevf_update_xcast_mode(struct ixgbe_hw *hw,
7088 struct ixgbe_mbx_info *mbx = &hw->mbx;
7092 switch (hw->api_version) {
7093 case ixgbe_mbox_api_12:
7099 msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
7100 msgbuf[1] = xcast_mode;
7102 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
7106 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
7110 msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
7111 if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
7118 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7120 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7122 ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7126 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7128 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7130 ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7133 static struct rte_driver rte_ixgbe_driver = {
7135 .init = rte_ixgbe_pmd_init,
7138 static struct rte_driver rte_ixgbevf_driver = {
7140 .init = rte_ixgbevf_pmd_init,
7143 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
7144 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);