drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIB_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static int ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
 233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
 234                                               uint32_t timeout_ms);
 235
 236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 237                         struct rte_ether_addr *mac_addr,
 238                         uint32_t index, uint32_t pool);
 239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 241                                            struct rte_ether_addr *mac_addr);
 242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 243 static bool is_device_supported(struct rte_eth_dev *dev,
 244                                 struct rte_pci_driver *drv);
 245
 246 /* For Virtual Function support */
 247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 250 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 252                                    int wait_to_complete);
 253 static int ixgbevf_dev_stop(struct rte_eth_dev *dev);
 254 static int ixgbevf_dev_close(struct rte_eth_dev *dev);
 255 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 259                 struct rte_eth_stats *stats);
 260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 262                 uint16_t vlan_id, int on);
 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 264                 uint16_t queue, int on);
 265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 269                                             uint16_t queue_id);
 270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 271                                              uint16_t queue_id);
 272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 273                                  uint8_t queue, uint8_t msix_vector);
 274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 rte_ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 285                 struct rte_eth_mirror_conf *mirror_conf,
 286                 uint8_t rule_id, uint8_t on);
 287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 288                 uint8_t rule_id);
 289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 290                                           uint16_t queue_id);
 291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 292                                            uint16_t queue_id);
 293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 294                                uint8_t queue, uint8_t msix_vector);
 295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 296
 297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 298                                 struct rte_ether_addr *mac_addr,
 299                                 uint32_t index, uint32_t pool);
 300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 302                                              struct rte_ether_addr *mac_addr);
 303 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 304                         struct ixgbe_5tuple_filter *filter);
 305 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 306                         struct ixgbe_5tuple_filter *filter);
 307 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 308                                 enum rte_filter_op filter_op,
 309                                 void *arg);
 310 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 311                         struct rte_eth_ntuple_filter *filter);
 312 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 313                      enum rte_filter_type filter_type,
 314                      enum rte_filter_op filter_op,
 315                      void *arg);
 316 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 317
 318 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 319                                       struct rte_ether_addr *mc_addr_set,
 320                                       uint32_t nb_mc_addr);
 321 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 322                                    struct rte_eth_dcb_info *dcb_info);
 323
 324 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 325 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 326                             struct rte_dev_reg_info *regs);
 327 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 328 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 329                                 struct rte_dev_eeprom_info *eeprom);
 330 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 331                                 struct rte_dev_eeprom_info *eeprom);
 332
 333 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 334                                  struct rte_eth_dev_module_info *modinfo);
 335 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 336                                    struct rte_dev_eeprom_info *info);
 337
 338 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 339 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 340                                 struct rte_dev_reg_info *regs);
 341
 342 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 343 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 344 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 345                                             struct timespec *timestamp,
 346                                             uint32_t flags);
 347 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 348                                             struct timespec *timestamp);
 349 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 350 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 351                                    struct timespec *timestamp);
 352 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 353                                    const struct timespec *timestamp);
 354 static void ixgbevf_dev_interrupt_handler(void *param);
 355
 356 static int ixgbe_dev_l2_tunnel_eth_type_conf
 357         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 358 static int ixgbe_dev_l2_tunnel_offload_set
 359         (struct rte_eth_dev *dev,
 360          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 361          uint32_t mask,
 362          uint8_t en);
 363 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 364                                              enum rte_filter_op filter_op,
 365                                              void *arg);
 366
 367 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 368                                          struct rte_eth_udp_tunnel *udp_tunnel);
 369 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 370                                          struct rte_eth_udp_tunnel *udp_tunnel);
 371 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 372 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 373 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
 374
 375 /*
 376  * Define VF Stats MACRO for Non "cleared on read" register
 377  */
 378 #define UPDATE_VF_STAT(reg, last, cur)                          \
 379 {                                                               \
 380         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 381         cur += (latest - last) & UINT_MAX;                      \
 382         last = latest;                                          \
 383 }
 384
 385 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 386 {                                                                \
 387         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 388         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 389         u64 latest = ((new_msb << 32) | new_lsb);                \
 390         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 391         last = latest;                                           \
 392 }
 393
 394 #define IXGBE_SET_HWSTRIP(h, q) do {\
 395                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 396                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 397                 (h)->bitmap[idx] |= 1 << bit;\
 398         } while (0)
 399
 400 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 401                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 402                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 403                 (h)->bitmap[idx] &= ~(1 << bit);\
 404         } while (0)
 405
 406 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 407                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 408                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 409                 (r) = (h)->bitmap[idx] >> bit & 1;\
 410         } while (0)
 411
 412 /*
 413  * The set of PCI devices this driver supports
 414  */
 415 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 464 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 466 #endif
 467         { .vendor_id = 0, /* sentinel */ },
 468 };
 469
 470 /*
 471  * The set of PCI devices this driver supports (for 82599 VF)
 472  */
 473 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 484         { .vendor_id = 0, /* sentinel */ },
 485 };
 486
 487 static const struct rte_eth_desc_lim rx_desc_lim = {
 488         .nb_max = IXGBE_MAX_RING_DESC,
 489         .nb_min = IXGBE_MIN_RING_DESC,
 490         .nb_align = IXGBE_RXD_ALIGN,
 491 };
 492
 493 static const struct rte_eth_desc_lim tx_desc_lim = {
 494         .nb_max = IXGBE_MAX_RING_DESC,
 495         .nb_min = IXGBE_MIN_RING_DESC,
 496         .nb_align = IXGBE_TXD_ALIGN,
 497         .nb_seg_max = IXGBE_TX_MAX_SEG,
 498         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 499 };
 500
 501 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 502         .dev_configure        = ixgbe_dev_configure,
 503         .dev_start            = ixgbe_dev_start,
 504         .dev_stop             = ixgbe_dev_stop,
 505         .dev_set_link_up    = ixgbe_dev_set_link_up,
 506         .dev_set_link_down  = ixgbe_dev_set_link_down,
 507         .dev_close            = ixgbe_dev_close,
 508         .dev_reset            = ixgbe_dev_reset,
 509         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 510         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 511         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 512         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 513         .link_update          = ixgbe_dev_link_update,
 514         .stats_get            = ixgbe_dev_stats_get,
 515         .xstats_get           = ixgbe_dev_xstats_get,
 516         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 517         .stats_reset          = ixgbe_dev_stats_reset,
 518         .xstats_reset         = ixgbe_dev_xstats_reset,
 519         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 520         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 521         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 522         .fw_version_get       = ixgbe_fw_version_get,
 523         .dev_infos_get        = ixgbe_dev_info_get,
 524         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 525         .mtu_set              = ixgbe_dev_mtu_set,
 526         .vlan_filter_set      = ixgbe_vlan_filter_set,
 527         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 528         .vlan_offload_set     = ixgbe_vlan_offload_set,
 529         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 530         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 531         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 532         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 533         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 534         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 535         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 536         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 537         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 538         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 539         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 540         .dev_led_on           = ixgbe_dev_led_on,
 541         .dev_led_off          = ixgbe_dev_led_off,
 542         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 543         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 544         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 545         .mac_addr_add         = ixgbe_add_rar,
 546         .mac_addr_remove      = ixgbe_remove_rar,
 547         .mac_addr_set         = ixgbe_set_default_mac_addr,
 548         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 549         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 550         .mirror_rule_set      = ixgbe_mirror_rule_set,
 551         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 552         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 553         .reta_update          = ixgbe_dev_rss_reta_update,
 554         .reta_query           = ixgbe_dev_rss_reta_query,
 555         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 556         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 557         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 558         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 559         .rxq_info_get         = ixgbe_rxq_info_get,
 560         .txq_info_get         = ixgbe_txq_info_get,
 561         .timesync_enable      = ixgbe_timesync_enable,
 562         .timesync_disable     = ixgbe_timesync_disable,
 563         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 564         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 565         .get_reg              = ixgbe_get_regs,
 566         .get_eeprom_length    = ixgbe_get_eeprom_length,
 567         .get_eeprom           = ixgbe_get_eeprom,
 568         .set_eeprom           = ixgbe_set_eeprom,
 569         .get_module_info      = ixgbe_get_module_info,
 570         .get_module_eeprom    = ixgbe_get_module_eeprom,
 571         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 572         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 573         .timesync_read_time   = ixgbe_timesync_read_time,
 574         .timesync_write_time  = ixgbe_timesync_write_time,
 575         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 576         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 577         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 578         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 579         .tm_ops_get           = ixgbe_tm_ops_get,
 580         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 581 };
 582
 583 /*
 584  * dev_ops for virtual function, bare necessities for basic vf
 585  * operation have been implemented
 586  */
 587 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 588         .dev_configure        = ixgbevf_dev_configure,
 589         .dev_start            = ixgbevf_dev_start,
 590         .dev_stop             = ixgbevf_dev_stop,
 591         .link_update          = ixgbevf_dev_link_update,
 592         .stats_get            = ixgbevf_dev_stats_get,
 593         .xstats_get           = ixgbevf_dev_xstats_get,
 594         .stats_reset          = ixgbevf_dev_stats_reset,
 595         .xstats_reset         = ixgbevf_dev_stats_reset,
 596         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 597         .dev_close            = ixgbevf_dev_close,
 598         .dev_reset            = ixgbevf_dev_reset,
 599         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 600         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 601         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 602         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 603         .dev_infos_get        = ixgbevf_dev_info_get,
 604         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 605         .mtu_set              = ixgbevf_dev_set_mtu,
 606         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 607         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 608         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 609         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 610         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 611         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 612         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 613         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 614         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 615         .mac_addr_add         = ixgbevf_add_mac_addr,
 616         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 617         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 618         .rxq_info_get         = ixgbe_rxq_info_get,
 619         .txq_info_get         = ixgbe_txq_info_get,
 620         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 621         .get_reg              = ixgbevf_get_regs,
 622         .reta_update          = ixgbe_dev_rss_reta_update,
 623         .reta_query           = ixgbe_dev_rss_reta_query,
 624         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 625         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 626         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 627 };
 628
 629 /* store statistics names and its offset in stats structure */
 630 struct rte_ixgbe_xstats_name_off {
 631         char name[RTE_ETH_XSTATS_NAME_SIZE];
 632         unsigned offset;
 633 };
 634
 635 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 636         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 637         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 638         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 639         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 640         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 641         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 642         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 643         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 644         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 645         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 646         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 647         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 648         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 649         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 650         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 651                 prc1023)},
 652         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 653                 prc1522)},
 654         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 655         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 656         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 657         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 658         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 659         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 660         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 661         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 662         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 663         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 664         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 665         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 666         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 667         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 668         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 669         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 670         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 671                 ptc1023)},
 672         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 673                 ptc1522)},
 674         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 675         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 676         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 677         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 678
 679         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 680                 fdirustat_add)},
 681         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 682                 fdirustat_remove)},
 683         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 684                 fdirfstat_fadd)},
 685         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 686                 fdirfstat_fremove)},
 687         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 688                 fdirmatch)},
 689         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 690                 fdirmiss)},
 691
 692         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 693         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 694         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 695                 fclast)},
 696         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 697         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 698         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 699         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 700         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 701                 fcoe_noddp)},
 702         {"rx_fcoe_no_direct_data_placement_ext_buff",
 703                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 704
 705         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 706                 lxontxc)},
 707         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 708                 lxonrxc)},
 709         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 710                 lxofftxc)},
 711         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 712                 lxoffrxc)},
 713         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 714 };
 715
 716 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 717                            sizeof(rte_ixgbe_stats_strings[0]))
 718
 719 /* MACsec statistics */
 720 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 721         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 722                 out_pkts_untagged)},
 723         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 724                 out_pkts_encrypted)},
 725         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 726                 out_pkts_protected)},
 727         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 728                 out_octets_encrypted)},
 729         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 730                 out_octets_protected)},
 731         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 732                 in_pkts_untagged)},
 733         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 734                 in_pkts_badtag)},
 735         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 736                 in_pkts_nosci)},
 737         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 738                 in_pkts_unknownsci)},
 739         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 740                 in_octets_decrypted)},
 741         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 742                 in_octets_validated)},
 743         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 744                 in_pkts_unchecked)},
 745         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 746                 in_pkts_delayed)},
 747         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_late)},
 749         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 750                 in_pkts_ok)},
 751         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 752                 in_pkts_invalid)},
 753         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_notvalid)},
 755         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_unusedsa)},
 757         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_notusingsa)},
 759 };
 760
 761 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 762                            sizeof(rte_ixgbe_macsec_strings[0]))
 763
 764 /* Per-queue statistics */
 765 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 766         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 767         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 768         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 769         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 770 };
 771
 772 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 773                            sizeof(rte_ixgbe_rxq_strings[0]))
 774 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 775
 776 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 777         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 778         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 779         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 780                 pxon2offc)},
 781 };
 782
 783 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 784                            sizeof(rte_ixgbe_txq_strings[0]))
 785 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 786
 787 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 788         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 789 };
 790
 791 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 792                 sizeof(rte_ixgbevf_stats_strings[0]))
 793
 794 /*
 795  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 796  */
 797 static inline int
 798 ixgbe_is_sfp(struct ixgbe_hw *hw)
 799 {
 800         switch (hw->phy.type) {
 801         case ixgbe_phy_sfp_avago:
 802         case ixgbe_phy_sfp_ftl:
 803         case ixgbe_phy_sfp_intel:
 804         case ixgbe_phy_sfp_unknown:
 805         case ixgbe_phy_sfp_passive_tyco:
 806         case ixgbe_phy_sfp_passive_unknown:
 807                 return 1;
 808         default:
 809                 return 0;
 810         }
 811 }
 812
 813 static inline int32_t
 814 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 815 {
 816         uint32_t ctrl_ext;
 817         int32_t status;
 818
 819         status = ixgbe_reset_hw(hw);
 820
 821         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 822         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 823         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 824         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 825         IXGBE_WRITE_FLUSH(hw);
 826
 827         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 828                 status = IXGBE_SUCCESS;
 829         return status;
 830 }
 831
 832 static inline void
 833 ixgbe_enable_intr(struct rte_eth_dev *dev)
 834 {
 835         struct ixgbe_interrupt *intr =
 836                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 837         struct ixgbe_hw *hw =
 838                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 839
 840         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 841         IXGBE_WRITE_FLUSH(hw);
 842 }
 843
 844 /*
 845  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 846  */
 847 static void
 848 ixgbe_disable_intr(struct ixgbe_hw *hw)
 849 {
 850         PMD_INIT_FUNC_TRACE();
 851
 852         if (hw->mac.type == ixgbe_mac_82598EB) {
 853                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 854         } else {
 855                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 856                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 857                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 858         }
 859         IXGBE_WRITE_FLUSH(hw);
 860 }
 861
 862 /*
 863  * This function resets queue statistics mapping registers.
 864  * From Niantic datasheet, Initialization of Statistics section:
 865  * "...if software requires the queue counters, the RQSMR and TQSM registers
 866  * must be re-programmed following a device reset.
 867  */
 868 static void
 869 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 870 {
 871         uint32_t i;
 872
 873         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 874                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 875                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 876         }
 877 }
 878
 879
 880 static int
 881 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 882                                   uint16_t queue_id,
 883                                   uint8_t stat_idx,
 884                                   uint8_t is_rx)
 885 {
 886 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 887 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 888 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 889
 890         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 891         struct ixgbe_stat_mapping_registers *stat_mappings =
 892                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 893         uint32_t qsmr_mask = 0;
 894         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 895         uint32_t q_map;
 896         uint8_t n, offset;
 897
 898         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 899                 (hw->mac.type != ixgbe_mac_X540) &&
 900                 (hw->mac.type != ixgbe_mac_X550) &&
 901                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 902                 (hw->mac.type != ixgbe_mac_X550EM_a))
 903                 return -ENOSYS;
 904
 905         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 906                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 907                      queue_id, stat_idx);
 908
 909         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 910         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 911                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 912                 return -EIO;
 913         }
 914         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 915
 916         /* Now clear any previous stat_idx set */
 917         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 918         if (!is_rx)
 919                 stat_mappings->tqsm[n] &= ~clearing_mask;
 920         else
 921                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 922
 923         q_map = (uint32_t)stat_idx;
 924         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 925         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 926         if (!is_rx)
 927                 stat_mappings->tqsm[n] |= qsmr_mask;
 928         else
 929                 stat_mappings->rqsmr[n] |= qsmr_mask;
 930
 931         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 932                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 933                      queue_id, stat_idx);
 934         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 935                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 936
 937         /* Now write the mapping in the appropriate register */
 938         if (is_rx) {
 939                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 940                              stat_mappings->rqsmr[n], n);
 941                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 942         } else {
 943                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 944                              stat_mappings->tqsm[n], n);
 945                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 946         }
 947         return 0;
 948 }
 949
 950 static void
 951 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 952 {
 953         struct ixgbe_stat_mapping_registers *stat_mappings =
 954                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 955         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 956         int i;
 957
 958         /* write whatever was in stat mapping table to the NIC */
 959         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 960                 /* rx */
 961                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 962
 963                 /* tx */
 964                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 965         }
 966 }
 967
 968 static void
 969 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 970 {
 971         uint8_t i;
 972         struct ixgbe_dcb_tc_config *tc;
 973         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 974
 975         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 976         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 977         for (i = 0; i < dcb_max_tc; i++) {
 978                 tc = &dcb_config->tc_config[i];
 979                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 980                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 981                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 982                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 983                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 984                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 985                 tc->pfc = ixgbe_dcb_pfc_disabled;
 986         }
 987
 988         /* Initialize default user to priority mapping, UPx->TC0 */
 989         tc = &dcb_config->tc_config[0];
 990         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 991         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 992         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 993                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 994                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 995         }
 996         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 997         dcb_config->pfc_mode_enable = false;
 998         dcb_config->vt_mode = true;
 999         dcb_config->round_robin_enable = false;
1000         /* support all DCB capabilities in 82599 */
1001         dcb_config->support.capabilities = 0xFF;
1002
1003         /*we only support 4 Tcs for X540, X550 */
1004         if (hw->mac.type == ixgbe_mac_X540 ||
1005                 hw->mac.type == ixgbe_mac_X550 ||
1006                 hw->mac.type == ixgbe_mac_X550EM_x ||
1007                 hw->mac.type == ixgbe_mac_X550EM_a) {
1008                 dcb_config->num_tcs.pg_tcs = 4;
1009                 dcb_config->num_tcs.pfc_tcs = 4;
1010         }
1011 }
1012
1013 /*
1014  * Ensure that all locks are released before first NVM or PHY access
1015  */
1016 static void
1017 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1018 {
1019         uint16_t mask;
1020
1021         /*
1022          * Phy lock should not fail in this early stage. If this is the case,
1023          * it is due to an improper exit of the application.
1024          * So force the release of the faulty lock. Release of common lock
1025          * is done automatically by swfw_sync function.
1026          */
1027         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1028         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1029                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1030         }
1031         ixgbe_release_swfw_semaphore(hw, mask);
1032
1033         /*
1034          * These ones are more tricky since they are common to all ports; but
1035          * swfw_sync retries last long enough (1s) to be almost sure that if
1036          * lock can not be taken it is due to an improper lock of the
1037          * semaphore.
1038          */
1039         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1040         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1041                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1042         }
1043         ixgbe_release_swfw_semaphore(hw, mask);
1044 }
1045
1046 /*
1047  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1048  * It returns 0 on success.
1049  */
1050 static int
1051 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1052 {
1053         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1054         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1055         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1056         struct ixgbe_hw *hw =
1057                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1058         struct ixgbe_vfta *shadow_vfta =
1059                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1060         struct ixgbe_hwstrip *hwstrip =
1061                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1062         struct ixgbe_dcb_config *dcb_config =
1063                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1064         struct ixgbe_filter_info *filter_info =
1065                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1066         struct ixgbe_bw_conf *bw_conf =
1067                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1068         uint32_t ctrl_ext;
1069         uint16_t csum;
1070         int diag, i, ret;
1071
1072         PMD_INIT_FUNC_TRACE();
1073
1074         ixgbe_dev_macsec_setting_reset(eth_dev);
1075
1076         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1077         eth_dev->rx_queue_count       = ixgbe_dev_rx_queue_count;
1078         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1079         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1080         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1081         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1082         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1083         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1084
1085         /*
1086          * For secondary processes, we don't initialise any further as primary
1087          * has already done this work. Only check we don't need a different
1088          * RX and TX function.
1089          */
1090         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1091                 struct ixgbe_tx_queue *txq;
1092                 /* TX queue function in primary, set by last queue initialized
1093                  * Tx queue may not initialized by primary process
1094                  */
1095                 if (eth_dev->data->tx_queues) {
1096                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1097                         ixgbe_set_tx_function(eth_dev, txq);
1098                 } else {
1099                         /* Use default TX function if we get here */
1100                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1101                                      "Using default TX function.");
1102                 }
1103
1104                 ixgbe_set_rx_function(eth_dev);
1105
1106                 return 0;
1107         }
1108
1109         rte_atomic32_clear(&ad->link_thread_running);
1110         rte_eth_copy_pci_info(eth_dev, pci_dev);
1111         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1112
1113         /* Vendor and Device ID need to be set before init of shared code */
1114         hw->device_id = pci_dev->id.device_id;
1115         hw->vendor_id = pci_dev->id.vendor_id;
1116         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1117         hw->allow_unsupported_sfp = 1;
1118
1119         /* Initialize the shared code (base driver) */
1120 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1121         diag = ixgbe_bypass_init_shared_code(hw);
1122 #else
1123         diag = ixgbe_init_shared_code(hw);
1124 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1125
1126         if (diag != IXGBE_SUCCESS) {
1127                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1128                 return -EIO;
1129         }
1130
1131         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1132                 PMD_INIT_LOG(ERR, "\nERROR: "
1133                         "Firmware recovery mode detected. Limiting functionality.\n"
1134                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1135                         "User Guide for details on firmware recovery mode.");
1136                 return -EIO;
1137         }
1138
1139         /* pick up the PCI bus settings for reporting later */
1140         ixgbe_get_bus_info(hw);
1141
1142         /* Unlock any pending hardware semaphore */
1143         ixgbe_swfw_lock_reset(hw);
1144
1145 #ifdef RTE_LIB_SECURITY
1146         /* Initialize security_ctx only for primary process*/
1147         if (ixgbe_ipsec_ctx_create(eth_dev))
1148                 return -ENOMEM;
1149 #endif
1150
1151         /* Initialize DCB configuration*/
1152         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1153         ixgbe_dcb_init(hw, dcb_config);
1154         /* Get Hardware Flow Control setting */
1155         hw->fc.requested_mode = ixgbe_fc_none;
1156         hw->fc.current_mode = ixgbe_fc_none;
1157         hw->fc.pause_time = IXGBE_FC_PAUSE;
1158         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1159                 hw->fc.low_water[i] = IXGBE_FC_LO;
1160                 hw->fc.high_water[i] = IXGBE_FC_HI;
1161         }
1162         hw->fc.send_xon = 1;
1163
1164         /* Make sure we have a good EEPROM before we read from it */
1165         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1166         if (diag != IXGBE_SUCCESS) {
1167                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1168                 return -EIO;
1169         }
1170
1171 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1172         diag = ixgbe_bypass_init_hw(hw);
1173 #else
1174         diag = ixgbe_init_hw(hw);
1175 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1176
1177         /*
1178          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1179          * is called too soon after the kernel driver unbinding/binding occurs.
1180          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1181          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1182          * also called. See ixgbe_identify_phy_82599(). The reason for the
1183          * failure is not known, and only occuts when virtualisation features
1184          * are disabled in the bios. A delay of 100ms  was found to be enough by
1185          * trial-and-error, and is doubled to be safe.
1186          */
1187         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1188                 rte_delay_ms(200);
1189                 diag = ixgbe_init_hw(hw);
1190         }
1191
1192         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1193                 diag = IXGBE_SUCCESS;
1194
1195         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1196                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1197                              "LOM.  Please be aware there may be issues associated "
1198                              "with your hardware.");
1199                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1200                              "please contact your Intel or hardware representative "
1201                              "who provided you with this hardware.");
1202         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1203                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1204         if (diag) {
1205                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1206                 return -EIO;
1207         }
1208
1209         /* Reset the hw statistics */
1210         ixgbe_dev_stats_reset(eth_dev);
1211
1212         /* disable interrupt */
1213         ixgbe_disable_intr(hw);
1214
1215         /* reset mappings for queue statistics hw counters*/
1216         ixgbe_reset_qstat_mappings(hw);
1217
1218         /* Allocate memory for storing MAC addresses */
1219         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1220                                                hw->mac.num_rar_entries, 0);
1221         if (eth_dev->data->mac_addrs == NULL) {
1222                 PMD_INIT_LOG(ERR,
1223                              "Failed to allocate %u bytes needed to store "
1224                              "MAC addresses",
1225                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1226                 return -ENOMEM;
1227         }
1228         /* Copy the permanent MAC address */
1229         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1230                         &eth_dev->data->mac_addrs[0]);
1231
1232         /* Allocate memory for storing hash filter MAC addresses */
1233         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1234                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1235         if (eth_dev->data->hash_mac_addrs == NULL) {
1236                 PMD_INIT_LOG(ERR,
1237                              "Failed to allocate %d bytes needed to store MAC addresses",
1238                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1239                 return -ENOMEM;
1240         }
1241
1242         /* initialize the vfta */
1243         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1244
1245         /* initialize the hw strip bitmap*/
1246         memset(hwstrip, 0, sizeof(*hwstrip));
1247
1248         /* initialize PF if max_vfs not zero */
1249         ret = ixgbe_pf_host_init(eth_dev);
1250         if (ret) {
1251                 rte_free(eth_dev->data->mac_addrs);
1252                 eth_dev->data->mac_addrs = NULL;
1253                 rte_free(eth_dev->data->hash_mac_addrs);
1254                 eth_dev->data->hash_mac_addrs = NULL;
1255                 return ret;
1256         }
1257
1258         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1259         /* let hardware know driver is loaded */
1260         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1261         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1262         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1263         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1264         IXGBE_WRITE_FLUSH(hw);
1265
1266         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1267                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1268                              (int) hw->mac.type, (int) hw->phy.type,
1269                              (int) hw->phy.sfp_type);
1270         else
1271                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1272                              (int) hw->mac.type, (int) hw->phy.type);
1273
1274         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1275                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1276                      pci_dev->id.device_id);
1277
1278         rte_intr_callback_register(intr_handle,
1279                                    ixgbe_dev_interrupt_handler, eth_dev);
1280
1281         /* enable uio/vfio intr/eventfd mapping */
1282         rte_intr_enable(intr_handle);
1283
1284         /* enable support intr */
1285         ixgbe_enable_intr(eth_dev);
1286
1287         /* initialize filter info */
1288         memset(filter_info, 0,
1289                sizeof(struct ixgbe_filter_info));
1290
1291         /* initialize 5tuple filter list */
1292         TAILQ_INIT(&filter_info->fivetuple_list);
1293
1294         /* initialize flow director filter list & hash */
1295         ixgbe_fdir_filter_init(eth_dev);
1296
1297         /* initialize l2 tunnel filter list & hash */
1298         ixgbe_l2_tn_filter_init(eth_dev);
1299
1300         /* initialize flow filter lists */
1301         ixgbe_filterlist_init();
1302
1303         /* initialize bandwidth configuration info */
1304         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1305
1306         /* initialize Traffic Manager configuration */
1307         ixgbe_tm_conf_init(eth_dev);
1308
1309         return 0;
1310 }
1311
1312 static int
1313 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1314 {
1315         PMD_INIT_FUNC_TRACE();
1316
1317         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1318                 return 0;
1319
1320         ixgbe_dev_close(eth_dev);
1321
1322         return 0;
1323 }
1324
1325 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1326 {
1327         struct ixgbe_filter_info *filter_info =
1328                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1329         struct ixgbe_5tuple_filter *p_5tuple;
1330
1331         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1332                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1333                              p_5tuple,
1334                              entries);
1335                 rte_free(p_5tuple);
1336         }
1337         memset(filter_info->fivetuple_mask, 0,
1338                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1339
1340         return 0;
1341 }
1342
1343 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1344 {
1345         struct ixgbe_hw_fdir_info *fdir_info =
1346                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1347         struct ixgbe_fdir_filter *fdir_filter;
1348
1349                 if (fdir_info->hash_map)
1350                 rte_free(fdir_info->hash_map);
1351         if (fdir_info->hash_handle)
1352                 rte_hash_free(fdir_info->hash_handle);
1353
1354         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1355                 TAILQ_REMOVE(&fdir_info->fdir_list,
1356                              fdir_filter,
1357                              entries);
1358                 rte_free(fdir_filter);
1359         }
1360
1361         return 0;
1362 }
1363
1364 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1365 {
1366         struct ixgbe_l2_tn_info *l2_tn_info =
1367                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1368         struct ixgbe_l2_tn_filter *l2_tn_filter;
1369
1370         if (l2_tn_info->hash_map)
1371                 rte_free(l2_tn_info->hash_map);
1372         if (l2_tn_info->hash_handle)
1373                 rte_hash_free(l2_tn_info->hash_handle);
1374
1375         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1376                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1377                              l2_tn_filter,
1378                              entries);
1379                 rte_free(l2_tn_filter);
1380         }
1381
1382         return 0;
1383 }
1384
1385 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1386 {
1387         struct ixgbe_hw_fdir_info *fdir_info =
1388                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1389         char fdir_hash_name[RTE_HASH_NAMESIZE];
1390         struct rte_hash_parameters fdir_hash_params = {
1391                 .name = fdir_hash_name,
1392                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1393                 .key_len = sizeof(union ixgbe_atr_input),
1394                 .hash_func = rte_hash_crc,
1395                 .hash_func_init_val = 0,
1396                 .socket_id = rte_socket_id(),
1397         };
1398
1399         TAILQ_INIT(&fdir_info->fdir_list);
1400         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1401                  "fdir_%s", eth_dev->device->name);
1402         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1403         if (!fdir_info->hash_handle) {
1404                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1405                 return -EINVAL;
1406         }
1407         fdir_info->hash_map = rte_zmalloc("ixgbe",
1408                                           sizeof(struct ixgbe_fdir_filter *) *
1409                                           IXGBE_MAX_FDIR_FILTER_NUM,
1410                                           0);
1411         if (!fdir_info->hash_map) {
1412                 PMD_INIT_LOG(ERR,
1413                              "Failed to allocate memory for fdir hash map!");
1414                 return -ENOMEM;
1415         }
1416         fdir_info->mask_added = FALSE;
1417
1418         return 0;
1419 }
1420
1421 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1422 {
1423         struct ixgbe_l2_tn_info *l2_tn_info =
1424                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1425         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1426         struct rte_hash_parameters l2_tn_hash_params = {
1427                 .name = l2_tn_hash_name,
1428                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1429                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1430                 .hash_func = rte_hash_crc,
1431                 .hash_func_init_val = 0,
1432                 .socket_id = rte_socket_id(),
1433         };
1434
1435         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1436         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1437                  "l2_tn_%s", eth_dev->device->name);
1438         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1439         if (!l2_tn_info->hash_handle) {
1440                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1441                 return -EINVAL;
1442         }
1443         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1444                                    sizeof(struct ixgbe_l2_tn_filter *) *
1445                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1446                                    0);
1447         if (!l2_tn_info->hash_map) {
1448                 PMD_INIT_LOG(ERR,
1449                         "Failed to allocate memory for L2 TN hash map!");
1450                 return -ENOMEM;
1451         }
1452         l2_tn_info->e_tag_en = FALSE;
1453         l2_tn_info->e_tag_fwd_en = FALSE;
1454         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1455
1456         return 0;
1457 }
1458 /*
1459  * Negotiate mailbox API version with the PF.
1460  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1461  * Then we try to negotiate starting with the most recent one.
1462  * If all negotiation attempts fail, then we will proceed with
1463  * the default one (ixgbe_mbox_api_10).
1464  */
1465 static void
1466 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1467 {
1468         int32_t i;
1469
1470         /* start with highest supported, proceed down */
1471         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1472                 ixgbe_mbox_api_13,
1473                 ixgbe_mbox_api_12,
1474                 ixgbe_mbox_api_11,
1475                 ixgbe_mbox_api_10,
1476         };
1477
1478         for (i = 0;
1479                         i != RTE_DIM(sup_ver) &&
1480                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1481                         i++)
1482                 ;
1483 }
1484
1485 static void
1486 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1487 {
1488         uint64_t random;
1489
1490         /* Set Organizationally Unique Identifier (OUI) prefix. */
1491         mac_addr->addr_bytes[0] = 0x00;
1492         mac_addr->addr_bytes[1] = 0x09;
1493         mac_addr->addr_bytes[2] = 0xC0;
1494         /* Force indication of locally assigned MAC address. */
1495         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1496         /* Generate the last 3 bytes of the MAC address with a random number. */
1497         random = rte_rand();
1498         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1499 }
1500
1501 static int
1502 devarg_handle_int(__rte_unused const char *key, const char *value,
1503                   void *extra_args)
1504 {
1505         uint16_t *n = extra_args;
1506
1507         if (value == NULL || extra_args == NULL)
1508                 return -EINVAL;
1509
1510         *n = (uint16_t)strtoul(value, NULL, 0);
1511         if (*n == USHRT_MAX && errno == ERANGE)
1512                 return -1;
1513
1514         return 0;
1515 }
1516
1517 static void
1518 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1519                       struct rte_devargs *devargs)
1520 {
1521         struct rte_kvargs *kvlist;
1522         uint16_t pflink_fullchk;
1523
1524         if (devargs == NULL)
1525                 return;
1526
1527         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1528         if (kvlist == NULL)
1529                 return;
1530
1531         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1532             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1533                                devarg_handle_int, &pflink_fullchk) == 0 &&
1534             pflink_fullchk == 1)
1535                 adapter->pflink_fullchk = 1;
1536
1537         rte_kvargs_free(kvlist);
1538 }
1539
1540 /*
1541  * Virtual Function device init
1542  */
1543 static int
1544 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1545 {
1546         int diag;
1547         uint32_t tc, tcs;
1548         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1549         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1550         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1551         struct ixgbe_hw *hw =
1552                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1553         struct ixgbe_vfta *shadow_vfta =
1554                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1555         struct ixgbe_hwstrip *hwstrip =
1556                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1557         struct rte_ether_addr *perm_addr =
1558                 (struct rte_ether_addr *)hw->mac.perm_addr;
1559
1560         PMD_INIT_FUNC_TRACE();
1561
1562         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1563         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1564         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1565         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1566         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1567         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1568
1569         /* for secondary processes, we don't initialise any further as primary
1570          * has already done this work. Only check we don't need a different
1571          * RX function
1572          */
1573         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1574                 struct ixgbe_tx_queue *txq;
1575                 /* TX queue function in primary, set by last queue initialized
1576                  * Tx queue may not initialized by primary process
1577                  */
1578                 if (eth_dev->data->tx_queues) {
1579                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1580                         ixgbe_set_tx_function(eth_dev, txq);
1581                 } else {
1582                         /* Use default TX function if we get here */
1583                         PMD_INIT_LOG(NOTICE,
1584                                      "No TX queues configured yet. Using default TX function.");
1585                 }
1586
1587                 ixgbe_set_rx_function(eth_dev);
1588
1589                 return 0;
1590         }
1591
1592         rte_atomic32_clear(&ad->link_thread_running);
1593         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1594                               pci_dev->device.devargs);
1595
1596         rte_eth_copy_pci_info(eth_dev, pci_dev);
1597         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1598
1599         hw->device_id = pci_dev->id.device_id;
1600         hw->vendor_id = pci_dev->id.vendor_id;
1601         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1602
1603         /* initialize the vfta */
1604         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1605
1606         /* initialize the hw strip bitmap*/
1607         memset(hwstrip, 0, sizeof(*hwstrip));
1608
1609         /* Initialize the shared code (base driver) */
1610         diag = ixgbe_init_shared_code(hw);
1611         if (diag != IXGBE_SUCCESS) {
1612                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1613                 return -EIO;
1614         }
1615
1616         /* init_mailbox_params */
1617         hw->mbx.ops.init_params(hw);
1618
1619         /* Reset the hw statistics */
1620         ixgbevf_dev_stats_reset(eth_dev);
1621
1622         /* Disable the interrupts for VF */
1623         ixgbevf_intr_disable(eth_dev);
1624
1625         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1626         diag = hw->mac.ops.reset_hw(hw);
1627
1628         /*
1629          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1630          * the underlying PF driver has not assigned a MAC address to the VF.
1631          * In this case, assign a random MAC address.
1632          */
1633         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1634                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1635                 /*
1636                  * This error code will be propagated to the app by
1637                  * rte_eth_dev_reset, so use a public error code rather than
1638                  * the internal-only IXGBE_ERR_RESET_FAILED
1639                  */
1640                 return -EAGAIN;
1641         }
1642
1643         /* negotiate mailbox API version to use with the PF. */
1644         ixgbevf_negotiate_api(hw);
1645
1646         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1647         ixgbevf_get_queues(hw, &tcs, &tc);
1648
1649         /* Allocate memory for storing MAC addresses */
1650         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1651                                                hw->mac.num_rar_entries, 0);
1652         if (eth_dev->data->mac_addrs == NULL) {
1653                 PMD_INIT_LOG(ERR,
1654                              "Failed to allocate %u bytes needed to store "
1655                              "MAC addresses",
1656                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1657                 return -ENOMEM;
1658         }
1659
1660         /* Generate a random MAC address, if none was assigned by PF. */
1661         if (rte_is_zero_ether_addr(perm_addr)) {
1662                 generate_random_mac_addr(perm_addr);
1663                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1664                 if (diag) {
1665                         rte_free(eth_dev->data->mac_addrs);
1666                         eth_dev->data->mac_addrs = NULL;
1667                         return diag;
1668                 }
1669                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1670                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1671                              "%02x:%02x:%02x:%02x:%02x:%02x",
1672                              perm_addr->addr_bytes[0],
1673                              perm_addr->addr_bytes[1],
1674                              perm_addr->addr_bytes[2],
1675                              perm_addr->addr_bytes[3],
1676                              perm_addr->addr_bytes[4],
1677                              perm_addr->addr_bytes[5]);
1678         }
1679
1680         /* Copy the permanent MAC address */
1681         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1682
1683         /* reset the hardware with the new settings */
1684         diag = hw->mac.ops.start_hw(hw);
1685         switch (diag) {
1686         case  0:
1687                 break;
1688
1689         default:
1690                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1691                 return -EIO;
1692         }
1693
1694         rte_intr_callback_register(intr_handle,
1695                                    ixgbevf_dev_interrupt_handler, eth_dev);
1696         rte_intr_enable(intr_handle);
1697         ixgbevf_intr_enable(eth_dev);
1698
1699         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1700                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1701                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1702
1703         return 0;
1704 }
1705
1706 /* Virtual Function device uninit */
1707
1708 static int
1709 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1710 {
1711         PMD_INIT_FUNC_TRACE();
1712
1713         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1714                 return 0;
1715
1716         ixgbevf_dev_close(eth_dev);
1717
1718         return 0;
1719 }
1720
1721 static int
1722 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1723                 struct rte_pci_device *pci_dev)
1724 {
1725         char name[RTE_ETH_NAME_MAX_LEN];
1726         struct rte_eth_dev *pf_ethdev;
1727         struct rte_eth_devargs eth_da;
1728         int i, retval;
1729
1730         if (pci_dev->device.devargs) {
1731                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1732                                 &eth_da);
1733                 if (retval)
1734                         return retval;
1735         } else
1736                 memset(&eth_da, 0, sizeof(eth_da));
1737
1738         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1739                 sizeof(struct ixgbe_adapter),
1740                 eth_dev_pci_specific_init, pci_dev,
1741                 eth_ixgbe_dev_init, NULL);
1742
1743         if (retval || eth_da.nb_representor_ports < 1)
1744                 return retval;
1745
1746         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1747         if (pf_ethdev == NULL)
1748                 return -ENODEV;
1749
1750         /* probe VF representor ports */
1751         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1752                 struct ixgbe_vf_info *vfinfo;
1753                 struct ixgbe_vf_representor representor;
1754
1755                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1756                         pf_ethdev->data->dev_private);
1757                 if (vfinfo == NULL) {
1758                         PMD_DRV_LOG(ERR,
1759                                 "no virtual functions supported by PF");
1760                         break;
1761                 }
1762
1763                 representor.vf_id = eth_da.representor_ports[i];
1764                 representor.switch_domain_id = vfinfo->switch_domain_id;
1765                 representor.pf_ethdev = pf_ethdev;
1766
1767                 /* representor port net_bdf_port */
1768                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1769                         pci_dev->device.name,
1770                         eth_da.representor_ports[i]);
1771
1772                 retval = rte_eth_dev_create(&pci_dev->device, name,
1773                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1774                         ixgbe_vf_representor_init, &representor);
1775
1776                 if (retval)
1777                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1778                                 "representor %s.", name);
1779         }
1780
1781         return 0;
1782 }
1783
1784 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1785 {
1786         struct rte_eth_dev *ethdev;
1787
1788         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1789         if (!ethdev)
1790                 return 0;
1791
1792         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1793                 return rte_eth_dev_pci_generic_remove(pci_dev,
1794                                         ixgbe_vf_representor_uninit);
1795         else
1796                 return rte_eth_dev_pci_generic_remove(pci_dev,
1797                                                 eth_ixgbe_dev_uninit);
1798 }
1799
1800 static struct rte_pci_driver rte_ixgbe_pmd = {
1801         .id_table = pci_id_ixgbe_map,
1802         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1803         .probe = eth_ixgbe_pci_probe,
1804         .remove = eth_ixgbe_pci_remove,
1805 };
1806
1807 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1808         struct rte_pci_device *pci_dev)
1809 {
1810         return rte_eth_dev_pci_generic_probe(pci_dev,
1811                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1812 }
1813
1814 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1815 {
1816         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1817 }
1818
1819 /*
1820  * virtual function driver struct
1821  */
1822 static struct rte_pci_driver rte_ixgbevf_pmd = {
1823         .id_table = pci_id_ixgbevf_map,
1824         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1825         .probe = eth_ixgbevf_pci_probe,
1826         .remove = eth_ixgbevf_pci_remove,
1827 };
1828
1829 static int
1830 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1831 {
1832         struct ixgbe_hw *hw =
1833                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1834         struct ixgbe_vfta *shadow_vfta =
1835                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1836         uint32_t vfta;
1837         uint32_t vid_idx;
1838         uint32_t vid_bit;
1839
1840         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1841         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1842         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1843         if (on)
1844                 vfta |= vid_bit;
1845         else
1846                 vfta &= ~vid_bit;
1847         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1848
1849         /* update local VFTA copy */
1850         shadow_vfta->vfta[vid_idx] = vfta;
1851
1852         return 0;
1853 }
1854
1855 static void
1856 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1857 {
1858         if (on)
1859                 ixgbe_vlan_hw_strip_enable(dev, queue);
1860         else
1861                 ixgbe_vlan_hw_strip_disable(dev, queue);
1862 }
1863
1864 static int
1865 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1866                     enum rte_vlan_type vlan_type,
1867                     uint16_t tpid)
1868 {
1869         struct ixgbe_hw *hw =
1870                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1871         int ret = 0;
1872         uint32_t reg;
1873         uint32_t qinq;
1874
1875         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1876         qinq &= IXGBE_DMATXCTL_GDV;
1877
1878         switch (vlan_type) {
1879         case ETH_VLAN_TYPE_INNER:
1880                 if (qinq) {
1881                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1882                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1883                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1884                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1885                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1886                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1887                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1888                 } else {
1889                         ret = -ENOTSUP;
1890                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1891                                     " by single VLAN");
1892                 }
1893                 break;
1894         case ETH_VLAN_TYPE_OUTER:
1895                 if (qinq) {
1896                         /* Only the high 16-bits is valid */
1897                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1898                                         IXGBE_EXVET_VET_EXT_SHIFT);
1899                 } else {
1900                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1901                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1902                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1903                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1904                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1905                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1906                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1907                 }
1908
1909                 break;
1910         default:
1911                 ret = -EINVAL;
1912                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1913                 break;
1914         }
1915
1916         return ret;
1917 }
1918
1919 void
1920 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1921 {
1922         struct ixgbe_hw *hw =
1923                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1924         uint32_t vlnctrl;
1925
1926         PMD_INIT_FUNC_TRACE();
1927
1928         /* Filter Table Disable */
1929         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1930         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1931
1932         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1933 }
1934
1935 void
1936 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1937 {
1938         struct ixgbe_hw *hw =
1939                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1940         struct ixgbe_vfta *shadow_vfta =
1941                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1942         uint32_t vlnctrl;
1943         uint16_t i;
1944
1945         PMD_INIT_FUNC_TRACE();
1946
1947         /* Filter Table Enable */
1948         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1949         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1950         vlnctrl |= IXGBE_VLNCTRL_VFE;
1951
1952         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1953
1954         /* write whatever is in local vfta copy */
1955         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1956                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1957 }
1958
1959 static void
1960 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1961 {
1962         struct ixgbe_hwstrip *hwstrip =
1963                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1964         struct ixgbe_rx_queue *rxq;
1965
1966         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1967                 return;
1968
1969         if (on)
1970                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1971         else
1972                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1973
1974         if (queue >= dev->data->nb_rx_queues)
1975                 return;
1976
1977         rxq = dev->data->rx_queues[queue];
1978
1979         if (on) {
1980                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1981                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1982         } else {
1983                 rxq->vlan_flags = PKT_RX_VLAN;
1984                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1985         }
1986 }
1987
1988 static void
1989 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1990 {
1991         struct ixgbe_hw *hw =
1992                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1993         uint32_t ctrl;
1994
1995         PMD_INIT_FUNC_TRACE();
1996
1997         if (hw->mac.type == ixgbe_mac_82598EB) {
1998                 /* No queue level support */
1999                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2000                 return;
2001         }
2002
2003         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2004         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2005         ctrl &= ~IXGBE_RXDCTL_VME;
2006         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2007
2008         /* record those setting for HW strip per queue */
2009         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2010 }
2011
2012 static void
2013 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2014 {
2015         struct ixgbe_hw *hw =
2016                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2017         uint32_t ctrl;
2018
2019         PMD_INIT_FUNC_TRACE();
2020
2021         if (hw->mac.type == ixgbe_mac_82598EB) {
2022                 /* No queue level supported */
2023                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2024                 return;
2025         }
2026
2027         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2028         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2029         ctrl |= IXGBE_RXDCTL_VME;
2030         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2031
2032         /* record those setting for HW strip per queue */
2033         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2034 }
2035
2036 static void
2037 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2038 {
2039         struct ixgbe_hw *hw =
2040                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2041         uint32_t ctrl;
2042
2043         PMD_INIT_FUNC_TRACE();
2044
2045         /* DMATXCTRL: Geric Double VLAN Disable */
2046         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2047         ctrl &= ~IXGBE_DMATXCTL_GDV;
2048         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2049
2050         /* CTRL_EXT: Global Double VLAN Disable */
2051         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2052         ctrl &= ~IXGBE_EXTENDED_VLAN;
2053         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2054
2055 }
2056
2057 static void
2058 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2059 {
2060         struct ixgbe_hw *hw =
2061                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2062         uint32_t ctrl;
2063
2064         PMD_INIT_FUNC_TRACE();
2065
2066         /* DMATXCTRL: Geric Double VLAN Enable */
2067         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2068         ctrl |= IXGBE_DMATXCTL_GDV;
2069         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2070
2071         /* CTRL_EXT: Global Double VLAN Enable */
2072         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2073         ctrl |= IXGBE_EXTENDED_VLAN;
2074         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2075
2076         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2077         if (hw->mac.type == ixgbe_mac_X550 ||
2078             hw->mac.type == ixgbe_mac_X550EM_x ||
2079             hw->mac.type == ixgbe_mac_X550EM_a) {
2080                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2081                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2082                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2083         }
2084
2085         /*
2086          * VET EXT field in the EXVET register = 0x8100 by default
2087          * So no need to change. Same to VT field of DMATXCTL register
2088          */
2089 }
2090
2091 void
2092 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2093 {
2094         struct ixgbe_hw *hw =
2095                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2096         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2097         uint32_t ctrl;
2098         uint16_t i;
2099         struct ixgbe_rx_queue *rxq;
2100         bool on;
2101
2102         PMD_INIT_FUNC_TRACE();
2103
2104         if (hw->mac.type == ixgbe_mac_82598EB) {
2105                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2106                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2107                         ctrl |= IXGBE_VLNCTRL_VME;
2108                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2109                 } else {
2110                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2111                         ctrl &= ~IXGBE_VLNCTRL_VME;
2112                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2113                 }
2114         } else {
2115                 /*
2116                  * Other 10G NIC, the VLAN strip can be setup
2117                  * per queue in RXDCTL
2118                  */
2119                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2120                         rxq = dev->data->rx_queues[i];
2121                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2122                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2123                                 ctrl |= IXGBE_RXDCTL_VME;
2124                                 on = TRUE;
2125                         } else {
2126                                 ctrl &= ~IXGBE_RXDCTL_VME;
2127                                 on = FALSE;
2128                         }
2129                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2130
2131                         /* record those setting for HW strip per queue */
2132                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2133                 }
2134         }
2135 }
2136
2137 static void
2138 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2139 {
2140         uint16_t i;
2141         struct rte_eth_rxmode *rxmode;
2142         struct ixgbe_rx_queue *rxq;
2143
2144         if (mask & ETH_VLAN_STRIP_MASK) {
2145                 rxmode = &dev->data->dev_conf.rxmode;
2146                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2147                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2148                                 rxq = dev->data->rx_queues[i];
2149                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2150                         }
2151                 else
2152                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2153                                 rxq = dev->data->rx_queues[i];
2154                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2155                         }
2156         }
2157 }
2158
2159 static int
2160 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2161 {
2162         struct rte_eth_rxmode *rxmode;
2163         rxmode = &dev->data->dev_conf.rxmode;
2164
2165         if (mask & ETH_VLAN_STRIP_MASK) {
2166                 ixgbe_vlan_hw_strip_config(dev);
2167         }
2168
2169         if (mask & ETH_VLAN_FILTER_MASK) {
2170                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2171                         ixgbe_vlan_hw_filter_enable(dev);
2172                 else
2173                         ixgbe_vlan_hw_filter_disable(dev);
2174         }
2175
2176         if (mask & ETH_VLAN_EXTEND_MASK) {
2177                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2178                         ixgbe_vlan_hw_extend_enable(dev);
2179                 else
2180                         ixgbe_vlan_hw_extend_disable(dev);
2181         }
2182
2183         return 0;
2184 }
2185
2186 static int
2187 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2188 {
2189         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2190
2191         ixgbe_vlan_offload_config(dev, mask);
2192
2193         return 0;
2194 }
2195
2196 static void
2197 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2198 {
2199         struct ixgbe_hw *hw =
2200                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2201         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2202         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2203
2204         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2205         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2206 }
2207
2208 static int
2209 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2210 {
2211         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2212
2213         switch (nb_rx_q) {
2214         case 1:
2215         case 2:
2216                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2217                 break;
2218         case 4:
2219                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2220                 break;
2221         default:
2222                 return -EINVAL;
2223         }
2224
2225         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2226                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2227         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2228                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2229         return 0;
2230 }
2231
2232 static int
2233 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2234 {
2235         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2236         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2237         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2238         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2239
2240         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2241                 /* check multi-queue mode */
2242                 switch (dev_conf->rxmode.mq_mode) {
2243                 case ETH_MQ_RX_VMDQ_DCB:
2244                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2245                         break;
2246                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2247                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2248                         PMD_INIT_LOG(ERR, "SRIOV active,"
2249                                         " unsupported mq_mode rx %d.",
2250                                         dev_conf->rxmode.mq_mode);
2251                         return -EINVAL;
2252                 case ETH_MQ_RX_RSS:
2253                 case ETH_MQ_RX_VMDQ_RSS:
2254                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2255                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2256                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2257                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2258                                                 " invalid queue number"
2259                                                 " for VMDQ RSS, allowed"
2260                                                 " value are 1, 2 or 4.");
2261                                         return -EINVAL;
2262                                 }
2263                         break;
2264                 case ETH_MQ_RX_VMDQ_ONLY:
2265                 case ETH_MQ_RX_NONE:
2266                         /* if nothing mq mode configure, use default scheme */
2267                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2268                         break;
2269                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2270                         /* SRIOV only works in VMDq enable mode */
2271                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2272                                         " wrong mq_mode rx %d.",
2273                                         dev_conf->rxmode.mq_mode);
2274                         return -EINVAL;
2275                 }
2276
2277                 switch (dev_conf->txmode.mq_mode) {
2278                 case ETH_MQ_TX_VMDQ_DCB:
2279                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2280                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2281                         break;
2282                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2283                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2284                         break;
2285                 }
2286
2287                 /* check valid queue number */
2288                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2289                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2290                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2291                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2292                                         " must be less than or equal to %d.",
2293                                         nb_rx_q, nb_tx_q,
2294                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2295                         return -EINVAL;
2296                 }
2297         } else {
2298                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2299                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2300                                           " not supported.");
2301                         return -EINVAL;
2302                 }
2303                 /* check configuration for vmdb+dcb mode */
2304                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2305                         const struct rte_eth_vmdq_dcb_conf *conf;
2306
2307                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2308                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2309                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2310                                 return -EINVAL;
2311                         }
2312                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2313                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2314                                conf->nb_queue_pools == ETH_32_POOLS)) {
2315                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2316                                                 " nb_queue_pools must be %d or %d.",
2317                                                 ETH_16_POOLS, ETH_32_POOLS);
2318                                 return -EINVAL;
2319                         }
2320                 }
2321                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2322                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2323
2324                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2325                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2326                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2327                                 return -EINVAL;
2328                         }
2329                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2330                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2331                                conf->nb_queue_pools == ETH_32_POOLS)) {
2332                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2333                                                 " nb_queue_pools != %d and"
2334                                                 " nb_queue_pools != %d.",
2335                                                 ETH_16_POOLS, ETH_32_POOLS);
2336                                 return -EINVAL;
2337                         }
2338                 }
2339
2340                 /* For DCB mode check our configuration before we go further */
2341                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2342                         const struct rte_eth_dcb_rx_conf *conf;
2343
2344                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2345                         if (!(conf->nb_tcs == ETH_4_TCS ||
2346                                conf->nb_tcs == ETH_8_TCS)) {
2347                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2348                                                 " and nb_tcs != %d.",
2349                                                 ETH_4_TCS, ETH_8_TCS);
2350                                 return -EINVAL;
2351                         }
2352                 }
2353
2354                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2355                         const struct rte_eth_dcb_tx_conf *conf;
2356
2357                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2358                         if (!(conf->nb_tcs == ETH_4_TCS ||
2359                                conf->nb_tcs == ETH_8_TCS)) {
2360                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2361                                                 " and nb_tcs != %d.",
2362                                                 ETH_4_TCS, ETH_8_TCS);
2363                                 return -EINVAL;
2364                         }
2365                 }
2366
2367                 /*
2368                  * When DCB/VT is off, maximum number of queues changes,
2369                  * except for 82598EB, which remains constant.
2370                  */
2371                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2372                                 hw->mac.type != ixgbe_mac_82598EB) {
2373                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2374                                 PMD_INIT_LOG(ERR,
2375                                              "Neither VT nor DCB are enabled, "
2376                                              "nb_tx_q > %d.",
2377                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2378                                 return -EINVAL;
2379                         }
2380                 }
2381         }
2382         return 0;
2383 }
2384
2385 static int
2386 ixgbe_dev_configure(struct rte_eth_dev *dev)
2387 {
2388         struct ixgbe_interrupt *intr =
2389                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2390         struct ixgbe_adapter *adapter = dev->data->dev_private;
2391         int ret;
2392
2393         PMD_INIT_FUNC_TRACE();
2394
2395         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2396                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2397
2398         /* multipe queue mode checking */
2399         ret  = ixgbe_check_mq_mode(dev);
2400         if (ret != 0) {
2401                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2402                             ret);
2403                 return ret;
2404         }
2405
2406         /* set flag to update link status after init */
2407         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2408
2409         /*
2410          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2411          * allocation or vector Rx preconditions we will reset it.
2412          */
2413         adapter->rx_bulk_alloc_allowed = true;
2414         adapter->rx_vec_allowed = true;
2415
2416         return 0;
2417 }
2418
2419 static void
2420 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2421 {
2422         struct ixgbe_hw *hw =
2423                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2424         struct ixgbe_interrupt *intr =
2425                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2426         uint32_t gpie;
2427
2428         /* only set up it on X550EM_X */
2429         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2430                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2431                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2432                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2433                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2434                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2435         }
2436 }
2437
2438 int
2439 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2440                         uint16_t tx_rate, uint64_t q_msk)
2441 {
2442         struct ixgbe_hw *hw;
2443         struct ixgbe_vf_info *vfinfo;
2444         struct rte_eth_link link;
2445         uint8_t  nb_q_per_pool;
2446         uint32_t queue_stride;
2447         uint32_t queue_idx, idx = 0, vf_idx;
2448         uint32_t queue_end;
2449         uint16_t total_rate = 0;
2450         struct rte_pci_device *pci_dev;
2451         int ret;
2452
2453         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2454         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2455         if (ret < 0)
2456                 return ret;
2457
2458         if (vf >= pci_dev->max_vfs)
2459                 return -EINVAL;
2460
2461         if (tx_rate > link.link_speed)
2462                 return -EINVAL;
2463
2464         if (q_msk == 0)
2465                 return 0;
2466
2467         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2468         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2469         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2470         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2471         queue_idx = vf * queue_stride;
2472         queue_end = queue_idx + nb_q_per_pool - 1;
2473         if (queue_end >= hw->mac.max_tx_queues)
2474                 return -EINVAL;
2475
2476         if (vfinfo) {
2477                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2478                         if (vf_idx == vf)
2479                                 continue;
2480                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2481                                 idx++)
2482                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2483                 }
2484         } else {
2485                 return -EINVAL;
2486         }
2487
2488         /* Store tx_rate for this vf. */
2489         for (idx = 0; idx < nb_q_per_pool; idx++) {
2490                 if (((uint64_t)0x1 << idx) & q_msk) {
2491                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2492                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2493                         total_rate += tx_rate;
2494                 }
2495         }
2496
2497         if (total_rate > dev->data->dev_link.link_speed) {
2498                 /* Reset stored TX rate of the VF if it causes exceed
2499                  * link speed.
2500                  */
2501                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2502                 return -EINVAL;
2503         }
2504
2505         /* Set RTTBCNRC of each queue/pool for vf X  */
2506         for (; queue_idx <= queue_end; queue_idx++) {
2507                 if (0x1 & q_msk)
2508                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2509                 q_msk = q_msk >> 1;
2510         }
2511
2512         return 0;
2513 }
2514
2515 static int
2516 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2517 {
2518         struct ixgbe_adapter *adapter = dev->data->dev_private;
2519         int err;
2520         uint32_t mflcn;
2521
2522         ixgbe_setup_fc(hw);
2523
2524         err = ixgbe_fc_enable(hw);
2525
2526         /* Not negotiated is not an error case */
2527         if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2528                 /*
2529                  *check if we want to forward MAC frames - driver doesn't
2530                  *have native capability to do that,
2531                  *so we'll write the registers ourselves
2532                  */
2533
2534                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2535
2536                 /* set or clear MFLCN.PMCF bit depending on configuration */
2537                 if (adapter->mac_ctrl_frame_fwd != 0)
2538                         mflcn |= IXGBE_MFLCN_PMCF;
2539                 else
2540                         mflcn &= ~IXGBE_MFLCN_PMCF;
2541
2542                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2543                 IXGBE_WRITE_FLUSH(hw);
2544
2545                 return 0;
2546         }
2547         return err;
2548 }
2549
2550 /*
2551  * Configure device link speed and setup link.
2552  * It returns 0 on success.
2553  */
2554 static int
2555 ixgbe_dev_start(struct rte_eth_dev *dev)
2556 {
2557         struct ixgbe_hw *hw =
2558                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2559         struct ixgbe_vf_info *vfinfo =
2560                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2561         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2562         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2563         uint32_t intr_vector = 0;
2564         int err;
2565         bool link_up = false, negotiate = 0;
2566         uint32_t speed = 0;
2567         uint32_t allowed_speeds = 0;
2568         int mask = 0;
2569         int status;
2570         uint16_t vf, idx;
2571         uint32_t *link_speeds;
2572         struct ixgbe_tm_conf *tm_conf =
2573                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2574         struct ixgbe_macsec_setting *macsec_setting =
2575                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2576
2577         PMD_INIT_FUNC_TRACE();
2578
2579         /* Stop the link setup handler before resetting the HW. */
2580         ixgbe_dev_wait_setup_link_complete(dev, 0);
2581
2582         /* disable uio/vfio intr/eventfd mapping */
2583         rte_intr_disable(intr_handle);
2584
2585         /* stop adapter */
2586         hw->adapter_stopped = 0;
2587         ixgbe_stop_adapter(hw);
2588
2589         /* reinitialize adapter
2590          * this calls reset and start
2591          */
2592         status = ixgbe_pf_reset_hw(hw);
2593         if (status != 0)
2594                 return -1;
2595         hw->mac.ops.start_hw(hw);
2596         hw->mac.get_link_status = true;
2597
2598         /* configure PF module if SRIOV enabled */
2599         ixgbe_pf_host_configure(dev);
2600
2601         ixgbe_dev_phy_intr_setup(dev);
2602
2603         /* check and configure queue intr-vector mapping */
2604         if ((rte_intr_cap_multiple(intr_handle) ||
2605              !RTE_ETH_DEV_SRIOV(dev).active) &&
2606             dev->data->dev_conf.intr_conf.rxq != 0) {
2607                 intr_vector = dev->data->nb_rx_queues;
2608                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2609                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2610                                         IXGBE_MAX_INTR_QUEUE_NUM);
2611                         return -ENOTSUP;
2612                 }
2613                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2614                         return -1;
2615         }
2616
2617         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2618                 intr_handle->intr_vec =
2619                         rte_zmalloc("intr_vec",
2620                                     dev->data->nb_rx_queues * sizeof(int), 0);
2621                 if (intr_handle->intr_vec == NULL) {
2622                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2623                                      " intr_vec", dev->data->nb_rx_queues);
2624                         return -ENOMEM;
2625                 }
2626         }
2627
2628         /* confiugre msix for sleep until rx interrupt */
2629         ixgbe_configure_msix(dev);
2630
2631         /* initialize transmission unit */
2632         ixgbe_dev_tx_init(dev);
2633
2634         /* This can fail when allocating mbufs for descriptor rings */
2635         err = ixgbe_dev_rx_init(dev);
2636         if (err) {
2637                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2638                 goto error;
2639         }
2640
2641         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2642                 ETH_VLAN_EXTEND_MASK;
2643         err = ixgbe_vlan_offload_config(dev, mask);
2644         if (err) {
2645                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2646                 goto error;
2647         }
2648
2649         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2650                 /* Enable vlan filtering for VMDq */
2651                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2652         }
2653
2654         /* Configure DCB hw */
2655         ixgbe_configure_dcb(dev);
2656
2657         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2658                 err = ixgbe_fdir_configure(dev);
2659                 if (err)
2660                         goto error;
2661         }
2662
2663         /* Restore vf rate limit */
2664         if (vfinfo != NULL) {
2665                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2666                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2667                                 if (vfinfo[vf].tx_rate[idx] != 0)
2668                                         ixgbe_set_vf_rate_limit(
2669                                                 dev, vf,
2670                                                 vfinfo[vf].tx_rate[idx],
2671                                                 1 << idx);
2672         }
2673
2674         ixgbe_restore_statistics_mapping(dev);
2675
2676         err = ixgbe_flow_ctrl_enable(dev, hw);
2677         if (err < 0) {
2678                 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2679                 goto error;
2680         }
2681
2682         err = ixgbe_dev_rxtx_start(dev);
2683         if (err < 0) {
2684                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2685                 goto error;
2686         }
2687
2688         /* Skip link setup if loopback mode is enabled. */
2689         if (dev->data->dev_conf.lpbk_mode != 0) {
2690                 err = ixgbe_check_supported_loopback_mode(dev);
2691                 if (err < 0) {
2692                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2693                         goto error;
2694                 } else {
2695                         goto skip_link_setup;
2696                 }
2697         }
2698
2699         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2700                 err = hw->mac.ops.setup_sfp(hw);
2701                 if (err)
2702                         goto error;
2703         }
2704
2705         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2706                 /* Turn on the copper */
2707                 ixgbe_set_phy_power(hw, true);
2708         } else {
2709                 /* Turn on the laser */
2710                 ixgbe_enable_tx_laser(hw);
2711         }
2712
2713         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2714         if (err)
2715                 goto error;
2716         dev->data->dev_link.link_status = link_up;
2717
2718         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2719         if (err)
2720                 goto error;
2721
2722         switch (hw->mac.type) {
2723         case ixgbe_mac_X550:
2724         case ixgbe_mac_X550EM_x:
2725         case ixgbe_mac_X550EM_a:
2726                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2727                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2728                         ETH_LINK_SPEED_10G;
2729                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2730                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2731                         allowed_speeds = ETH_LINK_SPEED_10M |
2732                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2733                 break;
2734         default:
2735                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2736                         ETH_LINK_SPEED_10G;
2737         }
2738
2739         link_speeds = &dev->data->dev_conf.link_speeds;
2740
2741         /* Ignore autoneg flag bit and check the validity of
2742          * link_speed
2743          */
2744         if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2745                 PMD_INIT_LOG(ERR, "Invalid link setting");
2746                 goto error;
2747         }
2748
2749         speed = 0x0;
2750         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2751                 switch (hw->mac.type) {
2752                 case ixgbe_mac_82598EB:
2753                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2754                         break;
2755                 case ixgbe_mac_82599EB:
2756                 case ixgbe_mac_X540:
2757                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2758                         break;
2759                 case ixgbe_mac_X550:
2760                 case ixgbe_mac_X550EM_x:
2761                 case ixgbe_mac_X550EM_a:
2762                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2763                         break;
2764                 default:
2765                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2766                 }
2767         } else {
2768                 if (*link_speeds & ETH_LINK_SPEED_10G)
2769                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2770                 if (*link_speeds & ETH_LINK_SPEED_5G)
2771                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2772                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2773                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2774                 if (*link_speeds & ETH_LINK_SPEED_1G)
2775                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2776                 if (*link_speeds & ETH_LINK_SPEED_100M)
2777                         speed |= IXGBE_LINK_SPEED_100_FULL;
2778                 if (*link_speeds & ETH_LINK_SPEED_10M)
2779                         speed |= IXGBE_LINK_SPEED_10_FULL;
2780         }
2781
2782         err = ixgbe_setup_link(hw, speed, link_up);
2783         if (err)
2784                 goto error;
2785
2786 skip_link_setup:
2787
2788         if (rte_intr_allow_others(intr_handle)) {
2789                 /* check if lsc interrupt is enabled */
2790                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2791                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2792                 else
2793                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2794                 ixgbe_dev_macsec_interrupt_setup(dev);
2795         } else {
2796                 rte_intr_callback_unregister(intr_handle,
2797                                              ixgbe_dev_interrupt_handler, dev);
2798                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2799                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2800                                      " no intr multiplex");
2801         }
2802
2803         /* check if rxq interrupt is enabled */
2804         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2805             rte_intr_dp_is_en(intr_handle))
2806                 ixgbe_dev_rxq_interrupt_setup(dev);
2807
2808         /* enable uio/vfio intr/eventfd mapping */
2809         rte_intr_enable(intr_handle);
2810
2811         /* resume enabled intr since hw reset */
2812         ixgbe_enable_intr(dev);
2813         ixgbe_l2_tunnel_conf(dev);
2814         ixgbe_filter_restore(dev);
2815
2816         if (tm_conf->root && !tm_conf->committed)
2817                 PMD_DRV_LOG(WARNING,
2818                             "please call hierarchy_commit() "
2819                             "before starting the port");
2820
2821         /* wait for the controller to acquire link */
2822         err = ixgbe_wait_for_link_up(hw);
2823         if (err)
2824                 goto error;
2825
2826         /*
2827          * Update link status right before return, because it may
2828          * start link configuration process in a separate thread.
2829          */
2830         ixgbe_dev_link_update(dev, 0);
2831
2832         /* setup the macsec setting register */
2833         if (macsec_setting->offload_en)
2834                 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2835
2836         return 0;
2837
2838 error:
2839         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2840         ixgbe_dev_clear_queues(dev);
2841         return -EIO;
2842 }
2843
2844 /*
2845  * Stop device: disable rx and tx functions to allow for reconfiguring.
2846  */
2847 static int
2848 ixgbe_dev_stop(struct rte_eth_dev *dev)
2849 {
2850         struct rte_eth_link link;
2851         struct ixgbe_adapter *adapter = dev->data->dev_private;
2852         struct ixgbe_hw *hw =
2853                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2854         struct ixgbe_vf_info *vfinfo =
2855                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2856         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2857         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2858         int vf;
2859         struct ixgbe_tm_conf *tm_conf =
2860                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2861
2862         if (hw->adapter_stopped)
2863                 return 0;
2864
2865         PMD_INIT_FUNC_TRACE();
2866
2867         ixgbe_dev_wait_setup_link_complete(dev, 0);
2868
2869         /* disable interrupts */
2870         ixgbe_disable_intr(hw);
2871
2872         /* reset the NIC */
2873         ixgbe_pf_reset_hw(hw);
2874         hw->adapter_stopped = 0;
2875
2876         /* stop adapter */
2877         ixgbe_stop_adapter(hw);
2878
2879         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2880                 vfinfo[vf].clear_to_send = false;
2881
2882         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2883                 /* Turn off the copper */
2884                 ixgbe_set_phy_power(hw, false);
2885         } else {
2886                 /* Turn off the laser */
2887                 ixgbe_disable_tx_laser(hw);
2888         }
2889
2890         ixgbe_dev_clear_queues(dev);
2891
2892         /* Clear stored conf */
2893         dev->data->scattered_rx = 0;
2894         dev->data->lro = 0;
2895
2896         /* Clear recorded link status */
2897         memset(&link, 0, sizeof(link));
2898         rte_eth_linkstatus_set(dev, &link);
2899
2900         if (!rte_intr_allow_others(intr_handle))
2901                 /* resume to the default handler */
2902                 rte_intr_callback_register(intr_handle,
2903                                            ixgbe_dev_interrupt_handler,
2904                                            (void *)dev);
2905
2906         /* Clean datapath event and queue/vec mapping */
2907         rte_intr_efd_disable(intr_handle);
2908         if (intr_handle->intr_vec != NULL) {
2909                 rte_free(intr_handle->intr_vec);
2910                 intr_handle->intr_vec = NULL;
2911         }
2912
2913         /* reset hierarchy commit */
2914         tm_conf->committed = false;
2915
2916         adapter->rss_reta_updated = 0;
2917
2918         hw->adapter_stopped = true;
2919         dev->data->dev_started = 0;
2920
2921         return 0;
2922 }
2923
2924 /*
2925  * Set device link up: enable tx.
2926  */
2927 static int
2928 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2929 {
2930         struct ixgbe_hw *hw =
2931                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2932         if (hw->mac.type == ixgbe_mac_82599EB) {
2933 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2934                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2935                         /* Not suported in bypass mode */
2936                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2937                                      "by device id 0x%x", hw->device_id);
2938                         return -ENOTSUP;
2939                 }
2940 #endif
2941         }
2942
2943         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2944                 /* Turn on the copper */
2945                 ixgbe_set_phy_power(hw, true);
2946         } else {
2947                 /* Turn on the laser */
2948                 ixgbe_enable_tx_laser(hw);
2949                 ixgbe_dev_link_update(dev, 0);
2950         }
2951
2952         return 0;
2953 }
2954
2955 /*
2956  * Set device link down: disable tx.
2957  */
2958 static int
2959 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2960 {
2961         struct ixgbe_hw *hw =
2962                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2963         if (hw->mac.type == ixgbe_mac_82599EB) {
2964 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2965                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2966                         /* Not suported in bypass mode */
2967                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2968                                      "by device id 0x%x", hw->device_id);
2969                         return -ENOTSUP;
2970                 }
2971 #endif
2972         }
2973
2974         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2975                 /* Turn off the copper */
2976                 ixgbe_set_phy_power(hw, false);
2977         } else {
2978                 /* Turn off the laser */
2979                 ixgbe_disable_tx_laser(hw);
2980                 ixgbe_dev_link_update(dev, 0);
2981         }
2982
2983         return 0;
2984 }
2985
2986 /*
2987  * Reset and stop device.
2988  */
2989 static int
2990 ixgbe_dev_close(struct rte_eth_dev *dev)
2991 {
2992         struct ixgbe_hw *hw =
2993                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2994         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2995         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2996         int retries = 0;
2997         int ret;
2998
2999         PMD_INIT_FUNC_TRACE();
3000         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3001                 return 0;
3002
3003         ixgbe_pf_reset_hw(hw);
3004
3005         ret = ixgbe_dev_stop(dev);
3006
3007         ixgbe_dev_free_queues(dev);
3008
3009         ixgbe_disable_pcie_master(hw);
3010
3011         /* reprogram the RAR[0] in case user changed it. */
3012         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3013
3014         /* Unlock any pending hardware semaphore */
3015         ixgbe_swfw_lock_reset(hw);
3016
3017         /* disable uio intr before callback unregister */
3018         rte_intr_disable(intr_handle);
3019
3020         do {
3021                 ret = rte_intr_callback_unregister(intr_handle,
3022                                 ixgbe_dev_interrupt_handler, dev);
3023                 if (ret >= 0 || ret == -ENOENT) {
3024                         break;
3025                 } else if (ret != -EAGAIN) {
3026                         PMD_INIT_LOG(ERR,
3027                                 "intr callback unregister failed: %d",
3028                                 ret);
3029                 }
3030                 rte_delay_ms(100);
3031         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3032
3033         /* cancel the delay handler before remove dev */
3034         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3035
3036         /* uninitialize PF if max_vfs not zero */
3037         ixgbe_pf_host_uninit(dev);
3038
3039         /* remove all the fdir filters & hash */
3040         ixgbe_fdir_filter_uninit(dev);
3041
3042         /* remove all the L2 tunnel filters & hash */
3043         ixgbe_l2_tn_filter_uninit(dev);
3044
3045         /* Remove all ntuple filters of the device */
3046         ixgbe_ntuple_filter_uninit(dev);
3047
3048         /* clear all the filters list */
3049         ixgbe_filterlist_flush();
3050
3051         /* Remove all Traffic Manager configuration */
3052         ixgbe_tm_conf_uninit(dev);
3053
3054 #ifdef RTE_LIB_SECURITY
3055         rte_free(dev->security_ctx);
3056 #endif
3057
3058         return ret;
3059 }
3060
3061 /*
3062  * Reset PF device.
3063  */
3064 static int
3065 ixgbe_dev_reset(struct rte_eth_dev *dev)
3066 {
3067         int ret;
3068
3069         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3070          * its VF to make them align with it. The detailed notification
3071          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3072          * To avoid unexpected behavior in VF, currently reset of PF with
3073          * SR-IOV activation is not supported. It might be supported later.
3074          */
3075         if (dev->data->sriov.active)
3076                 return -ENOTSUP;
3077
3078         ret = eth_ixgbe_dev_uninit(dev);
3079         if (ret)
3080                 return ret;
3081
3082         ret = eth_ixgbe_dev_init(dev, NULL);
3083
3084         return ret;
3085 }
3086
3087 static void
3088 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3089                            struct ixgbe_hw_stats *hw_stats,
3090                            struct ixgbe_macsec_stats *macsec_stats,
3091                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3092                            uint64_t *total_qprc, uint64_t *total_qprdc)
3093 {
3094         uint32_t bprc, lxon, lxoff, total;
3095         uint32_t delta_gprc = 0;
3096         unsigned i;
3097         /* Workaround for RX byte count not including CRC bytes when CRC
3098          * strip is enabled. CRC bytes are removed from counters when crc_strip
3099          * is disabled.
3100          */
3101         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3102                         IXGBE_HLREG0_RXCRCSTRP);
3103
3104         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3105         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3106         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3107         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3108
3109         for (i = 0; i < 8; i++) {
3110                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3111
3112                 /* global total per queue */
3113                 hw_stats->mpc[i] += mp;
3114                 /* Running comprehensive total for stats display */
3115                 *total_missed_rx += hw_stats->mpc[i];
3116                 if (hw->mac.type == ixgbe_mac_82598EB) {
3117                         hw_stats->rnbc[i] +=
3118                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3119                         hw_stats->pxonrxc[i] +=
3120                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3121                         hw_stats->pxoffrxc[i] +=
3122                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3123                 } else {
3124                         hw_stats->pxonrxc[i] +=
3125                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3126                         hw_stats->pxoffrxc[i] +=
3127                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3128                         hw_stats->pxon2offc[i] +=
3129                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3130                 }
3131                 hw_stats->pxontxc[i] +=
3132                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3133                 hw_stats->pxofftxc[i] +=
3134                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3135         }
3136         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3137                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3138                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3139                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3140
3141                 delta_gprc += delta_qprc;
3142
3143                 hw_stats->qprc[i] += delta_qprc;
3144                 hw_stats->qptc[i] += delta_qptc;
3145
3146                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3147                 hw_stats->qbrc[i] +=
3148                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3149                 if (crc_strip == 0)
3150                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3151
3152                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3153                 hw_stats->qbtc[i] +=
3154                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3155
3156                 hw_stats->qprdc[i] += delta_qprdc;
3157                 *total_qprdc += hw_stats->qprdc[i];
3158
3159                 *total_qprc += hw_stats->qprc[i];
3160                 *total_qbrc += hw_stats->qbrc[i];
3161         }
3162         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3163         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3164         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3165
3166         /*
3167          * An errata states that gprc actually counts good + missed packets:
3168          * Workaround to set gprc to summated queue packet receives
3169          */
3170         hw_stats->gprc = *total_qprc;
3171
3172         if (hw->mac.type != ixgbe_mac_82598EB) {
3173                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3174                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3175                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3176                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3177                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3178                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3179                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3180                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3181         } else {
3182                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3183                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3184                 /* 82598 only has a counter in the high register */
3185                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3186                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3187                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3188         }
3189         uint64_t old_tpr = hw_stats->tpr;
3190
3191         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3192         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3193
3194         if (crc_strip == 0)
3195                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3196
3197         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3198         hw_stats->gptc += delta_gptc;
3199         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3200         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3201
3202         /*
3203          * Workaround: mprc hardware is incorrectly counting
3204          * broadcasts, so for now we subtract those.
3205          */
3206         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3207         hw_stats->bprc += bprc;
3208         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3209         if (hw->mac.type == ixgbe_mac_82598EB)
3210                 hw_stats->mprc -= bprc;
3211
3212         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3213         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3214         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3215         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3216         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3217         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3218
3219         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3220         hw_stats->lxontxc += lxon;
3221         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3222         hw_stats->lxofftxc += lxoff;
3223         total = lxon + lxoff;
3224
3225         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3226         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3227         hw_stats->gptc -= total;
3228         hw_stats->mptc -= total;
3229         hw_stats->ptc64 -= total;
3230         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3231
3232         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3233         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3234         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3235         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3236         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3237         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3238         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3239         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3240         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3241         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3242         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3243         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3244         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3245         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3246         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3247         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3248         /* Only read FCOE on 82599 */
3249         if (hw->mac.type != ixgbe_mac_82598EB) {
3250                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3251                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3252                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3253                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3254                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3255         }
3256
3257         /* Flow Director Stats registers */
3258         if (hw->mac.type != ixgbe_mac_82598EB) {
3259                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3260                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3261                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3262                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3263                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3264                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3265                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3266                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3267                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3268                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3269         }
3270         /* MACsec Stats registers */
3271         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3272         macsec_stats->out_pkts_encrypted +=
3273                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3274         macsec_stats->out_pkts_protected +=
3275                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3276         macsec_stats->out_octets_encrypted +=
3277                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3278         macsec_stats->out_octets_protected +=
3279                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3280         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3281         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3282         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3283         macsec_stats->in_pkts_unknownsci +=
3284                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3285         macsec_stats->in_octets_decrypted +=
3286                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3287         macsec_stats->in_octets_validated +=
3288                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3289         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3290         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3291         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3292         for (i = 0; i < 2; i++) {
3293                 macsec_stats->in_pkts_ok +=
3294                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3295                 macsec_stats->in_pkts_invalid +=
3296                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3297                 macsec_stats->in_pkts_notvalid +=
3298                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3299         }
3300         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3301         macsec_stats->in_pkts_notusingsa +=
3302                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3303 }
3304
3305 /*
3306  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3307  */
3308 static int
3309 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3310 {
3311         struct ixgbe_hw *hw =
3312                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3313         struct ixgbe_hw_stats *hw_stats =
3314                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3315         struct ixgbe_macsec_stats *macsec_stats =
3316                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3317                                 dev->data->dev_private);
3318         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3319         unsigned i;
3320
3321         total_missed_rx = 0;
3322         total_qbrc = 0;
3323         total_qprc = 0;
3324         total_qprdc = 0;
3325
3326         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3327                         &total_qbrc, &total_qprc, &total_qprdc);
3328
3329         if (stats == NULL)
3330                 return -EINVAL;
3331
3332         /* Fill out the rte_eth_stats statistics structure */
3333         stats->ipackets = total_qprc;
3334         stats->ibytes = total_qbrc;
3335         stats->opackets = hw_stats->gptc;
3336         stats->obytes = hw_stats->gotc;
3337
3338         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3339                 stats->q_ipackets[i] = hw_stats->qprc[i];
3340                 stats->q_opackets[i] = hw_stats->qptc[i];
3341                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3342                 stats->q_obytes[i] = hw_stats->qbtc[i];
3343                 stats->q_errors[i] = hw_stats->qprdc[i];
3344         }
3345
3346         /* Rx Errors */
3347         stats->imissed  = total_missed_rx;
3348         stats->ierrors  = hw_stats->crcerrs +
3349                           hw_stats->mspdc +
3350                           hw_stats->rlec +
3351                           hw_stats->ruc +
3352                           hw_stats->roc +
3353                           hw_stats->illerrc +
3354                           hw_stats->errbc +
3355                           hw_stats->rfc +
3356                           hw_stats->fccrc +
3357                           hw_stats->fclast;
3358
3359         /* Tx Errors */
3360         stats->oerrors  = 0;
3361         return 0;
3362 }
3363
3364 static int
3365 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3366 {
3367         struct ixgbe_hw_stats *stats =
3368                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3369
3370         /* HW registers are cleared on read */
3371         ixgbe_dev_stats_get(dev, NULL);
3372
3373         /* Reset software totals */
3374         memset(stats, 0, sizeof(*stats));
3375
3376         return 0;
3377 }
3378
3379 /* This function calculates the number of xstats based on the current config */
3380 static unsigned
3381 ixgbe_xstats_calc_num(void) {
3382         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3383                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3384                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3385 }
3386
3387 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3388         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3389 {
3390         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3391         unsigned stat, i, count;
3392
3393         if (xstats_names != NULL) {
3394                 count = 0;
3395
3396                 /* Note: limit >= cnt_stats checked upstream
3397                  * in rte_eth_xstats_names()
3398                  */
3399
3400                 /* Extended stats from ixgbe_hw_stats */
3401                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3402                         strlcpy(xstats_names[count].name,
3403                                 rte_ixgbe_stats_strings[i].name,
3404                                 sizeof(xstats_names[count].name));
3405                         count++;
3406                 }
3407
3408                 /* MACsec Stats */
3409                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3410                         strlcpy(xstats_names[count].name,
3411                                 rte_ixgbe_macsec_strings[i].name,
3412                                 sizeof(xstats_names[count].name));
3413                         count++;
3414                 }
3415
3416                 /* RX Priority Stats */
3417                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3418                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3419                                 snprintf(xstats_names[count].name,
3420                                         sizeof(xstats_names[count].name),
3421                                         "rx_priority%u_%s", i,
3422                                         rte_ixgbe_rxq_strings[stat].name);
3423                                 count++;
3424                         }
3425                 }
3426
3427                 /* TX Priority Stats */
3428                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3429                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3430                                 snprintf(xstats_names[count].name,
3431                                         sizeof(xstats_names[count].name),
3432                                         "tx_priority%u_%s", i,
3433                                         rte_ixgbe_txq_strings[stat].name);
3434                                 count++;
3435                         }
3436                 }
3437         }
3438         return cnt_stats;
3439 }
3440
3441 static int ixgbe_dev_xstats_get_names_by_id(
3442         struct rte_eth_dev *dev,
3443         struct rte_eth_xstat_name *xstats_names,
3444         const uint64_t *ids,
3445         unsigned int limit)
3446 {
3447         if (!ids) {
3448                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3449                 unsigned int stat, i, count;
3450
3451                 if (xstats_names != NULL) {
3452                         count = 0;
3453
3454                         /* Note: limit >= cnt_stats checked upstream
3455                          * in rte_eth_xstats_names()
3456                          */
3457
3458                         /* Extended stats from ixgbe_hw_stats */
3459                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3460                                 strlcpy(xstats_names[count].name,
3461                                         rte_ixgbe_stats_strings[i].name,
3462                                         sizeof(xstats_names[count].name));
3463                                 count++;
3464                         }
3465
3466                         /* MACsec Stats */
3467                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3468                                 strlcpy(xstats_names[count].name,
3469                                         rte_ixgbe_macsec_strings[i].name,
3470                                         sizeof(xstats_names[count].name));
3471                                 count++;
3472                         }
3473
3474                         /* RX Priority Stats */
3475                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3476                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3477                                         snprintf(xstats_names[count].name,
3478                                             sizeof(xstats_names[count].name),
3479                                             "rx_priority%u_%s", i,
3480                                             rte_ixgbe_rxq_strings[stat].name);
3481                                         count++;
3482                                 }
3483                         }
3484
3485                         /* TX Priority Stats */
3486                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3487                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3488                                         snprintf(xstats_names[count].name,
3489                                             sizeof(xstats_names[count].name),
3490                                             "tx_priority%u_%s", i,
3491                                             rte_ixgbe_txq_strings[stat].name);
3492                                         count++;
3493                                 }
3494                         }
3495                 }
3496                 return cnt_stats;
3497         }
3498
3499         uint16_t i;
3500         uint16_t size = ixgbe_xstats_calc_num();
3501         struct rte_eth_xstat_name xstats_names_copy[size];
3502
3503         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3504                         size);
3505
3506         for (i = 0; i < limit; i++) {
3507                 if (ids[i] >= size) {
3508                         PMD_INIT_LOG(ERR, "id value isn't valid");
3509                         return -1;
3510                 }
3511                 strcpy(xstats_names[i].name,
3512                                 xstats_names_copy[ids[i]].name);
3513         }
3514         return limit;
3515 }
3516
3517 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3518         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3519 {
3520         unsigned i;
3521
3522         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3523                 return -ENOMEM;
3524
3525         if (xstats_names != NULL)
3526                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3527                         strlcpy(xstats_names[i].name,
3528                                 rte_ixgbevf_stats_strings[i].name,
3529                                 sizeof(xstats_names[i].name));
3530         return IXGBEVF_NB_XSTATS;
3531 }
3532
3533 static int
3534 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3535                                          unsigned n)
3536 {
3537         struct ixgbe_hw *hw =
3538                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3539         struct ixgbe_hw_stats *hw_stats =
3540                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3541         struct ixgbe_macsec_stats *macsec_stats =
3542                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3543                                 dev->data->dev_private);
3544         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3545         unsigned i, stat, count = 0;
3546
3547         count = ixgbe_xstats_calc_num();
3548
3549         if (n < count)
3550                 return count;
3551
3552         total_missed_rx = 0;
3553         total_qbrc = 0;
3554         total_qprc = 0;
3555         total_qprdc = 0;
3556
3557         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3558                         &total_qbrc, &total_qprc, &total_qprdc);
3559
3560         /* If this is a reset xstats is NULL, and we have cleared the
3561          * registers by reading them.
3562          */
3563         if (!xstats)
3564                 return 0;
3565
3566         /* Extended stats from ixgbe_hw_stats */
3567         count = 0;
3568         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3569                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3570                                 rte_ixgbe_stats_strings[i].offset);
3571                 xstats[count].id = count;
3572                 count++;
3573         }
3574
3575         /* MACsec Stats */
3576         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3577                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3578                                 rte_ixgbe_macsec_strings[i].offset);
3579                 xstats[count].id = count;
3580                 count++;
3581         }
3582
3583         /* RX Priority Stats */
3584         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3585                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3586                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3587                                         rte_ixgbe_rxq_strings[stat].offset +
3588                                         (sizeof(uint64_t) * i));
3589                         xstats[count].id = count;
3590                         count++;
3591                 }
3592         }
3593
3594         /* TX Priority Stats */
3595         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3596                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3597                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3598                                         rte_ixgbe_txq_strings[stat].offset +
3599                                         (sizeof(uint64_t) * i));
3600                         xstats[count].id = count;
3601                         count++;
3602                 }
3603         }
3604         return count;
3605 }
3606
3607 static int
3608 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3609                 uint64_t *values, unsigned int n)
3610 {
3611         if (!ids) {
3612                 struct ixgbe_hw *hw =
3613                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3614                 struct ixgbe_hw_stats *hw_stats =
3615                                 IXGBE_DEV_PRIVATE_TO_STATS(
3616                                                 dev->data->dev_private);
3617                 struct ixgbe_macsec_stats *macsec_stats =
3618                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3619                                         dev->data->dev_private);
3620                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3621                 unsigned int i, stat, count = 0;
3622
3623                 count = ixgbe_xstats_calc_num();
3624
3625                 if (!ids && n < count)
3626                         return count;
3627
3628                 total_missed_rx = 0;
3629                 total_qbrc = 0;
3630                 total_qprc = 0;
3631                 total_qprdc = 0;
3632
3633                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3634                                 &total_missed_rx, &total_qbrc, &total_qprc,
3635                                 &total_qprdc);
3636
3637                 /* If this is a reset xstats is NULL, and we have cleared the
3638                  * registers by reading them.
3639                  */
3640                 if (!ids && !values)
3641                         return 0;
3642
3643                 /* Extended stats from ixgbe_hw_stats */
3644                 count = 0;
3645                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3646                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3647                                         rte_ixgbe_stats_strings[i].offset);
3648                         count++;
3649                 }
3650
3651                 /* MACsec Stats */
3652                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3653                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3654                                         rte_ixgbe_macsec_strings[i].offset);
3655                         count++;
3656                 }
3657
3658                 /* RX Priority Stats */
3659                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3660                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3661                                 values[count] =
3662                                         *(uint64_t *)(((char *)hw_stats) +
3663                                         rte_ixgbe_rxq_strings[stat].offset +
3664                                         (sizeof(uint64_t) * i));
3665                                 count++;
3666                         }
3667                 }
3668
3669                 /* TX Priority Stats */
3670                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3671                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3672                                 values[count] =
3673                                         *(uint64_t *)(((char *)hw_stats) +
3674                                         rte_ixgbe_txq_strings[stat].offset +
3675                                         (sizeof(uint64_t) * i));
3676                                 count++;
3677                         }
3678                 }
3679                 return count;
3680         }
3681
3682         uint16_t i;
3683         uint16_t size = ixgbe_xstats_calc_num();
3684         uint64_t values_copy[size];
3685
3686         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3687
3688         for (i = 0; i < n; i++) {
3689                 if (ids[i] >= size) {
3690                         PMD_INIT_LOG(ERR, "id value isn't valid");
3691                         return -1;
3692                 }
3693                 values[i] = values_copy[ids[i]];
3694         }
3695         return n;
3696 }
3697
3698 static int
3699 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3700 {
3701         struct ixgbe_hw_stats *stats =
3702                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3703         struct ixgbe_macsec_stats *macsec_stats =
3704                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3705                                 dev->data->dev_private);
3706
3707         unsigned count = ixgbe_xstats_calc_num();
3708
3709         /* HW registers are cleared on read */
3710         ixgbe_dev_xstats_get(dev, NULL, count);
3711
3712         /* Reset software totals */
3713         memset(stats, 0, sizeof(*stats));
3714         memset(macsec_stats, 0, sizeof(*macsec_stats));
3715
3716         return 0;
3717 }
3718
3719 static void
3720 ixgbevf_update_stats(struct rte_eth_dev *dev)
3721 {
3722         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3723         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3724                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3725
3726         /* Good Rx packet, include VF loopback */
3727         UPDATE_VF_STAT(IXGBE_VFGPRC,
3728             hw_stats->last_vfgprc, hw_stats->vfgprc);
3729
3730         /* Good Rx octets, include VF loopback */
3731         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3732             hw_stats->last_vfgorc, hw_stats->vfgorc);
3733
3734         /* Good Tx packet, include VF loopback */
3735         UPDATE_VF_STAT(IXGBE_VFGPTC,
3736             hw_stats->last_vfgptc, hw_stats->vfgptc);
3737
3738         /* Good Tx octets, include VF loopback */
3739         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3740             hw_stats->last_vfgotc, hw_stats->vfgotc);
3741
3742         /* Rx Multicst Packet */
3743         UPDATE_VF_STAT(IXGBE_VFMPRC,
3744             hw_stats->last_vfmprc, hw_stats->vfmprc);
3745 }
3746
3747 static int
3748 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3749                        unsigned n)
3750 {
3751         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3752                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3753         unsigned i;
3754
3755         if (n < IXGBEVF_NB_XSTATS)
3756                 return IXGBEVF_NB_XSTATS;
3757
3758         ixgbevf_update_stats(dev);
3759
3760         if (!xstats)
3761                 return 0;
3762
3763         /* Extended stats */
3764         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3765                 xstats[i].id = i;
3766                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3767                         rte_ixgbevf_stats_strings[i].offset);
3768         }
3769
3770         return IXGBEVF_NB_XSTATS;
3771 }
3772
3773 static int
3774 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3775 {
3776         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3777                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3778
3779         ixgbevf_update_stats(dev);
3780
3781         if (stats == NULL)
3782                 return -EINVAL;
3783
3784         stats->ipackets = hw_stats->vfgprc;
3785         stats->ibytes = hw_stats->vfgorc;
3786         stats->opackets = hw_stats->vfgptc;
3787         stats->obytes = hw_stats->vfgotc;
3788         return 0;
3789 }
3790
3791 static int
3792 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3793 {
3794         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3795                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3796
3797         /* Sync HW register to the last stats */
3798         ixgbevf_dev_stats_get(dev, NULL);
3799
3800         /* reset HW current stats*/
3801         hw_stats->vfgprc = 0;
3802         hw_stats->vfgorc = 0;
3803         hw_stats->vfgptc = 0;
3804         hw_stats->vfgotc = 0;
3805
3806         return 0;
3807 }
3808
3809 static int
3810 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3811 {
3812         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3813         u16 eeprom_verh, eeprom_verl;
3814         u32 etrack_id;
3815         int ret;
3816
3817         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3818         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3819
3820         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3821         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3822
3823         ret += 1; /* add the size of '\0' */
3824         if (fw_size < (u32)ret)
3825                 return ret;
3826         else
3827                 return 0;
3828 }
3829
3830 static int
3831 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3832 {
3833         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3834         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3835         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3836
3837         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3838         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3839         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3840                 /*
3841                  * When DCB/VT is off, maximum number of queues changes,
3842                  * except for 82598EB, which remains constant.
3843                  */
3844                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3845                                 hw->mac.type != ixgbe_mac_82598EB)
3846                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3847         }
3848         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3849         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3850         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3851         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3852         dev_info->max_vfs = pci_dev->max_vfs;
3853         if (hw->mac.type == ixgbe_mac_82598EB)
3854                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3855         else
3856                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3857         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3858         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3859         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3860         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3861         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3862                                      dev_info->rx_queue_offload_capa);
3863         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3864         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3865
3866         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3867                 .rx_thresh = {
3868                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3869                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3870                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3871                 },
3872                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3873                 .rx_drop_en = 0,
3874                 .offloads = 0,
3875         };
3876
3877         dev_info->default_txconf = (struct rte_eth_txconf) {
3878                 .tx_thresh = {
3879                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3880                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3881                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3882                 },
3883                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3884                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3885                 .offloads = 0,
3886         };
3887
3888         dev_info->rx_desc_lim = rx_desc_lim;
3889         dev_info->tx_desc_lim = tx_desc_lim;
3890
3891         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3892         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3893         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3894
3895         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3896         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3897                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3898                 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3899                         ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3900
3901         if (hw->mac.type == ixgbe_mac_X540 ||
3902             hw->mac.type == ixgbe_mac_X540_vf ||
3903             hw->mac.type == ixgbe_mac_X550 ||
3904             hw->mac.type == ixgbe_mac_X550_vf) {
3905                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3906         }
3907         if (hw->mac.type == ixgbe_mac_X550) {
3908                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3909                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3910         }
3911
3912         /* Driver-preferred Rx/Tx parameters */
3913         dev_info->default_rxportconf.burst_size = 32;
3914         dev_info->default_txportconf.burst_size = 32;
3915         dev_info->default_rxportconf.nb_queues = 1;
3916         dev_info->default_txportconf.nb_queues = 1;
3917         dev_info->default_rxportconf.ring_size = 256;
3918         dev_info->default_txportconf.ring_size = 256;
3919
3920         return 0;
3921 }
3922
3923 static const uint32_t *
3924 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3925 {
3926         static const uint32_t ptypes[] = {
3927                 /* For non-vec functions,
3928                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3929                  * for vec functions,
3930                  * refers to _recv_raw_pkts_vec().
3931                  */
3932                 RTE_PTYPE_L2_ETHER,
3933                 RTE_PTYPE_L3_IPV4,
3934                 RTE_PTYPE_L3_IPV4_EXT,
3935                 RTE_PTYPE_L3_IPV6,
3936                 RTE_PTYPE_L3_IPV6_EXT,
3937                 RTE_PTYPE_L4_SCTP,
3938                 RTE_PTYPE_L4_TCP,
3939                 RTE_PTYPE_L4_UDP,
3940                 RTE_PTYPE_TUNNEL_IP,
3941                 RTE_PTYPE_INNER_L3_IPV6,
3942                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3943                 RTE_PTYPE_INNER_L4_TCP,
3944                 RTE_PTYPE_INNER_L4_UDP,
3945                 RTE_PTYPE_UNKNOWN
3946         };
3947
3948         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3949             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3950             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3951             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3952                 return ptypes;
3953
3954 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON)
3955         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3956             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3957                 return ptypes;
3958 #endif
3959         return NULL;
3960 }
3961
3962 static int
3963 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3964                      struct rte_eth_dev_info *dev_info)
3965 {
3966         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3967         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3968
3969         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3970         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3971         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3972         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3973         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3974         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3975         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3976         dev_info->max_vfs = pci_dev->max_vfs;
3977         if (hw->mac.type == ixgbe_mac_82598EB)
3978                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3979         else
3980                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3981         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3982         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3983                                      dev_info->rx_queue_offload_capa);
3984         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3985         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3986         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3987         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3988         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3989
3990         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3991                 .rx_thresh = {
3992                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3993                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3994                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3995                 },
3996                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3997                 .rx_drop_en = 0,
3998                 .offloads = 0,
3999         };
4000
4001         dev_info->default_txconf = (struct rte_eth_txconf) {
4002                 .tx_thresh = {
4003                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
4004                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
4005                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
4006                 },
4007                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
4008                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
4009                 .offloads = 0,
4010         };
4011
4012         dev_info->rx_desc_lim = rx_desc_lim;
4013         dev_info->tx_desc_lim = tx_desc_lim;
4014
4015         return 0;
4016 }
4017
4018 static int
4019 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4020                    bool *link_up, int wait_to_complete)
4021 {
4022         struct ixgbe_adapter *adapter = container_of(hw,
4023                                                      struct ixgbe_adapter, hw);
4024         struct ixgbe_mbx_info *mbx = &hw->mbx;
4025         struct ixgbe_mac_info *mac = &hw->mac;
4026         uint32_t links_reg, in_msg;
4027         int ret_val = 0;
4028
4029         /* If we were hit with a reset drop the link */
4030         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4031                 mac->get_link_status = true;
4032
4033         if (!mac->get_link_status)
4034                 goto out;
4035
4036         /* if link status is down no point in checking to see if pf is up */
4037         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4038         if (!(links_reg & IXGBE_LINKS_UP))
4039                 goto out;
4040
4041         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4042          * before the link status is correct
4043          */
4044         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4045                 int i;
4046
4047                 for (i = 0; i < 5; i++) {
4048                         rte_delay_us(100);
4049                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4050
4051                         if (!(links_reg & IXGBE_LINKS_UP))
4052                                 goto out;
4053                 }
4054         }
4055
4056         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4057         case IXGBE_LINKS_SPEED_10G_82599:
4058                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4059                 if (hw->mac.type >= ixgbe_mac_X550) {
4060                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4061                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4062                 }
4063                 break;
4064         case IXGBE_LINKS_SPEED_1G_82599:
4065                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4066                 break;
4067         case IXGBE_LINKS_SPEED_100_82599:
4068                 *speed = IXGBE_LINK_SPEED_100_FULL;
4069                 if (hw->mac.type == ixgbe_mac_X550) {
4070                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4071                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4072                 }
4073                 break;
4074         case IXGBE_LINKS_SPEED_10_X550EM_A:
4075                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4076                 /* Since Reserved in older MAC's */
4077                 if (hw->mac.type >= ixgbe_mac_X550)
4078                         *speed = IXGBE_LINK_SPEED_10_FULL;
4079                 break;
4080         default:
4081                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4082         }
4083
4084         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4085                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4086                         mac->get_link_status = true;
4087                 else
4088                         mac->get_link_status = false;
4089
4090                 goto out;
4091         }
4092
4093         /* if the read failed it could just be a mailbox collision, best wait
4094          * until we are called again and don't report an error
4095          */
4096         if (mbx->ops.read(hw, &in_msg, 1, 0))
4097                 goto out;
4098
4099         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4100                 /* msg is not CTS and is NACK we must have lost CTS status */
4101                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4102                         mac->get_link_status = false;
4103                 goto out;
4104         }
4105
4106         /* the pf is talking, if we timed out in the past we reinit */
4107         if (!mbx->timeout) {
4108                 ret_val = -1;
4109                 goto out;
4110         }
4111
4112         /* if we passed all the tests above then the link is up and we no
4113          * longer need to check for link
4114          */
4115         mac->get_link_status = false;
4116
4117 out:
4118         *link_up = !mac->get_link_status;
4119         return ret_val;
4120 }
4121
4122 /*
4123  * If @timeout_ms was 0, it means that it will not return until link complete.
4124  * It returns 1 on complete, return 0 on timeout.
4125  */
4126 static int
4127 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4128 {
4129 #define WARNING_TIMEOUT    9000 /* 9s  in total */
4130         struct ixgbe_adapter *ad = dev->data->dev_private;
4131         uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4132
4133         while (rte_atomic32_read(&ad->link_thread_running)) {
4134                 msec_delay(1);
4135                 timeout--;
4136
4137                 if (timeout_ms) {
4138                         if (!timeout)
4139                                 return 0;
4140                 } else if (!timeout) {
4141                         /* It will not return until link complete */
4142                         timeout = WARNING_TIMEOUT;
4143                         PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4144                 }
4145         }
4146
4147         return 1;
4148 }
4149
4150 static void *
4151 ixgbe_dev_setup_link_thread_handler(void *param)
4152 {
4153         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4154         struct ixgbe_adapter *ad = dev->data->dev_private;
4155         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4156         struct ixgbe_interrupt *intr =
4157                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4158         u32 speed;
4159         bool autoneg = false;
4160
4161         pthread_detach(pthread_self());
4162         speed = hw->phy.autoneg_advertised;
4163         if (!speed)
4164                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4165
4166         ixgbe_setup_link(hw, speed, true);
4167
4168         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4169         rte_atomic32_clear(&ad->link_thread_running);
4170         return NULL;
4171 }
4172
4173 /*
4174  * In freebsd environment, nic_uio drivers do not support interrupts,
4175  * rte_intr_callback_register() will fail to register interrupts.
4176  * We can not make link status to change from down to up by interrupt
4177  * callback. So we need to wait for the controller to acquire link
4178  * when ports start.
4179  * It returns 0 on link up.
4180  */
4181 static int
4182 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4183 {
4184 #ifdef RTE_EXEC_ENV_FREEBSD
4185         int err, i;
4186         bool link_up = false;
4187         uint32_t speed = 0;
4188         const int nb_iter = 25;
4189
4190         for (i = 0; i < nb_iter; i++) {
4191                 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4192                 if (err)
4193                         return err;
4194                 if (link_up)
4195                         return 0;
4196                 msec_delay(200);
4197         }
4198
4199         return 0;
4200 #else
4201         RTE_SET_USED(hw);
4202         return 0;
4203 #endif
4204 }
4205
4206 /* return 0 means link status changed, -1 means not changed */
4207 int
4208 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4209                             int wait_to_complete, int vf)
4210 {
4211         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4212         struct ixgbe_adapter *ad = dev->data->dev_private;
4213         struct rte_eth_link link;
4214         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4215         struct ixgbe_interrupt *intr =
4216                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4217         bool link_up;
4218         int diag;
4219         int wait = 1;
4220         u32 esdp_reg;
4221
4222         memset(&link, 0, sizeof(link));
4223         link.link_status = ETH_LINK_DOWN;
4224         link.link_speed = ETH_SPEED_NUM_NONE;
4225         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4226         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4227                         ETH_LINK_SPEED_FIXED);
4228
4229         hw->mac.get_link_status = true;
4230
4231         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4232                 return rte_eth_linkstatus_set(dev, &link);
4233
4234         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4235         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4236                 wait = 0;
4237
4238 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4239 #ifdef RTE_EXEC_ENV_FREEBSD
4240         wait = 1;
4241 #endif
4242
4243         if (vf)
4244                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4245         else
4246                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4247
4248         if (diag != 0) {
4249                 link.link_speed = ETH_SPEED_NUM_100M;
4250                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4251                 return rte_eth_linkstatus_set(dev, &link);
4252         }
4253
4254         if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4255                 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4256                 if ((esdp_reg & IXGBE_ESDP_SDP3))
4257                         link_up = 0;
4258         }
4259
4260         if (link_up == 0) {
4261                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4262                         ixgbe_dev_wait_setup_link_complete(dev, 0);
4263                         if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4264                                 /* To avoid race condition between threads, set
4265                                  * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4266                                  * when there is no link thread running.
4267                                  */
4268                                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4269                                 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4270                                         "ixgbe-link-handler",
4271                                         NULL,
4272                                         ixgbe_dev_setup_link_thread_handler,
4273                                         dev) < 0) {
4274                                         PMD_DRV_LOG(ERR,
4275                                                 "Create link thread failed!");
4276                                         rte_atomic32_clear(&ad->link_thread_running);
4277                                 }
4278                         } else {
4279                                 PMD_DRV_LOG(ERR,
4280                                         "Other link thread is running now!");
4281                         }
4282                 }
4283                 return rte_eth_linkstatus_set(dev, &link);
4284         }
4285
4286         link.link_status = ETH_LINK_UP;
4287         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4288
4289         switch (link_speed) {
4290         default:
4291         case IXGBE_LINK_SPEED_UNKNOWN:
4292                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
4293                 break;
4294
4295         case IXGBE_LINK_SPEED_10_FULL:
4296                 link.link_speed = ETH_SPEED_NUM_10M;
4297                 break;
4298
4299         case IXGBE_LINK_SPEED_100_FULL:
4300                 link.link_speed = ETH_SPEED_NUM_100M;
4301                 break;
4302
4303         case IXGBE_LINK_SPEED_1GB_FULL:
4304                 link.link_speed = ETH_SPEED_NUM_1G;
4305                 break;
4306
4307         case IXGBE_LINK_SPEED_2_5GB_FULL:
4308                 link.link_speed = ETH_SPEED_NUM_2_5G;
4309                 break;
4310
4311         case IXGBE_LINK_SPEED_5GB_FULL:
4312                 link.link_speed = ETH_SPEED_NUM_5G;
4313                 break;
4314
4315         case IXGBE_LINK_SPEED_10GB_FULL:
4316                 link.link_speed = ETH_SPEED_NUM_10G;
4317                 break;
4318         }
4319
4320         return rte_eth_linkstatus_set(dev, &link);
4321 }
4322
4323 static int
4324 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4325 {
4326         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4327 }
4328
4329 static int
4330 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4331 {
4332         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4333 }
4334
4335 static int
4336 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4337 {
4338         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4339         uint32_t fctrl;
4340
4341         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4342         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4343         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4344
4345         return 0;
4346 }
4347
4348 static int
4349 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4350 {
4351         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4352         uint32_t fctrl;
4353
4354         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4355         fctrl &= (~IXGBE_FCTRL_UPE);
4356         if (dev->data->all_multicast == 1)
4357                 fctrl |= IXGBE_FCTRL_MPE;
4358         else
4359                 fctrl &= (~IXGBE_FCTRL_MPE);
4360         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4361
4362         return 0;
4363 }
4364
4365 static int
4366 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4367 {
4368         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4369         uint32_t fctrl;
4370
4371         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4372         fctrl |= IXGBE_FCTRL_MPE;
4373         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4374
4375         return 0;
4376 }
4377
4378 static int
4379 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4380 {
4381         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4382         uint32_t fctrl;
4383
4384         if (dev->data->promiscuous == 1)
4385                 return 0; /* must remain in all_multicast mode */
4386
4387         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4388         fctrl &= (~IXGBE_FCTRL_MPE);
4389         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4390
4391         return 0;
4392 }
4393
4394 /**
4395  * It clears the interrupt causes and enables the interrupt.
4396  * It will be called once only during nic initialized.
4397  *
4398  * @param dev
4399  *  Pointer to struct rte_eth_dev.
4400  * @param on
4401  *  Enable or Disable.
4402  *
4403  * @return
4404  *  - On success, zero.
4405  *  - On failure, a negative value.
4406  */
4407 static int
4408 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4409 {
4410         struct ixgbe_interrupt *intr =
4411                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4412
4413         ixgbe_dev_link_status_print(dev);
4414         if (on)
4415                 intr->mask |= IXGBE_EICR_LSC;
4416         else
4417                 intr->mask &= ~IXGBE_EICR_LSC;
4418
4419         return 0;
4420 }
4421
4422 /**
4423  * It clears the interrupt causes and enables the interrupt.
4424  * It will be called once only during nic initialized.
4425  *
4426  * @param dev
4427  *  Pointer to struct rte_eth_dev.
4428  *
4429  * @return
4430  *  - On success, zero.
4431  *  - On failure, a negative value.
4432  */
4433 static int
4434 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4435 {
4436         struct ixgbe_interrupt *intr =
4437                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4438
4439         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4440
4441         return 0;
4442 }
4443
4444 /**
4445  * It clears the interrupt causes and enables the interrupt.
4446  * It will be called once only during nic initialized.
4447  *
4448  * @param dev
4449  *  Pointer to struct rte_eth_dev.
4450  *
4451  * @return
4452  *  - On success, zero.
4453  *  - On failure, a negative value.
4454  */
4455 static int
4456 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4457 {
4458         struct ixgbe_interrupt *intr =
4459                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4460
4461         intr->mask |= IXGBE_EICR_LINKSEC;
4462
4463         return 0;
4464 }
4465
4466 /*
4467  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4468  *
4469  * @param dev
4470  *  Pointer to struct rte_eth_dev.
4471  *
4472  * @return
4473  *  - On success, zero.
4474  *  - On failure, a negative value.
4475  */
4476 static int
4477 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4478 {
4479         uint32_t eicr;
4480         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4481         struct ixgbe_interrupt *intr =
4482                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4483
4484         /* clear all cause mask */
4485         ixgbe_disable_intr(hw);
4486
4487         /* read-on-clear nic registers here */
4488         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4489         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4490
4491         intr->flags = 0;
4492
4493         /* set flag for async link update */
4494         if (eicr & IXGBE_EICR_LSC)
4495                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4496
4497         if (eicr & IXGBE_EICR_MAILBOX)
4498                 intr->flags |= IXGBE_FLAG_MAILBOX;
4499
4500         if (eicr & IXGBE_EICR_LINKSEC)
4501                 intr->flags |= IXGBE_FLAG_MACSEC;
4502
4503         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4504             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4505             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4506                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4507
4508         return 0;
4509 }
4510
4511 /**
4512  * It gets and then prints the link status.
4513  *
4514  * @param dev
4515  *  Pointer to struct rte_eth_dev.
4516  *
4517  * @return
4518  *  - On success, zero.
4519  *  - On failure, a negative value.
4520  */
4521 static void
4522 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4523 {
4524         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4525         struct rte_eth_link link;
4526
4527         rte_eth_linkstatus_get(dev, &link);
4528
4529         if (link.link_status) {
4530                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4531                                         (int)(dev->data->port_id),
4532                                         (unsigned)link.link_speed,
4533                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4534                                         "full-duplex" : "half-duplex");
4535         } else {
4536                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4537                                 (int)(dev->data->port_id));
4538         }
4539         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4540                                 pci_dev->addr.domain,
4541                                 pci_dev->addr.bus,
4542                                 pci_dev->addr.devid,
4543                                 pci_dev->addr.function);
4544 }
4545
4546 /*
4547  * It executes link_update after knowing an interrupt occurred.
4548  *
4549  * @param dev
4550  *  Pointer to struct rte_eth_dev.
4551  *
4552  * @return
4553  *  - On success, zero.
4554  *  - On failure, a negative value.
4555  */
4556 static int
4557 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4558 {
4559         struct ixgbe_interrupt *intr =
4560                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4561         int64_t timeout;
4562         struct ixgbe_hw *hw =
4563                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4564
4565         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4566
4567         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4568                 ixgbe_pf_mbx_process(dev);
4569                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4570         }
4571
4572         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4573                 ixgbe_handle_lasi(hw);
4574                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4575         }
4576
4577         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4578                 struct rte_eth_link link;
4579
4580                 /* get the link status before link update, for predicting later */
4581                 rte_eth_linkstatus_get(dev, &link);
4582
4583                 ixgbe_dev_link_update(dev, 0);
4584
4585                 /* likely to up */
4586                 if (!link.link_status)
4587                         /* handle it 1 sec later, wait it being stable */
4588                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4589                 /* likely to down */
4590                 else
4591                         /* handle it 4 sec later, wait it being stable */
4592                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4593
4594                 ixgbe_dev_link_status_print(dev);
4595                 if (rte_eal_alarm_set(timeout * 1000,
4596                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4597                         PMD_DRV_LOG(ERR, "Error setting alarm");
4598                 else {
4599                         /* remember original mask */
4600                         intr->mask_original = intr->mask;
4601                         /* only disable lsc interrupt */
4602                         intr->mask &= ~IXGBE_EIMS_LSC;
4603                 }
4604         }
4605
4606         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4607         ixgbe_enable_intr(dev);
4608
4609         return 0;
4610 }
4611
4612 /**
4613  * Interrupt handler which shall be registered for alarm callback for delayed
4614  * handling specific interrupt to wait for the stable nic state. As the
4615  * NIC interrupt state is not stable for ixgbe after link is just down,
4616  * it needs to wait 4 seconds to get the stable status.
4617  *
4618  * @param handle
4619  *  Pointer to interrupt handle.
4620  * @param param
4621  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4622  *
4623  * @return
4624  *  void
4625  */
4626 static void
4627 ixgbe_dev_interrupt_delayed_handler(void *param)
4628 {
4629         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4630         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4631         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4632         struct ixgbe_interrupt *intr =
4633                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4634         struct ixgbe_hw *hw =
4635                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4636         uint32_t eicr;
4637
4638         ixgbe_disable_intr(hw);
4639
4640         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4641         if (eicr & IXGBE_EICR_MAILBOX)
4642                 ixgbe_pf_mbx_process(dev);
4643
4644         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4645                 ixgbe_handle_lasi(hw);
4646                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4647         }
4648
4649         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4650                 ixgbe_dev_link_update(dev, 0);
4651                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4652                 ixgbe_dev_link_status_print(dev);
4653                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4654         }
4655
4656         if (intr->flags & IXGBE_FLAG_MACSEC) {
4657                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL);
4658                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4659         }
4660
4661         /* restore original mask */
4662         intr->mask = intr->mask_original;
4663         intr->mask_original = 0;
4664
4665         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4666         ixgbe_enable_intr(dev);
4667         rte_intr_ack(intr_handle);
4668 }
4669
4670 /**
4671  * Interrupt handler triggered by NIC  for handling
4672  * specific interrupt.
4673  *
4674  * @param handle
4675  *  Pointer to interrupt handle.
4676  * @param param
4677  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4678  *
4679  * @return
4680  *  void
4681  */
4682 static void
4683 ixgbe_dev_interrupt_handler(void *param)
4684 {
4685         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4686
4687         ixgbe_dev_interrupt_get_status(dev);
4688         ixgbe_dev_interrupt_action(dev);
4689 }
4690
4691 static int
4692 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4693 {
4694         struct ixgbe_hw *hw;
4695
4696         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4697         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4698 }
4699
4700 static int
4701 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4702 {
4703         struct ixgbe_hw *hw;
4704
4705         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4706         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4707 }
4708
4709 static int
4710 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4711 {
4712         struct ixgbe_hw *hw;
4713         uint32_t mflcn_reg;
4714         uint32_t fccfg_reg;
4715         int rx_pause;
4716         int tx_pause;
4717
4718         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4719
4720         fc_conf->pause_time = hw->fc.pause_time;
4721         fc_conf->high_water = hw->fc.high_water[0];
4722         fc_conf->low_water = hw->fc.low_water[0];
4723         fc_conf->send_xon = hw->fc.send_xon;
4724         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4725
4726         /*
4727          * Return rx_pause status according to actual setting of
4728          * MFLCN register.
4729          */
4730         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4731         if (mflcn_reg & IXGBE_MFLCN_PMCF)
4732                 fc_conf->mac_ctrl_frame_fwd = 1;
4733         else
4734                 fc_conf->mac_ctrl_frame_fwd = 0;
4735
4736         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4737                 rx_pause = 1;
4738         else
4739                 rx_pause = 0;
4740
4741         /*
4742          * Return tx_pause status according to actual setting of
4743          * FCCFG register.
4744          */
4745         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4746         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4747                 tx_pause = 1;
4748         else
4749                 tx_pause = 0;
4750
4751         if (rx_pause && tx_pause)
4752                 fc_conf->mode = RTE_FC_FULL;
4753         else if (rx_pause)
4754                 fc_conf->mode = RTE_FC_RX_PAUSE;
4755         else if (tx_pause)
4756                 fc_conf->mode = RTE_FC_TX_PAUSE;
4757         else
4758                 fc_conf->mode = RTE_FC_NONE;
4759
4760         return 0;
4761 }
4762
4763 static int
4764 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4765 {
4766         struct ixgbe_hw *hw;
4767         struct ixgbe_adapter *adapter = dev->data->dev_private;
4768         int err;
4769         uint32_t rx_buf_size;
4770         uint32_t max_high_water;
4771         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4772                 ixgbe_fc_none,
4773                 ixgbe_fc_rx_pause,
4774                 ixgbe_fc_tx_pause,
4775                 ixgbe_fc_full
4776         };
4777
4778         PMD_INIT_FUNC_TRACE();
4779
4780         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4781         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4782         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4783
4784         /*
4785          * At least reserve one Ethernet frame for watermark
4786          * high_water/low_water in kilo bytes for ixgbe
4787          */
4788         max_high_water = (rx_buf_size -
4789                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4790         if ((fc_conf->high_water > max_high_water) ||
4791                 (fc_conf->high_water < fc_conf->low_water)) {
4792                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4793                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4794                 return -EINVAL;
4795         }
4796
4797         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4798         hw->fc.pause_time     = fc_conf->pause_time;
4799         hw->fc.high_water[0]  = fc_conf->high_water;
4800         hw->fc.low_water[0]   = fc_conf->low_water;
4801         hw->fc.send_xon       = fc_conf->send_xon;
4802         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4803         adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4804
4805         err = ixgbe_flow_ctrl_enable(dev, hw);
4806         if (err < 0) {
4807                 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4808                 return -EIO;
4809         }
4810         return err;
4811 }
4812
4813 /**
4814  *  ixgbe_pfc_enable_generic - Enable flow control
4815  *  @hw: pointer to hardware structure
4816  *  @tc_num: traffic class number
4817  *  Enable flow control according to the current settings.
4818  */
4819 static int
4820 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4821 {
4822         int ret_val = 0;
4823         uint32_t mflcn_reg, fccfg_reg;
4824         uint32_t reg;
4825         uint32_t fcrtl, fcrth;
4826         uint8_t i;
4827         uint8_t nb_rx_en;
4828
4829         /* Validate the water mark configuration */
4830         if (!hw->fc.pause_time) {
4831                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4832                 goto out;
4833         }
4834
4835         /* Low water mark of zero causes XOFF floods */
4836         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4837                  /* High/Low water can not be 0 */
4838                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4839                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4840                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4841                         goto out;
4842                 }
4843
4844                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4845                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4846                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4847                         goto out;
4848                 }
4849         }
4850         /* Negotiate the fc mode to use */
4851         ixgbe_fc_autoneg(hw);
4852
4853         /* Disable any previous flow control settings */
4854         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4855         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4856
4857         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4858         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4859
4860         switch (hw->fc.current_mode) {
4861         case ixgbe_fc_none:
4862                 /*
4863                  * If the count of enabled RX Priority Flow control >1,
4864                  * and the TX pause can not be disabled
4865                  */
4866                 nb_rx_en = 0;
4867                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4868                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4869                         if (reg & IXGBE_FCRTH_FCEN)
4870                                 nb_rx_en++;
4871                 }
4872                 if (nb_rx_en > 1)
4873                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4874                 break;
4875         case ixgbe_fc_rx_pause:
4876                 /*
4877                  * Rx Flow control is enabled and Tx Flow control is
4878                  * disabled by software override. Since there really
4879                  * isn't a way to advertise that we are capable of RX
4880                  * Pause ONLY, we will advertise that we support both
4881                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4882                  * disable the adapter's ability to send PAUSE frames.
4883                  */
4884                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4885                 /*
4886                  * If the count of enabled RX Priority Flow control >1,
4887                  * and the TX pause can not be disabled
4888                  */
4889                 nb_rx_en = 0;
4890                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4891                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4892                         if (reg & IXGBE_FCRTH_FCEN)
4893                                 nb_rx_en++;
4894                 }
4895                 if (nb_rx_en > 1)
4896                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4897                 break;
4898         case ixgbe_fc_tx_pause:
4899                 /*
4900                  * Tx Flow control is enabled, and Rx Flow control is
4901                  * disabled by software override.
4902                  */
4903                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4904                 break;
4905         case ixgbe_fc_full:
4906                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4907                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4908                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4909                 break;
4910         default:
4911                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4912                 ret_val = IXGBE_ERR_CONFIG;
4913                 goto out;
4914         }
4915
4916         /* Set 802.3x based flow control settings. */
4917         mflcn_reg |= IXGBE_MFLCN_DPF;
4918         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4919         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4920
4921         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4922         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4923                 hw->fc.high_water[tc_num]) {
4924                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4925                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4926                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4927         } else {
4928                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4929                 /*
4930                  * In order to prevent Tx hangs when the internal Tx
4931                  * switch is enabled we must set the high water mark
4932                  * to the maximum FCRTH value.  This allows the Tx
4933                  * switch to function even under heavy Rx workloads.
4934                  */
4935                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4936         }
4937         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4938
4939         /* Configure pause time (2 TCs per register) */
4940         reg = hw->fc.pause_time * 0x00010001;
4941         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4942                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4943
4944         /* Configure flow control refresh threshold value */
4945         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4946
4947 out:
4948         return ret_val;
4949 }
4950
4951 static int
4952 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4953 {
4954         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4955         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4956
4957         if (hw->mac.type != ixgbe_mac_82598EB) {
4958                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4959         }
4960         return ret_val;
4961 }
4962
4963 static int
4964 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4965 {
4966         int err;
4967         uint32_t rx_buf_size;
4968         uint32_t max_high_water;
4969         uint8_t tc_num;
4970         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4971         struct ixgbe_hw *hw =
4972                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4973         struct ixgbe_dcb_config *dcb_config =
4974                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4975
4976         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4977                 ixgbe_fc_none,
4978                 ixgbe_fc_rx_pause,
4979                 ixgbe_fc_tx_pause,
4980                 ixgbe_fc_full
4981         };
4982
4983         PMD_INIT_FUNC_TRACE();
4984
4985         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4986         tc_num = map[pfc_conf->priority];
4987         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4988         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4989         /*
4990          * At least reserve one Ethernet frame for watermark
4991          * high_water/low_water in kilo bytes for ixgbe
4992          */
4993         max_high_water = (rx_buf_size -
4994                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4995         if ((pfc_conf->fc.high_water > max_high_water) ||
4996             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4997                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4998                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4999                 return -EINVAL;
5000         }
5001
5002         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
5003         hw->fc.pause_time = pfc_conf->fc.pause_time;
5004         hw->fc.send_xon = pfc_conf->fc.send_xon;
5005         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
5006         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
5007
5008         err = ixgbe_dcb_pfc_enable(dev, tc_num);
5009
5010         /* Not negotiated is not an error case */
5011         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5012                 return 0;
5013
5014         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5015         return -EIO;
5016 }
5017
5018 static int
5019 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5020                           struct rte_eth_rss_reta_entry64 *reta_conf,
5021                           uint16_t reta_size)
5022 {
5023         uint16_t i, sp_reta_size;
5024         uint8_t j, mask;
5025         uint32_t reta, r;
5026         uint16_t idx, shift;
5027         struct ixgbe_adapter *adapter = dev->data->dev_private;
5028         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5029         uint32_t reta_reg;
5030
5031         PMD_INIT_FUNC_TRACE();
5032
5033         if (!ixgbe_rss_update_sp(hw->mac.type)) {
5034                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5035                         "NIC.");
5036                 return -ENOTSUP;
5037         }
5038
5039         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5040         if (reta_size != sp_reta_size) {
5041                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5042                         "(%d) doesn't match the number hardware can supported "
5043                         "(%d)", reta_size, sp_reta_size);
5044                 return -EINVAL;
5045         }
5046
5047         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5048                 idx = i / RTE_RETA_GROUP_SIZE;
5049                 shift = i % RTE_RETA_GROUP_SIZE;
5050                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5051                                                 IXGBE_4_BIT_MASK);
5052                 if (!mask)
5053                         continue;
5054                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5055                 if (mask == IXGBE_4_BIT_MASK)
5056                         r = 0;
5057                 else
5058                         r = IXGBE_READ_REG(hw, reta_reg);
5059                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5060                         if (mask & (0x1 << j))
5061                                 reta |= reta_conf[idx].reta[shift + j] <<
5062                                                         (CHAR_BIT * j);
5063                         else
5064                                 reta |= r & (IXGBE_8_BIT_MASK <<
5065                                                 (CHAR_BIT * j));
5066                 }
5067                 IXGBE_WRITE_REG(hw, reta_reg, reta);
5068         }
5069         adapter->rss_reta_updated = 1;
5070
5071         return 0;
5072 }
5073
5074 static int
5075 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5076                          struct rte_eth_rss_reta_entry64 *reta_conf,
5077                          uint16_t reta_size)
5078 {
5079         uint16_t i, sp_reta_size;
5080         uint8_t j, mask;
5081         uint32_t reta;
5082         uint16_t idx, shift;
5083         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5084         uint32_t reta_reg;
5085
5086         PMD_INIT_FUNC_TRACE();
5087         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5088         if (reta_size != sp_reta_size) {
5089                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5090                         "(%d) doesn't match the number hardware can supported "
5091                         "(%d)", reta_size, sp_reta_size);
5092                 return -EINVAL;
5093         }
5094
5095         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5096                 idx = i / RTE_RETA_GROUP_SIZE;
5097                 shift = i % RTE_RETA_GROUP_SIZE;
5098                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5099                                                 IXGBE_4_BIT_MASK);
5100                 if (!mask)
5101                         continue;
5102
5103                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5104                 reta = IXGBE_READ_REG(hw, reta_reg);
5105                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5106                         if (mask & (0x1 << j))
5107                                 reta_conf[idx].reta[shift + j] =
5108                                         ((reta >> (CHAR_BIT * j)) &
5109                                                 IXGBE_8_BIT_MASK);
5110                 }
5111         }
5112
5113         return 0;
5114 }
5115
5116 static int
5117 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5118                                 uint32_t index, uint32_t pool)
5119 {
5120         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5121         uint32_t enable_addr = 1;
5122
5123         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5124                              pool, enable_addr);
5125 }
5126
5127 static void
5128 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5129 {
5130         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5131
5132         ixgbe_clear_rar(hw, index);
5133 }
5134
5135 static int
5136 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5137 {
5138         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5139
5140         ixgbe_remove_rar(dev, 0);
5141         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5142
5143         return 0;
5144 }
5145
5146 static bool
5147 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5148 {
5149         if (strcmp(dev->device->driver->name, drv->driver.name))
5150                 return false;
5151
5152         return true;
5153 }
5154
5155 bool
5156 is_ixgbe_supported(struct rte_eth_dev *dev)
5157 {
5158         return is_device_supported(dev, &rte_ixgbe_pmd);
5159 }
5160
5161 static int
5162 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5163 {
5164         uint32_t hlreg0;
5165         uint32_t maxfrs;
5166         struct ixgbe_hw *hw;
5167         struct rte_eth_dev_info dev_info;
5168         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5169         struct rte_eth_dev_data *dev_data = dev->data;
5170         int ret;
5171
5172         ret = ixgbe_dev_info_get(dev, &dev_info);
5173         if (ret != 0)
5174                 return ret;
5175
5176         /* check that mtu is within the allowed range */
5177         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5178                 return -EINVAL;
5179
5180         /* If device is started, refuse mtu that requires the support of
5181          * scattered packets when this feature has not been enabled before.
5182          */
5183         if (dev_data->dev_started && !dev_data->scattered_rx &&
5184             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5185              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5186                 PMD_INIT_LOG(ERR, "Stop port first.");
5187                 return -EINVAL;
5188         }
5189
5190         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5191         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5192
5193         /* switch to jumbo mode if needed */
5194         if (frame_size > RTE_ETHER_MAX_LEN) {
5195                 dev->data->dev_conf.rxmode.offloads |=
5196                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5197                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5198         } else {
5199                 dev->data->dev_conf.rxmode.offloads &=
5200                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5201                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5202         }
5203         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5204
5205         /* update max frame size */
5206         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5207
5208         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5209         maxfrs &= 0x0000FFFF;
5210         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5211         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5212
5213         return 0;
5214 }
5215
5216 /*
5217  * Virtual Function operations
5218  */
5219 static void
5220 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5221 {
5222         struct ixgbe_interrupt *intr =
5223                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5224         struct ixgbe_hw *hw =
5225                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5226
5227         PMD_INIT_FUNC_TRACE();
5228
5229         /* Clear interrupt mask to stop from interrupts being generated */
5230         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5231
5232         IXGBE_WRITE_FLUSH(hw);
5233
5234         /* Clear mask value. */
5235         intr->mask = 0;
5236 }
5237
5238 static void
5239 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5240 {
5241         struct ixgbe_interrupt *intr =
5242                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5243         struct ixgbe_hw *hw =
5244                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5245
5246         PMD_INIT_FUNC_TRACE();
5247
5248         /* VF enable interrupt autoclean */
5249         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5250         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5251         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5252
5253         IXGBE_WRITE_FLUSH(hw);
5254
5255         /* Save IXGBE_VTEIMS value to mask. */
5256         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5257 }
5258
5259 static int
5260 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5261 {
5262         struct rte_eth_conf *conf = &dev->data->dev_conf;
5263         struct ixgbe_adapter *adapter = dev->data->dev_private;
5264
5265         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5266                      dev->data->port_id);
5267
5268         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5269                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5270
5271         /*
5272          * VF has no ability to enable/disable HW CRC
5273          * Keep the persistent behavior the same as Host PF
5274          */
5275 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5276         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5277                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5278                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5279         }
5280 #else
5281         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5282                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5283                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5284         }
5285 #endif
5286
5287         /*
5288          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5289          * allocation or vector Rx preconditions we will reset it.
5290          */
5291         adapter->rx_bulk_alloc_allowed = true;
5292         adapter->rx_vec_allowed = true;
5293
5294         return 0;
5295 }
5296
5297 static int
5298 ixgbevf_dev_start(struct rte_eth_dev *dev)
5299 {
5300         struct ixgbe_hw *hw =
5301                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5302         uint32_t intr_vector = 0;
5303         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5304         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5305
5306         int err, mask = 0;
5307
5308         PMD_INIT_FUNC_TRACE();
5309
5310         /* Stop the link setup handler before resetting the HW. */
5311         ixgbe_dev_wait_setup_link_complete(dev, 0);
5312
5313         err = hw->mac.ops.reset_hw(hw);
5314
5315         /**
5316          * In this case, reuses the MAC address assigned by VF
5317          * initialization.
5318          */
5319         if (err != IXGBE_SUCCESS && err != IXGBE_ERR_INVALID_MAC_ADDR) {
5320                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5321                 return err;
5322         }
5323
5324         hw->mac.get_link_status = true;
5325
5326         /* negotiate mailbox API version to use with the PF. */
5327         ixgbevf_negotiate_api(hw);
5328
5329         ixgbevf_dev_tx_init(dev);
5330
5331         /* This can fail when allocating mbufs for descriptor rings */
5332         err = ixgbevf_dev_rx_init(dev);
5333         if (err) {
5334                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5335                 ixgbe_dev_clear_queues(dev);
5336                 return err;
5337         }
5338
5339         /* Set vfta */
5340         ixgbevf_set_vfta_all(dev, 1);
5341
5342         /* Set HW strip */
5343         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5344                 ETH_VLAN_EXTEND_MASK;
5345         err = ixgbevf_vlan_offload_config(dev, mask);
5346         if (err) {
5347                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5348                 ixgbe_dev_clear_queues(dev);
5349                 return err;
5350         }
5351
5352         ixgbevf_dev_rxtx_start(dev);
5353
5354         /* check and configure queue intr-vector mapping */
5355         if (rte_intr_cap_multiple(intr_handle) &&
5356             dev->data->dev_conf.intr_conf.rxq) {
5357                 /* According to datasheet, only vector 0/1/2 can be used,
5358                  * now only one vector is used for Rx queue
5359                  */
5360                 intr_vector = 1;
5361                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5362                         return -1;
5363         }
5364
5365         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5366                 intr_handle->intr_vec =
5367                         rte_zmalloc("intr_vec",
5368                                     dev->data->nb_rx_queues * sizeof(int), 0);
5369                 if (intr_handle->intr_vec == NULL) {
5370                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5371                                      " intr_vec", dev->data->nb_rx_queues);
5372                         return -ENOMEM;
5373                 }
5374         }
5375         ixgbevf_configure_msix(dev);
5376
5377         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5378          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5379          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5380          * is not cleared, it will fail when following rte_intr_enable( ) tries
5381          * to map Rx queue interrupt to other VFIO vectors.
5382          * So clear uio/vfio intr/evevnfd first to avoid failure.
5383          */
5384         rte_intr_disable(intr_handle);
5385
5386         rte_intr_enable(intr_handle);
5387
5388         /* Re-enable interrupt for VF */
5389         ixgbevf_intr_enable(dev);
5390
5391         /*
5392          * Update link status right before return, because it may
5393          * start link configuration process in a separate thread.
5394          */
5395         ixgbevf_dev_link_update(dev, 0);
5396
5397         hw->adapter_stopped = false;
5398
5399         return 0;
5400 }
5401
5402 static int
5403 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5404 {
5405         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5406         struct ixgbe_adapter *adapter = dev->data->dev_private;
5407         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5408         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5409
5410         if (hw->adapter_stopped)
5411                 return 0;
5412
5413         PMD_INIT_FUNC_TRACE();
5414
5415         ixgbe_dev_wait_setup_link_complete(dev, 0);
5416
5417         ixgbevf_intr_disable(dev);
5418
5419         dev->data->dev_started = 0;
5420         hw->adapter_stopped = 1;
5421         ixgbe_stop_adapter(hw);
5422
5423         /*
5424           * Clear what we set, but we still keep shadow_vfta to
5425           * restore after device starts
5426           */
5427         ixgbevf_set_vfta_all(dev, 0);
5428
5429         /* Clear stored conf */
5430         dev->data->scattered_rx = 0;
5431
5432         ixgbe_dev_clear_queues(dev);
5433
5434         /* Clean datapath event and queue/vec mapping */
5435         rte_intr_efd_disable(intr_handle);
5436         if (intr_handle->intr_vec != NULL) {
5437                 rte_free(intr_handle->intr_vec);
5438                 intr_handle->intr_vec = NULL;
5439         }
5440
5441         adapter->rss_reta_updated = 0;
5442
5443         return 0;
5444 }
5445
5446 static int
5447 ixgbevf_dev_close(struct rte_eth_dev *dev)
5448 {
5449         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5450         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5451         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5452         int ret;
5453
5454         PMD_INIT_FUNC_TRACE();
5455         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5456                 return 0;
5457
5458         ixgbe_reset_hw(hw);
5459
5460         ret = ixgbevf_dev_stop(dev);
5461
5462         ixgbe_dev_free_queues(dev);
5463
5464         /**
5465          * Remove the VF MAC address ro ensure
5466          * that the VF traffic goes to the PF
5467          * after stop, close and detach of the VF
5468          **/
5469         ixgbevf_remove_mac_addr(dev, 0);
5470
5471         rte_intr_disable(intr_handle);
5472         rte_intr_callback_unregister(intr_handle,
5473                                      ixgbevf_dev_interrupt_handler, dev);
5474
5475         return ret;
5476 }
5477
5478 /*
5479  * Reset VF device
5480  */
5481 static int
5482 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5483 {
5484         int ret;
5485
5486         ret = eth_ixgbevf_dev_uninit(dev);
5487         if (ret)
5488                 return ret;
5489
5490         ret = eth_ixgbevf_dev_init(dev);
5491
5492         return ret;
5493 }
5494
5495 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5496 {
5497         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5498         struct ixgbe_vfta *shadow_vfta =
5499                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5500         int i = 0, j = 0, vfta = 0, mask = 1;
5501
5502         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5503                 vfta = shadow_vfta->vfta[i];
5504                 if (vfta) {
5505                         mask = 1;
5506                         for (j = 0; j < 32; j++) {
5507                                 if (vfta & mask)
5508                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5509                                                        on, false);
5510                                 mask <<= 1;
5511                         }
5512                 }
5513         }
5514
5515 }
5516
5517 static int
5518 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5519 {
5520         struct ixgbe_hw *hw =
5521                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5522         struct ixgbe_vfta *shadow_vfta =
5523                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5524         uint32_t vid_idx = 0;
5525         uint32_t vid_bit = 0;
5526         int ret = 0;
5527
5528         PMD_INIT_FUNC_TRACE();
5529
5530         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5531         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5532         if (ret) {
5533                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5534                 return ret;
5535         }
5536         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5537         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5538
5539         /* Save what we set and retore it after device reset */
5540         if (on)
5541                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5542         else
5543                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5544
5545         return 0;
5546 }
5547
5548 static void
5549 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5550 {
5551         struct ixgbe_hw *hw =
5552                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5553         uint32_t ctrl;
5554
5555         PMD_INIT_FUNC_TRACE();
5556
5557         if (queue >= hw->mac.max_rx_queues)
5558                 return;
5559
5560         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5561         if (on)
5562                 ctrl |= IXGBE_RXDCTL_VME;
5563         else
5564                 ctrl &= ~IXGBE_RXDCTL_VME;
5565         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5566
5567         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5568 }
5569
5570 static int
5571 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5572 {
5573         struct ixgbe_rx_queue *rxq;
5574         uint16_t i;
5575         int on = 0;
5576
5577         /* VF function only support hw strip feature, others are not support */
5578         if (mask & ETH_VLAN_STRIP_MASK) {
5579                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5580                         rxq = dev->data->rx_queues[i];
5581                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5582                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5583                 }
5584         }
5585
5586         return 0;
5587 }
5588
5589 static int
5590 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5591 {
5592         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5593
5594         ixgbevf_vlan_offload_config(dev, mask);
5595
5596         return 0;
5597 }
5598
5599 int
5600 ixgbe_vt_check(struct ixgbe_hw *hw)
5601 {
5602         uint32_t reg_val;
5603
5604         /* if Virtualization Technology is enabled */
5605         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5606         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5607                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5608                 return -1;
5609         }
5610
5611         return 0;
5612 }
5613
5614 static uint32_t
5615 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5616 {
5617         uint32_t vector = 0;
5618
5619         switch (hw->mac.mc_filter_type) {
5620         case 0:   /* use bits [47:36] of the address */
5621                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5622                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5623                 break;
5624         case 1:   /* use bits [46:35] of the address */
5625                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5626                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5627                 break;
5628         case 2:   /* use bits [45:34] of the address */
5629                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5630                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5631                 break;
5632         case 3:   /* use bits [43:32] of the address */
5633                 vector = ((uc_addr->addr_bytes[4]) |
5634                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5635                 break;
5636         default:  /* Invalid mc_filter_type */
5637                 break;
5638         }
5639
5640         /* vector can only be 12-bits or boundary will be exceeded */
5641         vector &= 0xFFF;
5642         return vector;
5643 }
5644
5645 static int
5646 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5647                         struct rte_ether_addr *mac_addr, uint8_t on)
5648 {
5649         uint32_t vector;
5650         uint32_t uta_idx;
5651         uint32_t reg_val;
5652         uint32_t uta_shift;
5653         uint32_t rc;
5654         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5655         const uint32_t ixgbe_uta_bit_shift = 5;
5656         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5657         const uint32_t bit1 = 0x1;
5658
5659         struct ixgbe_hw *hw =
5660                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5661         struct ixgbe_uta_info *uta_info =
5662                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5663
5664         /* The UTA table only exists on 82599 hardware and newer */
5665         if (hw->mac.type < ixgbe_mac_82599EB)
5666                 return -ENOTSUP;
5667
5668         vector = ixgbe_uta_vector(hw, mac_addr);
5669         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5670         uta_shift = vector & ixgbe_uta_bit_mask;
5671
5672         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5673         if (rc == on)
5674                 return 0;
5675
5676         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5677         if (on) {
5678                 uta_info->uta_in_use++;
5679                 reg_val |= (bit1 << uta_shift);
5680                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5681         } else {
5682                 uta_info->uta_in_use--;
5683                 reg_val &= ~(bit1 << uta_shift);
5684                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5685         }
5686
5687         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5688
5689         if (uta_info->uta_in_use > 0)
5690                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5691                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5692         else
5693                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5694
5695         return 0;
5696 }
5697
5698 static int
5699 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5700 {
5701         int i;
5702         struct ixgbe_hw *hw =
5703                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5704         struct ixgbe_uta_info *uta_info =
5705                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5706
5707         /* The UTA table only exists on 82599 hardware and newer */
5708         if (hw->mac.type < ixgbe_mac_82599EB)
5709                 return -ENOTSUP;
5710
5711         if (on) {
5712                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5713                         uta_info->uta_shadow[i] = ~0;
5714                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5715                 }
5716         } else {
5717                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5718                         uta_info->uta_shadow[i] = 0;
5719                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5720                 }
5721         }
5722         return 0;
5723
5724 }
5725
5726 uint32_t
5727 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5728 {
5729         uint32_t new_val = orig_val;
5730
5731         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5732                 new_val |= IXGBE_VMOLR_AUPE;
5733         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5734                 new_val |= IXGBE_VMOLR_ROMPE;
5735         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5736                 new_val |= IXGBE_VMOLR_ROPE;
5737         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5738                 new_val |= IXGBE_VMOLR_BAM;
5739         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5740                 new_val |= IXGBE_VMOLR_MPE;
5741
5742         return new_val;
5743 }
5744
5745 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5746 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5747 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5748 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5749 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5750         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5751         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5752
5753 static int
5754 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5755                       struct rte_eth_mirror_conf *mirror_conf,
5756                       uint8_t rule_id, uint8_t on)
5757 {
5758         uint32_t mr_ctl, vlvf;
5759         uint32_t mp_lsb = 0;
5760         uint32_t mv_msb = 0;
5761         uint32_t mv_lsb = 0;
5762         uint32_t mp_msb = 0;
5763         uint8_t i = 0;
5764         int reg_index = 0;
5765         uint64_t vlan_mask = 0;
5766
5767         const uint8_t pool_mask_offset = 32;
5768         const uint8_t vlan_mask_offset = 32;
5769         const uint8_t dst_pool_offset = 8;
5770         const uint8_t rule_mr_offset  = 4;
5771         const uint8_t mirror_rule_mask = 0x0F;
5772
5773         struct ixgbe_mirror_info *mr_info =
5774                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5775         struct ixgbe_hw *hw =
5776                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5777         uint8_t mirror_type = 0;
5778
5779         if (ixgbe_vt_check(hw) < 0)
5780                 return -ENOTSUP;
5781
5782         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5783                 return -EINVAL;
5784
5785         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5786                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5787                             mirror_conf->rule_type);
5788                 return -EINVAL;
5789         }
5790
5791         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5792                 mirror_type |= IXGBE_MRCTL_VLME;
5793                 /* Check if vlan id is valid and find conresponding VLAN ID
5794                  * index in VLVF
5795                  */
5796                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5797                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5798                                 /* search vlan id related pool vlan filter
5799                                  * index
5800                                  */
5801                                 reg_index = ixgbe_find_vlvf_slot(
5802                                                 hw,
5803                                                 mirror_conf->vlan.vlan_id[i],
5804                                                 false);
5805                                 if (reg_index < 0)
5806                                         return -EINVAL;
5807                                 vlvf = IXGBE_READ_REG(hw,
5808                                                       IXGBE_VLVF(reg_index));
5809                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5810                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5811                                       mirror_conf->vlan.vlan_id[i]))
5812                                         vlan_mask |= (1ULL << reg_index);
5813                                 else
5814                                         return -EINVAL;
5815                         }
5816                 }
5817
5818                 if (on) {
5819                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5820                         mv_msb = vlan_mask >> vlan_mask_offset;
5821
5822                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5823                                                 mirror_conf->vlan.vlan_mask;
5824                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5825                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5826                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5827                                                 mirror_conf->vlan.vlan_id[i];
5828                         }
5829                 } else {
5830                         mv_lsb = 0;
5831                         mv_msb = 0;
5832                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5833                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5834                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5835                 }
5836         }
5837
5838         /**
5839          * if enable pool mirror, write related pool mask register,if disable
5840          * pool mirror, clear PFMRVM register
5841          */
5842         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5843                 mirror_type |= IXGBE_MRCTL_VPME;
5844                 if (on) {
5845                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5846                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5847                         mr_info->mr_conf[rule_id].pool_mask =
5848                                         mirror_conf->pool_mask;
5849
5850                 } else {
5851                         mp_lsb = 0;
5852                         mp_msb = 0;
5853                         mr_info->mr_conf[rule_id].pool_mask = 0;
5854                 }
5855         }
5856         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5857                 mirror_type |= IXGBE_MRCTL_UPME;
5858         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5859                 mirror_type |= IXGBE_MRCTL_DPME;
5860
5861         /* read  mirror control register and recalculate it */
5862         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5863
5864         if (on) {
5865                 mr_ctl |= mirror_type;
5866                 mr_ctl &= mirror_rule_mask;
5867                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5868         } else {
5869                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5870         }
5871
5872         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5873         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5874
5875         /* write mirrror control  register */
5876         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5877
5878         /* write pool mirrror control  register */
5879         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5880                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5881                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5882                                 mp_msb);
5883         }
5884         /* write VLAN mirrror control  register */
5885         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5886                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5887                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5888                                 mv_msb);
5889         }
5890
5891         return 0;
5892 }
5893
5894 static int
5895 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5896 {
5897         int mr_ctl = 0;
5898         uint32_t lsb_val = 0;
5899         uint32_t msb_val = 0;
5900         const uint8_t rule_mr_offset = 4;
5901
5902         struct ixgbe_hw *hw =
5903                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5904         struct ixgbe_mirror_info *mr_info =
5905                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5906
5907         if (ixgbe_vt_check(hw) < 0)
5908                 return -ENOTSUP;
5909
5910         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5911                 return -EINVAL;
5912
5913         memset(&mr_info->mr_conf[rule_id], 0,
5914                sizeof(struct rte_eth_mirror_conf));
5915
5916         /* clear PFVMCTL register */
5917         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5918
5919         /* clear pool mask register */
5920         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5921         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5922
5923         /* clear vlan mask register */
5924         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5925         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5926
5927         return 0;
5928 }
5929
5930 static int
5931 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5932 {
5933         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5934         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5935         struct ixgbe_interrupt *intr =
5936                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5937         struct ixgbe_hw *hw =
5938                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5939         uint32_t vec = IXGBE_MISC_VEC_ID;
5940
5941         if (rte_intr_allow_others(intr_handle))
5942                 vec = IXGBE_RX_VEC_START;
5943         intr->mask |= (1 << vec);
5944         RTE_SET_USED(queue_id);
5945         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5946
5947         rte_intr_ack(intr_handle);
5948
5949         return 0;
5950 }
5951
5952 static int
5953 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5954 {
5955         struct ixgbe_interrupt *intr =
5956                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5957         struct ixgbe_hw *hw =
5958                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5959         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5960         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5961         uint32_t vec = IXGBE_MISC_VEC_ID;
5962
5963         if (rte_intr_allow_others(intr_handle))
5964                 vec = IXGBE_RX_VEC_START;
5965         intr->mask &= ~(1 << vec);
5966         RTE_SET_USED(queue_id);
5967         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5968
5969         return 0;
5970 }
5971
5972 static int
5973 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5974 {
5975         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5976         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5977         uint32_t mask;
5978         struct ixgbe_hw *hw =
5979                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5980         struct ixgbe_interrupt *intr =
5981                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5982
5983         if (queue_id < 16) {
5984                 ixgbe_disable_intr(hw);
5985                 intr->mask |= (1 << queue_id);
5986                 ixgbe_enable_intr(dev);
5987         } else if (queue_id < 32) {
5988                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5989                 mask &= (1 << queue_id);
5990                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5991         } else if (queue_id < 64) {
5992                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5993                 mask &= (1 << (queue_id - 32));
5994                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5995         }
5996         rte_intr_ack(intr_handle);
5997
5998         return 0;
5999 }
6000
6001 static int
6002 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
6003 {
6004         uint32_t mask;
6005         struct ixgbe_hw *hw =
6006                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6007         struct ixgbe_interrupt *intr =
6008                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
6009
6010         if (queue_id < 16) {
6011                 ixgbe_disable_intr(hw);
6012                 intr->mask &= ~(1 << queue_id);
6013                 ixgbe_enable_intr(dev);
6014         } else if (queue_id < 32) {
6015                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
6016                 mask &= ~(1 << queue_id);
6017                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6018         } else if (queue_id < 64) {
6019                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6020                 mask &= ~(1 << (queue_id - 32));
6021                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6022         }
6023
6024         return 0;
6025 }
6026
6027 static void
6028 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6029                      uint8_t queue, uint8_t msix_vector)
6030 {
6031         uint32_t tmp, idx;
6032
6033         if (direction == -1) {
6034                 /* other causes */
6035                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6036                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
6037                 tmp &= ~0xFF;
6038                 tmp |= msix_vector;
6039                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6040         } else {
6041                 /* rx or tx cause */
6042                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6043                 idx = ((16 * (queue & 1)) + (8 * direction));
6044                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6045                 tmp &= ~(0xFF << idx);
6046                 tmp |= (msix_vector << idx);
6047                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6048         }
6049 }
6050
6051 /**
6052  * set the IVAR registers, mapping interrupt causes to vectors
6053  * @param hw
6054  *  pointer to ixgbe_hw struct
6055  * @direction
6056  *  0 for Rx, 1 for Tx, -1 for other causes
6057  * @queue
6058  *  queue to map the corresponding interrupt to
6059  * @msix_vector
6060  *  the vector to map to the corresponding queue
6061  */
6062 static void
6063 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6064                    uint8_t queue, uint8_t msix_vector)
6065 {
6066         uint32_t tmp, idx;
6067
6068         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6069         if (hw->mac.type == ixgbe_mac_82598EB) {
6070                 if (direction == -1)
6071                         direction = 0;
6072                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6073                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6074                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6075                 tmp |= (msix_vector << (8 * (queue & 0x3)));
6076                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6077         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6078                         (hw->mac.type == ixgbe_mac_X540) ||
6079                         (hw->mac.type == ixgbe_mac_X550) ||
6080                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
6081                 if (direction == -1) {
6082                         /* other causes */
6083                         idx = ((queue & 1) * 8);
6084                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6085                         tmp &= ~(0xFF << idx);
6086                         tmp |= (msix_vector << idx);
6087                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6088                 } else {
6089                         /* rx or tx causes */
6090                         idx = ((16 * (queue & 1)) + (8 * direction));
6091                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6092                         tmp &= ~(0xFF << idx);
6093                         tmp |= (msix_vector << idx);
6094                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6095                 }
6096         }
6097 }
6098
6099 static void
6100 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6101 {
6102         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6103         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6104         struct ixgbe_hw *hw =
6105                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6106         uint32_t q_idx;
6107         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6108         uint32_t base = IXGBE_MISC_VEC_ID;
6109
6110         /* Configure VF other cause ivar */
6111         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6112
6113         /* won't configure msix register if no mapping is done
6114          * between intr vector and event fd.
6115          */
6116         if (!rte_intr_dp_is_en(intr_handle))
6117                 return;
6118
6119         if (rte_intr_allow_others(intr_handle)) {
6120                 base = IXGBE_RX_VEC_START;
6121                 vector_idx = IXGBE_RX_VEC_START;
6122         }
6123
6124         /* Configure all RX queues of VF */
6125         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6126                 /* Force all queue use vector 0,
6127                  * as IXGBE_VF_MAXMSIVECOTR = 1
6128                  */
6129                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6130                 intr_handle->intr_vec[q_idx] = vector_idx;
6131                 if (vector_idx < base + intr_handle->nb_efd - 1)
6132                         vector_idx++;
6133         }
6134
6135         /* As RX queue setting above show, all queues use the vector 0.
6136          * Set only the ITR value of IXGBE_MISC_VEC_ID.
6137          */
6138         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6139                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6140                         | IXGBE_EITR_CNT_WDIS);
6141 }
6142
6143 /**
6144  * Sets up the hardware to properly generate MSI-X interrupts
6145  * @hw
6146  *  board private structure
6147  */
6148 static void
6149 ixgbe_configure_msix(struct rte_eth_dev *dev)
6150 {
6151         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6152         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6153         struct ixgbe_hw *hw =
6154                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6155         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6156         uint32_t vec = IXGBE_MISC_VEC_ID;
6157         uint32_t mask;
6158         uint32_t gpie;
6159
6160         /* won't configure msix register if no mapping is done
6161          * between intr vector and event fd
6162          * but if misx has been enabled already, need to configure
6163          * auto clean, auto mask and throttling.
6164          */
6165         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6166         if (!rte_intr_dp_is_en(intr_handle) &&
6167             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6168                 return;
6169
6170         if (rte_intr_allow_others(intr_handle))
6171                 vec = base = IXGBE_RX_VEC_START;
6172
6173         /* setup GPIE for MSI-x mode */
6174         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6175         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6176                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6177         /* auto clearing and auto setting corresponding bits in EIMS
6178          * when MSI-X interrupt is triggered
6179          */
6180         if (hw->mac.type == ixgbe_mac_82598EB) {
6181                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6182         } else {
6183                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6184                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6185         }
6186         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6187
6188         /* Populate the IVAR table and set the ITR values to the
6189          * corresponding register.
6190          */
6191         if (rte_intr_dp_is_en(intr_handle)) {
6192                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6193                         queue_id++) {
6194                         /* by default, 1:1 mapping */
6195                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6196                         intr_handle->intr_vec[queue_id] = vec;
6197                         if (vec < base + intr_handle->nb_efd - 1)
6198                                 vec++;
6199                 }
6200
6201                 switch (hw->mac.type) {
6202                 case ixgbe_mac_82598EB:
6203                         ixgbe_set_ivar_map(hw, -1,
6204                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6205                                            IXGBE_MISC_VEC_ID);
6206                         break;
6207                 case ixgbe_mac_82599EB:
6208                 case ixgbe_mac_X540:
6209                 case ixgbe_mac_X550:
6210                 case ixgbe_mac_X550EM_x:
6211                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6212                         break;
6213                 default:
6214                         break;
6215                 }
6216         }
6217         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6218                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6219                         | IXGBE_EITR_CNT_WDIS);
6220
6221         /* set up to autoclear timer, and the vectors */
6222         mask = IXGBE_EIMS_ENABLE_MASK;
6223         mask &= ~(IXGBE_EIMS_OTHER |
6224                   IXGBE_EIMS_MAILBOX |
6225                   IXGBE_EIMS_LSC);
6226
6227         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6228 }
6229
6230 int
6231 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6232                            uint16_t queue_idx, uint16_t tx_rate)
6233 {
6234         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6235         struct rte_eth_rxmode *rxmode;
6236         uint32_t rf_dec, rf_int;
6237         uint32_t bcnrc_val;
6238         uint16_t link_speed = dev->data->dev_link.link_speed;
6239
6240         if (queue_idx >= hw->mac.max_tx_queues)
6241                 return -EINVAL;
6242
6243         if (tx_rate != 0) {
6244                 /* Calculate the rate factor values to set */
6245                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6246                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6247                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6248
6249                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6250                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6251                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6252                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6253         } else {
6254                 bcnrc_val = 0;
6255         }
6256
6257         rxmode = &dev->data->dev_conf.rxmode;
6258         /*
6259          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6260          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6261          * set as 0x4.
6262          */
6263         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6264             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6265                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6266                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6267         else
6268                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6269                         IXGBE_MMW_SIZE_DEFAULT);
6270
6271         /* Set RTTBCNRC of queue X */
6272         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6273         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6274         IXGBE_WRITE_FLUSH(hw);
6275
6276         return 0;
6277 }
6278
6279 static int
6280 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6281                      __rte_unused uint32_t index,
6282                      __rte_unused uint32_t pool)
6283 {
6284         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6285         int diag;
6286
6287         /*
6288          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6289          * operation. Trap this case to avoid exhausting the [very limited]
6290          * set of PF resources used to store VF MAC addresses.
6291          */
6292         if (memcmp(hw->mac.perm_addr, mac_addr,
6293                         sizeof(struct rte_ether_addr)) == 0)
6294                 return -1;
6295         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6296         if (diag != 0)
6297                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6298                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6299                             mac_addr->addr_bytes[0],
6300                             mac_addr->addr_bytes[1],
6301                             mac_addr->addr_bytes[2],
6302                             mac_addr->addr_bytes[3],
6303                             mac_addr->addr_bytes[4],
6304                             mac_addr->addr_bytes[5],
6305                             diag);
6306         return diag;
6307 }
6308
6309 static void
6310 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6311 {
6312         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6313         struct rte_ether_addr *perm_addr =
6314                 (struct rte_ether_addr *)hw->mac.perm_addr;
6315         struct rte_ether_addr *mac_addr;
6316         uint32_t i;
6317         int diag;
6318
6319         /*
6320          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6321          * not support the deletion of a given MAC address.
6322          * Instead, it imposes to delete all MAC addresses, then to add again
6323          * all MAC addresses with the exception of the one to be deleted.
6324          */
6325         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6326
6327         /*
6328          * Add again all MAC addresses, with the exception of the deleted one
6329          * and of the permanent MAC address.
6330          */
6331         for (i = 0, mac_addr = dev->data->mac_addrs;
6332              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6333                 /* Skip the deleted MAC address */
6334                 if (i == index)
6335                         continue;
6336                 /* Skip NULL MAC addresses */
6337                 if (rte_is_zero_ether_addr(mac_addr))
6338                         continue;
6339                 /* Skip the permanent MAC address */
6340                 if (memcmp(perm_addr, mac_addr,
6341                                 sizeof(struct rte_ether_addr)) == 0)
6342                         continue;
6343                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6344                 if (diag != 0)
6345                         PMD_DRV_LOG(ERR,
6346                                     "Adding again MAC address "
6347                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6348                                     "diag=%d",
6349                                     mac_addr->addr_bytes[0],
6350                                     mac_addr->addr_bytes[1],
6351                                     mac_addr->addr_bytes[2],
6352                                     mac_addr->addr_bytes[3],
6353                                     mac_addr->addr_bytes[4],
6354                                     mac_addr->addr_bytes[5],
6355                                     diag);
6356         }
6357 }
6358
6359 static int
6360 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6361                         struct rte_ether_addr *addr)
6362 {
6363         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6364
6365         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6366
6367         return 0;
6368 }
6369
6370 int
6371 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6372                         struct rte_eth_syn_filter *filter,
6373                         bool add)
6374 {
6375         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6376         struct ixgbe_filter_info *filter_info =
6377                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6378         uint32_t syn_info;
6379         uint32_t synqf;
6380
6381         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6382                 return -EINVAL;
6383
6384         syn_info = filter_info->syn_info;
6385
6386         if (add) {
6387                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6388                         return -EINVAL;
6389                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6390                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6391
6392                 if (filter->hig_pri)
6393                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6394                 else
6395                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6396         } else {
6397                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6398                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6399                         return -ENOENT;
6400                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6401         }
6402
6403         filter_info->syn_info = synqf;
6404         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6405         IXGBE_WRITE_FLUSH(hw);
6406         return 0;
6407 }
6408
6409
6410 static inline enum ixgbe_5tuple_protocol
6411 convert_protocol_type(uint8_t protocol_value)
6412 {
6413         if (protocol_value == IPPROTO_TCP)
6414                 return IXGBE_FILTER_PROTOCOL_TCP;
6415         else if (protocol_value == IPPROTO_UDP)
6416                 return IXGBE_FILTER_PROTOCOL_UDP;
6417         else if (protocol_value == IPPROTO_SCTP)
6418                 return IXGBE_FILTER_PROTOCOL_SCTP;
6419         else
6420                 return IXGBE_FILTER_PROTOCOL_NONE;
6421 }
6422
6423 /* inject a 5-tuple filter to HW */
6424 static inline void
6425 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6426                            struct ixgbe_5tuple_filter *filter)
6427 {
6428         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6429         int i;
6430         uint32_t ftqf, sdpqf;
6431         uint32_t l34timir = 0;
6432         uint8_t mask = 0xff;
6433
6434         i = filter->index;
6435
6436         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6437                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6438         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6439
6440         ftqf = (uint32_t)(filter->filter_info.proto &
6441                 IXGBE_FTQF_PROTOCOL_MASK);
6442         ftqf |= (uint32_t)((filter->filter_info.priority &
6443                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6444         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6445                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6446         if (filter->filter_info.dst_ip_mask == 0)
6447                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6448         if (filter->filter_info.src_port_mask == 0)
6449                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6450         if (filter->filter_info.dst_port_mask == 0)
6451                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6452         if (filter->filter_info.proto_mask == 0)
6453                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6454         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6455         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6456         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6457
6458         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6459         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6460         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6461         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6462
6463         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6464         l34timir |= (uint32_t)(filter->queue <<
6465                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6466         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6467 }
6468
6469 /*
6470  * add a 5tuple filter
6471  *
6472  * @param
6473  * dev: Pointer to struct rte_eth_dev.
6474  * index: the index the filter allocates.
6475  * filter: ponter to the filter that will be added.
6476  * rx_queue: the queue id the filter assigned to.
6477  *
6478  * @return
6479  *    - On success, zero.
6480  *    - On failure, a negative value.
6481  */
6482 static int
6483 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6484                         struct ixgbe_5tuple_filter *filter)
6485 {
6486         struct ixgbe_filter_info *filter_info =
6487                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6488         int i, idx, shift;
6489
6490         /*
6491          * look for an unused 5tuple filter index,
6492          * and insert the filter to list.
6493          */
6494         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6495                 idx = i / (sizeof(uint32_t) * NBBY);
6496                 shift = i % (sizeof(uint32_t) * NBBY);
6497                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6498                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6499                         filter->index = i;
6500                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6501                                           filter,
6502                                           entries);
6503                         break;
6504                 }
6505         }
6506         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6507                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6508                 return -ENOSYS;
6509         }
6510
6511         ixgbe_inject_5tuple_filter(dev, filter);
6512
6513         return 0;
6514 }
6515
6516 /*
6517  * remove a 5tuple filter
6518  *
6519  * @param
6520  * dev: Pointer to struct rte_eth_dev.
6521  * filter: the pointer of the filter will be removed.
6522  */
6523 static void
6524 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6525                         struct ixgbe_5tuple_filter *filter)
6526 {
6527         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6528         struct ixgbe_filter_info *filter_info =
6529                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6530         uint16_t index = filter->index;
6531
6532         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6533                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6534         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6535         rte_free(filter);
6536
6537         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6538         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6539         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6540         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6541         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6542 }
6543
6544 static int
6545 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6546 {
6547         struct ixgbe_hw *hw;
6548         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6549         struct rte_eth_dev_data *dev_data = dev->data;
6550
6551         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6552
6553         if (mtu < RTE_ETHER_MIN_MTU ||
6554                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6555                 return -EINVAL;
6556
6557         /* If device is started, refuse mtu that requires the support of
6558          * scattered packets when this feature has not been enabled before.
6559          */
6560         if (dev_data->dev_started && !dev_data->scattered_rx &&
6561             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6562              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6563                 PMD_INIT_LOG(ERR, "Stop port first.");
6564                 return -EINVAL;
6565         }
6566
6567         /*
6568          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6569          * request of the version 2.0 of the mailbox API.
6570          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6571          * of the mailbox API.
6572          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6573          * prior to 3.11.33 which contains the following change:
6574          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6575          */
6576         ixgbevf_rlpml_set_vf(hw, max_frame);
6577
6578         /* update max frame size */
6579         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6580         return 0;
6581 }
6582
6583 static inline struct ixgbe_5tuple_filter *
6584 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6585                         struct ixgbe_5tuple_filter_info *key)
6586 {
6587         struct ixgbe_5tuple_filter *it;
6588
6589         TAILQ_FOREACH(it, filter_list, entries) {
6590                 if (memcmp(key, &it->filter_info,
6591                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6592                         return it;
6593                 }
6594         }
6595         return NULL;
6596 }
6597
6598 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6599 static inline int
6600 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6601                         struct ixgbe_5tuple_filter_info *filter_info)
6602 {
6603         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6604                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6605                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6606                 return -EINVAL;
6607
6608         switch (filter->dst_ip_mask) {
6609         case UINT32_MAX:
6610                 filter_info->dst_ip_mask = 0;
6611                 filter_info->dst_ip = filter->dst_ip;
6612                 break;
6613         case 0:
6614                 filter_info->dst_ip_mask = 1;
6615                 break;
6616         default:
6617                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6618                 return -EINVAL;
6619         }
6620
6621         switch (filter->src_ip_mask) {
6622         case UINT32_MAX:
6623                 filter_info->src_ip_mask = 0;
6624                 filter_info->src_ip = filter->src_ip;
6625                 break;
6626         case 0:
6627                 filter_info->src_ip_mask = 1;
6628                 break;
6629         default:
6630                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6631                 return -EINVAL;
6632         }
6633
6634         switch (filter->dst_port_mask) {
6635         case UINT16_MAX:
6636                 filter_info->dst_port_mask = 0;
6637                 filter_info->dst_port = filter->dst_port;
6638                 break;
6639         case 0:
6640                 filter_info->dst_port_mask = 1;
6641                 break;
6642         default:
6643                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6644                 return -EINVAL;
6645         }
6646
6647         switch (filter->src_port_mask) {
6648         case UINT16_MAX:
6649                 filter_info->src_port_mask = 0;
6650                 filter_info->src_port = filter->src_port;
6651                 break;
6652         case 0:
6653                 filter_info->src_port_mask = 1;
6654                 break;
6655         default:
6656                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6657                 return -EINVAL;
6658         }
6659
6660         switch (filter->proto_mask) {
6661         case UINT8_MAX:
6662                 filter_info->proto_mask = 0;
6663                 filter_info->proto =
6664                         convert_protocol_type(filter->proto);
6665                 break;
6666         case 0:
6667                 filter_info->proto_mask = 1;
6668                 break;
6669         default:
6670                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6671                 return -EINVAL;
6672         }
6673
6674         filter_info->priority = (uint8_t)filter->priority;
6675         return 0;
6676 }
6677
6678 /*
6679  * add or delete a ntuple filter
6680  *
6681  * @param
6682  * dev: Pointer to struct rte_eth_dev.
6683  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6684  * add: if true, add filter, if false, remove filter
6685  *
6686  * @return
6687  *    - On success, zero.
6688  *    - On failure, a negative value.
6689  */
6690 int
6691 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6692                         struct rte_eth_ntuple_filter *ntuple_filter,
6693                         bool add)
6694 {
6695         struct ixgbe_filter_info *filter_info =
6696                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6697         struct ixgbe_5tuple_filter_info filter_5tuple;
6698         struct ixgbe_5tuple_filter *filter;
6699         int ret;
6700
6701         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6702                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6703                 return -EINVAL;
6704         }
6705
6706         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6707         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6708         if (ret < 0)
6709                 return ret;
6710
6711         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6712                                          &filter_5tuple);
6713         if (filter != NULL && add) {
6714                 PMD_DRV_LOG(ERR, "filter exists.");
6715                 return -EEXIST;
6716         }
6717         if (filter == NULL && !add) {
6718                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6719                 return -ENOENT;
6720         }
6721
6722         if (add) {
6723                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6724                                 sizeof(struct ixgbe_5tuple_filter), 0);
6725                 if (filter == NULL)
6726                         return -ENOMEM;
6727                 rte_memcpy(&filter->filter_info,
6728                                  &filter_5tuple,
6729                                  sizeof(struct ixgbe_5tuple_filter_info));
6730                 filter->queue = ntuple_filter->queue;
6731                 ret = ixgbe_add_5tuple_filter(dev, filter);
6732                 if (ret < 0) {
6733                         rte_free(filter);
6734                         return ret;
6735                 }
6736         } else
6737                 ixgbe_remove_5tuple_filter(dev, filter);
6738
6739         return 0;
6740 }
6741
6742 /*
6743  * get a ntuple filter
6744  *
6745  * @param
6746  * dev: Pointer to struct rte_eth_dev.
6747  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6748  *
6749  * @return
6750  *    - On success, zero.
6751  *    - On failure, a negative value.
6752  */
6753 static int
6754 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6755                         struct rte_eth_ntuple_filter *ntuple_filter)
6756 {
6757         struct ixgbe_filter_info *filter_info =
6758                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6759         struct ixgbe_5tuple_filter_info filter_5tuple;
6760         struct ixgbe_5tuple_filter *filter;
6761         int ret;
6762
6763         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6764                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6765                 return -EINVAL;
6766         }
6767
6768         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6769         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6770         if (ret < 0)
6771                 return ret;
6772
6773         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6774                                          &filter_5tuple);
6775         if (filter == NULL) {
6776                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6777                 return -ENOENT;
6778         }
6779         ntuple_filter->queue = filter->queue;
6780         return 0;
6781 }
6782
6783 /*
6784  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6785  * @dev: pointer to rte_eth_dev structure
6786  * @filter_op:operation will be taken.
6787  * @arg: a pointer to specific structure corresponding to the filter_op
6788  *
6789  * @return
6790  *    - On success, zero.
6791  *    - On failure, a negative value.
6792  */
6793 static int
6794 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6795                                 enum rte_filter_op filter_op,
6796                                 void *arg)
6797 {
6798         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6799         int ret;
6800
6801         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6802
6803         if (filter_op == RTE_ETH_FILTER_NOP)
6804                 return 0;
6805
6806         if (arg == NULL) {
6807                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6808                             filter_op);
6809                 return -EINVAL;
6810         }
6811
6812         switch (filter_op) {
6813         case RTE_ETH_FILTER_ADD:
6814                 ret = ixgbe_add_del_ntuple_filter(dev,
6815                         (struct rte_eth_ntuple_filter *)arg,
6816                         TRUE);
6817                 break;
6818         case RTE_ETH_FILTER_DELETE:
6819                 ret = ixgbe_add_del_ntuple_filter(dev,
6820                         (struct rte_eth_ntuple_filter *)arg,
6821                         FALSE);
6822                 break;
6823         case RTE_ETH_FILTER_GET:
6824                 ret = ixgbe_get_ntuple_filter(dev,
6825                         (struct rte_eth_ntuple_filter *)arg);
6826                 break;
6827         default:
6828                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6829                 ret = -EINVAL;
6830                 break;
6831         }
6832         return ret;
6833 }
6834
6835 int
6836 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6837                         struct rte_eth_ethertype_filter *filter,
6838                         bool add)
6839 {
6840         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6841         struct ixgbe_filter_info *filter_info =
6842                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6843         uint32_t etqf = 0;
6844         uint32_t etqs = 0;
6845         int ret;
6846         struct ixgbe_ethertype_filter ethertype_filter;
6847
6848         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6849                 return -EINVAL;
6850
6851         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6852                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6853                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6854                         " ethertype filter.", filter->ether_type);
6855                 return -EINVAL;
6856         }
6857
6858         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6859                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6860                 return -EINVAL;
6861         }
6862         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6863                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6864                 return -EINVAL;
6865         }
6866
6867         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6868         if (ret >= 0 && add) {
6869                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6870                             filter->ether_type);
6871                 return -EEXIST;
6872         }
6873         if (ret < 0 && !add) {
6874                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6875                             filter->ether_type);
6876                 return -ENOENT;
6877         }
6878
6879         if (add) {
6880                 etqf = IXGBE_ETQF_FILTER_EN;
6881                 etqf |= (uint32_t)filter->ether_type;
6882                 etqs |= (uint32_t)((filter->queue <<
6883                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6884                                     IXGBE_ETQS_RX_QUEUE);
6885                 etqs |= IXGBE_ETQS_QUEUE_EN;
6886
6887                 ethertype_filter.ethertype = filter->ether_type;
6888                 ethertype_filter.etqf = etqf;
6889                 ethertype_filter.etqs = etqs;
6890                 ethertype_filter.conf = FALSE;
6891                 ret = ixgbe_ethertype_filter_insert(filter_info,
6892                                                     &ethertype_filter);
6893                 if (ret < 0) {
6894                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6895                         return -ENOSPC;
6896                 }
6897         } else {
6898                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6899                 if (ret < 0)
6900                         return -ENOSYS;
6901         }
6902         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6903         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6904         IXGBE_WRITE_FLUSH(hw);
6905
6906         return 0;
6907 }
6908
6909 static int
6910 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6911                      enum rte_filter_type filter_type,
6912                      enum rte_filter_op filter_op,
6913                      void *arg)
6914 {
6915         int ret = 0;
6916
6917         switch (filter_type) {
6918         case RTE_ETH_FILTER_NTUPLE:
6919                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6920                 break;
6921         case RTE_ETH_FILTER_FDIR:
6922                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6923                 break;
6924         case RTE_ETH_FILTER_L2_TUNNEL:
6925                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6926                 break;
6927         case RTE_ETH_FILTER_GENERIC:
6928                 if (filter_op != RTE_ETH_FILTER_GET)
6929                         return -EINVAL;
6930                 *(const void **)arg = &ixgbe_flow_ops;
6931                 break;
6932         default:
6933                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6934                                                         filter_type);
6935                 ret = -EINVAL;
6936                 break;
6937         }
6938
6939         return ret;
6940 }
6941
6942 static u8 *
6943 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
6944                         u8 **mc_addr_ptr, u32 *vmdq)
6945 {
6946         u8 *mc_addr;
6947
6948         *vmdq = 0;
6949         mc_addr = *mc_addr_ptr;
6950         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6951         return mc_addr;
6952 }
6953
6954 static int
6955 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6956                           struct rte_ether_addr *mc_addr_set,
6957                           uint32_t nb_mc_addr)
6958 {
6959         struct ixgbe_hw *hw;
6960         u8 *mc_addr_list;
6961
6962         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6963         mc_addr_list = (u8 *)mc_addr_set;
6964         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6965                                          ixgbe_dev_addr_list_itr, TRUE);
6966 }
6967
6968 static uint64_t
6969 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6970 {
6971         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6972         uint64_t systime_cycles;
6973
6974         switch (hw->mac.type) {
6975         case ixgbe_mac_X550:
6976         case ixgbe_mac_X550EM_x:
6977         case ixgbe_mac_X550EM_a:
6978                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6979                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6980                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6981                                 * NSEC_PER_SEC;
6982                 break;
6983         default:
6984                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6985                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6986                                 << 32;
6987         }
6988
6989         return systime_cycles;
6990 }
6991
6992 static uint64_t
6993 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6994 {
6995         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6996         uint64_t rx_tstamp_cycles;
6997
6998         switch (hw->mac.type) {
6999         case ixgbe_mac_X550:
7000         case ixgbe_mac_X550EM_x:
7001         case ixgbe_mac_X550EM_a:
7002                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7003                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7004                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7005                                 * NSEC_PER_SEC;
7006                 break;
7007         default:
7008                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7009                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7010                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7011                                 << 32;
7012         }
7013
7014         return rx_tstamp_cycles;
7015 }
7016
7017 static uint64_t
7018 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7019 {
7020         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7021         uint64_t tx_tstamp_cycles;
7022
7023         switch (hw->mac.type) {
7024         case ixgbe_mac_X550:
7025         case ixgbe_mac_X550EM_x:
7026         case ixgbe_mac_X550EM_a:
7027                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7028                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7029                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7030                                 * NSEC_PER_SEC;
7031                 break;
7032         default:
7033                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7034                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7035                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7036                                 << 32;
7037         }
7038
7039         return tx_tstamp_cycles;
7040 }
7041
7042 static void
7043 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7044 {
7045         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7046         struct ixgbe_adapter *adapter = dev->data->dev_private;
7047         struct rte_eth_link link;
7048         uint32_t incval = 0;
7049         uint32_t shift = 0;
7050
7051         /* Get current link speed. */
7052         ixgbe_dev_link_update(dev, 1);
7053         rte_eth_linkstatus_get(dev, &link);
7054
7055         switch (link.link_speed) {
7056         case ETH_SPEED_NUM_100M:
7057                 incval = IXGBE_INCVAL_100;
7058                 shift = IXGBE_INCVAL_SHIFT_100;
7059                 break;
7060         case ETH_SPEED_NUM_1G:
7061                 incval = IXGBE_INCVAL_1GB;
7062                 shift = IXGBE_INCVAL_SHIFT_1GB;
7063                 break;
7064         case ETH_SPEED_NUM_10G:
7065         default:
7066                 incval = IXGBE_INCVAL_10GB;
7067                 shift = IXGBE_INCVAL_SHIFT_10GB;
7068                 break;
7069         }
7070
7071         switch (hw->mac.type) {
7072         case ixgbe_mac_X550:
7073         case ixgbe_mac_X550EM_x:
7074         case ixgbe_mac_X550EM_a:
7075                 /* Independent of link speed. */
7076                 incval = 1;
7077                 /* Cycles read will be interpreted as ns. */
7078                 shift = 0;
7079                 /* Fall-through */
7080         case ixgbe_mac_X540:
7081                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7082                 break;
7083         case ixgbe_mac_82599EB:
7084                 incval >>= IXGBE_INCVAL_SHIFT_82599;
7085                 shift -= IXGBE_INCVAL_SHIFT_82599;
7086                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7087                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7088                 break;
7089         default:
7090                 /* Not supported. */
7091                 return;
7092         }
7093
7094         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7095         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7096         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7097
7098         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7099         adapter->systime_tc.cc_shift = shift;
7100         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7101
7102         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7103         adapter->rx_tstamp_tc.cc_shift = shift;
7104         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7105
7106         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7107         adapter->tx_tstamp_tc.cc_shift = shift;
7108         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7109 }
7110
7111 static int
7112 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7113 {
7114         struct ixgbe_adapter *adapter = dev->data->dev_private;
7115
7116         adapter->systime_tc.nsec += delta;
7117         adapter->rx_tstamp_tc.nsec += delta;
7118         adapter->tx_tstamp_tc.nsec += delta;
7119
7120         return 0;
7121 }
7122
7123 static int
7124 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7125 {
7126         uint64_t ns;
7127         struct ixgbe_adapter *adapter = dev->data->dev_private;
7128
7129         ns = rte_timespec_to_ns(ts);
7130         /* Set the timecounters to a new value. */
7131         adapter->systime_tc.nsec = ns;
7132         adapter->rx_tstamp_tc.nsec = ns;
7133         adapter->tx_tstamp_tc.nsec = ns;
7134
7135         return 0;
7136 }
7137
7138 static int
7139 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7140 {
7141         uint64_t ns, systime_cycles;
7142         struct ixgbe_adapter *adapter = dev->data->dev_private;
7143
7144         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7145         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7146         *ts = rte_ns_to_timespec(ns);
7147
7148         return 0;
7149 }
7150
7151 static int
7152 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7153 {
7154         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7155         uint32_t tsync_ctl;
7156         uint32_t tsauxc;
7157
7158         /* Stop the timesync system time. */
7159         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7160         /* Reset the timesync system time value. */
7161         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7162         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7163
7164         /* Enable system time for platforms where it isn't on by default. */
7165         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7166         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7167         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7168
7169         ixgbe_start_timecounters(dev);
7170
7171         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7172         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7173                         (RTE_ETHER_TYPE_1588 |
7174                          IXGBE_ETQF_FILTER_EN |
7175                          IXGBE_ETQF_1588));
7176
7177         /* Enable timestamping of received PTP packets. */
7178         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7179         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7180         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7181
7182         /* Enable timestamping of transmitted PTP packets. */
7183         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7184         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7185         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7186
7187         IXGBE_WRITE_FLUSH(hw);
7188
7189         return 0;
7190 }
7191
7192 static int
7193 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7194 {
7195         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7196         uint32_t tsync_ctl;
7197
7198         /* Disable timestamping of transmitted PTP packets. */
7199         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7200         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7201         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7202
7203         /* Disable timestamping of received PTP packets. */
7204         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7205         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7206         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7207
7208         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7209         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7210
7211         /* Stop incrementating the System Time registers. */
7212         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7213
7214         return 0;
7215 }
7216
7217 static int
7218 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7219                                  struct timespec *timestamp,
7220                                  uint32_t flags __rte_unused)
7221 {
7222         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7223         struct ixgbe_adapter *adapter = dev->data->dev_private;
7224         uint32_t tsync_rxctl;
7225         uint64_t rx_tstamp_cycles;
7226         uint64_t ns;
7227
7228         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7229         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7230                 return -EINVAL;
7231
7232         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7233         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7234         *timestamp = rte_ns_to_timespec(ns);
7235
7236         return  0;
7237 }
7238
7239 static int
7240 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7241                                  struct timespec *timestamp)
7242 {
7243         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7244         struct ixgbe_adapter *adapter = dev->data->dev_private;
7245         uint32_t tsync_txctl;
7246         uint64_t tx_tstamp_cycles;
7247         uint64_t ns;
7248
7249         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7250         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7251                 return -EINVAL;
7252
7253         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7254         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7255         *timestamp = rte_ns_to_timespec(ns);
7256
7257         return 0;
7258 }
7259
7260 static int
7261 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7262 {
7263         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7264         int count = 0;
7265         int g_ind = 0;
7266         const struct reg_info *reg_group;
7267         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7268                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7269
7270         while ((reg_group = reg_set[g_ind++]))
7271                 count += ixgbe_regs_group_count(reg_group);
7272
7273         return count;
7274 }
7275
7276 static int
7277 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7278 {
7279         int count = 0;
7280         int g_ind = 0;
7281         const struct reg_info *reg_group;
7282
7283         while ((reg_group = ixgbevf_regs[g_ind++]))
7284                 count += ixgbe_regs_group_count(reg_group);
7285
7286         return count;
7287 }
7288
7289 static int
7290 ixgbe_get_regs(struct rte_eth_dev *dev,
7291               struct rte_dev_reg_info *regs)
7292 {
7293         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7294         uint32_t *data = regs->data;
7295         int g_ind = 0;
7296         int count = 0;
7297         const struct reg_info *reg_group;
7298         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7299                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7300
7301         if (data == NULL) {
7302                 regs->length = ixgbe_get_reg_length(dev);
7303                 regs->width = sizeof(uint32_t);
7304                 return 0;
7305         }
7306
7307         /* Support only full register dump */
7308         if ((regs->length == 0) ||
7309             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7310                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7311                         hw->device_id;
7312                 while ((reg_group = reg_set[g_ind++]))
7313                         count += ixgbe_read_regs_group(dev, &data[count],
7314                                 reg_group);
7315                 return 0;
7316         }
7317
7318         return -ENOTSUP;
7319 }
7320
7321 static int
7322 ixgbevf_get_regs(struct rte_eth_dev *dev,
7323                 struct rte_dev_reg_info *regs)
7324 {
7325         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7326         uint32_t *data = regs->data;
7327         int g_ind = 0;
7328         int count = 0;
7329         const struct reg_info *reg_group;
7330
7331         if (data == NULL) {
7332                 regs->length = ixgbevf_get_reg_length(dev);
7333                 regs->width = sizeof(uint32_t);
7334                 return 0;
7335         }
7336
7337         /* Support only full register dump */
7338         if ((regs->length == 0) ||
7339             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7340                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7341                         hw->device_id;
7342                 while ((reg_group = ixgbevf_regs[g_ind++]))
7343                         count += ixgbe_read_regs_group(dev, &data[count],
7344                                                       reg_group);
7345                 return 0;
7346         }
7347
7348         return -ENOTSUP;
7349 }
7350
7351 static int
7352 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7353 {
7354         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7355
7356         /* Return unit is byte count */
7357         return hw->eeprom.word_size * 2;
7358 }
7359
7360 static int
7361 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7362                 struct rte_dev_eeprom_info *in_eeprom)
7363 {
7364         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7365         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7366         uint16_t *data = in_eeprom->data;
7367         int first, length;
7368
7369         first = in_eeprom->offset >> 1;
7370         length = in_eeprom->length >> 1;
7371         if ((first > hw->eeprom.word_size) ||
7372             ((first + length) > hw->eeprom.word_size))
7373                 return -EINVAL;
7374
7375         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7376
7377         return eeprom->ops.read_buffer(hw, first, length, data);
7378 }
7379
7380 static int
7381 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7382                 struct rte_dev_eeprom_info *in_eeprom)
7383 {
7384         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7385         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7386         uint16_t *data = in_eeprom->data;
7387         int first, length;
7388
7389         first = in_eeprom->offset >> 1;
7390         length = in_eeprom->length >> 1;
7391         if ((first > hw->eeprom.word_size) ||
7392             ((first + length) > hw->eeprom.word_size))
7393                 return -EINVAL;
7394
7395         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7396
7397         return eeprom->ops.write_buffer(hw,  first, length, data);
7398 }
7399
7400 static int
7401 ixgbe_get_module_info(struct rte_eth_dev *dev,
7402                       struct rte_eth_dev_module_info *modinfo)
7403 {
7404         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7405         uint32_t status;
7406         uint8_t sff8472_rev, addr_mode;
7407         bool page_swap = false;
7408
7409         /* Check whether we support SFF-8472 or not */
7410         status = hw->phy.ops.read_i2c_eeprom(hw,
7411                                              IXGBE_SFF_SFF_8472_COMP,
7412                                              &sff8472_rev);
7413         if (status != 0)
7414                 return -EIO;
7415
7416         /* addressing mode is not supported */
7417         status = hw->phy.ops.read_i2c_eeprom(hw,
7418                                              IXGBE_SFF_SFF_8472_SWAP,
7419                                              &addr_mode);
7420         if (status != 0)
7421                 return -EIO;
7422
7423         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7424                 PMD_DRV_LOG(ERR,
7425                             "Address change required to access page 0xA2, "
7426                             "but not supported. Please report the module "
7427                             "type to the driver maintainers.");
7428                 page_swap = true;
7429         }
7430
7431         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7432                 /* We have a SFP, but it does not support SFF-8472 */
7433                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7434                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7435         } else {
7436                 /* We have a SFP which supports a revision of SFF-8472. */
7437                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7438                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7439         }
7440
7441         return 0;
7442 }
7443
7444 static int
7445 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7446                         struct rte_dev_eeprom_info *info)
7447 {
7448         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7449         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7450         uint8_t databyte = 0xFF;
7451         uint8_t *data = info->data;
7452         uint32_t i = 0;
7453
7454         if (info->length == 0)
7455                 return -EINVAL;
7456
7457         for (i = info->offset; i < info->offset + info->length; i++) {
7458                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7459                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7460                 else
7461                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7462
7463                 if (status != 0)
7464                         return -EIO;
7465
7466                 data[i - info->offset] = databyte;
7467         }
7468
7469         return 0;
7470 }
7471
7472 uint16_t
7473 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7474         switch (mac_type) {
7475         case ixgbe_mac_X550:
7476         case ixgbe_mac_X550EM_x:
7477         case ixgbe_mac_X550EM_a:
7478                 return ETH_RSS_RETA_SIZE_512;
7479         case ixgbe_mac_X550_vf:
7480         case ixgbe_mac_X550EM_x_vf:
7481         case ixgbe_mac_X550EM_a_vf:
7482                 return ETH_RSS_RETA_SIZE_64;
7483         case ixgbe_mac_X540_vf:
7484         case ixgbe_mac_82599_vf:
7485                 return 0;
7486         default:
7487                 return ETH_RSS_RETA_SIZE_128;
7488         }
7489 }
7490
7491 uint32_t
7492 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7493         switch (mac_type) {
7494         case ixgbe_mac_X550:
7495         case ixgbe_mac_X550EM_x:
7496         case ixgbe_mac_X550EM_a:
7497                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7498                         return IXGBE_RETA(reta_idx >> 2);
7499                 else
7500                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7501         case ixgbe_mac_X550_vf:
7502         case ixgbe_mac_X550EM_x_vf:
7503         case ixgbe_mac_X550EM_a_vf:
7504                 return IXGBE_VFRETA(reta_idx >> 2);
7505         default:
7506                 return IXGBE_RETA(reta_idx >> 2);
7507         }
7508 }
7509
7510 uint32_t
7511 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7512         switch (mac_type) {
7513         case ixgbe_mac_X550_vf:
7514         case ixgbe_mac_X550EM_x_vf:
7515         case ixgbe_mac_X550EM_a_vf:
7516                 return IXGBE_VFMRQC;
7517         default:
7518                 return IXGBE_MRQC;
7519         }
7520 }
7521
7522 uint32_t
7523 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7524         switch (mac_type) {
7525         case ixgbe_mac_X550_vf:
7526         case ixgbe_mac_X550EM_x_vf:
7527         case ixgbe_mac_X550EM_a_vf:
7528                 return IXGBE_VFRSSRK(i);
7529         default:
7530                 return IXGBE_RSSRK(i);
7531         }
7532 }
7533
7534 bool
7535 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7536         switch (mac_type) {
7537         case ixgbe_mac_82599_vf:
7538         case ixgbe_mac_X540_vf:
7539                 return 0;
7540         default:
7541                 return 1;
7542         }
7543 }
7544
7545 static int
7546 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7547                         struct rte_eth_dcb_info *dcb_info)
7548 {
7549         struct ixgbe_dcb_config *dcb_config =
7550                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7551         struct ixgbe_dcb_tc_config *tc;
7552         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7553         uint8_t nb_tcs;
7554         uint8_t i, j;
7555
7556         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7557                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7558         else
7559                 dcb_info->nb_tcs = 1;
7560
7561         tc_queue = &dcb_info->tc_queue;
7562         nb_tcs = dcb_info->nb_tcs;
7563
7564         if (dcb_config->vt_mode) { /* vt is enabled*/
7565                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7566                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7567                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7568                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7569                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7570                         for (j = 0; j < nb_tcs; j++) {
7571                                 tc_queue->tc_rxq[0][j].base = j;
7572                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7573                                 tc_queue->tc_txq[0][j].base = j;
7574                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7575                         }
7576                 } else {
7577                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7578                                 for (j = 0; j < nb_tcs; j++) {
7579                                         tc_queue->tc_rxq[i][j].base =
7580                                                 i * nb_tcs + j;
7581                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7582                                         tc_queue->tc_txq[i][j].base =
7583                                                 i * nb_tcs + j;
7584                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7585                                 }
7586                         }
7587                 }
7588         } else { /* vt is disabled*/
7589                 struct rte_eth_dcb_rx_conf *rx_conf =
7590                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7591                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7592                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7593                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7594                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7595                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7596                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7597                         }
7598                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7599                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7600                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7601                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7602                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7603                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7604                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7605                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7606                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7607                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7608                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7609                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7610                         }
7611                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7612                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7613                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7614                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7615                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7616                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7617                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7618                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7619                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7620                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7621                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7622                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7623                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7624                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7625                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7626                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7627                 }
7628         }
7629         for (i = 0; i < dcb_info->nb_tcs; i++) {
7630                 tc = &dcb_config->tc_config[i];
7631                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7632         }
7633         return 0;
7634 }
7635
7636 /* Update e-tag ether type */
7637 static int
7638 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7639                             uint16_t ether_type)
7640 {
7641         uint32_t etag_etype;
7642
7643         if (hw->mac.type != ixgbe_mac_X550 &&
7644             hw->mac.type != ixgbe_mac_X550EM_x &&
7645             hw->mac.type != ixgbe_mac_X550EM_a) {
7646                 return -ENOTSUP;
7647         }
7648
7649         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7650         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7651         etag_etype |= ether_type;
7652         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7653         IXGBE_WRITE_FLUSH(hw);
7654
7655         return 0;
7656 }
7657
7658 /* Config l2 tunnel ether type */
7659 static int
7660 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7661                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7662 {
7663         int ret = 0;
7664         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7665         struct ixgbe_l2_tn_info *l2_tn_info =
7666                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7667
7668         if (l2_tunnel == NULL)
7669                 return -EINVAL;
7670
7671         switch (l2_tunnel->l2_tunnel_type) {
7672         case RTE_L2_TUNNEL_TYPE_E_TAG:
7673                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7674                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7675                 break;
7676         default:
7677                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7678                 ret = -EINVAL;
7679                 break;
7680         }
7681
7682         return ret;
7683 }
7684
7685 /* Enable e-tag tunnel */
7686 static int
7687 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7688 {
7689         uint32_t etag_etype;
7690
7691         if (hw->mac.type != ixgbe_mac_X550 &&
7692             hw->mac.type != ixgbe_mac_X550EM_x &&
7693             hw->mac.type != ixgbe_mac_X550EM_a) {
7694                 return -ENOTSUP;
7695         }
7696
7697         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7698         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7699         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7700         IXGBE_WRITE_FLUSH(hw);
7701
7702         return 0;
7703 }
7704
7705 /* Enable l2 tunnel */
7706 static int
7707 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7708                            enum rte_eth_tunnel_type l2_tunnel_type)
7709 {
7710         int ret = 0;
7711         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7712         struct ixgbe_l2_tn_info *l2_tn_info =
7713                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7714
7715         switch (l2_tunnel_type) {
7716         case RTE_L2_TUNNEL_TYPE_E_TAG:
7717                 l2_tn_info->e_tag_en = TRUE;
7718                 ret = ixgbe_e_tag_enable(hw);
7719                 break;
7720         default:
7721                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7722                 ret = -EINVAL;
7723                 break;
7724         }
7725
7726         return ret;
7727 }
7728
7729 /* Disable e-tag tunnel */
7730 static int
7731 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7732 {
7733         uint32_t etag_etype;
7734
7735         if (hw->mac.type != ixgbe_mac_X550 &&
7736             hw->mac.type != ixgbe_mac_X550EM_x &&
7737             hw->mac.type != ixgbe_mac_X550EM_a) {
7738                 return -ENOTSUP;
7739         }
7740
7741         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7742         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7743         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7744         IXGBE_WRITE_FLUSH(hw);
7745
7746         return 0;
7747 }
7748
7749 /* Disable l2 tunnel */
7750 static int
7751 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7752                             enum rte_eth_tunnel_type l2_tunnel_type)
7753 {
7754         int ret = 0;
7755         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7756         struct ixgbe_l2_tn_info *l2_tn_info =
7757                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7758
7759         switch (l2_tunnel_type) {
7760         case RTE_L2_TUNNEL_TYPE_E_TAG:
7761                 l2_tn_info->e_tag_en = FALSE;
7762                 ret = ixgbe_e_tag_disable(hw);
7763                 break;
7764         default:
7765                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7766                 ret = -EINVAL;
7767                 break;
7768         }
7769
7770         return ret;
7771 }
7772
7773 static int
7774 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7775                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7776 {
7777         int ret = 0;
7778         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7779         uint32_t i, rar_entries;
7780         uint32_t rar_low, rar_high;
7781
7782         if (hw->mac.type != ixgbe_mac_X550 &&
7783             hw->mac.type != ixgbe_mac_X550EM_x &&
7784             hw->mac.type != ixgbe_mac_X550EM_a) {
7785                 return -ENOTSUP;
7786         }
7787
7788         rar_entries = ixgbe_get_num_rx_addrs(hw);
7789
7790         for (i = 1; i < rar_entries; i++) {
7791                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7792                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7793                 if ((rar_high & IXGBE_RAH_AV) &&
7794                     (rar_high & IXGBE_RAH_ADTYPE) &&
7795                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7796                      l2_tunnel->tunnel_id)) {
7797                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7798                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7799
7800                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7801
7802                         return ret;
7803                 }
7804         }
7805
7806         return ret;
7807 }
7808
7809 static int
7810 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7811                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7812 {
7813         int ret = 0;
7814         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7815         uint32_t i, rar_entries;
7816         uint32_t rar_low, rar_high;
7817
7818         if (hw->mac.type != ixgbe_mac_X550 &&
7819             hw->mac.type != ixgbe_mac_X550EM_x &&
7820             hw->mac.type != ixgbe_mac_X550EM_a) {
7821                 return -ENOTSUP;
7822         }
7823
7824         /* One entry for one tunnel. Try to remove potential existing entry. */
7825         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7826
7827         rar_entries = ixgbe_get_num_rx_addrs(hw);
7828
7829         for (i = 1; i < rar_entries; i++) {
7830                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7831                 if (rar_high & IXGBE_RAH_AV) {
7832                         continue;
7833                 } else {
7834                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7835                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7836                         rar_low = l2_tunnel->tunnel_id;
7837
7838                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7839                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7840
7841                         return ret;
7842                 }
7843         }
7844
7845         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7846                      " Please remove a rule before adding a new one.");
7847         return -EINVAL;
7848 }
7849
7850 static inline struct ixgbe_l2_tn_filter *
7851 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7852                           struct ixgbe_l2_tn_key *key)
7853 {
7854         int ret;
7855
7856         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7857         if (ret < 0)
7858                 return NULL;
7859
7860         return l2_tn_info->hash_map[ret];
7861 }
7862
7863 static inline int
7864 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7865                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7866 {
7867         int ret;
7868
7869         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7870                                &l2_tn_filter->key);
7871
7872         if (ret < 0) {
7873                 PMD_DRV_LOG(ERR,
7874                             "Failed to insert L2 tunnel filter"
7875                             " to hash table %d!",
7876                             ret);
7877                 return ret;
7878         }
7879
7880         l2_tn_info->hash_map[ret] = l2_tn_filter;
7881
7882         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7883
7884         return 0;
7885 }
7886
7887 static inline int
7888 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7889                           struct ixgbe_l2_tn_key *key)
7890 {
7891         int ret;
7892         struct ixgbe_l2_tn_filter *l2_tn_filter;
7893
7894         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7895
7896         if (ret < 0) {
7897                 PMD_DRV_LOG(ERR,
7898                             "No such L2 tunnel filter to delete %d!",
7899                             ret);
7900                 return ret;
7901         }
7902
7903         l2_tn_filter = l2_tn_info->hash_map[ret];
7904         l2_tn_info->hash_map[ret] = NULL;
7905
7906         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7907         rte_free(l2_tn_filter);
7908
7909         return 0;
7910 }
7911
7912 /* Add l2 tunnel filter */
7913 int
7914 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7915                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7916                                bool restore)
7917 {
7918         int ret;
7919         struct ixgbe_l2_tn_info *l2_tn_info =
7920                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7921         struct ixgbe_l2_tn_key key;
7922         struct ixgbe_l2_tn_filter *node;
7923
7924         if (!restore) {
7925                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7926                 key.tn_id = l2_tunnel->tunnel_id;
7927
7928                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7929
7930                 if (node) {
7931                         PMD_DRV_LOG(ERR,
7932                                     "The L2 tunnel filter already exists!");
7933                         return -EINVAL;
7934                 }
7935
7936                 node = rte_zmalloc("ixgbe_l2_tn",
7937                                    sizeof(struct ixgbe_l2_tn_filter),
7938                                    0);
7939                 if (!node)
7940                         return -ENOMEM;
7941
7942                 rte_memcpy(&node->key,
7943                                  &key,
7944                                  sizeof(struct ixgbe_l2_tn_key));
7945                 node->pool = l2_tunnel->pool;
7946                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7947                 if (ret < 0) {
7948                         rte_free(node);
7949                         return ret;
7950                 }
7951         }
7952
7953         switch (l2_tunnel->l2_tunnel_type) {
7954         case RTE_L2_TUNNEL_TYPE_E_TAG:
7955                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7956                 break;
7957         default:
7958                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7959                 ret = -EINVAL;
7960                 break;
7961         }
7962
7963         if ((!restore) && (ret < 0))
7964                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7965
7966         return ret;
7967 }
7968
7969 /* Delete l2 tunnel filter */
7970 int
7971 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7972                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7973 {
7974         int ret;
7975         struct ixgbe_l2_tn_info *l2_tn_info =
7976                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7977         struct ixgbe_l2_tn_key key;
7978
7979         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7980         key.tn_id = l2_tunnel->tunnel_id;
7981         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7982         if (ret < 0)
7983                 return ret;
7984
7985         switch (l2_tunnel->l2_tunnel_type) {
7986         case RTE_L2_TUNNEL_TYPE_E_TAG:
7987                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7988                 break;
7989         default:
7990                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7991                 ret = -EINVAL;
7992                 break;
7993         }
7994
7995         return ret;
7996 }
7997
7998 /**
7999  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8000  * @dev: pointer to rte_eth_dev structure
8001  * @filter_op:operation will be taken.
8002  * @arg: a pointer to specific structure corresponding to the filter_op
8003  */
8004 static int
8005 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8006                                   enum rte_filter_op filter_op,
8007                                   void *arg)
8008 {
8009         int ret;
8010
8011         if (filter_op == RTE_ETH_FILTER_NOP)
8012                 return 0;
8013
8014         if (arg == NULL) {
8015                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8016                             filter_op);
8017                 return -EINVAL;
8018         }
8019
8020         switch (filter_op) {
8021         case RTE_ETH_FILTER_ADD:
8022                 ret = ixgbe_dev_l2_tunnel_filter_add
8023                         (dev,
8024                          (struct rte_eth_l2_tunnel_conf *)arg,
8025                          FALSE);
8026                 break;
8027         case RTE_ETH_FILTER_DELETE:
8028                 ret = ixgbe_dev_l2_tunnel_filter_del
8029                         (dev,
8030                          (struct rte_eth_l2_tunnel_conf *)arg);
8031                 break;
8032         default:
8033                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8034                 ret = -EINVAL;
8035                 break;
8036         }
8037         return ret;
8038 }
8039
8040 static int
8041 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8042 {
8043         int ret = 0;
8044         uint32_t ctrl;
8045         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8046
8047         if (hw->mac.type != ixgbe_mac_X550 &&
8048             hw->mac.type != ixgbe_mac_X550EM_x &&
8049             hw->mac.type != ixgbe_mac_X550EM_a) {
8050                 return -ENOTSUP;
8051         }
8052
8053         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8054         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8055         if (en)
8056                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8057         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8058
8059         return ret;
8060 }
8061
8062 /* Enable l2 tunnel forwarding */
8063 static int
8064 ixgbe_dev_l2_tunnel_forwarding_enable
8065         (struct rte_eth_dev *dev,
8066          enum rte_eth_tunnel_type l2_tunnel_type)
8067 {
8068         struct ixgbe_l2_tn_info *l2_tn_info =
8069                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8070         int ret = 0;
8071
8072         switch (l2_tunnel_type) {
8073         case RTE_L2_TUNNEL_TYPE_E_TAG:
8074                 l2_tn_info->e_tag_fwd_en = TRUE;
8075                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8076                 break;
8077         default:
8078                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8079                 ret = -EINVAL;
8080                 break;
8081         }
8082
8083         return ret;
8084 }
8085
8086 /* Disable l2 tunnel forwarding */
8087 static int
8088 ixgbe_dev_l2_tunnel_forwarding_disable
8089         (struct rte_eth_dev *dev,
8090          enum rte_eth_tunnel_type l2_tunnel_type)
8091 {
8092         struct ixgbe_l2_tn_info *l2_tn_info =
8093                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8094         int ret = 0;
8095
8096         switch (l2_tunnel_type) {
8097         case RTE_L2_TUNNEL_TYPE_E_TAG:
8098                 l2_tn_info->e_tag_fwd_en = FALSE;
8099                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8100                 break;
8101         default:
8102                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8103                 ret = -EINVAL;
8104                 break;
8105         }
8106
8107         return ret;
8108 }
8109
8110 static int
8111 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8112                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
8113                              bool en)
8114 {
8115         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8116         int ret = 0;
8117         uint32_t vmtir, vmvir;
8118         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8119
8120         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8121                 PMD_DRV_LOG(ERR,
8122                             "VF id %u should be less than %u",
8123                             l2_tunnel->vf_id,
8124                             pci_dev->max_vfs);
8125                 return -EINVAL;
8126         }
8127
8128         if (hw->mac.type != ixgbe_mac_X550 &&
8129             hw->mac.type != ixgbe_mac_X550EM_x &&
8130             hw->mac.type != ixgbe_mac_X550EM_a) {
8131                 return -ENOTSUP;
8132         }
8133
8134         if (en)
8135                 vmtir = l2_tunnel->tunnel_id;
8136         else
8137                 vmtir = 0;
8138
8139         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8140
8141         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8142         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8143         if (en)
8144                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8145         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8146
8147         return ret;
8148 }
8149
8150 /* Enable l2 tunnel tag insertion */
8151 static int
8152 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8153                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8154 {
8155         int ret = 0;
8156
8157         switch (l2_tunnel->l2_tunnel_type) {
8158         case RTE_L2_TUNNEL_TYPE_E_TAG:
8159                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8160                 break;
8161         default:
8162                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8163                 ret = -EINVAL;
8164                 break;
8165         }
8166
8167         return ret;
8168 }
8169
8170 /* Disable l2 tunnel tag insertion */
8171 static int
8172 ixgbe_dev_l2_tunnel_insertion_disable
8173         (struct rte_eth_dev *dev,
8174          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8175 {
8176         int ret = 0;
8177
8178         switch (l2_tunnel->l2_tunnel_type) {
8179         case RTE_L2_TUNNEL_TYPE_E_TAG:
8180                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8181                 break;
8182         default:
8183                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8184                 ret = -EINVAL;
8185                 break;
8186         }
8187
8188         return ret;
8189 }
8190
8191 static int
8192 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8193                              bool en)
8194 {
8195         int ret = 0;
8196         uint32_t qde;
8197         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8198
8199         if (hw->mac.type != ixgbe_mac_X550 &&
8200             hw->mac.type != ixgbe_mac_X550EM_x &&
8201             hw->mac.type != ixgbe_mac_X550EM_a) {
8202                 return -ENOTSUP;
8203         }
8204
8205         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8206         if (en)
8207                 qde |= IXGBE_QDE_STRIP_TAG;
8208         else
8209                 qde &= ~IXGBE_QDE_STRIP_TAG;
8210         qde &= ~IXGBE_QDE_READ;
8211         qde |= IXGBE_QDE_WRITE;
8212         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8213
8214         return ret;
8215 }
8216
8217 /* Enable l2 tunnel tag stripping */
8218 static int
8219 ixgbe_dev_l2_tunnel_stripping_enable
8220         (struct rte_eth_dev *dev,
8221          enum rte_eth_tunnel_type l2_tunnel_type)
8222 {
8223         int ret = 0;
8224
8225         switch (l2_tunnel_type) {
8226         case RTE_L2_TUNNEL_TYPE_E_TAG:
8227                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8228                 break;
8229         default:
8230                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8231                 ret = -EINVAL;
8232                 break;
8233         }
8234
8235         return ret;
8236 }
8237
8238 /* Disable l2 tunnel tag stripping */
8239 static int
8240 ixgbe_dev_l2_tunnel_stripping_disable
8241         (struct rte_eth_dev *dev,
8242          enum rte_eth_tunnel_type l2_tunnel_type)
8243 {
8244         int ret = 0;
8245
8246         switch (l2_tunnel_type) {
8247         case RTE_L2_TUNNEL_TYPE_E_TAG:
8248                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8249                 break;
8250         default:
8251                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8252                 ret = -EINVAL;
8253                 break;
8254         }
8255
8256         return ret;
8257 }
8258
8259 /* Enable/disable l2 tunnel offload functions */
8260 static int
8261 ixgbe_dev_l2_tunnel_offload_set
8262         (struct rte_eth_dev *dev,
8263          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8264          uint32_t mask,
8265          uint8_t en)
8266 {
8267         int ret = 0;
8268
8269         if (l2_tunnel == NULL)
8270                 return -EINVAL;
8271
8272         ret = -EINVAL;
8273         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8274                 if (en)
8275                         ret = ixgbe_dev_l2_tunnel_enable(
8276                                 dev,
8277                                 l2_tunnel->l2_tunnel_type);
8278                 else
8279                         ret = ixgbe_dev_l2_tunnel_disable(
8280                                 dev,
8281                                 l2_tunnel->l2_tunnel_type);
8282         }
8283
8284         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8285                 if (en)
8286                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8287                                 dev,
8288                                 l2_tunnel);
8289                 else
8290                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8291                                 dev,
8292                                 l2_tunnel);
8293         }
8294
8295         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8296                 if (en)
8297                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8298                                 dev,
8299                                 l2_tunnel->l2_tunnel_type);
8300                 else
8301                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8302                                 dev,
8303                                 l2_tunnel->l2_tunnel_type);
8304         }
8305
8306         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8307                 if (en)
8308                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8309                                 dev,
8310                                 l2_tunnel->l2_tunnel_type);
8311                 else
8312                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8313                                 dev,
8314                                 l2_tunnel->l2_tunnel_type);
8315         }
8316
8317         return ret;
8318 }
8319
8320 static int
8321 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8322                         uint16_t port)
8323 {
8324         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8325         IXGBE_WRITE_FLUSH(hw);
8326
8327         return 0;
8328 }
8329
8330 /* There's only one register for VxLAN UDP port.
8331  * So, we cannot add several ports. Will update it.
8332  */
8333 static int
8334 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8335                      uint16_t port)
8336 {
8337         if (port == 0) {
8338                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8339                 return -EINVAL;
8340         }
8341
8342         return ixgbe_update_vxlan_port(hw, port);
8343 }
8344
8345 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8346  * UDP port, it must have a value.
8347  * So, will reset it to the original value 0.
8348  */
8349 static int
8350 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8351                      uint16_t port)
8352 {
8353         uint16_t cur_port;
8354
8355         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8356
8357         if (cur_port != port) {
8358                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8359                 return -EINVAL;
8360         }
8361
8362         return ixgbe_update_vxlan_port(hw, 0);
8363 }
8364
8365 /* Add UDP tunneling port */
8366 static int
8367 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8368                               struct rte_eth_udp_tunnel *udp_tunnel)
8369 {
8370         int ret = 0;
8371         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8372
8373         if (hw->mac.type != ixgbe_mac_X550 &&
8374             hw->mac.type != ixgbe_mac_X550EM_x &&
8375             hw->mac.type != ixgbe_mac_X550EM_a) {
8376                 return -ENOTSUP;
8377         }
8378
8379         if (udp_tunnel == NULL)
8380                 return -EINVAL;
8381
8382         switch (udp_tunnel->prot_type) {
8383         case RTE_TUNNEL_TYPE_VXLAN:
8384                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8385                 break;
8386
8387         case RTE_TUNNEL_TYPE_GENEVE:
8388         case RTE_TUNNEL_TYPE_TEREDO:
8389                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8390                 ret = -EINVAL;
8391                 break;
8392
8393         default:
8394                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8395                 ret = -EINVAL;
8396                 break;
8397         }
8398
8399         return ret;
8400 }
8401
8402 /* Remove UDP tunneling port */
8403 static int
8404 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8405                               struct rte_eth_udp_tunnel *udp_tunnel)
8406 {
8407         int ret = 0;
8408         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8409
8410         if (hw->mac.type != ixgbe_mac_X550 &&
8411             hw->mac.type != ixgbe_mac_X550EM_x &&
8412             hw->mac.type != ixgbe_mac_X550EM_a) {
8413                 return -ENOTSUP;
8414         }
8415
8416         if (udp_tunnel == NULL)
8417                 return -EINVAL;
8418
8419         switch (udp_tunnel->prot_type) {
8420         case RTE_TUNNEL_TYPE_VXLAN:
8421                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8422                 break;
8423         case RTE_TUNNEL_TYPE_GENEVE:
8424         case RTE_TUNNEL_TYPE_TEREDO:
8425                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8426                 ret = -EINVAL;
8427                 break;
8428         default:
8429                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8430                 ret = -EINVAL;
8431                 break;
8432         }
8433
8434         return ret;
8435 }
8436
8437 static int
8438 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8439 {
8440         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8441         int ret;
8442
8443         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8444         case IXGBE_SUCCESS:
8445                 ret = 0;
8446                 break;
8447         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8448                 ret = -ENOTSUP;
8449                 break;
8450         default:
8451                 ret = -EAGAIN;
8452                 break;
8453         }
8454
8455         return ret;
8456 }
8457
8458 static int
8459 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8460 {
8461         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8462         int ret;
8463
8464         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8465         case IXGBE_SUCCESS:
8466                 ret = 0;
8467                 break;
8468         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8469                 ret = -ENOTSUP;
8470                 break;
8471         default:
8472                 ret = -EAGAIN;
8473                 break;
8474         }
8475
8476         return ret;
8477 }
8478
8479 static int
8480 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8481 {
8482         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8483         int ret;
8484         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8485
8486         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8487         case IXGBE_SUCCESS:
8488                 ret = 0;
8489                 break;
8490         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8491                 ret = -ENOTSUP;
8492                 break;
8493         default:
8494                 ret = -EAGAIN;
8495                 break;
8496         }
8497
8498         return ret;
8499 }
8500
8501 static int
8502 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8503 {
8504         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8505         int ret;
8506
8507         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8508         case IXGBE_SUCCESS:
8509                 ret = 0;
8510                 break;
8511         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8512                 ret = -ENOTSUP;
8513                 break;
8514         default:
8515                 ret = -EAGAIN;
8516                 break;
8517         }
8518
8519         return ret;
8520 }
8521
8522 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8523 {
8524         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8525         u32 in_msg = 0;
8526
8527         /* peek the message first */
8528         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8529
8530         /* PF reset VF event */
8531         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8532                 /* dummy mbx read to ack pf */
8533                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8534                         return;
8535                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8536                                              NULL);
8537         }
8538 }
8539
8540 static int
8541 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8542 {
8543         uint32_t eicr;
8544         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8545         struct ixgbe_interrupt *intr =
8546                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8547         ixgbevf_intr_disable(dev);
8548
8549         /* read-on-clear nic registers here */
8550         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8551         intr->flags = 0;
8552
8553         /* only one misc vector supported - mailbox */
8554         eicr &= IXGBE_VTEICR_MASK;
8555         if (eicr == IXGBE_MISC_VEC_ID)
8556                 intr->flags |= IXGBE_FLAG_MAILBOX;
8557
8558         return 0;
8559 }
8560
8561 static int
8562 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8563 {
8564         struct ixgbe_interrupt *intr =
8565                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8566
8567         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8568                 ixgbevf_mbx_process(dev);
8569                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8570         }
8571
8572         ixgbevf_intr_enable(dev);
8573
8574         return 0;
8575 }
8576
8577 static void
8578 ixgbevf_dev_interrupt_handler(void *param)
8579 {
8580         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8581
8582         ixgbevf_dev_interrupt_get_status(dev);
8583         ixgbevf_dev_interrupt_action(dev);
8584 }
8585
8586 /**
8587  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8588  *  @hw: pointer to hardware structure
8589  *
8590  *  Stops the transmit data path and waits for the HW to internally empty
8591  *  the Tx security block
8592  **/
8593 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8594 {
8595 #define IXGBE_MAX_SECTX_POLL 40
8596
8597         int i;
8598         int sectxreg;
8599
8600         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8601         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8602         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8603         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8604                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8605                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8606                         break;
8607                 /* Use interrupt-safe sleep just in case */
8608                 usec_delay(1000);
8609         }
8610
8611         /* For informational purposes only */
8612         if (i >= IXGBE_MAX_SECTX_POLL)
8613                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8614                          "path fully disabled.  Continuing with init.");
8615
8616         return IXGBE_SUCCESS;
8617 }
8618
8619 /**
8620  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8621  *  @hw: pointer to hardware structure
8622  *
8623  *  Enables the transmit data path.
8624  **/
8625 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8626 {
8627         uint32_t sectxreg;
8628
8629         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8630         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8631         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8632         IXGBE_WRITE_FLUSH(hw);
8633
8634         return IXGBE_SUCCESS;
8635 }
8636
8637 /* restore n-tuple filter */
8638 static inline void
8639 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8640 {
8641         struct ixgbe_filter_info *filter_info =
8642                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8643         struct ixgbe_5tuple_filter *node;
8644
8645         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8646                 ixgbe_inject_5tuple_filter(dev, node);
8647         }
8648 }
8649
8650 /* restore ethernet type filter */
8651 static inline void
8652 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8653 {
8654         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8655         struct ixgbe_filter_info *filter_info =
8656                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8657         int i;
8658
8659         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8660                 if (filter_info->ethertype_mask & (1 << i)) {
8661                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8662                                         filter_info->ethertype_filters[i].etqf);
8663                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8664                                         filter_info->ethertype_filters[i].etqs);
8665                         IXGBE_WRITE_FLUSH(hw);
8666                 }
8667         }
8668 }
8669
8670 /* restore SYN filter */
8671 static inline void
8672 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8673 {
8674         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8675         struct ixgbe_filter_info *filter_info =
8676                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8677         uint32_t synqf;
8678
8679         synqf = filter_info->syn_info;
8680
8681         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8682                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8683                 IXGBE_WRITE_FLUSH(hw);
8684         }
8685 }
8686
8687 /* restore L2 tunnel filter */
8688 static inline void
8689 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8690 {
8691         struct ixgbe_l2_tn_info *l2_tn_info =
8692                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8693         struct ixgbe_l2_tn_filter *node;
8694         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8695
8696         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8697                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8698                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8699                 l2_tn_conf.pool           = node->pool;
8700                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8701         }
8702 }
8703
8704 /* restore rss filter */
8705 static inline void
8706 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8707 {
8708         struct ixgbe_filter_info *filter_info =
8709                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8710
8711         if (filter_info->rss_info.conf.queue_num)
8712                 ixgbe_config_rss_filter(dev,
8713                         &filter_info->rss_info, TRUE);
8714 }
8715
8716 static int
8717 ixgbe_filter_restore(struct rte_eth_dev *dev)
8718 {
8719         ixgbe_ntuple_filter_restore(dev);
8720         ixgbe_ethertype_filter_restore(dev);
8721         ixgbe_syn_filter_restore(dev);
8722         ixgbe_fdir_filter_restore(dev);
8723         ixgbe_l2_tn_filter_restore(dev);
8724         ixgbe_rss_filter_restore(dev);
8725
8726         return 0;
8727 }
8728
8729 static void
8730 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8731 {
8732         struct ixgbe_l2_tn_info *l2_tn_info =
8733                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8734         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8735
8736         if (l2_tn_info->e_tag_en)
8737                 (void)ixgbe_e_tag_enable(hw);
8738
8739         if (l2_tn_info->e_tag_fwd_en)
8740                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8741
8742         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8743 }
8744
8745 /* remove all the n-tuple filters */
8746 void
8747 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8748 {
8749         struct ixgbe_filter_info *filter_info =
8750                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8751         struct ixgbe_5tuple_filter *p_5tuple;
8752
8753         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8754                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8755 }
8756
8757 /* remove all the ether type filters */
8758 void
8759 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8760 {
8761         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8762         struct ixgbe_filter_info *filter_info =
8763                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8764         int i;
8765
8766         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8767                 if (filter_info->ethertype_mask & (1 << i) &&
8768                     !filter_info->ethertype_filters[i].conf) {
8769                         (void)ixgbe_ethertype_filter_remove(filter_info,
8770                                                             (uint8_t)i);
8771                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8772                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8773                         IXGBE_WRITE_FLUSH(hw);
8774                 }
8775         }
8776 }
8777
8778 /* remove the SYN filter */
8779 void
8780 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8781 {
8782         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8783         struct ixgbe_filter_info *filter_info =
8784                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8785
8786         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8787                 filter_info->syn_info = 0;
8788
8789                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8790                 IXGBE_WRITE_FLUSH(hw);
8791         }
8792 }
8793
8794 /* remove all the L2 tunnel filters */
8795 int
8796 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8797 {
8798         struct ixgbe_l2_tn_info *l2_tn_info =
8799                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8800         struct ixgbe_l2_tn_filter *l2_tn_filter;
8801         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8802         int ret = 0;
8803
8804         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8805                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8806                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8807                 l2_tn_conf.pool           = l2_tn_filter->pool;
8808                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8809                 if (ret < 0)
8810                         return ret;
8811         }
8812
8813         return 0;
8814 }
8815
8816 void
8817 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8818                                 struct ixgbe_macsec_setting *macsec_setting)
8819 {
8820         struct ixgbe_macsec_setting *macsec =
8821                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8822
8823         macsec->offload_en = macsec_setting->offload_en;
8824         macsec->encrypt_en = macsec_setting->encrypt_en;
8825         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8826 }
8827
8828 void
8829 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8830 {
8831         struct ixgbe_macsec_setting *macsec =
8832                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8833
8834         macsec->offload_en = 0;
8835         macsec->encrypt_en = 0;
8836         macsec->replayprotect_en = 0;
8837 }
8838
8839 void
8840 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8841                                 struct ixgbe_macsec_setting *macsec_setting)
8842 {
8843         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8844         uint32_t ctrl;
8845         uint8_t en = macsec_setting->encrypt_en;
8846         uint8_t rp = macsec_setting->replayprotect_en;
8847
8848         /**
8849          * Workaround:
8850          * As no ixgbe_disable_sec_rx_path equivalent is
8851          * implemented for tx in the base code, and we are
8852          * not allowed to modify the base code in DPDK, so
8853          * just call the hand-written one directly for now.
8854          * The hardware support has been checked by
8855          * ixgbe_disable_sec_rx_path().
8856          */
8857         ixgbe_disable_sec_tx_path_generic(hw);
8858
8859         /* Enable Ethernet CRC (required by MACsec offload) */
8860         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8861         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8862         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8863
8864         /* Enable the TX and RX crypto engines */
8865         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8866         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8867         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8868
8869         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8870         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8871         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8872
8873         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8874         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8875         ctrl |= 0x3;
8876         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8877
8878         /* Enable SA lookup */
8879         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8880         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8881         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8882                      IXGBE_LSECTXCTRL_AUTH;
8883         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8884         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8885         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8886         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8887
8888         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8889         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8890         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8891         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8892         if (rp)
8893                 ctrl |= IXGBE_LSECRXCTRL_RP;
8894         else
8895                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8896         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8897
8898         /* Start the data paths */
8899         ixgbe_enable_sec_rx_path(hw);
8900         /**
8901          * Workaround:
8902          * As no ixgbe_enable_sec_rx_path equivalent is
8903          * implemented for tx in the base code, and we are
8904          * not allowed to modify the base code in DPDK, so
8905          * just call the hand-written one directly for now.
8906          */
8907         ixgbe_enable_sec_tx_path_generic(hw);
8908 }
8909
8910 void
8911 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
8912 {
8913         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8914         uint32_t ctrl;
8915
8916         /**
8917          * Workaround:
8918          * As no ixgbe_disable_sec_rx_path equivalent is
8919          * implemented for tx in the base code, and we are
8920          * not allowed to modify the base code in DPDK, so
8921          * just call the hand-written one directly for now.
8922          * The hardware support has been checked by
8923          * ixgbe_disable_sec_rx_path().
8924          */
8925         ixgbe_disable_sec_tx_path_generic(hw);
8926
8927         /* Disable the TX and RX crypto engines */
8928         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8929         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8930         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8931
8932         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8933         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8934         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8935
8936         /* Disable SA lookup */
8937         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8938         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8939         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8940         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8941
8942         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8943         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8944         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8945         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8946
8947         /* Start the data paths */
8948         ixgbe_enable_sec_rx_path(hw);
8949         /**
8950          * Workaround:
8951          * As no ixgbe_enable_sec_rx_path equivalent is
8952          * implemented for tx in the base code, and we are
8953          * not allowed to modify the base code in DPDK, so
8954          * just call the hand-written one directly for now.
8955          */
8956         ixgbe_enable_sec_tx_path_generic(hw);
8957 }
8958
8959 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8960 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8961 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8962 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8963 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8964 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8965 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
8966                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
8967
8968 RTE_LOG_REGISTER(ixgbe_logtype_init, pmd.net.ixgbe.init, NOTICE);
8969 RTE_LOG_REGISTER(ixgbe_logtype_driver, pmd.net.ixgbe.driver, NOTICE);
8970
8971 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
8972 RTE_LOG_REGISTER(ixgbe_logtype_rx, pmd.net.ixgbe.rx, DEBUG);
8973 #endif
8974 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
8975 RTE_LOG_REGISTER(ixgbe_logtype_tx, pmd.net.ixgbe.tx, DEBUG);
8976 #endif
8977 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
8978 RTE_LOG_REGISTER(ixgbe_logtype_tx_free, pmd.net.ixgbe.tx_free, DEBUG);
8979 #endif