drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIBRTE_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static int  ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
 233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
 234                                               uint32_t timeout_ms);
 235
 236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 237                         struct rte_ether_addr *mac_addr,
 238                         uint32_t index, uint32_t pool);
 239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 241                                            struct rte_ether_addr *mac_addr);
 242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 243 static bool is_device_supported(struct rte_eth_dev *dev,
 244                                 struct rte_pci_driver *drv);
 245
 246 /* For Virtual Function support */
 247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 250 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 252                                    int wait_to_complete);
 253 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 254 static int ixgbevf_dev_close(struct rte_eth_dev *dev);
 255 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 259                 struct rte_eth_stats *stats);
 260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 262                 uint16_t vlan_id, int on);
 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 264                 uint16_t queue, int on);
 265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 269                                             uint16_t queue_id);
 270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 271                                              uint16_t queue_id);
 272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 273                                  uint8_t queue, uint8_t msix_vector);
 274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 rte_ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 285                 struct rte_eth_mirror_conf *mirror_conf,
 286                 uint8_t rule_id, uint8_t on);
 287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 288                 uint8_t rule_id);
 289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 290                                           uint16_t queue_id);
 291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 292                                            uint16_t queue_id);
 293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 294                                uint8_t queue, uint8_t msix_vector);
 295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 296
 297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 298                                 struct rte_ether_addr *mac_addr,
 299                                 uint32_t index, uint32_t pool);
 300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 302                                              struct rte_ether_addr *mac_addr);
 303 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 304                         struct rte_eth_syn_filter *filter);
 305 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 306                         enum rte_filter_op filter_op,
 307                         void *arg);
 308 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 309                         struct ixgbe_5tuple_filter *filter);
 310 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 311                         struct ixgbe_5tuple_filter *filter);
 312 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 313                                 enum rte_filter_op filter_op,
 314                                 void *arg);
 315 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 316                         struct rte_eth_ntuple_filter *filter);
 317 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 318                                 enum rte_filter_op filter_op,
 319                                 void *arg);
 320 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 321                         struct rte_eth_ethertype_filter *filter);
 322 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 323                      enum rte_filter_type filter_type,
 324                      enum rte_filter_op filter_op,
 325                      void *arg);
 326 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 327
 328 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 329                                       struct rte_ether_addr *mc_addr_set,
 330                                       uint32_t nb_mc_addr);
 331 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 332                                    struct rte_eth_dcb_info *dcb_info);
 333
 334 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 335 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 336                             struct rte_dev_reg_info *regs);
 337 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 338 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 339                                 struct rte_dev_eeprom_info *eeprom);
 340 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 341                                 struct rte_dev_eeprom_info *eeprom);
 342
 343 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 344                                  struct rte_eth_dev_module_info *modinfo);
 345 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 346                                    struct rte_dev_eeprom_info *info);
 347
 348 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 349 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 350                                 struct rte_dev_reg_info *regs);
 351
 352 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 354 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 355                                             struct timespec *timestamp,
 356                                             uint32_t flags);
 357 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 358                                             struct timespec *timestamp);
 359 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 360 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 361                                    struct timespec *timestamp);
 362 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 363                                    const struct timespec *timestamp);
 364 static void ixgbevf_dev_interrupt_handler(void *param);
 365
 366 static int ixgbe_dev_l2_tunnel_eth_type_conf
 367         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 368 static int ixgbe_dev_l2_tunnel_offload_set
 369         (struct rte_eth_dev *dev,
 370          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 371          uint32_t mask,
 372          uint8_t en);
 373 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 374                                              enum rte_filter_op filter_op,
 375                                              void *arg);
 376
 377 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 380                                          struct rte_eth_udp_tunnel *udp_tunnel);
 381 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 382 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 383 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
 384
 385 /*
 386  * Define VF Stats MACRO for Non "cleared on read" register
 387  */
 388 #define UPDATE_VF_STAT(reg, last, cur)                          \
 389 {                                                               \
 390         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 391         cur += (latest - last) & UINT_MAX;                      \
 392         last = latest;                                          \
 393 }
 394
 395 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 396 {                                                                \
 397         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 398         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 399         u64 latest = ((new_msb << 32) | new_lsb);                \
 400         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 401         last = latest;                                           \
 402 }
 403
 404 #define IXGBE_SET_HWSTRIP(h, q) do {\
 405                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 406                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 407                 (h)->bitmap[idx] |= 1 << bit;\
 408         } while (0)
 409
 410 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 411                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 412                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 413                 (h)->bitmap[idx] &= ~(1 << bit);\
 414         } while (0)
 415
 416 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 417                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 418                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 419                 (r) = (h)->bitmap[idx] >> bit & 1;\
 420         } while (0)
 421
 422 /*
 423  * The set of PCI devices this driver supports
 424  */
 425 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 474 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 476 #endif
 477         { .vendor_id = 0, /* sentinel */ },
 478 };
 479
 480 /*
 481  * The set of PCI devices this driver supports (for 82599 VF)
 482  */
 483 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 492         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 494         { .vendor_id = 0, /* sentinel */ },
 495 };
 496
 497 static const struct rte_eth_desc_lim rx_desc_lim = {
 498         .nb_max = IXGBE_MAX_RING_DESC,
 499         .nb_min = IXGBE_MIN_RING_DESC,
 500         .nb_align = IXGBE_RXD_ALIGN,
 501 };
 502
 503 static const struct rte_eth_desc_lim tx_desc_lim = {
 504         .nb_max = IXGBE_MAX_RING_DESC,
 505         .nb_min = IXGBE_MIN_RING_DESC,
 506         .nb_align = IXGBE_TXD_ALIGN,
 507         .nb_seg_max = IXGBE_TX_MAX_SEG,
 508         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 509 };
 510
 511 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 512         .dev_configure        = ixgbe_dev_configure,
 513         .dev_start            = ixgbe_dev_start,
 514         .dev_stop             = ixgbe_dev_stop,
 515         .dev_set_link_up    = ixgbe_dev_set_link_up,
 516         .dev_set_link_down  = ixgbe_dev_set_link_down,
 517         .dev_close            = ixgbe_dev_close,
 518         .dev_reset            = ixgbe_dev_reset,
 519         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 520         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 521         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 522         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 523         .link_update          = ixgbe_dev_link_update,
 524         .stats_get            = ixgbe_dev_stats_get,
 525         .xstats_get           = ixgbe_dev_xstats_get,
 526         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 527         .stats_reset          = ixgbe_dev_stats_reset,
 528         .xstats_reset         = ixgbe_dev_xstats_reset,
 529         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 530         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 531         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 532         .fw_version_get       = ixgbe_fw_version_get,
 533         .dev_infos_get        = ixgbe_dev_info_get,
 534         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 535         .mtu_set              = ixgbe_dev_mtu_set,
 536         .vlan_filter_set      = ixgbe_vlan_filter_set,
 537         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 538         .vlan_offload_set     = ixgbe_vlan_offload_set,
 539         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 540         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 541         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 542         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 543         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 544         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 545         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 546         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 547         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 548         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 549         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 550         .dev_led_on           = ixgbe_dev_led_on,
 551         .dev_led_off          = ixgbe_dev_led_off,
 552         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 553         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 554         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 555         .mac_addr_add         = ixgbe_add_rar,
 556         .mac_addr_remove      = ixgbe_remove_rar,
 557         .mac_addr_set         = ixgbe_set_default_mac_addr,
 558         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 559         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 560         .mirror_rule_set      = ixgbe_mirror_rule_set,
 561         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 562         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 563         .reta_update          = ixgbe_dev_rss_reta_update,
 564         .reta_query           = ixgbe_dev_rss_reta_query,
 565         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 566         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 567         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 568         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 569         .rxq_info_get         = ixgbe_rxq_info_get,
 570         .txq_info_get         = ixgbe_txq_info_get,
 571         .timesync_enable      = ixgbe_timesync_enable,
 572         .timesync_disable     = ixgbe_timesync_disable,
 573         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 574         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 575         .get_reg              = ixgbe_get_regs,
 576         .get_eeprom_length    = ixgbe_get_eeprom_length,
 577         .get_eeprom           = ixgbe_get_eeprom,
 578         .set_eeprom           = ixgbe_set_eeprom,
 579         .get_module_info      = ixgbe_get_module_info,
 580         .get_module_eeprom    = ixgbe_get_module_eeprom,
 581         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 582         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 583         .timesync_read_time   = ixgbe_timesync_read_time,
 584         .timesync_write_time  = ixgbe_timesync_write_time,
 585         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 586         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 587         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 588         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 589         .tm_ops_get           = ixgbe_tm_ops_get,
 590         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 591 };
 592
 593 /*
 594  * dev_ops for virtual function, bare necessities for basic vf
 595  * operation have been implemented
 596  */
 597 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 598         .dev_configure        = ixgbevf_dev_configure,
 599         .dev_start            = ixgbevf_dev_start,
 600         .dev_stop             = ixgbevf_dev_stop,
 601         .link_update          = ixgbevf_dev_link_update,
 602         .stats_get            = ixgbevf_dev_stats_get,
 603         .xstats_get           = ixgbevf_dev_xstats_get,
 604         .stats_reset          = ixgbevf_dev_stats_reset,
 605         .xstats_reset         = ixgbevf_dev_stats_reset,
 606         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 607         .dev_close            = ixgbevf_dev_close,
 608         .dev_reset            = ixgbevf_dev_reset,
 609         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 610         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 611         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 612         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 613         .dev_infos_get        = ixgbevf_dev_info_get,
 614         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 615         .mtu_set              = ixgbevf_dev_set_mtu,
 616         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 617         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 618         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 619         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 620         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 621         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 622         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 623         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 624         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 625         .mac_addr_add         = ixgbevf_add_mac_addr,
 626         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 627         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 628         .rxq_info_get         = ixgbe_rxq_info_get,
 629         .txq_info_get         = ixgbe_txq_info_get,
 630         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 631         .get_reg              = ixgbevf_get_regs,
 632         .reta_update          = ixgbe_dev_rss_reta_update,
 633         .reta_query           = ixgbe_dev_rss_reta_query,
 634         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 635         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 636         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 637 };
 638
 639 /* store statistics names and its offset in stats structure */
 640 struct rte_ixgbe_xstats_name_off {
 641         char name[RTE_ETH_XSTATS_NAME_SIZE];
 642         unsigned offset;
 643 };
 644
 645 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 646         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 647         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 648         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 649         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 650         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 651         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 652         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 653         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 654         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 655         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 656         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 657         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 658         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 659         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 660         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 661                 prc1023)},
 662         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 663                 prc1522)},
 664         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 665         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 666         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 667         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 668         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 669         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 670         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 671         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 672         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 673         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 674         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 675         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 676         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 677         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 678         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 679         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 680         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 681                 ptc1023)},
 682         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 683                 ptc1522)},
 684         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 685         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 686         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 687         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 688
 689         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 690                 fdirustat_add)},
 691         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 692                 fdirustat_remove)},
 693         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 694                 fdirfstat_fadd)},
 695         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 696                 fdirfstat_fremove)},
 697         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 698                 fdirmatch)},
 699         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 700                 fdirmiss)},
 701
 702         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 703         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 704         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 705                 fclast)},
 706         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 707         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 708         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 709         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 710         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 711                 fcoe_noddp)},
 712         {"rx_fcoe_no_direct_data_placement_ext_buff",
 713                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 714
 715         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 716                 lxontxc)},
 717         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 718                 lxonrxc)},
 719         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 720                 lxofftxc)},
 721         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 722                 lxoffrxc)},
 723         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 724 };
 725
 726 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 727                            sizeof(rte_ixgbe_stats_strings[0]))
 728
 729 /* MACsec statistics */
 730 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 731         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 732                 out_pkts_untagged)},
 733         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 734                 out_pkts_encrypted)},
 735         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 736                 out_pkts_protected)},
 737         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 738                 out_octets_encrypted)},
 739         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 740                 out_octets_protected)},
 741         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 742                 in_pkts_untagged)},
 743         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 744                 in_pkts_badtag)},
 745         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 746                 in_pkts_nosci)},
 747         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_unknownsci)},
 749         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 750                 in_octets_decrypted)},
 751         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 752                 in_octets_validated)},
 753         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_unchecked)},
 755         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_delayed)},
 757         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_late)},
 759         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 760                 in_pkts_ok)},
 761         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 762                 in_pkts_invalid)},
 763         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 764                 in_pkts_notvalid)},
 765         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 766                 in_pkts_unusedsa)},
 767         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 768                 in_pkts_notusingsa)},
 769 };
 770
 771 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 772                            sizeof(rte_ixgbe_macsec_strings[0]))
 773
 774 /* Per-queue statistics */
 775 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 776         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 777         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 778         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 779         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 780 };
 781
 782 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 783                            sizeof(rte_ixgbe_rxq_strings[0]))
 784 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 785
 786 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 787         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 788         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 789         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 790                 pxon2offc)},
 791 };
 792
 793 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 794                            sizeof(rte_ixgbe_txq_strings[0]))
 795 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 796
 797 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 798         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 799 };
 800
 801 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 802                 sizeof(rte_ixgbevf_stats_strings[0]))
 803
 804 /*
 805  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 806  */
 807 static inline int
 808 ixgbe_is_sfp(struct ixgbe_hw *hw)
 809 {
 810         switch (hw->phy.type) {
 811         case ixgbe_phy_sfp_avago:
 812         case ixgbe_phy_sfp_ftl:
 813         case ixgbe_phy_sfp_intel:
 814         case ixgbe_phy_sfp_unknown:
 815         case ixgbe_phy_sfp_passive_tyco:
 816         case ixgbe_phy_sfp_passive_unknown:
 817                 return 1;
 818         default:
 819                 return 0;
 820         }
 821 }
 822
 823 static inline int32_t
 824 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 825 {
 826         uint32_t ctrl_ext;
 827         int32_t status;
 828
 829         status = ixgbe_reset_hw(hw);
 830
 831         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 832         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 833         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 834         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 835         IXGBE_WRITE_FLUSH(hw);
 836
 837         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 838                 status = IXGBE_SUCCESS;
 839         return status;
 840 }
 841
 842 static inline void
 843 ixgbe_enable_intr(struct rte_eth_dev *dev)
 844 {
 845         struct ixgbe_interrupt *intr =
 846                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 847         struct ixgbe_hw *hw =
 848                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 849
 850         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 851         IXGBE_WRITE_FLUSH(hw);
 852 }
 853
 854 /*
 855  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 856  */
 857 static void
 858 ixgbe_disable_intr(struct ixgbe_hw *hw)
 859 {
 860         PMD_INIT_FUNC_TRACE();
 861
 862         if (hw->mac.type == ixgbe_mac_82598EB) {
 863                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 864         } else {
 865                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 866                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 867                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 868         }
 869         IXGBE_WRITE_FLUSH(hw);
 870 }
 871
 872 /*
 873  * This function resets queue statistics mapping registers.
 874  * From Niantic datasheet, Initialization of Statistics section:
 875  * "...if software requires the queue counters, the RQSMR and TQSM registers
 876  * must be re-programmed following a device reset.
 877  */
 878 static void
 879 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 880 {
 881         uint32_t i;
 882
 883         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 884                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 885                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 886         }
 887 }
 888
 889
 890 static int
 891 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 892                                   uint16_t queue_id,
 893                                   uint8_t stat_idx,
 894                                   uint8_t is_rx)
 895 {
 896 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 897 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 898 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 899
 900         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 901         struct ixgbe_stat_mapping_registers *stat_mappings =
 902                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 903         uint32_t qsmr_mask = 0;
 904         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 905         uint32_t q_map;
 906         uint8_t n, offset;
 907
 908         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 909                 (hw->mac.type != ixgbe_mac_X540) &&
 910                 (hw->mac.type != ixgbe_mac_X550) &&
 911                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 912                 (hw->mac.type != ixgbe_mac_X550EM_a))
 913                 return -ENOSYS;
 914
 915         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 916                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 917                      queue_id, stat_idx);
 918
 919         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 920         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 921                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 922                 return -EIO;
 923         }
 924         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 925
 926         /* Now clear any previous stat_idx set */
 927         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 928         if (!is_rx)
 929                 stat_mappings->tqsm[n] &= ~clearing_mask;
 930         else
 931                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 932
 933         q_map = (uint32_t)stat_idx;
 934         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 935         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 936         if (!is_rx)
 937                 stat_mappings->tqsm[n] |= qsmr_mask;
 938         else
 939                 stat_mappings->rqsmr[n] |= qsmr_mask;
 940
 941         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 942                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 943                      queue_id, stat_idx);
 944         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 945                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 946
 947         /* Now write the mapping in the appropriate register */
 948         if (is_rx) {
 949                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 950                              stat_mappings->rqsmr[n], n);
 951                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 952         } else {
 953                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 954                              stat_mappings->tqsm[n], n);
 955                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 956         }
 957         return 0;
 958 }
 959
 960 static void
 961 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 962 {
 963         struct ixgbe_stat_mapping_registers *stat_mappings =
 964                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 965         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 966         int i;
 967
 968         /* write whatever was in stat mapping table to the NIC */
 969         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 970                 /* rx */
 971                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 972
 973                 /* tx */
 974                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 975         }
 976 }
 977
 978 static void
 979 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 980 {
 981         uint8_t i;
 982         struct ixgbe_dcb_tc_config *tc;
 983         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 984
 985         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 986         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 987         for (i = 0; i < dcb_max_tc; i++) {
 988                 tc = &dcb_config->tc_config[i];
 989                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 990                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 991                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 992                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 993                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 994                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 995                 tc->pfc = ixgbe_dcb_pfc_disabled;
 996         }
 997
 998         /* Initialize default user to priority mapping, UPx->TC0 */
 999         tc = &dcb_config->tc_config[0];
1000         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1001         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1002         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1003                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1004                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1005         }
1006         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1007         dcb_config->pfc_mode_enable = false;
1008         dcb_config->vt_mode = true;
1009         dcb_config->round_robin_enable = false;
1010         /* support all DCB capabilities in 82599 */
1011         dcb_config->support.capabilities = 0xFF;
1012
1013         /*we only support 4 Tcs for X540, X550 */
1014         if (hw->mac.type == ixgbe_mac_X540 ||
1015                 hw->mac.type == ixgbe_mac_X550 ||
1016                 hw->mac.type == ixgbe_mac_X550EM_x ||
1017                 hw->mac.type == ixgbe_mac_X550EM_a) {
1018                 dcb_config->num_tcs.pg_tcs = 4;
1019                 dcb_config->num_tcs.pfc_tcs = 4;
1020         }
1021 }
1022
1023 /*
1024  * Ensure that all locks are released before first NVM or PHY access
1025  */
1026 static void
1027 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1028 {
1029         uint16_t mask;
1030
1031         /*
1032          * Phy lock should not fail in this early stage. If this is the case,
1033          * it is due to an improper exit of the application.
1034          * So force the release of the faulty lock. Release of common lock
1035          * is done automatically by swfw_sync function.
1036          */
1037         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1038         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1039                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1040         }
1041         ixgbe_release_swfw_semaphore(hw, mask);
1042
1043         /*
1044          * These ones are more tricky since they are common to all ports; but
1045          * swfw_sync retries last long enough (1s) to be almost sure that if
1046          * lock can not be taken it is due to an improper lock of the
1047          * semaphore.
1048          */
1049         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1050         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1051                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1052         }
1053         ixgbe_release_swfw_semaphore(hw, mask);
1054 }
1055
1056 /*
1057  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1058  * It returns 0 on success.
1059  */
1060 static int
1061 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1062 {
1063         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1064         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1065         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1066         struct ixgbe_hw *hw =
1067                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1068         struct ixgbe_vfta *shadow_vfta =
1069                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1070         struct ixgbe_hwstrip *hwstrip =
1071                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1072         struct ixgbe_dcb_config *dcb_config =
1073                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1074         struct ixgbe_filter_info *filter_info =
1075                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1076         struct ixgbe_bw_conf *bw_conf =
1077                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1078         uint32_t ctrl_ext;
1079         uint16_t csum;
1080         int diag, i;
1081
1082         PMD_INIT_FUNC_TRACE();
1083
1084         ixgbe_dev_macsec_setting_reset(eth_dev);
1085
1086         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1087         eth_dev->rx_queue_count       = ixgbe_dev_rx_queue_count;
1088         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1089         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1090         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1091         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1092         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1093         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1094
1095         /*
1096          * For secondary processes, we don't initialise any further as primary
1097          * has already done this work. Only check we don't need a different
1098          * RX and TX function.
1099          */
1100         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1101                 struct ixgbe_tx_queue *txq;
1102                 /* TX queue function in primary, set by last queue initialized
1103                  * Tx queue may not initialized by primary process
1104                  */
1105                 if (eth_dev->data->tx_queues) {
1106                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1107                         ixgbe_set_tx_function(eth_dev, txq);
1108                 } else {
1109                         /* Use default TX function if we get here */
1110                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1111                                      "Using default TX function.");
1112                 }
1113
1114                 ixgbe_set_rx_function(eth_dev);
1115
1116                 return 0;
1117         }
1118
1119         rte_atomic32_clear(&ad->link_thread_running);
1120         rte_eth_copy_pci_info(eth_dev, pci_dev);
1121
1122         /* Vendor and Device ID need to be set before init of shared code */
1123         hw->device_id = pci_dev->id.device_id;
1124         hw->vendor_id = pci_dev->id.vendor_id;
1125         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1126         hw->allow_unsupported_sfp = 1;
1127
1128         /* Initialize the shared code (base driver) */
1129 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1130         diag = ixgbe_bypass_init_shared_code(hw);
1131 #else
1132         diag = ixgbe_init_shared_code(hw);
1133 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1134
1135         if (diag != IXGBE_SUCCESS) {
1136                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1137                 return -EIO;
1138         }
1139
1140         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1141                 PMD_INIT_LOG(ERR, "\nERROR: "
1142                         "Firmware recovery mode detected. Limiting functionality.\n"
1143                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1144                         "User Guide for details on firmware recovery mode.");
1145                 return -EIO;
1146         }
1147
1148         /* pick up the PCI bus settings for reporting later */
1149         ixgbe_get_bus_info(hw);
1150
1151         /* Unlock any pending hardware semaphore */
1152         ixgbe_swfw_lock_reset(hw);
1153
1154 #ifdef RTE_LIBRTE_SECURITY
1155         /* Initialize security_ctx only for primary process*/
1156         if (ixgbe_ipsec_ctx_create(eth_dev))
1157                 return -ENOMEM;
1158 #endif
1159
1160         /* Initialize DCB configuration*/
1161         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1162         ixgbe_dcb_init(hw, dcb_config);
1163         /* Get Hardware Flow Control setting */
1164         hw->fc.requested_mode = ixgbe_fc_none;
1165         hw->fc.current_mode = ixgbe_fc_none;
1166         hw->fc.pause_time = IXGBE_FC_PAUSE;
1167         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1168                 hw->fc.low_water[i] = IXGBE_FC_LO;
1169                 hw->fc.high_water[i] = IXGBE_FC_HI;
1170         }
1171         hw->fc.send_xon = 1;
1172
1173         /* Make sure we have a good EEPROM before we read from it */
1174         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1175         if (diag != IXGBE_SUCCESS) {
1176                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1177                 return -EIO;
1178         }
1179
1180 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1181         diag = ixgbe_bypass_init_hw(hw);
1182 #else
1183         diag = ixgbe_init_hw(hw);
1184 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1185
1186         /*
1187          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1188          * is called too soon after the kernel driver unbinding/binding occurs.
1189          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1190          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1191          * also called. See ixgbe_identify_phy_82599(). The reason for the
1192          * failure is not known, and only occuts when virtualisation features
1193          * are disabled in the bios. A delay of 100ms  was found to be enough by
1194          * trial-and-error, and is doubled to be safe.
1195          */
1196         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1197                 rte_delay_ms(200);
1198                 diag = ixgbe_init_hw(hw);
1199         }
1200
1201         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1202                 diag = IXGBE_SUCCESS;
1203
1204         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1205                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1206                              "LOM.  Please be aware there may be issues associated "
1207                              "with your hardware.");
1208                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1209                              "please contact your Intel or hardware representative "
1210                              "who provided you with this hardware.");
1211         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1212                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1213         if (diag) {
1214                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1215                 return -EIO;
1216         }
1217
1218         /* Reset the hw statistics */
1219         ixgbe_dev_stats_reset(eth_dev);
1220
1221         /* disable interrupt */
1222         ixgbe_disable_intr(hw);
1223
1224         /* reset mappings for queue statistics hw counters*/
1225         ixgbe_reset_qstat_mappings(hw);
1226
1227         /* Allocate memory for storing MAC addresses */
1228         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1229                                                hw->mac.num_rar_entries, 0);
1230         if (eth_dev->data->mac_addrs == NULL) {
1231                 PMD_INIT_LOG(ERR,
1232                              "Failed to allocate %u bytes needed to store "
1233                              "MAC addresses",
1234                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1235                 return -ENOMEM;
1236         }
1237         /* Copy the permanent MAC address */
1238         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1239                         &eth_dev->data->mac_addrs[0]);
1240
1241         /* Allocate memory for storing hash filter MAC addresses */
1242         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1243                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1244         if (eth_dev->data->hash_mac_addrs == NULL) {
1245                 PMD_INIT_LOG(ERR,
1246                              "Failed to allocate %d bytes needed to store MAC addresses",
1247                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1248                 return -ENOMEM;
1249         }
1250
1251         /* initialize the vfta */
1252         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1253
1254         /* initialize the hw strip bitmap*/
1255         memset(hwstrip, 0, sizeof(*hwstrip));
1256
1257         /* initialize PF if max_vfs not zero */
1258         ixgbe_pf_host_init(eth_dev);
1259
1260         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1261         /* let hardware know driver is loaded */
1262         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1263         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1264         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1265         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1266         IXGBE_WRITE_FLUSH(hw);
1267
1268         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1269                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1270                              (int) hw->mac.type, (int) hw->phy.type,
1271                              (int) hw->phy.sfp_type);
1272         else
1273                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1274                              (int) hw->mac.type, (int) hw->phy.type);
1275
1276         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1277                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1278                      pci_dev->id.device_id);
1279
1280         rte_intr_callback_register(intr_handle,
1281                                    ixgbe_dev_interrupt_handler, eth_dev);
1282
1283         /* enable uio/vfio intr/eventfd mapping */
1284         rte_intr_enable(intr_handle);
1285
1286         /* enable support intr */
1287         ixgbe_enable_intr(eth_dev);
1288
1289         /* initialize filter info */
1290         memset(filter_info, 0,
1291                sizeof(struct ixgbe_filter_info));
1292
1293         /* initialize 5tuple filter list */
1294         TAILQ_INIT(&filter_info->fivetuple_list);
1295
1296         /* initialize flow director filter list & hash */
1297         ixgbe_fdir_filter_init(eth_dev);
1298
1299         /* initialize l2 tunnel filter list & hash */
1300         ixgbe_l2_tn_filter_init(eth_dev);
1301
1302         /* initialize flow filter lists */
1303         ixgbe_filterlist_init();
1304
1305         /* initialize bandwidth configuration info */
1306         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1307
1308         /* initialize Traffic Manager configuration */
1309         ixgbe_tm_conf_init(eth_dev);
1310
1311         return 0;
1312 }
1313
1314 static int
1315 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1316 {
1317         PMD_INIT_FUNC_TRACE();
1318
1319         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1320                 return 0;
1321
1322         ixgbe_dev_close(eth_dev);
1323
1324         return 0;
1325 }
1326
1327 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1328 {
1329         struct ixgbe_filter_info *filter_info =
1330                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1331         struct ixgbe_5tuple_filter *p_5tuple;
1332
1333         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1334                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1335                              p_5tuple,
1336                              entries);
1337                 rte_free(p_5tuple);
1338         }
1339         memset(filter_info->fivetuple_mask, 0,
1340                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1341
1342         return 0;
1343 }
1344
1345 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1346 {
1347         struct ixgbe_hw_fdir_info *fdir_info =
1348                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1349         struct ixgbe_fdir_filter *fdir_filter;
1350
1351                 if (fdir_info->hash_map)
1352                 rte_free(fdir_info->hash_map);
1353         if (fdir_info->hash_handle)
1354                 rte_hash_free(fdir_info->hash_handle);
1355
1356         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1357                 TAILQ_REMOVE(&fdir_info->fdir_list,
1358                              fdir_filter,
1359                              entries);
1360                 rte_free(fdir_filter);
1361         }
1362
1363         return 0;
1364 }
1365
1366 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1367 {
1368         struct ixgbe_l2_tn_info *l2_tn_info =
1369                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1370         struct ixgbe_l2_tn_filter *l2_tn_filter;
1371
1372         if (l2_tn_info->hash_map)
1373                 rte_free(l2_tn_info->hash_map);
1374         if (l2_tn_info->hash_handle)
1375                 rte_hash_free(l2_tn_info->hash_handle);
1376
1377         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1378                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1379                              l2_tn_filter,
1380                              entries);
1381                 rte_free(l2_tn_filter);
1382         }
1383
1384         return 0;
1385 }
1386
1387 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1388 {
1389         struct ixgbe_hw_fdir_info *fdir_info =
1390                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1391         char fdir_hash_name[RTE_HASH_NAMESIZE];
1392         struct rte_hash_parameters fdir_hash_params = {
1393                 .name = fdir_hash_name,
1394                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1395                 .key_len = sizeof(union ixgbe_atr_input),
1396                 .hash_func = rte_hash_crc,
1397                 .hash_func_init_val = 0,
1398                 .socket_id = rte_socket_id(),
1399         };
1400
1401         TAILQ_INIT(&fdir_info->fdir_list);
1402         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1403                  "fdir_%s", eth_dev->device->name);
1404         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1405         if (!fdir_info->hash_handle) {
1406                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1407                 return -EINVAL;
1408         }
1409         fdir_info->hash_map = rte_zmalloc("ixgbe",
1410                                           sizeof(struct ixgbe_fdir_filter *) *
1411                                           IXGBE_MAX_FDIR_FILTER_NUM,
1412                                           0);
1413         if (!fdir_info->hash_map) {
1414                 PMD_INIT_LOG(ERR,
1415                              "Failed to allocate memory for fdir hash map!");
1416                 return -ENOMEM;
1417         }
1418         fdir_info->mask_added = FALSE;
1419
1420         return 0;
1421 }
1422
1423 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1424 {
1425         struct ixgbe_l2_tn_info *l2_tn_info =
1426                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1427         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1428         struct rte_hash_parameters l2_tn_hash_params = {
1429                 .name = l2_tn_hash_name,
1430                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1431                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1432                 .hash_func = rte_hash_crc,
1433                 .hash_func_init_val = 0,
1434                 .socket_id = rte_socket_id(),
1435         };
1436
1437         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1438         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1439                  "l2_tn_%s", eth_dev->device->name);
1440         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1441         if (!l2_tn_info->hash_handle) {
1442                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1443                 return -EINVAL;
1444         }
1445         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1446                                    sizeof(struct ixgbe_l2_tn_filter *) *
1447                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1448                                    0);
1449         if (!l2_tn_info->hash_map) {
1450                 PMD_INIT_LOG(ERR,
1451                         "Failed to allocate memory for L2 TN hash map!");
1452                 return -ENOMEM;
1453         }
1454         l2_tn_info->e_tag_en = FALSE;
1455         l2_tn_info->e_tag_fwd_en = FALSE;
1456         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1457
1458         return 0;
1459 }
1460 /*
1461  * Negotiate mailbox API version with the PF.
1462  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1463  * Then we try to negotiate starting with the most recent one.
1464  * If all negotiation attempts fail, then we will proceed with
1465  * the default one (ixgbe_mbox_api_10).
1466  */
1467 static void
1468 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1469 {
1470         int32_t i;
1471
1472         /* start with highest supported, proceed down */
1473         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1474                 ixgbe_mbox_api_13,
1475                 ixgbe_mbox_api_12,
1476                 ixgbe_mbox_api_11,
1477                 ixgbe_mbox_api_10,
1478         };
1479
1480         for (i = 0;
1481                         i != RTE_DIM(sup_ver) &&
1482                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1483                         i++)
1484                 ;
1485 }
1486
1487 static void
1488 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1489 {
1490         uint64_t random;
1491
1492         /* Set Organizationally Unique Identifier (OUI) prefix. */
1493         mac_addr->addr_bytes[0] = 0x00;
1494         mac_addr->addr_bytes[1] = 0x09;
1495         mac_addr->addr_bytes[2] = 0xC0;
1496         /* Force indication of locally assigned MAC address. */
1497         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1498         /* Generate the last 3 bytes of the MAC address with a random number. */
1499         random = rte_rand();
1500         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1501 }
1502
1503 static int
1504 devarg_handle_int(__rte_unused const char *key, const char *value,
1505                   void *extra_args)
1506 {
1507         uint16_t *n = extra_args;
1508
1509         if (value == NULL || extra_args == NULL)
1510                 return -EINVAL;
1511
1512         *n = (uint16_t)strtoul(value, NULL, 0);
1513         if (*n == USHRT_MAX && errno == ERANGE)
1514                 return -1;
1515
1516         return 0;
1517 }
1518
1519 static void
1520 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1521                       struct rte_devargs *devargs)
1522 {
1523         struct rte_kvargs *kvlist;
1524         uint16_t pflink_fullchk;
1525
1526         if (devargs == NULL)
1527                 return;
1528
1529         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1530         if (kvlist == NULL)
1531                 return;
1532
1533         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1534             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1535                                devarg_handle_int, &pflink_fullchk) == 0 &&
1536             pflink_fullchk == 1)
1537                 adapter->pflink_fullchk = 1;
1538
1539         rte_kvargs_free(kvlist);
1540 }
1541
1542 /*
1543  * Virtual Function device init
1544  */
1545 static int
1546 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1547 {
1548         int diag;
1549         uint32_t tc, tcs;
1550         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1551         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1552         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1553         struct ixgbe_hw *hw =
1554                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1555         struct ixgbe_vfta *shadow_vfta =
1556                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1557         struct ixgbe_hwstrip *hwstrip =
1558                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1559         struct rte_ether_addr *perm_addr =
1560                 (struct rte_ether_addr *)hw->mac.perm_addr;
1561
1562         PMD_INIT_FUNC_TRACE();
1563
1564         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1565         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1566         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1567         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1568         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1569         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1570
1571         /* for secondary processes, we don't initialise any further as primary
1572          * has already done this work. Only check we don't need a different
1573          * RX function
1574          */
1575         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1576                 struct ixgbe_tx_queue *txq;
1577                 /* TX queue function in primary, set by last queue initialized
1578                  * Tx queue may not initialized by primary process
1579                  */
1580                 if (eth_dev->data->tx_queues) {
1581                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1582                         ixgbe_set_tx_function(eth_dev, txq);
1583                 } else {
1584                         /* Use default TX function if we get here */
1585                         PMD_INIT_LOG(NOTICE,
1586                                      "No TX queues configured yet. Using default TX function.");
1587                 }
1588
1589                 ixgbe_set_rx_function(eth_dev);
1590
1591                 return 0;
1592         }
1593
1594         rte_atomic32_clear(&ad->link_thread_running);
1595         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1596                               pci_dev->device.devargs);
1597
1598         rte_eth_copy_pci_info(eth_dev, pci_dev);
1599
1600         hw->device_id = pci_dev->id.device_id;
1601         hw->vendor_id = pci_dev->id.vendor_id;
1602         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1603
1604         /* initialize the vfta */
1605         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1606
1607         /* initialize the hw strip bitmap*/
1608         memset(hwstrip, 0, sizeof(*hwstrip));
1609
1610         /* Initialize the shared code (base driver) */
1611         diag = ixgbe_init_shared_code(hw);
1612         if (diag != IXGBE_SUCCESS) {
1613                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1614                 return -EIO;
1615         }
1616
1617         /* init_mailbox_params */
1618         hw->mbx.ops.init_params(hw);
1619
1620         /* Reset the hw statistics */
1621         ixgbevf_dev_stats_reset(eth_dev);
1622
1623         /* Disable the interrupts for VF */
1624         ixgbevf_intr_disable(eth_dev);
1625
1626         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1627         diag = hw->mac.ops.reset_hw(hw);
1628
1629         /*
1630          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1631          * the underlying PF driver has not assigned a MAC address to the VF.
1632          * In this case, assign a random MAC address.
1633          */
1634         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1635                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1636                 /*
1637                  * This error code will be propagated to the app by
1638                  * rte_eth_dev_reset, so use a public error code rather than
1639                  * the internal-only IXGBE_ERR_RESET_FAILED
1640                  */
1641                 return -EAGAIN;
1642         }
1643
1644         /* negotiate mailbox API version to use with the PF. */
1645         ixgbevf_negotiate_api(hw);
1646
1647         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1648         ixgbevf_get_queues(hw, &tcs, &tc);
1649
1650         /* Allocate memory for storing MAC addresses */
1651         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1652                                                hw->mac.num_rar_entries, 0);
1653         if (eth_dev->data->mac_addrs == NULL) {
1654                 PMD_INIT_LOG(ERR,
1655                              "Failed to allocate %u bytes needed to store "
1656                              "MAC addresses",
1657                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1658                 return -ENOMEM;
1659         }
1660
1661         /* Generate a random MAC address, if none was assigned by PF. */
1662         if (rte_is_zero_ether_addr(perm_addr)) {
1663                 generate_random_mac_addr(perm_addr);
1664                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1665                 if (diag) {
1666                         rte_free(eth_dev->data->mac_addrs);
1667                         eth_dev->data->mac_addrs = NULL;
1668                         return diag;
1669                 }
1670                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1671                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1672                              "%02x:%02x:%02x:%02x:%02x:%02x",
1673                              perm_addr->addr_bytes[0],
1674                              perm_addr->addr_bytes[1],
1675                              perm_addr->addr_bytes[2],
1676                              perm_addr->addr_bytes[3],
1677                              perm_addr->addr_bytes[4],
1678                              perm_addr->addr_bytes[5]);
1679         }
1680
1681         /* Copy the permanent MAC address */
1682         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1683
1684         /* reset the hardware with the new settings */
1685         diag = hw->mac.ops.start_hw(hw);
1686         switch (diag) {
1687         case  0:
1688                 break;
1689
1690         default:
1691                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1692                 return -EIO;
1693         }
1694
1695         rte_intr_callback_register(intr_handle,
1696                                    ixgbevf_dev_interrupt_handler, eth_dev);
1697         rte_intr_enable(intr_handle);
1698         ixgbevf_intr_enable(eth_dev);
1699
1700         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1701                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1702                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1703
1704         return 0;
1705 }
1706
1707 /* Virtual Function device uninit */
1708
1709 static int
1710 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1711 {
1712         PMD_INIT_FUNC_TRACE();
1713
1714         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1715                 return 0;
1716
1717         ixgbevf_dev_close(eth_dev);
1718
1719         return 0;
1720 }
1721
1722 static int
1723 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1724                 struct rte_pci_device *pci_dev)
1725 {
1726         char name[RTE_ETH_NAME_MAX_LEN];
1727         struct rte_eth_dev *pf_ethdev;
1728         struct rte_eth_devargs eth_da;
1729         int i, retval;
1730
1731         if (pci_dev->device.devargs) {
1732                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1733                                 &eth_da);
1734                 if (retval)
1735                         return retval;
1736         } else
1737                 memset(&eth_da, 0, sizeof(eth_da));
1738
1739         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1740                 sizeof(struct ixgbe_adapter),
1741                 eth_dev_pci_specific_init, pci_dev,
1742                 eth_ixgbe_dev_init, NULL);
1743
1744         if (retval || eth_da.nb_representor_ports < 1)
1745                 return retval;
1746
1747         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1748         if (pf_ethdev == NULL)
1749                 return -ENODEV;
1750
1751         /* probe VF representor ports */
1752         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1753                 struct ixgbe_vf_info *vfinfo;
1754                 struct ixgbe_vf_representor representor;
1755
1756                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1757                         pf_ethdev->data->dev_private);
1758                 if (vfinfo == NULL) {
1759                         PMD_DRV_LOG(ERR,
1760                                 "no virtual functions supported by PF");
1761                         break;
1762                 }
1763
1764                 representor.vf_id = eth_da.representor_ports[i];
1765                 representor.switch_domain_id = vfinfo->switch_domain_id;
1766                 representor.pf_ethdev = pf_ethdev;
1767
1768                 /* representor port net_bdf_port */
1769                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1770                         pci_dev->device.name,
1771                         eth_da.representor_ports[i]);
1772
1773                 retval = rte_eth_dev_create(&pci_dev->device, name,
1774                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1775                         ixgbe_vf_representor_init, &representor);
1776
1777                 if (retval)
1778                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1779                                 "representor %s.", name);
1780         }
1781
1782         return 0;
1783 }
1784
1785 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1786 {
1787         struct rte_eth_dev *ethdev;
1788
1789         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1790         if (!ethdev)
1791                 return 0;
1792
1793         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1794                 return rte_eth_dev_pci_generic_remove(pci_dev,
1795                                         ixgbe_vf_representor_uninit);
1796         else
1797                 return rte_eth_dev_pci_generic_remove(pci_dev,
1798                                                 eth_ixgbe_dev_uninit);
1799 }
1800
1801 static struct rte_pci_driver rte_ixgbe_pmd = {
1802         .id_table = pci_id_ixgbe_map,
1803         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1804         .probe = eth_ixgbe_pci_probe,
1805         .remove = eth_ixgbe_pci_remove,
1806 };
1807
1808 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1809         struct rte_pci_device *pci_dev)
1810 {
1811         return rte_eth_dev_pci_generic_probe(pci_dev,
1812                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1813 }
1814
1815 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1816 {
1817         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1818 }
1819
1820 /*
1821  * virtual function driver struct
1822  */
1823 static struct rte_pci_driver rte_ixgbevf_pmd = {
1824         .id_table = pci_id_ixgbevf_map,
1825         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1826         .probe = eth_ixgbevf_pci_probe,
1827         .remove = eth_ixgbevf_pci_remove,
1828 };
1829
1830 static int
1831 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1832 {
1833         struct ixgbe_hw *hw =
1834                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1835         struct ixgbe_vfta *shadow_vfta =
1836                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1837         uint32_t vfta;
1838         uint32_t vid_idx;
1839         uint32_t vid_bit;
1840
1841         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1842         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1843         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1844         if (on)
1845                 vfta |= vid_bit;
1846         else
1847                 vfta &= ~vid_bit;
1848         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1849
1850         /* update local VFTA copy */
1851         shadow_vfta->vfta[vid_idx] = vfta;
1852
1853         return 0;
1854 }
1855
1856 static void
1857 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1858 {
1859         if (on)
1860                 ixgbe_vlan_hw_strip_enable(dev, queue);
1861         else
1862                 ixgbe_vlan_hw_strip_disable(dev, queue);
1863 }
1864
1865 static int
1866 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1867                     enum rte_vlan_type vlan_type,
1868                     uint16_t tpid)
1869 {
1870         struct ixgbe_hw *hw =
1871                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872         int ret = 0;
1873         uint32_t reg;
1874         uint32_t qinq;
1875
1876         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1877         qinq &= IXGBE_DMATXCTL_GDV;
1878
1879         switch (vlan_type) {
1880         case ETH_VLAN_TYPE_INNER:
1881                 if (qinq) {
1882                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1883                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1884                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1885                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1886                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1887                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1888                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1889                 } else {
1890                         ret = -ENOTSUP;
1891                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1892                                     " by single VLAN");
1893                 }
1894                 break;
1895         case ETH_VLAN_TYPE_OUTER:
1896                 if (qinq) {
1897                         /* Only the high 16-bits is valid */
1898                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1899                                         IXGBE_EXVET_VET_EXT_SHIFT);
1900                 } else {
1901                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1902                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1903                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1904                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1905                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1906                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1907                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1908                 }
1909
1910                 break;
1911         default:
1912                 ret = -EINVAL;
1913                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1914                 break;
1915         }
1916
1917         return ret;
1918 }
1919
1920 void
1921 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1922 {
1923         struct ixgbe_hw *hw =
1924                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1925         uint32_t vlnctrl;
1926
1927         PMD_INIT_FUNC_TRACE();
1928
1929         /* Filter Table Disable */
1930         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1931         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1932
1933         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1934 }
1935
1936 void
1937 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1938 {
1939         struct ixgbe_hw *hw =
1940                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1941         struct ixgbe_vfta *shadow_vfta =
1942                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1943         uint32_t vlnctrl;
1944         uint16_t i;
1945
1946         PMD_INIT_FUNC_TRACE();
1947
1948         /* Filter Table Enable */
1949         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1950         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1951         vlnctrl |= IXGBE_VLNCTRL_VFE;
1952
1953         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1954
1955         /* write whatever is in local vfta copy */
1956         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1957                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1958 }
1959
1960 static void
1961 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1962 {
1963         struct ixgbe_hwstrip *hwstrip =
1964                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1965         struct ixgbe_rx_queue *rxq;
1966
1967         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1968                 return;
1969
1970         if (on)
1971                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1972         else
1973                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1974
1975         if (queue >= dev->data->nb_rx_queues)
1976                 return;
1977
1978         rxq = dev->data->rx_queues[queue];
1979
1980         if (on) {
1981                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1982                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1983         } else {
1984                 rxq->vlan_flags = PKT_RX_VLAN;
1985                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1986         }
1987 }
1988
1989 static void
1990 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1991 {
1992         struct ixgbe_hw *hw =
1993                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1994         uint32_t ctrl;
1995
1996         PMD_INIT_FUNC_TRACE();
1997
1998         if (hw->mac.type == ixgbe_mac_82598EB) {
1999                 /* No queue level support */
2000                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2001                 return;
2002         }
2003
2004         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2005         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2006         ctrl &= ~IXGBE_RXDCTL_VME;
2007         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2008
2009         /* record those setting for HW strip per queue */
2010         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2011 }
2012
2013 static void
2014 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2015 {
2016         struct ixgbe_hw *hw =
2017                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2018         uint32_t ctrl;
2019
2020         PMD_INIT_FUNC_TRACE();
2021
2022         if (hw->mac.type == ixgbe_mac_82598EB) {
2023                 /* No queue level supported */
2024                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2025                 return;
2026         }
2027
2028         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2029         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2030         ctrl |= IXGBE_RXDCTL_VME;
2031         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2032
2033         /* record those setting for HW strip per queue */
2034         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2035 }
2036
2037 static void
2038 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2039 {
2040         struct ixgbe_hw *hw =
2041                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2042         uint32_t ctrl;
2043
2044         PMD_INIT_FUNC_TRACE();
2045
2046         /* DMATXCTRL: Geric Double VLAN Disable */
2047         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2048         ctrl &= ~IXGBE_DMATXCTL_GDV;
2049         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2050
2051         /* CTRL_EXT: Global Double VLAN Disable */
2052         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2053         ctrl &= ~IXGBE_EXTENDED_VLAN;
2054         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2055
2056 }
2057
2058 static void
2059 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2060 {
2061         struct ixgbe_hw *hw =
2062                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2063         uint32_t ctrl;
2064
2065         PMD_INIT_FUNC_TRACE();
2066
2067         /* DMATXCTRL: Geric Double VLAN Enable */
2068         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2069         ctrl |= IXGBE_DMATXCTL_GDV;
2070         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2071
2072         /* CTRL_EXT: Global Double VLAN Enable */
2073         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2074         ctrl |= IXGBE_EXTENDED_VLAN;
2075         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2076
2077         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2078         if (hw->mac.type == ixgbe_mac_X550 ||
2079             hw->mac.type == ixgbe_mac_X550EM_x ||
2080             hw->mac.type == ixgbe_mac_X550EM_a) {
2081                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2082                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2083                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2084         }
2085
2086         /*
2087          * VET EXT field in the EXVET register = 0x8100 by default
2088          * So no need to change. Same to VT field of DMATXCTL register
2089          */
2090 }
2091
2092 void
2093 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2094 {
2095         struct ixgbe_hw *hw =
2096                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2097         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2098         uint32_t ctrl;
2099         uint16_t i;
2100         struct ixgbe_rx_queue *rxq;
2101         bool on;
2102
2103         PMD_INIT_FUNC_TRACE();
2104
2105         if (hw->mac.type == ixgbe_mac_82598EB) {
2106                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2107                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2108                         ctrl |= IXGBE_VLNCTRL_VME;
2109                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2110                 } else {
2111                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2112                         ctrl &= ~IXGBE_VLNCTRL_VME;
2113                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2114                 }
2115         } else {
2116                 /*
2117                  * Other 10G NIC, the VLAN strip can be setup
2118                  * per queue in RXDCTL
2119                  */
2120                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2121                         rxq = dev->data->rx_queues[i];
2122                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2123                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2124                                 ctrl |= IXGBE_RXDCTL_VME;
2125                                 on = TRUE;
2126                         } else {
2127                                 ctrl &= ~IXGBE_RXDCTL_VME;
2128                                 on = FALSE;
2129                         }
2130                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2131
2132                         /* record those setting for HW strip per queue */
2133                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2134                 }
2135         }
2136 }
2137
2138 static void
2139 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2140 {
2141         uint16_t i;
2142         struct rte_eth_rxmode *rxmode;
2143         struct ixgbe_rx_queue *rxq;
2144
2145         if (mask & ETH_VLAN_STRIP_MASK) {
2146                 rxmode = &dev->data->dev_conf.rxmode;
2147                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2148                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2149                                 rxq = dev->data->rx_queues[i];
2150                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2151                         }
2152                 else
2153                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2154                                 rxq = dev->data->rx_queues[i];
2155                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2156                         }
2157         }
2158 }
2159
2160 static int
2161 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2162 {
2163         struct rte_eth_rxmode *rxmode;
2164         rxmode = &dev->data->dev_conf.rxmode;
2165
2166         if (mask & ETH_VLAN_STRIP_MASK) {
2167                 ixgbe_vlan_hw_strip_config(dev);
2168         }
2169
2170         if (mask & ETH_VLAN_FILTER_MASK) {
2171                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2172                         ixgbe_vlan_hw_filter_enable(dev);
2173                 else
2174                         ixgbe_vlan_hw_filter_disable(dev);
2175         }
2176
2177         if (mask & ETH_VLAN_EXTEND_MASK) {
2178                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2179                         ixgbe_vlan_hw_extend_enable(dev);
2180                 else
2181                         ixgbe_vlan_hw_extend_disable(dev);
2182         }
2183
2184         return 0;
2185 }
2186
2187 static int
2188 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2189 {
2190         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2191
2192         ixgbe_vlan_offload_config(dev, mask);
2193
2194         return 0;
2195 }
2196
2197 static void
2198 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2199 {
2200         struct ixgbe_hw *hw =
2201                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2202         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2203         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2204
2205         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2206         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2207 }
2208
2209 static int
2210 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2211 {
2212         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2213
2214         switch (nb_rx_q) {
2215         case 1:
2216         case 2:
2217                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2218                 break;
2219         case 4:
2220                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2221                 break;
2222         default:
2223                 return -EINVAL;
2224         }
2225
2226         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2227                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2228         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2229                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2230         return 0;
2231 }
2232
2233 static int
2234 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2235 {
2236         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2237         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2238         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2239         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2240
2241         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2242                 /* check multi-queue mode */
2243                 switch (dev_conf->rxmode.mq_mode) {
2244                 case ETH_MQ_RX_VMDQ_DCB:
2245                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2246                         break;
2247                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2248                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2249                         PMD_INIT_LOG(ERR, "SRIOV active,"
2250                                         " unsupported mq_mode rx %d.",
2251                                         dev_conf->rxmode.mq_mode);
2252                         return -EINVAL;
2253                 case ETH_MQ_RX_RSS:
2254                 case ETH_MQ_RX_VMDQ_RSS:
2255                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2256                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2257                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2258                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2259                                                 " invalid queue number"
2260                                                 " for VMDQ RSS, allowed"
2261                                                 " value are 1, 2 or 4.");
2262                                         return -EINVAL;
2263                                 }
2264                         break;
2265                 case ETH_MQ_RX_VMDQ_ONLY:
2266                 case ETH_MQ_RX_NONE:
2267                         /* if nothing mq mode configure, use default scheme */
2268                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2269                         break;
2270                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2271                         /* SRIOV only works in VMDq enable mode */
2272                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2273                                         " wrong mq_mode rx %d.",
2274                                         dev_conf->rxmode.mq_mode);
2275                         return -EINVAL;
2276                 }
2277
2278                 switch (dev_conf->txmode.mq_mode) {
2279                 case ETH_MQ_TX_VMDQ_DCB:
2280                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2281                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2282                         break;
2283                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2284                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2285                         break;
2286                 }
2287
2288                 /* check valid queue number */
2289                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2290                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2291                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2292                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2293                                         " must be less than or equal to %d.",
2294                                         nb_rx_q, nb_tx_q,
2295                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2296                         return -EINVAL;
2297                 }
2298         } else {
2299                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2300                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2301                                           " not supported.");
2302                         return -EINVAL;
2303                 }
2304                 /* check configuration for vmdb+dcb mode */
2305                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2306                         const struct rte_eth_vmdq_dcb_conf *conf;
2307
2308                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2309                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2310                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2311                                 return -EINVAL;
2312                         }
2313                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2314                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2315                                conf->nb_queue_pools == ETH_32_POOLS)) {
2316                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2317                                                 " nb_queue_pools must be %d or %d.",
2318                                                 ETH_16_POOLS, ETH_32_POOLS);
2319                                 return -EINVAL;
2320                         }
2321                 }
2322                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2323                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2324
2325                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2326                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2327                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2328                                 return -EINVAL;
2329                         }
2330                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2331                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2332                                conf->nb_queue_pools == ETH_32_POOLS)) {
2333                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2334                                                 " nb_queue_pools != %d and"
2335                                                 " nb_queue_pools != %d.",
2336                                                 ETH_16_POOLS, ETH_32_POOLS);
2337                                 return -EINVAL;
2338                         }
2339                 }
2340
2341                 /* For DCB mode check our configuration before we go further */
2342                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2343                         const struct rte_eth_dcb_rx_conf *conf;
2344
2345                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2346                         if (!(conf->nb_tcs == ETH_4_TCS ||
2347                                conf->nb_tcs == ETH_8_TCS)) {
2348                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2349                                                 " and nb_tcs != %d.",
2350                                                 ETH_4_TCS, ETH_8_TCS);
2351                                 return -EINVAL;
2352                         }
2353                 }
2354
2355                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2356                         const struct rte_eth_dcb_tx_conf *conf;
2357
2358                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2359                         if (!(conf->nb_tcs == ETH_4_TCS ||
2360                                conf->nb_tcs == ETH_8_TCS)) {
2361                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2362                                                 " and nb_tcs != %d.",
2363                                                 ETH_4_TCS, ETH_8_TCS);
2364                                 return -EINVAL;
2365                         }
2366                 }
2367
2368                 /*
2369                  * When DCB/VT is off, maximum number of queues changes,
2370                  * except for 82598EB, which remains constant.
2371                  */
2372                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2373                                 hw->mac.type != ixgbe_mac_82598EB) {
2374                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2375                                 PMD_INIT_LOG(ERR,
2376                                              "Neither VT nor DCB are enabled, "
2377                                              "nb_tx_q > %d.",
2378                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2379                                 return -EINVAL;
2380                         }
2381                 }
2382         }
2383         return 0;
2384 }
2385
2386 static int
2387 ixgbe_dev_configure(struct rte_eth_dev *dev)
2388 {
2389         struct ixgbe_interrupt *intr =
2390                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2391         struct ixgbe_adapter *adapter = dev->data->dev_private;
2392         int ret;
2393
2394         PMD_INIT_FUNC_TRACE();
2395
2396         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2397                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2398
2399         /* multipe queue mode checking */
2400         ret  = ixgbe_check_mq_mode(dev);
2401         if (ret != 0) {
2402                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2403                             ret);
2404                 return ret;
2405         }
2406
2407         /* set flag to update link status after init */
2408         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2409
2410         /*
2411          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2412          * allocation or vector Rx preconditions we will reset it.
2413          */
2414         adapter->rx_bulk_alloc_allowed = true;
2415         adapter->rx_vec_allowed = true;
2416
2417         return 0;
2418 }
2419
2420 static void
2421 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2422 {
2423         struct ixgbe_hw *hw =
2424                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2425         struct ixgbe_interrupt *intr =
2426                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2427         uint32_t gpie;
2428
2429         /* only set up it on X550EM_X */
2430         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2431                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2432                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2433                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2434                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2435                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2436         }
2437 }
2438
2439 int
2440 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2441                         uint16_t tx_rate, uint64_t q_msk)
2442 {
2443         struct ixgbe_hw *hw;
2444         struct ixgbe_vf_info *vfinfo;
2445         struct rte_eth_link link;
2446         uint8_t  nb_q_per_pool;
2447         uint32_t queue_stride;
2448         uint32_t queue_idx, idx = 0, vf_idx;
2449         uint32_t queue_end;
2450         uint16_t total_rate = 0;
2451         struct rte_pci_device *pci_dev;
2452         int ret;
2453
2454         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2455         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2456         if (ret < 0)
2457                 return ret;
2458
2459         if (vf >= pci_dev->max_vfs)
2460                 return -EINVAL;
2461
2462         if (tx_rate > link.link_speed)
2463                 return -EINVAL;
2464
2465         if (q_msk == 0)
2466                 return 0;
2467
2468         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2469         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2470         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2471         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2472         queue_idx = vf * queue_stride;
2473         queue_end = queue_idx + nb_q_per_pool - 1;
2474         if (queue_end >= hw->mac.max_tx_queues)
2475                 return -EINVAL;
2476
2477         if (vfinfo) {
2478                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2479                         if (vf_idx == vf)
2480                                 continue;
2481                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2482                                 idx++)
2483                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2484                 }
2485         } else {
2486                 return -EINVAL;
2487         }
2488
2489         /* Store tx_rate for this vf. */
2490         for (idx = 0; idx < nb_q_per_pool; idx++) {
2491                 if (((uint64_t)0x1 << idx) & q_msk) {
2492                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2493                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2494                         total_rate += tx_rate;
2495                 }
2496         }
2497
2498         if (total_rate > dev->data->dev_link.link_speed) {
2499                 /* Reset stored TX rate of the VF if it causes exceed
2500                  * link speed.
2501                  */
2502                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2503                 return -EINVAL;
2504         }
2505
2506         /* Set RTTBCNRC of each queue/pool for vf X  */
2507         for (; queue_idx <= queue_end; queue_idx++) {
2508                 if (0x1 & q_msk)
2509                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2510                 q_msk = q_msk >> 1;
2511         }
2512
2513         return 0;
2514 }
2515
2516 static int
2517 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2518 {
2519         struct ixgbe_adapter *adapter = dev->data->dev_private;
2520         int err;
2521         uint32_t mflcn;
2522
2523         ixgbe_setup_fc(hw);
2524
2525         err = ixgbe_fc_enable(hw);
2526
2527         /* Not negotiated is not an error case */
2528         if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2529                 /*
2530                  *check if we want to forward MAC frames - driver doesn't
2531                  *have native capability to do that,
2532                  *so we'll write the registers ourselves
2533                  */
2534
2535                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2536
2537                 /* set or clear MFLCN.PMCF bit depending on configuration */
2538                 if (adapter->mac_ctrl_frame_fwd != 0)
2539                         mflcn |= IXGBE_MFLCN_PMCF;
2540                 else
2541                         mflcn &= ~IXGBE_MFLCN_PMCF;
2542
2543                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2544                 IXGBE_WRITE_FLUSH(hw);
2545
2546                 return 0;
2547         }
2548         return err;
2549 }
2550
2551 /*
2552  * Configure device link speed and setup link.
2553  * It returns 0 on success.
2554  */
2555 static int
2556 ixgbe_dev_start(struct rte_eth_dev *dev)
2557 {
2558         struct ixgbe_hw *hw =
2559                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2560         struct ixgbe_vf_info *vfinfo =
2561                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2562         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2563         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2564         uint32_t intr_vector = 0;
2565         int err;
2566         bool link_up = false, negotiate = 0;
2567         uint32_t speed = 0;
2568         uint32_t allowed_speeds = 0;
2569         int mask = 0;
2570         int status;
2571         uint16_t vf, idx;
2572         uint32_t *link_speeds;
2573         struct ixgbe_tm_conf *tm_conf =
2574                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2575         struct ixgbe_macsec_setting *macsec_setting =
2576                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2577
2578         PMD_INIT_FUNC_TRACE();
2579
2580         /* Stop the link setup handler before resetting the HW. */
2581         ixgbe_dev_wait_setup_link_complete(dev, 0);
2582
2583         /* disable uio/vfio intr/eventfd mapping */
2584         rte_intr_disable(intr_handle);
2585
2586         /* stop adapter */
2587         hw->adapter_stopped = 0;
2588         ixgbe_stop_adapter(hw);
2589
2590         /* reinitialize adapter
2591          * this calls reset and start
2592          */
2593         status = ixgbe_pf_reset_hw(hw);
2594         if (status != 0)
2595                 return -1;
2596         hw->mac.ops.start_hw(hw);
2597         hw->mac.get_link_status = true;
2598
2599         /* configure PF module if SRIOV enabled */
2600         ixgbe_pf_host_configure(dev);
2601
2602         ixgbe_dev_phy_intr_setup(dev);
2603
2604         /* check and configure queue intr-vector mapping */
2605         if ((rte_intr_cap_multiple(intr_handle) ||
2606              !RTE_ETH_DEV_SRIOV(dev).active) &&
2607             dev->data->dev_conf.intr_conf.rxq != 0) {
2608                 intr_vector = dev->data->nb_rx_queues;
2609                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2610                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2611                                         IXGBE_MAX_INTR_QUEUE_NUM);
2612                         return -ENOTSUP;
2613                 }
2614                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2615                         return -1;
2616         }
2617
2618         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2619                 intr_handle->intr_vec =
2620                         rte_zmalloc("intr_vec",
2621                                     dev->data->nb_rx_queues * sizeof(int), 0);
2622                 if (intr_handle->intr_vec == NULL) {
2623                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2624                                      " intr_vec", dev->data->nb_rx_queues);
2625                         return -ENOMEM;
2626                 }
2627         }
2628
2629         /* confiugre msix for sleep until rx interrupt */
2630         ixgbe_configure_msix(dev);
2631
2632         /* initialize transmission unit */
2633         ixgbe_dev_tx_init(dev);
2634
2635         /* This can fail when allocating mbufs for descriptor rings */
2636         err = ixgbe_dev_rx_init(dev);
2637         if (err) {
2638                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2639                 goto error;
2640         }
2641
2642         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2643                 ETH_VLAN_EXTEND_MASK;
2644         err = ixgbe_vlan_offload_config(dev, mask);
2645         if (err) {
2646                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2647                 goto error;
2648         }
2649
2650         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2651                 /* Enable vlan filtering for VMDq */
2652                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2653         }
2654
2655         /* Configure DCB hw */
2656         ixgbe_configure_dcb(dev);
2657
2658         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2659                 err = ixgbe_fdir_configure(dev);
2660                 if (err)
2661                         goto error;
2662         }
2663
2664         /* Restore vf rate limit */
2665         if (vfinfo != NULL) {
2666                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2667                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2668                                 if (vfinfo[vf].tx_rate[idx] != 0)
2669                                         ixgbe_set_vf_rate_limit(
2670                                                 dev, vf,
2671                                                 vfinfo[vf].tx_rate[idx],
2672                                                 1 << idx);
2673         }
2674
2675         ixgbe_restore_statistics_mapping(dev);
2676
2677         err = ixgbe_flow_ctrl_enable(dev, hw);
2678         if (err < 0) {
2679                 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2680                 goto error;
2681         }
2682
2683         err = ixgbe_dev_rxtx_start(dev);
2684         if (err < 0) {
2685                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2686                 goto error;
2687         }
2688
2689         /* Skip link setup if loopback mode is enabled. */
2690         if (dev->data->dev_conf.lpbk_mode != 0) {
2691                 err = ixgbe_check_supported_loopback_mode(dev);
2692                 if (err < 0) {
2693                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2694                         goto error;
2695                 } else {
2696                         goto skip_link_setup;
2697                 }
2698         }
2699
2700         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2701                 err = hw->mac.ops.setup_sfp(hw);
2702                 if (err)
2703                         goto error;
2704         }
2705
2706         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2707                 /* Turn on the copper */
2708                 ixgbe_set_phy_power(hw, true);
2709         } else {
2710                 /* Turn on the laser */
2711                 ixgbe_enable_tx_laser(hw);
2712         }
2713
2714         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2715         if (err)
2716                 goto error;
2717         dev->data->dev_link.link_status = link_up;
2718
2719         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2720         if (err)
2721                 goto error;
2722
2723         switch (hw->mac.type) {
2724         case ixgbe_mac_X550:
2725         case ixgbe_mac_X550EM_x:
2726         case ixgbe_mac_X550EM_a:
2727                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2728                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2729                         ETH_LINK_SPEED_10G;
2730                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2731                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2732                         allowed_speeds = ETH_LINK_SPEED_10M |
2733                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2734                 break;
2735         default:
2736                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2737                         ETH_LINK_SPEED_10G;
2738         }
2739
2740         link_speeds = &dev->data->dev_conf.link_speeds;
2741
2742         /* Ignore autoneg flag bit and check the validity of
2743          * link_speed
2744          */
2745         if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2746                 PMD_INIT_LOG(ERR, "Invalid link setting");
2747                 goto error;
2748         }
2749
2750         speed = 0x0;
2751         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2752                 switch (hw->mac.type) {
2753                 case ixgbe_mac_82598EB:
2754                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2755                         break;
2756                 case ixgbe_mac_82599EB:
2757                 case ixgbe_mac_X540:
2758                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2759                         break;
2760                 case ixgbe_mac_X550:
2761                 case ixgbe_mac_X550EM_x:
2762                 case ixgbe_mac_X550EM_a:
2763                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2764                         break;
2765                 default:
2766                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2767                 }
2768         } else {
2769                 if (*link_speeds & ETH_LINK_SPEED_10G)
2770                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2771                 if (*link_speeds & ETH_LINK_SPEED_5G)
2772                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2773                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2774                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2775                 if (*link_speeds & ETH_LINK_SPEED_1G)
2776                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2777                 if (*link_speeds & ETH_LINK_SPEED_100M)
2778                         speed |= IXGBE_LINK_SPEED_100_FULL;
2779                 if (*link_speeds & ETH_LINK_SPEED_10M)
2780                         speed |= IXGBE_LINK_SPEED_10_FULL;
2781         }
2782
2783         err = ixgbe_setup_link(hw, speed, link_up);
2784         if (err)
2785                 goto error;
2786
2787 skip_link_setup:
2788
2789         if (rte_intr_allow_others(intr_handle)) {
2790                 /* check if lsc interrupt is enabled */
2791                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2792                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2793                 else
2794                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2795                 ixgbe_dev_macsec_interrupt_setup(dev);
2796         } else {
2797                 rte_intr_callback_unregister(intr_handle,
2798                                              ixgbe_dev_interrupt_handler, dev);
2799                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2800                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2801                                      " no intr multiplex");
2802         }
2803
2804         /* check if rxq interrupt is enabled */
2805         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2806             rte_intr_dp_is_en(intr_handle))
2807                 ixgbe_dev_rxq_interrupt_setup(dev);
2808
2809         /* enable uio/vfio intr/eventfd mapping */
2810         rte_intr_enable(intr_handle);
2811
2812         /* resume enabled intr since hw reset */
2813         ixgbe_enable_intr(dev);
2814         ixgbe_l2_tunnel_conf(dev);
2815         ixgbe_filter_restore(dev);
2816
2817         if (tm_conf->root && !tm_conf->committed)
2818                 PMD_DRV_LOG(WARNING,
2819                             "please call hierarchy_commit() "
2820                             "before starting the port");
2821
2822         /* wait for the controller to acquire link */
2823         err = ixgbe_wait_for_link_up(hw);
2824         if (err)
2825                 goto error;
2826
2827         /*
2828          * Update link status right before return, because it may
2829          * start link configuration process in a separate thread.
2830          */
2831         ixgbe_dev_link_update(dev, 0);
2832
2833         /* setup the macsec setting register */
2834         if (macsec_setting->offload_en)
2835                 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2836
2837         return 0;
2838
2839 error:
2840         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2841         ixgbe_dev_clear_queues(dev);
2842         return -EIO;
2843 }
2844
2845 /*
2846  * Stop device: disable rx and tx functions to allow for reconfiguring.
2847  */
2848 static void
2849 ixgbe_dev_stop(struct rte_eth_dev *dev)
2850 {
2851         struct rte_eth_link link;
2852         struct ixgbe_adapter *adapter = dev->data->dev_private;
2853         struct ixgbe_hw *hw =
2854                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2855         struct ixgbe_vf_info *vfinfo =
2856                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2857         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2858         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2859         int vf;
2860         struct ixgbe_tm_conf *tm_conf =
2861                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2862
2863         if (hw->adapter_stopped)
2864                 return;
2865
2866         PMD_INIT_FUNC_TRACE();
2867
2868         ixgbe_dev_wait_setup_link_complete(dev, 0);
2869
2870         /* disable interrupts */
2871         ixgbe_disable_intr(hw);
2872
2873         /* reset the NIC */
2874         ixgbe_pf_reset_hw(hw);
2875         hw->adapter_stopped = 0;
2876
2877         /* stop adapter */
2878         ixgbe_stop_adapter(hw);
2879
2880         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2881                 vfinfo[vf].clear_to_send = false;
2882
2883         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2884                 /* Turn off the copper */
2885                 ixgbe_set_phy_power(hw, false);
2886         } else {
2887                 /* Turn off the laser */
2888                 ixgbe_disable_tx_laser(hw);
2889         }
2890
2891         ixgbe_dev_clear_queues(dev);
2892
2893         /* Clear stored conf */
2894         dev->data->scattered_rx = 0;
2895         dev->data->lro = 0;
2896
2897         /* Clear recorded link status */
2898         memset(&link, 0, sizeof(link));
2899         rte_eth_linkstatus_set(dev, &link);
2900
2901         if (!rte_intr_allow_others(intr_handle))
2902                 /* resume to the default handler */
2903                 rte_intr_callback_register(intr_handle,
2904                                            ixgbe_dev_interrupt_handler,
2905                                            (void *)dev);
2906
2907         /* Clean datapath event and queue/vec mapping */
2908         rte_intr_efd_disable(intr_handle);
2909         if (intr_handle->intr_vec != NULL) {
2910                 rte_free(intr_handle->intr_vec);
2911                 intr_handle->intr_vec = NULL;
2912         }
2913
2914         /* reset hierarchy commit */
2915         tm_conf->committed = false;
2916
2917         adapter->rss_reta_updated = 0;
2918
2919         hw->adapter_stopped = true;
2920 }
2921
2922 /*
2923  * Set device link up: enable tx.
2924  */
2925 static int
2926 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2927 {
2928         struct ixgbe_hw *hw =
2929                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2930         if (hw->mac.type == ixgbe_mac_82599EB) {
2931 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2932                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2933                         /* Not suported in bypass mode */
2934                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2935                                      "by device id 0x%x", hw->device_id);
2936                         return -ENOTSUP;
2937                 }
2938 #endif
2939         }
2940
2941         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2942                 /* Turn on the copper */
2943                 ixgbe_set_phy_power(hw, true);
2944         } else {
2945                 /* Turn on the laser */
2946                 ixgbe_enable_tx_laser(hw);
2947                 ixgbe_dev_link_update(dev, 0);
2948         }
2949
2950         return 0;
2951 }
2952
2953 /*
2954  * Set device link down: disable tx.
2955  */
2956 static int
2957 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2958 {
2959         struct ixgbe_hw *hw =
2960                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2961         if (hw->mac.type == ixgbe_mac_82599EB) {
2962 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2963                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2964                         /* Not suported in bypass mode */
2965                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2966                                      "by device id 0x%x", hw->device_id);
2967                         return -ENOTSUP;
2968                 }
2969 #endif
2970         }
2971
2972         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2973                 /* Turn off the copper */
2974                 ixgbe_set_phy_power(hw, false);
2975         } else {
2976                 /* Turn off the laser */
2977                 ixgbe_disable_tx_laser(hw);
2978                 ixgbe_dev_link_update(dev, 0);
2979         }
2980
2981         return 0;
2982 }
2983
2984 /*
2985  * Reset and stop device.
2986  */
2987 static int
2988 ixgbe_dev_close(struct rte_eth_dev *dev)
2989 {
2990         struct ixgbe_hw *hw =
2991                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2992         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2993         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2994         int retries = 0;
2995         int ret;
2996
2997         PMD_INIT_FUNC_TRACE();
2998
2999         ixgbe_pf_reset_hw(hw);
3000
3001         ixgbe_dev_stop(dev);
3002
3003         ixgbe_dev_free_queues(dev);
3004
3005         ixgbe_disable_pcie_master(hw);
3006
3007         /* reprogram the RAR[0] in case user changed it. */
3008         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3009
3010         dev->dev_ops = NULL;
3011         dev->rx_pkt_burst = NULL;
3012         dev->tx_pkt_burst = NULL;
3013
3014         /* Unlock any pending hardware semaphore */
3015         ixgbe_swfw_lock_reset(hw);
3016
3017         /* disable uio intr before callback unregister */
3018         rte_intr_disable(intr_handle);
3019
3020         do {
3021                 ret = rte_intr_callback_unregister(intr_handle,
3022                                 ixgbe_dev_interrupt_handler, dev);
3023                 if (ret >= 0 || ret == -ENOENT) {
3024                         break;
3025                 } else if (ret != -EAGAIN) {
3026                         PMD_INIT_LOG(ERR,
3027                                 "intr callback unregister failed: %d",
3028                                 ret);
3029                 }
3030                 rte_delay_ms(100);
3031         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3032
3033         /* cancel the delay handler before remove dev */
3034         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3035
3036         /* uninitialize PF if max_vfs not zero */
3037         ixgbe_pf_host_uninit(dev);
3038
3039         /* remove all the fdir filters & hash */
3040         ixgbe_fdir_filter_uninit(dev);
3041
3042         /* remove all the L2 tunnel filters & hash */
3043         ixgbe_l2_tn_filter_uninit(dev);
3044
3045         /* Remove all ntuple filters of the device */
3046         ixgbe_ntuple_filter_uninit(dev);
3047
3048         /* clear all the filters list */
3049         ixgbe_filterlist_flush();
3050
3051         /* Remove all Traffic Manager configuration */
3052         ixgbe_tm_conf_uninit(dev);
3053
3054 #ifdef RTE_LIBRTE_SECURITY
3055         rte_free(dev->security_ctx);
3056 #endif
3057
3058         return 0;
3059 }
3060
3061 /*
3062  * Reset PF device.
3063  */
3064 static int
3065 ixgbe_dev_reset(struct rte_eth_dev *dev)
3066 {
3067         int ret;
3068
3069         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3070          * its VF to make them align with it. The detailed notification
3071          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3072          * To avoid unexpected behavior in VF, currently reset of PF with
3073          * SR-IOV activation is not supported. It might be supported later.
3074          */
3075         if (dev->data->sriov.active)
3076                 return -ENOTSUP;
3077
3078         ret = eth_ixgbe_dev_uninit(dev);
3079         if (ret)
3080                 return ret;
3081
3082         ret = eth_ixgbe_dev_init(dev, NULL);
3083
3084         return ret;
3085 }
3086
3087 static void
3088 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3089                            struct ixgbe_hw_stats *hw_stats,
3090                            struct ixgbe_macsec_stats *macsec_stats,
3091                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3092                            uint64_t *total_qprc, uint64_t *total_qprdc)
3093 {
3094         uint32_t bprc, lxon, lxoff, total;
3095         uint32_t delta_gprc = 0;
3096         unsigned i;
3097         /* Workaround for RX byte count not including CRC bytes when CRC
3098          * strip is enabled. CRC bytes are removed from counters when crc_strip
3099          * is disabled.
3100          */
3101         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3102                         IXGBE_HLREG0_RXCRCSTRP);
3103
3104         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3105         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3106         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3107         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3108
3109         for (i = 0; i < 8; i++) {
3110                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3111
3112                 /* global total per queue */
3113                 hw_stats->mpc[i] += mp;
3114                 /* Running comprehensive total for stats display */
3115                 *total_missed_rx += hw_stats->mpc[i];
3116                 if (hw->mac.type == ixgbe_mac_82598EB) {
3117                         hw_stats->rnbc[i] +=
3118                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3119                         hw_stats->pxonrxc[i] +=
3120                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3121                         hw_stats->pxoffrxc[i] +=
3122                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3123                 } else {
3124                         hw_stats->pxonrxc[i] +=
3125                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3126                         hw_stats->pxoffrxc[i] +=
3127                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3128                         hw_stats->pxon2offc[i] +=
3129                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3130                 }
3131                 hw_stats->pxontxc[i] +=
3132                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3133                 hw_stats->pxofftxc[i] +=
3134                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3135         }
3136         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3137                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3138                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3139                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3140
3141                 delta_gprc += delta_qprc;
3142
3143                 hw_stats->qprc[i] += delta_qprc;
3144                 hw_stats->qptc[i] += delta_qptc;
3145
3146                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3147                 hw_stats->qbrc[i] +=
3148                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3149                 if (crc_strip == 0)
3150                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3151
3152                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3153                 hw_stats->qbtc[i] +=
3154                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3155
3156                 hw_stats->qprdc[i] += delta_qprdc;
3157                 *total_qprdc += hw_stats->qprdc[i];
3158
3159                 *total_qprc += hw_stats->qprc[i];
3160                 *total_qbrc += hw_stats->qbrc[i];
3161         }
3162         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3163         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3164         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3165
3166         /*
3167          * An errata states that gprc actually counts good + missed packets:
3168          * Workaround to set gprc to summated queue packet receives
3169          */
3170         hw_stats->gprc = *total_qprc;
3171
3172         if (hw->mac.type != ixgbe_mac_82598EB) {
3173                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3174                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3175                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3176                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3177                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3178                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3179                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3180                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3181         } else {
3182                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3183                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3184                 /* 82598 only has a counter in the high register */
3185                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3186                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3187                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3188         }
3189         uint64_t old_tpr = hw_stats->tpr;
3190
3191         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3192         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3193
3194         if (crc_strip == 0)
3195                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3196
3197         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3198         hw_stats->gptc += delta_gptc;
3199         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3200         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3201
3202         /*
3203          * Workaround: mprc hardware is incorrectly counting
3204          * broadcasts, so for now we subtract those.
3205          */
3206         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3207         hw_stats->bprc += bprc;
3208         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3209         if (hw->mac.type == ixgbe_mac_82598EB)
3210                 hw_stats->mprc -= bprc;
3211
3212         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3213         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3214         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3215         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3216         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3217         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3218
3219         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3220         hw_stats->lxontxc += lxon;
3221         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3222         hw_stats->lxofftxc += lxoff;
3223         total = lxon + lxoff;
3224
3225         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3226         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3227         hw_stats->gptc -= total;
3228         hw_stats->mptc -= total;
3229         hw_stats->ptc64 -= total;
3230         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3231
3232         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3233         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3234         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3235         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3236         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3237         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3238         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3239         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3240         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3241         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3242         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3243         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3244         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3245         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3246         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3247         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3248         /* Only read FCOE on 82599 */
3249         if (hw->mac.type != ixgbe_mac_82598EB) {
3250                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3251                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3252                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3253                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3254                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3255         }
3256
3257         /* Flow Director Stats registers */
3258         if (hw->mac.type != ixgbe_mac_82598EB) {
3259                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3260                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3261                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3262                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3263                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3264                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3265                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3266                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3267                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3268                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3269         }
3270         /* MACsec Stats registers */
3271         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3272         macsec_stats->out_pkts_encrypted +=
3273                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3274         macsec_stats->out_pkts_protected +=
3275                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3276         macsec_stats->out_octets_encrypted +=
3277                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3278         macsec_stats->out_octets_protected +=
3279                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3280         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3281         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3282         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3283         macsec_stats->in_pkts_unknownsci +=
3284                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3285         macsec_stats->in_octets_decrypted +=
3286                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3287         macsec_stats->in_octets_validated +=
3288                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3289         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3290         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3291         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3292         for (i = 0; i < 2; i++) {
3293                 macsec_stats->in_pkts_ok +=
3294                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3295                 macsec_stats->in_pkts_invalid +=
3296                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3297                 macsec_stats->in_pkts_notvalid +=
3298                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3299         }
3300         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3301         macsec_stats->in_pkts_notusingsa +=
3302                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3303 }
3304
3305 /*
3306  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3307  */
3308 static int
3309 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3310 {
3311         struct ixgbe_hw *hw =
3312                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3313         struct ixgbe_hw_stats *hw_stats =
3314                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3315         struct ixgbe_macsec_stats *macsec_stats =
3316                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3317                                 dev->data->dev_private);
3318         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3319         unsigned i;
3320
3321         total_missed_rx = 0;
3322         total_qbrc = 0;
3323         total_qprc = 0;
3324         total_qprdc = 0;
3325
3326         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3327                         &total_qbrc, &total_qprc, &total_qprdc);
3328
3329         if (stats == NULL)
3330                 return -EINVAL;
3331
3332         /* Fill out the rte_eth_stats statistics structure */
3333         stats->ipackets = total_qprc;
3334         stats->ibytes = total_qbrc;
3335         stats->opackets = hw_stats->gptc;
3336         stats->obytes = hw_stats->gotc;
3337
3338         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3339                 stats->q_ipackets[i] = hw_stats->qprc[i];
3340                 stats->q_opackets[i] = hw_stats->qptc[i];
3341                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3342                 stats->q_obytes[i] = hw_stats->qbtc[i];
3343                 stats->q_errors[i] = hw_stats->qprdc[i];
3344         }
3345
3346         /* Rx Errors */
3347         stats->imissed  = total_missed_rx;
3348         stats->ierrors  = hw_stats->crcerrs +
3349                           hw_stats->mspdc +
3350                           hw_stats->rlec +
3351                           hw_stats->ruc +
3352                           hw_stats->roc +
3353                           hw_stats->illerrc +
3354                           hw_stats->errbc +
3355                           hw_stats->rfc +
3356                           hw_stats->fccrc +
3357                           hw_stats->fclast;
3358
3359         /* Tx Errors */
3360         stats->oerrors  = 0;
3361         return 0;
3362 }
3363
3364 static int
3365 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3366 {
3367         struct ixgbe_hw_stats *stats =
3368                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3369
3370         /* HW registers are cleared on read */
3371         ixgbe_dev_stats_get(dev, NULL);
3372
3373         /* Reset software totals */
3374         memset(stats, 0, sizeof(*stats));
3375
3376         return 0;
3377 }
3378
3379 /* This function calculates the number of xstats based on the current config */
3380 static unsigned
3381 ixgbe_xstats_calc_num(void) {
3382         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3383                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3384                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3385 }
3386
3387 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3388         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3389 {
3390         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3391         unsigned stat, i, count;
3392
3393         if (xstats_names != NULL) {
3394                 count = 0;
3395
3396                 /* Note: limit >= cnt_stats checked upstream
3397                  * in rte_eth_xstats_names()
3398                  */
3399
3400                 /* Extended stats from ixgbe_hw_stats */
3401                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3402                         strlcpy(xstats_names[count].name,
3403                                 rte_ixgbe_stats_strings[i].name,
3404                                 sizeof(xstats_names[count].name));
3405                         count++;
3406                 }
3407
3408                 /* MACsec Stats */
3409                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3410                         strlcpy(xstats_names[count].name,
3411                                 rte_ixgbe_macsec_strings[i].name,
3412                                 sizeof(xstats_names[count].name));
3413                         count++;
3414                 }
3415
3416                 /* RX Priority Stats */
3417                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3418                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3419                                 snprintf(xstats_names[count].name,
3420                                         sizeof(xstats_names[count].name),
3421                                         "rx_priority%u_%s", i,
3422                                         rte_ixgbe_rxq_strings[stat].name);
3423                                 count++;
3424                         }
3425                 }
3426
3427                 /* TX Priority Stats */
3428                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3429                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3430                                 snprintf(xstats_names[count].name,
3431                                         sizeof(xstats_names[count].name),
3432                                         "tx_priority%u_%s", i,
3433                                         rte_ixgbe_txq_strings[stat].name);
3434                                 count++;
3435                         }
3436                 }
3437         }
3438         return cnt_stats;
3439 }
3440
3441 static int ixgbe_dev_xstats_get_names_by_id(
3442         struct rte_eth_dev *dev,
3443         struct rte_eth_xstat_name *xstats_names,
3444         const uint64_t *ids,
3445         unsigned int limit)
3446 {
3447         if (!ids) {
3448                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3449                 unsigned int stat, i, count;
3450
3451                 if (xstats_names != NULL) {
3452                         count = 0;
3453
3454                         /* Note: limit >= cnt_stats checked upstream
3455                          * in rte_eth_xstats_names()
3456                          */
3457
3458                         /* Extended stats from ixgbe_hw_stats */
3459                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3460                                 strlcpy(xstats_names[count].name,
3461                                         rte_ixgbe_stats_strings[i].name,
3462                                         sizeof(xstats_names[count].name));
3463                                 count++;
3464                         }
3465
3466                         /* MACsec Stats */
3467                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3468                                 strlcpy(xstats_names[count].name,
3469                                         rte_ixgbe_macsec_strings[i].name,
3470                                         sizeof(xstats_names[count].name));
3471                                 count++;
3472                         }
3473
3474                         /* RX Priority Stats */
3475                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3476                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3477                                         snprintf(xstats_names[count].name,
3478                                             sizeof(xstats_names[count].name),
3479                                             "rx_priority%u_%s", i,
3480                                             rte_ixgbe_rxq_strings[stat].name);
3481                                         count++;
3482                                 }
3483                         }
3484
3485                         /* TX Priority Stats */
3486                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3487                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3488                                         snprintf(xstats_names[count].name,
3489                                             sizeof(xstats_names[count].name),
3490                                             "tx_priority%u_%s", i,
3491                                             rte_ixgbe_txq_strings[stat].name);
3492                                         count++;
3493                                 }
3494                         }
3495                 }
3496                 return cnt_stats;
3497         }
3498
3499         uint16_t i;
3500         uint16_t size = ixgbe_xstats_calc_num();
3501         struct rte_eth_xstat_name xstats_names_copy[size];
3502
3503         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3504                         size);
3505
3506         for (i = 0; i < limit; i++) {
3507                 if (ids[i] >= size) {
3508                         PMD_INIT_LOG(ERR, "id value isn't valid");
3509                         return -1;
3510                 }
3511                 strcpy(xstats_names[i].name,
3512                                 xstats_names_copy[ids[i]].name);
3513         }
3514         return limit;
3515 }
3516
3517 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3518         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3519 {
3520         unsigned i;
3521
3522         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3523                 return -ENOMEM;
3524
3525         if (xstats_names != NULL)
3526                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3527                         strlcpy(xstats_names[i].name,
3528                                 rte_ixgbevf_stats_strings[i].name,
3529                                 sizeof(xstats_names[i].name));
3530         return IXGBEVF_NB_XSTATS;
3531 }
3532
3533 static int
3534 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3535                                          unsigned n)
3536 {
3537         struct ixgbe_hw *hw =
3538                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3539         struct ixgbe_hw_stats *hw_stats =
3540                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3541         struct ixgbe_macsec_stats *macsec_stats =
3542                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3543                                 dev->data->dev_private);
3544         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3545         unsigned i, stat, count = 0;
3546
3547         count = ixgbe_xstats_calc_num();
3548
3549         if (n < count)
3550                 return count;
3551
3552         total_missed_rx = 0;
3553         total_qbrc = 0;
3554         total_qprc = 0;
3555         total_qprdc = 0;
3556
3557         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3558                         &total_qbrc, &total_qprc, &total_qprdc);
3559
3560         /* If this is a reset xstats is NULL, and we have cleared the
3561          * registers by reading them.
3562          */
3563         if (!xstats)
3564                 return 0;
3565
3566         /* Extended stats from ixgbe_hw_stats */
3567         count = 0;
3568         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3569                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3570                                 rte_ixgbe_stats_strings[i].offset);
3571                 xstats[count].id = count;
3572                 count++;
3573         }
3574
3575         /* MACsec Stats */
3576         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3577                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3578                                 rte_ixgbe_macsec_strings[i].offset);
3579                 xstats[count].id = count;
3580                 count++;
3581         }
3582
3583         /* RX Priority Stats */
3584         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3585                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3586                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3587                                         rte_ixgbe_rxq_strings[stat].offset +
3588                                         (sizeof(uint64_t) * i));
3589                         xstats[count].id = count;
3590                         count++;
3591                 }
3592         }
3593
3594         /* TX Priority Stats */
3595         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3596                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3597                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3598                                         rte_ixgbe_txq_strings[stat].offset +
3599                                         (sizeof(uint64_t) * i));
3600                         xstats[count].id = count;
3601                         count++;
3602                 }
3603         }
3604         return count;
3605 }
3606
3607 static int
3608 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3609                 uint64_t *values, unsigned int n)
3610 {
3611         if (!ids) {
3612                 struct ixgbe_hw *hw =
3613                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3614                 struct ixgbe_hw_stats *hw_stats =
3615                                 IXGBE_DEV_PRIVATE_TO_STATS(
3616                                                 dev->data->dev_private);
3617                 struct ixgbe_macsec_stats *macsec_stats =
3618                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3619                                         dev->data->dev_private);
3620                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3621                 unsigned int i, stat, count = 0;
3622
3623                 count = ixgbe_xstats_calc_num();
3624
3625                 if (!ids && n < count)
3626                         return count;
3627
3628                 total_missed_rx = 0;
3629                 total_qbrc = 0;
3630                 total_qprc = 0;
3631                 total_qprdc = 0;
3632
3633                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3634                                 &total_missed_rx, &total_qbrc, &total_qprc,
3635                                 &total_qprdc);
3636
3637                 /* If this is a reset xstats is NULL, and we have cleared the
3638                  * registers by reading them.
3639                  */
3640                 if (!ids && !values)
3641                         return 0;
3642
3643                 /* Extended stats from ixgbe_hw_stats */
3644                 count = 0;
3645                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3646                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3647                                         rte_ixgbe_stats_strings[i].offset);
3648                         count++;
3649                 }
3650
3651                 /* MACsec Stats */
3652                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3653                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3654                                         rte_ixgbe_macsec_strings[i].offset);
3655                         count++;
3656                 }
3657
3658                 /* RX Priority Stats */
3659                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3660                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3661                                 values[count] =
3662                                         *(uint64_t *)(((char *)hw_stats) +
3663                                         rte_ixgbe_rxq_strings[stat].offset +
3664                                         (sizeof(uint64_t) * i));
3665                                 count++;
3666                         }
3667                 }
3668
3669                 /* TX Priority Stats */
3670                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3671                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3672                                 values[count] =
3673                                         *(uint64_t *)(((char *)hw_stats) +
3674                                         rte_ixgbe_txq_strings[stat].offset +
3675                                         (sizeof(uint64_t) * i));
3676                                 count++;
3677                         }
3678                 }
3679                 return count;
3680         }
3681
3682         uint16_t i;
3683         uint16_t size = ixgbe_xstats_calc_num();
3684         uint64_t values_copy[size];
3685
3686         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3687
3688         for (i = 0; i < n; i++) {
3689                 if (ids[i] >= size) {
3690                         PMD_INIT_LOG(ERR, "id value isn't valid");
3691                         return -1;
3692                 }
3693                 values[i] = values_copy[ids[i]];
3694         }
3695         return n;
3696 }
3697
3698 static int
3699 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3700 {
3701         struct ixgbe_hw_stats *stats =
3702                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3703         struct ixgbe_macsec_stats *macsec_stats =
3704                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3705                                 dev->data->dev_private);
3706
3707         unsigned count = ixgbe_xstats_calc_num();
3708
3709         /* HW registers are cleared on read */
3710         ixgbe_dev_xstats_get(dev, NULL, count);
3711
3712         /* Reset software totals */
3713         memset(stats, 0, sizeof(*stats));
3714         memset(macsec_stats, 0, sizeof(*macsec_stats));
3715
3716         return 0;
3717 }
3718
3719 static void
3720 ixgbevf_update_stats(struct rte_eth_dev *dev)
3721 {
3722         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3723         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3724                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3725
3726         /* Good Rx packet, include VF loopback */
3727         UPDATE_VF_STAT(IXGBE_VFGPRC,
3728             hw_stats->last_vfgprc, hw_stats->vfgprc);
3729
3730         /* Good Rx octets, include VF loopback */
3731         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3732             hw_stats->last_vfgorc, hw_stats->vfgorc);
3733
3734         /* Good Tx packet, include VF loopback */
3735         UPDATE_VF_STAT(IXGBE_VFGPTC,
3736             hw_stats->last_vfgptc, hw_stats->vfgptc);
3737
3738         /* Good Tx octets, include VF loopback */
3739         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3740             hw_stats->last_vfgotc, hw_stats->vfgotc);
3741
3742         /* Rx Multicst Packet */
3743         UPDATE_VF_STAT(IXGBE_VFMPRC,
3744             hw_stats->last_vfmprc, hw_stats->vfmprc);
3745 }
3746
3747 static int
3748 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3749                        unsigned n)
3750 {
3751         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3752                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3753         unsigned i;
3754
3755         if (n < IXGBEVF_NB_XSTATS)
3756                 return IXGBEVF_NB_XSTATS;
3757
3758         ixgbevf_update_stats(dev);
3759
3760         if (!xstats)
3761                 return 0;
3762
3763         /* Extended stats */
3764         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3765                 xstats[i].id = i;
3766                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3767                         rte_ixgbevf_stats_strings[i].offset);
3768         }
3769
3770         return IXGBEVF_NB_XSTATS;
3771 }
3772
3773 static int
3774 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3775 {
3776         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3777                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3778
3779         ixgbevf_update_stats(dev);
3780
3781         if (stats == NULL)
3782                 return -EINVAL;
3783
3784         stats->ipackets = hw_stats->vfgprc;
3785         stats->ibytes = hw_stats->vfgorc;
3786         stats->opackets = hw_stats->vfgptc;
3787         stats->obytes = hw_stats->vfgotc;
3788         return 0;
3789 }
3790
3791 static int
3792 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3793 {
3794         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3795                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3796
3797         /* Sync HW register to the last stats */
3798         ixgbevf_dev_stats_get(dev, NULL);
3799
3800         /* reset HW current stats*/
3801         hw_stats->vfgprc = 0;
3802         hw_stats->vfgorc = 0;
3803         hw_stats->vfgptc = 0;
3804         hw_stats->vfgotc = 0;
3805
3806         return 0;
3807 }
3808
3809 static int
3810 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3811 {
3812         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3813         u16 eeprom_verh, eeprom_verl;
3814         u32 etrack_id;
3815         int ret;
3816
3817         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3818         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3819
3820         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3821         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3822
3823         ret += 1; /* add the size of '\0' */
3824         if (fw_size < (u32)ret)
3825                 return ret;
3826         else
3827                 return 0;
3828 }
3829
3830 static int
3831 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3832 {
3833         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3834         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3835         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3836
3837         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3838         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3839         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3840                 /*
3841                  * When DCB/VT is off, maximum number of queues changes,
3842                  * except for 82598EB, which remains constant.
3843                  */
3844                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3845                                 hw->mac.type != ixgbe_mac_82598EB)
3846                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3847         }
3848         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3849         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3850         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3851         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3852         dev_info->max_vfs = pci_dev->max_vfs;
3853         if (hw->mac.type == ixgbe_mac_82598EB)
3854                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3855         else
3856                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3857         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3858         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3859         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3860         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3861         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3862                                      dev_info->rx_queue_offload_capa);
3863         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3864         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3865
3866         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3867                 .rx_thresh = {
3868                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3869                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3870                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3871                 },
3872                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3873                 .rx_drop_en = 0,
3874                 .offloads = 0,
3875         };
3876
3877         dev_info->default_txconf = (struct rte_eth_txconf) {
3878                 .tx_thresh = {
3879                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3880                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3881                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3882                 },
3883                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3884                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3885                 .offloads = 0,
3886         };
3887
3888         dev_info->rx_desc_lim = rx_desc_lim;
3889         dev_info->tx_desc_lim = tx_desc_lim;
3890
3891         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3892         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3893         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3894
3895         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3896         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3897                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3898                 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3899                         ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3900
3901         if (hw->mac.type == ixgbe_mac_X540 ||
3902             hw->mac.type == ixgbe_mac_X540_vf ||
3903             hw->mac.type == ixgbe_mac_X550 ||
3904             hw->mac.type == ixgbe_mac_X550_vf) {
3905                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3906         }
3907         if (hw->mac.type == ixgbe_mac_X550) {
3908                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3909                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3910         }
3911
3912         /* Driver-preferred Rx/Tx parameters */
3913         dev_info->default_rxportconf.burst_size = 32;
3914         dev_info->default_txportconf.burst_size = 32;
3915         dev_info->default_rxportconf.nb_queues = 1;
3916         dev_info->default_txportconf.nb_queues = 1;
3917         dev_info->default_rxportconf.ring_size = 256;
3918         dev_info->default_txportconf.ring_size = 256;
3919
3920         return 0;
3921 }
3922
3923 static const uint32_t *
3924 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3925 {
3926         static const uint32_t ptypes[] = {
3927                 /* For non-vec functions,
3928                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3929                  * for vec functions,
3930                  * refers to _recv_raw_pkts_vec().
3931                  */
3932                 RTE_PTYPE_L2_ETHER,
3933                 RTE_PTYPE_L3_IPV4,
3934                 RTE_PTYPE_L3_IPV4_EXT,
3935                 RTE_PTYPE_L3_IPV6,
3936                 RTE_PTYPE_L3_IPV6_EXT,
3937                 RTE_PTYPE_L4_SCTP,
3938                 RTE_PTYPE_L4_TCP,
3939                 RTE_PTYPE_L4_UDP,
3940                 RTE_PTYPE_TUNNEL_IP,
3941                 RTE_PTYPE_INNER_L3_IPV6,
3942                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3943                 RTE_PTYPE_INNER_L4_TCP,
3944                 RTE_PTYPE_INNER_L4_UDP,
3945                 RTE_PTYPE_UNKNOWN
3946         };
3947
3948         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3949             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3950             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3951             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3952                 return ptypes;
3953
3954 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON)
3955         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3956             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3957                 return ptypes;
3958 #endif
3959         return NULL;
3960 }
3961
3962 static int
3963 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3964                      struct rte_eth_dev_info *dev_info)
3965 {
3966         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3967         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3968
3969         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3970         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3971         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3972         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3973         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3974         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3975         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3976         dev_info->max_vfs = pci_dev->max_vfs;
3977         if (hw->mac.type == ixgbe_mac_82598EB)
3978                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3979         else
3980                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3981         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3982         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3983                                      dev_info->rx_queue_offload_capa);
3984         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3985         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3986         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3987         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3988         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3989
3990         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3991                 .rx_thresh = {
3992                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3993                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3994                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3995                 },
3996                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3997                 .rx_drop_en = 0,
3998                 .offloads = 0,
3999         };
4000
4001         dev_info->default_txconf = (struct rte_eth_txconf) {
4002                 .tx_thresh = {
4003                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
4004                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
4005                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
4006                 },
4007                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
4008                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
4009                 .offloads = 0,
4010         };
4011
4012         dev_info->rx_desc_lim = rx_desc_lim;
4013         dev_info->tx_desc_lim = tx_desc_lim;
4014
4015         return 0;
4016 }
4017
4018 static int
4019 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4020                    bool *link_up, int wait_to_complete)
4021 {
4022         struct ixgbe_adapter *adapter = container_of(hw,
4023                                                      struct ixgbe_adapter, hw);
4024         struct ixgbe_mbx_info *mbx = &hw->mbx;
4025         struct ixgbe_mac_info *mac = &hw->mac;
4026         uint32_t links_reg, in_msg;
4027         int ret_val = 0;
4028
4029         /* If we were hit with a reset drop the link */
4030         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4031                 mac->get_link_status = true;
4032
4033         if (!mac->get_link_status)
4034                 goto out;
4035
4036         /* if link status is down no point in checking to see if pf is up */
4037         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4038         if (!(links_reg & IXGBE_LINKS_UP))
4039                 goto out;
4040
4041         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4042          * before the link status is correct
4043          */
4044         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4045                 int i;
4046
4047                 for (i = 0; i < 5; i++) {
4048                         rte_delay_us(100);
4049                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4050
4051                         if (!(links_reg & IXGBE_LINKS_UP))
4052                                 goto out;
4053                 }
4054         }
4055
4056         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4057         case IXGBE_LINKS_SPEED_10G_82599:
4058                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4059                 if (hw->mac.type >= ixgbe_mac_X550) {
4060                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4061                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4062                 }
4063                 break;
4064         case IXGBE_LINKS_SPEED_1G_82599:
4065                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4066                 break;
4067         case IXGBE_LINKS_SPEED_100_82599:
4068                 *speed = IXGBE_LINK_SPEED_100_FULL;
4069                 if (hw->mac.type == ixgbe_mac_X550) {
4070                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4071                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4072                 }
4073                 break;
4074         case IXGBE_LINKS_SPEED_10_X550EM_A:
4075                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4076                 /* Since Reserved in older MAC's */
4077                 if (hw->mac.type >= ixgbe_mac_X550)
4078                         *speed = IXGBE_LINK_SPEED_10_FULL;
4079                 break;
4080         default:
4081                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4082         }
4083
4084         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4085                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4086                         mac->get_link_status = true;
4087                 else
4088                         mac->get_link_status = false;
4089
4090                 goto out;
4091         }
4092
4093         /* if the read failed it could just be a mailbox collision, best wait
4094          * until we are called again and don't report an error
4095          */
4096         if (mbx->ops.read(hw, &in_msg, 1, 0))
4097                 goto out;
4098
4099         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4100                 /* msg is not CTS and is NACK we must have lost CTS status */
4101                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4102                         mac->get_link_status = false;
4103                 goto out;
4104         }
4105
4106         /* the pf is talking, if we timed out in the past we reinit */
4107         if (!mbx->timeout) {
4108                 ret_val = -1;
4109                 goto out;
4110         }
4111
4112         /* if we passed all the tests above then the link is up and we no
4113          * longer need to check for link
4114          */
4115         mac->get_link_status = false;
4116
4117 out:
4118         *link_up = !mac->get_link_status;
4119         return ret_val;
4120 }
4121
4122 /*
4123  * If @timeout_ms was 0, it means that it will not return until link complete.
4124  * It returns 1 on complete, return 0 on timeout.
4125  */
4126 static int
4127 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4128 {
4129 #define WARNING_TIMEOUT    9000 /* 9s  in total */
4130         struct ixgbe_adapter *ad = dev->data->dev_private;
4131         uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4132
4133         while (rte_atomic32_read(&ad->link_thread_running)) {
4134                 msec_delay(1);
4135                 timeout--;
4136
4137                 if (timeout_ms) {
4138                         if (!timeout)
4139                                 return 0;
4140                 } else if (!timeout) {
4141                         /* It will not return until link complete */
4142                         timeout = WARNING_TIMEOUT;
4143                         PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4144                 }
4145         }
4146
4147         return 1;
4148 }
4149
4150 static void *
4151 ixgbe_dev_setup_link_thread_handler(void *param)
4152 {
4153         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4154         struct ixgbe_adapter *ad = dev->data->dev_private;
4155         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4156         struct ixgbe_interrupt *intr =
4157                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4158         u32 speed;
4159         bool autoneg = false;
4160
4161         pthread_detach(pthread_self());
4162         speed = hw->phy.autoneg_advertised;
4163         if (!speed)
4164                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4165
4166         ixgbe_setup_link(hw, speed, true);
4167
4168         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4169         rte_atomic32_clear(&ad->link_thread_running);
4170         return NULL;
4171 }
4172
4173 /*
4174  * In freebsd environment, nic_uio drivers do not support interrupts,
4175  * rte_intr_callback_register() will fail to register interrupts.
4176  * We can not make link status to change from down to up by interrupt
4177  * callback. So we need to wait for the controller to acquire link
4178  * when ports start.
4179  * It returns 0 on link up.
4180  */
4181 static int
4182 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4183 {
4184 #ifdef RTE_EXEC_ENV_FREEBSD
4185         int err, i;
4186         bool link_up = false;
4187         uint32_t speed = 0;
4188         const int nb_iter = 25;
4189
4190         for (i = 0; i < nb_iter; i++) {
4191                 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4192                 if (err)
4193                         return err;
4194                 if (link_up)
4195                         return 0;
4196                 msec_delay(200);
4197         }
4198
4199         return 0;
4200 #else
4201         RTE_SET_USED(hw);
4202         return 0;
4203 #endif
4204 }
4205
4206 /* return 0 means link status changed, -1 means not changed */
4207 int
4208 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4209                             int wait_to_complete, int vf)
4210 {
4211         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4212         struct ixgbe_adapter *ad = dev->data->dev_private;
4213         struct rte_eth_link link;
4214         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4215         struct ixgbe_interrupt *intr =
4216                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4217         bool link_up;
4218         int diag;
4219         int wait = 1;
4220         u32 esdp_reg;
4221
4222         memset(&link, 0, sizeof(link));
4223         link.link_status = ETH_LINK_DOWN;
4224         link.link_speed = ETH_SPEED_NUM_NONE;
4225         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4226         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4227                         ETH_LINK_SPEED_FIXED);
4228
4229         hw->mac.get_link_status = true;
4230
4231         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4232                 return rte_eth_linkstatus_set(dev, &link);
4233
4234         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4235         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4236                 wait = 0;
4237
4238 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4239 #ifdef RTE_EXEC_ENV_FREEBSD
4240         wait = 1;
4241 #endif
4242
4243         if (vf)
4244                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4245         else
4246                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4247
4248         if (diag != 0) {
4249                 link.link_speed = ETH_SPEED_NUM_100M;
4250                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4251                 return rte_eth_linkstatus_set(dev, &link);
4252         }
4253
4254         if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4255                 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4256                 if ((esdp_reg & IXGBE_ESDP_SDP3))
4257                         link_up = 0;
4258         }
4259
4260         if (link_up == 0) {
4261                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4262                         ixgbe_dev_wait_setup_link_complete(dev, 0);
4263                         if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4264                                 /* To avoid race condition between threads, set
4265                                  * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4266                                  * when there is no link thread running.
4267                                  */
4268                                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4269                                 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4270                                         "ixgbe-link-handler",
4271                                         NULL,
4272                                         ixgbe_dev_setup_link_thread_handler,
4273                                         dev) < 0) {
4274                                         PMD_DRV_LOG(ERR,
4275                                                 "Create link thread failed!");
4276                                         rte_atomic32_clear(&ad->link_thread_running);
4277                                 }
4278                         } else {
4279                                 PMD_DRV_LOG(ERR,
4280                                         "Other link thread is running now!");
4281                         }
4282                 }
4283                 return rte_eth_linkstatus_set(dev, &link);
4284         }
4285
4286         link.link_status = ETH_LINK_UP;
4287         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4288
4289         switch (link_speed) {
4290         default:
4291         case IXGBE_LINK_SPEED_UNKNOWN:
4292                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
4293                 break;
4294
4295         case IXGBE_LINK_SPEED_10_FULL:
4296                 link.link_speed = ETH_SPEED_NUM_10M;
4297                 break;
4298
4299         case IXGBE_LINK_SPEED_100_FULL:
4300                 link.link_speed = ETH_SPEED_NUM_100M;
4301                 break;
4302
4303         case IXGBE_LINK_SPEED_1GB_FULL:
4304                 link.link_speed = ETH_SPEED_NUM_1G;
4305                 break;
4306
4307         case IXGBE_LINK_SPEED_2_5GB_FULL:
4308                 link.link_speed = ETH_SPEED_NUM_2_5G;
4309                 break;
4310
4311         case IXGBE_LINK_SPEED_5GB_FULL:
4312                 link.link_speed = ETH_SPEED_NUM_5G;
4313                 break;
4314
4315         case IXGBE_LINK_SPEED_10GB_FULL:
4316                 link.link_speed = ETH_SPEED_NUM_10G;
4317                 break;
4318         }
4319
4320         return rte_eth_linkstatus_set(dev, &link);
4321 }
4322
4323 static int
4324 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4325 {
4326         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4327 }
4328
4329 static int
4330 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4331 {
4332         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4333 }
4334
4335 static int
4336 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4337 {
4338         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4339         uint32_t fctrl;
4340
4341         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4342         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4343         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4344
4345         return 0;
4346 }
4347
4348 static int
4349 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4350 {
4351         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4352         uint32_t fctrl;
4353
4354         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4355         fctrl &= (~IXGBE_FCTRL_UPE);
4356         if (dev->data->all_multicast == 1)
4357                 fctrl |= IXGBE_FCTRL_MPE;
4358         else
4359                 fctrl &= (~IXGBE_FCTRL_MPE);
4360         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4361
4362         return 0;
4363 }
4364
4365 static int
4366 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4367 {
4368         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4369         uint32_t fctrl;
4370
4371         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4372         fctrl |= IXGBE_FCTRL_MPE;
4373         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4374
4375         return 0;
4376 }
4377
4378 static int
4379 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4380 {
4381         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4382         uint32_t fctrl;
4383
4384         if (dev->data->promiscuous == 1)
4385                 return 0; /* must remain in all_multicast mode */
4386
4387         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4388         fctrl &= (~IXGBE_FCTRL_MPE);
4389         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4390
4391         return 0;
4392 }
4393
4394 /**
4395  * It clears the interrupt causes and enables the interrupt.
4396  * It will be called once only during nic initialized.
4397  *
4398  * @param dev
4399  *  Pointer to struct rte_eth_dev.
4400  * @param on
4401  *  Enable or Disable.
4402  *
4403  * @return
4404  *  - On success, zero.
4405  *  - On failure, a negative value.
4406  */
4407 static int
4408 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4409 {
4410         struct ixgbe_interrupt *intr =
4411                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4412
4413         ixgbe_dev_link_status_print(dev);
4414         if (on)
4415                 intr->mask |= IXGBE_EICR_LSC;
4416         else
4417                 intr->mask &= ~IXGBE_EICR_LSC;
4418
4419         return 0;
4420 }
4421
4422 /**
4423  * It clears the interrupt causes and enables the interrupt.
4424  * It will be called once only during nic initialized.
4425  *
4426  * @param dev
4427  *  Pointer to struct rte_eth_dev.
4428  *
4429  * @return
4430  *  - On success, zero.
4431  *  - On failure, a negative value.
4432  */
4433 static int
4434 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4435 {
4436         struct ixgbe_interrupt *intr =
4437                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4438
4439         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4440
4441         return 0;
4442 }
4443
4444 /**
4445  * It clears the interrupt causes and enables the interrupt.
4446  * It will be called once only during nic initialized.
4447  *
4448  * @param dev
4449  *  Pointer to struct rte_eth_dev.
4450  *
4451  * @return
4452  *  - On success, zero.
4453  *  - On failure, a negative value.
4454  */
4455 static int
4456 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4457 {
4458         struct ixgbe_interrupt *intr =
4459                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4460
4461         intr->mask |= IXGBE_EICR_LINKSEC;
4462
4463         return 0;
4464 }
4465
4466 /*
4467  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4468  *
4469  * @param dev
4470  *  Pointer to struct rte_eth_dev.
4471  *
4472  * @return
4473  *  - On success, zero.
4474  *  - On failure, a negative value.
4475  */
4476 static int
4477 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4478 {
4479         uint32_t eicr;
4480         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4481         struct ixgbe_interrupt *intr =
4482                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4483
4484         /* clear all cause mask */
4485         ixgbe_disable_intr(hw);
4486
4487         /* read-on-clear nic registers here */
4488         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4489         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4490
4491         intr->flags = 0;
4492
4493         /* set flag for async link update */
4494         if (eicr & IXGBE_EICR_LSC)
4495                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4496
4497         if (eicr & IXGBE_EICR_MAILBOX)
4498                 intr->flags |= IXGBE_FLAG_MAILBOX;
4499
4500         if (eicr & IXGBE_EICR_LINKSEC)
4501                 intr->flags |= IXGBE_FLAG_MACSEC;
4502
4503         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4504             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4505             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4506                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4507
4508         return 0;
4509 }
4510
4511 /**
4512  * It gets and then prints the link status.
4513  *
4514  * @param dev
4515  *  Pointer to struct rte_eth_dev.
4516  *
4517  * @return
4518  *  - On success, zero.
4519  *  - On failure, a negative value.
4520  */
4521 static void
4522 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4523 {
4524         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4525         struct rte_eth_link link;
4526
4527         rte_eth_linkstatus_get(dev, &link);
4528
4529         if (link.link_status) {
4530                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4531                                         (int)(dev->data->port_id),
4532                                         (unsigned)link.link_speed,
4533                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4534                                         "full-duplex" : "half-duplex");
4535         } else {
4536                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4537                                 (int)(dev->data->port_id));
4538         }
4539         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4540                                 pci_dev->addr.domain,
4541                                 pci_dev->addr.bus,
4542                                 pci_dev->addr.devid,
4543                                 pci_dev->addr.function);
4544 }
4545
4546 /*
4547  * It executes link_update after knowing an interrupt occurred.
4548  *
4549  * @param dev
4550  *  Pointer to struct rte_eth_dev.
4551  *
4552  * @return
4553  *  - On success, zero.
4554  *  - On failure, a negative value.
4555  */
4556 static int
4557 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4558 {
4559         struct ixgbe_interrupt *intr =
4560                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4561         int64_t timeout;
4562         struct ixgbe_hw *hw =
4563                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4564
4565         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4566
4567         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4568                 ixgbe_pf_mbx_process(dev);
4569                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4570         }
4571
4572         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4573                 ixgbe_handle_lasi(hw);
4574                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4575         }
4576
4577         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4578                 struct rte_eth_link link;
4579
4580                 /* get the link status before link update, for predicting later */
4581                 rte_eth_linkstatus_get(dev, &link);
4582
4583                 ixgbe_dev_link_update(dev, 0);
4584
4585                 /* likely to up */
4586                 if (!link.link_status)
4587                         /* handle it 1 sec later, wait it being stable */
4588                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4589                 /* likely to down */
4590                 else
4591                         /* handle it 4 sec later, wait it being stable */
4592                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4593
4594                 ixgbe_dev_link_status_print(dev);
4595                 if (rte_eal_alarm_set(timeout * 1000,
4596                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4597                         PMD_DRV_LOG(ERR, "Error setting alarm");
4598                 else {
4599                         /* remember original mask */
4600                         intr->mask_original = intr->mask;
4601                         /* only disable lsc interrupt */
4602                         intr->mask &= ~IXGBE_EIMS_LSC;
4603                 }
4604         }
4605
4606         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4607         ixgbe_enable_intr(dev);
4608
4609         return 0;
4610 }
4611
4612 /**
4613  * Interrupt handler which shall be registered for alarm callback for delayed
4614  * handling specific interrupt to wait for the stable nic state. As the
4615  * NIC interrupt state is not stable for ixgbe after link is just down,
4616  * it needs to wait 4 seconds to get the stable status.
4617  *
4618  * @param handle
4619  *  Pointer to interrupt handle.
4620  * @param param
4621  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4622  *
4623  * @return
4624  *  void
4625  */
4626 static void
4627 ixgbe_dev_interrupt_delayed_handler(void *param)
4628 {
4629         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4630         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4631         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4632         struct ixgbe_interrupt *intr =
4633                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4634         struct ixgbe_hw *hw =
4635                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4636         uint32_t eicr;
4637
4638         ixgbe_disable_intr(hw);
4639
4640         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4641         if (eicr & IXGBE_EICR_MAILBOX)
4642                 ixgbe_pf_mbx_process(dev);
4643
4644         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4645                 ixgbe_handle_lasi(hw);
4646                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4647         }
4648
4649         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4650                 ixgbe_dev_link_update(dev, 0);
4651                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4652                 ixgbe_dev_link_status_print(dev);
4653                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4654         }
4655
4656         if (intr->flags & IXGBE_FLAG_MACSEC) {
4657                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL);
4658                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4659         }
4660
4661         /* restore original mask */
4662         intr->mask = intr->mask_original;
4663         intr->mask_original = 0;
4664
4665         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4666         ixgbe_enable_intr(dev);
4667         rte_intr_ack(intr_handle);
4668 }
4669
4670 /**
4671  * Interrupt handler triggered by NIC  for handling
4672  * specific interrupt.
4673  *
4674  * @param handle
4675  *  Pointer to interrupt handle.
4676  * @param param
4677  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4678  *
4679  * @return
4680  *  void
4681  */
4682 static void
4683 ixgbe_dev_interrupt_handler(void *param)
4684 {
4685         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4686
4687         ixgbe_dev_interrupt_get_status(dev);
4688         ixgbe_dev_interrupt_action(dev);
4689 }
4690
4691 static int
4692 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4693 {
4694         struct ixgbe_hw *hw;
4695
4696         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4697         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4698 }
4699
4700 static int
4701 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4702 {
4703         struct ixgbe_hw *hw;
4704
4705         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4706         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4707 }
4708
4709 static int
4710 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4711 {
4712         struct ixgbe_hw *hw;
4713         uint32_t mflcn_reg;
4714         uint32_t fccfg_reg;
4715         int rx_pause;
4716         int tx_pause;
4717
4718         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4719
4720         fc_conf->pause_time = hw->fc.pause_time;
4721         fc_conf->high_water = hw->fc.high_water[0];
4722         fc_conf->low_water = hw->fc.low_water[0];
4723         fc_conf->send_xon = hw->fc.send_xon;
4724         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4725
4726         /*
4727          * Return rx_pause status according to actual setting of
4728          * MFLCN register.
4729          */
4730         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4731         if (mflcn_reg & IXGBE_MFLCN_PMCF)
4732                 fc_conf->mac_ctrl_frame_fwd = 1;
4733         else
4734                 fc_conf->mac_ctrl_frame_fwd = 0;
4735
4736         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4737                 rx_pause = 1;
4738         else
4739                 rx_pause = 0;
4740
4741         /*
4742          * Return tx_pause status according to actual setting of
4743          * FCCFG register.
4744          */
4745         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4746         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4747                 tx_pause = 1;
4748         else
4749                 tx_pause = 0;
4750
4751         if (rx_pause && tx_pause)
4752                 fc_conf->mode = RTE_FC_FULL;
4753         else if (rx_pause)
4754                 fc_conf->mode = RTE_FC_RX_PAUSE;
4755         else if (tx_pause)
4756                 fc_conf->mode = RTE_FC_TX_PAUSE;
4757         else
4758                 fc_conf->mode = RTE_FC_NONE;
4759
4760         return 0;
4761 }
4762
4763 static int
4764 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4765 {
4766         struct ixgbe_hw *hw;
4767         struct ixgbe_adapter *adapter = dev->data->dev_private;
4768         int err;
4769         uint32_t rx_buf_size;
4770         uint32_t max_high_water;
4771         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4772                 ixgbe_fc_none,
4773                 ixgbe_fc_rx_pause,
4774                 ixgbe_fc_tx_pause,
4775                 ixgbe_fc_full
4776         };
4777
4778         PMD_INIT_FUNC_TRACE();
4779
4780         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4781         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4782         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4783
4784         /*
4785          * At least reserve one Ethernet frame for watermark
4786          * high_water/low_water in kilo bytes for ixgbe
4787          */
4788         max_high_water = (rx_buf_size -
4789                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4790         if ((fc_conf->high_water > max_high_water) ||
4791                 (fc_conf->high_water < fc_conf->low_water)) {
4792                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4793                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4794                 return -EINVAL;
4795         }
4796
4797         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4798         hw->fc.pause_time     = fc_conf->pause_time;
4799         hw->fc.high_water[0]  = fc_conf->high_water;
4800         hw->fc.low_water[0]   = fc_conf->low_water;
4801         hw->fc.send_xon       = fc_conf->send_xon;
4802         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4803         adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4804
4805         err = ixgbe_flow_ctrl_enable(dev, hw);
4806         if (err < 0) {
4807                 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4808                 return -EIO;
4809         }
4810         return err;
4811 }
4812
4813 /**
4814  *  ixgbe_pfc_enable_generic - Enable flow control
4815  *  @hw: pointer to hardware structure
4816  *  @tc_num: traffic class number
4817  *  Enable flow control according to the current settings.
4818  */
4819 static int
4820 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4821 {
4822         int ret_val = 0;
4823         uint32_t mflcn_reg, fccfg_reg;
4824         uint32_t reg;
4825         uint32_t fcrtl, fcrth;
4826         uint8_t i;
4827         uint8_t nb_rx_en;
4828
4829         /* Validate the water mark configuration */
4830         if (!hw->fc.pause_time) {
4831                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4832                 goto out;
4833         }
4834
4835         /* Low water mark of zero causes XOFF floods */
4836         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4837                  /* High/Low water can not be 0 */
4838                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4839                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4840                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4841                         goto out;
4842                 }
4843
4844                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4845                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4846                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4847                         goto out;
4848                 }
4849         }
4850         /* Negotiate the fc mode to use */
4851         ixgbe_fc_autoneg(hw);
4852
4853         /* Disable any previous flow control settings */
4854         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4855         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4856
4857         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4858         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4859
4860         switch (hw->fc.current_mode) {
4861         case ixgbe_fc_none:
4862                 /*
4863                  * If the count of enabled RX Priority Flow control >1,
4864                  * and the TX pause can not be disabled
4865                  */
4866                 nb_rx_en = 0;
4867                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4868                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4869                         if (reg & IXGBE_FCRTH_FCEN)
4870                                 nb_rx_en++;
4871                 }
4872                 if (nb_rx_en > 1)
4873                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4874                 break;
4875         case ixgbe_fc_rx_pause:
4876                 /*
4877                  * Rx Flow control is enabled and Tx Flow control is
4878                  * disabled by software override. Since there really
4879                  * isn't a way to advertise that we are capable of RX
4880                  * Pause ONLY, we will advertise that we support both
4881                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4882                  * disable the adapter's ability to send PAUSE frames.
4883                  */
4884                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4885                 /*
4886                  * If the count of enabled RX Priority Flow control >1,
4887                  * and the TX pause can not be disabled
4888                  */
4889                 nb_rx_en = 0;
4890                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4891                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4892                         if (reg & IXGBE_FCRTH_FCEN)
4893                                 nb_rx_en++;
4894                 }
4895                 if (nb_rx_en > 1)
4896                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4897                 break;
4898         case ixgbe_fc_tx_pause:
4899                 /*
4900                  * Tx Flow control is enabled, and Rx Flow control is
4901                  * disabled by software override.
4902                  */
4903                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4904                 break;
4905         case ixgbe_fc_full:
4906                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4907                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4908                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4909                 break;
4910         default:
4911                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4912                 ret_val = IXGBE_ERR_CONFIG;
4913                 goto out;
4914         }
4915
4916         /* Set 802.3x based flow control settings. */
4917         mflcn_reg |= IXGBE_MFLCN_DPF;
4918         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4919         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4920
4921         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4922         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4923                 hw->fc.high_water[tc_num]) {
4924                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4925                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4926                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4927         } else {
4928                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4929                 /*
4930                  * In order to prevent Tx hangs when the internal Tx
4931                  * switch is enabled we must set the high water mark
4932                  * to the maximum FCRTH value.  This allows the Tx
4933                  * switch to function even under heavy Rx workloads.
4934                  */
4935                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4936         }
4937         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4938
4939         /* Configure pause time (2 TCs per register) */
4940         reg = hw->fc.pause_time * 0x00010001;
4941         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4942                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4943
4944         /* Configure flow control refresh threshold value */
4945         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4946
4947 out:
4948         return ret_val;
4949 }
4950
4951 static int
4952 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4953 {
4954         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4955         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4956
4957         if (hw->mac.type != ixgbe_mac_82598EB) {
4958                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4959         }
4960         return ret_val;
4961 }
4962
4963 static int
4964 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4965 {
4966         int err;
4967         uint32_t rx_buf_size;
4968         uint32_t max_high_water;
4969         uint8_t tc_num;
4970         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4971         struct ixgbe_hw *hw =
4972                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4973         struct ixgbe_dcb_config *dcb_config =
4974                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4975
4976         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4977                 ixgbe_fc_none,
4978                 ixgbe_fc_rx_pause,
4979                 ixgbe_fc_tx_pause,
4980                 ixgbe_fc_full
4981         };
4982
4983         PMD_INIT_FUNC_TRACE();
4984
4985         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4986         tc_num = map[pfc_conf->priority];
4987         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4988         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4989         /*
4990          * At least reserve one Ethernet frame for watermark
4991          * high_water/low_water in kilo bytes for ixgbe
4992          */
4993         max_high_water = (rx_buf_size -
4994                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4995         if ((pfc_conf->fc.high_water > max_high_water) ||
4996             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4997                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4998                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4999                 return -EINVAL;
5000         }
5001
5002         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
5003         hw->fc.pause_time = pfc_conf->fc.pause_time;
5004         hw->fc.send_xon = pfc_conf->fc.send_xon;
5005         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
5006         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
5007
5008         err = ixgbe_dcb_pfc_enable(dev, tc_num);
5009
5010         /* Not negotiated is not an error case */
5011         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5012                 return 0;
5013
5014         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5015         return -EIO;
5016 }
5017
5018 static int
5019 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5020                           struct rte_eth_rss_reta_entry64 *reta_conf,
5021                           uint16_t reta_size)
5022 {
5023         uint16_t i, sp_reta_size;
5024         uint8_t j, mask;
5025         uint32_t reta, r;
5026         uint16_t idx, shift;
5027         struct ixgbe_adapter *adapter = dev->data->dev_private;
5028         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5029         uint32_t reta_reg;
5030
5031         PMD_INIT_FUNC_TRACE();
5032
5033         if (!ixgbe_rss_update_sp(hw->mac.type)) {
5034                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5035                         "NIC.");
5036                 return -ENOTSUP;
5037         }
5038
5039         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5040         if (reta_size != sp_reta_size) {
5041                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5042                         "(%d) doesn't match the number hardware can supported "
5043                         "(%d)", reta_size, sp_reta_size);
5044                 return -EINVAL;
5045         }
5046
5047         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5048                 idx = i / RTE_RETA_GROUP_SIZE;
5049                 shift = i % RTE_RETA_GROUP_SIZE;
5050                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5051                                                 IXGBE_4_BIT_MASK);
5052                 if (!mask)
5053                         continue;
5054                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5055                 if (mask == IXGBE_4_BIT_MASK)
5056                         r = 0;
5057                 else
5058                         r = IXGBE_READ_REG(hw, reta_reg);
5059                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5060                         if (mask & (0x1 << j))
5061                                 reta |= reta_conf[idx].reta[shift + j] <<
5062                                                         (CHAR_BIT * j);
5063                         else
5064                                 reta |= r & (IXGBE_8_BIT_MASK <<
5065                                                 (CHAR_BIT * j));
5066                 }
5067                 IXGBE_WRITE_REG(hw, reta_reg, reta);
5068         }
5069         adapter->rss_reta_updated = 1;
5070
5071         return 0;
5072 }
5073
5074 static int
5075 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5076                          struct rte_eth_rss_reta_entry64 *reta_conf,
5077                          uint16_t reta_size)
5078 {
5079         uint16_t i, sp_reta_size;
5080         uint8_t j, mask;
5081         uint32_t reta;
5082         uint16_t idx, shift;
5083         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5084         uint32_t reta_reg;
5085
5086         PMD_INIT_FUNC_TRACE();
5087         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5088         if (reta_size != sp_reta_size) {
5089                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5090                         "(%d) doesn't match the number hardware can supported "
5091                         "(%d)", reta_size, sp_reta_size);
5092                 return -EINVAL;
5093         }
5094
5095         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5096                 idx = i / RTE_RETA_GROUP_SIZE;
5097                 shift = i % RTE_RETA_GROUP_SIZE;
5098                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5099                                                 IXGBE_4_BIT_MASK);
5100                 if (!mask)
5101                         continue;
5102
5103                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5104                 reta = IXGBE_READ_REG(hw, reta_reg);
5105                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5106                         if (mask & (0x1 << j))
5107                                 reta_conf[idx].reta[shift + j] =
5108                                         ((reta >> (CHAR_BIT * j)) &
5109                                                 IXGBE_8_BIT_MASK);
5110                 }
5111         }
5112
5113         return 0;
5114 }
5115
5116 static int
5117 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5118                                 uint32_t index, uint32_t pool)
5119 {
5120         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5121         uint32_t enable_addr = 1;
5122
5123         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5124                              pool, enable_addr);
5125 }
5126
5127 static void
5128 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5129 {
5130         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5131
5132         ixgbe_clear_rar(hw, index);
5133 }
5134
5135 static int
5136 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5137 {
5138         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5139
5140         ixgbe_remove_rar(dev, 0);
5141         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5142
5143         return 0;
5144 }
5145
5146 static bool
5147 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5148 {
5149         if (strcmp(dev->device->driver->name, drv->driver.name))
5150                 return false;
5151
5152         return true;
5153 }
5154
5155 bool
5156 is_ixgbe_supported(struct rte_eth_dev *dev)
5157 {
5158         return is_device_supported(dev, &rte_ixgbe_pmd);
5159 }
5160
5161 static int
5162 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5163 {
5164         uint32_t hlreg0;
5165         uint32_t maxfrs;
5166         struct ixgbe_hw *hw;
5167         struct rte_eth_dev_info dev_info;
5168         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5169         struct rte_eth_dev_data *dev_data = dev->data;
5170         int ret;
5171
5172         ret = ixgbe_dev_info_get(dev, &dev_info);
5173         if (ret != 0)
5174                 return ret;
5175
5176         /* check that mtu is within the allowed range */
5177         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5178                 return -EINVAL;
5179
5180         /* If device is started, refuse mtu that requires the support of
5181          * scattered packets when this feature has not been enabled before.
5182          */
5183         if (dev_data->dev_started && !dev_data->scattered_rx &&
5184             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5185              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5186                 PMD_INIT_LOG(ERR, "Stop port first.");
5187                 return -EINVAL;
5188         }
5189
5190         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5191         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5192
5193         /* switch to jumbo mode if needed */
5194         if (frame_size > RTE_ETHER_MAX_LEN) {
5195                 dev->data->dev_conf.rxmode.offloads |=
5196                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5197                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5198         } else {
5199                 dev->data->dev_conf.rxmode.offloads &=
5200                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5201                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5202         }
5203         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5204
5205         /* update max frame size */
5206         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5207
5208         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5209         maxfrs &= 0x0000FFFF;
5210         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5211         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5212
5213         return 0;
5214 }
5215
5216 /*
5217  * Virtual Function operations
5218  */
5219 static void
5220 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5221 {
5222         struct ixgbe_interrupt *intr =
5223                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5224         struct ixgbe_hw *hw =
5225                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5226
5227         PMD_INIT_FUNC_TRACE();
5228
5229         /* Clear interrupt mask to stop from interrupts being generated */
5230         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5231
5232         IXGBE_WRITE_FLUSH(hw);
5233
5234         /* Clear mask value. */
5235         intr->mask = 0;
5236 }
5237
5238 static void
5239 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5240 {
5241         struct ixgbe_interrupt *intr =
5242                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5243         struct ixgbe_hw *hw =
5244                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5245
5246         PMD_INIT_FUNC_TRACE();
5247
5248         /* VF enable interrupt autoclean */
5249         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5250         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5251         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5252
5253         IXGBE_WRITE_FLUSH(hw);
5254
5255         /* Save IXGBE_VTEIMS value to mask. */
5256         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5257 }
5258
5259 static int
5260 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5261 {
5262         struct rte_eth_conf *conf = &dev->data->dev_conf;
5263         struct ixgbe_adapter *adapter = dev->data->dev_private;
5264
5265         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5266                      dev->data->port_id);
5267
5268         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5269                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5270
5271         /*
5272          * VF has no ability to enable/disable HW CRC
5273          * Keep the persistent behavior the same as Host PF
5274          */
5275 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5276         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5277                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5278                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5279         }
5280 #else
5281         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5282                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5283                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5284         }
5285 #endif
5286
5287         /*
5288          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5289          * allocation or vector Rx preconditions we will reset it.
5290          */
5291         adapter->rx_bulk_alloc_allowed = true;
5292         adapter->rx_vec_allowed = true;
5293
5294         return 0;
5295 }
5296
5297 static int
5298 ixgbevf_dev_start(struct rte_eth_dev *dev)
5299 {
5300         struct ixgbe_hw *hw =
5301                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5302         uint32_t intr_vector = 0;
5303         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5304         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5305
5306         int err, mask = 0;
5307
5308         PMD_INIT_FUNC_TRACE();
5309
5310         /* Stop the link setup handler before resetting the HW. */
5311         ixgbe_dev_wait_setup_link_complete(dev, 0);
5312
5313         err = hw->mac.ops.reset_hw(hw);
5314
5315         /**
5316          * In this case, reuses the MAC address assigned by VF
5317          * initialization.
5318          */
5319         if (err != IXGBE_SUCCESS && err != IXGBE_ERR_INVALID_MAC_ADDR) {
5320                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5321                 return err;
5322         }
5323
5324         hw->mac.get_link_status = true;
5325
5326         /* negotiate mailbox API version to use with the PF. */
5327         ixgbevf_negotiate_api(hw);
5328
5329         ixgbevf_dev_tx_init(dev);
5330
5331         /* This can fail when allocating mbufs for descriptor rings */
5332         err = ixgbevf_dev_rx_init(dev);
5333         if (err) {
5334                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5335                 ixgbe_dev_clear_queues(dev);
5336                 return err;
5337         }
5338
5339         /* Set vfta */
5340         ixgbevf_set_vfta_all(dev, 1);
5341
5342         /* Set HW strip */
5343         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5344                 ETH_VLAN_EXTEND_MASK;
5345         err = ixgbevf_vlan_offload_config(dev, mask);
5346         if (err) {
5347                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5348                 ixgbe_dev_clear_queues(dev);
5349                 return err;
5350         }
5351
5352         ixgbevf_dev_rxtx_start(dev);
5353
5354         /* check and configure queue intr-vector mapping */
5355         if (rte_intr_cap_multiple(intr_handle) &&
5356             dev->data->dev_conf.intr_conf.rxq) {
5357                 /* According to datasheet, only vector 0/1/2 can be used,
5358                  * now only one vector is used for Rx queue
5359                  */
5360                 intr_vector = 1;
5361                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5362                         return -1;
5363         }
5364
5365         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5366                 intr_handle->intr_vec =
5367                         rte_zmalloc("intr_vec",
5368                                     dev->data->nb_rx_queues * sizeof(int), 0);
5369                 if (intr_handle->intr_vec == NULL) {
5370                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5371                                      " intr_vec", dev->data->nb_rx_queues);
5372                         return -ENOMEM;
5373                 }
5374         }
5375         ixgbevf_configure_msix(dev);
5376
5377         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5378          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5379          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5380          * is not cleared, it will fail when following rte_intr_enable( ) tries
5381          * to map Rx queue interrupt to other VFIO vectors.
5382          * So clear uio/vfio intr/evevnfd first to avoid failure.
5383          */
5384         rte_intr_disable(intr_handle);
5385
5386         rte_intr_enable(intr_handle);
5387
5388         /* Re-enable interrupt for VF */
5389         ixgbevf_intr_enable(dev);
5390
5391         /*
5392          * Update link status right before return, because it may
5393          * start link configuration process in a separate thread.
5394          */
5395         ixgbevf_dev_link_update(dev, 0);
5396
5397         hw->adapter_stopped = false;
5398
5399         return 0;
5400 }
5401
5402 static void
5403 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5404 {
5405         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5406         struct ixgbe_adapter *adapter = dev->data->dev_private;
5407         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5408         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5409
5410         if (hw->adapter_stopped)
5411                 return;
5412
5413         PMD_INIT_FUNC_TRACE();
5414
5415         ixgbe_dev_wait_setup_link_complete(dev, 0);
5416
5417         ixgbevf_intr_disable(dev);
5418
5419         hw->adapter_stopped = 1;
5420         ixgbe_stop_adapter(hw);
5421
5422         /*
5423           * Clear what we set, but we still keep shadow_vfta to
5424           * restore after device starts
5425           */
5426         ixgbevf_set_vfta_all(dev, 0);
5427
5428         /* Clear stored conf */
5429         dev->data->scattered_rx = 0;
5430
5431         ixgbe_dev_clear_queues(dev);
5432
5433         /* Clean datapath event and queue/vec mapping */
5434         rte_intr_efd_disable(intr_handle);
5435         if (intr_handle->intr_vec != NULL) {
5436                 rte_free(intr_handle->intr_vec);
5437                 intr_handle->intr_vec = NULL;
5438         }
5439
5440         adapter->rss_reta_updated = 0;
5441 }
5442
5443 static int
5444 ixgbevf_dev_close(struct rte_eth_dev *dev)
5445 {
5446         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5447         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5448         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5449
5450         PMD_INIT_FUNC_TRACE();
5451
5452         ixgbe_reset_hw(hw);
5453
5454         ixgbevf_dev_stop(dev);
5455
5456         ixgbe_dev_free_queues(dev);
5457
5458         /**
5459          * Remove the VF MAC address ro ensure
5460          * that the VF traffic goes to the PF
5461          * after stop, close and detach of the VF
5462          **/
5463         ixgbevf_remove_mac_addr(dev, 0);
5464
5465         dev->dev_ops = NULL;
5466         dev->rx_pkt_burst = NULL;
5467         dev->tx_pkt_burst = NULL;
5468
5469         rte_intr_disable(intr_handle);
5470         rte_intr_callback_unregister(intr_handle,
5471                                      ixgbevf_dev_interrupt_handler, dev);
5472
5473         return 0;
5474 }
5475
5476 /*
5477  * Reset VF device
5478  */
5479 static int
5480 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5481 {
5482         int ret;
5483
5484         ret = eth_ixgbevf_dev_uninit(dev);
5485         if (ret)
5486                 return ret;
5487
5488         ret = eth_ixgbevf_dev_init(dev);
5489
5490         return ret;
5491 }
5492
5493 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5494 {
5495         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5496         struct ixgbe_vfta *shadow_vfta =
5497                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5498         int i = 0, j = 0, vfta = 0, mask = 1;
5499
5500         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5501                 vfta = shadow_vfta->vfta[i];
5502                 if (vfta) {
5503                         mask = 1;
5504                         for (j = 0; j < 32; j++) {
5505                                 if (vfta & mask)
5506                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5507                                                        on, false);
5508                                 mask <<= 1;
5509                         }
5510                 }
5511         }
5512
5513 }
5514
5515 static int
5516 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5517 {
5518         struct ixgbe_hw *hw =
5519                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5520         struct ixgbe_vfta *shadow_vfta =
5521                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5522         uint32_t vid_idx = 0;
5523         uint32_t vid_bit = 0;
5524         int ret = 0;
5525
5526         PMD_INIT_FUNC_TRACE();
5527
5528         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5529         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5530         if (ret) {
5531                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5532                 return ret;
5533         }
5534         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5535         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5536
5537         /* Save what we set and retore it after device reset */
5538         if (on)
5539                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5540         else
5541                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5542
5543         return 0;
5544 }
5545
5546 static void
5547 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5548 {
5549         struct ixgbe_hw *hw =
5550                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5551         uint32_t ctrl;
5552
5553         PMD_INIT_FUNC_TRACE();
5554
5555         if (queue >= hw->mac.max_rx_queues)
5556                 return;
5557
5558         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5559         if (on)
5560                 ctrl |= IXGBE_RXDCTL_VME;
5561         else
5562                 ctrl &= ~IXGBE_RXDCTL_VME;
5563         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5564
5565         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5566 }
5567
5568 static int
5569 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5570 {
5571         struct ixgbe_rx_queue *rxq;
5572         uint16_t i;
5573         int on = 0;
5574
5575         /* VF function only support hw strip feature, others are not support */
5576         if (mask & ETH_VLAN_STRIP_MASK) {
5577                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5578                         rxq = dev->data->rx_queues[i];
5579                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5580                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5581                 }
5582         }
5583
5584         return 0;
5585 }
5586
5587 static int
5588 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5589 {
5590         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5591
5592         ixgbevf_vlan_offload_config(dev, mask);
5593
5594         return 0;
5595 }
5596
5597 int
5598 ixgbe_vt_check(struct ixgbe_hw *hw)
5599 {
5600         uint32_t reg_val;
5601
5602         /* if Virtualization Technology is enabled */
5603         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5604         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5605                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5606                 return -1;
5607         }
5608
5609         return 0;
5610 }
5611
5612 static uint32_t
5613 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5614 {
5615         uint32_t vector = 0;
5616
5617         switch (hw->mac.mc_filter_type) {
5618         case 0:   /* use bits [47:36] of the address */
5619                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5620                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5621                 break;
5622         case 1:   /* use bits [46:35] of the address */
5623                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5624                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5625                 break;
5626         case 2:   /* use bits [45:34] of the address */
5627                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5628                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5629                 break;
5630         case 3:   /* use bits [43:32] of the address */
5631                 vector = ((uc_addr->addr_bytes[4]) |
5632                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5633                 break;
5634         default:  /* Invalid mc_filter_type */
5635                 break;
5636         }
5637
5638         /* vector can only be 12-bits or boundary will be exceeded */
5639         vector &= 0xFFF;
5640         return vector;
5641 }
5642
5643 static int
5644 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5645                         struct rte_ether_addr *mac_addr, uint8_t on)
5646 {
5647         uint32_t vector;
5648         uint32_t uta_idx;
5649         uint32_t reg_val;
5650         uint32_t uta_shift;
5651         uint32_t rc;
5652         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5653         const uint32_t ixgbe_uta_bit_shift = 5;
5654         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5655         const uint32_t bit1 = 0x1;
5656
5657         struct ixgbe_hw *hw =
5658                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5659         struct ixgbe_uta_info *uta_info =
5660                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5661
5662         /* The UTA table only exists on 82599 hardware and newer */
5663         if (hw->mac.type < ixgbe_mac_82599EB)
5664                 return -ENOTSUP;
5665
5666         vector = ixgbe_uta_vector(hw, mac_addr);
5667         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5668         uta_shift = vector & ixgbe_uta_bit_mask;
5669
5670         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5671         if (rc == on)
5672                 return 0;
5673
5674         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5675         if (on) {
5676                 uta_info->uta_in_use++;
5677                 reg_val |= (bit1 << uta_shift);
5678                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5679         } else {
5680                 uta_info->uta_in_use--;
5681                 reg_val &= ~(bit1 << uta_shift);
5682                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5683         }
5684
5685         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5686
5687         if (uta_info->uta_in_use > 0)
5688                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5689                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5690         else
5691                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5692
5693         return 0;
5694 }
5695
5696 static int
5697 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5698 {
5699         int i;
5700         struct ixgbe_hw *hw =
5701                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5702         struct ixgbe_uta_info *uta_info =
5703                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5704
5705         /* The UTA table only exists on 82599 hardware and newer */
5706         if (hw->mac.type < ixgbe_mac_82599EB)
5707                 return -ENOTSUP;
5708
5709         if (on) {
5710                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5711                         uta_info->uta_shadow[i] = ~0;
5712                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5713                 }
5714         } else {
5715                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5716                         uta_info->uta_shadow[i] = 0;
5717                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5718                 }
5719         }
5720         return 0;
5721
5722 }
5723
5724 uint32_t
5725 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5726 {
5727         uint32_t new_val = orig_val;
5728
5729         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5730                 new_val |= IXGBE_VMOLR_AUPE;
5731         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5732                 new_val |= IXGBE_VMOLR_ROMPE;
5733         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5734                 new_val |= IXGBE_VMOLR_ROPE;
5735         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5736                 new_val |= IXGBE_VMOLR_BAM;
5737         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5738                 new_val |= IXGBE_VMOLR_MPE;
5739
5740         return new_val;
5741 }
5742
5743 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5744 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5745 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5746 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5747 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5748         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5749         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5750
5751 static int
5752 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5753                       struct rte_eth_mirror_conf *mirror_conf,
5754                       uint8_t rule_id, uint8_t on)
5755 {
5756         uint32_t mr_ctl, vlvf;
5757         uint32_t mp_lsb = 0;
5758         uint32_t mv_msb = 0;
5759         uint32_t mv_lsb = 0;
5760         uint32_t mp_msb = 0;
5761         uint8_t i = 0;
5762         int reg_index = 0;
5763         uint64_t vlan_mask = 0;
5764
5765         const uint8_t pool_mask_offset = 32;
5766         const uint8_t vlan_mask_offset = 32;
5767         const uint8_t dst_pool_offset = 8;
5768         const uint8_t rule_mr_offset  = 4;
5769         const uint8_t mirror_rule_mask = 0x0F;
5770
5771         struct ixgbe_mirror_info *mr_info =
5772                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5773         struct ixgbe_hw *hw =
5774                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5775         uint8_t mirror_type = 0;
5776
5777         if (ixgbe_vt_check(hw) < 0)
5778                 return -ENOTSUP;
5779
5780         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5781                 return -EINVAL;
5782
5783         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5784                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5785                             mirror_conf->rule_type);
5786                 return -EINVAL;
5787         }
5788
5789         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5790                 mirror_type |= IXGBE_MRCTL_VLME;
5791                 /* Check if vlan id is valid and find conresponding VLAN ID
5792                  * index in VLVF
5793                  */
5794                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5795                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5796                                 /* search vlan id related pool vlan filter
5797                                  * index
5798                                  */
5799                                 reg_index = ixgbe_find_vlvf_slot(
5800                                                 hw,
5801                                                 mirror_conf->vlan.vlan_id[i],
5802                                                 false);
5803                                 if (reg_index < 0)
5804                                         return -EINVAL;
5805                                 vlvf = IXGBE_READ_REG(hw,
5806                                                       IXGBE_VLVF(reg_index));
5807                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5808                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5809                                       mirror_conf->vlan.vlan_id[i]))
5810                                         vlan_mask |= (1ULL << reg_index);
5811                                 else
5812                                         return -EINVAL;
5813                         }
5814                 }
5815
5816                 if (on) {
5817                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5818                         mv_msb = vlan_mask >> vlan_mask_offset;
5819
5820                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5821                                                 mirror_conf->vlan.vlan_mask;
5822                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5823                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5824                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5825                                                 mirror_conf->vlan.vlan_id[i];
5826                         }
5827                 } else {
5828                         mv_lsb = 0;
5829                         mv_msb = 0;
5830                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5831                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5832                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5833                 }
5834         }
5835
5836         /**
5837          * if enable pool mirror, write related pool mask register,if disable
5838          * pool mirror, clear PFMRVM register
5839          */
5840         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5841                 mirror_type |= IXGBE_MRCTL_VPME;
5842                 if (on) {
5843                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5844                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5845                         mr_info->mr_conf[rule_id].pool_mask =
5846                                         mirror_conf->pool_mask;
5847
5848                 } else {
5849                         mp_lsb = 0;
5850                         mp_msb = 0;
5851                         mr_info->mr_conf[rule_id].pool_mask = 0;
5852                 }
5853         }
5854         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5855                 mirror_type |= IXGBE_MRCTL_UPME;
5856         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5857                 mirror_type |= IXGBE_MRCTL_DPME;
5858
5859         /* read  mirror control register and recalculate it */
5860         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5861
5862         if (on) {
5863                 mr_ctl |= mirror_type;
5864                 mr_ctl &= mirror_rule_mask;
5865                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5866         } else {
5867                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5868         }
5869
5870         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5871         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5872
5873         /* write mirrror control  register */
5874         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5875
5876         /* write pool mirrror control  register */
5877         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5878                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5879                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5880                                 mp_msb);
5881         }
5882         /* write VLAN mirrror control  register */
5883         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5884                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5885                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5886                                 mv_msb);
5887         }
5888
5889         return 0;
5890 }
5891
5892 static int
5893 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5894 {
5895         int mr_ctl = 0;
5896         uint32_t lsb_val = 0;
5897         uint32_t msb_val = 0;
5898         const uint8_t rule_mr_offset = 4;
5899
5900         struct ixgbe_hw *hw =
5901                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5902         struct ixgbe_mirror_info *mr_info =
5903                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5904
5905         if (ixgbe_vt_check(hw) < 0)
5906                 return -ENOTSUP;
5907
5908         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5909                 return -EINVAL;
5910
5911         memset(&mr_info->mr_conf[rule_id], 0,
5912                sizeof(struct rte_eth_mirror_conf));
5913
5914         /* clear PFVMCTL register */
5915         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5916
5917         /* clear pool mask register */
5918         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5919         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5920
5921         /* clear vlan mask register */
5922         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5923         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5924
5925         return 0;
5926 }
5927
5928 static int
5929 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5930 {
5931         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5932         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5933         struct ixgbe_interrupt *intr =
5934                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5935         struct ixgbe_hw *hw =
5936                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5937         uint32_t vec = IXGBE_MISC_VEC_ID;
5938
5939         if (rte_intr_allow_others(intr_handle))
5940                 vec = IXGBE_RX_VEC_START;
5941         intr->mask |= (1 << vec);
5942         RTE_SET_USED(queue_id);
5943         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5944
5945         rte_intr_ack(intr_handle);
5946
5947         return 0;
5948 }
5949
5950 static int
5951 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5952 {
5953         struct ixgbe_interrupt *intr =
5954                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5955         struct ixgbe_hw *hw =
5956                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5957         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5958         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5959         uint32_t vec = IXGBE_MISC_VEC_ID;
5960
5961         if (rte_intr_allow_others(intr_handle))
5962                 vec = IXGBE_RX_VEC_START;
5963         intr->mask &= ~(1 << vec);
5964         RTE_SET_USED(queue_id);
5965         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5966
5967         return 0;
5968 }
5969
5970 static int
5971 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5972 {
5973         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5974         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5975         uint32_t mask;
5976         struct ixgbe_hw *hw =
5977                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5978         struct ixgbe_interrupt *intr =
5979                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5980
5981         if (queue_id < 16) {
5982                 ixgbe_disable_intr(hw);
5983                 intr->mask |= (1 << queue_id);
5984                 ixgbe_enable_intr(dev);
5985         } else if (queue_id < 32) {
5986                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5987                 mask &= (1 << queue_id);
5988                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5989         } else if (queue_id < 64) {
5990                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5991                 mask &= (1 << (queue_id - 32));
5992                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5993         }
5994         rte_intr_ack(intr_handle);
5995
5996         return 0;
5997 }
5998
5999 static int
6000 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
6001 {
6002         uint32_t mask;
6003         struct ixgbe_hw *hw =
6004                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6005         struct ixgbe_interrupt *intr =
6006                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
6007
6008         if (queue_id < 16) {
6009                 ixgbe_disable_intr(hw);
6010                 intr->mask &= ~(1 << queue_id);
6011                 ixgbe_enable_intr(dev);
6012         } else if (queue_id < 32) {
6013                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
6014                 mask &= ~(1 << queue_id);
6015                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6016         } else if (queue_id < 64) {
6017                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6018                 mask &= ~(1 << (queue_id - 32));
6019                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6020         }
6021
6022         return 0;
6023 }
6024
6025 static void
6026 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6027                      uint8_t queue, uint8_t msix_vector)
6028 {
6029         uint32_t tmp, idx;
6030
6031         if (direction == -1) {
6032                 /* other causes */
6033                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6034                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
6035                 tmp &= ~0xFF;
6036                 tmp |= msix_vector;
6037                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6038         } else {
6039                 /* rx or tx cause */
6040                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6041                 idx = ((16 * (queue & 1)) + (8 * direction));
6042                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6043                 tmp &= ~(0xFF << idx);
6044                 tmp |= (msix_vector << idx);
6045                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6046         }
6047 }
6048
6049 /**
6050  * set the IVAR registers, mapping interrupt causes to vectors
6051  * @param hw
6052  *  pointer to ixgbe_hw struct
6053  * @direction
6054  *  0 for Rx, 1 for Tx, -1 for other causes
6055  * @queue
6056  *  queue to map the corresponding interrupt to
6057  * @msix_vector
6058  *  the vector to map to the corresponding queue
6059  */
6060 static void
6061 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6062                    uint8_t queue, uint8_t msix_vector)
6063 {
6064         uint32_t tmp, idx;
6065
6066         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6067         if (hw->mac.type == ixgbe_mac_82598EB) {
6068                 if (direction == -1)
6069                         direction = 0;
6070                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6071                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6072                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6073                 tmp |= (msix_vector << (8 * (queue & 0x3)));
6074                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6075         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6076                         (hw->mac.type == ixgbe_mac_X540) ||
6077                         (hw->mac.type == ixgbe_mac_X550) ||
6078                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
6079                 if (direction == -1) {
6080                         /* other causes */
6081                         idx = ((queue & 1) * 8);
6082                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6083                         tmp &= ~(0xFF << idx);
6084                         tmp |= (msix_vector << idx);
6085                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6086                 } else {
6087                         /* rx or tx causes */
6088                         idx = ((16 * (queue & 1)) + (8 * direction));
6089                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6090                         tmp &= ~(0xFF << idx);
6091                         tmp |= (msix_vector << idx);
6092                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6093                 }
6094         }
6095 }
6096
6097 static void
6098 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6099 {
6100         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6101         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6102         struct ixgbe_hw *hw =
6103                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6104         uint32_t q_idx;
6105         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6106         uint32_t base = IXGBE_MISC_VEC_ID;
6107
6108         /* Configure VF other cause ivar */
6109         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6110
6111         /* won't configure msix register if no mapping is done
6112          * between intr vector and event fd.
6113          */
6114         if (!rte_intr_dp_is_en(intr_handle))
6115                 return;
6116
6117         if (rte_intr_allow_others(intr_handle)) {
6118                 base = IXGBE_RX_VEC_START;
6119                 vector_idx = IXGBE_RX_VEC_START;
6120         }
6121
6122         /* Configure all RX queues of VF */
6123         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6124                 /* Force all queue use vector 0,
6125                  * as IXGBE_VF_MAXMSIVECOTR = 1
6126                  */
6127                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6128                 intr_handle->intr_vec[q_idx] = vector_idx;
6129                 if (vector_idx < base + intr_handle->nb_efd - 1)
6130                         vector_idx++;
6131         }
6132
6133         /* As RX queue setting above show, all queues use the vector 0.
6134          * Set only the ITR value of IXGBE_MISC_VEC_ID.
6135          */
6136         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6137                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6138                         | IXGBE_EITR_CNT_WDIS);
6139 }
6140
6141 /**
6142  * Sets up the hardware to properly generate MSI-X interrupts
6143  * @hw
6144  *  board private structure
6145  */
6146 static void
6147 ixgbe_configure_msix(struct rte_eth_dev *dev)
6148 {
6149         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6150         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6151         struct ixgbe_hw *hw =
6152                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6153         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6154         uint32_t vec = IXGBE_MISC_VEC_ID;
6155         uint32_t mask;
6156         uint32_t gpie;
6157
6158         /* won't configure msix register if no mapping is done
6159          * between intr vector and event fd
6160          * but if misx has been enabled already, need to configure
6161          * auto clean, auto mask and throttling.
6162          */
6163         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6164         if (!rte_intr_dp_is_en(intr_handle) &&
6165             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6166                 return;
6167
6168         if (rte_intr_allow_others(intr_handle))
6169                 vec = base = IXGBE_RX_VEC_START;
6170
6171         /* setup GPIE for MSI-x mode */
6172         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6173         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6174                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6175         /* auto clearing and auto setting corresponding bits in EIMS
6176          * when MSI-X interrupt is triggered
6177          */
6178         if (hw->mac.type == ixgbe_mac_82598EB) {
6179                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6180         } else {
6181                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6182                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6183         }
6184         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6185
6186         /* Populate the IVAR table and set the ITR values to the
6187          * corresponding register.
6188          */
6189         if (rte_intr_dp_is_en(intr_handle)) {
6190                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6191                         queue_id++) {
6192                         /* by default, 1:1 mapping */
6193                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6194                         intr_handle->intr_vec[queue_id] = vec;
6195                         if (vec < base + intr_handle->nb_efd - 1)
6196                                 vec++;
6197                 }
6198
6199                 switch (hw->mac.type) {
6200                 case ixgbe_mac_82598EB:
6201                         ixgbe_set_ivar_map(hw, -1,
6202                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6203                                            IXGBE_MISC_VEC_ID);
6204                         break;
6205                 case ixgbe_mac_82599EB:
6206                 case ixgbe_mac_X540:
6207                 case ixgbe_mac_X550:
6208                 case ixgbe_mac_X550EM_x:
6209                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6210                         break;
6211                 default:
6212                         break;
6213                 }
6214         }
6215         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6216                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6217                         | IXGBE_EITR_CNT_WDIS);
6218
6219         /* set up to autoclear timer, and the vectors */
6220         mask = IXGBE_EIMS_ENABLE_MASK;
6221         mask &= ~(IXGBE_EIMS_OTHER |
6222                   IXGBE_EIMS_MAILBOX |
6223                   IXGBE_EIMS_LSC);
6224
6225         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6226 }
6227
6228 int
6229 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6230                            uint16_t queue_idx, uint16_t tx_rate)
6231 {
6232         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6233         struct rte_eth_rxmode *rxmode;
6234         uint32_t rf_dec, rf_int;
6235         uint32_t bcnrc_val;
6236         uint16_t link_speed = dev->data->dev_link.link_speed;
6237
6238         if (queue_idx >= hw->mac.max_tx_queues)
6239                 return -EINVAL;
6240
6241         if (tx_rate != 0) {
6242                 /* Calculate the rate factor values to set */
6243                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6244                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6245                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6246
6247                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6248                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6249                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6250                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6251         } else {
6252                 bcnrc_val = 0;
6253         }
6254
6255         rxmode = &dev->data->dev_conf.rxmode;
6256         /*
6257          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6258          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6259          * set as 0x4.
6260          */
6261         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6262             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6263                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6264                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6265         else
6266                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6267                         IXGBE_MMW_SIZE_DEFAULT);
6268
6269         /* Set RTTBCNRC of queue X */
6270         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6271         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6272         IXGBE_WRITE_FLUSH(hw);
6273
6274         return 0;
6275 }
6276
6277 static int
6278 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6279                      __rte_unused uint32_t index,
6280                      __rte_unused uint32_t pool)
6281 {
6282         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6283         int diag;
6284
6285         /*
6286          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6287          * operation. Trap this case to avoid exhausting the [very limited]
6288          * set of PF resources used to store VF MAC addresses.
6289          */
6290         if (memcmp(hw->mac.perm_addr, mac_addr,
6291                         sizeof(struct rte_ether_addr)) == 0)
6292                 return -1;
6293         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6294         if (diag != 0)
6295                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6296                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6297                             mac_addr->addr_bytes[0],
6298                             mac_addr->addr_bytes[1],
6299                             mac_addr->addr_bytes[2],
6300                             mac_addr->addr_bytes[3],
6301                             mac_addr->addr_bytes[4],
6302                             mac_addr->addr_bytes[5],
6303                             diag);
6304         return diag;
6305 }
6306
6307 static void
6308 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6309 {
6310         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6311         struct rte_ether_addr *perm_addr =
6312                 (struct rte_ether_addr *)hw->mac.perm_addr;
6313         struct rte_ether_addr *mac_addr;
6314         uint32_t i;
6315         int diag;
6316
6317         /*
6318          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6319          * not support the deletion of a given MAC address.
6320          * Instead, it imposes to delete all MAC addresses, then to add again
6321          * all MAC addresses with the exception of the one to be deleted.
6322          */
6323         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6324
6325         /*
6326          * Add again all MAC addresses, with the exception of the deleted one
6327          * and of the permanent MAC address.
6328          */
6329         for (i = 0, mac_addr = dev->data->mac_addrs;
6330              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6331                 /* Skip the deleted MAC address */
6332                 if (i == index)
6333                         continue;
6334                 /* Skip NULL MAC addresses */
6335                 if (rte_is_zero_ether_addr(mac_addr))
6336                         continue;
6337                 /* Skip the permanent MAC address */
6338                 if (memcmp(perm_addr, mac_addr,
6339                                 sizeof(struct rte_ether_addr)) == 0)
6340                         continue;
6341                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6342                 if (diag != 0)
6343                         PMD_DRV_LOG(ERR,
6344                                     "Adding again MAC address "
6345                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6346                                     "diag=%d",
6347                                     mac_addr->addr_bytes[0],
6348                                     mac_addr->addr_bytes[1],
6349                                     mac_addr->addr_bytes[2],
6350                                     mac_addr->addr_bytes[3],
6351                                     mac_addr->addr_bytes[4],
6352                                     mac_addr->addr_bytes[5],
6353                                     diag);
6354         }
6355 }
6356
6357 static int
6358 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6359                         struct rte_ether_addr *addr)
6360 {
6361         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6362
6363         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6364
6365         return 0;
6366 }
6367
6368 int
6369 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6370                         struct rte_eth_syn_filter *filter,
6371                         bool add)
6372 {
6373         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6374         struct ixgbe_filter_info *filter_info =
6375                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6376         uint32_t syn_info;
6377         uint32_t synqf;
6378
6379         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6380                 return -EINVAL;
6381
6382         syn_info = filter_info->syn_info;
6383
6384         if (add) {
6385                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6386                         return -EINVAL;
6387                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6388                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6389
6390                 if (filter->hig_pri)
6391                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6392                 else
6393                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6394         } else {
6395                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6396                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6397                         return -ENOENT;
6398                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6399         }
6400
6401         filter_info->syn_info = synqf;
6402         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6403         IXGBE_WRITE_FLUSH(hw);
6404         return 0;
6405 }
6406
6407 static int
6408 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6409                         struct rte_eth_syn_filter *filter)
6410 {
6411         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6412         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6413
6414         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6415                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6416                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6417                 return 0;
6418         }
6419         return -ENOENT;
6420 }
6421
6422 static int
6423 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6424                         enum rte_filter_op filter_op,
6425                         void *arg)
6426 {
6427         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6428         int ret;
6429
6430         MAC_TYPE_FILTER_SUP(hw->mac.type);
6431
6432         if (filter_op == RTE_ETH_FILTER_NOP)
6433                 return 0;
6434
6435         if (arg == NULL) {
6436                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6437                             filter_op);
6438                 return -EINVAL;
6439         }
6440
6441         switch (filter_op) {
6442         case RTE_ETH_FILTER_ADD:
6443                 ret = ixgbe_syn_filter_set(dev,
6444                                 (struct rte_eth_syn_filter *)arg,
6445                                 TRUE);
6446                 break;
6447         case RTE_ETH_FILTER_DELETE:
6448                 ret = ixgbe_syn_filter_set(dev,
6449                                 (struct rte_eth_syn_filter *)arg,
6450                                 FALSE);
6451                 break;
6452         case RTE_ETH_FILTER_GET:
6453                 ret = ixgbe_syn_filter_get(dev,
6454                                 (struct rte_eth_syn_filter *)arg);
6455                 break;
6456         default:
6457                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6458                 ret = -EINVAL;
6459                 break;
6460         }
6461
6462         return ret;
6463 }
6464
6465
6466 static inline enum ixgbe_5tuple_protocol
6467 convert_protocol_type(uint8_t protocol_value)
6468 {
6469         if (protocol_value == IPPROTO_TCP)
6470                 return IXGBE_FILTER_PROTOCOL_TCP;
6471         else if (protocol_value == IPPROTO_UDP)
6472                 return IXGBE_FILTER_PROTOCOL_UDP;
6473         else if (protocol_value == IPPROTO_SCTP)
6474                 return IXGBE_FILTER_PROTOCOL_SCTP;
6475         else
6476                 return IXGBE_FILTER_PROTOCOL_NONE;
6477 }
6478
6479 /* inject a 5-tuple filter to HW */
6480 static inline void
6481 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6482                            struct ixgbe_5tuple_filter *filter)
6483 {
6484         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6485         int i;
6486         uint32_t ftqf, sdpqf;
6487         uint32_t l34timir = 0;
6488         uint8_t mask = 0xff;
6489
6490         i = filter->index;
6491
6492         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6493                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6494         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6495
6496         ftqf = (uint32_t)(filter->filter_info.proto &
6497                 IXGBE_FTQF_PROTOCOL_MASK);
6498         ftqf |= (uint32_t)((filter->filter_info.priority &
6499                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6500         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6501                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6502         if (filter->filter_info.dst_ip_mask == 0)
6503                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6504         if (filter->filter_info.src_port_mask == 0)
6505                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6506         if (filter->filter_info.dst_port_mask == 0)
6507                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6508         if (filter->filter_info.proto_mask == 0)
6509                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6510         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6511         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6512         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6513
6514         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6515         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6516         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6517         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6518
6519         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6520         l34timir |= (uint32_t)(filter->queue <<
6521                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6522         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6523 }
6524
6525 /*
6526  * add a 5tuple filter
6527  *
6528  * @param
6529  * dev: Pointer to struct rte_eth_dev.
6530  * index: the index the filter allocates.
6531  * filter: ponter to the filter that will be added.
6532  * rx_queue: the queue id the filter assigned to.
6533  *
6534  * @return
6535  *    - On success, zero.
6536  *    - On failure, a negative value.
6537  */
6538 static int
6539 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6540                         struct ixgbe_5tuple_filter *filter)
6541 {
6542         struct ixgbe_filter_info *filter_info =
6543                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6544         int i, idx, shift;
6545
6546         /*
6547          * look for an unused 5tuple filter index,
6548          * and insert the filter to list.
6549          */
6550         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6551                 idx = i / (sizeof(uint32_t) * NBBY);
6552                 shift = i % (sizeof(uint32_t) * NBBY);
6553                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6554                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6555                         filter->index = i;
6556                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6557                                           filter,
6558                                           entries);
6559                         break;
6560                 }
6561         }
6562         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6563                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6564                 return -ENOSYS;
6565         }
6566
6567         ixgbe_inject_5tuple_filter(dev, filter);
6568
6569         return 0;
6570 }
6571
6572 /*
6573  * remove a 5tuple filter
6574  *
6575  * @param
6576  * dev: Pointer to struct rte_eth_dev.
6577  * filter: the pointer of the filter will be removed.
6578  */
6579 static void
6580 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6581                         struct ixgbe_5tuple_filter *filter)
6582 {
6583         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6584         struct ixgbe_filter_info *filter_info =
6585                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6586         uint16_t index = filter->index;
6587
6588         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6589                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6590         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6591         rte_free(filter);
6592
6593         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6594         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6595         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6596         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6597         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6598 }
6599
6600 static int
6601 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6602 {
6603         struct ixgbe_hw *hw;
6604         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6605         struct rte_eth_dev_data *dev_data = dev->data;
6606
6607         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6608
6609         if (mtu < RTE_ETHER_MIN_MTU ||
6610                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6611                 return -EINVAL;
6612
6613         /* If device is started, refuse mtu that requires the support of
6614          * scattered packets when this feature has not been enabled before.
6615          */
6616         if (dev_data->dev_started && !dev_data->scattered_rx &&
6617             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6618              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6619                 PMD_INIT_LOG(ERR, "Stop port first.");
6620                 return -EINVAL;
6621         }
6622
6623         /*
6624          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6625          * request of the version 2.0 of the mailbox API.
6626          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6627          * of the mailbox API.
6628          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6629          * prior to 3.11.33 which contains the following change:
6630          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6631          */
6632         ixgbevf_rlpml_set_vf(hw, max_frame);
6633
6634         /* update max frame size */
6635         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6636         return 0;
6637 }
6638
6639 static inline struct ixgbe_5tuple_filter *
6640 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6641                         struct ixgbe_5tuple_filter_info *key)
6642 {
6643         struct ixgbe_5tuple_filter *it;
6644
6645         TAILQ_FOREACH(it, filter_list, entries) {
6646                 if (memcmp(key, &it->filter_info,
6647                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6648                         return it;
6649                 }
6650         }
6651         return NULL;
6652 }
6653
6654 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6655 static inline int
6656 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6657                         struct ixgbe_5tuple_filter_info *filter_info)
6658 {
6659         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6660                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6661                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6662                 return -EINVAL;
6663
6664         switch (filter->dst_ip_mask) {
6665         case UINT32_MAX:
6666                 filter_info->dst_ip_mask = 0;
6667                 filter_info->dst_ip = filter->dst_ip;
6668                 break;
6669         case 0:
6670                 filter_info->dst_ip_mask = 1;
6671                 break;
6672         default:
6673                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6674                 return -EINVAL;
6675         }
6676
6677         switch (filter->src_ip_mask) {
6678         case UINT32_MAX:
6679                 filter_info->src_ip_mask = 0;
6680                 filter_info->src_ip = filter->src_ip;
6681                 break;
6682         case 0:
6683                 filter_info->src_ip_mask = 1;
6684                 break;
6685         default:
6686                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6687                 return -EINVAL;
6688         }
6689
6690         switch (filter->dst_port_mask) {
6691         case UINT16_MAX:
6692                 filter_info->dst_port_mask = 0;
6693                 filter_info->dst_port = filter->dst_port;
6694                 break;
6695         case 0:
6696                 filter_info->dst_port_mask = 1;
6697                 break;
6698         default:
6699                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6700                 return -EINVAL;
6701         }
6702
6703         switch (filter->src_port_mask) {
6704         case UINT16_MAX:
6705                 filter_info->src_port_mask = 0;
6706                 filter_info->src_port = filter->src_port;
6707                 break;
6708         case 0:
6709                 filter_info->src_port_mask = 1;
6710                 break;
6711         default:
6712                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6713                 return -EINVAL;
6714         }
6715
6716         switch (filter->proto_mask) {
6717         case UINT8_MAX:
6718                 filter_info->proto_mask = 0;
6719                 filter_info->proto =
6720                         convert_protocol_type(filter->proto);
6721                 break;
6722         case 0:
6723                 filter_info->proto_mask = 1;
6724                 break;
6725         default:
6726                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6727                 return -EINVAL;
6728         }
6729
6730         filter_info->priority = (uint8_t)filter->priority;
6731         return 0;
6732 }
6733
6734 /*
6735  * add or delete a ntuple filter
6736  *
6737  * @param
6738  * dev: Pointer to struct rte_eth_dev.
6739  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6740  * add: if true, add filter, if false, remove filter
6741  *
6742  * @return
6743  *    - On success, zero.
6744  *    - On failure, a negative value.
6745  */
6746 int
6747 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6748                         struct rte_eth_ntuple_filter *ntuple_filter,
6749                         bool add)
6750 {
6751         struct ixgbe_filter_info *filter_info =
6752                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6753         struct ixgbe_5tuple_filter_info filter_5tuple;
6754         struct ixgbe_5tuple_filter *filter;
6755         int ret;
6756
6757         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6758                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6759                 return -EINVAL;
6760         }
6761
6762         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6763         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6764         if (ret < 0)
6765                 return ret;
6766
6767         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6768                                          &filter_5tuple);
6769         if (filter != NULL && add) {
6770                 PMD_DRV_LOG(ERR, "filter exists.");
6771                 return -EEXIST;
6772         }
6773         if (filter == NULL && !add) {
6774                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6775                 return -ENOENT;
6776         }
6777
6778         if (add) {
6779                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6780                                 sizeof(struct ixgbe_5tuple_filter), 0);
6781                 if (filter == NULL)
6782                         return -ENOMEM;
6783                 rte_memcpy(&filter->filter_info,
6784                                  &filter_5tuple,
6785                                  sizeof(struct ixgbe_5tuple_filter_info));
6786                 filter->queue = ntuple_filter->queue;
6787                 ret = ixgbe_add_5tuple_filter(dev, filter);
6788                 if (ret < 0) {
6789                         rte_free(filter);
6790                         return ret;
6791                 }
6792         } else
6793                 ixgbe_remove_5tuple_filter(dev, filter);
6794
6795         return 0;
6796 }
6797
6798 /*
6799  * get a ntuple filter
6800  *
6801  * @param
6802  * dev: Pointer to struct rte_eth_dev.
6803  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6804  *
6805  * @return
6806  *    - On success, zero.
6807  *    - On failure, a negative value.
6808  */
6809 static int
6810 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6811                         struct rte_eth_ntuple_filter *ntuple_filter)
6812 {
6813         struct ixgbe_filter_info *filter_info =
6814                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6815         struct ixgbe_5tuple_filter_info filter_5tuple;
6816         struct ixgbe_5tuple_filter *filter;
6817         int ret;
6818
6819         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6820                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6821                 return -EINVAL;
6822         }
6823
6824         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6825         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6826         if (ret < 0)
6827                 return ret;
6828
6829         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6830                                          &filter_5tuple);
6831         if (filter == NULL) {
6832                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6833                 return -ENOENT;
6834         }
6835         ntuple_filter->queue = filter->queue;
6836         return 0;
6837 }
6838
6839 /*
6840  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6841  * @dev: pointer to rte_eth_dev structure
6842  * @filter_op:operation will be taken.
6843  * @arg: a pointer to specific structure corresponding to the filter_op
6844  *
6845  * @return
6846  *    - On success, zero.
6847  *    - On failure, a negative value.
6848  */
6849 static int
6850 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6851                                 enum rte_filter_op filter_op,
6852                                 void *arg)
6853 {
6854         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6855         int ret;
6856
6857         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6858
6859         if (filter_op == RTE_ETH_FILTER_NOP)
6860                 return 0;
6861
6862         if (arg == NULL) {
6863                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6864                             filter_op);
6865                 return -EINVAL;
6866         }
6867
6868         switch (filter_op) {
6869         case RTE_ETH_FILTER_ADD:
6870                 ret = ixgbe_add_del_ntuple_filter(dev,
6871                         (struct rte_eth_ntuple_filter *)arg,
6872                         TRUE);
6873                 break;
6874         case RTE_ETH_FILTER_DELETE:
6875                 ret = ixgbe_add_del_ntuple_filter(dev,
6876                         (struct rte_eth_ntuple_filter *)arg,
6877                         FALSE);
6878                 break;
6879         case RTE_ETH_FILTER_GET:
6880                 ret = ixgbe_get_ntuple_filter(dev,
6881                         (struct rte_eth_ntuple_filter *)arg);
6882                 break;
6883         default:
6884                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6885                 ret = -EINVAL;
6886                 break;
6887         }
6888         return ret;
6889 }
6890
6891 int
6892 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6893                         struct rte_eth_ethertype_filter *filter,
6894                         bool add)
6895 {
6896         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6897         struct ixgbe_filter_info *filter_info =
6898                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6899         uint32_t etqf = 0;
6900         uint32_t etqs = 0;
6901         int ret;
6902         struct ixgbe_ethertype_filter ethertype_filter;
6903
6904         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6905                 return -EINVAL;
6906
6907         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6908                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6909                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6910                         " ethertype filter.", filter->ether_type);
6911                 return -EINVAL;
6912         }
6913
6914         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6915                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6916                 return -EINVAL;
6917         }
6918         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6919                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6920                 return -EINVAL;
6921         }
6922
6923         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6924         if (ret >= 0 && add) {
6925                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6926                             filter->ether_type);
6927                 return -EEXIST;
6928         }
6929         if (ret < 0 && !add) {
6930                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6931                             filter->ether_type);
6932                 return -ENOENT;
6933         }
6934
6935         if (add) {
6936                 etqf = IXGBE_ETQF_FILTER_EN;
6937                 etqf |= (uint32_t)filter->ether_type;
6938                 etqs |= (uint32_t)((filter->queue <<
6939                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6940                                     IXGBE_ETQS_RX_QUEUE);
6941                 etqs |= IXGBE_ETQS_QUEUE_EN;
6942
6943                 ethertype_filter.ethertype = filter->ether_type;
6944                 ethertype_filter.etqf = etqf;
6945                 ethertype_filter.etqs = etqs;
6946                 ethertype_filter.conf = FALSE;
6947                 ret = ixgbe_ethertype_filter_insert(filter_info,
6948                                                     &ethertype_filter);
6949                 if (ret < 0) {
6950                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6951                         return -ENOSPC;
6952                 }
6953         } else {
6954                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6955                 if (ret < 0)
6956                         return -ENOSYS;
6957         }
6958         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6959         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6960         IXGBE_WRITE_FLUSH(hw);
6961
6962         return 0;
6963 }
6964
6965 static int
6966 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6967                         struct rte_eth_ethertype_filter *filter)
6968 {
6969         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6970         struct ixgbe_filter_info *filter_info =
6971                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6972         uint32_t etqf, etqs;
6973         int ret;
6974
6975         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6976         if (ret < 0) {
6977                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6978                             filter->ether_type);
6979                 return -ENOENT;
6980         }
6981
6982         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6983         if (etqf & IXGBE_ETQF_FILTER_EN) {
6984                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6985                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6986                 filter->flags = 0;
6987                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6988                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6989                 return 0;
6990         }
6991         return -ENOENT;
6992 }
6993
6994 /*
6995  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6996  * @dev: pointer to rte_eth_dev structure
6997  * @filter_op:operation will be taken.
6998  * @arg: a pointer to specific structure corresponding to the filter_op
6999  */
7000 static int
7001 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
7002                                 enum rte_filter_op filter_op,
7003                                 void *arg)
7004 {
7005         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7006         int ret;
7007
7008         MAC_TYPE_FILTER_SUP(hw->mac.type);
7009
7010         if (filter_op == RTE_ETH_FILTER_NOP)
7011                 return 0;
7012
7013         if (arg == NULL) {
7014                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7015                             filter_op);
7016                 return -EINVAL;
7017         }
7018
7019         switch (filter_op) {
7020         case RTE_ETH_FILTER_ADD:
7021                 ret = ixgbe_add_del_ethertype_filter(dev,
7022                         (struct rte_eth_ethertype_filter *)arg,
7023                         TRUE);
7024                 break;
7025         case RTE_ETH_FILTER_DELETE:
7026                 ret = ixgbe_add_del_ethertype_filter(dev,
7027                         (struct rte_eth_ethertype_filter *)arg,
7028                         FALSE);
7029                 break;
7030         case RTE_ETH_FILTER_GET:
7031                 ret = ixgbe_get_ethertype_filter(dev,
7032                         (struct rte_eth_ethertype_filter *)arg);
7033                 break;
7034         default:
7035                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7036                 ret = -EINVAL;
7037                 break;
7038         }
7039         return ret;
7040 }
7041
7042 static int
7043 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
7044                      enum rte_filter_type filter_type,
7045                      enum rte_filter_op filter_op,
7046                      void *arg)
7047 {
7048         int ret = 0;
7049
7050         switch (filter_type) {
7051         case RTE_ETH_FILTER_NTUPLE:
7052                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
7053                 break;
7054         case RTE_ETH_FILTER_ETHERTYPE:
7055                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
7056                 break;
7057         case RTE_ETH_FILTER_SYN:
7058                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
7059                 break;
7060         case RTE_ETH_FILTER_FDIR:
7061                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
7062                 break;
7063         case RTE_ETH_FILTER_L2_TUNNEL:
7064                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
7065                 break;
7066         case RTE_ETH_FILTER_GENERIC:
7067                 if (filter_op != RTE_ETH_FILTER_GET)
7068                         return -EINVAL;
7069                 *(const void **)arg = &ixgbe_flow_ops;
7070                 break;
7071         default:
7072                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7073                                                         filter_type);
7074                 ret = -EINVAL;
7075                 break;
7076         }
7077
7078         return ret;
7079 }
7080
7081 static u8 *
7082 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
7083                         u8 **mc_addr_ptr, u32 *vmdq)
7084 {
7085         u8 *mc_addr;
7086
7087         *vmdq = 0;
7088         mc_addr = *mc_addr_ptr;
7089         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
7090         return mc_addr;
7091 }
7092
7093 static int
7094 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
7095                           struct rte_ether_addr *mc_addr_set,
7096                           uint32_t nb_mc_addr)
7097 {
7098         struct ixgbe_hw *hw;
7099         u8 *mc_addr_list;
7100
7101         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7102         mc_addr_list = (u8 *)mc_addr_set;
7103         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
7104                                          ixgbe_dev_addr_list_itr, TRUE);
7105 }
7106
7107 static uint64_t
7108 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
7109 {
7110         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7111         uint64_t systime_cycles;
7112
7113         switch (hw->mac.type) {
7114         case ixgbe_mac_X550:
7115         case ixgbe_mac_X550EM_x:
7116         case ixgbe_mac_X550EM_a:
7117                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
7118                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7119                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7120                                 * NSEC_PER_SEC;
7121                 break;
7122         default:
7123                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7124                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7125                                 << 32;
7126         }
7127
7128         return systime_cycles;
7129 }
7130
7131 static uint64_t
7132 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7133 {
7134         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7135         uint64_t rx_tstamp_cycles;
7136
7137         switch (hw->mac.type) {
7138         case ixgbe_mac_X550:
7139         case ixgbe_mac_X550EM_x:
7140         case ixgbe_mac_X550EM_a:
7141                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7142                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7143                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7144                                 * NSEC_PER_SEC;
7145                 break;
7146         default:
7147                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7148                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7149                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7150                                 << 32;
7151         }
7152
7153         return rx_tstamp_cycles;
7154 }
7155
7156 static uint64_t
7157 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7158 {
7159         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7160         uint64_t tx_tstamp_cycles;
7161
7162         switch (hw->mac.type) {
7163         case ixgbe_mac_X550:
7164         case ixgbe_mac_X550EM_x:
7165         case ixgbe_mac_X550EM_a:
7166                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7167                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7168                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7169                                 * NSEC_PER_SEC;
7170                 break;
7171         default:
7172                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7173                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7174                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7175                                 << 32;
7176         }
7177
7178         return tx_tstamp_cycles;
7179 }
7180
7181 static void
7182 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7183 {
7184         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7185         struct ixgbe_adapter *adapter = dev->data->dev_private;
7186         struct rte_eth_link link;
7187         uint32_t incval = 0;
7188         uint32_t shift = 0;
7189
7190         /* Get current link speed. */
7191         ixgbe_dev_link_update(dev, 1);
7192         rte_eth_linkstatus_get(dev, &link);
7193
7194         switch (link.link_speed) {
7195         case ETH_SPEED_NUM_100M:
7196                 incval = IXGBE_INCVAL_100;
7197                 shift = IXGBE_INCVAL_SHIFT_100;
7198                 break;
7199         case ETH_SPEED_NUM_1G:
7200                 incval = IXGBE_INCVAL_1GB;
7201                 shift = IXGBE_INCVAL_SHIFT_1GB;
7202                 break;
7203         case ETH_SPEED_NUM_10G:
7204         default:
7205                 incval = IXGBE_INCVAL_10GB;
7206                 shift = IXGBE_INCVAL_SHIFT_10GB;
7207                 break;
7208         }
7209
7210         switch (hw->mac.type) {
7211         case ixgbe_mac_X550:
7212         case ixgbe_mac_X550EM_x:
7213         case ixgbe_mac_X550EM_a:
7214                 /* Independent of link speed. */
7215                 incval = 1;
7216                 /* Cycles read will be interpreted as ns. */
7217                 shift = 0;
7218                 /* Fall-through */
7219         case ixgbe_mac_X540:
7220                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7221                 break;
7222         case ixgbe_mac_82599EB:
7223                 incval >>= IXGBE_INCVAL_SHIFT_82599;
7224                 shift -= IXGBE_INCVAL_SHIFT_82599;
7225                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7226                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7227                 break;
7228         default:
7229                 /* Not supported. */
7230                 return;
7231         }
7232
7233         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7234         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7235         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7236
7237         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7238         adapter->systime_tc.cc_shift = shift;
7239         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7240
7241         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7242         adapter->rx_tstamp_tc.cc_shift = shift;
7243         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7244
7245         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7246         adapter->tx_tstamp_tc.cc_shift = shift;
7247         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7248 }
7249
7250 static int
7251 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7252 {
7253         struct ixgbe_adapter *adapter = dev->data->dev_private;
7254
7255         adapter->systime_tc.nsec += delta;
7256         adapter->rx_tstamp_tc.nsec += delta;
7257         adapter->tx_tstamp_tc.nsec += delta;
7258
7259         return 0;
7260 }
7261
7262 static int
7263 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7264 {
7265         uint64_t ns;
7266         struct ixgbe_adapter *adapter = dev->data->dev_private;
7267
7268         ns = rte_timespec_to_ns(ts);
7269         /* Set the timecounters to a new value. */
7270         adapter->systime_tc.nsec = ns;
7271         adapter->rx_tstamp_tc.nsec = ns;
7272         adapter->tx_tstamp_tc.nsec = ns;
7273
7274         return 0;
7275 }
7276
7277 static int
7278 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7279 {
7280         uint64_t ns, systime_cycles;
7281         struct ixgbe_adapter *adapter = dev->data->dev_private;
7282
7283         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7284         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7285         *ts = rte_ns_to_timespec(ns);
7286
7287         return 0;
7288 }
7289
7290 static int
7291 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7292 {
7293         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7294         uint32_t tsync_ctl;
7295         uint32_t tsauxc;
7296
7297         /* Stop the timesync system time. */
7298         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7299         /* Reset the timesync system time value. */
7300         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7301         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7302
7303         /* Enable system time for platforms where it isn't on by default. */
7304         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7305         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7306         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7307
7308         ixgbe_start_timecounters(dev);
7309
7310         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7311         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7312                         (RTE_ETHER_TYPE_1588 |
7313                          IXGBE_ETQF_FILTER_EN |
7314                          IXGBE_ETQF_1588));
7315
7316         /* Enable timestamping of received PTP packets. */
7317         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7318         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7319         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7320
7321         /* Enable timestamping of transmitted PTP packets. */
7322         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7323         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7324         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7325
7326         IXGBE_WRITE_FLUSH(hw);
7327
7328         return 0;
7329 }
7330
7331 static int
7332 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7333 {
7334         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7335         uint32_t tsync_ctl;
7336
7337         /* Disable timestamping of transmitted PTP packets. */
7338         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7339         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7340         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7341
7342         /* Disable timestamping of received PTP packets. */
7343         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7344         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7345         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7346
7347         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7348         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7349
7350         /* Stop incrementating the System Time registers. */
7351         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7352
7353         return 0;
7354 }
7355
7356 static int
7357 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7358                                  struct timespec *timestamp,
7359                                  uint32_t flags __rte_unused)
7360 {
7361         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7362         struct ixgbe_adapter *adapter = dev->data->dev_private;
7363         uint32_t tsync_rxctl;
7364         uint64_t rx_tstamp_cycles;
7365         uint64_t ns;
7366
7367         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7368         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7369                 return -EINVAL;
7370
7371         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7372         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7373         *timestamp = rte_ns_to_timespec(ns);
7374
7375         return  0;
7376 }
7377
7378 static int
7379 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7380                                  struct timespec *timestamp)
7381 {
7382         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7383         struct ixgbe_adapter *adapter = dev->data->dev_private;
7384         uint32_t tsync_txctl;
7385         uint64_t tx_tstamp_cycles;
7386         uint64_t ns;
7387
7388         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7389         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7390                 return -EINVAL;
7391
7392         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7393         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7394         *timestamp = rte_ns_to_timespec(ns);
7395
7396         return 0;
7397 }
7398
7399 static int
7400 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7401 {
7402         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7403         int count = 0;
7404         int g_ind = 0;
7405         const struct reg_info *reg_group;
7406         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7407                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7408
7409         while ((reg_group = reg_set[g_ind++]))
7410                 count += ixgbe_regs_group_count(reg_group);
7411
7412         return count;
7413 }
7414
7415 static int
7416 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7417 {
7418         int count = 0;
7419         int g_ind = 0;
7420         const struct reg_info *reg_group;
7421
7422         while ((reg_group = ixgbevf_regs[g_ind++]))
7423                 count += ixgbe_regs_group_count(reg_group);
7424
7425         return count;
7426 }
7427
7428 static int
7429 ixgbe_get_regs(struct rte_eth_dev *dev,
7430               struct rte_dev_reg_info *regs)
7431 {
7432         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7433         uint32_t *data = regs->data;
7434         int g_ind = 0;
7435         int count = 0;
7436         const struct reg_info *reg_group;
7437         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7438                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7439
7440         if (data == NULL) {
7441                 regs->length = ixgbe_get_reg_length(dev);
7442                 regs->width = sizeof(uint32_t);
7443                 return 0;
7444         }
7445
7446         /* Support only full register dump */
7447         if ((regs->length == 0) ||
7448             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7449                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7450                         hw->device_id;
7451                 while ((reg_group = reg_set[g_ind++]))
7452                         count += ixgbe_read_regs_group(dev, &data[count],
7453                                 reg_group);
7454                 return 0;
7455         }
7456
7457         return -ENOTSUP;
7458 }
7459
7460 static int
7461 ixgbevf_get_regs(struct rte_eth_dev *dev,
7462                 struct rte_dev_reg_info *regs)
7463 {
7464         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7465         uint32_t *data = regs->data;
7466         int g_ind = 0;
7467         int count = 0;
7468         const struct reg_info *reg_group;
7469
7470         if (data == NULL) {
7471                 regs->length = ixgbevf_get_reg_length(dev);
7472                 regs->width = sizeof(uint32_t);
7473                 return 0;
7474         }
7475
7476         /* Support only full register dump */
7477         if ((regs->length == 0) ||
7478             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7479                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7480                         hw->device_id;
7481                 while ((reg_group = ixgbevf_regs[g_ind++]))
7482                         count += ixgbe_read_regs_group(dev, &data[count],
7483                                                       reg_group);
7484                 return 0;
7485         }
7486
7487         return -ENOTSUP;
7488 }
7489
7490 static int
7491 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7492 {
7493         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7494
7495         /* Return unit is byte count */
7496         return hw->eeprom.word_size * 2;
7497 }
7498
7499 static int
7500 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7501                 struct rte_dev_eeprom_info *in_eeprom)
7502 {
7503         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7504         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7505         uint16_t *data = in_eeprom->data;
7506         int first, length;
7507
7508         first = in_eeprom->offset >> 1;
7509         length = in_eeprom->length >> 1;
7510         if ((first > hw->eeprom.word_size) ||
7511             ((first + length) > hw->eeprom.word_size))
7512                 return -EINVAL;
7513
7514         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7515
7516         return eeprom->ops.read_buffer(hw, first, length, data);
7517 }
7518
7519 static int
7520 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7521                 struct rte_dev_eeprom_info *in_eeprom)
7522 {
7523         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7524         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7525         uint16_t *data = in_eeprom->data;
7526         int first, length;
7527
7528         first = in_eeprom->offset >> 1;
7529         length = in_eeprom->length >> 1;
7530         if ((first > hw->eeprom.word_size) ||
7531             ((first + length) > hw->eeprom.word_size))
7532                 return -EINVAL;
7533
7534         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7535
7536         return eeprom->ops.write_buffer(hw,  first, length, data);
7537 }
7538
7539 static int
7540 ixgbe_get_module_info(struct rte_eth_dev *dev,
7541                       struct rte_eth_dev_module_info *modinfo)
7542 {
7543         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7544         uint32_t status;
7545         uint8_t sff8472_rev, addr_mode;
7546         bool page_swap = false;
7547
7548         /* Check whether we support SFF-8472 or not */
7549         status = hw->phy.ops.read_i2c_eeprom(hw,
7550                                              IXGBE_SFF_SFF_8472_COMP,
7551                                              &sff8472_rev);
7552         if (status != 0)
7553                 return -EIO;
7554
7555         /* addressing mode is not supported */
7556         status = hw->phy.ops.read_i2c_eeprom(hw,
7557                                              IXGBE_SFF_SFF_8472_SWAP,
7558                                              &addr_mode);
7559         if (status != 0)
7560                 return -EIO;
7561
7562         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7563                 PMD_DRV_LOG(ERR,
7564                             "Address change required to access page 0xA2, "
7565                             "but not supported. Please report the module "
7566                             "type to the driver maintainers.");
7567                 page_swap = true;
7568         }
7569
7570         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7571                 /* We have a SFP, but it does not support SFF-8472 */
7572                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7573                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7574         } else {
7575                 /* We have a SFP which supports a revision of SFF-8472. */
7576                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7577                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7578         }
7579
7580         return 0;
7581 }
7582
7583 static int
7584 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7585                         struct rte_dev_eeprom_info *info)
7586 {
7587         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7588         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7589         uint8_t databyte = 0xFF;
7590         uint8_t *data = info->data;
7591         uint32_t i = 0;
7592
7593         if (info->length == 0)
7594                 return -EINVAL;
7595
7596         for (i = info->offset; i < info->offset + info->length; i++) {
7597                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7598                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7599                 else
7600                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7601
7602                 if (status != 0)
7603                         return -EIO;
7604
7605                 data[i - info->offset] = databyte;
7606         }
7607
7608         return 0;
7609 }
7610
7611 uint16_t
7612 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7613         switch (mac_type) {
7614         case ixgbe_mac_X550:
7615         case ixgbe_mac_X550EM_x:
7616         case ixgbe_mac_X550EM_a:
7617                 return ETH_RSS_RETA_SIZE_512;
7618         case ixgbe_mac_X550_vf:
7619         case ixgbe_mac_X550EM_x_vf:
7620         case ixgbe_mac_X550EM_a_vf:
7621                 return ETH_RSS_RETA_SIZE_64;
7622         case ixgbe_mac_X540_vf:
7623         case ixgbe_mac_82599_vf:
7624                 return 0;
7625         default:
7626                 return ETH_RSS_RETA_SIZE_128;
7627         }
7628 }
7629
7630 uint32_t
7631 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7632         switch (mac_type) {
7633         case ixgbe_mac_X550:
7634         case ixgbe_mac_X550EM_x:
7635         case ixgbe_mac_X550EM_a:
7636                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7637                         return IXGBE_RETA(reta_idx >> 2);
7638                 else
7639                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7640         case ixgbe_mac_X550_vf:
7641         case ixgbe_mac_X550EM_x_vf:
7642         case ixgbe_mac_X550EM_a_vf:
7643                 return IXGBE_VFRETA(reta_idx >> 2);
7644         default:
7645                 return IXGBE_RETA(reta_idx >> 2);
7646         }
7647 }
7648
7649 uint32_t
7650 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7651         switch (mac_type) {
7652         case ixgbe_mac_X550_vf:
7653         case ixgbe_mac_X550EM_x_vf:
7654         case ixgbe_mac_X550EM_a_vf:
7655                 return IXGBE_VFMRQC;
7656         default:
7657                 return IXGBE_MRQC;
7658         }
7659 }
7660
7661 uint32_t
7662 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7663         switch (mac_type) {
7664         case ixgbe_mac_X550_vf:
7665         case ixgbe_mac_X550EM_x_vf:
7666         case ixgbe_mac_X550EM_a_vf:
7667                 return IXGBE_VFRSSRK(i);
7668         default:
7669                 return IXGBE_RSSRK(i);
7670         }
7671 }
7672
7673 bool
7674 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7675         switch (mac_type) {
7676         case ixgbe_mac_82599_vf:
7677         case ixgbe_mac_X540_vf:
7678                 return 0;
7679         default:
7680                 return 1;
7681         }
7682 }
7683
7684 static int
7685 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7686                         struct rte_eth_dcb_info *dcb_info)
7687 {
7688         struct ixgbe_dcb_config *dcb_config =
7689                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7690         struct ixgbe_dcb_tc_config *tc;
7691         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7692         uint8_t nb_tcs;
7693         uint8_t i, j;
7694
7695         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7696                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7697         else
7698                 dcb_info->nb_tcs = 1;
7699
7700         tc_queue = &dcb_info->tc_queue;
7701         nb_tcs = dcb_info->nb_tcs;
7702
7703         if (dcb_config->vt_mode) { /* vt is enabled*/
7704                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7705                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7706                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7707                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7708                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7709                         for (j = 0; j < nb_tcs; j++) {
7710                                 tc_queue->tc_rxq[0][j].base = j;
7711                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7712                                 tc_queue->tc_txq[0][j].base = j;
7713                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7714                         }
7715                 } else {
7716                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7717                                 for (j = 0; j < nb_tcs; j++) {
7718                                         tc_queue->tc_rxq[i][j].base =
7719                                                 i * nb_tcs + j;
7720                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7721                                         tc_queue->tc_txq[i][j].base =
7722                                                 i * nb_tcs + j;
7723                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7724                                 }
7725                         }
7726                 }
7727         } else { /* vt is disabled*/
7728                 struct rte_eth_dcb_rx_conf *rx_conf =
7729                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7730                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7731                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7732                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7733                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7734                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7735                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7736                         }
7737                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7738                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7739                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7740                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7741                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7742                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7743                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7744                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7745                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7746                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7747                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7748                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7749                         }
7750                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7751                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7752                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7753                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7754                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7755                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7756                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7757                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7758                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7759                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7760                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7761                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7762                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7763                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7764                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7765                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7766                 }
7767         }
7768         for (i = 0; i < dcb_info->nb_tcs; i++) {
7769                 tc = &dcb_config->tc_config[i];
7770                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7771         }
7772         return 0;
7773 }
7774
7775 /* Update e-tag ether type */
7776 static int
7777 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7778                             uint16_t ether_type)
7779 {
7780         uint32_t etag_etype;
7781
7782         if (hw->mac.type != ixgbe_mac_X550 &&
7783             hw->mac.type != ixgbe_mac_X550EM_x &&
7784             hw->mac.type != ixgbe_mac_X550EM_a) {
7785                 return -ENOTSUP;
7786         }
7787
7788         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7789         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7790         etag_etype |= ether_type;
7791         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7792         IXGBE_WRITE_FLUSH(hw);
7793
7794         return 0;
7795 }
7796
7797 /* Config l2 tunnel ether type */
7798 static int
7799 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7800                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7801 {
7802         int ret = 0;
7803         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7804         struct ixgbe_l2_tn_info *l2_tn_info =
7805                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7806
7807         if (l2_tunnel == NULL)
7808                 return -EINVAL;
7809
7810         switch (l2_tunnel->l2_tunnel_type) {
7811         case RTE_L2_TUNNEL_TYPE_E_TAG:
7812                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7813                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7814                 break;
7815         default:
7816                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7817                 ret = -EINVAL;
7818                 break;
7819         }
7820
7821         return ret;
7822 }
7823
7824 /* Enable e-tag tunnel */
7825 static int
7826 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7827 {
7828         uint32_t etag_etype;
7829
7830         if (hw->mac.type != ixgbe_mac_X550 &&
7831             hw->mac.type != ixgbe_mac_X550EM_x &&
7832             hw->mac.type != ixgbe_mac_X550EM_a) {
7833                 return -ENOTSUP;
7834         }
7835
7836         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7837         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7838         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7839         IXGBE_WRITE_FLUSH(hw);
7840
7841         return 0;
7842 }
7843
7844 /* Enable l2 tunnel */
7845 static int
7846 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7847                            enum rte_eth_tunnel_type l2_tunnel_type)
7848 {
7849         int ret = 0;
7850         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7851         struct ixgbe_l2_tn_info *l2_tn_info =
7852                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7853
7854         switch (l2_tunnel_type) {
7855         case RTE_L2_TUNNEL_TYPE_E_TAG:
7856                 l2_tn_info->e_tag_en = TRUE;
7857                 ret = ixgbe_e_tag_enable(hw);
7858                 break;
7859         default:
7860                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7861                 ret = -EINVAL;
7862                 break;
7863         }
7864
7865         return ret;
7866 }
7867
7868 /* Disable e-tag tunnel */
7869 static int
7870 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7871 {
7872         uint32_t etag_etype;
7873
7874         if (hw->mac.type != ixgbe_mac_X550 &&
7875             hw->mac.type != ixgbe_mac_X550EM_x &&
7876             hw->mac.type != ixgbe_mac_X550EM_a) {
7877                 return -ENOTSUP;
7878         }
7879
7880         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7881         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7882         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7883         IXGBE_WRITE_FLUSH(hw);
7884
7885         return 0;
7886 }
7887
7888 /* Disable l2 tunnel */
7889 static int
7890 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7891                             enum rte_eth_tunnel_type l2_tunnel_type)
7892 {
7893         int ret = 0;
7894         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7895         struct ixgbe_l2_tn_info *l2_tn_info =
7896                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7897
7898         switch (l2_tunnel_type) {
7899         case RTE_L2_TUNNEL_TYPE_E_TAG:
7900                 l2_tn_info->e_tag_en = FALSE;
7901                 ret = ixgbe_e_tag_disable(hw);
7902                 break;
7903         default:
7904                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7905                 ret = -EINVAL;
7906                 break;
7907         }
7908
7909         return ret;
7910 }
7911
7912 static int
7913 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7914                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7915 {
7916         int ret = 0;
7917         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7918         uint32_t i, rar_entries;
7919         uint32_t rar_low, rar_high;
7920
7921         if (hw->mac.type != ixgbe_mac_X550 &&
7922             hw->mac.type != ixgbe_mac_X550EM_x &&
7923             hw->mac.type != ixgbe_mac_X550EM_a) {
7924                 return -ENOTSUP;
7925         }
7926
7927         rar_entries = ixgbe_get_num_rx_addrs(hw);
7928
7929         for (i = 1; i < rar_entries; i++) {
7930                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7931                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7932                 if ((rar_high & IXGBE_RAH_AV) &&
7933                     (rar_high & IXGBE_RAH_ADTYPE) &&
7934                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7935                      l2_tunnel->tunnel_id)) {
7936                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7937                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7938
7939                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7940
7941                         return ret;
7942                 }
7943         }
7944
7945         return ret;
7946 }
7947
7948 static int
7949 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7950                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7951 {
7952         int ret = 0;
7953         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7954         uint32_t i, rar_entries;
7955         uint32_t rar_low, rar_high;
7956
7957         if (hw->mac.type != ixgbe_mac_X550 &&
7958             hw->mac.type != ixgbe_mac_X550EM_x &&
7959             hw->mac.type != ixgbe_mac_X550EM_a) {
7960                 return -ENOTSUP;
7961         }
7962
7963         /* One entry for one tunnel. Try to remove potential existing entry. */
7964         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7965
7966         rar_entries = ixgbe_get_num_rx_addrs(hw);
7967
7968         for (i = 1; i < rar_entries; i++) {
7969                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7970                 if (rar_high & IXGBE_RAH_AV) {
7971                         continue;
7972                 } else {
7973                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7974                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7975                         rar_low = l2_tunnel->tunnel_id;
7976
7977                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7978                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7979
7980                         return ret;
7981                 }
7982         }
7983
7984         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7985                      " Please remove a rule before adding a new one.");
7986         return -EINVAL;
7987 }
7988
7989 static inline struct ixgbe_l2_tn_filter *
7990 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7991                           struct ixgbe_l2_tn_key *key)
7992 {
7993         int ret;
7994
7995         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7996         if (ret < 0)
7997                 return NULL;
7998
7999         return l2_tn_info->hash_map[ret];
8000 }
8001
8002 static inline int
8003 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8004                           struct ixgbe_l2_tn_filter *l2_tn_filter)
8005 {
8006         int ret;
8007
8008         ret = rte_hash_add_key(l2_tn_info->hash_handle,
8009                                &l2_tn_filter->key);
8010
8011         if (ret < 0) {
8012                 PMD_DRV_LOG(ERR,
8013                             "Failed to insert L2 tunnel filter"
8014                             " to hash table %d!",
8015                             ret);
8016                 return ret;
8017         }
8018
8019         l2_tn_info->hash_map[ret] = l2_tn_filter;
8020
8021         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8022
8023         return 0;
8024 }
8025
8026 static inline int
8027 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8028                           struct ixgbe_l2_tn_key *key)
8029 {
8030         int ret;
8031         struct ixgbe_l2_tn_filter *l2_tn_filter;
8032
8033         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
8034
8035         if (ret < 0) {
8036                 PMD_DRV_LOG(ERR,
8037                             "No such L2 tunnel filter to delete %d!",
8038                             ret);
8039                 return ret;
8040         }
8041
8042         l2_tn_filter = l2_tn_info->hash_map[ret];
8043         l2_tn_info->hash_map[ret] = NULL;
8044
8045         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8046         rte_free(l2_tn_filter);
8047
8048         return 0;
8049 }
8050
8051 /* Add l2 tunnel filter */
8052 int
8053 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
8054                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
8055                                bool restore)
8056 {
8057         int ret;
8058         struct ixgbe_l2_tn_info *l2_tn_info =
8059                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8060         struct ixgbe_l2_tn_key key;
8061         struct ixgbe_l2_tn_filter *node;
8062
8063         if (!restore) {
8064                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8065                 key.tn_id = l2_tunnel->tunnel_id;
8066
8067                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
8068
8069                 if (node) {
8070                         PMD_DRV_LOG(ERR,
8071                                     "The L2 tunnel filter already exists!");
8072                         return -EINVAL;
8073                 }
8074
8075                 node = rte_zmalloc("ixgbe_l2_tn",
8076                                    sizeof(struct ixgbe_l2_tn_filter),
8077                                    0);
8078                 if (!node)
8079                         return -ENOMEM;
8080
8081                 rte_memcpy(&node->key,
8082                                  &key,
8083                                  sizeof(struct ixgbe_l2_tn_key));
8084                 node->pool = l2_tunnel->pool;
8085                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
8086                 if (ret < 0) {
8087                         rte_free(node);
8088                         return ret;
8089                 }
8090         }
8091
8092         switch (l2_tunnel->l2_tunnel_type) {
8093         case RTE_L2_TUNNEL_TYPE_E_TAG:
8094                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
8095                 break;
8096         default:
8097                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8098                 ret = -EINVAL;
8099                 break;
8100         }
8101
8102         if ((!restore) && (ret < 0))
8103                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8104
8105         return ret;
8106 }
8107
8108 /* Delete l2 tunnel filter */
8109 int
8110 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
8111                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
8112 {
8113         int ret;
8114         struct ixgbe_l2_tn_info *l2_tn_info =
8115                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8116         struct ixgbe_l2_tn_key key;
8117
8118         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8119         key.tn_id = l2_tunnel->tunnel_id;
8120         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8121         if (ret < 0)
8122                 return ret;
8123
8124         switch (l2_tunnel->l2_tunnel_type) {
8125         case RTE_L2_TUNNEL_TYPE_E_TAG:
8126                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
8127                 break;
8128         default:
8129                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8130                 ret = -EINVAL;
8131                 break;
8132         }
8133
8134         return ret;
8135 }
8136
8137 /**
8138  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8139  * @dev: pointer to rte_eth_dev structure
8140  * @filter_op:operation will be taken.
8141  * @arg: a pointer to specific structure corresponding to the filter_op
8142  */
8143 static int
8144 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8145                                   enum rte_filter_op filter_op,
8146                                   void *arg)
8147 {
8148         int ret;
8149
8150         if (filter_op == RTE_ETH_FILTER_NOP)
8151                 return 0;
8152
8153         if (arg == NULL) {
8154                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8155                             filter_op);
8156                 return -EINVAL;
8157         }
8158
8159         switch (filter_op) {
8160         case RTE_ETH_FILTER_ADD:
8161                 ret = ixgbe_dev_l2_tunnel_filter_add
8162                         (dev,
8163                          (struct rte_eth_l2_tunnel_conf *)arg,
8164                          FALSE);
8165                 break;
8166         case RTE_ETH_FILTER_DELETE:
8167                 ret = ixgbe_dev_l2_tunnel_filter_del
8168                         (dev,
8169                          (struct rte_eth_l2_tunnel_conf *)arg);
8170                 break;
8171         default:
8172                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8173                 ret = -EINVAL;
8174                 break;
8175         }
8176         return ret;
8177 }
8178
8179 static int
8180 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8181 {
8182         int ret = 0;
8183         uint32_t ctrl;
8184         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8185
8186         if (hw->mac.type != ixgbe_mac_X550 &&
8187             hw->mac.type != ixgbe_mac_X550EM_x &&
8188             hw->mac.type != ixgbe_mac_X550EM_a) {
8189                 return -ENOTSUP;
8190         }
8191
8192         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8193         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8194         if (en)
8195                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8196         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8197
8198         return ret;
8199 }
8200
8201 /* Enable l2 tunnel forwarding */
8202 static int
8203 ixgbe_dev_l2_tunnel_forwarding_enable
8204         (struct rte_eth_dev *dev,
8205          enum rte_eth_tunnel_type l2_tunnel_type)
8206 {
8207         struct ixgbe_l2_tn_info *l2_tn_info =
8208                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8209         int ret = 0;
8210
8211         switch (l2_tunnel_type) {
8212         case RTE_L2_TUNNEL_TYPE_E_TAG:
8213                 l2_tn_info->e_tag_fwd_en = TRUE;
8214                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8215                 break;
8216         default:
8217                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8218                 ret = -EINVAL;
8219                 break;
8220         }
8221
8222         return ret;
8223 }
8224
8225 /* Disable l2 tunnel forwarding */
8226 static int
8227 ixgbe_dev_l2_tunnel_forwarding_disable
8228         (struct rte_eth_dev *dev,
8229          enum rte_eth_tunnel_type l2_tunnel_type)
8230 {
8231         struct ixgbe_l2_tn_info *l2_tn_info =
8232                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8233         int ret = 0;
8234
8235         switch (l2_tunnel_type) {
8236         case RTE_L2_TUNNEL_TYPE_E_TAG:
8237                 l2_tn_info->e_tag_fwd_en = FALSE;
8238                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8239                 break;
8240         default:
8241                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8242                 ret = -EINVAL;
8243                 break;
8244         }
8245
8246         return ret;
8247 }
8248
8249 static int
8250 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8251                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
8252                              bool en)
8253 {
8254         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8255         int ret = 0;
8256         uint32_t vmtir, vmvir;
8257         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8258
8259         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8260                 PMD_DRV_LOG(ERR,
8261                             "VF id %u should be less than %u",
8262                             l2_tunnel->vf_id,
8263                             pci_dev->max_vfs);
8264                 return -EINVAL;
8265         }
8266
8267         if (hw->mac.type != ixgbe_mac_X550 &&
8268             hw->mac.type != ixgbe_mac_X550EM_x &&
8269             hw->mac.type != ixgbe_mac_X550EM_a) {
8270                 return -ENOTSUP;
8271         }
8272
8273         if (en)
8274                 vmtir = l2_tunnel->tunnel_id;
8275         else
8276                 vmtir = 0;
8277
8278         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8279
8280         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8281         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8282         if (en)
8283                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8284         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8285
8286         return ret;
8287 }
8288
8289 /* Enable l2 tunnel tag insertion */
8290 static int
8291 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8292                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8293 {
8294         int ret = 0;
8295
8296         switch (l2_tunnel->l2_tunnel_type) {
8297         case RTE_L2_TUNNEL_TYPE_E_TAG:
8298                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8299                 break;
8300         default:
8301                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8302                 ret = -EINVAL;
8303                 break;
8304         }
8305
8306         return ret;
8307 }
8308
8309 /* Disable l2 tunnel tag insertion */
8310 static int
8311 ixgbe_dev_l2_tunnel_insertion_disable
8312         (struct rte_eth_dev *dev,
8313          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8314 {
8315         int ret = 0;
8316
8317         switch (l2_tunnel->l2_tunnel_type) {
8318         case RTE_L2_TUNNEL_TYPE_E_TAG:
8319                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8320                 break;
8321         default:
8322                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8323                 ret = -EINVAL;
8324                 break;
8325         }
8326
8327         return ret;
8328 }
8329
8330 static int
8331 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8332                              bool en)
8333 {
8334         int ret = 0;
8335         uint32_t qde;
8336         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8337
8338         if (hw->mac.type != ixgbe_mac_X550 &&
8339             hw->mac.type != ixgbe_mac_X550EM_x &&
8340             hw->mac.type != ixgbe_mac_X550EM_a) {
8341                 return -ENOTSUP;
8342         }
8343
8344         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8345         if (en)
8346                 qde |= IXGBE_QDE_STRIP_TAG;
8347         else
8348                 qde &= ~IXGBE_QDE_STRIP_TAG;
8349         qde &= ~IXGBE_QDE_READ;
8350         qde |= IXGBE_QDE_WRITE;
8351         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8352
8353         return ret;
8354 }
8355
8356 /* Enable l2 tunnel tag stripping */
8357 static int
8358 ixgbe_dev_l2_tunnel_stripping_enable
8359         (struct rte_eth_dev *dev,
8360          enum rte_eth_tunnel_type l2_tunnel_type)
8361 {
8362         int ret = 0;
8363
8364         switch (l2_tunnel_type) {
8365         case RTE_L2_TUNNEL_TYPE_E_TAG:
8366                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8367                 break;
8368         default:
8369                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8370                 ret = -EINVAL;
8371                 break;
8372         }
8373
8374         return ret;
8375 }
8376
8377 /* Disable l2 tunnel tag stripping */
8378 static int
8379 ixgbe_dev_l2_tunnel_stripping_disable
8380         (struct rte_eth_dev *dev,
8381          enum rte_eth_tunnel_type l2_tunnel_type)
8382 {
8383         int ret = 0;
8384
8385         switch (l2_tunnel_type) {
8386         case RTE_L2_TUNNEL_TYPE_E_TAG:
8387                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8388                 break;
8389         default:
8390                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8391                 ret = -EINVAL;
8392                 break;
8393         }
8394
8395         return ret;
8396 }
8397
8398 /* Enable/disable l2 tunnel offload functions */
8399 static int
8400 ixgbe_dev_l2_tunnel_offload_set
8401         (struct rte_eth_dev *dev,
8402          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8403          uint32_t mask,
8404          uint8_t en)
8405 {
8406         int ret = 0;
8407
8408         if (l2_tunnel == NULL)
8409                 return -EINVAL;
8410
8411         ret = -EINVAL;
8412         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8413                 if (en)
8414                         ret = ixgbe_dev_l2_tunnel_enable(
8415                                 dev,
8416                                 l2_tunnel->l2_tunnel_type);
8417                 else
8418                         ret = ixgbe_dev_l2_tunnel_disable(
8419                                 dev,
8420                                 l2_tunnel->l2_tunnel_type);
8421         }
8422
8423         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8424                 if (en)
8425                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8426                                 dev,
8427                                 l2_tunnel);
8428                 else
8429                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8430                                 dev,
8431                                 l2_tunnel);
8432         }
8433
8434         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8435                 if (en)
8436                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8437                                 dev,
8438                                 l2_tunnel->l2_tunnel_type);
8439                 else
8440                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8441                                 dev,
8442                                 l2_tunnel->l2_tunnel_type);
8443         }
8444
8445         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8446                 if (en)
8447                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8448                                 dev,
8449                                 l2_tunnel->l2_tunnel_type);
8450                 else
8451                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8452                                 dev,
8453                                 l2_tunnel->l2_tunnel_type);
8454         }
8455
8456         return ret;
8457 }
8458
8459 static int
8460 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8461                         uint16_t port)
8462 {
8463         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8464         IXGBE_WRITE_FLUSH(hw);
8465
8466         return 0;
8467 }
8468
8469 /* There's only one register for VxLAN UDP port.
8470  * So, we cannot add several ports. Will update it.
8471  */
8472 static int
8473 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8474                      uint16_t port)
8475 {
8476         if (port == 0) {
8477                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8478                 return -EINVAL;
8479         }
8480
8481         return ixgbe_update_vxlan_port(hw, port);
8482 }
8483
8484 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8485  * UDP port, it must have a value.
8486  * So, will reset it to the original value 0.
8487  */
8488 static int
8489 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8490                      uint16_t port)
8491 {
8492         uint16_t cur_port;
8493
8494         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8495
8496         if (cur_port != port) {
8497                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8498                 return -EINVAL;
8499         }
8500
8501         return ixgbe_update_vxlan_port(hw, 0);
8502 }
8503
8504 /* Add UDP tunneling port */
8505 static int
8506 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8507                               struct rte_eth_udp_tunnel *udp_tunnel)
8508 {
8509         int ret = 0;
8510         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8511
8512         if (hw->mac.type != ixgbe_mac_X550 &&
8513             hw->mac.type != ixgbe_mac_X550EM_x &&
8514             hw->mac.type != ixgbe_mac_X550EM_a) {
8515                 return -ENOTSUP;
8516         }
8517
8518         if (udp_tunnel == NULL)
8519                 return -EINVAL;
8520
8521         switch (udp_tunnel->prot_type) {
8522         case RTE_TUNNEL_TYPE_VXLAN:
8523                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8524                 break;
8525
8526         case RTE_TUNNEL_TYPE_GENEVE:
8527         case RTE_TUNNEL_TYPE_TEREDO:
8528                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8529                 ret = -EINVAL;
8530                 break;
8531
8532         default:
8533                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8534                 ret = -EINVAL;
8535                 break;
8536         }
8537
8538         return ret;
8539 }
8540
8541 /* Remove UDP tunneling port */
8542 static int
8543 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8544                               struct rte_eth_udp_tunnel *udp_tunnel)
8545 {
8546         int ret = 0;
8547         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8548
8549         if (hw->mac.type != ixgbe_mac_X550 &&
8550             hw->mac.type != ixgbe_mac_X550EM_x &&
8551             hw->mac.type != ixgbe_mac_X550EM_a) {
8552                 return -ENOTSUP;
8553         }
8554
8555         if (udp_tunnel == NULL)
8556                 return -EINVAL;
8557
8558         switch (udp_tunnel->prot_type) {
8559         case RTE_TUNNEL_TYPE_VXLAN:
8560                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8561                 break;
8562         case RTE_TUNNEL_TYPE_GENEVE:
8563         case RTE_TUNNEL_TYPE_TEREDO:
8564                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8565                 ret = -EINVAL;
8566                 break;
8567         default:
8568                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8569                 ret = -EINVAL;
8570                 break;
8571         }
8572
8573         return ret;
8574 }
8575
8576 static int
8577 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8578 {
8579         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8580         int ret;
8581
8582         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8583         case IXGBE_SUCCESS:
8584                 ret = 0;
8585                 break;
8586         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8587                 ret = -ENOTSUP;
8588                 break;
8589         default:
8590                 ret = -EAGAIN;
8591                 break;
8592         }
8593
8594         return ret;
8595 }
8596
8597 static int
8598 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8599 {
8600         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8601         int ret;
8602
8603         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8604         case IXGBE_SUCCESS:
8605                 ret = 0;
8606                 break;
8607         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8608                 ret = -ENOTSUP;
8609                 break;
8610         default:
8611                 ret = -EAGAIN;
8612                 break;
8613         }
8614
8615         return ret;
8616 }
8617
8618 static int
8619 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8620 {
8621         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8622         int ret;
8623         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8624
8625         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8626         case IXGBE_SUCCESS:
8627                 ret = 0;
8628                 break;
8629         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8630                 ret = -ENOTSUP;
8631                 break;
8632         default:
8633                 ret = -EAGAIN;
8634                 break;
8635         }
8636
8637         return ret;
8638 }
8639
8640 static int
8641 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8642 {
8643         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8644         int ret;
8645
8646         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8647         case IXGBE_SUCCESS:
8648                 ret = 0;
8649                 break;
8650         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8651                 ret = -ENOTSUP;
8652                 break;
8653         default:
8654                 ret = -EAGAIN;
8655                 break;
8656         }
8657
8658         return ret;
8659 }
8660
8661 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8662 {
8663         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8664         u32 in_msg = 0;
8665
8666         /* peek the message first */
8667         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8668
8669         /* PF reset VF event */
8670         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8671                 /* dummy mbx read to ack pf */
8672                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8673                         return;
8674                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8675                                              NULL);
8676         }
8677 }
8678
8679 static int
8680 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8681 {
8682         uint32_t eicr;
8683         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8684         struct ixgbe_interrupt *intr =
8685                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8686         ixgbevf_intr_disable(dev);
8687
8688         /* read-on-clear nic registers here */
8689         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8690         intr->flags = 0;
8691
8692         /* only one misc vector supported - mailbox */
8693         eicr &= IXGBE_VTEICR_MASK;
8694         if (eicr == IXGBE_MISC_VEC_ID)
8695                 intr->flags |= IXGBE_FLAG_MAILBOX;
8696
8697         return 0;
8698 }
8699
8700 static int
8701 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8702 {
8703         struct ixgbe_interrupt *intr =
8704                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8705
8706         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8707                 ixgbevf_mbx_process(dev);
8708                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8709         }
8710
8711         ixgbevf_intr_enable(dev);
8712
8713         return 0;
8714 }
8715
8716 static void
8717 ixgbevf_dev_interrupt_handler(void *param)
8718 {
8719         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8720
8721         ixgbevf_dev_interrupt_get_status(dev);
8722         ixgbevf_dev_interrupt_action(dev);
8723 }
8724
8725 /**
8726  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8727  *  @hw: pointer to hardware structure
8728  *
8729  *  Stops the transmit data path and waits for the HW to internally empty
8730  *  the Tx security block
8731  **/
8732 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8733 {
8734 #define IXGBE_MAX_SECTX_POLL 40
8735
8736         int i;
8737         int sectxreg;
8738
8739         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8740         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8741         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8742         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8743                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8744                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8745                         break;
8746                 /* Use interrupt-safe sleep just in case */
8747                 usec_delay(1000);
8748         }
8749
8750         /* For informational purposes only */
8751         if (i >= IXGBE_MAX_SECTX_POLL)
8752                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8753                          "path fully disabled.  Continuing with init.");
8754
8755         return IXGBE_SUCCESS;
8756 }
8757
8758 /**
8759  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8760  *  @hw: pointer to hardware structure
8761  *
8762  *  Enables the transmit data path.
8763  **/
8764 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8765 {
8766         uint32_t sectxreg;
8767
8768         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8769         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8770         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8771         IXGBE_WRITE_FLUSH(hw);
8772
8773         return IXGBE_SUCCESS;
8774 }
8775
8776 /* restore n-tuple filter */
8777 static inline void
8778 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8779 {
8780         struct ixgbe_filter_info *filter_info =
8781                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8782         struct ixgbe_5tuple_filter *node;
8783
8784         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8785                 ixgbe_inject_5tuple_filter(dev, node);
8786         }
8787 }
8788
8789 /* restore ethernet type filter */
8790 static inline void
8791 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8792 {
8793         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8794         struct ixgbe_filter_info *filter_info =
8795                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8796         int i;
8797
8798         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8799                 if (filter_info->ethertype_mask & (1 << i)) {
8800                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8801                                         filter_info->ethertype_filters[i].etqf);
8802                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8803                                         filter_info->ethertype_filters[i].etqs);
8804                         IXGBE_WRITE_FLUSH(hw);
8805                 }
8806         }
8807 }
8808
8809 /* restore SYN filter */
8810 static inline void
8811 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8812 {
8813         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8814         struct ixgbe_filter_info *filter_info =
8815                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8816         uint32_t synqf;
8817
8818         synqf = filter_info->syn_info;
8819
8820         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8821                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8822                 IXGBE_WRITE_FLUSH(hw);
8823         }
8824 }
8825
8826 /* restore L2 tunnel filter */
8827 static inline void
8828 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8829 {
8830         struct ixgbe_l2_tn_info *l2_tn_info =
8831                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8832         struct ixgbe_l2_tn_filter *node;
8833         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8834
8835         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8836                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8837                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8838                 l2_tn_conf.pool           = node->pool;
8839                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8840         }
8841 }
8842
8843 /* restore rss filter */
8844 static inline void
8845 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8846 {
8847         struct ixgbe_filter_info *filter_info =
8848                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8849
8850         if (filter_info->rss_info.conf.queue_num)
8851                 ixgbe_config_rss_filter(dev,
8852                         &filter_info->rss_info, TRUE);
8853 }
8854
8855 static int
8856 ixgbe_filter_restore(struct rte_eth_dev *dev)
8857 {
8858         ixgbe_ntuple_filter_restore(dev);
8859         ixgbe_ethertype_filter_restore(dev);
8860         ixgbe_syn_filter_restore(dev);
8861         ixgbe_fdir_filter_restore(dev);
8862         ixgbe_l2_tn_filter_restore(dev);
8863         ixgbe_rss_filter_restore(dev);
8864
8865         return 0;
8866 }
8867
8868 static void
8869 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8870 {
8871         struct ixgbe_l2_tn_info *l2_tn_info =
8872                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8873         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8874
8875         if (l2_tn_info->e_tag_en)
8876                 (void)ixgbe_e_tag_enable(hw);
8877
8878         if (l2_tn_info->e_tag_fwd_en)
8879                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8880
8881         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8882 }
8883
8884 /* remove all the n-tuple filters */
8885 void
8886 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8887 {
8888         struct ixgbe_filter_info *filter_info =
8889                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8890         struct ixgbe_5tuple_filter *p_5tuple;
8891
8892         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8893                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8894 }
8895
8896 /* remove all the ether type filters */
8897 void
8898 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8899 {
8900         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8901         struct ixgbe_filter_info *filter_info =
8902                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8903         int i;
8904
8905         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8906                 if (filter_info->ethertype_mask & (1 << i) &&
8907                     !filter_info->ethertype_filters[i].conf) {
8908                         (void)ixgbe_ethertype_filter_remove(filter_info,
8909                                                             (uint8_t)i);
8910                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8911                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8912                         IXGBE_WRITE_FLUSH(hw);
8913                 }
8914         }
8915 }
8916
8917 /* remove the SYN filter */
8918 void
8919 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8920 {
8921         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8922         struct ixgbe_filter_info *filter_info =
8923                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8924
8925         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8926                 filter_info->syn_info = 0;
8927
8928                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8929                 IXGBE_WRITE_FLUSH(hw);
8930         }
8931 }
8932
8933 /* remove all the L2 tunnel filters */
8934 int
8935 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8936 {
8937         struct ixgbe_l2_tn_info *l2_tn_info =
8938                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8939         struct ixgbe_l2_tn_filter *l2_tn_filter;
8940         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8941         int ret = 0;
8942
8943         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8944                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8945                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8946                 l2_tn_conf.pool           = l2_tn_filter->pool;
8947                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8948                 if (ret < 0)
8949                         return ret;
8950         }
8951
8952         return 0;
8953 }
8954
8955 void
8956 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8957                                 struct ixgbe_macsec_setting *macsec_setting)
8958 {
8959         struct ixgbe_macsec_setting *macsec =
8960                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8961
8962         macsec->offload_en = macsec_setting->offload_en;
8963         macsec->encrypt_en = macsec_setting->encrypt_en;
8964         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8965 }
8966
8967 void
8968 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8969 {
8970         struct ixgbe_macsec_setting *macsec =
8971                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8972
8973         macsec->offload_en = 0;
8974         macsec->encrypt_en = 0;
8975         macsec->replayprotect_en = 0;
8976 }
8977
8978 void
8979 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8980                                 struct ixgbe_macsec_setting *macsec_setting)
8981 {
8982         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8983         uint32_t ctrl;
8984         uint8_t en = macsec_setting->encrypt_en;
8985         uint8_t rp = macsec_setting->replayprotect_en;
8986
8987         /**
8988          * Workaround:
8989          * As no ixgbe_disable_sec_rx_path equivalent is
8990          * implemented for tx in the base code, and we are
8991          * not allowed to modify the base code in DPDK, so
8992          * just call the hand-written one directly for now.
8993          * The hardware support has been checked by
8994          * ixgbe_disable_sec_rx_path().
8995          */
8996         ixgbe_disable_sec_tx_path_generic(hw);
8997
8998         /* Enable Ethernet CRC (required by MACsec offload) */
8999         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
9000         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
9001         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
9002
9003         /* Enable the TX and RX crypto engines */
9004         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9005         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
9006         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9007
9008         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9009         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
9010         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9011
9012         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
9013         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
9014         ctrl |= 0x3;
9015         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
9016
9017         /* Enable SA lookup */
9018         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9019         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9020         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
9021                      IXGBE_LSECTXCTRL_AUTH;
9022         ctrl |= IXGBE_LSECTXCTRL_AISCI;
9023         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9024         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9025         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9026
9027         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9028         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9029         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
9030         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
9031         if (rp)
9032                 ctrl |= IXGBE_LSECRXCTRL_RP;
9033         else
9034                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
9035         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9036
9037         /* Start the data paths */
9038         ixgbe_enable_sec_rx_path(hw);
9039         /**
9040          * Workaround:
9041          * As no ixgbe_enable_sec_rx_path equivalent is
9042          * implemented for tx in the base code, and we are
9043          * not allowed to modify the base code in DPDK, so
9044          * just call the hand-written one directly for now.
9045          */
9046         ixgbe_enable_sec_tx_path_generic(hw);
9047 }
9048
9049 void
9050 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
9051 {
9052         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9053         uint32_t ctrl;
9054
9055         /**
9056          * Workaround:
9057          * As no ixgbe_disable_sec_rx_path equivalent is
9058          * implemented for tx in the base code, and we are
9059          * not allowed to modify the base code in DPDK, so
9060          * just call the hand-written one directly for now.
9061          * The hardware support has been checked by
9062          * ixgbe_disable_sec_rx_path().
9063          */
9064         ixgbe_disable_sec_tx_path_generic(hw);
9065
9066         /* Disable the TX and RX crypto engines */
9067         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9068         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
9069         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9070
9071         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9072         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
9073         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9074
9075         /* Disable SA lookup */
9076         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9077         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9078         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
9079         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9080
9081         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9082         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9083         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
9084         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9085
9086         /* Start the data paths */
9087         ixgbe_enable_sec_rx_path(hw);
9088         /**
9089          * Workaround:
9090          * As no ixgbe_enable_sec_rx_path equivalent is
9091          * implemented for tx in the base code, and we are
9092          * not allowed to modify the base code in DPDK, so
9093          * just call the hand-written one directly for now.
9094          */
9095         ixgbe_enable_sec_tx_path_generic(hw);
9096 }
9097
9098 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
9099 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
9100 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
9101 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
9102 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
9103 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
9104 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
9105                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
9106
9107 RTE_LOG_REGISTER(ixgbe_logtype_init, pmd.net.ixgbe.init, NOTICE);
9108 RTE_LOG_REGISTER(ixgbe_logtype_driver, pmd.net.ixgbe.driver, NOTICE);
9109
9110 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
9111 RTE_LOG_REGISTER(ixgbe_logtype_rx, pmd.net.ixgbe.rx, DEBUG);
9112 #endif
9113 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
9114 RTE_LOG_REGISTER(ixgbe_logtype_tx, pmd.net.ixgbe.tx, DEBUG);
9115 #endif
9116 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
9117 RTE_LOG_REGISTER(ixgbe_logtype_tx_free, pmd.net.ixgbe.tx_free, DEBUG);
9118 #endif