drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIBRTE_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static int  ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
 233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
 234                                               uint32_t timeout_ms);
 235
 236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 237                         struct rte_ether_addr *mac_addr,
 238                         uint32_t index, uint32_t pool);
 239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 241                                            struct rte_ether_addr *mac_addr);
 242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 243 static bool is_device_supported(struct rte_eth_dev *dev,
 244                                 struct rte_pci_driver *drv);
 245
 246 /* For Virtual Function support */
 247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 250 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 252                                    int wait_to_complete);
 253 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 254 static int ixgbevf_dev_close(struct rte_eth_dev *dev);
 255 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 259                 struct rte_eth_stats *stats);
 260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 262                 uint16_t vlan_id, int on);
 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 264                 uint16_t queue, int on);
 265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 269                                             uint16_t queue_id);
 270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 271                                              uint16_t queue_id);
 272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 273                                  uint8_t queue, uint8_t msix_vector);
 274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 rte_ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 285                 struct rte_eth_mirror_conf *mirror_conf,
 286                 uint8_t rule_id, uint8_t on);
 287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 288                 uint8_t rule_id);
 289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 290                                           uint16_t queue_id);
 291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 292                                            uint16_t queue_id);
 293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 294                                uint8_t queue, uint8_t msix_vector);
 295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 296
 297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 298                                 struct rte_ether_addr *mac_addr,
 299                                 uint32_t index, uint32_t pool);
 300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 302                                              struct rte_ether_addr *mac_addr);
 303 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 304                         struct rte_eth_syn_filter *filter);
 305 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 306                         enum rte_filter_op filter_op,
 307                         void *arg);
 308 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 309                         struct ixgbe_5tuple_filter *filter);
 310 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 311                         struct ixgbe_5tuple_filter *filter);
 312 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 313                                 enum rte_filter_op filter_op,
 314                                 void *arg);
 315 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 316                         struct rte_eth_ntuple_filter *filter);
 317 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 318                                 enum rte_filter_op filter_op,
 319                                 void *arg);
 320 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 321                         struct rte_eth_ethertype_filter *filter);
 322 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 323                      enum rte_filter_type filter_type,
 324                      enum rte_filter_op filter_op,
 325                      void *arg);
 326 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 327
 328 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 329                                       struct rte_ether_addr *mc_addr_set,
 330                                       uint32_t nb_mc_addr);
 331 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 332                                    struct rte_eth_dcb_info *dcb_info);
 333
 334 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 335 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 336                             struct rte_dev_reg_info *regs);
 337 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 338 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 339                                 struct rte_dev_eeprom_info *eeprom);
 340 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 341                                 struct rte_dev_eeprom_info *eeprom);
 342
 343 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 344                                  struct rte_eth_dev_module_info *modinfo);
 345 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 346                                    struct rte_dev_eeprom_info *info);
 347
 348 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 349 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 350                                 struct rte_dev_reg_info *regs);
 351
 352 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 354 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 355                                             struct timespec *timestamp,
 356                                             uint32_t flags);
 357 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 358                                             struct timespec *timestamp);
 359 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 360 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 361                                    struct timespec *timestamp);
 362 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 363                                    const struct timespec *timestamp);
 364 static void ixgbevf_dev_interrupt_handler(void *param);
 365
 366 static int ixgbe_dev_l2_tunnel_eth_type_conf
 367         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 368 static int ixgbe_dev_l2_tunnel_offload_set
 369         (struct rte_eth_dev *dev,
 370          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 371          uint32_t mask,
 372          uint8_t en);
 373 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 374                                              enum rte_filter_op filter_op,
 375                                              void *arg);
 376
 377 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 380                                          struct rte_eth_udp_tunnel *udp_tunnel);
 381 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 382 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 383 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
 384
 385 /*
 386  * Define VF Stats MACRO for Non "cleared on read" register
 387  */
 388 #define UPDATE_VF_STAT(reg, last, cur)                          \
 389 {                                                               \
 390         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 391         cur += (latest - last) & UINT_MAX;                      \
 392         last = latest;                                          \
 393 }
 394
 395 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 396 {                                                                \
 397         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 398         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 399         u64 latest = ((new_msb << 32) | new_lsb);                \
 400         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 401         last = latest;                                           \
 402 }
 403
 404 #define IXGBE_SET_HWSTRIP(h, q) do {\
 405                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 406                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 407                 (h)->bitmap[idx] |= 1 << bit;\
 408         } while (0)
 409
 410 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 411                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 412                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 413                 (h)->bitmap[idx] &= ~(1 << bit);\
 414         } while (0)
 415
 416 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 417                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 418                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 419                 (r) = (h)->bitmap[idx] >> bit & 1;\
 420         } while (0)
 421
 422 /*
 423  * The set of PCI devices this driver supports
 424  */
 425 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 474 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 476 #endif
 477         { .vendor_id = 0, /* sentinel */ },
 478 };
 479
 480 /*
 481  * The set of PCI devices this driver supports (for 82599 VF)
 482  */
 483 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 492         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 494         { .vendor_id = 0, /* sentinel */ },
 495 };
 496
 497 static const struct rte_eth_desc_lim rx_desc_lim = {
 498         .nb_max = IXGBE_MAX_RING_DESC,
 499         .nb_min = IXGBE_MIN_RING_DESC,
 500         .nb_align = IXGBE_RXD_ALIGN,
 501 };
 502
 503 static const struct rte_eth_desc_lim tx_desc_lim = {
 504         .nb_max = IXGBE_MAX_RING_DESC,
 505         .nb_min = IXGBE_MIN_RING_DESC,
 506         .nb_align = IXGBE_TXD_ALIGN,
 507         .nb_seg_max = IXGBE_TX_MAX_SEG,
 508         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 509 };
 510
 511 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 512         .dev_configure        = ixgbe_dev_configure,
 513         .dev_start            = ixgbe_dev_start,
 514         .dev_stop             = ixgbe_dev_stop,
 515         .dev_set_link_up    = ixgbe_dev_set_link_up,
 516         .dev_set_link_down  = ixgbe_dev_set_link_down,
 517         .dev_close            = ixgbe_dev_close,
 518         .dev_reset            = ixgbe_dev_reset,
 519         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 520         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 521         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 522         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 523         .link_update          = ixgbe_dev_link_update,
 524         .stats_get            = ixgbe_dev_stats_get,
 525         .xstats_get           = ixgbe_dev_xstats_get,
 526         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 527         .stats_reset          = ixgbe_dev_stats_reset,
 528         .xstats_reset         = ixgbe_dev_xstats_reset,
 529         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 530         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 531         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 532         .fw_version_get       = ixgbe_fw_version_get,
 533         .dev_infos_get        = ixgbe_dev_info_get,
 534         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 535         .mtu_set              = ixgbe_dev_mtu_set,
 536         .vlan_filter_set      = ixgbe_vlan_filter_set,
 537         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 538         .vlan_offload_set     = ixgbe_vlan_offload_set,
 539         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 540         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 541         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 542         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 543         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 544         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 545         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 546         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 547         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 548         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 549         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 550         .dev_led_on           = ixgbe_dev_led_on,
 551         .dev_led_off          = ixgbe_dev_led_off,
 552         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 553         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 554         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 555         .mac_addr_add         = ixgbe_add_rar,
 556         .mac_addr_remove      = ixgbe_remove_rar,
 557         .mac_addr_set         = ixgbe_set_default_mac_addr,
 558         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 559         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 560         .mirror_rule_set      = ixgbe_mirror_rule_set,
 561         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 562         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 563         .reta_update          = ixgbe_dev_rss_reta_update,
 564         .reta_query           = ixgbe_dev_rss_reta_query,
 565         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 566         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 567         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 568         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 569         .rxq_info_get         = ixgbe_rxq_info_get,
 570         .txq_info_get         = ixgbe_txq_info_get,
 571         .timesync_enable      = ixgbe_timesync_enable,
 572         .timesync_disable     = ixgbe_timesync_disable,
 573         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 574         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 575         .get_reg              = ixgbe_get_regs,
 576         .get_eeprom_length    = ixgbe_get_eeprom_length,
 577         .get_eeprom           = ixgbe_get_eeprom,
 578         .set_eeprom           = ixgbe_set_eeprom,
 579         .get_module_info      = ixgbe_get_module_info,
 580         .get_module_eeprom    = ixgbe_get_module_eeprom,
 581         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 582         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 583         .timesync_read_time   = ixgbe_timesync_read_time,
 584         .timesync_write_time  = ixgbe_timesync_write_time,
 585         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 586         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 587         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 588         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 589         .tm_ops_get           = ixgbe_tm_ops_get,
 590         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 591 };
 592
 593 /*
 594  * dev_ops for virtual function, bare necessities for basic vf
 595  * operation have been implemented
 596  */
 597 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 598         .dev_configure        = ixgbevf_dev_configure,
 599         .dev_start            = ixgbevf_dev_start,
 600         .dev_stop             = ixgbevf_dev_stop,
 601         .link_update          = ixgbevf_dev_link_update,
 602         .stats_get            = ixgbevf_dev_stats_get,
 603         .xstats_get           = ixgbevf_dev_xstats_get,
 604         .stats_reset          = ixgbevf_dev_stats_reset,
 605         .xstats_reset         = ixgbevf_dev_stats_reset,
 606         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 607         .dev_close            = ixgbevf_dev_close,
 608         .dev_reset            = ixgbevf_dev_reset,
 609         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 610         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 611         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 612         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 613         .dev_infos_get        = ixgbevf_dev_info_get,
 614         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 615         .mtu_set              = ixgbevf_dev_set_mtu,
 616         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 617         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 618         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 619         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 620         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 621         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 622         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 623         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 624         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 625         .mac_addr_add         = ixgbevf_add_mac_addr,
 626         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 627         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 628         .rxq_info_get         = ixgbe_rxq_info_get,
 629         .txq_info_get         = ixgbe_txq_info_get,
 630         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 631         .get_reg              = ixgbevf_get_regs,
 632         .reta_update          = ixgbe_dev_rss_reta_update,
 633         .reta_query           = ixgbe_dev_rss_reta_query,
 634         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 635         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 636         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 637 };
 638
 639 /* store statistics names and its offset in stats structure */
 640 struct rte_ixgbe_xstats_name_off {
 641         char name[RTE_ETH_XSTATS_NAME_SIZE];
 642         unsigned offset;
 643 };
 644
 645 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 646         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 647         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 648         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 649         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 650         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 651         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 652         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 653         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 654         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 655         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 656         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 657         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 658         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 659         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 660         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 661                 prc1023)},
 662         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 663                 prc1522)},
 664         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 665         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 666         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 667         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 668         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 669         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 670         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 671         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 672         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 673         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 674         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 675         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 676         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 677         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 678         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 679         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 680         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 681                 ptc1023)},
 682         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 683                 ptc1522)},
 684         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 685         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 686         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 687         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 688
 689         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 690                 fdirustat_add)},
 691         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 692                 fdirustat_remove)},
 693         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 694                 fdirfstat_fadd)},
 695         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 696                 fdirfstat_fremove)},
 697         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 698                 fdirmatch)},
 699         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 700                 fdirmiss)},
 701
 702         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 703         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 704         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 705                 fclast)},
 706         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 707         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 708         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 709         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 710         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 711                 fcoe_noddp)},
 712         {"rx_fcoe_no_direct_data_placement_ext_buff",
 713                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 714
 715         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 716                 lxontxc)},
 717         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 718                 lxonrxc)},
 719         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 720                 lxofftxc)},
 721         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 722                 lxoffrxc)},
 723         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 724 };
 725
 726 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 727                            sizeof(rte_ixgbe_stats_strings[0]))
 728
 729 /* MACsec statistics */
 730 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 731         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 732                 out_pkts_untagged)},
 733         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 734                 out_pkts_encrypted)},
 735         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 736                 out_pkts_protected)},
 737         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 738                 out_octets_encrypted)},
 739         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 740                 out_octets_protected)},
 741         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 742                 in_pkts_untagged)},
 743         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 744                 in_pkts_badtag)},
 745         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 746                 in_pkts_nosci)},
 747         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_unknownsci)},
 749         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 750                 in_octets_decrypted)},
 751         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 752                 in_octets_validated)},
 753         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_unchecked)},
 755         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_delayed)},
 757         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_late)},
 759         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 760                 in_pkts_ok)},
 761         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 762                 in_pkts_invalid)},
 763         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 764                 in_pkts_notvalid)},
 765         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 766                 in_pkts_unusedsa)},
 767         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 768                 in_pkts_notusingsa)},
 769 };
 770
 771 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 772                            sizeof(rte_ixgbe_macsec_strings[0]))
 773
 774 /* Per-queue statistics */
 775 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 776         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 777         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 778         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 779         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 780 };
 781
 782 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 783                            sizeof(rte_ixgbe_rxq_strings[0]))
 784 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 785
 786 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 787         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 788         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 789         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 790                 pxon2offc)},
 791 };
 792
 793 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 794                            sizeof(rte_ixgbe_txq_strings[0]))
 795 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 796
 797 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 798         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 799 };
 800
 801 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 802                 sizeof(rte_ixgbevf_stats_strings[0]))
 803
 804 /*
 805  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 806  */
 807 static inline int
 808 ixgbe_is_sfp(struct ixgbe_hw *hw)
 809 {
 810         switch (hw->phy.type) {
 811         case ixgbe_phy_sfp_avago:
 812         case ixgbe_phy_sfp_ftl:
 813         case ixgbe_phy_sfp_intel:
 814         case ixgbe_phy_sfp_unknown:
 815         case ixgbe_phy_sfp_passive_tyco:
 816         case ixgbe_phy_sfp_passive_unknown:
 817                 return 1;
 818         default:
 819                 return 0;
 820         }
 821 }
 822
 823 static inline int32_t
 824 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 825 {
 826         uint32_t ctrl_ext;
 827         int32_t status;
 828
 829         status = ixgbe_reset_hw(hw);
 830
 831         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 832         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 833         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 834         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 835         IXGBE_WRITE_FLUSH(hw);
 836
 837         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 838                 status = IXGBE_SUCCESS;
 839         return status;
 840 }
 841
 842 static inline void
 843 ixgbe_enable_intr(struct rte_eth_dev *dev)
 844 {
 845         struct ixgbe_interrupt *intr =
 846                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 847         struct ixgbe_hw *hw =
 848                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 849
 850         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 851         IXGBE_WRITE_FLUSH(hw);
 852 }
 853
 854 /*
 855  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 856  */
 857 static void
 858 ixgbe_disable_intr(struct ixgbe_hw *hw)
 859 {
 860         PMD_INIT_FUNC_TRACE();
 861
 862         if (hw->mac.type == ixgbe_mac_82598EB) {
 863                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 864         } else {
 865                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 866                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 867                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 868         }
 869         IXGBE_WRITE_FLUSH(hw);
 870 }
 871
 872 /*
 873  * This function resets queue statistics mapping registers.
 874  * From Niantic datasheet, Initialization of Statistics section:
 875  * "...if software requires the queue counters, the RQSMR and TQSM registers
 876  * must be re-programmed following a device reset.
 877  */
 878 static void
 879 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 880 {
 881         uint32_t i;
 882
 883         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 884                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 885                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 886         }
 887 }
 888
 889
 890 static int
 891 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 892                                   uint16_t queue_id,
 893                                   uint8_t stat_idx,
 894                                   uint8_t is_rx)
 895 {
 896 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 897 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 898 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 899
 900         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 901         struct ixgbe_stat_mapping_registers *stat_mappings =
 902                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 903         uint32_t qsmr_mask = 0;
 904         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 905         uint32_t q_map;
 906         uint8_t n, offset;
 907
 908         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 909                 (hw->mac.type != ixgbe_mac_X540) &&
 910                 (hw->mac.type != ixgbe_mac_X550) &&
 911                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 912                 (hw->mac.type != ixgbe_mac_X550EM_a))
 913                 return -ENOSYS;
 914
 915         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 916                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 917                      queue_id, stat_idx);
 918
 919         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 920         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 921                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 922                 return -EIO;
 923         }
 924         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 925
 926         /* Now clear any previous stat_idx set */
 927         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 928         if (!is_rx)
 929                 stat_mappings->tqsm[n] &= ~clearing_mask;
 930         else
 931                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 932
 933         q_map = (uint32_t)stat_idx;
 934         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 935         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 936         if (!is_rx)
 937                 stat_mappings->tqsm[n] |= qsmr_mask;
 938         else
 939                 stat_mappings->rqsmr[n] |= qsmr_mask;
 940
 941         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 942                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 943                      queue_id, stat_idx);
 944         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 945                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 946
 947         /* Now write the mapping in the appropriate register */
 948         if (is_rx) {
 949                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 950                              stat_mappings->rqsmr[n], n);
 951                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 952         } else {
 953                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 954                              stat_mappings->tqsm[n], n);
 955                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 956         }
 957         return 0;
 958 }
 959
 960 static void
 961 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 962 {
 963         struct ixgbe_stat_mapping_registers *stat_mappings =
 964                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 965         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 966         int i;
 967
 968         /* write whatever was in stat mapping table to the NIC */
 969         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 970                 /* rx */
 971                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 972
 973                 /* tx */
 974                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 975         }
 976 }
 977
 978 static void
 979 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 980 {
 981         uint8_t i;
 982         struct ixgbe_dcb_tc_config *tc;
 983         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 984
 985         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 986         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 987         for (i = 0; i < dcb_max_tc; i++) {
 988                 tc = &dcb_config->tc_config[i];
 989                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 990                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 991                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 992                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 993                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 994                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 995                 tc->pfc = ixgbe_dcb_pfc_disabled;
 996         }
 997
 998         /* Initialize default user to priority mapping, UPx->TC0 */
 999         tc = &dcb_config->tc_config[0];
1000         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1001         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1002         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1003                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1004                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1005         }
1006         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1007         dcb_config->pfc_mode_enable = false;
1008         dcb_config->vt_mode = true;
1009         dcb_config->round_robin_enable = false;
1010         /* support all DCB capabilities in 82599 */
1011         dcb_config->support.capabilities = 0xFF;
1012
1013         /*we only support 4 Tcs for X540, X550 */
1014         if (hw->mac.type == ixgbe_mac_X540 ||
1015                 hw->mac.type == ixgbe_mac_X550 ||
1016                 hw->mac.type == ixgbe_mac_X550EM_x ||
1017                 hw->mac.type == ixgbe_mac_X550EM_a) {
1018                 dcb_config->num_tcs.pg_tcs = 4;
1019                 dcb_config->num_tcs.pfc_tcs = 4;
1020         }
1021 }
1022
1023 /*
1024  * Ensure that all locks are released before first NVM or PHY access
1025  */
1026 static void
1027 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1028 {
1029         uint16_t mask;
1030
1031         /*
1032          * Phy lock should not fail in this early stage. If this is the case,
1033          * it is due to an improper exit of the application.
1034          * So force the release of the faulty lock. Release of common lock
1035          * is done automatically by swfw_sync function.
1036          */
1037         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1038         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1039                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1040         }
1041         ixgbe_release_swfw_semaphore(hw, mask);
1042
1043         /*
1044          * These ones are more tricky since they are common to all ports; but
1045          * swfw_sync retries last long enough (1s) to be almost sure that if
1046          * lock can not be taken it is due to an improper lock of the
1047          * semaphore.
1048          */
1049         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1050         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1051                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1052         }
1053         ixgbe_release_swfw_semaphore(hw, mask);
1054 }
1055
1056 /*
1057  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1058  * It returns 0 on success.
1059  */
1060 static int
1061 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1062 {
1063         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1064         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1065         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1066         struct ixgbe_hw *hw =
1067                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1068         struct ixgbe_vfta *shadow_vfta =
1069                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1070         struct ixgbe_hwstrip *hwstrip =
1071                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1072         struct ixgbe_dcb_config *dcb_config =
1073                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1074         struct ixgbe_filter_info *filter_info =
1075                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1076         struct ixgbe_bw_conf *bw_conf =
1077                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1078         uint32_t ctrl_ext;
1079         uint16_t csum;
1080         int diag, i;
1081
1082         PMD_INIT_FUNC_TRACE();
1083
1084         ixgbe_dev_macsec_setting_reset(eth_dev);
1085
1086         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1087         eth_dev->rx_queue_count       = ixgbe_dev_rx_queue_count;
1088         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1089         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1090         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1091         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1092         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1093         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1094
1095         /*
1096          * For secondary processes, we don't initialise any further as primary
1097          * has already done this work. Only check we don't need a different
1098          * RX and TX function.
1099          */
1100         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1101                 struct ixgbe_tx_queue *txq;
1102                 /* TX queue function in primary, set by last queue initialized
1103                  * Tx queue may not initialized by primary process
1104                  */
1105                 if (eth_dev->data->tx_queues) {
1106                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1107                         ixgbe_set_tx_function(eth_dev, txq);
1108                 } else {
1109                         /* Use default TX function if we get here */
1110                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1111                                      "Using default TX function.");
1112                 }
1113
1114                 ixgbe_set_rx_function(eth_dev);
1115
1116                 return 0;
1117         }
1118
1119         rte_atomic32_clear(&ad->link_thread_running);
1120         rte_eth_copy_pci_info(eth_dev, pci_dev);
1121
1122         /* Vendor and Device ID need to be set before init of shared code */
1123         hw->device_id = pci_dev->id.device_id;
1124         hw->vendor_id = pci_dev->id.vendor_id;
1125         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1126         hw->allow_unsupported_sfp = 1;
1127
1128         /* Initialize the shared code (base driver) */
1129 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1130         diag = ixgbe_bypass_init_shared_code(hw);
1131 #else
1132         diag = ixgbe_init_shared_code(hw);
1133 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1134
1135         if (diag != IXGBE_SUCCESS) {
1136                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1137                 return -EIO;
1138         }
1139
1140         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1141                 PMD_INIT_LOG(ERR, "\nERROR: "
1142                         "Firmware recovery mode detected. Limiting functionality.\n"
1143                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1144                         "User Guide for details on firmware recovery mode.");
1145                 return -EIO;
1146         }
1147
1148         /* pick up the PCI bus settings for reporting later */
1149         ixgbe_get_bus_info(hw);
1150
1151         /* Unlock any pending hardware semaphore */
1152         ixgbe_swfw_lock_reset(hw);
1153
1154 #ifdef RTE_LIBRTE_SECURITY
1155         /* Initialize security_ctx only for primary process*/
1156         if (ixgbe_ipsec_ctx_create(eth_dev))
1157                 return -ENOMEM;
1158 #endif
1159
1160         /* Initialize DCB configuration*/
1161         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1162         ixgbe_dcb_init(hw, dcb_config);
1163         /* Get Hardware Flow Control setting */
1164         hw->fc.requested_mode = ixgbe_fc_none;
1165         hw->fc.current_mode = ixgbe_fc_none;
1166         hw->fc.pause_time = IXGBE_FC_PAUSE;
1167         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1168                 hw->fc.low_water[i] = IXGBE_FC_LO;
1169                 hw->fc.high_water[i] = IXGBE_FC_HI;
1170         }
1171         hw->fc.send_xon = 1;
1172
1173         /* Make sure we have a good EEPROM before we read from it */
1174         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1175         if (diag != IXGBE_SUCCESS) {
1176                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1177                 return -EIO;
1178         }
1179
1180 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1181         diag = ixgbe_bypass_init_hw(hw);
1182 #else
1183         diag = ixgbe_init_hw(hw);
1184 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1185
1186         /*
1187          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1188          * is called too soon after the kernel driver unbinding/binding occurs.
1189          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1190          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1191          * also called. See ixgbe_identify_phy_82599(). The reason for the
1192          * failure is not known, and only occuts when virtualisation features
1193          * are disabled in the bios. A delay of 100ms  was found to be enough by
1194          * trial-and-error, and is doubled to be safe.
1195          */
1196         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1197                 rte_delay_ms(200);
1198                 diag = ixgbe_init_hw(hw);
1199         }
1200
1201         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1202                 diag = IXGBE_SUCCESS;
1203
1204         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1205                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1206                              "LOM.  Please be aware there may be issues associated "
1207                              "with your hardware.");
1208                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1209                              "please contact your Intel or hardware representative "
1210                              "who provided you with this hardware.");
1211         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1212                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1213         if (diag) {
1214                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1215                 return -EIO;
1216         }
1217
1218         /* Reset the hw statistics */
1219         ixgbe_dev_stats_reset(eth_dev);
1220
1221         /* disable interrupt */
1222         ixgbe_disable_intr(hw);
1223
1224         /* reset mappings for queue statistics hw counters*/
1225         ixgbe_reset_qstat_mappings(hw);
1226
1227         /* Allocate memory for storing MAC addresses */
1228         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1229                                                hw->mac.num_rar_entries, 0);
1230         if (eth_dev->data->mac_addrs == NULL) {
1231                 PMD_INIT_LOG(ERR,
1232                              "Failed to allocate %u bytes needed to store "
1233                              "MAC addresses",
1234                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1235                 return -ENOMEM;
1236         }
1237         /* Copy the permanent MAC address */
1238         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1239                         &eth_dev->data->mac_addrs[0]);
1240
1241         /* Allocate memory for storing hash filter MAC addresses */
1242         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1243                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1244         if (eth_dev->data->hash_mac_addrs == NULL) {
1245                 PMD_INIT_LOG(ERR,
1246                              "Failed to allocate %d bytes needed to store MAC addresses",
1247                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1248                 return -ENOMEM;
1249         }
1250
1251         /* initialize the vfta */
1252         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1253
1254         /* initialize the hw strip bitmap*/
1255         memset(hwstrip, 0, sizeof(*hwstrip));
1256
1257         /* initialize PF if max_vfs not zero */
1258         ixgbe_pf_host_init(eth_dev);
1259
1260         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1261         /* let hardware know driver is loaded */
1262         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1263         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1264         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1265         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1266         IXGBE_WRITE_FLUSH(hw);
1267
1268         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1269                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1270                              (int) hw->mac.type, (int) hw->phy.type,
1271                              (int) hw->phy.sfp_type);
1272         else
1273                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1274                              (int) hw->mac.type, (int) hw->phy.type);
1275
1276         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1277                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1278                      pci_dev->id.device_id);
1279
1280         rte_intr_callback_register(intr_handle,
1281                                    ixgbe_dev_interrupt_handler, eth_dev);
1282
1283         /* enable uio/vfio intr/eventfd mapping */
1284         rte_intr_enable(intr_handle);
1285
1286         /* enable support intr */
1287         ixgbe_enable_intr(eth_dev);
1288
1289         /* initialize filter info */
1290         memset(filter_info, 0,
1291                sizeof(struct ixgbe_filter_info));
1292
1293         /* initialize 5tuple filter list */
1294         TAILQ_INIT(&filter_info->fivetuple_list);
1295
1296         /* initialize flow director filter list & hash */
1297         ixgbe_fdir_filter_init(eth_dev);
1298
1299         /* initialize l2 tunnel filter list & hash */
1300         ixgbe_l2_tn_filter_init(eth_dev);
1301
1302         /* initialize flow filter lists */
1303         ixgbe_filterlist_init();
1304
1305         /* initialize bandwidth configuration info */
1306         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1307
1308         /* initialize Traffic Manager configuration */
1309         ixgbe_tm_conf_init(eth_dev);
1310
1311         return 0;
1312 }
1313
1314 static int
1315 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1316 {
1317         PMD_INIT_FUNC_TRACE();
1318
1319         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1320                 return 0;
1321
1322         ixgbe_dev_close(eth_dev);
1323
1324         return 0;
1325 }
1326
1327 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1328 {
1329         struct ixgbe_filter_info *filter_info =
1330                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1331         struct ixgbe_5tuple_filter *p_5tuple;
1332
1333         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1334                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1335                              p_5tuple,
1336                              entries);
1337                 rte_free(p_5tuple);
1338         }
1339         memset(filter_info->fivetuple_mask, 0,
1340                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1341
1342         return 0;
1343 }
1344
1345 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1346 {
1347         struct ixgbe_hw_fdir_info *fdir_info =
1348                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1349         struct ixgbe_fdir_filter *fdir_filter;
1350
1351                 if (fdir_info->hash_map)
1352                 rte_free(fdir_info->hash_map);
1353         if (fdir_info->hash_handle)
1354                 rte_hash_free(fdir_info->hash_handle);
1355
1356         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1357                 TAILQ_REMOVE(&fdir_info->fdir_list,
1358                              fdir_filter,
1359                              entries);
1360                 rte_free(fdir_filter);
1361         }
1362
1363         return 0;
1364 }
1365
1366 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1367 {
1368         struct ixgbe_l2_tn_info *l2_tn_info =
1369                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1370         struct ixgbe_l2_tn_filter *l2_tn_filter;
1371
1372         if (l2_tn_info->hash_map)
1373                 rte_free(l2_tn_info->hash_map);
1374         if (l2_tn_info->hash_handle)
1375                 rte_hash_free(l2_tn_info->hash_handle);
1376
1377         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1378                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1379                              l2_tn_filter,
1380                              entries);
1381                 rte_free(l2_tn_filter);
1382         }
1383
1384         return 0;
1385 }
1386
1387 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1388 {
1389         struct ixgbe_hw_fdir_info *fdir_info =
1390                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1391         char fdir_hash_name[RTE_HASH_NAMESIZE];
1392         struct rte_hash_parameters fdir_hash_params = {
1393                 .name = fdir_hash_name,
1394                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1395                 .key_len = sizeof(union ixgbe_atr_input),
1396                 .hash_func = rte_hash_crc,
1397                 .hash_func_init_val = 0,
1398                 .socket_id = rte_socket_id(),
1399         };
1400
1401         TAILQ_INIT(&fdir_info->fdir_list);
1402         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1403                  "fdir_%s", eth_dev->device->name);
1404         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1405         if (!fdir_info->hash_handle) {
1406                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1407                 return -EINVAL;
1408         }
1409         fdir_info->hash_map = rte_zmalloc("ixgbe",
1410                                           sizeof(struct ixgbe_fdir_filter *) *
1411                                           IXGBE_MAX_FDIR_FILTER_NUM,
1412                                           0);
1413         if (!fdir_info->hash_map) {
1414                 PMD_INIT_LOG(ERR,
1415                              "Failed to allocate memory for fdir hash map!");
1416                 return -ENOMEM;
1417         }
1418         fdir_info->mask_added = FALSE;
1419
1420         return 0;
1421 }
1422
1423 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1424 {
1425         struct ixgbe_l2_tn_info *l2_tn_info =
1426                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1427         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1428         struct rte_hash_parameters l2_tn_hash_params = {
1429                 .name = l2_tn_hash_name,
1430                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1431                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1432                 .hash_func = rte_hash_crc,
1433                 .hash_func_init_val = 0,
1434                 .socket_id = rte_socket_id(),
1435         };
1436
1437         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1438         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1439                  "l2_tn_%s", eth_dev->device->name);
1440         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1441         if (!l2_tn_info->hash_handle) {
1442                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1443                 return -EINVAL;
1444         }
1445         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1446                                    sizeof(struct ixgbe_l2_tn_filter *) *
1447                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1448                                    0);
1449         if (!l2_tn_info->hash_map) {
1450                 PMD_INIT_LOG(ERR,
1451                         "Failed to allocate memory for L2 TN hash map!");
1452                 return -ENOMEM;
1453         }
1454         l2_tn_info->e_tag_en = FALSE;
1455         l2_tn_info->e_tag_fwd_en = FALSE;
1456         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1457
1458         return 0;
1459 }
1460 /*
1461  * Negotiate mailbox API version with the PF.
1462  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1463  * Then we try to negotiate starting with the most recent one.
1464  * If all negotiation attempts fail, then we will proceed with
1465  * the default one (ixgbe_mbox_api_10).
1466  */
1467 static void
1468 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1469 {
1470         int32_t i;
1471
1472         /* start with highest supported, proceed down */
1473         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1474                 ixgbe_mbox_api_13,
1475                 ixgbe_mbox_api_12,
1476                 ixgbe_mbox_api_11,
1477                 ixgbe_mbox_api_10,
1478         };
1479
1480         for (i = 0;
1481                         i != RTE_DIM(sup_ver) &&
1482                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1483                         i++)
1484                 ;
1485 }
1486
1487 static void
1488 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1489 {
1490         uint64_t random;
1491
1492         /* Set Organizationally Unique Identifier (OUI) prefix. */
1493         mac_addr->addr_bytes[0] = 0x00;
1494         mac_addr->addr_bytes[1] = 0x09;
1495         mac_addr->addr_bytes[2] = 0xC0;
1496         /* Force indication of locally assigned MAC address. */
1497         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1498         /* Generate the last 3 bytes of the MAC address with a random number. */
1499         random = rte_rand();
1500         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1501 }
1502
1503 static int
1504 devarg_handle_int(__rte_unused const char *key, const char *value,
1505                   void *extra_args)
1506 {
1507         uint16_t *n = extra_args;
1508
1509         if (value == NULL || extra_args == NULL)
1510                 return -EINVAL;
1511
1512         *n = (uint16_t)strtoul(value, NULL, 0);
1513         if (*n == USHRT_MAX && errno == ERANGE)
1514                 return -1;
1515
1516         return 0;
1517 }
1518
1519 static void
1520 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1521                       struct rte_devargs *devargs)
1522 {
1523         struct rte_kvargs *kvlist;
1524         uint16_t pflink_fullchk;
1525
1526         if (devargs == NULL)
1527                 return;
1528
1529         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1530         if (kvlist == NULL)
1531                 return;
1532
1533         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1534             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1535                                devarg_handle_int, &pflink_fullchk) == 0 &&
1536             pflink_fullchk == 1)
1537                 adapter->pflink_fullchk = 1;
1538
1539         rte_kvargs_free(kvlist);
1540 }
1541
1542 /*
1543  * Virtual Function device init
1544  */
1545 static int
1546 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1547 {
1548         int diag;
1549         uint32_t tc, tcs;
1550         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1551         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1552         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1553         struct ixgbe_hw *hw =
1554                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1555         struct ixgbe_vfta *shadow_vfta =
1556                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1557         struct ixgbe_hwstrip *hwstrip =
1558                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1559         struct rte_ether_addr *perm_addr =
1560                 (struct rte_ether_addr *)hw->mac.perm_addr;
1561
1562         PMD_INIT_FUNC_TRACE();
1563
1564         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1565         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1566         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1567         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1568         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1569         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1570
1571         /* for secondary processes, we don't initialise any further as primary
1572          * has already done this work. Only check we don't need a different
1573          * RX function
1574          */
1575         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1576                 struct ixgbe_tx_queue *txq;
1577                 /* TX queue function in primary, set by last queue initialized
1578                  * Tx queue may not initialized by primary process
1579                  */
1580                 if (eth_dev->data->tx_queues) {
1581                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1582                         ixgbe_set_tx_function(eth_dev, txq);
1583                 } else {
1584                         /* Use default TX function if we get here */
1585                         PMD_INIT_LOG(NOTICE,
1586                                      "No TX queues configured yet. Using default TX function.");
1587                 }
1588
1589                 ixgbe_set_rx_function(eth_dev);
1590
1591                 return 0;
1592         }
1593
1594         rte_atomic32_clear(&ad->link_thread_running);
1595         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1596                               pci_dev->device.devargs);
1597
1598         rte_eth_copy_pci_info(eth_dev, pci_dev);
1599
1600         hw->device_id = pci_dev->id.device_id;
1601         hw->vendor_id = pci_dev->id.vendor_id;
1602         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1603
1604         /* initialize the vfta */
1605         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1606
1607         /* initialize the hw strip bitmap*/
1608         memset(hwstrip, 0, sizeof(*hwstrip));
1609
1610         /* Initialize the shared code (base driver) */
1611         diag = ixgbe_init_shared_code(hw);
1612         if (diag != IXGBE_SUCCESS) {
1613                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1614                 return -EIO;
1615         }
1616
1617         /* init_mailbox_params */
1618         hw->mbx.ops.init_params(hw);
1619
1620         /* Reset the hw statistics */
1621         ixgbevf_dev_stats_reset(eth_dev);
1622
1623         /* Disable the interrupts for VF */
1624         ixgbevf_intr_disable(eth_dev);
1625
1626         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1627         diag = hw->mac.ops.reset_hw(hw);
1628
1629         /*
1630          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1631          * the underlying PF driver has not assigned a MAC address to the VF.
1632          * In this case, assign a random MAC address.
1633          */
1634         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1635                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1636                 /*
1637                  * This error code will be propagated to the app by
1638                  * rte_eth_dev_reset, so use a public error code rather than
1639                  * the internal-only IXGBE_ERR_RESET_FAILED
1640                  */
1641                 return -EAGAIN;
1642         }
1643
1644         /* negotiate mailbox API version to use with the PF. */
1645         ixgbevf_negotiate_api(hw);
1646
1647         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1648         ixgbevf_get_queues(hw, &tcs, &tc);
1649
1650         /* Allocate memory for storing MAC addresses */
1651         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1652                                                hw->mac.num_rar_entries, 0);
1653         if (eth_dev->data->mac_addrs == NULL) {
1654                 PMD_INIT_LOG(ERR,
1655                              "Failed to allocate %u bytes needed to store "
1656                              "MAC addresses",
1657                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1658                 return -ENOMEM;
1659         }
1660
1661         /* Generate a random MAC address, if none was assigned by PF. */
1662         if (rte_is_zero_ether_addr(perm_addr)) {
1663                 generate_random_mac_addr(perm_addr);
1664                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1665                 if (diag) {
1666                         rte_free(eth_dev->data->mac_addrs);
1667                         eth_dev->data->mac_addrs = NULL;
1668                         return diag;
1669                 }
1670                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1671                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1672                              "%02x:%02x:%02x:%02x:%02x:%02x",
1673                              perm_addr->addr_bytes[0],
1674                              perm_addr->addr_bytes[1],
1675                              perm_addr->addr_bytes[2],
1676                              perm_addr->addr_bytes[3],
1677                              perm_addr->addr_bytes[4],
1678                              perm_addr->addr_bytes[5]);
1679         }
1680
1681         /* Copy the permanent MAC address */
1682         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1683
1684         /* reset the hardware with the new settings */
1685         diag = hw->mac.ops.start_hw(hw);
1686         switch (diag) {
1687         case  0:
1688                 break;
1689
1690         default:
1691                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1692                 return -EIO;
1693         }
1694
1695         rte_intr_callback_register(intr_handle,
1696                                    ixgbevf_dev_interrupt_handler, eth_dev);
1697         rte_intr_enable(intr_handle);
1698         ixgbevf_intr_enable(eth_dev);
1699
1700         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1701                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1702                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1703
1704         return 0;
1705 }
1706
1707 /* Virtual Function device uninit */
1708
1709 static int
1710 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1711 {
1712         PMD_INIT_FUNC_TRACE();
1713
1714         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1715                 return 0;
1716
1717         ixgbevf_dev_close(eth_dev);
1718
1719         return 0;
1720 }
1721
1722 static int
1723 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1724                 struct rte_pci_device *pci_dev)
1725 {
1726         char name[RTE_ETH_NAME_MAX_LEN];
1727         struct rte_eth_dev *pf_ethdev;
1728         struct rte_eth_devargs eth_da;
1729         int i, retval;
1730
1731         if (pci_dev->device.devargs) {
1732                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1733                                 &eth_da);
1734                 if (retval)
1735                         return retval;
1736         } else
1737                 memset(&eth_da, 0, sizeof(eth_da));
1738
1739         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1740                 sizeof(struct ixgbe_adapter),
1741                 eth_dev_pci_specific_init, pci_dev,
1742                 eth_ixgbe_dev_init, NULL);
1743
1744         if (retval || eth_da.nb_representor_ports < 1)
1745                 return retval;
1746
1747         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1748         if (pf_ethdev == NULL)
1749                 return -ENODEV;
1750
1751         /* probe VF representor ports */
1752         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1753                 struct ixgbe_vf_info *vfinfo;
1754                 struct ixgbe_vf_representor representor;
1755
1756                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1757                         pf_ethdev->data->dev_private);
1758                 if (vfinfo == NULL) {
1759                         PMD_DRV_LOG(ERR,
1760                                 "no virtual functions supported by PF");
1761                         break;
1762                 }
1763
1764                 representor.vf_id = eth_da.representor_ports[i];
1765                 representor.switch_domain_id = vfinfo->switch_domain_id;
1766                 representor.pf_ethdev = pf_ethdev;
1767
1768                 /* representor port net_bdf_port */
1769                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1770                         pci_dev->device.name,
1771                         eth_da.representor_ports[i]);
1772
1773                 retval = rte_eth_dev_create(&pci_dev->device, name,
1774                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1775                         ixgbe_vf_representor_init, &representor);
1776
1777                 if (retval)
1778                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1779                                 "representor %s.", name);
1780         }
1781
1782         return 0;
1783 }
1784
1785 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1786 {
1787         struct rte_eth_dev *ethdev;
1788
1789         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1790         if (!ethdev)
1791                 return 0;
1792
1793         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1794                 return rte_eth_dev_pci_generic_remove(pci_dev,
1795                                         ixgbe_vf_representor_uninit);
1796         else
1797                 return rte_eth_dev_pci_generic_remove(pci_dev,
1798                                                 eth_ixgbe_dev_uninit);
1799 }
1800
1801 static struct rte_pci_driver rte_ixgbe_pmd = {
1802         .id_table = pci_id_ixgbe_map,
1803         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1804         .probe = eth_ixgbe_pci_probe,
1805         .remove = eth_ixgbe_pci_remove,
1806 };
1807
1808 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1809         struct rte_pci_device *pci_dev)
1810 {
1811         return rte_eth_dev_pci_generic_probe(pci_dev,
1812                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1813 }
1814
1815 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1816 {
1817         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1818 }
1819
1820 /*
1821  * virtual function driver struct
1822  */
1823 static struct rte_pci_driver rte_ixgbevf_pmd = {
1824         .id_table = pci_id_ixgbevf_map,
1825         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1826         .probe = eth_ixgbevf_pci_probe,
1827         .remove = eth_ixgbevf_pci_remove,
1828 };
1829
1830 static int
1831 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1832 {
1833         struct ixgbe_hw *hw =
1834                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1835         struct ixgbe_vfta *shadow_vfta =
1836                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1837         uint32_t vfta;
1838         uint32_t vid_idx;
1839         uint32_t vid_bit;
1840
1841         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1842         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1843         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1844         if (on)
1845                 vfta |= vid_bit;
1846         else
1847                 vfta &= ~vid_bit;
1848         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1849
1850         /* update local VFTA copy */
1851         shadow_vfta->vfta[vid_idx] = vfta;
1852
1853         return 0;
1854 }
1855
1856 static void
1857 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1858 {
1859         if (on)
1860                 ixgbe_vlan_hw_strip_enable(dev, queue);
1861         else
1862                 ixgbe_vlan_hw_strip_disable(dev, queue);
1863 }
1864
1865 static int
1866 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1867                     enum rte_vlan_type vlan_type,
1868                     uint16_t tpid)
1869 {
1870         struct ixgbe_hw *hw =
1871                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872         int ret = 0;
1873         uint32_t reg;
1874         uint32_t qinq;
1875
1876         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1877         qinq &= IXGBE_DMATXCTL_GDV;
1878
1879         switch (vlan_type) {
1880         case ETH_VLAN_TYPE_INNER:
1881                 if (qinq) {
1882                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1883                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1884                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1885                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1886                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1887                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1888                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1889                 } else {
1890                         ret = -ENOTSUP;
1891                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1892                                     " by single VLAN");
1893                 }
1894                 break;
1895         case ETH_VLAN_TYPE_OUTER:
1896                 if (qinq) {
1897                         /* Only the high 16-bits is valid */
1898                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1899                                         IXGBE_EXVET_VET_EXT_SHIFT);
1900                 } else {
1901                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1902                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1903                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1904                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1905                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1906                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1907                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1908                 }
1909
1910                 break;
1911         default:
1912                 ret = -EINVAL;
1913                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1914                 break;
1915         }
1916
1917         return ret;
1918 }
1919
1920 void
1921 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1922 {
1923         struct ixgbe_hw *hw =
1924                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1925         uint32_t vlnctrl;
1926
1927         PMD_INIT_FUNC_TRACE();
1928
1929         /* Filter Table Disable */
1930         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1931         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1932
1933         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1934 }
1935
1936 void
1937 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1938 {
1939         struct ixgbe_hw *hw =
1940                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1941         struct ixgbe_vfta *shadow_vfta =
1942                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1943         uint32_t vlnctrl;
1944         uint16_t i;
1945
1946         PMD_INIT_FUNC_TRACE();
1947
1948         /* Filter Table Enable */
1949         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1950         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1951         vlnctrl |= IXGBE_VLNCTRL_VFE;
1952
1953         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1954
1955         /* write whatever is in local vfta copy */
1956         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1957                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1958 }
1959
1960 static void
1961 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1962 {
1963         struct ixgbe_hwstrip *hwstrip =
1964                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1965         struct ixgbe_rx_queue *rxq;
1966
1967         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1968                 return;
1969
1970         if (on)
1971                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1972         else
1973                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1974
1975         if (queue >= dev->data->nb_rx_queues)
1976                 return;
1977
1978         rxq = dev->data->rx_queues[queue];
1979
1980         if (on) {
1981                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1982                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1983         } else {
1984                 rxq->vlan_flags = PKT_RX_VLAN;
1985                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1986         }
1987 }
1988
1989 static void
1990 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1991 {
1992         struct ixgbe_hw *hw =
1993                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1994         uint32_t ctrl;
1995
1996         PMD_INIT_FUNC_TRACE();
1997
1998         if (hw->mac.type == ixgbe_mac_82598EB) {
1999                 /* No queue level support */
2000                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2001                 return;
2002         }
2003
2004         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2005         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2006         ctrl &= ~IXGBE_RXDCTL_VME;
2007         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2008
2009         /* record those setting for HW strip per queue */
2010         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2011 }
2012
2013 static void
2014 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2015 {
2016         struct ixgbe_hw *hw =
2017                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2018         uint32_t ctrl;
2019
2020         PMD_INIT_FUNC_TRACE();
2021
2022         if (hw->mac.type == ixgbe_mac_82598EB) {
2023                 /* No queue level supported */
2024                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2025                 return;
2026         }
2027
2028         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2029         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2030         ctrl |= IXGBE_RXDCTL_VME;
2031         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2032
2033         /* record those setting for HW strip per queue */
2034         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2035 }
2036
2037 static void
2038 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2039 {
2040         struct ixgbe_hw *hw =
2041                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2042         uint32_t ctrl;
2043
2044         PMD_INIT_FUNC_TRACE();
2045
2046         /* DMATXCTRL: Geric Double VLAN Disable */
2047         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2048         ctrl &= ~IXGBE_DMATXCTL_GDV;
2049         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2050
2051         /* CTRL_EXT: Global Double VLAN Disable */
2052         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2053         ctrl &= ~IXGBE_EXTENDED_VLAN;
2054         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2055
2056 }
2057
2058 static void
2059 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2060 {
2061         struct ixgbe_hw *hw =
2062                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2063         uint32_t ctrl;
2064
2065         PMD_INIT_FUNC_TRACE();
2066
2067         /* DMATXCTRL: Geric Double VLAN Enable */
2068         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2069         ctrl |= IXGBE_DMATXCTL_GDV;
2070         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2071
2072         /* CTRL_EXT: Global Double VLAN Enable */
2073         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2074         ctrl |= IXGBE_EXTENDED_VLAN;
2075         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2076
2077         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2078         if (hw->mac.type == ixgbe_mac_X550 ||
2079             hw->mac.type == ixgbe_mac_X550EM_x ||
2080             hw->mac.type == ixgbe_mac_X550EM_a) {
2081                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2082                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2083                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2084         }
2085
2086         /*
2087          * VET EXT field in the EXVET register = 0x8100 by default
2088          * So no need to change. Same to VT field of DMATXCTL register
2089          */
2090 }
2091
2092 void
2093 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2094 {
2095         struct ixgbe_hw *hw =
2096                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2097         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2098         uint32_t ctrl;
2099         uint16_t i;
2100         struct ixgbe_rx_queue *rxq;
2101         bool on;
2102
2103         PMD_INIT_FUNC_TRACE();
2104
2105         if (hw->mac.type == ixgbe_mac_82598EB) {
2106                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2107                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2108                         ctrl |= IXGBE_VLNCTRL_VME;
2109                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2110                 } else {
2111                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2112                         ctrl &= ~IXGBE_VLNCTRL_VME;
2113                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2114                 }
2115         } else {
2116                 /*
2117                  * Other 10G NIC, the VLAN strip can be setup
2118                  * per queue in RXDCTL
2119                  */
2120                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2121                         rxq = dev->data->rx_queues[i];
2122                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2123                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2124                                 ctrl |= IXGBE_RXDCTL_VME;
2125                                 on = TRUE;
2126                         } else {
2127                                 ctrl &= ~IXGBE_RXDCTL_VME;
2128                                 on = FALSE;
2129                         }
2130                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2131
2132                         /* record those setting for HW strip per queue */
2133                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2134                 }
2135         }
2136 }
2137
2138 static void
2139 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2140 {
2141         uint16_t i;
2142         struct rte_eth_rxmode *rxmode;
2143         struct ixgbe_rx_queue *rxq;
2144
2145         if (mask & ETH_VLAN_STRIP_MASK) {
2146                 rxmode = &dev->data->dev_conf.rxmode;
2147                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2148                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2149                                 rxq = dev->data->rx_queues[i];
2150                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2151                         }
2152                 else
2153                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2154                                 rxq = dev->data->rx_queues[i];
2155                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2156                         }
2157         }
2158 }
2159
2160 static int
2161 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2162 {
2163         struct rte_eth_rxmode *rxmode;
2164         rxmode = &dev->data->dev_conf.rxmode;
2165
2166         if (mask & ETH_VLAN_STRIP_MASK) {
2167                 ixgbe_vlan_hw_strip_config(dev);
2168         }
2169
2170         if (mask & ETH_VLAN_FILTER_MASK) {
2171                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2172                         ixgbe_vlan_hw_filter_enable(dev);
2173                 else
2174                         ixgbe_vlan_hw_filter_disable(dev);
2175         }
2176
2177         if (mask & ETH_VLAN_EXTEND_MASK) {
2178                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2179                         ixgbe_vlan_hw_extend_enable(dev);
2180                 else
2181                         ixgbe_vlan_hw_extend_disable(dev);
2182         }
2183
2184         return 0;
2185 }
2186
2187 static int
2188 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2189 {
2190         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2191
2192         ixgbe_vlan_offload_config(dev, mask);
2193
2194         return 0;
2195 }
2196
2197 static void
2198 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2199 {
2200         struct ixgbe_hw *hw =
2201                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2202         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2203         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2204
2205         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2206         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2207 }
2208
2209 static int
2210 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2211 {
2212         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2213
2214         switch (nb_rx_q) {
2215         case 1:
2216         case 2:
2217                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2218                 break;
2219         case 4:
2220                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2221                 break;
2222         default:
2223                 return -EINVAL;
2224         }
2225
2226         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2227                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2228         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2229                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2230         return 0;
2231 }
2232
2233 static int
2234 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2235 {
2236         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2237         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2238         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2239         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2240
2241         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2242                 /* check multi-queue mode */
2243                 switch (dev_conf->rxmode.mq_mode) {
2244                 case ETH_MQ_RX_VMDQ_DCB:
2245                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2246                         break;
2247                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2248                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2249                         PMD_INIT_LOG(ERR, "SRIOV active,"
2250                                         " unsupported mq_mode rx %d.",
2251                                         dev_conf->rxmode.mq_mode);
2252                         return -EINVAL;
2253                 case ETH_MQ_RX_RSS:
2254                 case ETH_MQ_RX_VMDQ_RSS:
2255                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2256                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2257                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2258                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2259                                                 " invalid queue number"
2260                                                 " for VMDQ RSS, allowed"
2261                                                 " value are 1, 2 or 4.");
2262                                         return -EINVAL;
2263                                 }
2264                         break;
2265                 case ETH_MQ_RX_VMDQ_ONLY:
2266                 case ETH_MQ_RX_NONE:
2267                         /* if nothing mq mode configure, use default scheme */
2268                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2269                         break;
2270                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2271                         /* SRIOV only works in VMDq enable mode */
2272                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2273                                         " wrong mq_mode rx %d.",
2274                                         dev_conf->rxmode.mq_mode);
2275                         return -EINVAL;
2276                 }
2277
2278                 switch (dev_conf->txmode.mq_mode) {
2279                 case ETH_MQ_TX_VMDQ_DCB:
2280                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2281                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2282                         break;
2283                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2284                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2285                         break;
2286                 }
2287
2288                 /* check valid queue number */
2289                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2290                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2291                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2292                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2293                                         " must be less than or equal to %d.",
2294                                         nb_rx_q, nb_tx_q,
2295                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2296                         return -EINVAL;
2297                 }
2298         } else {
2299                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2300                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2301                                           " not supported.");
2302                         return -EINVAL;
2303                 }
2304                 /* check configuration for vmdb+dcb mode */
2305                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2306                         const struct rte_eth_vmdq_dcb_conf *conf;
2307
2308                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2309                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2310                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2311                                 return -EINVAL;
2312                         }
2313                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2314                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2315                                conf->nb_queue_pools == ETH_32_POOLS)) {
2316                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2317                                                 " nb_queue_pools must be %d or %d.",
2318                                                 ETH_16_POOLS, ETH_32_POOLS);
2319                                 return -EINVAL;
2320                         }
2321                 }
2322                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2323                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2324
2325                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2326                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2327                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2328                                 return -EINVAL;
2329                         }
2330                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2331                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2332                                conf->nb_queue_pools == ETH_32_POOLS)) {
2333                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2334                                                 " nb_queue_pools != %d and"
2335                                                 " nb_queue_pools != %d.",
2336                                                 ETH_16_POOLS, ETH_32_POOLS);
2337                                 return -EINVAL;
2338                         }
2339                 }
2340
2341                 /* For DCB mode check our configuration before we go further */
2342                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2343                         const struct rte_eth_dcb_rx_conf *conf;
2344
2345                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2346                         if (!(conf->nb_tcs == ETH_4_TCS ||
2347                                conf->nb_tcs == ETH_8_TCS)) {
2348                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2349                                                 " and nb_tcs != %d.",
2350                                                 ETH_4_TCS, ETH_8_TCS);
2351                                 return -EINVAL;
2352                         }
2353                 }
2354
2355                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2356                         const struct rte_eth_dcb_tx_conf *conf;
2357
2358                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2359                         if (!(conf->nb_tcs == ETH_4_TCS ||
2360                                conf->nb_tcs == ETH_8_TCS)) {
2361                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2362                                                 " and nb_tcs != %d.",
2363                                                 ETH_4_TCS, ETH_8_TCS);
2364                                 return -EINVAL;
2365                         }
2366                 }
2367
2368                 /*
2369                  * When DCB/VT is off, maximum number of queues changes,
2370                  * except for 82598EB, which remains constant.
2371                  */
2372                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2373                                 hw->mac.type != ixgbe_mac_82598EB) {
2374                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2375                                 PMD_INIT_LOG(ERR,
2376                                              "Neither VT nor DCB are enabled, "
2377                                              "nb_tx_q > %d.",
2378                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2379                                 return -EINVAL;
2380                         }
2381                 }
2382         }
2383         return 0;
2384 }
2385
2386 static int
2387 ixgbe_dev_configure(struct rte_eth_dev *dev)
2388 {
2389         struct ixgbe_interrupt *intr =
2390                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2391         struct ixgbe_adapter *adapter = dev->data->dev_private;
2392         int ret;
2393
2394         PMD_INIT_FUNC_TRACE();
2395
2396         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2397                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2398
2399         /* multipe queue mode checking */
2400         ret  = ixgbe_check_mq_mode(dev);
2401         if (ret != 0) {
2402                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2403                             ret);
2404                 return ret;
2405         }
2406
2407         /* set flag to update link status after init */
2408         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2409
2410         /*
2411          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2412          * allocation or vector Rx preconditions we will reset it.
2413          */
2414         adapter->rx_bulk_alloc_allowed = true;
2415         adapter->rx_vec_allowed = true;
2416
2417         return 0;
2418 }
2419
2420 static void
2421 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2422 {
2423         struct ixgbe_hw *hw =
2424                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2425         struct ixgbe_interrupt *intr =
2426                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2427         uint32_t gpie;
2428
2429         /* only set up it on X550EM_X */
2430         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2431                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2432                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2433                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2434                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2435                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2436         }
2437 }
2438
2439 int
2440 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2441                         uint16_t tx_rate, uint64_t q_msk)
2442 {
2443         struct ixgbe_hw *hw;
2444         struct ixgbe_vf_info *vfinfo;
2445         struct rte_eth_link link;
2446         uint8_t  nb_q_per_pool;
2447         uint32_t queue_stride;
2448         uint32_t queue_idx, idx = 0, vf_idx;
2449         uint32_t queue_end;
2450         uint16_t total_rate = 0;
2451         struct rte_pci_device *pci_dev;
2452         int ret;
2453
2454         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2455         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2456         if (ret < 0)
2457                 return ret;
2458
2459         if (vf >= pci_dev->max_vfs)
2460                 return -EINVAL;
2461
2462         if (tx_rate > link.link_speed)
2463                 return -EINVAL;
2464
2465         if (q_msk == 0)
2466                 return 0;
2467
2468         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2469         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2470         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2471         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2472         queue_idx = vf * queue_stride;
2473         queue_end = queue_idx + nb_q_per_pool - 1;
2474         if (queue_end >= hw->mac.max_tx_queues)
2475                 return -EINVAL;
2476
2477         if (vfinfo) {
2478                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2479                         if (vf_idx == vf)
2480                                 continue;
2481                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2482                                 idx++)
2483                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2484                 }
2485         } else {
2486                 return -EINVAL;
2487         }
2488
2489         /* Store tx_rate for this vf. */
2490         for (idx = 0; idx < nb_q_per_pool; idx++) {
2491                 if (((uint64_t)0x1 << idx) & q_msk) {
2492                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2493                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2494                         total_rate += tx_rate;
2495                 }
2496         }
2497
2498         if (total_rate > dev->data->dev_link.link_speed) {
2499                 /* Reset stored TX rate of the VF if it causes exceed
2500                  * link speed.
2501                  */
2502                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2503                 return -EINVAL;
2504         }
2505
2506         /* Set RTTBCNRC of each queue/pool for vf X  */
2507         for (; queue_idx <= queue_end; queue_idx++) {
2508                 if (0x1 & q_msk)
2509                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2510                 q_msk = q_msk >> 1;
2511         }
2512
2513         return 0;
2514 }
2515
2516 static int
2517 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2518 {
2519         struct ixgbe_adapter *adapter = dev->data->dev_private;
2520         int err;
2521         uint32_t mflcn;
2522
2523         ixgbe_setup_fc(hw);
2524
2525         err = ixgbe_fc_enable(hw);
2526
2527         /* Not negotiated is not an error case */
2528         if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2529                 /*
2530                  *check if we want to forward MAC frames - driver doesn't
2531                  *have native capability to do that,
2532                  *so we'll write the registers ourselves
2533                  */
2534
2535                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2536
2537                 /* set or clear MFLCN.PMCF bit depending on configuration */
2538                 if (adapter->mac_ctrl_frame_fwd != 0)
2539                         mflcn |= IXGBE_MFLCN_PMCF;
2540                 else
2541                         mflcn &= ~IXGBE_MFLCN_PMCF;
2542
2543                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2544                 IXGBE_WRITE_FLUSH(hw);
2545
2546                 return 0;
2547         }
2548         return err;
2549 }
2550
2551 /*
2552  * Configure device link speed and setup link.
2553  * It returns 0 on success.
2554  */
2555 static int
2556 ixgbe_dev_start(struct rte_eth_dev *dev)
2557 {
2558         struct ixgbe_hw *hw =
2559                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2560         struct ixgbe_vf_info *vfinfo =
2561                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2562         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2563         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2564         uint32_t intr_vector = 0;
2565         int err;
2566         bool link_up = false, negotiate = 0;
2567         uint32_t speed = 0;
2568         uint32_t allowed_speeds = 0;
2569         int mask = 0;
2570         int status;
2571         uint16_t vf, idx;
2572         uint32_t *link_speeds;
2573         struct ixgbe_tm_conf *tm_conf =
2574                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2575         struct ixgbe_macsec_setting *macsec_setting =
2576                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2577
2578         PMD_INIT_FUNC_TRACE();
2579
2580         /* Stop the link setup handler before resetting the HW. */
2581         ixgbe_dev_wait_setup_link_complete(dev, 0);
2582
2583         /* disable uio/vfio intr/eventfd mapping */
2584         rte_intr_disable(intr_handle);
2585
2586         /* stop adapter */
2587         hw->adapter_stopped = 0;
2588         ixgbe_stop_adapter(hw);
2589
2590         /* reinitialize adapter
2591          * this calls reset and start
2592          */
2593         status = ixgbe_pf_reset_hw(hw);
2594         if (status != 0)
2595                 return -1;
2596         hw->mac.ops.start_hw(hw);
2597         hw->mac.get_link_status = true;
2598
2599         /* configure PF module if SRIOV enabled */
2600         ixgbe_pf_host_configure(dev);
2601
2602         ixgbe_dev_phy_intr_setup(dev);
2603
2604         /* check and configure queue intr-vector mapping */
2605         if ((rte_intr_cap_multiple(intr_handle) ||
2606              !RTE_ETH_DEV_SRIOV(dev).active) &&
2607             dev->data->dev_conf.intr_conf.rxq != 0) {
2608                 intr_vector = dev->data->nb_rx_queues;
2609                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2610                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2611                                         IXGBE_MAX_INTR_QUEUE_NUM);
2612                         return -ENOTSUP;
2613                 }
2614                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2615                         return -1;
2616         }
2617
2618         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2619                 intr_handle->intr_vec =
2620                         rte_zmalloc("intr_vec",
2621                                     dev->data->nb_rx_queues * sizeof(int), 0);
2622                 if (intr_handle->intr_vec == NULL) {
2623                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2624                                      " intr_vec", dev->data->nb_rx_queues);
2625                         return -ENOMEM;
2626                 }
2627         }
2628
2629         /* confiugre msix for sleep until rx interrupt */
2630         ixgbe_configure_msix(dev);
2631
2632         /* initialize transmission unit */
2633         ixgbe_dev_tx_init(dev);
2634
2635         /* This can fail when allocating mbufs for descriptor rings */
2636         err = ixgbe_dev_rx_init(dev);
2637         if (err) {
2638                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2639                 goto error;
2640         }
2641
2642         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2643                 ETH_VLAN_EXTEND_MASK;
2644         err = ixgbe_vlan_offload_config(dev, mask);
2645         if (err) {
2646                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2647                 goto error;
2648         }
2649
2650         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2651                 /* Enable vlan filtering for VMDq */
2652                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2653         }
2654
2655         /* Configure DCB hw */
2656         ixgbe_configure_dcb(dev);
2657
2658         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2659                 err = ixgbe_fdir_configure(dev);
2660                 if (err)
2661                         goto error;
2662         }
2663
2664         /* Restore vf rate limit */
2665         if (vfinfo != NULL) {
2666                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2667                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2668                                 if (vfinfo[vf].tx_rate[idx] != 0)
2669                                         ixgbe_set_vf_rate_limit(
2670                                                 dev, vf,
2671                                                 vfinfo[vf].tx_rate[idx],
2672                                                 1 << idx);
2673         }
2674
2675         ixgbe_restore_statistics_mapping(dev);
2676
2677         err = ixgbe_flow_ctrl_enable(dev, hw);
2678         if (err < 0) {
2679                 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2680                 goto error;
2681         }
2682
2683         err = ixgbe_dev_rxtx_start(dev);
2684         if (err < 0) {
2685                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2686                 goto error;
2687         }
2688
2689         /* Skip link setup if loopback mode is enabled. */
2690         if (dev->data->dev_conf.lpbk_mode != 0) {
2691                 err = ixgbe_check_supported_loopback_mode(dev);
2692                 if (err < 0) {
2693                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2694                         goto error;
2695                 } else {
2696                         goto skip_link_setup;
2697                 }
2698         }
2699
2700         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2701                 err = hw->mac.ops.setup_sfp(hw);
2702                 if (err)
2703                         goto error;
2704         }
2705
2706         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2707                 /* Turn on the copper */
2708                 ixgbe_set_phy_power(hw, true);
2709         } else {
2710                 /* Turn on the laser */
2711                 ixgbe_enable_tx_laser(hw);
2712         }
2713
2714         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2715         if (err)
2716                 goto error;
2717         dev->data->dev_link.link_status = link_up;
2718
2719         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2720         if (err)
2721                 goto error;
2722
2723         switch (hw->mac.type) {
2724         case ixgbe_mac_X550:
2725         case ixgbe_mac_X550EM_x:
2726         case ixgbe_mac_X550EM_a:
2727                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2728                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2729                         ETH_LINK_SPEED_10G;
2730                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2731                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2732                         allowed_speeds = ETH_LINK_SPEED_10M |
2733                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2734                 break;
2735         default:
2736                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2737                         ETH_LINK_SPEED_10G;
2738         }
2739
2740         link_speeds = &dev->data->dev_conf.link_speeds;
2741
2742         /* Ignore autoneg flag bit and check the validity of
2743          * link_speed
2744          */
2745         if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2746                 PMD_INIT_LOG(ERR, "Invalid link setting");
2747                 goto error;
2748         }
2749
2750         speed = 0x0;
2751         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2752                 switch (hw->mac.type) {
2753                 case ixgbe_mac_82598EB:
2754                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2755                         break;
2756                 case ixgbe_mac_82599EB:
2757                 case ixgbe_mac_X540:
2758                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2759                         break;
2760                 case ixgbe_mac_X550:
2761                 case ixgbe_mac_X550EM_x:
2762                 case ixgbe_mac_X550EM_a:
2763                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2764                         break;
2765                 default:
2766                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2767                 }
2768         } else {
2769                 if (*link_speeds & ETH_LINK_SPEED_10G)
2770                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2771                 if (*link_speeds & ETH_LINK_SPEED_5G)
2772                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2773                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2774                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2775                 if (*link_speeds & ETH_LINK_SPEED_1G)
2776                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2777                 if (*link_speeds & ETH_LINK_SPEED_100M)
2778                         speed |= IXGBE_LINK_SPEED_100_FULL;
2779                 if (*link_speeds & ETH_LINK_SPEED_10M)
2780                         speed |= IXGBE_LINK_SPEED_10_FULL;
2781         }
2782
2783         err = ixgbe_setup_link(hw, speed, link_up);
2784         if (err)
2785                 goto error;
2786
2787 skip_link_setup:
2788
2789         if (rte_intr_allow_others(intr_handle)) {
2790                 /* check if lsc interrupt is enabled */
2791                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2792                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2793                 else
2794                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2795                 ixgbe_dev_macsec_interrupt_setup(dev);
2796         } else {
2797                 rte_intr_callback_unregister(intr_handle,
2798                                              ixgbe_dev_interrupt_handler, dev);
2799                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2800                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2801                                      " no intr multiplex");
2802         }
2803
2804         /* check if rxq interrupt is enabled */
2805         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2806             rte_intr_dp_is_en(intr_handle))
2807                 ixgbe_dev_rxq_interrupt_setup(dev);
2808
2809         /* enable uio/vfio intr/eventfd mapping */
2810         rte_intr_enable(intr_handle);
2811
2812         /* resume enabled intr since hw reset */
2813         ixgbe_enable_intr(dev);
2814         ixgbe_l2_tunnel_conf(dev);
2815         ixgbe_filter_restore(dev);
2816
2817         if (tm_conf->root && !tm_conf->committed)
2818                 PMD_DRV_LOG(WARNING,
2819                             "please call hierarchy_commit() "
2820                             "before starting the port");
2821
2822         /* wait for the controller to acquire link */
2823         err = ixgbe_wait_for_link_up(hw);
2824         if (err)
2825                 goto error;
2826
2827         /*
2828          * Update link status right before return, because it may
2829          * start link configuration process in a separate thread.
2830          */
2831         ixgbe_dev_link_update(dev, 0);
2832
2833         /* setup the macsec setting register */
2834         if (macsec_setting->offload_en)
2835                 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2836
2837         return 0;
2838
2839 error:
2840         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2841         ixgbe_dev_clear_queues(dev);
2842         return -EIO;
2843 }
2844
2845 /*
2846  * Stop device: disable rx and tx functions to allow for reconfiguring.
2847  */
2848 static void
2849 ixgbe_dev_stop(struct rte_eth_dev *dev)
2850 {
2851         struct rte_eth_link link;
2852         struct ixgbe_adapter *adapter = dev->data->dev_private;
2853         struct ixgbe_hw *hw =
2854                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2855         struct ixgbe_vf_info *vfinfo =
2856                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2857         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2858         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2859         int vf;
2860         struct ixgbe_tm_conf *tm_conf =
2861                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2862
2863         if (hw->adapter_stopped)
2864                 return;
2865
2866         PMD_INIT_FUNC_TRACE();
2867
2868         ixgbe_dev_wait_setup_link_complete(dev, 0);
2869
2870         /* disable interrupts */
2871         ixgbe_disable_intr(hw);
2872
2873         /* reset the NIC */
2874         ixgbe_pf_reset_hw(hw);
2875         hw->adapter_stopped = 0;
2876
2877         /* stop adapter */
2878         ixgbe_stop_adapter(hw);
2879
2880         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2881                 vfinfo[vf].clear_to_send = false;
2882
2883         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2884                 /* Turn off the copper */
2885                 ixgbe_set_phy_power(hw, false);
2886         } else {
2887                 /* Turn off the laser */
2888                 ixgbe_disable_tx_laser(hw);
2889         }
2890
2891         ixgbe_dev_clear_queues(dev);
2892
2893         /* Clear stored conf */
2894         dev->data->scattered_rx = 0;
2895         dev->data->lro = 0;
2896
2897         /* Clear recorded link status */
2898         memset(&link, 0, sizeof(link));
2899         rte_eth_linkstatus_set(dev, &link);
2900
2901         if (!rte_intr_allow_others(intr_handle))
2902                 /* resume to the default handler */
2903                 rte_intr_callback_register(intr_handle,
2904                                            ixgbe_dev_interrupt_handler,
2905                                            (void *)dev);
2906
2907         /* Clean datapath event and queue/vec mapping */
2908         rte_intr_efd_disable(intr_handle);
2909         if (intr_handle->intr_vec != NULL) {
2910                 rte_free(intr_handle->intr_vec);
2911                 intr_handle->intr_vec = NULL;
2912         }
2913
2914         /* reset hierarchy commit */
2915         tm_conf->committed = false;
2916
2917         adapter->rss_reta_updated = 0;
2918
2919         hw->adapter_stopped = true;
2920         dev->data->dev_started = 0;
2921 }
2922
2923 /*
2924  * Set device link up: enable tx.
2925  */
2926 static int
2927 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2928 {
2929         struct ixgbe_hw *hw =
2930                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2931         if (hw->mac.type == ixgbe_mac_82599EB) {
2932 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2933                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2934                         /* Not suported in bypass mode */
2935                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2936                                      "by device id 0x%x", hw->device_id);
2937                         return -ENOTSUP;
2938                 }
2939 #endif
2940         }
2941
2942         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2943                 /* Turn on the copper */
2944                 ixgbe_set_phy_power(hw, true);
2945         } else {
2946                 /* Turn on the laser */
2947                 ixgbe_enable_tx_laser(hw);
2948                 ixgbe_dev_link_update(dev, 0);
2949         }
2950
2951         return 0;
2952 }
2953
2954 /*
2955  * Set device link down: disable tx.
2956  */
2957 static int
2958 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2959 {
2960         struct ixgbe_hw *hw =
2961                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2962         if (hw->mac.type == ixgbe_mac_82599EB) {
2963 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2964                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2965                         /* Not suported in bypass mode */
2966                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2967                                      "by device id 0x%x", hw->device_id);
2968                         return -ENOTSUP;
2969                 }
2970 #endif
2971         }
2972
2973         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2974                 /* Turn off the copper */
2975                 ixgbe_set_phy_power(hw, false);
2976         } else {
2977                 /* Turn off the laser */
2978                 ixgbe_disable_tx_laser(hw);
2979                 ixgbe_dev_link_update(dev, 0);
2980         }
2981
2982         return 0;
2983 }
2984
2985 /*
2986  * Reset and stop device.
2987  */
2988 static int
2989 ixgbe_dev_close(struct rte_eth_dev *dev)
2990 {
2991         struct ixgbe_hw *hw =
2992                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2993         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2994         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2995         int retries = 0;
2996         int ret;
2997
2998         PMD_INIT_FUNC_TRACE();
2999         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3000                 return 0;
3001
3002         ixgbe_pf_reset_hw(hw);
3003
3004         ixgbe_dev_stop(dev);
3005
3006         ixgbe_dev_free_queues(dev);
3007
3008         ixgbe_disable_pcie_master(hw);
3009
3010         /* reprogram the RAR[0] in case user changed it. */
3011         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3012
3013         dev->dev_ops = NULL;
3014         dev->rx_pkt_burst = NULL;
3015         dev->tx_pkt_burst = NULL;
3016
3017         /* Unlock any pending hardware semaphore */
3018         ixgbe_swfw_lock_reset(hw);
3019
3020         /* disable uio intr before callback unregister */
3021         rte_intr_disable(intr_handle);
3022
3023         do {
3024                 ret = rte_intr_callback_unregister(intr_handle,
3025                                 ixgbe_dev_interrupt_handler, dev);
3026                 if (ret >= 0 || ret == -ENOENT) {
3027                         break;
3028                 } else if (ret != -EAGAIN) {
3029                         PMD_INIT_LOG(ERR,
3030                                 "intr callback unregister failed: %d",
3031                                 ret);
3032                 }
3033                 rte_delay_ms(100);
3034         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3035
3036         /* cancel the delay handler before remove dev */
3037         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3038
3039         /* uninitialize PF if max_vfs not zero */
3040         ixgbe_pf_host_uninit(dev);
3041
3042         /* remove all the fdir filters & hash */
3043         ixgbe_fdir_filter_uninit(dev);
3044
3045         /* remove all the L2 tunnel filters & hash */
3046         ixgbe_l2_tn_filter_uninit(dev);
3047
3048         /* Remove all ntuple filters of the device */
3049         ixgbe_ntuple_filter_uninit(dev);
3050
3051         /* clear all the filters list */
3052         ixgbe_filterlist_flush();
3053
3054         /* Remove all Traffic Manager configuration */
3055         ixgbe_tm_conf_uninit(dev);
3056
3057 #ifdef RTE_LIBRTE_SECURITY
3058         rte_free(dev->security_ctx);
3059 #endif
3060
3061         return 0;
3062 }
3063
3064 /*
3065  * Reset PF device.
3066  */
3067 static int
3068 ixgbe_dev_reset(struct rte_eth_dev *dev)
3069 {
3070         int ret;
3071
3072         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3073          * its VF to make them align with it. The detailed notification
3074          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3075          * To avoid unexpected behavior in VF, currently reset of PF with
3076          * SR-IOV activation is not supported. It might be supported later.
3077          */
3078         if (dev->data->sriov.active)
3079                 return -ENOTSUP;
3080
3081         ret = eth_ixgbe_dev_uninit(dev);
3082         if (ret)
3083                 return ret;
3084
3085         ret = eth_ixgbe_dev_init(dev, NULL);
3086
3087         return ret;
3088 }
3089
3090 static void
3091 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3092                            struct ixgbe_hw_stats *hw_stats,
3093                            struct ixgbe_macsec_stats *macsec_stats,
3094                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3095                            uint64_t *total_qprc, uint64_t *total_qprdc)
3096 {
3097         uint32_t bprc, lxon, lxoff, total;
3098         uint32_t delta_gprc = 0;
3099         unsigned i;
3100         /* Workaround for RX byte count not including CRC bytes when CRC
3101          * strip is enabled. CRC bytes are removed from counters when crc_strip
3102          * is disabled.
3103          */
3104         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3105                         IXGBE_HLREG0_RXCRCSTRP);
3106
3107         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3108         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3109         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3110         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3111
3112         for (i = 0; i < 8; i++) {
3113                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3114
3115                 /* global total per queue */
3116                 hw_stats->mpc[i] += mp;
3117                 /* Running comprehensive total for stats display */
3118                 *total_missed_rx += hw_stats->mpc[i];
3119                 if (hw->mac.type == ixgbe_mac_82598EB) {
3120                         hw_stats->rnbc[i] +=
3121                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3122                         hw_stats->pxonrxc[i] +=
3123                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3124                         hw_stats->pxoffrxc[i] +=
3125                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3126                 } else {
3127                         hw_stats->pxonrxc[i] +=
3128                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3129                         hw_stats->pxoffrxc[i] +=
3130                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3131                         hw_stats->pxon2offc[i] +=
3132                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3133                 }
3134                 hw_stats->pxontxc[i] +=
3135                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3136                 hw_stats->pxofftxc[i] +=
3137                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3138         }
3139         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3140                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3141                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3142                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3143
3144                 delta_gprc += delta_qprc;
3145
3146                 hw_stats->qprc[i] += delta_qprc;
3147                 hw_stats->qptc[i] += delta_qptc;
3148
3149                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3150                 hw_stats->qbrc[i] +=
3151                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3152                 if (crc_strip == 0)
3153                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3154
3155                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3156                 hw_stats->qbtc[i] +=
3157                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3158
3159                 hw_stats->qprdc[i] += delta_qprdc;
3160                 *total_qprdc += hw_stats->qprdc[i];
3161
3162                 *total_qprc += hw_stats->qprc[i];
3163                 *total_qbrc += hw_stats->qbrc[i];
3164         }
3165         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3166         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3167         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3168
3169         /*
3170          * An errata states that gprc actually counts good + missed packets:
3171          * Workaround to set gprc to summated queue packet receives
3172          */
3173         hw_stats->gprc = *total_qprc;
3174
3175         if (hw->mac.type != ixgbe_mac_82598EB) {
3176                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3177                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3178                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3179                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3180                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3181                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3182                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3183                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3184         } else {
3185                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3186                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3187                 /* 82598 only has a counter in the high register */
3188                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3189                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3190                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3191         }
3192         uint64_t old_tpr = hw_stats->tpr;
3193
3194         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3195         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3196
3197         if (crc_strip == 0)
3198                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3199
3200         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3201         hw_stats->gptc += delta_gptc;
3202         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3203         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3204
3205         /*
3206          * Workaround: mprc hardware is incorrectly counting
3207          * broadcasts, so for now we subtract those.
3208          */
3209         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3210         hw_stats->bprc += bprc;
3211         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3212         if (hw->mac.type == ixgbe_mac_82598EB)
3213                 hw_stats->mprc -= bprc;
3214
3215         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3216         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3217         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3218         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3219         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3220         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3221
3222         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3223         hw_stats->lxontxc += lxon;
3224         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3225         hw_stats->lxofftxc += lxoff;
3226         total = lxon + lxoff;
3227
3228         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3229         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3230         hw_stats->gptc -= total;
3231         hw_stats->mptc -= total;
3232         hw_stats->ptc64 -= total;
3233         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3234
3235         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3236         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3237         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3238         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3239         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3240         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3241         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3242         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3243         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3244         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3245         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3246         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3247         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3248         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3249         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3250         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3251         /* Only read FCOE on 82599 */
3252         if (hw->mac.type != ixgbe_mac_82598EB) {
3253                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3254                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3255                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3256                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3257                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3258         }
3259
3260         /* Flow Director Stats registers */
3261         if (hw->mac.type != ixgbe_mac_82598EB) {
3262                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3263                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3264                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3265                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3266                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3267                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3268                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3269                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3270                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3271                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3272         }
3273         /* MACsec Stats registers */
3274         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3275         macsec_stats->out_pkts_encrypted +=
3276                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3277         macsec_stats->out_pkts_protected +=
3278                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3279         macsec_stats->out_octets_encrypted +=
3280                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3281         macsec_stats->out_octets_protected +=
3282                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3283         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3284         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3285         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3286         macsec_stats->in_pkts_unknownsci +=
3287                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3288         macsec_stats->in_octets_decrypted +=
3289                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3290         macsec_stats->in_octets_validated +=
3291                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3292         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3293         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3294         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3295         for (i = 0; i < 2; i++) {
3296                 macsec_stats->in_pkts_ok +=
3297                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3298                 macsec_stats->in_pkts_invalid +=
3299                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3300                 macsec_stats->in_pkts_notvalid +=
3301                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3302         }
3303         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3304         macsec_stats->in_pkts_notusingsa +=
3305                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3306 }
3307
3308 /*
3309  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3310  */
3311 static int
3312 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3313 {
3314         struct ixgbe_hw *hw =
3315                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3316         struct ixgbe_hw_stats *hw_stats =
3317                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3318         struct ixgbe_macsec_stats *macsec_stats =
3319                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3320                                 dev->data->dev_private);
3321         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3322         unsigned i;
3323
3324         total_missed_rx = 0;
3325         total_qbrc = 0;
3326         total_qprc = 0;
3327         total_qprdc = 0;
3328
3329         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3330                         &total_qbrc, &total_qprc, &total_qprdc);
3331
3332         if (stats == NULL)
3333                 return -EINVAL;
3334
3335         /* Fill out the rte_eth_stats statistics structure */
3336         stats->ipackets = total_qprc;
3337         stats->ibytes = total_qbrc;
3338         stats->opackets = hw_stats->gptc;
3339         stats->obytes = hw_stats->gotc;
3340
3341         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3342                 stats->q_ipackets[i] = hw_stats->qprc[i];
3343                 stats->q_opackets[i] = hw_stats->qptc[i];
3344                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3345                 stats->q_obytes[i] = hw_stats->qbtc[i];
3346                 stats->q_errors[i] = hw_stats->qprdc[i];
3347         }
3348
3349         /* Rx Errors */
3350         stats->imissed  = total_missed_rx;
3351         stats->ierrors  = hw_stats->crcerrs +
3352                           hw_stats->mspdc +
3353                           hw_stats->rlec +
3354                           hw_stats->ruc +
3355                           hw_stats->roc +
3356                           hw_stats->illerrc +
3357                           hw_stats->errbc +
3358                           hw_stats->rfc +
3359                           hw_stats->fccrc +
3360                           hw_stats->fclast;
3361
3362         /* Tx Errors */
3363         stats->oerrors  = 0;
3364         return 0;
3365 }
3366
3367 static int
3368 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3369 {
3370         struct ixgbe_hw_stats *stats =
3371                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3372
3373         /* HW registers are cleared on read */
3374         ixgbe_dev_stats_get(dev, NULL);
3375
3376         /* Reset software totals */
3377         memset(stats, 0, sizeof(*stats));
3378
3379         return 0;
3380 }
3381
3382 /* This function calculates the number of xstats based on the current config */
3383 static unsigned
3384 ixgbe_xstats_calc_num(void) {
3385         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3386                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3387                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3388 }
3389
3390 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3391         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3392 {
3393         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3394         unsigned stat, i, count;
3395
3396         if (xstats_names != NULL) {
3397                 count = 0;
3398
3399                 /* Note: limit >= cnt_stats checked upstream
3400                  * in rte_eth_xstats_names()
3401                  */
3402
3403                 /* Extended stats from ixgbe_hw_stats */
3404                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3405                         strlcpy(xstats_names[count].name,
3406                                 rte_ixgbe_stats_strings[i].name,
3407                                 sizeof(xstats_names[count].name));
3408                         count++;
3409                 }
3410
3411                 /* MACsec Stats */
3412                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3413                         strlcpy(xstats_names[count].name,
3414                                 rte_ixgbe_macsec_strings[i].name,
3415                                 sizeof(xstats_names[count].name));
3416                         count++;
3417                 }
3418
3419                 /* RX Priority Stats */
3420                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3421                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3422                                 snprintf(xstats_names[count].name,
3423                                         sizeof(xstats_names[count].name),
3424                                         "rx_priority%u_%s", i,
3425                                         rte_ixgbe_rxq_strings[stat].name);
3426                                 count++;
3427                         }
3428                 }
3429
3430                 /* TX Priority Stats */
3431                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3432                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3433                                 snprintf(xstats_names[count].name,
3434                                         sizeof(xstats_names[count].name),
3435                                         "tx_priority%u_%s", i,
3436                                         rte_ixgbe_txq_strings[stat].name);
3437                                 count++;
3438                         }
3439                 }
3440         }
3441         return cnt_stats;
3442 }
3443
3444 static int ixgbe_dev_xstats_get_names_by_id(
3445         struct rte_eth_dev *dev,
3446         struct rte_eth_xstat_name *xstats_names,
3447         const uint64_t *ids,
3448         unsigned int limit)
3449 {
3450         if (!ids) {
3451                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3452                 unsigned int stat, i, count;
3453
3454                 if (xstats_names != NULL) {
3455                         count = 0;
3456
3457                         /* Note: limit >= cnt_stats checked upstream
3458                          * in rte_eth_xstats_names()
3459                          */
3460
3461                         /* Extended stats from ixgbe_hw_stats */
3462                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3463                                 strlcpy(xstats_names[count].name,
3464                                         rte_ixgbe_stats_strings[i].name,
3465                                         sizeof(xstats_names[count].name));
3466                                 count++;
3467                         }
3468
3469                         /* MACsec Stats */
3470                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3471                                 strlcpy(xstats_names[count].name,
3472                                         rte_ixgbe_macsec_strings[i].name,
3473                                         sizeof(xstats_names[count].name));
3474                                 count++;
3475                         }
3476
3477                         /* RX Priority Stats */
3478                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3479                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3480                                         snprintf(xstats_names[count].name,
3481                                             sizeof(xstats_names[count].name),
3482                                             "rx_priority%u_%s", i,
3483                                             rte_ixgbe_rxq_strings[stat].name);
3484                                         count++;
3485                                 }
3486                         }
3487
3488                         /* TX Priority Stats */
3489                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3490                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3491                                         snprintf(xstats_names[count].name,
3492                                             sizeof(xstats_names[count].name),
3493                                             "tx_priority%u_%s", i,
3494                                             rte_ixgbe_txq_strings[stat].name);
3495                                         count++;
3496                                 }
3497                         }
3498                 }
3499                 return cnt_stats;
3500         }
3501
3502         uint16_t i;
3503         uint16_t size = ixgbe_xstats_calc_num();
3504         struct rte_eth_xstat_name xstats_names_copy[size];
3505
3506         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3507                         size);
3508
3509         for (i = 0; i < limit; i++) {
3510                 if (ids[i] >= size) {
3511                         PMD_INIT_LOG(ERR, "id value isn't valid");
3512                         return -1;
3513                 }
3514                 strcpy(xstats_names[i].name,
3515                                 xstats_names_copy[ids[i]].name);
3516         }
3517         return limit;
3518 }
3519
3520 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3521         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3522 {
3523         unsigned i;
3524
3525         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3526                 return -ENOMEM;
3527
3528         if (xstats_names != NULL)
3529                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3530                         strlcpy(xstats_names[i].name,
3531                                 rte_ixgbevf_stats_strings[i].name,
3532                                 sizeof(xstats_names[i].name));
3533         return IXGBEVF_NB_XSTATS;
3534 }
3535
3536 static int
3537 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3538                                          unsigned n)
3539 {
3540         struct ixgbe_hw *hw =
3541                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3542         struct ixgbe_hw_stats *hw_stats =
3543                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3544         struct ixgbe_macsec_stats *macsec_stats =
3545                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3546                                 dev->data->dev_private);
3547         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3548         unsigned i, stat, count = 0;
3549
3550         count = ixgbe_xstats_calc_num();
3551
3552         if (n < count)
3553                 return count;
3554
3555         total_missed_rx = 0;
3556         total_qbrc = 0;
3557         total_qprc = 0;
3558         total_qprdc = 0;
3559
3560         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3561                         &total_qbrc, &total_qprc, &total_qprdc);
3562
3563         /* If this is a reset xstats is NULL, and we have cleared the
3564          * registers by reading them.
3565          */
3566         if (!xstats)
3567                 return 0;
3568
3569         /* Extended stats from ixgbe_hw_stats */
3570         count = 0;
3571         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3572                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3573                                 rte_ixgbe_stats_strings[i].offset);
3574                 xstats[count].id = count;
3575                 count++;
3576         }
3577
3578         /* MACsec Stats */
3579         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3580                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3581                                 rte_ixgbe_macsec_strings[i].offset);
3582                 xstats[count].id = count;
3583                 count++;
3584         }
3585
3586         /* RX Priority Stats */
3587         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3588                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3589                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3590                                         rte_ixgbe_rxq_strings[stat].offset +
3591                                         (sizeof(uint64_t) * i));
3592                         xstats[count].id = count;
3593                         count++;
3594                 }
3595         }
3596
3597         /* TX Priority Stats */
3598         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3599                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3600                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3601                                         rte_ixgbe_txq_strings[stat].offset +
3602                                         (sizeof(uint64_t) * i));
3603                         xstats[count].id = count;
3604                         count++;
3605                 }
3606         }
3607         return count;
3608 }
3609
3610 static int
3611 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3612                 uint64_t *values, unsigned int n)
3613 {
3614         if (!ids) {
3615                 struct ixgbe_hw *hw =
3616                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3617                 struct ixgbe_hw_stats *hw_stats =
3618                                 IXGBE_DEV_PRIVATE_TO_STATS(
3619                                                 dev->data->dev_private);
3620                 struct ixgbe_macsec_stats *macsec_stats =
3621                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3622                                         dev->data->dev_private);
3623                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3624                 unsigned int i, stat, count = 0;
3625
3626                 count = ixgbe_xstats_calc_num();
3627
3628                 if (!ids && n < count)
3629                         return count;
3630
3631                 total_missed_rx = 0;
3632                 total_qbrc = 0;
3633                 total_qprc = 0;
3634                 total_qprdc = 0;
3635
3636                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3637                                 &total_missed_rx, &total_qbrc, &total_qprc,
3638                                 &total_qprdc);
3639
3640                 /* If this is a reset xstats is NULL, and we have cleared the
3641                  * registers by reading them.
3642                  */
3643                 if (!ids && !values)
3644                         return 0;
3645
3646                 /* Extended stats from ixgbe_hw_stats */
3647                 count = 0;
3648                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3649                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3650                                         rte_ixgbe_stats_strings[i].offset);
3651                         count++;
3652                 }
3653
3654                 /* MACsec Stats */
3655                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3656                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3657                                         rte_ixgbe_macsec_strings[i].offset);
3658                         count++;
3659                 }
3660
3661                 /* RX Priority Stats */
3662                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3663                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3664                                 values[count] =
3665                                         *(uint64_t *)(((char *)hw_stats) +
3666                                         rte_ixgbe_rxq_strings[stat].offset +
3667                                         (sizeof(uint64_t) * i));
3668                                 count++;
3669                         }
3670                 }
3671
3672                 /* TX Priority Stats */
3673                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3674                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3675                                 values[count] =
3676                                         *(uint64_t *)(((char *)hw_stats) +
3677                                         rte_ixgbe_txq_strings[stat].offset +
3678                                         (sizeof(uint64_t) * i));
3679                                 count++;
3680                         }
3681                 }
3682                 return count;
3683         }
3684
3685         uint16_t i;
3686         uint16_t size = ixgbe_xstats_calc_num();
3687         uint64_t values_copy[size];
3688
3689         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3690
3691         for (i = 0; i < n; i++) {
3692                 if (ids[i] >= size) {
3693                         PMD_INIT_LOG(ERR, "id value isn't valid");
3694                         return -1;
3695                 }
3696                 values[i] = values_copy[ids[i]];
3697         }
3698         return n;
3699 }
3700
3701 static int
3702 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3703 {
3704         struct ixgbe_hw_stats *stats =
3705                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3706         struct ixgbe_macsec_stats *macsec_stats =
3707                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3708                                 dev->data->dev_private);
3709
3710         unsigned count = ixgbe_xstats_calc_num();
3711
3712         /* HW registers are cleared on read */
3713         ixgbe_dev_xstats_get(dev, NULL, count);
3714
3715         /* Reset software totals */
3716         memset(stats, 0, sizeof(*stats));
3717         memset(macsec_stats, 0, sizeof(*macsec_stats));
3718
3719         return 0;
3720 }
3721
3722 static void
3723 ixgbevf_update_stats(struct rte_eth_dev *dev)
3724 {
3725         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3726         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3727                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3728
3729         /* Good Rx packet, include VF loopback */
3730         UPDATE_VF_STAT(IXGBE_VFGPRC,
3731             hw_stats->last_vfgprc, hw_stats->vfgprc);
3732
3733         /* Good Rx octets, include VF loopback */
3734         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3735             hw_stats->last_vfgorc, hw_stats->vfgorc);
3736
3737         /* Good Tx packet, include VF loopback */
3738         UPDATE_VF_STAT(IXGBE_VFGPTC,
3739             hw_stats->last_vfgptc, hw_stats->vfgptc);
3740
3741         /* Good Tx octets, include VF loopback */
3742         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3743             hw_stats->last_vfgotc, hw_stats->vfgotc);
3744
3745         /* Rx Multicst Packet */
3746         UPDATE_VF_STAT(IXGBE_VFMPRC,
3747             hw_stats->last_vfmprc, hw_stats->vfmprc);
3748 }
3749
3750 static int
3751 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3752                        unsigned n)
3753 {
3754         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3755                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3756         unsigned i;
3757
3758         if (n < IXGBEVF_NB_XSTATS)
3759                 return IXGBEVF_NB_XSTATS;
3760
3761         ixgbevf_update_stats(dev);
3762
3763         if (!xstats)
3764                 return 0;
3765
3766         /* Extended stats */
3767         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3768                 xstats[i].id = i;
3769                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3770                         rte_ixgbevf_stats_strings[i].offset);
3771         }
3772
3773         return IXGBEVF_NB_XSTATS;
3774 }
3775
3776 static int
3777 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3778 {
3779         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3780                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3781
3782         ixgbevf_update_stats(dev);
3783
3784         if (stats == NULL)
3785                 return -EINVAL;
3786
3787         stats->ipackets = hw_stats->vfgprc;
3788         stats->ibytes = hw_stats->vfgorc;
3789         stats->opackets = hw_stats->vfgptc;
3790         stats->obytes = hw_stats->vfgotc;
3791         return 0;
3792 }
3793
3794 static int
3795 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3796 {
3797         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3798                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3799
3800         /* Sync HW register to the last stats */
3801         ixgbevf_dev_stats_get(dev, NULL);
3802
3803         /* reset HW current stats*/
3804         hw_stats->vfgprc = 0;
3805         hw_stats->vfgorc = 0;
3806         hw_stats->vfgptc = 0;
3807         hw_stats->vfgotc = 0;
3808
3809         return 0;
3810 }
3811
3812 static int
3813 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3814 {
3815         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3816         u16 eeprom_verh, eeprom_verl;
3817         u32 etrack_id;
3818         int ret;
3819
3820         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3821         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3822
3823         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3824         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3825
3826         ret += 1; /* add the size of '\0' */
3827         if (fw_size < (u32)ret)
3828                 return ret;
3829         else
3830                 return 0;
3831 }
3832
3833 static int
3834 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3835 {
3836         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3837         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3838         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3839
3840         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3841         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3842         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3843                 /*
3844                  * When DCB/VT is off, maximum number of queues changes,
3845                  * except for 82598EB, which remains constant.
3846                  */
3847                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3848                                 hw->mac.type != ixgbe_mac_82598EB)
3849                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3850         }
3851         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3852         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3853         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3854         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3855         dev_info->max_vfs = pci_dev->max_vfs;
3856         if (hw->mac.type == ixgbe_mac_82598EB)
3857                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3858         else
3859                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3860         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3861         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3862         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3863         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3864         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3865                                      dev_info->rx_queue_offload_capa);
3866         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3867         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3868
3869         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3870                 .rx_thresh = {
3871                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3872                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3873                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3874                 },
3875                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3876                 .rx_drop_en = 0,
3877                 .offloads = 0,
3878         };
3879
3880         dev_info->default_txconf = (struct rte_eth_txconf) {
3881                 .tx_thresh = {
3882                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3883                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3884                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3885                 },
3886                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3887                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3888                 .offloads = 0,
3889         };
3890
3891         dev_info->rx_desc_lim = rx_desc_lim;
3892         dev_info->tx_desc_lim = tx_desc_lim;
3893
3894         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3895         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3896         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3897
3898         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3899         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3900                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3901                 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3902                         ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3903
3904         if (hw->mac.type == ixgbe_mac_X540 ||
3905             hw->mac.type == ixgbe_mac_X540_vf ||
3906             hw->mac.type == ixgbe_mac_X550 ||
3907             hw->mac.type == ixgbe_mac_X550_vf) {
3908                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3909         }
3910         if (hw->mac.type == ixgbe_mac_X550) {
3911                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3912                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3913         }
3914
3915         /* Driver-preferred Rx/Tx parameters */
3916         dev_info->default_rxportconf.burst_size = 32;
3917         dev_info->default_txportconf.burst_size = 32;
3918         dev_info->default_rxportconf.nb_queues = 1;
3919         dev_info->default_txportconf.nb_queues = 1;
3920         dev_info->default_rxportconf.ring_size = 256;
3921         dev_info->default_txportconf.ring_size = 256;
3922
3923         return 0;
3924 }
3925
3926 static const uint32_t *
3927 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3928 {
3929         static const uint32_t ptypes[] = {
3930                 /* For non-vec functions,
3931                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3932                  * for vec functions,
3933                  * refers to _recv_raw_pkts_vec().
3934                  */
3935                 RTE_PTYPE_L2_ETHER,
3936                 RTE_PTYPE_L3_IPV4,
3937                 RTE_PTYPE_L3_IPV4_EXT,
3938                 RTE_PTYPE_L3_IPV6,
3939                 RTE_PTYPE_L3_IPV6_EXT,
3940                 RTE_PTYPE_L4_SCTP,
3941                 RTE_PTYPE_L4_TCP,
3942                 RTE_PTYPE_L4_UDP,
3943                 RTE_PTYPE_TUNNEL_IP,
3944                 RTE_PTYPE_INNER_L3_IPV6,
3945                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3946                 RTE_PTYPE_INNER_L4_TCP,
3947                 RTE_PTYPE_INNER_L4_UDP,
3948                 RTE_PTYPE_UNKNOWN
3949         };
3950
3951         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3952             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3953             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3954             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3955                 return ptypes;
3956
3957 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON)
3958         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3959             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3960                 return ptypes;
3961 #endif
3962         return NULL;
3963 }
3964
3965 static int
3966 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3967                      struct rte_eth_dev_info *dev_info)
3968 {
3969         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3970         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3971
3972         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3973         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3974         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3975         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3976         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3977         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3978         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3979         dev_info->max_vfs = pci_dev->max_vfs;
3980         if (hw->mac.type == ixgbe_mac_82598EB)
3981                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3982         else
3983                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3984         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3985         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3986                                      dev_info->rx_queue_offload_capa);
3987         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3988         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3989         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3990         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3991         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3992
3993         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3994                 .rx_thresh = {
3995                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3996                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3997                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3998                 },
3999                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
4000                 .rx_drop_en = 0,
4001                 .offloads = 0,
4002         };
4003
4004         dev_info->default_txconf = (struct rte_eth_txconf) {
4005                 .tx_thresh = {
4006                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
4007                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
4008                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
4009                 },
4010                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
4011                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
4012                 .offloads = 0,
4013         };
4014
4015         dev_info->rx_desc_lim = rx_desc_lim;
4016         dev_info->tx_desc_lim = tx_desc_lim;
4017
4018         return 0;
4019 }
4020
4021 static int
4022 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4023                    bool *link_up, int wait_to_complete)
4024 {
4025         struct ixgbe_adapter *adapter = container_of(hw,
4026                                                      struct ixgbe_adapter, hw);
4027         struct ixgbe_mbx_info *mbx = &hw->mbx;
4028         struct ixgbe_mac_info *mac = &hw->mac;
4029         uint32_t links_reg, in_msg;
4030         int ret_val = 0;
4031
4032         /* If we were hit with a reset drop the link */
4033         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4034                 mac->get_link_status = true;
4035
4036         if (!mac->get_link_status)
4037                 goto out;
4038
4039         /* if link status is down no point in checking to see if pf is up */
4040         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4041         if (!(links_reg & IXGBE_LINKS_UP))
4042                 goto out;
4043
4044         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4045          * before the link status is correct
4046          */
4047         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4048                 int i;
4049
4050                 for (i = 0; i < 5; i++) {
4051                         rte_delay_us(100);
4052                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4053
4054                         if (!(links_reg & IXGBE_LINKS_UP))
4055                                 goto out;
4056                 }
4057         }
4058
4059         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4060         case IXGBE_LINKS_SPEED_10G_82599:
4061                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4062                 if (hw->mac.type >= ixgbe_mac_X550) {
4063                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4064                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4065                 }
4066                 break;
4067         case IXGBE_LINKS_SPEED_1G_82599:
4068                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4069                 break;
4070         case IXGBE_LINKS_SPEED_100_82599:
4071                 *speed = IXGBE_LINK_SPEED_100_FULL;
4072                 if (hw->mac.type == ixgbe_mac_X550) {
4073                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4074                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4075                 }
4076                 break;
4077         case IXGBE_LINKS_SPEED_10_X550EM_A:
4078                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4079                 /* Since Reserved in older MAC's */
4080                 if (hw->mac.type >= ixgbe_mac_X550)
4081                         *speed = IXGBE_LINK_SPEED_10_FULL;
4082                 break;
4083         default:
4084                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4085         }
4086
4087         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4088                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4089                         mac->get_link_status = true;
4090                 else
4091                         mac->get_link_status = false;
4092
4093                 goto out;
4094         }
4095
4096         /* if the read failed it could just be a mailbox collision, best wait
4097          * until we are called again and don't report an error
4098          */
4099         if (mbx->ops.read(hw, &in_msg, 1, 0))
4100                 goto out;
4101
4102         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4103                 /* msg is not CTS and is NACK we must have lost CTS status */
4104                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4105                         mac->get_link_status = false;
4106                 goto out;
4107         }
4108
4109         /* the pf is talking, if we timed out in the past we reinit */
4110         if (!mbx->timeout) {
4111                 ret_val = -1;
4112                 goto out;
4113         }
4114
4115         /* if we passed all the tests above then the link is up and we no
4116          * longer need to check for link
4117          */
4118         mac->get_link_status = false;
4119
4120 out:
4121         *link_up = !mac->get_link_status;
4122         return ret_val;
4123 }
4124
4125 /*
4126  * If @timeout_ms was 0, it means that it will not return until link complete.
4127  * It returns 1 on complete, return 0 on timeout.
4128  */
4129 static int
4130 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4131 {
4132 #define WARNING_TIMEOUT    9000 /* 9s  in total */
4133         struct ixgbe_adapter *ad = dev->data->dev_private;
4134         uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4135
4136         while (rte_atomic32_read(&ad->link_thread_running)) {
4137                 msec_delay(1);
4138                 timeout--;
4139
4140                 if (timeout_ms) {
4141                         if (!timeout)
4142                                 return 0;
4143                 } else if (!timeout) {
4144                         /* It will not return until link complete */
4145                         timeout = WARNING_TIMEOUT;
4146                         PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4147                 }
4148         }
4149
4150         return 1;
4151 }
4152
4153 static void *
4154 ixgbe_dev_setup_link_thread_handler(void *param)
4155 {
4156         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4157         struct ixgbe_adapter *ad = dev->data->dev_private;
4158         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4159         struct ixgbe_interrupt *intr =
4160                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4161         u32 speed;
4162         bool autoneg = false;
4163
4164         pthread_detach(pthread_self());
4165         speed = hw->phy.autoneg_advertised;
4166         if (!speed)
4167                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4168
4169         ixgbe_setup_link(hw, speed, true);
4170
4171         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4172         rte_atomic32_clear(&ad->link_thread_running);
4173         return NULL;
4174 }
4175
4176 /*
4177  * In freebsd environment, nic_uio drivers do not support interrupts,
4178  * rte_intr_callback_register() will fail to register interrupts.
4179  * We can not make link status to change from down to up by interrupt
4180  * callback. So we need to wait for the controller to acquire link
4181  * when ports start.
4182  * It returns 0 on link up.
4183  */
4184 static int
4185 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4186 {
4187 #ifdef RTE_EXEC_ENV_FREEBSD
4188         int err, i;
4189         bool link_up = false;
4190         uint32_t speed = 0;
4191         const int nb_iter = 25;
4192
4193         for (i = 0; i < nb_iter; i++) {
4194                 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4195                 if (err)
4196                         return err;
4197                 if (link_up)
4198                         return 0;
4199                 msec_delay(200);
4200         }
4201
4202         return 0;
4203 #else
4204         RTE_SET_USED(hw);
4205         return 0;
4206 #endif
4207 }
4208
4209 /* return 0 means link status changed, -1 means not changed */
4210 int
4211 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4212                             int wait_to_complete, int vf)
4213 {
4214         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4215         struct ixgbe_adapter *ad = dev->data->dev_private;
4216         struct rte_eth_link link;
4217         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4218         struct ixgbe_interrupt *intr =
4219                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4220         bool link_up;
4221         int diag;
4222         int wait = 1;
4223         u32 esdp_reg;
4224
4225         memset(&link, 0, sizeof(link));
4226         link.link_status = ETH_LINK_DOWN;
4227         link.link_speed = ETH_SPEED_NUM_NONE;
4228         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4229         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4230                         ETH_LINK_SPEED_FIXED);
4231
4232         hw->mac.get_link_status = true;
4233
4234         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4235                 return rte_eth_linkstatus_set(dev, &link);
4236
4237         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4238         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4239                 wait = 0;
4240
4241 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4242 #ifdef RTE_EXEC_ENV_FREEBSD
4243         wait = 1;
4244 #endif
4245
4246         if (vf)
4247                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4248         else
4249                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4250
4251         if (diag != 0) {
4252                 link.link_speed = ETH_SPEED_NUM_100M;
4253                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4254                 return rte_eth_linkstatus_set(dev, &link);
4255         }
4256
4257         if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4258                 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4259                 if ((esdp_reg & IXGBE_ESDP_SDP3))
4260                         link_up = 0;
4261         }
4262
4263         if (link_up == 0) {
4264                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4265                         ixgbe_dev_wait_setup_link_complete(dev, 0);
4266                         if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4267                                 /* To avoid race condition between threads, set
4268                                  * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4269                                  * when there is no link thread running.
4270                                  */
4271                                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4272                                 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4273                                         "ixgbe-link-handler",
4274                                         NULL,
4275                                         ixgbe_dev_setup_link_thread_handler,
4276                                         dev) < 0) {
4277                                         PMD_DRV_LOG(ERR,
4278                                                 "Create link thread failed!");
4279                                         rte_atomic32_clear(&ad->link_thread_running);
4280                                 }
4281                         } else {
4282                                 PMD_DRV_LOG(ERR,
4283                                         "Other link thread is running now!");
4284                         }
4285                 }
4286                 return rte_eth_linkstatus_set(dev, &link);
4287         }
4288
4289         link.link_status = ETH_LINK_UP;
4290         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4291
4292         switch (link_speed) {
4293         default:
4294         case IXGBE_LINK_SPEED_UNKNOWN:
4295                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
4296                 break;
4297
4298         case IXGBE_LINK_SPEED_10_FULL:
4299                 link.link_speed = ETH_SPEED_NUM_10M;
4300                 break;
4301
4302         case IXGBE_LINK_SPEED_100_FULL:
4303                 link.link_speed = ETH_SPEED_NUM_100M;
4304                 break;
4305
4306         case IXGBE_LINK_SPEED_1GB_FULL:
4307                 link.link_speed = ETH_SPEED_NUM_1G;
4308                 break;
4309
4310         case IXGBE_LINK_SPEED_2_5GB_FULL:
4311                 link.link_speed = ETH_SPEED_NUM_2_5G;
4312                 break;
4313
4314         case IXGBE_LINK_SPEED_5GB_FULL:
4315                 link.link_speed = ETH_SPEED_NUM_5G;
4316                 break;
4317
4318         case IXGBE_LINK_SPEED_10GB_FULL:
4319                 link.link_speed = ETH_SPEED_NUM_10G;
4320                 break;
4321         }
4322
4323         return rte_eth_linkstatus_set(dev, &link);
4324 }
4325
4326 static int
4327 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4328 {
4329         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4330 }
4331
4332 static int
4333 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4334 {
4335         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4336 }
4337
4338 static int
4339 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4340 {
4341         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4342         uint32_t fctrl;
4343
4344         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4345         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4346         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4347
4348         return 0;
4349 }
4350
4351 static int
4352 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4353 {
4354         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4355         uint32_t fctrl;
4356
4357         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4358         fctrl &= (~IXGBE_FCTRL_UPE);
4359         if (dev->data->all_multicast == 1)
4360                 fctrl |= IXGBE_FCTRL_MPE;
4361         else
4362                 fctrl &= (~IXGBE_FCTRL_MPE);
4363         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4364
4365         return 0;
4366 }
4367
4368 static int
4369 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4370 {
4371         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4372         uint32_t fctrl;
4373
4374         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4375         fctrl |= IXGBE_FCTRL_MPE;
4376         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4377
4378         return 0;
4379 }
4380
4381 static int
4382 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4383 {
4384         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4385         uint32_t fctrl;
4386
4387         if (dev->data->promiscuous == 1)
4388                 return 0; /* must remain in all_multicast mode */
4389
4390         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4391         fctrl &= (~IXGBE_FCTRL_MPE);
4392         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4393
4394         return 0;
4395 }
4396
4397 /**
4398  * It clears the interrupt causes and enables the interrupt.
4399  * It will be called once only during nic initialized.
4400  *
4401  * @param dev
4402  *  Pointer to struct rte_eth_dev.
4403  * @param on
4404  *  Enable or Disable.
4405  *
4406  * @return
4407  *  - On success, zero.
4408  *  - On failure, a negative value.
4409  */
4410 static int
4411 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4412 {
4413         struct ixgbe_interrupt *intr =
4414                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4415
4416         ixgbe_dev_link_status_print(dev);
4417         if (on)
4418                 intr->mask |= IXGBE_EICR_LSC;
4419         else
4420                 intr->mask &= ~IXGBE_EICR_LSC;
4421
4422         return 0;
4423 }
4424
4425 /**
4426  * It clears the interrupt causes and enables the interrupt.
4427  * It will be called once only during nic initialized.
4428  *
4429  * @param dev
4430  *  Pointer to struct rte_eth_dev.
4431  *
4432  * @return
4433  *  - On success, zero.
4434  *  - On failure, a negative value.
4435  */
4436 static int
4437 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4438 {
4439         struct ixgbe_interrupt *intr =
4440                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4441
4442         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4443
4444         return 0;
4445 }
4446
4447 /**
4448  * It clears the interrupt causes and enables the interrupt.
4449  * It will be called once only during nic initialized.
4450  *
4451  * @param dev
4452  *  Pointer to struct rte_eth_dev.
4453  *
4454  * @return
4455  *  - On success, zero.
4456  *  - On failure, a negative value.
4457  */
4458 static int
4459 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4460 {
4461         struct ixgbe_interrupt *intr =
4462                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4463
4464         intr->mask |= IXGBE_EICR_LINKSEC;
4465
4466         return 0;
4467 }
4468
4469 /*
4470  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4471  *
4472  * @param dev
4473  *  Pointer to struct rte_eth_dev.
4474  *
4475  * @return
4476  *  - On success, zero.
4477  *  - On failure, a negative value.
4478  */
4479 static int
4480 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4481 {
4482         uint32_t eicr;
4483         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4484         struct ixgbe_interrupt *intr =
4485                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4486
4487         /* clear all cause mask */
4488         ixgbe_disable_intr(hw);
4489
4490         /* read-on-clear nic registers here */
4491         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4492         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4493
4494         intr->flags = 0;
4495
4496         /* set flag for async link update */
4497         if (eicr & IXGBE_EICR_LSC)
4498                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4499
4500         if (eicr & IXGBE_EICR_MAILBOX)
4501                 intr->flags |= IXGBE_FLAG_MAILBOX;
4502
4503         if (eicr & IXGBE_EICR_LINKSEC)
4504                 intr->flags |= IXGBE_FLAG_MACSEC;
4505
4506         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4507             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4508             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4509                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4510
4511         return 0;
4512 }
4513
4514 /**
4515  * It gets and then prints the link status.
4516  *
4517  * @param dev
4518  *  Pointer to struct rte_eth_dev.
4519  *
4520  * @return
4521  *  - On success, zero.
4522  *  - On failure, a negative value.
4523  */
4524 static void
4525 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4526 {
4527         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4528         struct rte_eth_link link;
4529
4530         rte_eth_linkstatus_get(dev, &link);
4531
4532         if (link.link_status) {
4533                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4534                                         (int)(dev->data->port_id),
4535                                         (unsigned)link.link_speed,
4536                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4537                                         "full-duplex" : "half-duplex");
4538         } else {
4539                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4540                                 (int)(dev->data->port_id));
4541         }
4542         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4543                                 pci_dev->addr.domain,
4544                                 pci_dev->addr.bus,
4545                                 pci_dev->addr.devid,
4546                                 pci_dev->addr.function);
4547 }
4548
4549 /*
4550  * It executes link_update after knowing an interrupt occurred.
4551  *
4552  * @param dev
4553  *  Pointer to struct rte_eth_dev.
4554  *
4555  * @return
4556  *  - On success, zero.
4557  *  - On failure, a negative value.
4558  */
4559 static int
4560 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4561 {
4562         struct ixgbe_interrupt *intr =
4563                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4564         int64_t timeout;
4565         struct ixgbe_hw *hw =
4566                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4567
4568         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4569
4570         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4571                 ixgbe_pf_mbx_process(dev);
4572                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4573         }
4574
4575         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4576                 ixgbe_handle_lasi(hw);
4577                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4578         }
4579
4580         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4581                 struct rte_eth_link link;
4582
4583                 /* get the link status before link update, for predicting later */
4584                 rte_eth_linkstatus_get(dev, &link);
4585
4586                 ixgbe_dev_link_update(dev, 0);
4587
4588                 /* likely to up */
4589                 if (!link.link_status)
4590                         /* handle it 1 sec later, wait it being stable */
4591                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4592                 /* likely to down */
4593                 else
4594                         /* handle it 4 sec later, wait it being stable */
4595                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4596
4597                 ixgbe_dev_link_status_print(dev);
4598                 if (rte_eal_alarm_set(timeout * 1000,
4599                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4600                         PMD_DRV_LOG(ERR, "Error setting alarm");
4601                 else {
4602                         /* remember original mask */
4603                         intr->mask_original = intr->mask;
4604                         /* only disable lsc interrupt */
4605                         intr->mask &= ~IXGBE_EIMS_LSC;
4606                 }
4607         }
4608
4609         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4610         ixgbe_enable_intr(dev);
4611
4612         return 0;
4613 }
4614
4615 /**
4616  * Interrupt handler which shall be registered for alarm callback for delayed
4617  * handling specific interrupt to wait for the stable nic state. As the
4618  * NIC interrupt state is not stable for ixgbe after link is just down,
4619  * it needs to wait 4 seconds to get the stable status.
4620  *
4621  * @param handle
4622  *  Pointer to interrupt handle.
4623  * @param param
4624  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4625  *
4626  * @return
4627  *  void
4628  */
4629 static void
4630 ixgbe_dev_interrupt_delayed_handler(void *param)
4631 {
4632         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4633         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4634         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4635         struct ixgbe_interrupt *intr =
4636                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4637         struct ixgbe_hw *hw =
4638                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4639         uint32_t eicr;
4640
4641         ixgbe_disable_intr(hw);
4642
4643         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4644         if (eicr & IXGBE_EICR_MAILBOX)
4645                 ixgbe_pf_mbx_process(dev);
4646
4647         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4648                 ixgbe_handle_lasi(hw);
4649                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4650         }
4651
4652         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4653                 ixgbe_dev_link_update(dev, 0);
4654                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4655                 ixgbe_dev_link_status_print(dev);
4656                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4657         }
4658
4659         if (intr->flags & IXGBE_FLAG_MACSEC) {
4660                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL);
4661                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4662         }
4663
4664         /* restore original mask */
4665         intr->mask = intr->mask_original;
4666         intr->mask_original = 0;
4667
4668         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4669         ixgbe_enable_intr(dev);
4670         rte_intr_ack(intr_handle);
4671 }
4672
4673 /**
4674  * Interrupt handler triggered by NIC  for handling
4675  * specific interrupt.
4676  *
4677  * @param handle
4678  *  Pointer to interrupt handle.
4679  * @param param
4680  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4681  *
4682  * @return
4683  *  void
4684  */
4685 static void
4686 ixgbe_dev_interrupt_handler(void *param)
4687 {
4688         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4689
4690         ixgbe_dev_interrupt_get_status(dev);
4691         ixgbe_dev_interrupt_action(dev);
4692 }
4693
4694 static int
4695 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4696 {
4697         struct ixgbe_hw *hw;
4698
4699         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4700         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4701 }
4702
4703 static int
4704 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4705 {
4706         struct ixgbe_hw *hw;
4707
4708         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4709         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4710 }
4711
4712 static int
4713 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4714 {
4715         struct ixgbe_hw *hw;
4716         uint32_t mflcn_reg;
4717         uint32_t fccfg_reg;
4718         int rx_pause;
4719         int tx_pause;
4720
4721         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4722
4723         fc_conf->pause_time = hw->fc.pause_time;
4724         fc_conf->high_water = hw->fc.high_water[0];
4725         fc_conf->low_water = hw->fc.low_water[0];
4726         fc_conf->send_xon = hw->fc.send_xon;
4727         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4728
4729         /*
4730          * Return rx_pause status according to actual setting of
4731          * MFLCN register.
4732          */
4733         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4734         if (mflcn_reg & IXGBE_MFLCN_PMCF)
4735                 fc_conf->mac_ctrl_frame_fwd = 1;
4736         else
4737                 fc_conf->mac_ctrl_frame_fwd = 0;
4738
4739         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4740                 rx_pause = 1;
4741         else
4742                 rx_pause = 0;
4743
4744         /*
4745          * Return tx_pause status according to actual setting of
4746          * FCCFG register.
4747          */
4748         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4749         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4750                 tx_pause = 1;
4751         else
4752                 tx_pause = 0;
4753
4754         if (rx_pause && tx_pause)
4755                 fc_conf->mode = RTE_FC_FULL;
4756         else if (rx_pause)
4757                 fc_conf->mode = RTE_FC_RX_PAUSE;
4758         else if (tx_pause)
4759                 fc_conf->mode = RTE_FC_TX_PAUSE;
4760         else
4761                 fc_conf->mode = RTE_FC_NONE;
4762
4763         return 0;
4764 }
4765
4766 static int
4767 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4768 {
4769         struct ixgbe_hw *hw;
4770         struct ixgbe_adapter *adapter = dev->data->dev_private;
4771         int err;
4772         uint32_t rx_buf_size;
4773         uint32_t max_high_water;
4774         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4775                 ixgbe_fc_none,
4776                 ixgbe_fc_rx_pause,
4777                 ixgbe_fc_tx_pause,
4778                 ixgbe_fc_full
4779         };
4780
4781         PMD_INIT_FUNC_TRACE();
4782
4783         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4784         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4785         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4786
4787         /*
4788          * At least reserve one Ethernet frame for watermark
4789          * high_water/low_water in kilo bytes for ixgbe
4790          */
4791         max_high_water = (rx_buf_size -
4792                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4793         if ((fc_conf->high_water > max_high_water) ||
4794                 (fc_conf->high_water < fc_conf->low_water)) {
4795                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4796                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4797                 return -EINVAL;
4798         }
4799
4800         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4801         hw->fc.pause_time     = fc_conf->pause_time;
4802         hw->fc.high_water[0]  = fc_conf->high_water;
4803         hw->fc.low_water[0]   = fc_conf->low_water;
4804         hw->fc.send_xon       = fc_conf->send_xon;
4805         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4806         adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4807
4808         err = ixgbe_flow_ctrl_enable(dev, hw);
4809         if (err < 0) {
4810                 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4811                 return -EIO;
4812         }
4813         return err;
4814 }
4815
4816 /**
4817  *  ixgbe_pfc_enable_generic - Enable flow control
4818  *  @hw: pointer to hardware structure
4819  *  @tc_num: traffic class number
4820  *  Enable flow control according to the current settings.
4821  */
4822 static int
4823 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4824 {
4825         int ret_val = 0;
4826         uint32_t mflcn_reg, fccfg_reg;
4827         uint32_t reg;
4828         uint32_t fcrtl, fcrth;
4829         uint8_t i;
4830         uint8_t nb_rx_en;
4831
4832         /* Validate the water mark configuration */
4833         if (!hw->fc.pause_time) {
4834                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4835                 goto out;
4836         }
4837
4838         /* Low water mark of zero causes XOFF floods */
4839         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4840                  /* High/Low water can not be 0 */
4841                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4842                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4843                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4844                         goto out;
4845                 }
4846
4847                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4848                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4849                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4850                         goto out;
4851                 }
4852         }
4853         /* Negotiate the fc mode to use */
4854         ixgbe_fc_autoneg(hw);
4855
4856         /* Disable any previous flow control settings */
4857         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4858         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4859
4860         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4861         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4862
4863         switch (hw->fc.current_mode) {
4864         case ixgbe_fc_none:
4865                 /*
4866                  * If the count of enabled RX Priority Flow control >1,
4867                  * and the TX pause can not be disabled
4868                  */
4869                 nb_rx_en = 0;
4870                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4871                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4872                         if (reg & IXGBE_FCRTH_FCEN)
4873                                 nb_rx_en++;
4874                 }
4875                 if (nb_rx_en > 1)
4876                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4877                 break;
4878         case ixgbe_fc_rx_pause:
4879                 /*
4880                  * Rx Flow control is enabled and Tx Flow control is
4881                  * disabled by software override. Since there really
4882                  * isn't a way to advertise that we are capable of RX
4883                  * Pause ONLY, we will advertise that we support both
4884                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4885                  * disable the adapter's ability to send PAUSE frames.
4886                  */
4887                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4888                 /*
4889                  * If the count of enabled RX Priority Flow control >1,
4890                  * and the TX pause can not be disabled
4891                  */
4892                 nb_rx_en = 0;
4893                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4894                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4895                         if (reg & IXGBE_FCRTH_FCEN)
4896                                 nb_rx_en++;
4897                 }
4898                 if (nb_rx_en > 1)
4899                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4900                 break;
4901         case ixgbe_fc_tx_pause:
4902                 /*
4903                  * Tx Flow control is enabled, and Rx Flow control is
4904                  * disabled by software override.
4905                  */
4906                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4907                 break;
4908         case ixgbe_fc_full:
4909                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4910                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4911                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4912                 break;
4913         default:
4914                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4915                 ret_val = IXGBE_ERR_CONFIG;
4916                 goto out;
4917         }
4918
4919         /* Set 802.3x based flow control settings. */
4920         mflcn_reg |= IXGBE_MFLCN_DPF;
4921         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4922         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4923
4924         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4925         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4926                 hw->fc.high_water[tc_num]) {
4927                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4928                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4929                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4930         } else {
4931                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4932                 /*
4933                  * In order to prevent Tx hangs when the internal Tx
4934                  * switch is enabled we must set the high water mark
4935                  * to the maximum FCRTH value.  This allows the Tx
4936                  * switch to function even under heavy Rx workloads.
4937                  */
4938                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4939         }
4940         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4941
4942         /* Configure pause time (2 TCs per register) */
4943         reg = hw->fc.pause_time * 0x00010001;
4944         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4945                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4946
4947         /* Configure flow control refresh threshold value */
4948         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4949
4950 out:
4951         return ret_val;
4952 }
4953
4954 static int
4955 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4956 {
4957         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4958         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4959
4960         if (hw->mac.type != ixgbe_mac_82598EB) {
4961                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4962         }
4963         return ret_val;
4964 }
4965
4966 static int
4967 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4968 {
4969         int err;
4970         uint32_t rx_buf_size;
4971         uint32_t max_high_water;
4972         uint8_t tc_num;
4973         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4974         struct ixgbe_hw *hw =
4975                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4976         struct ixgbe_dcb_config *dcb_config =
4977                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4978
4979         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4980                 ixgbe_fc_none,
4981                 ixgbe_fc_rx_pause,
4982                 ixgbe_fc_tx_pause,
4983                 ixgbe_fc_full
4984         };
4985
4986         PMD_INIT_FUNC_TRACE();
4987
4988         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4989         tc_num = map[pfc_conf->priority];
4990         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4991         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4992         /*
4993          * At least reserve one Ethernet frame for watermark
4994          * high_water/low_water in kilo bytes for ixgbe
4995          */
4996         max_high_water = (rx_buf_size -
4997                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4998         if ((pfc_conf->fc.high_water > max_high_water) ||
4999             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
5000                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
5001                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
5002                 return -EINVAL;
5003         }
5004
5005         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
5006         hw->fc.pause_time = pfc_conf->fc.pause_time;
5007         hw->fc.send_xon = pfc_conf->fc.send_xon;
5008         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
5009         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
5010
5011         err = ixgbe_dcb_pfc_enable(dev, tc_num);
5012
5013         /* Not negotiated is not an error case */
5014         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5015                 return 0;
5016
5017         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5018         return -EIO;
5019 }
5020
5021 static int
5022 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5023                           struct rte_eth_rss_reta_entry64 *reta_conf,
5024                           uint16_t reta_size)
5025 {
5026         uint16_t i, sp_reta_size;
5027         uint8_t j, mask;
5028         uint32_t reta, r;
5029         uint16_t idx, shift;
5030         struct ixgbe_adapter *adapter = dev->data->dev_private;
5031         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5032         uint32_t reta_reg;
5033
5034         PMD_INIT_FUNC_TRACE();
5035
5036         if (!ixgbe_rss_update_sp(hw->mac.type)) {
5037                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5038                         "NIC.");
5039                 return -ENOTSUP;
5040         }
5041
5042         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5043         if (reta_size != sp_reta_size) {
5044                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5045                         "(%d) doesn't match the number hardware can supported "
5046                         "(%d)", reta_size, sp_reta_size);
5047                 return -EINVAL;
5048         }
5049
5050         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5051                 idx = i / RTE_RETA_GROUP_SIZE;
5052                 shift = i % RTE_RETA_GROUP_SIZE;
5053                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5054                                                 IXGBE_4_BIT_MASK);
5055                 if (!mask)
5056                         continue;
5057                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5058                 if (mask == IXGBE_4_BIT_MASK)
5059                         r = 0;
5060                 else
5061                         r = IXGBE_READ_REG(hw, reta_reg);
5062                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5063                         if (mask & (0x1 << j))
5064                                 reta |= reta_conf[idx].reta[shift + j] <<
5065                                                         (CHAR_BIT * j);
5066                         else
5067                                 reta |= r & (IXGBE_8_BIT_MASK <<
5068                                                 (CHAR_BIT * j));
5069                 }
5070                 IXGBE_WRITE_REG(hw, reta_reg, reta);
5071         }
5072         adapter->rss_reta_updated = 1;
5073
5074         return 0;
5075 }
5076
5077 static int
5078 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5079                          struct rte_eth_rss_reta_entry64 *reta_conf,
5080                          uint16_t reta_size)
5081 {
5082         uint16_t i, sp_reta_size;
5083         uint8_t j, mask;
5084         uint32_t reta;
5085         uint16_t idx, shift;
5086         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5087         uint32_t reta_reg;
5088
5089         PMD_INIT_FUNC_TRACE();
5090         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5091         if (reta_size != sp_reta_size) {
5092                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5093                         "(%d) doesn't match the number hardware can supported "
5094                         "(%d)", reta_size, sp_reta_size);
5095                 return -EINVAL;
5096         }
5097
5098         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5099                 idx = i / RTE_RETA_GROUP_SIZE;
5100                 shift = i % RTE_RETA_GROUP_SIZE;
5101                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5102                                                 IXGBE_4_BIT_MASK);
5103                 if (!mask)
5104                         continue;
5105
5106                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5107                 reta = IXGBE_READ_REG(hw, reta_reg);
5108                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5109                         if (mask & (0x1 << j))
5110                                 reta_conf[idx].reta[shift + j] =
5111                                         ((reta >> (CHAR_BIT * j)) &
5112                                                 IXGBE_8_BIT_MASK);
5113                 }
5114         }
5115
5116         return 0;
5117 }
5118
5119 static int
5120 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5121                                 uint32_t index, uint32_t pool)
5122 {
5123         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5124         uint32_t enable_addr = 1;
5125
5126         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5127                              pool, enable_addr);
5128 }
5129
5130 static void
5131 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5132 {
5133         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5134
5135         ixgbe_clear_rar(hw, index);
5136 }
5137
5138 static int
5139 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5140 {
5141         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5142
5143         ixgbe_remove_rar(dev, 0);
5144         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5145
5146         return 0;
5147 }
5148
5149 static bool
5150 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5151 {
5152         if (strcmp(dev->device->driver->name, drv->driver.name))
5153                 return false;
5154
5155         return true;
5156 }
5157
5158 bool
5159 is_ixgbe_supported(struct rte_eth_dev *dev)
5160 {
5161         return is_device_supported(dev, &rte_ixgbe_pmd);
5162 }
5163
5164 static int
5165 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5166 {
5167         uint32_t hlreg0;
5168         uint32_t maxfrs;
5169         struct ixgbe_hw *hw;
5170         struct rte_eth_dev_info dev_info;
5171         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5172         struct rte_eth_dev_data *dev_data = dev->data;
5173         int ret;
5174
5175         ret = ixgbe_dev_info_get(dev, &dev_info);
5176         if (ret != 0)
5177                 return ret;
5178
5179         /* check that mtu is within the allowed range */
5180         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5181                 return -EINVAL;
5182
5183         /* If device is started, refuse mtu that requires the support of
5184          * scattered packets when this feature has not been enabled before.
5185          */
5186         if (dev_data->dev_started && !dev_data->scattered_rx &&
5187             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5188              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5189                 PMD_INIT_LOG(ERR, "Stop port first.");
5190                 return -EINVAL;
5191         }
5192
5193         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5194         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5195
5196         /* switch to jumbo mode if needed */
5197         if (frame_size > RTE_ETHER_MAX_LEN) {
5198                 dev->data->dev_conf.rxmode.offloads |=
5199                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5200                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5201         } else {
5202                 dev->data->dev_conf.rxmode.offloads &=
5203                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5204                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5205         }
5206         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5207
5208         /* update max frame size */
5209         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5210
5211         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5212         maxfrs &= 0x0000FFFF;
5213         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5214         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5215
5216         return 0;
5217 }
5218
5219 /*
5220  * Virtual Function operations
5221  */
5222 static void
5223 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5224 {
5225         struct ixgbe_interrupt *intr =
5226                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5227         struct ixgbe_hw *hw =
5228                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5229
5230         PMD_INIT_FUNC_TRACE();
5231
5232         /* Clear interrupt mask to stop from interrupts being generated */
5233         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5234
5235         IXGBE_WRITE_FLUSH(hw);
5236
5237         /* Clear mask value. */
5238         intr->mask = 0;
5239 }
5240
5241 static void
5242 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5243 {
5244         struct ixgbe_interrupt *intr =
5245                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5246         struct ixgbe_hw *hw =
5247                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5248
5249         PMD_INIT_FUNC_TRACE();
5250
5251         /* VF enable interrupt autoclean */
5252         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5253         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5254         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5255
5256         IXGBE_WRITE_FLUSH(hw);
5257
5258         /* Save IXGBE_VTEIMS value to mask. */
5259         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5260 }
5261
5262 static int
5263 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5264 {
5265         struct rte_eth_conf *conf = &dev->data->dev_conf;
5266         struct ixgbe_adapter *adapter = dev->data->dev_private;
5267
5268         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5269                      dev->data->port_id);
5270
5271         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5272                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5273
5274         /*
5275          * VF has no ability to enable/disable HW CRC
5276          * Keep the persistent behavior the same as Host PF
5277          */
5278 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5279         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5280                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5281                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5282         }
5283 #else
5284         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5285                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5286                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5287         }
5288 #endif
5289
5290         /*
5291          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5292          * allocation or vector Rx preconditions we will reset it.
5293          */
5294         adapter->rx_bulk_alloc_allowed = true;
5295         adapter->rx_vec_allowed = true;
5296
5297         return 0;
5298 }
5299
5300 static int
5301 ixgbevf_dev_start(struct rte_eth_dev *dev)
5302 {
5303         struct ixgbe_hw *hw =
5304                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5305         uint32_t intr_vector = 0;
5306         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5307         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5308
5309         int err, mask = 0;
5310
5311         PMD_INIT_FUNC_TRACE();
5312
5313         /* Stop the link setup handler before resetting the HW. */
5314         ixgbe_dev_wait_setup_link_complete(dev, 0);
5315
5316         err = hw->mac.ops.reset_hw(hw);
5317
5318         /**
5319          * In this case, reuses the MAC address assigned by VF
5320          * initialization.
5321          */
5322         if (err != IXGBE_SUCCESS && err != IXGBE_ERR_INVALID_MAC_ADDR) {
5323                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5324                 return err;
5325         }
5326
5327         hw->mac.get_link_status = true;
5328
5329         /* negotiate mailbox API version to use with the PF. */
5330         ixgbevf_negotiate_api(hw);
5331
5332         ixgbevf_dev_tx_init(dev);
5333
5334         /* This can fail when allocating mbufs for descriptor rings */
5335         err = ixgbevf_dev_rx_init(dev);
5336         if (err) {
5337                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5338                 ixgbe_dev_clear_queues(dev);
5339                 return err;
5340         }
5341
5342         /* Set vfta */
5343         ixgbevf_set_vfta_all(dev, 1);
5344
5345         /* Set HW strip */
5346         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5347                 ETH_VLAN_EXTEND_MASK;
5348         err = ixgbevf_vlan_offload_config(dev, mask);
5349         if (err) {
5350                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5351                 ixgbe_dev_clear_queues(dev);
5352                 return err;
5353         }
5354
5355         ixgbevf_dev_rxtx_start(dev);
5356
5357         /* check and configure queue intr-vector mapping */
5358         if (rte_intr_cap_multiple(intr_handle) &&
5359             dev->data->dev_conf.intr_conf.rxq) {
5360                 /* According to datasheet, only vector 0/1/2 can be used,
5361                  * now only one vector is used for Rx queue
5362                  */
5363                 intr_vector = 1;
5364                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5365                         return -1;
5366         }
5367
5368         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5369                 intr_handle->intr_vec =
5370                         rte_zmalloc("intr_vec",
5371                                     dev->data->nb_rx_queues * sizeof(int), 0);
5372                 if (intr_handle->intr_vec == NULL) {
5373                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5374                                      " intr_vec", dev->data->nb_rx_queues);
5375                         return -ENOMEM;
5376                 }
5377         }
5378         ixgbevf_configure_msix(dev);
5379
5380         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5381          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5382          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5383          * is not cleared, it will fail when following rte_intr_enable( ) tries
5384          * to map Rx queue interrupt to other VFIO vectors.
5385          * So clear uio/vfio intr/evevnfd first to avoid failure.
5386          */
5387         rte_intr_disable(intr_handle);
5388
5389         rte_intr_enable(intr_handle);
5390
5391         /* Re-enable interrupt for VF */
5392         ixgbevf_intr_enable(dev);
5393
5394         /*
5395          * Update link status right before return, because it may
5396          * start link configuration process in a separate thread.
5397          */
5398         ixgbevf_dev_link_update(dev, 0);
5399
5400         hw->adapter_stopped = false;
5401
5402         return 0;
5403 }
5404
5405 static void
5406 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5407 {
5408         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5409         struct ixgbe_adapter *adapter = dev->data->dev_private;
5410         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5411         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5412
5413         if (hw->adapter_stopped)
5414                 return;
5415
5416         PMD_INIT_FUNC_TRACE();
5417
5418         ixgbe_dev_wait_setup_link_complete(dev, 0);
5419
5420         ixgbevf_intr_disable(dev);
5421
5422         dev->data->dev_started = 0;
5423         hw->adapter_stopped = 1;
5424         ixgbe_stop_adapter(hw);
5425
5426         /*
5427           * Clear what we set, but we still keep shadow_vfta to
5428           * restore after device starts
5429           */
5430         ixgbevf_set_vfta_all(dev, 0);
5431
5432         /* Clear stored conf */
5433         dev->data->scattered_rx = 0;
5434
5435         ixgbe_dev_clear_queues(dev);
5436
5437         /* Clean datapath event and queue/vec mapping */
5438         rte_intr_efd_disable(intr_handle);
5439         if (intr_handle->intr_vec != NULL) {
5440                 rte_free(intr_handle->intr_vec);
5441                 intr_handle->intr_vec = NULL;
5442         }
5443
5444         adapter->rss_reta_updated = 0;
5445 }
5446
5447 static int
5448 ixgbevf_dev_close(struct rte_eth_dev *dev)
5449 {
5450         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5451         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5452         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5453
5454         PMD_INIT_FUNC_TRACE();
5455         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5456                 return 0;
5457
5458         ixgbe_reset_hw(hw);
5459
5460         ixgbevf_dev_stop(dev);
5461
5462         ixgbe_dev_free_queues(dev);
5463
5464         /**
5465          * Remove the VF MAC address ro ensure
5466          * that the VF traffic goes to the PF
5467          * after stop, close and detach of the VF
5468          **/
5469         ixgbevf_remove_mac_addr(dev, 0);
5470
5471         dev->dev_ops = NULL;
5472         dev->rx_pkt_burst = NULL;
5473         dev->tx_pkt_burst = NULL;
5474
5475         rte_intr_disable(intr_handle);
5476         rte_intr_callback_unregister(intr_handle,
5477                                      ixgbevf_dev_interrupt_handler, dev);
5478
5479         return 0;
5480 }
5481
5482 /*
5483  * Reset VF device
5484  */
5485 static int
5486 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5487 {
5488         int ret;
5489
5490         ret = eth_ixgbevf_dev_uninit(dev);
5491         if (ret)
5492                 return ret;
5493
5494         ret = eth_ixgbevf_dev_init(dev);
5495
5496         return ret;
5497 }
5498
5499 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5500 {
5501         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5502         struct ixgbe_vfta *shadow_vfta =
5503                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5504         int i = 0, j = 0, vfta = 0, mask = 1;
5505
5506         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5507                 vfta = shadow_vfta->vfta[i];
5508                 if (vfta) {
5509                         mask = 1;
5510                         for (j = 0; j < 32; j++) {
5511                                 if (vfta & mask)
5512                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5513                                                        on, false);
5514                                 mask <<= 1;
5515                         }
5516                 }
5517         }
5518
5519 }
5520
5521 static int
5522 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5523 {
5524         struct ixgbe_hw *hw =
5525                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5526         struct ixgbe_vfta *shadow_vfta =
5527                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5528         uint32_t vid_idx = 0;
5529         uint32_t vid_bit = 0;
5530         int ret = 0;
5531
5532         PMD_INIT_FUNC_TRACE();
5533
5534         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5535         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5536         if (ret) {
5537                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5538                 return ret;
5539         }
5540         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5541         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5542
5543         /* Save what we set and retore it after device reset */
5544         if (on)
5545                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5546         else
5547                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5548
5549         return 0;
5550 }
5551
5552 static void
5553 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5554 {
5555         struct ixgbe_hw *hw =
5556                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5557         uint32_t ctrl;
5558
5559         PMD_INIT_FUNC_TRACE();
5560
5561         if (queue >= hw->mac.max_rx_queues)
5562                 return;
5563
5564         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5565         if (on)
5566                 ctrl |= IXGBE_RXDCTL_VME;
5567         else
5568                 ctrl &= ~IXGBE_RXDCTL_VME;
5569         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5570
5571         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5572 }
5573
5574 static int
5575 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5576 {
5577         struct ixgbe_rx_queue *rxq;
5578         uint16_t i;
5579         int on = 0;
5580
5581         /* VF function only support hw strip feature, others are not support */
5582         if (mask & ETH_VLAN_STRIP_MASK) {
5583                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5584                         rxq = dev->data->rx_queues[i];
5585                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5586                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5587                 }
5588         }
5589
5590         return 0;
5591 }
5592
5593 static int
5594 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5595 {
5596         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5597
5598         ixgbevf_vlan_offload_config(dev, mask);
5599
5600         return 0;
5601 }
5602
5603 int
5604 ixgbe_vt_check(struct ixgbe_hw *hw)
5605 {
5606         uint32_t reg_val;
5607
5608         /* if Virtualization Technology is enabled */
5609         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5610         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5611                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5612                 return -1;
5613         }
5614
5615         return 0;
5616 }
5617
5618 static uint32_t
5619 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5620 {
5621         uint32_t vector = 0;
5622
5623         switch (hw->mac.mc_filter_type) {
5624         case 0:   /* use bits [47:36] of the address */
5625                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5626                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5627                 break;
5628         case 1:   /* use bits [46:35] of the address */
5629                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5630                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5631                 break;
5632         case 2:   /* use bits [45:34] of the address */
5633                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5634                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5635                 break;
5636         case 3:   /* use bits [43:32] of the address */
5637                 vector = ((uc_addr->addr_bytes[4]) |
5638                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5639                 break;
5640         default:  /* Invalid mc_filter_type */
5641                 break;
5642         }
5643
5644         /* vector can only be 12-bits or boundary will be exceeded */
5645         vector &= 0xFFF;
5646         return vector;
5647 }
5648
5649 static int
5650 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5651                         struct rte_ether_addr *mac_addr, uint8_t on)
5652 {
5653         uint32_t vector;
5654         uint32_t uta_idx;
5655         uint32_t reg_val;
5656         uint32_t uta_shift;
5657         uint32_t rc;
5658         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5659         const uint32_t ixgbe_uta_bit_shift = 5;
5660         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5661         const uint32_t bit1 = 0x1;
5662
5663         struct ixgbe_hw *hw =
5664                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5665         struct ixgbe_uta_info *uta_info =
5666                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5667
5668         /* The UTA table only exists on 82599 hardware and newer */
5669         if (hw->mac.type < ixgbe_mac_82599EB)
5670                 return -ENOTSUP;
5671
5672         vector = ixgbe_uta_vector(hw, mac_addr);
5673         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5674         uta_shift = vector & ixgbe_uta_bit_mask;
5675
5676         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5677         if (rc == on)
5678                 return 0;
5679
5680         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5681         if (on) {
5682                 uta_info->uta_in_use++;
5683                 reg_val |= (bit1 << uta_shift);
5684                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5685         } else {
5686                 uta_info->uta_in_use--;
5687                 reg_val &= ~(bit1 << uta_shift);
5688                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5689         }
5690
5691         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5692
5693         if (uta_info->uta_in_use > 0)
5694                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5695                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5696         else
5697                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5698
5699         return 0;
5700 }
5701
5702 static int
5703 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5704 {
5705         int i;
5706         struct ixgbe_hw *hw =
5707                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5708         struct ixgbe_uta_info *uta_info =
5709                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5710
5711         /* The UTA table only exists on 82599 hardware and newer */
5712         if (hw->mac.type < ixgbe_mac_82599EB)
5713                 return -ENOTSUP;
5714
5715         if (on) {
5716                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5717                         uta_info->uta_shadow[i] = ~0;
5718                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5719                 }
5720         } else {
5721                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5722                         uta_info->uta_shadow[i] = 0;
5723                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5724                 }
5725         }
5726         return 0;
5727
5728 }
5729
5730 uint32_t
5731 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5732 {
5733         uint32_t new_val = orig_val;
5734
5735         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5736                 new_val |= IXGBE_VMOLR_AUPE;
5737         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5738                 new_val |= IXGBE_VMOLR_ROMPE;
5739         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5740                 new_val |= IXGBE_VMOLR_ROPE;
5741         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5742                 new_val |= IXGBE_VMOLR_BAM;
5743         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5744                 new_val |= IXGBE_VMOLR_MPE;
5745
5746         return new_val;
5747 }
5748
5749 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5750 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5751 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5752 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5753 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5754         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5755         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5756
5757 static int
5758 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5759                       struct rte_eth_mirror_conf *mirror_conf,
5760                       uint8_t rule_id, uint8_t on)
5761 {
5762         uint32_t mr_ctl, vlvf;
5763         uint32_t mp_lsb = 0;
5764         uint32_t mv_msb = 0;
5765         uint32_t mv_lsb = 0;
5766         uint32_t mp_msb = 0;
5767         uint8_t i = 0;
5768         int reg_index = 0;
5769         uint64_t vlan_mask = 0;
5770
5771         const uint8_t pool_mask_offset = 32;
5772         const uint8_t vlan_mask_offset = 32;
5773         const uint8_t dst_pool_offset = 8;
5774         const uint8_t rule_mr_offset  = 4;
5775         const uint8_t mirror_rule_mask = 0x0F;
5776
5777         struct ixgbe_mirror_info *mr_info =
5778                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5779         struct ixgbe_hw *hw =
5780                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5781         uint8_t mirror_type = 0;
5782
5783         if (ixgbe_vt_check(hw) < 0)
5784                 return -ENOTSUP;
5785
5786         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5787                 return -EINVAL;
5788
5789         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5790                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5791                             mirror_conf->rule_type);
5792                 return -EINVAL;
5793         }
5794
5795         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5796                 mirror_type |= IXGBE_MRCTL_VLME;
5797                 /* Check if vlan id is valid and find conresponding VLAN ID
5798                  * index in VLVF
5799                  */
5800                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5801                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5802                                 /* search vlan id related pool vlan filter
5803                                  * index
5804                                  */
5805                                 reg_index = ixgbe_find_vlvf_slot(
5806                                                 hw,
5807                                                 mirror_conf->vlan.vlan_id[i],
5808                                                 false);
5809                                 if (reg_index < 0)
5810                                         return -EINVAL;
5811                                 vlvf = IXGBE_READ_REG(hw,
5812                                                       IXGBE_VLVF(reg_index));
5813                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5814                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5815                                       mirror_conf->vlan.vlan_id[i]))
5816                                         vlan_mask |= (1ULL << reg_index);
5817                                 else
5818                                         return -EINVAL;
5819                         }
5820                 }
5821
5822                 if (on) {
5823                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5824                         mv_msb = vlan_mask >> vlan_mask_offset;
5825
5826                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5827                                                 mirror_conf->vlan.vlan_mask;
5828                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5829                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5830                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5831                                                 mirror_conf->vlan.vlan_id[i];
5832                         }
5833                 } else {
5834                         mv_lsb = 0;
5835                         mv_msb = 0;
5836                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5837                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5838                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5839                 }
5840         }
5841
5842         /**
5843          * if enable pool mirror, write related pool mask register,if disable
5844          * pool mirror, clear PFMRVM register
5845          */
5846         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5847                 mirror_type |= IXGBE_MRCTL_VPME;
5848                 if (on) {
5849                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5850                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5851                         mr_info->mr_conf[rule_id].pool_mask =
5852                                         mirror_conf->pool_mask;
5853
5854                 } else {
5855                         mp_lsb = 0;
5856                         mp_msb = 0;
5857                         mr_info->mr_conf[rule_id].pool_mask = 0;
5858                 }
5859         }
5860         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5861                 mirror_type |= IXGBE_MRCTL_UPME;
5862         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5863                 mirror_type |= IXGBE_MRCTL_DPME;
5864
5865         /* read  mirror control register and recalculate it */
5866         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5867
5868         if (on) {
5869                 mr_ctl |= mirror_type;
5870                 mr_ctl &= mirror_rule_mask;
5871                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5872         } else {
5873                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5874         }
5875
5876         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5877         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5878
5879         /* write mirrror control  register */
5880         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5881
5882         /* write pool mirrror control  register */
5883         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5884                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5885                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5886                                 mp_msb);
5887         }
5888         /* write VLAN mirrror control  register */
5889         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5890                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5891                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5892                                 mv_msb);
5893         }
5894
5895         return 0;
5896 }
5897
5898 static int
5899 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5900 {
5901         int mr_ctl = 0;
5902         uint32_t lsb_val = 0;
5903         uint32_t msb_val = 0;
5904         const uint8_t rule_mr_offset = 4;
5905
5906         struct ixgbe_hw *hw =
5907                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5908         struct ixgbe_mirror_info *mr_info =
5909                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5910
5911         if (ixgbe_vt_check(hw) < 0)
5912                 return -ENOTSUP;
5913
5914         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5915                 return -EINVAL;
5916
5917         memset(&mr_info->mr_conf[rule_id], 0,
5918                sizeof(struct rte_eth_mirror_conf));
5919
5920         /* clear PFVMCTL register */
5921         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5922
5923         /* clear pool mask register */
5924         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5925         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5926
5927         /* clear vlan mask register */
5928         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5929         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5930
5931         return 0;
5932 }
5933
5934 static int
5935 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5936 {
5937         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5938         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5939         struct ixgbe_interrupt *intr =
5940                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5941         struct ixgbe_hw *hw =
5942                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5943         uint32_t vec = IXGBE_MISC_VEC_ID;
5944
5945         if (rte_intr_allow_others(intr_handle))
5946                 vec = IXGBE_RX_VEC_START;
5947         intr->mask |= (1 << vec);
5948         RTE_SET_USED(queue_id);
5949         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5950
5951         rte_intr_ack(intr_handle);
5952
5953         return 0;
5954 }
5955
5956 static int
5957 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5958 {
5959         struct ixgbe_interrupt *intr =
5960                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5961         struct ixgbe_hw *hw =
5962                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5963         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5964         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5965         uint32_t vec = IXGBE_MISC_VEC_ID;
5966
5967         if (rte_intr_allow_others(intr_handle))
5968                 vec = IXGBE_RX_VEC_START;
5969         intr->mask &= ~(1 << vec);
5970         RTE_SET_USED(queue_id);
5971         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5972
5973         return 0;
5974 }
5975
5976 static int
5977 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5978 {
5979         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5980         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5981         uint32_t mask;
5982         struct ixgbe_hw *hw =
5983                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5984         struct ixgbe_interrupt *intr =
5985                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5986
5987         if (queue_id < 16) {
5988                 ixgbe_disable_intr(hw);
5989                 intr->mask |= (1 << queue_id);
5990                 ixgbe_enable_intr(dev);
5991         } else if (queue_id < 32) {
5992                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5993                 mask &= (1 << queue_id);
5994                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5995         } else if (queue_id < 64) {
5996                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5997                 mask &= (1 << (queue_id - 32));
5998                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5999         }
6000         rte_intr_ack(intr_handle);
6001
6002         return 0;
6003 }
6004
6005 static int
6006 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
6007 {
6008         uint32_t mask;
6009         struct ixgbe_hw *hw =
6010                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6011         struct ixgbe_interrupt *intr =
6012                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
6013
6014         if (queue_id < 16) {
6015                 ixgbe_disable_intr(hw);
6016                 intr->mask &= ~(1 << queue_id);
6017                 ixgbe_enable_intr(dev);
6018         } else if (queue_id < 32) {
6019                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
6020                 mask &= ~(1 << queue_id);
6021                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6022         } else if (queue_id < 64) {
6023                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6024                 mask &= ~(1 << (queue_id - 32));
6025                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6026         }
6027
6028         return 0;
6029 }
6030
6031 static void
6032 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6033                      uint8_t queue, uint8_t msix_vector)
6034 {
6035         uint32_t tmp, idx;
6036
6037         if (direction == -1) {
6038                 /* other causes */
6039                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6040                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
6041                 tmp &= ~0xFF;
6042                 tmp |= msix_vector;
6043                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6044         } else {
6045                 /* rx or tx cause */
6046                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6047                 idx = ((16 * (queue & 1)) + (8 * direction));
6048                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6049                 tmp &= ~(0xFF << idx);
6050                 tmp |= (msix_vector << idx);
6051                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6052         }
6053 }
6054
6055 /**
6056  * set the IVAR registers, mapping interrupt causes to vectors
6057  * @param hw
6058  *  pointer to ixgbe_hw struct
6059  * @direction
6060  *  0 for Rx, 1 for Tx, -1 for other causes
6061  * @queue
6062  *  queue to map the corresponding interrupt to
6063  * @msix_vector
6064  *  the vector to map to the corresponding queue
6065  */
6066 static void
6067 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6068                    uint8_t queue, uint8_t msix_vector)
6069 {
6070         uint32_t tmp, idx;
6071
6072         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6073         if (hw->mac.type == ixgbe_mac_82598EB) {
6074                 if (direction == -1)
6075                         direction = 0;
6076                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6077                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6078                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6079                 tmp |= (msix_vector << (8 * (queue & 0x3)));
6080                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6081         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6082                         (hw->mac.type == ixgbe_mac_X540) ||
6083                         (hw->mac.type == ixgbe_mac_X550) ||
6084                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
6085                 if (direction == -1) {
6086                         /* other causes */
6087                         idx = ((queue & 1) * 8);
6088                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6089                         tmp &= ~(0xFF << idx);
6090                         tmp |= (msix_vector << idx);
6091                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6092                 } else {
6093                         /* rx or tx causes */
6094                         idx = ((16 * (queue & 1)) + (8 * direction));
6095                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6096                         tmp &= ~(0xFF << idx);
6097                         tmp |= (msix_vector << idx);
6098                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6099                 }
6100         }
6101 }
6102
6103 static void
6104 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6105 {
6106         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6107         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6108         struct ixgbe_hw *hw =
6109                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6110         uint32_t q_idx;
6111         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6112         uint32_t base = IXGBE_MISC_VEC_ID;
6113
6114         /* Configure VF other cause ivar */
6115         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6116
6117         /* won't configure msix register if no mapping is done
6118          * between intr vector and event fd.
6119          */
6120         if (!rte_intr_dp_is_en(intr_handle))
6121                 return;
6122
6123         if (rte_intr_allow_others(intr_handle)) {
6124                 base = IXGBE_RX_VEC_START;
6125                 vector_idx = IXGBE_RX_VEC_START;
6126         }
6127
6128         /* Configure all RX queues of VF */
6129         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6130                 /* Force all queue use vector 0,
6131                  * as IXGBE_VF_MAXMSIVECOTR = 1
6132                  */
6133                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6134                 intr_handle->intr_vec[q_idx] = vector_idx;
6135                 if (vector_idx < base + intr_handle->nb_efd - 1)
6136                         vector_idx++;
6137         }
6138
6139         /* As RX queue setting above show, all queues use the vector 0.
6140          * Set only the ITR value of IXGBE_MISC_VEC_ID.
6141          */
6142         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6143                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6144                         | IXGBE_EITR_CNT_WDIS);
6145 }
6146
6147 /**
6148  * Sets up the hardware to properly generate MSI-X interrupts
6149  * @hw
6150  *  board private structure
6151  */
6152 static void
6153 ixgbe_configure_msix(struct rte_eth_dev *dev)
6154 {
6155         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6156         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6157         struct ixgbe_hw *hw =
6158                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6159         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6160         uint32_t vec = IXGBE_MISC_VEC_ID;
6161         uint32_t mask;
6162         uint32_t gpie;
6163
6164         /* won't configure msix register if no mapping is done
6165          * between intr vector and event fd
6166          * but if misx has been enabled already, need to configure
6167          * auto clean, auto mask and throttling.
6168          */
6169         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6170         if (!rte_intr_dp_is_en(intr_handle) &&
6171             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6172                 return;
6173
6174         if (rte_intr_allow_others(intr_handle))
6175                 vec = base = IXGBE_RX_VEC_START;
6176
6177         /* setup GPIE for MSI-x mode */
6178         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6179         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6180                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6181         /* auto clearing and auto setting corresponding bits in EIMS
6182          * when MSI-X interrupt is triggered
6183          */
6184         if (hw->mac.type == ixgbe_mac_82598EB) {
6185                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6186         } else {
6187                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6188                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6189         }
6190         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6191
6192         /* Populate the IVAR table and set the ITR values to the
6193          * corresponding register.
6194          */
6195         if (rte_intr_dp_is_en(intr_handle)) {
6196                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6197                         queue_id++) {
6198                         /* by default, 1:1 mapping */
6199                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6200                         intr_handle->intr_vec[queue_id] = vec;
6201                         if (vec < base + intr_handle->nb_efd - 1)
6202                                 vec++;
6203                 }
6204
6205                 switch (hw->mac.type) {
6206                 case ixgbe_mac_82598EB:
6207                         ixgbe_set_ivar_map(hw, -1,
6208                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6209                                            IXGBE_MISC_VEC_ID);
6210                         break;
6211                 case ixgbe_mac_82599EB:
6212                 case ixgbe_mac_X540:
6213                 case ixgbe_mac_X550:
6214                 case ixgbe_mac_X550EM_x:
6215                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6216                         break;
6217                 default:
6218                         break;
6219                 }
6220         }
6221         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6222                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6223                         | IXGBE_EITR_CNT_WDIS);
6224
6225         /* set up to autoclear timer, and the vectors */
6226         mask = IXGBE_EIMS_ENABLE_MASK;
6227         mask &= ~(IXGBE_EIMS_OTHER |
6228                   IXGBE_EIMS_MAILBOX |
6229                   IXGBE_EIMS_LSC);
6230
6231         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6232 }
6233
6234 int
6235 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6236                            uint16_t queue_idx, uint16_t tx_rate)
6237 {
6238         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6239         struct rte_eth_rxmode *rxmode;
6240         uint32_t rf_dec, rf_int;
6241         uint32_t bcnrc_val;
6242         uint16_t link_speed = dev->data->dev_link.link_speed;
6243
6244         if (queue_idx >= hw->mac.max_tx_queues)
6245                 return -EINVAL;
6246
6247         if (tx_rate != 0) {
6248                 /* Calculate the rate factor values to set */
6249                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6250                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6251                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6252
6253                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6254                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6255                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6256                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6257         } else {
6258                 bcnrc_val = 0;
6259         }
6260
6261         rxmode = &dev->data->dev_conf.rxmode;
6262         /*
6263          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6264          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6265          * set as 0x4.
6266          */
6267         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6268             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6269                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6270                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6271         else
6272                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6273                         IXGBE_MMW_SIZE_DEFAULT);
6274
6275         /* Set RTTBCNRC of queue X */
6276         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6277         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6278         IXGBE_WRITE_FLUSH(hw);
6279
6280         return 0;
6281 }
6282
6283 static int
6284 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6285                      __rte_unused uint32_t index,
6286                      __rte_unused uint32_t pool)
6287 {
6288         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6289         int diag;
6290
6291         /*
6292          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6293          * operation. Trap this case to avoid exhausting the [very limited]
6294          * set of PF resources used to store VF MAC addresses.
6295          */
6296         if (memcmp(hw->mac.perm_addr, mac_addr,
6297                         sizeof(struct rte_ether_addr)) == 0)
6298                 return -1;
6299         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6300         if (diag != 0)
6301                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6302                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6303                             mac_addr->addr_bytes[0],
6304                             mac_addr->addr_bytes[1],
6305                             mac_addr->addr_bytes[2],
6306                             mac_addr->addr_bytes[3],
6307                             mac_addr->addr_bytes[4],
6308                             mac_addr->addr_bytes[5],
6309                             diag);
6310         return diag;
6311 }
6312
6313 static void
6314 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6315 {
6316         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6317         struct rte_ether_addr *perm_addr =
6318                 (struct rte_ether_addr *)hw->mac.perm_addr;
6319         struct rte_ether_addr *mac_addr;
6320         uint32_t i;
6321         int diag;
6322
6323         /*
6324          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6325          * not support the deletion of a given MAC address.
6326          * Instead, it imposes to delete all MAC addresses, then to add again
6327          * all MAC addresses with the exception of the one to be deleted.
6328          */
6329         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6330
6331         /*
6332          * Add again all MAC addresses, with the exception of the deleted one
6333          * and of the permanent MAC address.
6334          */
6335         for (i = 0, mac_addr = dev->data->mac_addrs;
6336              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6337                 /* Skip the deleted MAC address */
6338                 if (i == index)
6339                         continue;
6340                 /* Skip NULL MAC addresses */
6341                 if (rte_is_zero_ether_addr(mac_addr))
6342                         continue;
6343                 /* Skip the permanent MAC address */
6344                 if (memcmp(perm_addr, mac_addr,
6345                                 sizeof(struct rte_ether_addr)) == 0)
6346                         continue;
6347                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6348                 if (diag != 0)
6349                         PMD_DRV_LOG(ERR,
6350                                     "Adding again MAC address "
6351                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6352                                     "diag=%d",
6353                                     mac_addr->addr_bytes[0],
6354                                     mac_addr->addr_bytes[1],
6355                                     mac_addr->addr_bytes[2],
6356                                     mac_addr->addr_bytes[3],
6357                                     mac_addr->addr_bytes[4],
6358                                     mac_addr->addr_bytes[5],
6359                                     diag);
6360         }
6361 }
6362
6363 static int
6364 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6365                         struct rte_ether_addr *addr)
6366 {
6367         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6368
6369         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6370
6371         return 0;
6372 }
6373
6374 int
6375 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6376                         struct rte_eth_syn_filter *filter,
6377                         bool add)
6378 {
6379         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6380         struct ixgbe_filter_info *filter_info =
6381                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6382         uint32_t syn_info;
6383         uint32_t synqf;
6384
6385         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6386                 return -EINVAL;
6387
6388         syn_info = filter_info->syn_info;
6389
6390         if (add) {
6391                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6392                         return -EINVAL;
6393                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6394                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6395
6396                 if (filter->hig_pri)
6397                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6398                 else
6399                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6400         } else {
6401                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6402                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6403                         return -ENOENT;
6404                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6405         }
6406
6407         filter_info->syn_info = synqf;
6408         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6409         IXGBE_WRITE_FLUSH(hw);
6410         return 0;
6411 }
6412
6413 static int
6414 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6415                         struct rte_eth_syn_filter *filter)
6416 {
6417         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6418         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6419
6420         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6421                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6422                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6423                 return 0;
6424         }
6425         return -ENOENT;
6426 }
6427
6428 static int
6429 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6430                         enum rte_filter_op filter_op,
6431                         void *arg)
6432 {
6433         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6434         int ret;
6435
6436         MAC_TYPE_FILTER_SUP(hw->mac.type);
6437
6438         if (filter_op == RTE_ETH_FILTER_NOP)
6439                 return 0;
6440
6441         if (arg == NULL) {
6442                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6443                             filter_op);
6444                 return -EINVAL;
6445         }
6446
6447         switch (filter_op) {
6448         case RTE_ETH_FILTER_ADD:
6449                 ret = ixgbe_syn_filter_set(dev,
6450                                 (struct rte_eth_syn_filter *)arg,
6451                                 TRUE);
6452                 break;
6453         case RTE_ETH_FILTER_DELETE:
6454                 ret = ixgbe_syn_filter_set(dev,
6455                                 (struct rte_eth_syn_filter *)arg,
6456                                 FALSE);
6457                 break;
6458         case RTE_ETH_FILTER_GET:
6459                 ret = ixgbe_syn_filter_get(dev,
6460                                 (struct rte_eth_syn_filter *)arg);
6461                 break;
6462         default:
6463                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6464                 ret = -EINVAL;
6465                 break;
6466         }
6467
6468         return ret;
6469 }
6470
6471
6472 static inline enum ixgbe_5tuple_protocol
6473 convert_protocol_type(uint8_t protocol_value)
6474 {
6475         if (protocol_value == IPPROTO_TCP)
6476                 return IXGBE_FILTER_PROTOCOL_TCP;
6477         else if (protocol_value == IPPROTO_UDP)
6478                 return IXGBE_FILTER_PROTOCOL_UDP;
6479         else if (protocol_value == IPPROTO_SCTP)
6480                 return IXGBE_FILTER_PROTOCOL_SCTP;
6481         else
6482                 return IXGBE_FILTER_PROTOCOL_NONE;
6483 }
6484
6485 /* inject a 5-tuple filter to HW */
6486 static inline void
6487 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6488                            struct ixgbe_5tuple_filter *filter)
6489 {
6490         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6491         int i;
6492         uint32_t ftqf, sdpqf;
6493         uint32_t l34timir = 0;
6494         uint8_t mask = 0xff;
6495
6496         i = filter->index;
6497
6498         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6499                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6500         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6501
6502         ftqf = (uint32_t)(filter->filter_info.proto &
6503                 IXGBE_FTQF_PROTOCOL_MASK);
6504         ftqf |= (uint32_t)((filter->filter_info.priority &
6505                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6506         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6507                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6508         if (filter->filter_info.dst_ip_mask == 0)
6509                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6510         if (filter->filter_info.src_port_mask == 0)
6511                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6512         if (filter->filter_info.dst_port_mask == 0)
6513                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6514         if (filter->filter_info.proto_mask == 0)
6515                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6516         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6517         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6518         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6519
6520         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6521         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6522         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6523         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6524
6525         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6526         l34timir |= (uint32_t)(filter->queue <<
6527                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6528         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6529 }
6530
6531 /*
6532  * add a 5tuple filter
6533  *
6534  * @param
6535  * dev: Pointer to struct rte_eth_dev.
6536  * index: the index the filter allocates.
6537  * filter: ponter to the filter that will be added.
6538  * rx_queue: the queue id the filter assigned to.
6539  *
6540  * @return
6541  *    - On success, zero.
6542  *    - On failure, a negative value.
6543  */
6544 static int
6545 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6546                         struct ixgbe_5tuple_filter *filter)
6547 {
6548         struct ixgbe_filter_info *filter_info =
6549                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6550         int i, idx, shift;
6551
6552         /*
6553          * look for an unused 5tuple filter index,
6554          * and insert the filter to list.
6555          */
6556         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6557                 idx = i / (sizeof(uint32_t) * NBBY);
6558                 shift = i % (sizeof(uint32_t) * NBBY);
6559                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6560                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6561                         filter->index = i;
6562                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6563                                           filter,
6564                                           entries);
6565                         break;
6566                 }
6567         }
6568         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6569                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6570                 return -ENOSYS;
6571         }
6572
6573         ixgbe_inject_5tuple_filter(dev, filter);
6574
6575         return 0;
6576 }
6577
6578 /*
6579  * remove a 5tuple filter
6580  *
6581  * @param
6582  * dev: Pointer to struct rte_eth_dev.
6583  * filter: the pointer of the filter will be removed.
6584  */
6585 static void
6586 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6587                         struct ixgbe_5tuple_filter *filter)
6588 {
6589         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6590         struct ixgbe_filter_info *filter_info =
6591                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6592         uint16_t index = filter->index;
6593
6594         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6595                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6596         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6597         rte_free(filter);
6598
6599         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6600         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6601         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6602         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6603         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6604 }
6605
6606 static int
6607 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6608 {
6609         struct ixgbe_hw *hw;
6610         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6611         struct rte_eth_dev_data *dev_data = dev->data;
6612
6613         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6614
6615         if (mtu < RTE_ETHER_MIN_MTU ||
6616                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6617                 return -EINVAL;
6618
6619         /* If device is started, refuse mtu that requires the support of
6620          * scattered packets when this feature has not been enabled before.
6621          */
6622         if (dev_data->dev_started && !dev_data->scattered_rx &&
6623             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6624              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6625                 PMD_INIT_LOG(ERR, "Stop port first.");
6626                 return -EINVAL;
6627         }
6628
6629         /*
6630          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6631          * request of the version 2.0 of the mailbox API.
6632          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6633          * of the mailbox API.
6634          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6635          * prior to 3.11.33 which contains the following change:
6636          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6637          */
6638         ixgbevf_rlpml_set_vf(hw, max_frame);
6639
6640         /* update max frame size */
6641         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6642         return 0;
6643 }
6644
6645 static inline struct ixgbe_5tuple_filter *
6646 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6647                         struct ixgbe_5tuple_filter_info *key)
6648 {
6649         struct ixgbe_5tuple_filter *it;
6650
6651         TAILQ_FOREACH(it, filter_list, entries) {
6652                 if (memcmp(key, &it->filter_info,
6653                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6654                         return it;
6655                 }
6656         }
6657         return NULL;
6658 }
6659
6660 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6661 static inline int
6662 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6663                         struct ixgbe_5tuple_filter_info *filter_info)
6664 {
6665         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6666                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6667                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6668                 return -EINVAL;
6669
6670         switch (filter->dst_ip_mask) {
6671         case UINT32_MAX:
6672                 filter_info->dst_ip_mask = 0;
6673                 filter_info->dst_ip = filter->dst_ip;
6674                 break;
6675         case 0:
6676                 filter_info->dst_ip_mask = 1;
6677                 break;
6678         default:
6679                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6680                 return -EINVAL;
6681         }
6682
6683         switch (filter->src_ip_mask) {
6684         case UINT32_MAX:
6685                 filter_info->src_ip_mask = 0;
6686                 filter_info->src_ip = filter->src_ip;
6687                 break;
6688         case 0:
6689                 filter_info->src_ip_mask = 1;
6690                 break;
6691         default:
6692                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6693                 return -EINVAL;
6694         }
6695
6696         switch (filter->dst_port_mask) {
6697         case UINT16_MAX:
6698                 filter_info->dst_port_mask = 0;
6699                 filter_info->dst_port = filter->dst_port;
6700                 break;
6701         case 0:
6702                 filter_info->dst_port_mask = 1;
6703                 break;
6704         default:
6705                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6706                 return -EINVAL;
6707         }
6708
6709         switch (filter->src_port_mask) {
6710         case UINT16_MAX:
6711                 filter_info->src_port_mask = 0;
6712                 filter_info->src_port = filter->src_port;
6713                 break;
6714         case 0:
6715                 filter_info->src_port_mask = 1;
6716                 break;
6717         default:
6718                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6719                 return -EINVAL;
6720         }
6721
6722         switch (filter->proto_mask) {
6723         case UINT8_MAX:
6724                 filter_info->proto_mask = 0;
6725                 filter_info->proto =
6726                         convert_protocol_type(filter->proto);
6727                 break;
6728         case 0:
6729                 filter_info->proto_mask = 1;
6730                 break;
6731         default:
6732                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6733                 return -EINVAL;
6734         }
6735
6736         filter_info->priority = (uint8_t)filter->priority;
6737         return 0;
6738 }
6739
6740 /*
6741  * add or delete a ntuple filter
6742  *
6743  * @param
6744  * dev: Pointer to struct rte_eth_dev.
6745  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6746  * add: if true, add filter, if false, remove filter
6747  *
6748  * @return
6749  *    - On success, zero.
6750  *    - On failure, a negative value.
6751  */
6752 int
6753 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6754                         struct rte_eth_ntuple_filter *ntuple_filter,
6755                         bool add)
6756 {
6757         struct ixgbe_filter_info *filter_info =
6758                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6759         struct ixgbe_5tuple_filter_info filter_5tuple;
6760         struct ixgbe_5tuple_filter *filter;
6761         int ret;
6762
6763         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6764                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6765                 return -EINVAL;
6766         }
6767
6768         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6769         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6770         if (ret < 0)
6771                 return ret;
6772
6773         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6774                                          &filter_5tuple);
6775         if (filter != NULL && add) {
6776                 PMD_DRV_LOG(ERR, "filter exists.");
6777                 return -EEXIST;
6778         }
6779         if (filter == NULL && !add) {
6780                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6781                 return -ENOENT;
6782         }
6783
6784         if (add) {
6785                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6786                                 sizeof(struct ixgbe_5tuple_filter), 0);
6787                 if (filter == NULL)
6788                         return -ENOMEM;
6789                 rte_memcpy(&filter->filter_info,
6790                                  &filter_5tuple,
6791                                  sizeof(struct ixgbe_5tuple_filter_info));
6792                 filter->queue = ntuple_filter->queue;
6793                 ret = ixgbe_add_5tuple_filter(dev, filter);
6794                 if (ret < 0) {
6795                         rte_free(filter);
6796                         return ret;
6797                 }
6798         } else
6799                 ixgbe_remove_5tuple_filter(dev, filter);
6800
6801         return 0;
6802 }
6803
6804 /*
6805  * get a ntuple filter
6806  *
6807  * @param
6808  * dev: Pointer to struct rte_eth_dev.
6809  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6810  *
6811  * @return
6812  *    - On success, zero.
6813  *    - On failure, a negative value.
6814  */
6815 static int
6816 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6817                         struct rte_eth_ntuple_filter *ntuple_filter)
6818 {
6819         struct ixgbe_filter_info *filter_info =
6820                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6821         struct ixgbe_5tuple_filter_info filter_5tuple;
6822         struct ixgbe_5tuple_filter *filter;
6823         int ret;
6824
6825         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6826                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6827                 return -EINVAL;
6828         }
6829
6830         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6831         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6832         if (ret < 0)
6833                 return ret;
6834
6835         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6836                                          &filter_5tuple);
6837         if (filter == NULL) {
6838                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6839                 return -ENOENT;
6840         }
6841         ntuple_filter->queue = filter->queue;
6842         return 0;
6843 }
6844
6845 /*
6846  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6847  * @dev: pointer to rte_eth_dev structure
6848  * @filter_op:operation will be taken.
6849  * @arg: a pointer to specific structure corresponding to the filter_op
6850  *
6851  * @return
6852  *    - On success, zero.
6853  *    - On failure, a negative value.
6854  */
6855 static int
6856 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6857                                 enum rte_filter_op filter_op,
6858                                 void *arg)
6859 {
6860         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6861         int ret;
6862
6863         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6864
6865         if (filter_op == RTE_ETH_FILTER_NOP)
6866                 return 0;
6867
6868         if (arg == NULL) {
6869                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6870                             filter_op);
6871                 return -EINVAL;
6872         }
6873
6874         switch (filter_op) {
6875         case RTE_ETH_FILTER_ADD:
6876                 ret = ixgbe_add_del_ntuple_filter(dev,
6877                         (struct rte_eth_ntuple_filter *)arg,
6878                         TRUE);
6879                 break;
6880         case RTE_ETH_FILTER_DELETE:
6881                 ret = ixgbe_add_del_ntuple_filter(dev,
6882                         (struct rte_eth_ntuple_filter *)arg,
6883                         FALSE);
6884                 break;
6885         case RTE_ETH_FILTER_GET:
6886                 ret = ixgbe_get_ntuple_filter(dev,
6887                         (struct rte_eth_ntuple_filter *)arg);
6888                 break;
6889         default:
6890                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6891                 ret = -EINVAL;
6892                 break;
6893         }
6894         return ret;
6895 }
6896
6897 int
6898 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6899                         struct rte_eth_ethertype_filter *filter,
6900                         bool add)
6901 {
6902         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6903         struct ixgbe_filter_info *filter_info =
6904                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6905         uint32_t etqf = 0;
6906         uint32_t etqs = 0;
6907         int ret;
6908         struct ixgbe_ethertype_filter ethertype_filter;
6909
6910         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6911                 return -EINVAL;
6912
6913         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6914                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6915                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6916                         " ethertype filter.", filter->ether_type);
6917                 return -EINVAL;
6918         }
6919
6920         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6921                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6922                 return -EINVAL;
6923         }
6924         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6925                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6926                 return -EINVAL;
6927         }
6928
6929         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6930         if (ret >= 0 && add) {
6931                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6932                             filter->ether_type);
6933                 return -EEXIST;
6934         }
6935         if (ret < 0 && !add) {
6936                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6937                             filter->ether_type);
6938                 return -ENOENT;
6939         }
6940
6941         if (add) {
6942                 etqf = IXGBE_ETQF_FILTER_EN;
6943                 etqf |= (uint32_t)filter->ether_type;
6944                 etqs |= (uint32_t)((filter->queue <<
6945                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6946                                     IXGBE_ETQS_RX_QUEUE);
6947                 etqs |= IXGBE_ETQS_QUEUE_EN;
6948
6949                 ethertype_filter.ethertype = filter->ether_type;
6950                 ethertype_filter.etqf = etqf;
6951                 ethertype_filter.etqs = etqs;
6952                 ethertype_filter.conf = FALSE;
6953                 ret = ixgbe_ethertype_filter_insert(filter_info,
6954                                                     &ethertype_filter);
6955                 if (ret < 0) {
6956                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6957                         return -ENOSPC;
6958                 }
6959         } else {
6960                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6961                 if (ret < 0)
6962                         return -ENOSYS;
6963         }
6964         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6965         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6966         IXGBE_WRITE_FLUSH(hw);
6967
6968         return 0;
6969 }
6970
6971 static int
6972 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6973                         struct rte_eth_ethertype_filter *filter)
6974 {
6975         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6976         struct ixgbe_filter_info *filter_info =
6977                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6978         uint32_t etqf, etqs;
6979         int ret;
6980
6981         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6982         if (ret < 0) {
6983                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6984                             filter->ether_type);
6985                 return -ENOENT;
6986         }
6987
6988         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6989         if (etqf & IXGBE_ETQF_FILTER_EN) {
6990                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6991                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6992                 filter->flags = 0;
6993                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6994                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6995                 return 0;
6996         }
6997         return -ENOENT;
6998 }
6999
7000 /*
7001  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
7002  * @dev: pointer to rte_eth_dev structure
7003  * @filter_op:operation will be taken.
7004  * @arg: a pointer to specific structure corresponding to the filter_op
7005  */
7006 static int
7007 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
7008                                 enum rte_filter_op filter_op,
7009                                 void *arg)
7010 {
7011         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7012         int ret;
7013
7014         MAC_TYPE_FILTER_SUP(hw->mac.type);
7015
7016         if (filter_op == RTE_ETH_FILTER_NOP)
7017                 return 0;
7018
7019         if (arg == NULL) {
7020                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7021                             filter_op);
7022                 return -EINVAL;
7023         }
7024
7025         switch (filter_op) {
7026         case RTE_ETH_FILTER_ADD:
7027                 ret = ixgbe_add_del_ethertype_filter(dev,
7028                         (struct rte_eth_ethertype_filter *)arg,
7029                         TRUE);
7030                 break;
7031         case RTE_ETH_FILTER_DELETE:
7032                 ret = ixgbe_add_del_ethertype_filter(dev,
7033                         (struct rte_eth_ethertype_filter *)arg,
7034                         FALSE);
7035                 break;
7036         case RTE_ETH_FILTER_GET:
7037                 ret = ixgbe_get_ethertype_filter(dev,
7038                         (struct rte_eth_ethertype_filter *)arg);
7039                 break;
7040         default:
7041                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7042                 ret = -EINVAL;
7043                 break;
7044         }
7045         return ret;
7046 }
7047
7048 static int
7049 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
7050                      enum rte_filter_type filter_type,
7051                      enum rte_filter_op filter_op,
7052                      void *arg)
7053 {
7054         int ret = 0;
7055
7056         switch (filter_type) {
7057         case RTE_ETH_FILTER_NTUPLE:
7058                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
7059                 break;
7060         case RTE_ETH_FILTER_ETHERTYPE:
7061                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
7062                 break;
7063         case RTE_ETH_FILTER_SYN:
7064                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
7065                 break;
7066         case RTE_ETH_FILTER_FDIR:
7067                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
7068                 break;
7069         case RTE_ETH_FILTER_L2_TUNNEL:
7070                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
7071                 break;
7072         case RTE_ETH_FILTER_GENERIC:
7073                 if (filter_op != RTE_ETH_FILTER_GET)
7074                         return -EINVAL;
7075                 *(const void **)arg = &ixgbe_flow_ops;
7076                 break;
7077         default:
7078                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7079                                                         filter_type);
7080                 ret = -EINVAL;
7081                 break;
7082         }
7083
7084         return ret;
7085 }
7086
7087 static u8 *
7088 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
7089                         u8 **mc_addr_ptr, u32 *vmdq)
7090 {
7091         u8 *mc_addr;
7092
7093         *vmdq = 0;
7094         mc_addr = *mc_addr_ptr;
7095         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
7096         return mc_addr;
7097 }
7098
7099 static int
7100 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
7101                           struct rte_ether_addr *mc_addr_set,
7102                           uint32_t nb_mc_addr)
7103 {
7104         struct ixgbe_hw *hw;
7105         u8 *mc_addr_list;
7106
7107         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7108         mc_addr_list = (u8 *)mc_addr_set;
7109         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
7110                                          ixgbe_dev_addr_list_itr, TRUE);
7111 }
7112
7113 static uint64_t
7114 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
7115 {
7116         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7117         uint64_t systime_cycles;
7118
7119         switch (hw->mac.type) {
7120         case ixgbe_mac_X550:
7121         case ixgbe_mac_X550EM_x:
7122         case ixgbe_mac_X550EM_a:
7123                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
7124                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7125                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7126                                 * NSEC_PER_SEC;
7127                 break;
7128         default:
7129                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7130                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7131                                 << 32;
7132         }
7133
7134         return systime_cycles;
7135 }
7136
7137 static uint64_t
7138 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7139 {
7140         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7141         uint64_t rx_tstamp_cycles;
7142
7143         switch (hw->mac.type) {
7144         case ixgbe_mac_X550:
7145         case ixgbe_mac_X550EM_x:
7146         case ixgbe_mac_X550EM_a:
7147                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7148                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7149                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7150                                 * NSEC_PER_SEC;
7151                 break;
7152         default:
7153                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7154                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7155                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7156                                 << 32;
7157         }
7158
7159         return rx_tstamp_cycles;
7160 }
7161
7162 static uint64_t
7163 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7164 {
7165         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7166         uint64_t tx_tstamp_cycles;
7167
7168         switch (hw->mac.type) {
7169         case ixgbe_mac_X550:
7170         case ixgbe_mac_X550EM_x:
7171         case ixgbe_mac_X550EM_a:
7172                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7173                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7174                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7175                                 * NSEC_PER_SEC;
7176                 break;
7177         default:
7178                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7179                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7180                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7181                                 << 32;
7182         }
7183
7184         return tx_tstamp_cycles;
7185 }
7186
7187 static void
7188 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7189 {
7190         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7191         struct ixgbe_adapter *adapter = dev->data->dev_private;
7192         struct rte_eth_link link;
7193         uint32_t incval = 0;
7194         uint32_t shift = 0;
7195
7196         /* Get current link speed. */
7197         ixgbe_dev_link_update(dev, 1);
7198         rte_eth_linkstatus_get(dev, &link);
7199
7200         switch (link.link_speed) {
7201         case ETH_SPEED_NUM_100M:
7202                 incval = IXGBE_INCVAL_100;
7203                 shift = IXGBE_INCVAL_SHIFT_100;
7204                 break;
7205         case ETH_SPEED_NUM_1G:
7206                 incval = IXGBE_INCVAL_1GB;
7207                 shift = IXGBE_INCVAL_SHIFT_1GB;
7208                 break;
7209         case ETH_SPEED_NUM_10G:
7210         default:
7211                 incval = IXGBE_INCVAL_10GB;
7212                 shift = IXGBE_INCVAL_SHIFT_10GB;
7213                 break;
7214         }
7215
7216         switch (hw->mac.type) {
7217         case ixgbe_mac_X550:
7218         case ixgbe_mac_X550EM_x:
7219         case ixgbe_mac_X550EM_a:
7220                 /* Independent of link speed. */
7221                 incval = 1;
7222                 /* Cycles read will be interpreted as ns. */
7223                 shift = 0;
7224                 /* Fall-through */
7225         case ixgbe_mac_X540:
7226                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7227                 break;
7228         case ixgbe_mac_82599EB:
7229                 incval >>= IXGBE_INCVAL_SHIFT_82599;
7230                 shift -= IXGBE_INCVAL_SHIFT_82599;
7231                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7232                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7233                 break;
7234         default:
7235                 /* Not supported. */
7236                 return;
7237         }
7238
7239         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7240         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7241         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7242
7243         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7244         adapter->systime_tc.cc_shift = shift;
7245         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7246
7247         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7248         adapter->rx_tstamp_tc.cc_shift = shift;
7249         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7250
7251         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7252         adapter->tx_tstamp_tc.cc_shift = shift;
7253         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7254 }
7255
7256 static int
7257 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7258 {
7259         struct ixgbe_adapter *adapter = dev->data->dev_private;
7260
7261         adapter->systime_tc.nsec += delta;
7262         adapter->rx_tstamp_tc.nsec += delta;
7263         adapter->tx_tstamp_tc.nsec += delta;
7264
7265         return 0;
7266 }
7267
7268 static int
7269 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7270 {
7271         uint64_t ns;
7272         struct ixgbe_adapter *adapter = dev->data->dev_private;
7273
7274         ns = rte_timespec_to_ns(ts);
7275         /* Set the timecounters to a new value. */
7276         adapter->systime_tc.nsec = ns;
7277         adapter->rx_tstamp_tc.nsec = ns;
7278         adapter->tx_tstamp_tc.nsec = ns;
7279
7280         return 0;
7281 }
7282
7283 static int
7284 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7285 {
7286         uint64_t ns, systime_cycles;
7287         struct ixgbe_adapter *adapter = dev->data->dev_private;
7288
7289         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7290         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7291         *ts = rte_ns_to_timespec(ns);
7292
7293         return 0;
7294 }
7295
7296 static int
7297 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7298 {
7299         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7300         uint32_t tsync_ctl;
7301         uint32_t tsauxc;
7302
7303         /* Stop the timesync system time. */
7304         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7305         /* Reset the timesync system time value. */
7306         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7307         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7308
7309         /* Enable system time for platforms where it isn't on by default. */
7310         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7311         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7312         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7313
7314         ixgbe_start_timecounters(dev);
7315
7316         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7317         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7318                         (RTE_ETHER_TYPE_1588 |
7319                          IXGBE_ETQF_FILTER_EN |
7320                          IXGBE_ETQF_1588));
7321
7322         /* Enable timestamping of received PTP packets. */
7323         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7324         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7325         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7326
7327         /* Enable timestamping of transmitted PTP packets. */
7328         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7329         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7330         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7331
7332         IXGBE_WRITE_FLUSH(hw);
7333
7334         return 0;
7335 }
7336
7337 static int
7338 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7339 {
7340         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7341         uint32_t tsync_ctl;
7342
7343         /* Disable timestamping of transmitted PTP packets. */
7344         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7345         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7346         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7347
7348         /* Disable timestamping of received PTP packets. */
7349         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7350         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7351         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7352
7353         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7354         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7355
7356         /* Stop incrementating the System Time registers. */
7357         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7358
7359         return 0;
7360 }
7361
7362 static int
7363 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7364                                  struct timespec *timestamp,
7365                                  uint32_t flags __rte_unused)
7366 {
7367         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7368         struct ixgbe_adapter *adapter = dev->data->dev_private;
7369         uint32_t tsync_rxctl;
7370         uint64_t rx_tstamp_cycles;
7371         uint64_t ns;
7372
7373         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7374         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7375                 return -EINVAL;
7376
7377         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7378         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7379         *timestamp = rte_ns_to_timespec(ns);
7380
7381         return  0;
7382 }
7383
7384 static int
7385 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7386                                  struct timespec *timestamp)
7387 {
7388         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7389         struct ixgbe_adapter *adapter = dev->data->dev_private;
7390         uint32_t tsync_txctl;
7391         uint64_t tx_tstamp_cycles;
7392         uint64_t ns;
7393
7394         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7395         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7396                 return -EINVAL;
7397
7398         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7399         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7400         *timestamp = rte_ns_to_timespec(ns);
7401
7402         return 0;
7403 }
7404
7405 static int
7406 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7407 {
7408         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7409         int count = 0;
7410         int g_ind = 0;
7411         const struct reg_info *reg_group;
7412         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7413                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7414
7415         while ((reg_group = reg_set[g_ind++]))
7416                 count += ixgbe_regs_group_count(reg_group);
7417
7418         return count;
7419 }
7420
7421 static int
7422 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7423 {
7424         int count = 0;
7425         int g_ind = 0;
7426         const struct reg_info *reg_group;
7427
7428         while ((reg_group = ixgbevf_regs[g_ind++]))
7429                 count += ixgbe_regs_group_count(reg_group);
7430
7431         return count;
7432 }
7433
7434 static int
7435 ixgbe_get_regs(struct rte_eth_dev *dev,
7436               struct rte_dev_reg_info *regs)
7437 {
7438         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7439         uint32_t *data = regs->data;
7440         int g_ind = 0;
7441         int count = 0;
7442         const struct reg_info *reg_group;
7443         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7444                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7445
7446         if (data == NULL) {
7447                 regs->length = ixgbe_get_reg_length(dev);
7448                 regs->width = sizeof(uint32_t);
7449                 return 0;
7450         }
7451
7452         /* Support only full register dump */
7453         if ((regs->length == 0) ||
7454             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7455                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7456                         hw->device_id;
7457                 while ((reg_group = reg_set[g_ind++]))
7458                         count += ixgbe_read_regs_group(dev, &data[count],
7459                                 reg_group);
7460                 return 0;
7461         }
7462
7463         return -ENOTSUP;
7464 }
7465
7466 static int
7467 ixgbevf_get_regs(struct rte_eth_dev *dev,
7468                 struct rte_dev_reg_info *regs)
7469 {
7470         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7471         uint32_t *data = regs->data;
7472         int g_ind = 0;
7473         int count = 0;
7474         const struct reg_info *reg_group;
7475
7476         if (data == NULL) {
7477                 regs->length = ixgbevf_get_reg_length(dev);
7478                 regs->width = sizeof(uint32_t);
7479                 return 0;
7480         }
7481
7482         /* Support only full register dump */
7483         if ((regs->length == 0) ||
7484             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7485                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7486                         hw->device_id;
7487                 while ((reg_group = ixgbevf_regs[g_ind++]))
7488                         count += ixgbe_read_regs_group(dev, &data[count],
7489                                                       reg_group);
7490                 return 0;
7491         }
7492
7493         return -ENOTSUP;
7494 }
7495
7496 static int
7497 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7498 {
7499         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7500
7501         /* Return unit is byte count */
7502         return hw->eeprom.word_size * 2;
7503 }
7504
7505 static int
7506 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7507                 struct rte_dev_eeprom_info *in_eeprom)
7508 {
7509         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7510         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7511         uint16_t *data = in_eeprom->data;
7512         int first, length;
7513
7514         first = in_eeprom->offset >> 1;
7515         length = in_eeprom->length >> 1;
7516         if ((first > hw->eeprom.word_size) ||
7517             ((first + length) > hw->eeprom.word_size))
7518                 return -EINVAL;
7519
7520         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7521
7522         return eeprom->ops.read_buffer(hw, first, length, data);
7523 }
7524
7525 static int
7526 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7527                 struct rte_dev_eeprom_info *in_eeprom)
7528 {
7529         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7530         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7531         uint16_t *data = in_eeprom->data;
7532         int first, length;
7533
7534         first = in_eeprom->offset >> 1;
7535         length = in_eeprom->length >> 1;
7536         if ((first > hw->eeprom.word_size) ||
7537             ((first + length) > hw->eeprom.word_size))
7538                 return -EINVAL;
7539
7540         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7541
7542         return eeprom->ops.write_buffer(hw,  first, length, data);
7543 }
7544
7545 static int
7546 ixgbe_get_module_info(struct rte_eth_dev *dev,
7547                       struct rte_eth_dev_module_info *modinfo)
7548 {
7549         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7550         uint32_t status;
7551         uint8_t sff8472_rev, addr_mode;
7552         bool page_swap = false;
7553
7554         /* Check whether we support SFF-8472 or not */
7555         status = hw->phy.ops.read_i2c_eeprom(hw,
7556                                              IXGBE_SFF_SFF_8472_COMP,
7557                                              &sff8472_rev);
7558         if (status != 0)
7559                 return -EIO;
7560
7561         /* addressing mode is not supported */
7562         status = hw->phy.ops.read_i2c_eeprom(hw,
7563                                              IXGBE_SFF_SFF_8472_SWAP,
7564                                              &addr_mode);
7565         if (status != 0)
7566                 return -EIO;
7567
7568         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7569                 PMD_DRV_LOG(ERR,
7570                             "Address change required to access page 0xA2, "
7571                             "but not supported. Please report the module "
7572                             "type to the driver maintainers.");
7573                 page_swap = true;
7574         }
7575
7576         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7577                 /* We have a SFP, but it does not support SFF-8472 */
7578                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7579                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7580         } else {
7581                 /* We have a SFP which supports a revision of SFF-8472. */
7582                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7583                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7584         }
7585
7586         return 0;
7587 }
7588
7589 static int
7590 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7591                         struct rte_dev_eeprom_info *info)
7592 {
7593         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7594         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7595         uint8_t databyte = 0xFF;
7596         uint8_t *data = info->data;
7597         uint32_t i = 0;
7598
7599         if (info->length == 0)
7600                 return -EINVAL;
7601
7602         for (i = info->offset; i < info->offset + info->length; i++) {
7603                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7604                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7605                 else
7606                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7607
7608                 if (status != 0)
7609                         return -EIO;
7610
7611                 data[i - info->offset] = databyte;
7612         }
7613
7614         return 0;
7615 }
7616
7617 uint16_t
7618 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7619         switch (mac_type) {
7620         case ixgbe_mac_X550:
7621         case ixgbe_mac_X550EM_x:
7622         case ixgbe_mac_X550EM_a:
7623                 return ETH_RSS_RETA_SIZE_512;
7624         case ixgbe_mac_X550_vf:
7625         case ixgbe_mac_X550EM_x_vf:
7626         case ixgbe_mac_X550EM_a_vf:
7627                 return ETH_RSS_RETA_SIZE_64;
7628         case ixgbe_mac_X540_vf:
7629         case ixgbe_mac_82599_vf:
7630                 return 0;
7631         default:
7632                 return ETH_RSS_RETA_SIZE_128;
7633         }
7634 }
7635
7636 uint32_t
7637 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7638         switch (mac_type) {
7639         case ixgbe_mac_X550:
7640         case ixgbe_mac_X550EM_x:
7641         case ixgbe_mac_X550EM_a:
7642                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7643                         return IXGBE_RETA(reta_idx >> 2);
7644                 else
7645                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7646         case ixgbe_mac_X550_vf:
7647         case ixgbe_mac_X550EM_x_vf:
7648         case ixgbe_mac_X550EM_a_vf:
7649                 return IXGBE_VFRETA(reta_idx >> 2);
7650         default:
7651                 return IXGBE_RETA(reta_idx >> 2);
7652         }
7653 }
7654
7655 uint32_t
7656 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7657         switch (mac_type) {
7658         case ixgbe_mac_X550_vf:
7659         case ixgbe_mac_X550EM_x_vf:
7660         case ixgbe_mac_X550EM_a_vf:
7661                 return IXGBE_VFMRQC;
7662         default:
7663                 return IXGBE_MRQC;
7664         }
7665 }
7666
7667 uint32_t
7668 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7669         switch (mac_type) {
7670         case ixgbe_mac_X550_vf:
7671         case ixgbe_mac_X550EM_x_vf:
7672         case ixgbe_mac_X550EM_a_vf:
7673                 return IXGBE_VFRSSRK(i);
7674         default:
7675                 return IXGBE_RSSRK(i);
7676         }
7677 }
7678
7679 bool
7680 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7681         switch (mac_type) {
7682         case ixgbe_mac_82599_vf:
7683         case ixgbe_mac_X540_vf:
7684                 return 0;
7685         default:
7686                 return 1;
7687         }
7688 }
7689
7690 static int
7691 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7692                         struct rte_eth_dcb_info *dcb_info)
7693 {
7694         struct ixgbe_dcb_config *dcb_config =
7695                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7696         struct ixgbe_dcb_tc_config *tc;
7697         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7698         uint8_t nb_tcs;
7699         uint8_t i, j;
7700
7701         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7702                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7703         else
7704                 dcb_info->nb_tcs = 1;
7705
7706         tc_queue = &dcb_info->tc_queue;
7707         nb_tcs = dcb_info->nb_tcs;
7708
7709         if (dcb_config->vt_mode) { /* vt is enabled*/
7710                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7711                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7712                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7713                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7714                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7715                         for (j = 0; j < nb_tcs; j++) {
7716                                 tc_queue->tc_rxq[0][j].base = j;
7717                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7718                                 tc_queue->tc_txq[0][j].base = j;
7719                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7720                         }
7721                 } else {
7722                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7723                                 for (j = 0; j < nb_tcs; j++) {
7724                                         tc_queue->tc_rxq[i][j].base =
7725                                                 i * nb_tcs + j;
7726                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7727                                         tc_queue->tc_txq[i][j].base =
7728                                                 i * nb_tcs + j;
7729                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7730                                 }
7731                         }
7732                 }
7733         } else { /* vt is disabled*/
7734                 struct rte_eth_dcb_rx_conf *rx_conf =
7735                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7736                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7737                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7738                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7739                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7740                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7741                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7742                         }
7743                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7744                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7745                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7746                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7747                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7748                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7749                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7750                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7751                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7752                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7753                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7754                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7755                         }
7756                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7757                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7758                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7759                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7760                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7761                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7762                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7763                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7764                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7765                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7766                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7767                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7768                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7769                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7770                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7771                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7772                 }
7773         }
7774         for (i = 0; i < dcb_info->nb_tcs; i++) {
7775                 tc = &dcb_config->tc_config[i];
7776                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7777         }
7778         return 0;
7779 }
7780
7781 /* Update e-tag ether type */
7782 static int
7783 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7784                             uint16_t ether_type)
7785 {
7786         uint32_t etag_etype;
7787
7788         if (hw->mac.type != ixgbe_mac_X550 &&
7789             hw->mac.type != ixgbe_mac_X550EM_x &&
7790             hw->mac.type != ixgbe_mac_X550EM_a) {
7791                 return -ENOTSUP;
7792         }
7793
7794         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7795         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7796         etag_etype |= ether_type;
7797         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7798         IXGBE_WRITE_FLUSH(hw);
7799
7800         return 0;
7801 }
7802
7803 /* Config l2 tunnel ether type */
7804 static int
7805 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7806                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7807 {
7808         int ret = 0;
7809         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7810         struct ixgbe_l2_tn_info *l2_tn_info =
7811                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7812
7813         if (l2_tunnel == NULL)
7814                 return -EINVAL;
7815
7816         switch (l2_tunnel->l2_tunnel_type) {
7817         case RTE_L2_TUNNEL_TYPE_E_TAG:
7818                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7819                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7820                 break;
7821         default:
7822                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7823                 ret = -EINVAL;
7824                 break;
7825         }
7826
7827         return ret;
7828 }
7829
7830 /* Enable e-tag tunnel */
7831 static int
7832 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7833 {
7834         uint32_t etag_etype;
7835
7836         if (hw->mac.type != ixgbe_mac_X550 &&
7837             hw->mac.type != ixgbe_mac_X550EM_x &&
7838             hw->mac.type != ixgbe_mac_X550EM_a) {
7839                 return -ENOTSUP;
7840         }
7841
7842         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7843         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7844         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7845         IXGBE_WRITE_FLUSH(hw);
7846
7847         return 0;
7848 }
7849
7850 /* Enable l2 tunnel */
7851 static int
7852 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7853                            enum rte_eth_tunnel_type l2_tunnel_type)
7854 {
7855         int ret = 0;
7856         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7857         struct ixgbe_l2_tn_info *l2_tn_info =
7858                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7859
7860         switch (l2_tunnel_type) {
7861         case RTE_L2_TUNNEL_TYPE_E_TAG:
7862                 l2_tn_info->e_tag_en = TRUE;
7863                 ret = ixgbe_e_tag_enable(hw);
7864                 break;
7865         default:
7866                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7867                 ret = -EINVAL;
7868                 break;
7869         }
7870
7871         return ret;
7872 }
7873
7874 /* Disable e-tag tunnel */
7875 static int
7876 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7877 {
7878         uint32_t etag_etype;
7879
7880         if (hw->mac.type != ixgbe_mac_X550 &&
7881             hw->mac.type != ixgbe_mac_X550EM_x &&
7882             hw->mac.type != ixgbe_mac_X550EM_a) {
7883                 return -ENOTSUP;
7884         }
7885
7886         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7887         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7888         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7889         IXGBE_WRITE_FLUSH(hw);
7890
7891         return 0;
7892 }
7893
7894 /* Disable l2 tunnel */
7895 static int
7896 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7897                             enum rte_eth_tunnel_type l2_tunnel_type)
7898 {
7899         int ret = 0;
7900         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7901         struct ixgbe_l2_tn_info *l2_tn_info =
7902                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7903
7904         switch (l2_tunnel_type) {
7905         case RTE_L2_TUNNEL_TYPE_E_TAG:
7906                 l2_tn_info->e_tag_en = FALSE;
7907                 ret = ixgbe_e_tag_disable(hw);
7908                 break;
7909         default:
7910                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7911                 ret = -EINVAL;
7912                 break;
7913         }
7914
7915         return ret;
7916 }
7917
7918 static int
7919 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7920                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7921 {
7922         int ret = 0;
7923         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7924         uint32_t i, rar_entries;
7925         uint32_t rar_low, rar_high;
7926
7927         if (hw->mac.type != ixgbe_mac_X550 &&
7928             hw->mac.type != ixgbe_mac_X550EM_x &&
7929             hw->mac.type != ixgbe_mac_X550EM_a) {
7930                 return -ENOTSUP;
7931         }
7932
7933         rar_entries = ixgbe_get_num_rx_addrs(hw);
7934
7935         for (i = 1; i < rar_entries; i++) {
7936                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7937                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7938                 if ((rar_high & IXGBE_RAH_AV) &&
7939                     (rar_high & IXGBE_RAH_ADTYPE) &&
7940                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7941                      l2_tunnel->tunnel_id)) {
7942                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7943                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7944
7945                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7946
7947                         return ret;
7948                 }
7949         }
7950
7951         return ret;
7952 }
7953
7954 static int
7955 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7956                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7957 {
7958         int ret = 0;
7959         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7960         uint32_t i, rar_entries;
7961         uint32_t rar_low, rar_high;
7962
7963         if (hw->mac.type != ixgbe_mac_X550 &&
7964             hw->mac.type != ixgbe_mac_X550EM_x &&
7965             hw->mac.type != ixgbe_mac_X550EM_a) {
7966                 return -ENOTSUP;
7967         }
7968
7969         /* One entry for one tunnel. Try to remove potential existing entry. */
7970         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7971
7972         rar_entries = ixgbe_get_num_rx_addrs(hw);
7973
7974         for (i = 1; i < rar_entries; i++) {
7975                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7976                 if (rar_high & IXGBE_RAH_AV) {
7977                         continue;
7978                 } else {
7979                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7980                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7981                         rar_low = l2_tunnel->tunnel_id;
7982
7983                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7984                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7985
7986                         return ret;
7987                 }
7988         }
7989
7990         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7991                      " Please remove a rule before adding a new one.");
7992         return -EINVAL;
7993 }
7994
7995 static inline struct ixgbe_l2_tn_filter *
7996 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7997                           struct ixgbe_l2_tn_key *key)
7998 {
7999         int ret;
8000
8001         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
8002         if (ret < 0)
8003                 return NULL;
8004
8005         return l2_tn_info->hash_map[ret];
8006 }
8007
8008 static inline int
8009 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8010                           struct ixgbe_l2_tn_filter *l2_tn_filter)
8011 {
8012         int ret;
8013
8014         ret = rte_hash_add_key(l2_tn_info->hash_handle,
8015                                &l2_tn_filter->key);
8016
8017         if (ret < 0) {
8018                 PMD_DRV_LOG(ERR,
8019                             "Failed to insert L2 tunnel filter"
8020                             " to hash table %d!",
8021                             ret);
8022                 return ret;
8023         }
8024
8025         l2_tn_info->hash_map[ret] = l2_tn_filter;
8026
8027         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8028
8029         return 0;
8030 }
8031
8032 static inline int
8033 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8034                           struct ixgbe_l2_tn_key *key)
8035 {
8036         int ret;
8037         struct ixgbe_l2_tn_filter *l2_tn_filter;
8038
8039         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
8040
8041         if (ret < 0) {
8042                 PMD_DRV_LOG(ERR,
8043                             "No such L2 tunnel filter to delete %d!",
8044                             ret);
8045                 return ret;
8046         }
8047
8048         l2_tn_filter = l2_tn_info->hash_map[ret];
8049         l2_tn_info->hash_map[ret] = NULL;
8050
8051         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8052         rte_free(l2_tn_filter);
8053
8054         return 0;
8055 }
8056
8057 /* Add l2 tunnel filter */
8058 int
8059 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
8060                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
8061                                bool restore)
8062 {
8063         int ret;
8064         struct ixgbe_l2_tn_info *l2_tn_info =
8065                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8066         struct ixgbe_l2_tn_key key;
8067         struct ixgbe_l2_tn_filter *node;
8068
8069         if (!restore) {
8070                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8071                 key.tn_id = l2_tunnel->tunnel_id;
8072
8073                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
8074
8075                 if (node) {
8076                         PMD_DRV_LOG(ERR,
8077                                     "The L2 tunnel filter already exists!");
8078                         return -EINVAL;
8079                 }
8080
8081                 node = rte_zmalloc("ixgbe_l2_tn",
8082                                    sizeof(struct ixgbe_l2_tn_filter),
8083                                    0);
8084                 if (!node)
8085                         return -ENOMEM;
8086
8087                 rte_memcpy(&node->key,
8088                                  &key,
8089                                  sizeof(struct ixgbe_l2_tn_key));
8090                 node->pool = l2_tunnel->pool;
8091                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
8092                 if (ret < 0) {
8093                         rte_free(node);
8094                         return ret;
8095                 }
8096         }
8097
8098         switch (l2_tunnel->l2_tunnel_type) {
8099         case RTE_L2_TUNNEL_TYPE_E_TAG:
8100                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
8101                 break;
8102         default:
8103                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8104                 ret = -EINVAL;
8105                 break;
8106         }
8107
8108         if ((!restore) && (ret < 0))
8109                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8110
8111         return ret;
8112 }
8113
8114 /* Delete l2 tunnel filter */
8115 int
8116 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
8117                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
8118 {
8119         int ret;
8120         struct ixgbe_l2_tn_info *l2_tn_info =
8121                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8122         struct ixgbe_l2_tn_key key;
8123
8124         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8125         key.tn_id = l2_tunnel->tunnel_id;
8126         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8127         if (ret < 0)
8128                 return ret;
8129
8130         switch (l2_tunnel->l2_tunnel_type) {
8131         case RTE_L2_TUNNEL_TYPE_E_TAG:
8132                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
8133                 break;
8134         default:
8135                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8136                 ret = -EINVAL;
8137                 break;
8138         }
8139
8140         return ret;
8141 }
8142
8143 /**
8144  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8145  * @dev: pointer to rte_eth_dev structure
8146  * @filter_op:operation will be taken.
8147  * @arg: a pointer to specific structure corresponding to the filter_op
8148  */
8149 static int
8150 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8151                                   enum rte_filter_op filter_op,
8152                                   void *arg)
8153 {
8154         int ret;
8155
8156         if (filter_op == RTE_ETH_FILTER_NOP)
8157                 return 0;
8158
8159         if (arg == NULL) {
8160                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8161                             filter_op);
8162                 return -EINVAL;
8163         }
8164
8165         switch (filter_op) {
8166         case RTE_ETH_FILTER_ADD:
8167                 ret = ixgbe_dev_l2_tunnel_filter_add
8168                         (dev,
8169                          (struct rte_eth_l2_tunnel_conf *)arg,
8170                          FALSE);
8171                 break;
8172         case RTE_ETH_FILTER_DELETE:
8173                 ret = ixgbe_dev_l2_tunnel_filter_del
8174                         (dev,
8175                          (struct rte_eth_l2_tunnel_conf *)arg);
8176                 break;
8177         default:
8178                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8179                 ret = -EINVAL;
8180                 break;
8181         }
8182         return ret;
8183 }
8184
8185 static int
8186 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8187 {
8188         int ret = 0;
8189         uint32_t ctrl;
8190         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8191
8192         if (hw->mac.type != ixgbe_mac_X550 &&
8193             hw->mac.type != ixgbe_mac_X550EM_x &&
8194             hw->mac.type != ixgbe_mac_X550EM_a) {
8195                 return -ENOTSUP;
8196         }
8197
8198         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8199         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8200         if (en)
8201                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8202         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8203
8204         return ret;
8205 }
8206
8207 /* Enable l2 tunnel forwarding */
8208 static int
8209 ixgbe_dev_l2_tunnel_forwarding_enable
8210         (struct rte_eth_dev *dev,
8211          enum rte_eth_tunnel_type l2_tunnel_type)
8212 {
8213         struct ixgbe_l2_tn_info *l2_tn_info =
8214                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8215         int ret = 0;
8216
8217         switch (l2_tunnel_type) {
8218         case RTE_L2_TUNNEL_TYPE_E_TAG:
8219                 l2_tn_info->e_tag_fwd_en = TRUE;
8220                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8221                 break;
8222         default:
8223                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8224                 ret = -EINVAL;
8225                 break;
8226         }
8227
8228         return ret;
8229 }
8230
8231 /* Disable l2 tunnel forwarding */
8232 static int
8233 ixgbe_dev_l2_tunnel_forwarding_disable
8234         (struct rte_eth_dev *dev,
8235          enum rte_eth_tunnel_type l2_tunnel_type)
8236 {
8237         struct ixgbe_l2_tn_info *l2_tn_info =
8238                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8239         int ret = 0;
8240
8241         switch (l2_tunnel_type) {
8242         case RTE_L2_TUNNEL_TYPE_E_TAG:
8243                 l2_tn_info->e_tag_fwd_en = FALSE;
8244                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8245                 break;
8246         default:
8247                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8248                 ret = -EINVAL;
8249                 break;
8250         }
8251
8252         return ret;
8253 }
8254
8255 static int
8256 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8257                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
8258                              bool en)
8259 {
8260         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8261         int ret = 0;
8262         uint32_t vmtir, vmvir;
8263         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8264
8265         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8266                 PMD_DRV_LOG(ERR,
8267                             "VF id %u should be less than %u",
8268                             l2_tunnel->vf_id,
8269                             pci_dev->max_vfs);
8270                 return -EINVAL;
8271         }
8272
8273         if (hw->mac.type != ixgbe_mac_X550 &&
8274             hw->mac.type != ixgbe_mac_X550EM_x &&
8275             hw->mac.type != ixgbe_mac_X550EM_a) {
8276                 return -ENOTSUP;
8277         }
8278
8279         if (en)
8280                 vmtir = l2_tunnel->tunnel_id;
8281         else
8282                 vmtir = 0;
8283
8284         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8285
8286         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8287         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8288         if (en)
8289                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8290         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8291
8292         return ret;
8293 }
8294
8295 /* Enable l2 tunnel tag insertion */
8296 static int
8297 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8298                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8299 {
8300         int ret = 0;
8301
8302         switch (l2_tunnel->l2_tunnel_type) {
8303         case RTE_L2_TUNNEL_TYPE_E_TAG:
8304                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8305                 break;
8306         default:
8307                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8308                 ret = -EINVAL;
8309                 break;
8310         }
8311
8312         return ret;
8313 }
8314
8315 /* Disable l2 tunnel tag insertion */
8316 static int
8317 ixgbe_dev_l2_tunnel_insertion_disable
8318         (struct rte_eth_dev *dev,
8319          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8320 {
8321         int ret = 0;
8322
8323         switch (l2_tunnel->l2_tunnel_type) {
8324         case RTE_L2_TUNNEL_TYPE_E_TAG:
8325                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8326                 break;
8327         default:
8328                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8329                 ret = -EINVAL;
8330                 break;
8331         }
8332
8333         return ret;
8334 }
8335
8336 static int
8337 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8338                              bool en)
8339 {
8340         int ret = 0;
8341         uint32_t qde;
8342         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8343
8344         if (hw->mac.type != ixgbe_mac_X550 &&
8345             hw->mac.type != ixgbe_mac_X550EM_x &&
8346             hw->mac.type != ixgbe_mac_X550EM_a) {
8347                 return -ENOTSUP;
8348         }
8349
8350         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8351         if (en)
8352                 qde |= IXGBE_QDE_STRIP_TAG;
8353         else
8354                 qde &= ~IXGBE_QDE_STRIP_TAG;
8355         qde &= ~IXGBE_QDE_READ;
8356         qde |= IXGBE_QDE_WRITE;
8357         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8358
8359         return ret;
8360 }
8361
8362 /* Enable l2 tunnel tag stripping */
8363 static int
8364 ixgbe_dev_l2_tunnel_stripping_enable
8365         (struct rte_eth_dev *dev,
8366          enum rte_eth_tunnel_type l2_tunnel_type)
8367 {
8368         int ret = 0;
8369
8370         switch (l2_tunnel_type) {
8371         case RTE_L2_TUNNEL_TYPE_E_TAG:
8372                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8373                 break;
8374         default:
8375                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8376                 ret = -EINVAL;
8377                 break;
8378         }
8379
8380         return ret;
8381 }
8382
8383 /* Disable l2 tunnel tag stripping */
8384 static int
8385 ixgbe_dev_l2_tunnel_stripping_disable
8386         (struct rte_eth_dev *dev,
8387          enum rte_eth_tunnel_type l2_tunnel_type)
8388 {
8389         int ret = 0;
8390
8391         switch (l2_tunnel_type) {
8392         case RTE_L2_TUNNEL_TYPE_E_TAG:
8393                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8394                 break;
8395         default:
8396                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8397                 ret = -EINVAL;
8398                 break;
8399         }
8400
8401         return ret;
8402 }
8403
8404 /* Enable/disable l2 tunnel offload functions */
8405 static int
8406 ixgbe_dev_l2_tunnel_offload_set
8407         (struct rte_eth_dev *dev,
8408          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8409          uint32_t mask,
8410          uint8_t en)
8411 {
8412         int ret = 0;
8413
8414         if (l2_tunnel == NULL)
8415                 return -EINVAL;
8416
8417         ret = -EINVAL;
8418         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8419                 if (en)
8420                         ret = ixgbe_dev_l2_tunnel_enable(
8421                                 dev,
8422                                 l2_tunnel->l2_tunnel_type);
8423                 else
8424                         ret = ixgbe_dev_l2_tunnel_disable(
8425                                 dev,
8426                                 l2_tunnel->l2_tunnel_type);
8427         }
8428
8429         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8430                 if (en)
8431                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8432                                 dev,
8433                                 l2_tunnel);
8434                 else
8435                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8436                                 dev,
8437                                 l2_tunnel);
8438         }
8439
8440         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8441                 if (en)
8442                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8443                                 dev,
8444                                 l2_tunnel->l2_tunnel_type);
8445                 else
8446                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8447                                 dev,
8448                                 l2_tunnel->l2_tunnel_type);
8449         }
8450
8451         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8452                 if (en)
8453                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8454                                 dev,
8455                                 l2_tunnel->l2_tunnel_type);
8456                 else
8457                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8458                                 dev,
8459                                 l2_tunnel->l2_tunnel_type);
8460         }
8461
8462         return ret;
8463 }
8464
8465 static int
8466 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8467                         uint16_t port)
8468 {
8469         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8470         IXGBE_WRITE_FLUSH(hw);
8471
8472         return 0;
8473 }
8474
8475 /* There's only one register for VxLAN UDP port.
8476  * So, we cannot add several ports. Will update it.
8477  */
8478 static int
8479 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8480                      uint16_t port)
8481 {
8482         if (port == 0) {
8483                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8484                 return -EINVAL;
8485         }
8486
8487         return ixgbe_update_vxlan_port(hw, port);
8488 }
8489
8490 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8491  * UDP port, it must have a value.
8492  * So, will reset it to the original value 0.
8493  */
8494 static int
8495 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8496                      uint16_t port)
8497 {
8498         uint16_t cur_port;
8499
8500         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8501
8502         if (cur_port != port) {
8503                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8504                 return -EINVAL;
8505         }
8506
8507         return ixgbe_update_vxlan_port(hw, 0);
8508 }
8509
8510 /* Add UDP tunneling port */
8511 static int
8512 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8513                               struct rte_eth_udp_tunnel *udp_tunnel)
8514 {
8515         int ret = 0;
8516         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8517
8518         if (hw->mac.type != ixgbe_mac_X550 &&
8519             hw->mac.type != ixgbe_mac_X550EM_x &&
8520             hw->mac.type != ixgbe_mac_X550EM_a) {
8521                 return -ENOTSUP;
8522         }
8523
8524         if (udp_tunnel == NULL)
8525                 return -EINVAL;
8526
8527         switch (udp_tunnel->prot_type) {
8528         case RTE_TUNNEL_TYPE_VXLAN:
8529                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8530                 break;
8531
8532         case RTE_TUNNEL_TYPE_GENEVE:
8533         case RTE_TUNNEL_TYPE_TEREDO:
8534                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8535                 ret = -EINVAL;
8536                 break;
8537
8538         default:
8539                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8540                 ret = -EINVAL;
8541                 break;
8542         }
8543
8544         return ret;
8545 }
8546
8547 /* Remove UDP tunneling port */
8548 static int
8549 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8550                               struct rte_eth_udp_tunnel *udp_tunnel)
8551 {
8552         int ret = 0;
8553         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8554
8555         if (hw->mac.type != ixgbe_mac_X550 &&
8556             hw->mac.type != ixgbe_mac_X550EM_x &&
8557             hw->mac.type != ixgbe_mac_X550EM_a) {
8558                 return -ENOTSUP;
8559         }
8560
8561         if (udp_tunnel == NULL)
8562                 return -EINVAL;
8563
8564         switch (udp_tunnel->prot_type) {
8565         case RTE_TUNNEL_TYPE_VXLAN:
8566                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8567                 break;
8568         case RTE_TUNNEL_TYPE_GENEVE:
8569         case RTE_TUNNEL_TYPE_TEREDO:
8570                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8571                 ret = -EINVAL;
8572                 break;
8573         default:
8574                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8575                 ret = -EINVAL;
8576                 break;
8577         }
8578
8579         return ret;
8580 }
8581
8582 static int
8583 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8584 {
8585         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8586         int ret;
8587
8588         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8589         case IXGBE_SUCCESS:
8590                 ret = 0;
8591                 break;
8592         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8593                 ret = -ENOTSUP;
8594                 break;
8595         default:
8596                 ret = -EAGAIN;
8597                 break;
8598         }
8599
8600         return ret;
8601 }
8602
8603 static int
8604 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8605 {
8606         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8607         int ret;
8608
8609         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8610         case IXGBE_SUCCESS:
8611                 ret = 0;
8612                 break;
8613         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8614                 ret = -ENOTSUP;
8615                 break;
8616         default:
8617                 ret = -EAGAIN;
8618                 break;
8619         }
8620
8621         return ret;
8622 }
8623
8624 static int
8625 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8626 {
8627         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8628         int ret;
8629         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8630
8631         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8632         case IXGBE_SUCCESS:
8633                 ret = 0;
8634                 break;
8635         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8636                 ret = -ENOTSUP;
8637                 break;
8638         default:
8639                 ret = -EAGAIN;
8640                 break;
8641         }
8642
8643         return ret;
8644 }
8645
8646 static int
8647 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8648 {
8649         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8650         int ret;
8651
8652         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8653         case IXGBE_SUCCESS:
8654                 ret = 0;
8655                 break;
8656         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8657                 ret = -ENOTSUP;
8658                 break;
8659         default:
8660                 ret = -EAGAIN;
8661                 break;
8662         }
8663
8664         return ret;
8665 }
8666
8667 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8668 {
8669         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8670         u32 in_msg = 0;
8671
8672         /* peek the message first */
8673         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8674
8675         /* PF reset VF event */
8676         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8677                 /* dummy mbx read to ack pf */
8678                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8679                         return;
8680                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8681                                              NULL);
8682         }
8683 }
8684
8685 static int
8686 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8687 {
8688         uint32_t eicr;
8689         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8690         struct ixgbe_interrupt *intr =
8691                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8692         ixgbevf_intr_disable(dev);
8693
8694         /* read-on-clear nic registers here */
8695         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8696         intr->flags = 0;
8697
8698         /* only one misc vector supported - mailbox */
8699         eicr &= IXGBE_VTEICR_MASK;
8700         if (eicr == IXGBE_MISC_VEC_ID)
8701                 intr->flags |= IXGBE_FLAG_MAILBOX;
8702
8703         return 0;
8704 }
8705
8706 static int
8707 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8708 {
8709         struct ixgbe_interrupt *intr =
8710                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8711
8712         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8713                 ixgbevf_mbx_process(dev);
8714                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8715         }
8716
8717         ixgbevf_intr_enable(dev);
8718
8719         return 0;
8720 }
8721
8722 static void
8723 ixgbevf_dev_interrupt_handler(void *param)
8724 {
8725         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8726
8727         ixgbevf_dev_interrupt_get_status(dev);
8728         ixgbevf_dev_interrupt_action(dev);
8729 }
8730
8731 /**
8732  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8733  *  @hw: pointer to hardware structure
8734  *
8735  *  Stops the transmit data path and waits for the HW to internally empty
8736  *  the Tx security block
8737  **/
8738 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8739 {
8740 #define IXGBE_MAX_SECTX_POLL 40
8741
8742         int i;
8743         int sectxreg;
8744
8745         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8746         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8747         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8748         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8749                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8750                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8751                         break;
8752                 /* Use interrupt-safe sleep just in case */
8753                 usec_delay(1000);
8754         }
8755
8756         /* For informational purposes only */
8757         if (i >= IXGBE_MAX_SECTX_POLL)
8758                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8759                          "path fully disabled.  Continuing with init.");
8760
8761         return IXGBE_SUCCESS;
8762 }
8763
8764 /**
8765  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8766  *  @hw: pointer to hardware structure
8767  *
8768  *  Enables the transmit data path.
8769  **/
8770 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8771 {
8772         uint32_t sectxreg;
8773
8774         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8775         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8776         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8777         IXGBE_WRITE_FLUSH(hw);
8778
8779         return IXGBE_SUCCESS;
8780 }
8781
8782 /* restore n-tuple filter */
8783 static inline void
8784 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8785 {
8786         struct ixgbe_filter_info *filter_info =
8787                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8788         struct ixgbe_5tuple_filter *node;
8789
8790         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8791                 ixgbe_inject_5tuple_filter(dev, node);
8792         }
8793 }
8794
8795 /* restore ethernet type filter */
8796 static inline void
8797 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8798 {
8799         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8800         struct ixgbe_filter_info *filter_info =
8801                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8802         int i;
8803
8804         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8805                 if (filter_info->ethertype_mask & (1 << i)) {
8806                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8807                                         filter_info->ethertype_filters[i].etqf);
8808                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8809                                         filter_info->ethertype_filters[i].etqs);
8810                         IXGBE_WRITE_FLUSH(hw);
8811                 }
8812         }
8813 }
8814
8815 /* restore SYN filter */
8816 static inline void
8817 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8818 {
8819         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8820         struct ixgbe_filter_info *filter_info =
8821                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8822         uint32_t synqf;
8823
8824         synqf = filter_info->syn_info;
8825
8826         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8827                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8828                 IXGBE_WRITE_FLUSH(hw);
8829         }
8830 }
8831
8832 /* restore L2 tunnel filter */
8833 static inline void
8834 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8835 {
8836         struct ixgbe_l2_tn_info *l2_tn_info =
8837                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8838         struct ixgbe_l2_tn_filter *node;
8839         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8840
8841         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8842                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8843                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8844                 l2_tn_conf.pool           = node->pool;
8845                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8846         }
8847 }
8848
8849 /* restore rss filter */
8850 static inline void
8851 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8852 {
8853         struct ixgbe_filter_info *filter_info =
8854                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8855
8856         if (filter_info->rss_info.conf.queue_num)
8857                 ixgbe_config_rss_filter(dev,
8858                         &filter_info->rss_info, TRUE);
8859 }
8860
8861 static int
8862 ixgbe_filter_restore(struct rte_eth_dev *dev)
8863 {
8864         ixgbe_ntuple_filter_restore(dev);
8865         ixgbe_ethertype_filter_restore(dev);
8866         ixgbe_syn_filter_restore(dev);
8867         ixgbe_fdir_filter_restore(dev);
8868         ixgbe_l2_tn_filter_restore(dev);
8869         ixgbe_rss_filter_restore(dev);
8870
8871         return 0;
8872 }
8873
8874 static void
8875 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8876 {
8877         struct ixgbe_l2_tn_info *l2_tn_info =
8878                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8879         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8880
8881         if (l2_tn_info->e_tag_en)
8882                 (void)ixgbe_e_tag_enable(hw);
8883
8884         if (l2_tn_info->e_tag_fwd_en)
8885                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8886
8887         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8888 }
8889
8890 /* remove all the n-tuple filters */
8891 void
8892 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8893 {
8894         struct ixgbe_filter_info *filter_info =
8895                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8896         struct ixgbe_5tuple_filter *p_5tuple;
8897
8898         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8899                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8900 }
8901
8902 /* remove all the ether type filters */
8903 void
8904 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8905 {
8906         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8907         struct ixgbe_filter_info *filter_info =
8908                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8909         int i;
8910
8911         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8912                 if (filter_info->ethertype_mask & (1 << i) &&
8913                     !filter_info->ethertype_filters[i].conf) {
8914                         (void)ixgbe_ethertype_filter_remove(filter_info,
8915                                                             (uint8_t)i);
8916                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8917                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8918                         IXGBE_WRITE_FLUSH(hw);
8919                 }
8920         }
8921 }
8922
8923 /* remove the SYN filter */
8924 void
8925 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8926 {
8927         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8928         struct ixgbe_filter_info *filter_info =
8929                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8930
8931         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8932                 filter_info->syn_info = 0;
8933
8934                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8935                 IXGBE_WRITE_FLUSH(hw);
8936         }
8937 }
8938
8939 /* remove all the L2 tunnel filters */
8940 int
8941 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8942 {
8943         struct ixgbe_l2_tn_info *l2_tn_info =
8944                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8945         struct ixgbe_l2_tn_filter *l2_tn_filter;
8946         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8947         int ret = 0;
8948
8949         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8950                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8951                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8952                 l2_tn_conf.pool           = l2_tn_filter->pool;
8953                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8954                 if (ret < 0)
8955                         return ret;
8956         }
8957
8958         return 0;
8959 }
8960
8961 void
8962 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8963                                 struct ixgbe_macsec_setting *macsec_setting)
8964 {
8965         struct ixgbe_macsec_setting *macsec =
8966                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8967
8968         macsec->offload_en = macsec_setting->offload_en;
8969         macsec->encrypt_en = macsec_setting->encrypt_en;
8970         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8971 }
8972
8973 void
8974 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8975 {
8976         struct ixgbe_macsec_setting *macsec =
8977                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8978
8979         macsec->offload_en = 0;
8980         macsec->encrypt_en = 0;
8981         macsec->replayprotect_en = 0;
8982 }
8983
8984 void
8985 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8986                                 struct ixgbe_macsec_setting *macsec_setting)
8987 {
8988         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8989         uint32_t ctrl;
8990         uint8_t en = macsec_setting->encrypt_en;
8991         uint8_t rp = macsec_setting->replayprotect_en;
8992
8993         /**
8994          * Workaround:
8995          * As no ixgbe_disable_sec_rx_path equivalent is
8996          * implemented for tx in the base code, and we are
8997          * not allowed to modify the base code in DPDK, so
8998          * just call the hand-written one directly for now.
8999          * The hardware support has been checked by
9000          * ixgbe_disable_sec_rx_path().
9001          */
9002         ixgbe_disable_sec_tx_path_generic(hw);
9003
9004         /* Enable Ethernet CRC (required by MACsec offload) */
9005         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
9006         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
9007         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
9008
9009         /* Enable the TX and RX crypto engines */
9010         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9011         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
9012         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9013
9014         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9015         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
9016         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9017
9018         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
9019         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
9020         ctrl |= 0x3;
9021         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
9022
9023         /* Enable SA lookup */
9024         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9025         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9026         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
9027                      IXGBE_LSECTXCTRL_AUTH;
9028         ctrl |= IXGBE_LSECTXCTRL_AISCI;
9029         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9030         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9031         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9032
9033         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9034         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9035         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
9036         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
9037         if (rp)
9038                 ctrl |= IXGBE_LSECRXCTRL_RP;
9039         else
9040                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
9041         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9042
9043         /* Start the data paths */
9044         ixgbe_enable_sec_rx_path(hw);
9045         /**
9046          * Workaround:
9047          * As no ixgbe_enable_sec_rx_path equivalent is
9048          * implemented for tx in the base code, and we are
9049          * not allowed to modify the base code in DPDK, so
9050          * just call the hand-written one directly for now.
9051          */
9052         ixgbe_enable_sec_tx_path_generic(hw);
9053 }
9054
9055 void
9056 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
9057 {
9058         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9059         uint32_t ctrl;
9060
9061         /**
9062          * Workaround:
9063          * As no ixgbe_disable_sec_rx_path equivalent is
9064          * implemented for tx in the base code, and we are
9065          * not allowed to modify the base code in DPDK, so
9066          * just call the hand-written one directly for now.
9067          * The hardware support has been checked by
9068          * ixgbe_disable_sec_rx_path().
9069          */
9070         ixgbe_disable_sec_tx_path_generic(hw);
9071
9072         /* Disable the TX and RX crypto engines */
9073         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9074         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
9075         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9076
9077         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9078         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
9079         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9080
9081         /* Disable SA lookup */
9082         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9083         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9084         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
9085         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9086
9087         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9088         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9089         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
9090         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9091
9092         /* Start the data paths */
9093         ixgbe_enable_sec_rx_path(hw);
9094         /**
9095          * Workaround:
9096          * As no ixgbe_enable_sec_rx_path equivalent is
9097          * implemented for tx in the base code, and we are
9098          * not allowed to modify the base code in DPDK, so
9099          * just call the hand-written one directly for now.
9100          */
9101         ixgbe_enable_sec_tx_path_generic(hw);
9102 }
9103
9104 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
9105 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
9106 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
9107 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
9108 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
9109 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
9110 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
9111                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
9112
9113 RTE_LOG_REGISTER(ixgbe_logtype_init, pmd.net.ixgbe.init, NOTICE);
9114 RTE_LOG_REGISTER(ixgbe_logtype_driver, pmd.net.ixgbe.driver, NOTICE);
9115
9116 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
9117 RTE_LOG_REGISTER(ixgbe_logtype_rx, pmd.net.ixgbe.rx, DEBUG);
9118 #endif
9119 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
9120 RTE_LOG_REGISTER(ixgbe_logtype_tx, pmd.net.ixgbe.tx, DEBUG);
9121 #endif
9122 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
9123 RTE_LOG_REGISTER(ixgbe_logtype_tx_free, pmd.net.ixgbe.tx_free, DEBUG);
9124 #endif