drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define NSEC_PER_SEC             1000000000L
 130 #define IXGBE_INCVAL_10GB        0x66666666
 131 #define IXGBE_INCVAL_1GB         0x40000000
 132 #define IXGBE_INCVAL_100         0x50000000
 133 #define IXGBE_INCVAL_SHIFT_10GB  28
 134 #define IXGBE_INCVAL_SHIFT_1GB   24
 135 #define IXGBE_INCVAL_SHIFT_100   21
 136 #define IXGBE_INCVAL_SHIFT_82599 7
 137 #define IXGBE_INCPER_SHIFT_82599 24
 138
 139 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 143 #define DEFAULT_ETAG_ETYPE                     0x893f
 144 #define IXGBE_ETAG_ETYPE                       0x00005084
 145 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 146 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 147 #define IXGBE_RAH_ADTYPE                       0x40000000
 148 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 149 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 152 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 153
 154 enum ixgbevf_xcast_modes {
 155         IXGBEVF_XCAST_MODE_NONE = 0,
 156         IXGBEVF_XCAST_MODE_MULTI,
 157         IXGBEVF_XCAST_MODE_ALLMULTI,
 158 };
 159
 160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 162 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 163 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 164 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 165 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 166 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 167 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 168 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 169 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 171 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 172 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 173                                 int wait_to_complete);
 174 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 175                                 struct rte_eth_stats *stats);
 176 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 177                                 struct rte_eth_xstats *xstats, unsigned n);
 178 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 179                                   struct rte_eth_xstats *xstats, unsigned n);
 180 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 181 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 182 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 183                                              uint16_t queue_id,
 184                                              uint8_t stat_idx,
 185                                              uint8_t is_rx);
 186 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 187                                struct rte_eth_dev_info *dev_info);
 188 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                  struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 202 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 203 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 204 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 205 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 206
 207 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 208 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 209 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 210                                struct rte_eth_fc_conf *fc_conf);
 211 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 212                                struct rte_eth_fc_conf *fc_conf);
 213 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 214                 struct rte_eth_pfc_conf *pfc_conf);
 215 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 216                         struct rte_eth_rss_reta_entry64 *reta_conf,
 217                         uint16_t reta_size);
 218 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 222 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 223 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 224 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 226 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 227                 void *param);
 228 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 229 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 230                 uint32_t index, uint32_t pool);
 231 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 232 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 233                                            struct ether_addr *mac_addr);
 234 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 235
 236 /* For Virtual Function support */
 237 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 238 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 239 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 240 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 241 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 242 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 243 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 244 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 245 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 246                 struct rte_eth_stats *stats);
 247 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 248 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 249                 uint16_t vlan_id, int on);
 250 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 251                 uint16_t queue, int on);
 252 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 253 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 254 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 255                                             uint16_t queue_id);
 256 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 257                                              uint16_t queue_id);
 258 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 259                                  uint8_t queue, uint8_t msix_vector);
 260 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 261 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 262 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 263
 264 /* For Eth VMDQ APIs support */
 265 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 266                 ether_addr* mac_addr,uint8_t on);
 267 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 268 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 269                 uint16_t rx_mask, uint8_t on);
 270 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 271 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 272 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 273                 uint64_t pool_mask,uint8_t vlan_on);
 274 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 275                 struct rte_eth_mirror_conf *mirror_conf,
 276                 uint8_t rule_id, uint8_t on);
 277 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 278                 uint8_t rule_id);
 279 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 280                                           uint16_t queue_id);
 281 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 282                                            uint16_t queue_id);
 283 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 284                                uint8_t queue, uint8_t msix_vector);
 285 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 286
 287 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 288                 uint16_t queue_idx, uint16_t tx_rate);
 289 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 290                 uint16_t tx_rate, uint64_t q_msk);
 291
 292 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 293                                  struct ether_addr *mac_addr,
 294                                  uint32_t index, uint32_t pool);
 295 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 296 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 297                                              struct ether_addr *mac_addr);
 298 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 299                         struct rte_eth_syn_filter *filter,
 300                         bool add);
 301 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 302                         struct rte_eth_syn_filter *filter);
 303 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 304                         enum rte_filter_op filter_op,
 305                         void *arg);
 306 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 307                         struct ixgbe_5tuple_filter *filter);
 308 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 309                         struct ixgbe_5tuple_filter *filter);
 310 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 311                         struct rte_eth_ntuple_filter *filter,
 312                         bool add);
 313 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 314                                 enum rte_filter_op filter_op,
 315                                 void *arg);
 316 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 317                         struct rte_eth_ntuple_filter *filter);
 318 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 319                         struct rte_eth_ethertype_filter *filter,
 320                         bool add);
 321 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 322                                 enum rte_filter_op filter_op,
 323                                 void *arg);
 324 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 325                         struct rte_eth_ethertype_filter *filter);
 326 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 327                      enum rte_filter_type filter_type,
 328                      enum rte_filter_op filter_op,
 329                      void *arg);
 330 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 331
 332 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 333                                       struct ether_addr *mc_addr_set,
 334                                       uint32_t nb_mc_addr);
 335 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 336                                    struct rte_eth_dcb_info *dcb_info);
 337
 338 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 339 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 340                             struct rte_dev_reg_info *regs);
 341 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 342 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 343                                 struct rte_dev_eeprom_info *eeprom);
 344 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 345                                 struct rte_dev_eeprom_info *eeprom);
 346
 347 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 348 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 349                                 struct rte_dev_reg_info *regs);
 350
 351 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 352 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 354                                             struct timespec *timestamp,
 355                                             uint32_t flags);
 356 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 357                                             struct timespec *timestamp);
 358 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 359 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 360                                    struct timespec *timestamp);
 361 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 362                                    const struct timespec *timestamp);
 363
 364 static int ixgbe_dev_l2_tunnel_eth_type_conf
 365         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 366 static int ixgbe_dev_l2_tunnel_offload_set
 367         (struct rte_eth_dev *dev,
 368          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 369          uint32_t mask,
 370          uint8_t en);
 371 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 372                                              enum rte_filter_op filter_op,
 373                                              void *arg);
 374
 375 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 376                                          struct rte_eth_udp_tunnel *udp_tunnel);
 377 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379
 380 /*
 381  * Define VF Stats MACRO for Non "cleared on read" register
 382  */
 383 #define UPDATE_VF_STAT(reg, last, cur)                          \
 384 {                                                               \
 385         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 386         cur += (latest - last) & UINT_MAX;                      \
 387         last = latest;                                          \
 388 }
 389
 390 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 391 {                                                                \
 392         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 393         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 394         u64 latest = ((new_msb << 32) | new_lsb);                \
 395         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 396         last = latest;                                           \
 397 }
 398
 399 #define IXGBE_SET_HWSTRIP(h, q) do{\
 400                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 401                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 402                 (h)->bitmap[idx] |= 1 << bit;\
 403         } while (0)
 404
 405 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 406                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 407                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 408                 (h)->bitmap[idx] &= ~(1 << bit);\
 409         } while (0)
 410
 411 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 412                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 413                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 414                 (r) = (h)->bitmap[idx] >> bit & 1;\
 415         } while (0)
 416
 417 /*
 418  * The set of PCI devices this driver supports
 419  */
 420 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 421
 422 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 423 #include "rte_pci_dev_ids.h"
 424
 425 { .vendor_id = 0, /* sentinel */ },
 426 };
 427
 428
 429 /*
 430  * The set of PCI devices this driver supports (for 82599 VF)
 431  */
 432 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 433
 434 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 435 #include "rte_pci_dev_ids.h"
 436 { .vendor_id = 0, /* sentinel */ },
 437
 438 };
 439
 440 static const struct rte_eth_desc_lim rx_desc_lim = {
 441         .nb_max = IXGBE_MAX_RING_DESC,
 442         .nb_min = IXGBE_MIN_RING_DESC,
 443         .nb_align = IXGBE_RXD_ALIGN,
 444 };
 445
 446 static const struct rte_eth_desc_lim tx_desc_lim = {
 447         .nb_max = IXGBE_MAX_RING_DESC,
 448         .nb_min = IXGBE_MIN_RING_DESC,
 449         .nb_align = IXGBE_TXD_ALIGN,
 450 };
 451
 452 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 453         .dev_configure        = ixgbe_dev_configure,
 454         .dev_start            = ixgbe_dev_start,
 455         .dev_stop             = ixgbe_dev_stop,
 456         .dev_set_link_up    = ixgbe_dev_set_link_up,
 457         .dev_set_link_down  = ixgbe_dev_set_link_down,
 458         .dev_close            = ixgbe_dev_close,
 459         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 460         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 461         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 462         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 463         .link_update          = ixgbe_dev_link_update,
 464         .stats_get            = ixgbe_dev_stats_get,
 465         .xstats_get           = ixgbe_dev_xstats_get,
 466         .stats_reset          = ixgbe_dev_stats_reset,
 467         .xstats_reset         = ixgbe_dev_xstats_reset,
 468         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 469         .dev_infos_get        = ixgbe_dev_info_get,
 470         .mtu_set              = ixgbe_dev_mtu_set,
 471         .vlan_filter_set      = ixgbe_vlan_filter_set,
 472         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 473         .vlan_offload_set     = ixgbe_vlan_offload_set,
 474         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 475         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 476         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 477         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 478         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 479         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 480         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 481         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 482         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 483         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 484         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 485         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 486         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 487         .dev_led_on           = ixgbe_dev_led_on,
 488         .dev_led_off          = ixgbe_dev_led_off,
 489         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 490         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 491         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 492         .mac_addr_add         = ixgbe_add_rar,
 493         .mac_addr_remove      = ixgbe_remove_rar,
 494         .mac_addr_set         = ixgbe_set_default_mac_addr,
 495         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 496         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 497         .mirror_rule_set      = ixgbe_mirror_rule_set,
 498         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 499         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 500         .set_vf_rx            = ixgbe_set_pool_rx,
 501         .set_vf_tx            = ixgbe_set_pool_tx,
 502         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 503         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 504         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 505         .reta_update          = ixgbe_dev_rss_reta_update,
 506         .reta_query           = ixgbe_dev_rss_reta_query,
 507 #ifdef RTE_NIC_BYPASS
 508         .bypass_init          = ixgbe_bypass_init,
 509         .bypass_state_set     = ixgbe_bypass_state_store,
 510         .bypass_state_show    = ixgbe_bypass_state_show,
 511         .bypass_event_set     = ixgbe_bypass_event_store,
 512         .bypass_event_show    = ixgbe_bypass_event_show,
 513         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 514         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 515         .bypass_ver_show      = ixgbe_bypass_ver_show,
 516         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 517 #endif /* RTE_NIC_BYPASS */
 518         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 519         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 520         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 521         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 522         .rxq_info_get         = ixgbe_rxq_info_get,
 523         .txq_info_get         = ixgbe_txq_info_get,
 524         .timesync_enable      = ixgbe_timesync_enable,
 525         .timesync_disable     = ixgbe_timesync_disable,
 526         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 527         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 528         .get_reg_length       = ixgbe_get_reg_length,
 529         .get_reg              = ixgbe_get_regs,
 530         .get_eeprom_length    = ixgbe_get_eeprom_length,
 531         .get_eeprom           = ixgbe_get_eeprom,
 532         .set_eeprom           = ixgbe_set_eeprom,
 533         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 534         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 535         .timesync_read_time   = ixgbe_timesync_read_time,
 536         .timesync_write_time  = ixgbe_timesync_write_time,
 537         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 538         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 539         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 540         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 541 };
 542
 543 /*
 544  * dev_ops for virtual function, bare necessities for basic vf
 545  * operation have been implemented
 546  */
 547 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 548         .dev_configure        = ixgbevf_dev_configure,
 549         .dev_start            = ixgbevf_dev_start,
 550         .dev_stop             = ixgbevf_dev_stop,
 551         .link_update          = ixgbe_dev_link_update,
 552         .stats_get            = ixgbevf_dev_stats_get,
 553         .xstats_get           = ixgbevf_dev_xstats_get,
 554         .stats_reset          = ixgbevf_dev_stats_reset,
 555         .xstats_reset         = ixgbevf_dev_stats_reset,
 556         .dev_close            = ixgbevf_dev_close,
 557         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 558         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 559         .dev_infos_get        = ixgbevf_dev_info_get,
 560         .mtu_set              = ixgbevf_dev_set_mtu,
 561         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 562         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 563         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 564         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 565         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 566         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 567         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 568         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 569         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 570         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 571         .mac_addr_add         = ixgbevf_add_mac_addr,
 572         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 573         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 574         .rxq_info_get         = ixgbe_rxq_info_get,
 575         .txq_info_get         = ixgbe_txq_info_get,
 576         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 577         .get_reg_length       = ixgbevf_get_reg_length,
 578         .get_reg              = ixgbevf_get_regs,
 579         .reta_update          = ixgbe_dev_rss_reta_update,
 580         .reta_query           = ixgbe_dev_rss_reta_query,
 581         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 582         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 583 };
 584
 585 /* store statistics names and its offset in stats structure */
 586 struct rte_ixgbe_xstats_name_off {
 587         char name[RTE_ETH_XSTATS_NAME_SIZE];
 588         unsigned offset;
 589 };
 590
 591 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 592         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 593         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 594         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 595         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 596         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 597         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 598         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 599         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 600         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 601         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 602         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 603         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 604         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 605         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 606         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 607                 prc1023)},
 608         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 609                 prc1522)},
 610         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 611         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 612         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 613         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 614         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 615         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 616         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 617         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 618         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 619         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 620         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 621         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 622         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 623         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 624         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 625         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 626         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 627                 ptc1023)},
 628         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 629                 ptc1522)},
 630         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 631         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 632         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 633         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 634
 635         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 636                 fdirustat_add)},
 637         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 638                 fdirustat_remove)},
 639         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 640                 fdirfstat_fadd)},
 641         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 642                 fdirfstat_fremove)},
 643         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 644                 fdirmatch)},
 645         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 646                 fdirmiss)},
 647
 648         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 649         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 650         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 651                 fclast)},
 652         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 653         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 654         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 655         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 656         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 657                 fcoe_noddp)},
 658         {"rx_fcoe_no_direct_data_placement_ext_buff",
 659                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 660
 661         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 662                 lxontxc)},
 663         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 664                 lxonrxc)},
 665         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 666                 lxofftxc)},
 667         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 668                 lxoffrxc)},
 669         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 670 };
 671
 672 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 673                            sizeof(rte_ixgbe_stats_strings[0]))
 674
 675 /* Per-queue statistics */
 676 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 677         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 678         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 679         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 680         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 681 };
 682
 683 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 684                            sizeof(rte_ixgbe_rxq_strings[0]))
 685
 686 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 687         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 688         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 689         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 690                 pxon2offc)},
 691 };
 692
 693 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 694                            sizeof(rte_ixgbe_txq_strings[0]))
 695
 696 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 697         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 698 };
 699
 700 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 701                 sizeof(rte_ixgbevf_stats_strings[0]))
 702
 703 /**
 704  * Atomically reads the link status information from global
 705  * structure rte_eth_dev.
 706  *
 707  * @param dev
 708  *   - Pointer to the structure rte_eth_dev to read from.
 709  *   - Pointer to the buffer to be saved with the link status.
 710  *
 711  * @return
 712  *   - On success, zero.
 713  *   - On failure, negative value.
 714  */
 715 static inline int
 716 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 717                                 struct rte_eth_link *link)
 718 {
 719         struct rte_eth_link *dst = link;
 720         struct rte_eth_link *src = &(dev->data->dev_link);
 721
 722         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 723                                         *(uint64_t *)src) == 0)
 724                 return -1;
 725
 726         return 0;
 727 }
 728
 729 /**
 730  * Atomically writes the link status information into global
 731  * structure rte_eth_dev.
 732  *
 733  * @param dev
 734  *   - Pointer to the structure rte_eth_dev to read from.
 735  *   - Pointer to the buffer to be saved with the link status.
 736  *
 737  * @return
 738  *   - On success, zero.
 739  *   - On failure, negative value.
 740  */
 741 static inline int
 742 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 743                                 struct rte_eth_link *link)
 744 {
 745         struct rte_eth_link *dst = &(dev->data->dev_link);
 746         struct rte_eth_link *src = link;
 747
 748         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 749                                         *(uint64_t *)src) == 0)
 750                 return -1;
 751
 752         return 0;
 753 }
 754
 755 /*
 756  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 757  */
 758 static inline int
 759 ixgbe_is_sfp(struct ixgbe_hw *hw)
 760 {
 761         switch (hw->phy.type) {
 762         case ixgbe_phy_sfp_avago:
 763         case ixgbe_phy_sfp_ftl:
 764         case ixgbe_phy_sfp_intel:
 765         case ixgbe_phy_sfp_unknown:
 766         case ixgbe_phy_sfp_passive_tyco:
 767         case ixgbe_phy_sfp_passive_unknown:
 768                 return 1;
 769         default:
 770                 return 0;
 771         }
 772 }
 773
 774 static inline int32_t
 775 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 776 {
 777         uint32_t ctrl_ext;
 778         int32_t status;
 779
 780         status = ixgbe_reset_hw(hw);
 781
 782         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 783         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 784         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 785         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 786         IXGBE_WRITE_FLUSH(hw);
 787
 788         return status;
 789 }
 790
 791 static inline void
 792 ixgbe_enable_intr(struct rte_eth_dev *dev)
 793 {
 794         struct ixgbe_interrupt *intr =
 795                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 796         struct ixgbe_hw *hw =
 797                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 798
 799         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 800         IXGBE_WRITE_FLUSH(hw);
 801 }
 802
 803 /*
 804  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 805  */
 806 static void
 807 ixgbe_disable_intr(struct ixgbe_hw *hw)
 808 {
 809         PMD_INIT_FUNC_TRACE();
 810
 811         if (hw->mac.type == ixgbe_mac_82598EB) {
 812                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 813         } else {
 814                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 815                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 816                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 817         }
 818         IXGBE_WRITE_FLUSH(hw);
 819 }
 820
 821 /*
 822  * This function resets queue statistics mapping registers.
 823  * From Niantic datasheet, Initialization of Statistics section:
 824  * "...if software requires the queue counters, the RQSMR and TQSM registers
 825  * must be re-programmed following a device reset.
 826  */
 827 static void
 828 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 829 {
 830         uint32_t i;
 831
 832         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 833                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 834                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 835         }
 836 }
 837
 838
 839 static int
 840 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 841                                   uint16_t queue_id,
 842                                   uint8_t stat_idx,
 843                                   uint8_t is_rx)
 844 {
 845 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 846 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 847 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 848
 849         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 850         struct ixgbe_stat_mapping_registers *stat_mappings =
 851                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 852         uint32_t qsmr_mask = 0;
 853         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 854         uint32_t q_map;
 855         uint8_t n, offset;
 856
 857         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 858                 (hw->mac.type != ixgbe_mac_X540) &&
 859                 (hw->mac.type != ixgbe_mac_X550) &&
 860                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 861                 (hw->mac.type != ixgbe_mac_X550EM_a))
 862                 return -ENOSYS;
 863
 864         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 865                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 866                      queue_id, stat_idx);
 867
 868         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 869         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 870                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 871                 return -EIO;
 872         }
 873         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 874
 875         /* Now clear any previous stat_idx set */
 876         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 877         if (!is_rx)
 878                 stat_mappings->tqsm[n] &= ~clearing_mask;
 879         else
 880                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 881
 882         q_map = (uint32_t)stat_idx;
 883         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 884         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 885         if (!is_rx)
 886                 stat_mappings->tqsm[n] |= qsmr_mask;
 887         else
 888                 stat_mappings->rqsmr[n] |= qsmr_mask;
 889
 890         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 891                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 892                      queue_id, stat_idx);
 893         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 894                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 895
 896         /* Now write the mapping in the appropriate register */
 897         if (is_rx) {
 898                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 899                              stat_mappings->rqsmr[n], n);
 900                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 901         }
 902         else {
 903                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 904                              stat_mappings->tqsm[n], n);
 905                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 906         }
 907         return 0;
 908 }
 909
 910 static void
 911 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 912 {
 913         struct ixgbe_stat_mapping_registers *stat_mappings =
 914                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 915         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 916         int i;
 917
 918         /* write whatever was in stat mapping table to the NIC */
 919         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 920                 /* rx */
 921                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 922
 923                 /* tx */
 924                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 925         }
 926 }
 927
 928 static void
 929 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 930 {
 931         uint8_t i;
 932         struct ixgbe_dcb_tc_config *tc;
 933         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 934
 935         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 936         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 937         for (i = 0; i < dcb_max_tc; i++) {
 938                 tc = &dcb_config->tc_config[i];
 939                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 940                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 941                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 942                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 943                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 944                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 945                 tc->pfc = ixgbe_dcb_pfc_disabled;
 946         }
 947
 948         /* Initialize default user to priority mapping, UPx->TC0 */
 949         tc = &dcb_config->tc_config[0];
 950         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 951         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 952         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 953                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 954                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 955         }
 956         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 957         dcb_config->pfc_mode_enable = false;
 958         dcb_config->vt_mode = true;
 959         dcb_config->round_robin_enable = false;
 960         /* support all DCB capabilities in 82599 */
 961         dcb_config->support.capabilities = 0xFF;
 962
 963         /*we only support 4 Tcs for X540, X550 */
 964         if (hw->mac.type == ixgbe_mac_X540 ||
 965                 hw->mac.type == ixgbe_mac_X550 ||
 966                 hw->mac.type == ixgbe_mac_X550EM_x ||
 967                 hw->mac.type == ixgbe_mac_X550EM_a) {
 968                 dcb_config->num_tcs.pg_tcs = 4;
 969                 dcb_config->num_tcs.pfc_tcs = 4;
 970         }
 971 }
 972
 973 /*
 974  * Ensure that all locks are released before first NVM or PHY access
 975  */
 976 static void
 977 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 978 {
 979         uint16_t mask;
 980
 981         /*
 982          * Phy lock should not fail in this early stage. If this is the case,
 983          * it is due to an improper exit of the application.
 984          * So force the release of the faulty lock. Release of common lock
 985          * is done automatically by swfw_sync function.
 986          */
 987         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 988         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 989                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 990         }
 991         ixgbe_release_swfw_semaphore(hw, mask);
 992
 993         /*
 994          * These ones are more tricky since they are common to all ports; but
 995          * swfw_sync retries last long enough (1s) to be almost sure that if
 996          * lock can not be taken it is due to an improper lock of the
 997          * semaphore.
 998          */
 999         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1000         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1001                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1002         }
1003         ixgbe_release_swfw_semaphore(hw, mask);
1004 }
1005
1006 /*
1007  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1008  * It returns 0 on success.
1009  */
1010 static int
1011 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1012 {
1013         struct rte_pci_device *pci_dev;
1014         struct ixgbe_hw *hw =
1015                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1016         struct ixgbe_vfta * shadow_vfta =
1017                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1018         struct ixgbe_hwstrip *hwstrip =
1019                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1020         struct ixgbe_dcb_config *dcb_config =
1021                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1022         struct ixgbe_filter_info *filter_info =
1023                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1024         uint32_t ctrl_ext;
1025         uint16_t csum;
1026         int diag, i;
1027
1028         PMD_INIT_FUNC_TRACE();
1029
1030         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1031         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1032         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1033
1034         /*
1035          * For secondary processes, we don't initialise any further as primary
1036          * has already done this work. Only check we don't need a different
1037          * RX and TX function.
1038          */
1039         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1040                 struct ixgbe_tx_queue *txq;
1041                 /* TX queue function in primary, set by last queue initialized
1042                  * Tx queue may not initialized by primary process */
1043                 if (eth_dev->data->tx_queues) {
1044                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1045                         ixgbe_set_tx_function(eth_dev, txq);
1046                 } else {
1047                         /* Use default TX function if we get here */
1048                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1049                                              "Using default TX function.");
1050                 }
1051
1052                 ixgbe_set_rx_function(eth_dev);
1053
1054                 return 0;
1055         }
1056         pci_dev = eth_dev->pci_dev;
1057
1058         rte_eth_copy_pci_info(eth_dev, pci_dev);
1059
1060         /* Vendor and Device ID need to be set before init of shared code */
1061         hw->device_id = pci_dev->id.device_id;
1062         hw->vendor_id = pci_dev->id.vendor_id;
1063         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1064         hw->allow_unsupported_sfp = 1;
1065
1066         /* Initialize the shared code (base driver) */
1067 #ifdef RTE_NIC_BYPASS
1068         diag = ixgbe_bypass_init_shared_code(hw);
1069 #else
1070         diag = ixgbe_init_shared_code(hw);
1071 #endif /* RTE_NIC_BYPASS */
1072
1073         if (diag != IXGBE_SUCCESS) {
1074                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1075                 return -EIO;
1076         }
1077
1078         /* pick up the PCI bus settings for reporting later */
1079         ixgbe_get_bus_info(hw);
1080
1081         /* Unlock any pending hardware semaphore */
1082         ixgbe_swfw_lock_reset(hw);
1083
1084         /* Initialize DCB configuration*/
1085         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1086         ixgbe_dcb_init(hw,dcb_config);
1087         /* Get Hardware Flow Control setting */
1088         hw->fc.requested_mode = ixgbe_fc_full;
1089         hw->fc.current_mode = ixgbe_fc_full;
1090         hw->fc.pause_time = IXGBE_FC_PAUSE;
1091         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1092                 hw->fc.low_water[i] = IXGBE_FC_LO;
1093                 hw->fc.high_water[i] = IXGBE_FC_HI;
1094         }
1095         hw->fc.send_xon = 1;
1096
1097         /* Make sure we have a good EEPROM before we read from it */
1098         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1099         if (diag != IXGBE_SUCCESS) {
1100                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1101                 return -EIO;
1102         }
1103
1104 #ifdef RTE_NIC_BYPASS
1105         diag = ixgbe_bypass_init_hw(hw);
1106 #else
1107         diag = ixgbe_init_hw(hw);
1108 #endif /* RTE_NIC_BYPASS */
1109
1110         /*
1111          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1112          * is called too soon after the kernel driver unbinding/binding occurs.
1113          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1114          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1115          * also called. See ixgbe_identify_phy_82599(). The reason for the
1116          * failure is not known, and only occuts when virtualisation features
1117          * are disabled in the bios. A delay of 100ms  was found to be enough by
1118          * trial-and-error, and is doubled to be safe.
1119          */
1120         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1121                 rte_delay_ms(200);
1122                 diag = ixgbe_init_hw(hw);
1123         }
1124
1125         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1126                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1127                     "LOM.  Please be aware there may be issues associated "
1128                     "with your hardware.");
1129                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1130                     "please contact your Intel or hardware representative "
1131                     "who provided you with this hardware.");
1132         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1133                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1134         if (diag) {
1135                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1136                 return -EIO;
1137         }
1138
1139         /* Reset the hw statistics */
1140         ixgbe_dev_stats_reset(eth_dev);
1141
1142         /* disable interrupt */
1143         ixgbe_disable_intr(hw);
1144
1145         /* reset mappings for queue statistics hw counters*/
1146         ixgbe_reset_qstat_mappings(hw);
1147
1148         /* Allocate memory for storing MAC addresses */
1149         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1150                         hw->mac.num_rar_entries, 0);
1151         if (eth_dev->data->mac_addrs == NULL) {
1152                 PMD_INIT_LOG(ERR,
1153                         "Failed to allocate %u bytes needed to store "
1154                         "MAC addresses",
1155                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1156                 return -ENOMEM;
1157         }
1158         /* Copy the permanent MAC address */
1159         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1160                         &eth_dev->data->mac_addrs[0]);
1161
1162         /* Allocate memory for storing hash filter MAC addresses */
1163         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1164                         IXGBE_VMDQ_NUM_UC_MAC, 0);
1165         if (eth_dev->data->hash_mac_addrs == NULL) {
1166                 PMD_INIT_LOG(ERR,
1167                         "Failed to allocate %d bytes needed to store MAC addresses",
1168                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1169                 return -ENOMEM;
1170         }
1171
1172         /* initialize the vfta */
1173         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1174
1175         /* initialize the hw strip bitmap*/
1176         memset(hwstrip, 0, sizeof(*hwstrip));
1177
1178         /* initialize PF if max_vfs not zero */
1179         ixgbe_pf_host_init(eth_dev);
1180
1181         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1182         /* let hardware know driver is loaded */
1183         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1184         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1185         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1186         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1187         IXGBE_WRITE_FLUSH(hw);
1188
1189         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1190                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1191                              (int) hw->mac.type, (int) hw->phy.type,
1192                              (int) hw->phy.sfp_type);
1193         else
1194                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1195                              (int) hw->mac.type, (int) hw->phy.type);
1196
1197         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1198                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1199                         pci_dev->id.device_id);
1200
1201         rte_intr_callback_register(&pci_dev->intr_handle,
1202                                    ixgbe_dev_interrupt_handler,
1203                                    (void *)eth_dev);
1204
1205         /* enable uio/vfio intr/eventfd mapping */
1206         rte_intr_enable(&pci_dev->intr_handle);
1207
1208         /* enable support intr */
1209         ixgbe_enable_intr(eth_dev);
1210
1211         /* initialize 5tuple filter list */
1212         TAILQ_INIT(&filter_info->fivetuple_list);
1213         memset(filter_info->fivetuple_mask, 0,
1214                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1215
1216         return 0;
1217 }
1218
1219 static int
1220 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1221 {
1222         struct rte_pci_device *pci_dev;
1223         struct ixgbe_hw *hw;
1224
1225         PMD_INIT_FUNC_TRACE();
1226
1227         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1228                 return -EPERM;
1229
1230         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1231         pci_dev = eth_dev->pci_dev;
1232
1233         if (hw->adapter_stopped == 0)
1234                 ixgbe_dev_close(eth_dev);
1235
1236         eth_dev->dev_ops = NULL;
1237         eth_dev->rx_pkt_burst = NULL;
1238         eth_dev->tx_pkt_burst = NULL;
1239
1240         /* Unlock any pending hardware semaphore */
1241         ixgbe_swfw_lock_reset(hw);
1242
1243         /* disable uio intr before callback unregister */
1244         rte_intr_disable(&(pci_dev->intr_handle));
1245         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1246                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1247
1248         /* uninitialize PF if max_vfs not zero */
1249         ixgbe_pf_host_uninit(eth_dev);
1250
1251         rte_free(eth_dev->data->mac_addrs);
1252         eth_dev->data->mac_addrs = NULL;
1253
1254         rte_free(eth_dev->data->hash_mac_addrs);
1255         eth_dev->data->hash_mac_addrs = NULL;
1256
1257         return 0;
1258 }
1259
1260 /*
1261  * Negotiate mailbox API version with the PF.
1262  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1263  * Then we try to negotiate starting with the most recent one.
1264  * If all negotiation attempts fail, then we will proceed with
1265  * the default one (ixgbe_mbox_api_10).
1266  */
1267 static void
1268 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1269 {
1270         int32_t i;
1271
1272         /* start with highest supported, proceed down */
1273         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1274                 ixgbe_mbox_api_12,
1275                 ixgbe_mbox_api_11,
1276                 ixgbe_mbox_api_10,
1277         };
1278
1279         for (i = 0;
1280                         i != RTE_DIM(sup_ver) &&
1281                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1282                         i++)
1283                 ;
1284 }
1285
1286 static void
1287 generate_random_mac_addr(struct ether_addr *mac_addr)
1288 {
1289         uint64_t random;
1290
1291         /* Set Organizationally Unique Identifier (OUI) prefix. */
1292         mac_addr->addr_bytes[0] = 0x00;
1293         mac_addr->addr_bytes[1] = 0x09;
1294         mac_addr->addr_bytes[2] = 0xC0;
1295         /* Force indication of locally assigned MAC address. */
1296         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1297         /* Generate the last 3 bytes of the MAC address with a random number. */
1298         random = rte_rand();
1299         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1300 }
1301
1302 /*
1303  * Virtual Function device init
1304  */
1305 static int
1306 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1307 {
1308         int diag;
1309         uint32_t tc, tcs;
1310         struct rte_pci_device *pci_dev;
1311         struct ixgbe_hw *hw =
1312                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1313         struct ixgbe_vfta * shadow_vfta =
1314                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1315         struct ixgbe_hwstrip *hwstrip =
1316                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1317         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1318
1319         PMD_INIT_FUNC_TRACE();
1320
1321         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1322         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1323         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1324
1325         /* for secondary processes, we don't initialise any further as primary
1326          * has already done this work. Only check we don't need a different
1327          * RX function */
1328         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1329                 struct ixgbe_tx_queue *txq;
1330                 /* TX queue function in primary, set by last queue initialized
1331                  * Tx queue may not initialized by primary process
1332                  */
1333                 if (eth_dev->data->tx_queues) {
1334                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1335                         ixgbe_set_tx_function(eth_dev, txq);
1336                 } else {
1337                         /* Use default TX function if we get here */
1338                         PMD_INIT_LOG(NOTICE,
1339                                 "No TX queues configured yet. Using default TX function.");
1340                 }
1341
1342                 ixgbe_set_rx_function(eth_dev);
1343
1344                 return 0;
1345         }
1346
1347         pci_dev = eth_dev->pci_dev;
1348
1349         rte_eth_copy_pci_info(eth_dev, pci_dev);
1350
1351         hw->device_id = pci_dev->id.device_id;
1352         hw->vendor_id = pci_dev->id.vendor_id;
1353         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1354
1355         /* initialize the vfta */
1356         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1357
1358         /* initialize the hw strip bitmap*/
1359         memset(hwstrip, 0, sizeof(*hwstrip));
1360
1361         /* Initialize the shared code (base driver) */
1362         diag = ixgbe_init_shared_code(hw);
1363         if (diag != IXGBE_SUCCESS) {
1364                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1365                 return -EIO;
1366         }
1367
1368         /* init_mailbox_params */
1369         hw->mbx.ops.init_params(hw);
1370
1371         /* Reset the hw statistics */
1372         ixgbevf_dev_stats_reset(eth_dev);
1373
1374         /* Disable the interrupts for VF */
1375         ixgbevf_intr_disable(hw);
1376
1377         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1378         diag = hw->mac.ops.reset_hw(hw);
1379
1380         /*
1381          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1382          * the underlying PF driver has not assigned a MAC address to the VF.
1383          * In this case, assign a random MAC address.
1384          */
1385         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1386                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1387                 return diag;
1388         }
1389
1390         /* negotiate mailbox API version to use with the PF. */
1391         ixgbevf_negotiate_api(hw);
1392
1393         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1394         ixgbevf_get_queues(hw, &tcs, &tc);
1395
1396         /* Allocate memory for storing MAC addresses */
1397         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1398                         hw->mac.num_rar_entries, 0);
1399         if (eth_dev->data->mac_addrs == NULL) {
1400                 PMD_INIT_LOG(ERR,
1401                         "Failed to allocate %u bytes needed to store "
1402                         "MAC addresses",
1403                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1404                 return -ENOMEM;
1405         }
1406
1407         /* Generate a random MAC address, if none was assigned by PF. */
1408         if (is_zero_ether_addr(perm_addr)) {
1409                 generate_random_mac_addr(perm_addr);
1410                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1411                 if (diag) {
1412                         rte_free(eth_dev->data->mac_addrs);
1413                         eth_dev->data->mac_addrs = NULL;
1414                         return diag;
1415                 }
1416                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1417                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1418                              "%02x:%02x:%02x:%02x:%02x:%02x",
1419                              perm_addr->addr_bytes[0],
1420                              perm_addr->addr_bytes[1],
1421                              perm_addr->addr_bytes[2],
1422                              perm_addr->addr_bytes[3],
1423                              perm_addr->addr_bytes[4],
1424                              perm_addr->addr_bytes[5]);
1425         }
1426
1427         /* Copy the permanent MAC address */
1428         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1429
1430         /* reset the hardware with the new settings */
1431         diag = hw->mac.ops.start_hw(hw);
1432         switch (diag) {
1433                 case  0:
1434                         break;
1435
1436                 default:
1437                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1438                         return -EIO;
1439         }
1440
1441         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1442                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1443                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1444
1445         return 0;
1446 }
1447
1448 /* Virtual Function device uninit */
1449
1450 static int
1451 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1452 {
1453         struct ixgbe_hw *hw;
1454         unsigned i;
1455
1456         PMD_INIT_FUNC_TRACE();
1457
1458         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1459                 return -EPERM;
1460
1461         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1462
1463         if (hw->adapter_stopped == 0)
1464                 ixgbevf_dev_close(eth_dev);
1465
1466         eth_dev->dev_ops = NULL;
1467         eth_dev->rx_pkt_burst = NULL;
1468         eth_dev->tx_pkt_burst = NULL;
1469
1470         /* Disable the interrupts for VF */
1471         ixgbevf_intr_disable(hw);
1472
1473         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1474                 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1475                 eth_dev->data->rx_queues[i] = NULL;
1476         }
1477         eth_dev->data->nb_rx_queues = 0;
1478
1479         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1480                 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1481                 eth_dev->data->tx_queues[i] = NULL;
1482         }
1483         eth_dev->data->nb_tx_queues = 0;
1484
1485         rte_free(eth_dev->data->mac_addrs);
1486         eth_dev->data->mac_addrs = NULL;
1487
1488         return 0;
1489 }
1490
1491 static struct eth_driver rte_ixgbe_pmd = {
1492         .pci_drv = {
1493                 .name = "rte_ixgbe_pmd",
1494                 .id_table = pci_id_ixgbe_map,
1495                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1496                         RTE_PCI_DRV_DETACHABLE,
1497         },
1498         .eth_dev_init = eth_ixgbe_dev_init,
1499         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1500         .dev_private_size = sizeof(struct ixgbe_adapter),
1501 };
1502
1503 /*
1504  * virtual function driver struct
1505  */
1506 static struct eth_driver rte_ixgbevf_pmd = {
1507         .pci_drv = {
1508                 .name = "rte_ixgbevf_pmd",
1509                 .id_table = pci_id_ixgbevf_map,
1510                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1511         },
1512         .eth_dev_init = eth_ixgbevf_dev_init,
1513         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1514         .dev_private_size = sizeof(struct ixgbe_adapter),
1515 };
1516
1517 /*
1518  * Driver initialization routine.
1519  * Invoked once at EAL init time.
1520  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1521  */
1522 static int
1523 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1524 {
1525         PMD_INIT_FUNC_TRACE();
1526
1527         rte_eth_driver_register(&rte_ixgbe_pmd);
1528         return 0;
1529 }
1530
1531 /*
1532  * VF Driver initialization routine.
1533  * Invoked one at EAL init time.
1534  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1535  */
1536 static int
1537 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1538 {
1539         PMD_INIT_FUNC_TRACE();
1540
1541         rte_eth_driver_register(&rte_ixgbevf_pmd);
1542         return 0;
1543 }
1544
1545 static int
1546 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1547 {
1548         struct ixgbe_hw *hw =
1549                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1550         struct ixgbe_vfta * shadow_vfta =
1551                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1552         uint32_t vfta;
1553         uint32_t vid_idx;
1554         uint32_t vid_bit;
1555
1556         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1557         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1558         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1559         if (on)
1560                 vfta |= vid_bit;
1561         else
1562                 vfta &= ~vid_bit;
1563         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1564
1565         /* update local VFTA copy */
1566         shadow_vfta->vfta[vid_idx] = vfta;
1567
1568         return 0;
1569 }
1570
1571 static void
1572 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1573 {
1574         if (on)
1575                 ixgbe_vlan_hw_strip_enable(dev, queue);
1576         else
1577                 ixgbe_vlan_hw_strip_disable(dev, queue);
1578 }
1579
1580 static int
1581 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1582                     enum rte_vlan_type vlan_type,
1583                     uint16_t tpid)
1584 {
1585         struct ixgbe_hw *hw =
1586                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1587         int ret = 0;
1588
1589         switch (vlan_type) {
1590         case ETH_VLAN_TYPE_INNER:
1591                 /* Only the high 16-bits is valid */
1592                 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1593                 break;
1594         default:
1595                 ret = -EINVAL;
1596                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
1597                 break;
1598         }
1599
1600         return ret;
1601 }
1602
1603 void
1604 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1605 {
1606         struct ixgbe_hw *hw =
1607                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1608         uint32_t vlnctrl;
1609
1610         PMD_INIT_FUNC_TRACE();
1611
1612         /* Filter Table Disable */
1613         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1614         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1615
1616         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1617 }
1618
1619 void
1620 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1621 {
1622         struct ixgbe_hw *hw =
1623                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1624         struct ixgbe_vfta * shadow_vfta =
1625                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1626         uint32_t vlnctrl;
1627         uint16_t i;
1628
1629         PMD_INIT_FUNC_TRACE();
1630
1631         /* Filter Table Enable */
1632         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1633         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1634         vlnctrl |= IXGBE_VLNCTRL_VFE;
1635
1636         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1637
1638         /* write whatever is in local vfta copy */
1639         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1640                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1641 }
1642
1643 static void
1644 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1645 {
1646         struct ixgbe_hwstrip *hwstrip =
1647                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1648
1649         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1650                 return;
1651
1652         if (on)
1653                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1654         else
1655                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1656 }
1657
1658 static void
1659 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1660 {
1661         struct ixgbe_hw *hw =
1662                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1663         uint32_t ctrl;
1664
1665         PMD_INIT_FUNC_TRACE();
1666
1667         if (hw->mac.type == ixgbe_mac_82598EB) {
1668                 /* No queue level support */
1669                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1670                 return;
1671         }
1672         else {
1673                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1674                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1675                 ctrl &= ~IXGBE_RXDCTL_VME;
1676                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1677         }
1678         /* record those setting for HW strip per queue */
1679         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1680 }
1681
1682 static void
1683 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1684 {
1685         struct ixgbe_hw *hw =
1686                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1687         uint32_t ctrl;
1688
1689         PMD_INIT_FUNC_TRACE();
1690
1691         if (hw->mac.type == ixgbe_mac_82598EB) {
1692                 /* No queue level supported */
1693                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1694                 return;
1695         }
1696         else {
1697                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1698                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1699                 ctrl |= IXGBE_RXDCTL_VME;
1700                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1701         }
1702         /* record those setting for HW strip per queue */
1703         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1704 }
1705
1706 void
1707 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1708 {
1709         struct ixgbe_hw *hw =
1710                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1711         uint32_t ctrl;
1712         uint16_t i;
1713
1714         PMD_INIT_FUNC_TRACE();
1715
1716         if (hw->mac.type == ixgbe_mac_82598EB) {
1717                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1718                 ctrl &= ~IXGBE_VLNCTRL_VME;
1719                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1720         }
1721         else {
1722                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1723                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1724                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1725                         ctrl &= ~IXGBE_RXDCTL_VME;
1726                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1727
1728                         /* record those setting for HW strip per queue */
1729                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1730                 }
1731         }
1732 }
1733
1734 void
1735 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1736 {
1737         struct ixgbe_hw *hw =
1738                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1739         uint32_t ctrl;
1740         uint16_t i;
1741
1742         PMD_INIT_FUNC_TRACE();
1743
1744         if (hw->mac.type == ixgbe_mac_82598EB) {
1745                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1746                 ctrl |= IXGBE_VLNCTRL_VME;
1747                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1748         }
1749         else {
1750                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1751                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1752                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1753                         ctrl |= IXGBE_RXDCTL_VME;
1754                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1755
1756                         /* record those setting for HW strip per queue */
1757                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1758                 }
1759         }
1760 }
1761
1762 static void
1763 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1764 {
1765         struct ixgbe_hw *hw =
1766                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1767         uint32_t ctrl;
1768
1769         PMD_INIT_FUNC_TRACE();
1770
1771         /* DMATXCTRL: Geric Double VLAN Disable */
1772         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1773         ctrl &= ~IXGBE_DMATXCTL_GDV;
1774         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1775
1776         /* CTRL_EXT: Global Double VLAN Disable */
1777         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1778         ctrl &= ~IXGBE_EXTENDED_VLAN;
1779         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1780
1781 }
1782
1783 static void
1784 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1785 {
1786         struct ixgbe_hw *hw =
1787                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1788         uint32_t ctrl;
1789
1790         PMD_INIT_FUNC_TRACE();
1791
1792         /* DMATXCTRL: Geric Double VLAN Enable */
1793         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1794         ctrl |= IXGBE_DMATXCTL_GDV;
1795         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1796
1797         /* CTRL_EXT: Global Double VLAN Enable */
1798         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1799         ctrl |= IXGBE_EXTENDED_VLAN;
1800         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1801
1802         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1803         if (hw->mac.type == ixgbe_mac_X550 ||
1804             hw->mac.type == ixgbe_mac_X550EM_x) {
1805                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1806                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1807                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1808         }
1809
1810         /*
1811          * VET EXT field in the EXVET register = 0x8100 by default
1812          * So no need to change. Same to VT field of DMATXCTL register
1813          */
1814 }
1815
1816 static void
1817 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1818 {
1819         if (mask & ETH_VLAN_STRIP_MASK) {
1820                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1821                         ixgbe_vlan_hw_strip_enable_all(dev);
1822                 else
1823                         ixgbe_vlan_hw_strip_disable_all(dev);
1824         }
1825
1826         if (mask & ETH_VLAN_FILTER_MASK) {
1827                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1828                         ixgbe_vlan_hw_filter_enable(dev);
1829                 else
1830                         ixgbe_vlan_hw_filter_disable(dev);
1831         }
1832
1833         if (mask & ETH_VLAN_EXTEND_MASK) {
1834                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1835                         ixgbe_vlan_hw_extend_enable(dev);
1836                 else
1837                         ixgbe_vlan_hw_extend_disable(dev);
1838         }
1839 }
1840
1841 static void
1842 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1843 {
1844         struct ixgbe_hw *hw =
1845                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1846         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1847         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1848         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1849         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1850 }
1851
1852 static int
1853 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1854 {
1855         switch (nb_rx_q) {
1856         case 1:
1857         case 2:
1858                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1859                 break;
1860         case 4:
1861                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1862                 break;
1863         default:
1864                 return -EINVAL;
1865         }
1866
1867         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1868         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1869
1870         return 0;
1871 }
1872
1873 static int
1874 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1875 {
1876         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1877         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1878         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1879
1880         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1881                 /* check multi-queue mode */
1882                 switch (dev_conf->rxmode.mq_mode) {
1883                 case ETH_MQ_RX_VMDQ_DCB:
1884                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1885                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1886                         PMD_INIT_LOG(ERR, "SRIOV active,"
1887                                         " unsupported mq_mode rx %d.",
1888                                         dev_conf->rxmode.mq_mode);
1889                         return -EINVAL;
1890                 case ETH_MQ_RX_RSS:
1891                 case ETH_MQ_RX_VMDQ_RSS:
1892                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1893                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1894                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1895                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1896                                                 " invalid queue number"
1897                                                 " for VMDQ RSS, allowed"
1898                                                 " value are 1, 2 or 4.");
1899                                         return -EINVAL;
1900                                 }
1901                         break;
1902                 case ETH_MQ_RX_VMDQ_ONLY:
1903                 case ETH_MQ_RX_NONE:
1904                         /* if nothing mq mode configure, use default scheme */
1905                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1906                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1907                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1908                         break;
1909                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1910                         /* SRIOV only works in VMDq enable mode */
1911                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1912                                         " wrong mq_mode rx %d.",
1913                                         dev_conf->rxmode.mq_mode);
1914                         return -EINVAL;
1915                 }
1916
1917                 switch (dev_conf->txmode.mq_mode) {
1918                 case ETH_MQ_TX_VMDQ_DCB:
1919                         /* DCB VMDQ in SRIOV mode, not implement yet */
1920                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1921                                         " unsupported VMDQ mq_mode tx %d.",
1922                                         dev_conf->txmode.mq_mode);
1923                         return -EINVAL;
1924                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1925                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1926                         break;
1927                 }
1928
1929                 /* check valid queue number */
1930                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1931                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1932                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1933                                         " queue number must less equal to %d.",
1934                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1935                         return -EINVAL;
1936                 }
1937         } else {
1938                 /* check configuration for vmdb+dcb mode */
1939                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1940                         const struct rte_eth_vmdq_dcb_conf *conf;
1941
1942                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1943                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1944                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1945                                 return -EINVAL;
1946                         }
1947                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1948                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1949                                conf->nb_queue_pools == ETH_32_POOLS)) {
1950                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1951                                                 " nb_queue_pools must be %d or %d.",
1952                                                 ETH_16_POOLS, ETH_32_POOLS);
1953                                 return -EINVAL;
1954                         }
1955                 }
1956                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1957                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1958
1959                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1960                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1961                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1962                                 return -EINVAL;
1963                         }
1964                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1965                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1966                                conf->nb_queue_pools == ETH_32_POOLS)) {
1967                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1968                                                 " nb_queue_pools != %d and"
1969                                                 " nb_queue_pools != %d.",
1970                                                 ETH_16_POOLS, ETH_32_POOLS);
1971                                 return -EINVAL;
1972                         }
1973                 }
1974
1975                 /* For DCB mode check our configuration before we go further */
1976                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1977                         const struct rte_eth_dcb_rx_conf *conf;
1978
1979                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1980                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1981                                                  IXGBE_DCB_NB_QUEUES);
1982                                 return -EINVAL;
1983                         }
1984                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1985                         if (!(conf->nb_tcs == ETH_4_TCS ||
1986                                conf->nb_tcs == ETH_8_TCS)) {
1987                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1988                                                 " and nb_tcs != %d.",
1989                                                 ETH_4_TCS, ETH_8_TCS);
1990                                 return -EINVAL;
1991                         }
1992                 }
1993
1994                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1995                         const struct rte_eth_dcb_tx_conf *conf;
1996
1997                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1998                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1999                                                  IXGBE_DCB_NB_QUEUES);
2000                                 return -EINVAL;
2001                         }
2002                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2003                         if (!(conf->nb_tcs == ETH_4_TCS ||
2004                                conf->nb_tcs == ETH_8_TCS)) {
2005                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2006                                                 " and nb_tcs != %d.",
2007                                                 ETH_4_TCS, ETH_8_TCS);
2008                                 return -EINVAL;
2009                         }
2010                 }
2011         }
2012         return 0;
2013 }
2014
2015 static int
2016 ixgbe_dev_configure(struct rte_eth_dev *dev)
2017 {
2018         struct ixgbe_interrupt *intr =
2019                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2020         struct ixgbe_adapter *adapter =
2021                 (struct ixgbe_adapter *)dev->data->dev_private;
2022         int ret;
2023
2024         PMD_INIT_FUNC_TRACE();
2025         /* multipe queue mode checking */
2026         ret  = ixgbe_check_mq_mode(dev);
2027         if (ret != 0) {
2028                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2029                             ret);
2030                 return ret;
2031         }
2032
2033         /* set flag to update link status after init */
2034         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2035
2036         /*
2037          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2038          * allocation or vector Rx preconditions we will reset it.
2039          */
2040         adapter->rx_bulk_alloc_allowed = true;
2041         adapter->rx_vec_allowed = true;
2042
2043         return 0;
2044 }
2045
2046 static void
2047 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2048 {
2049         struct ixgbe_hw *hw =
2050                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2051         struct ixgbe_interrupt *intr =
2052                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2053         uint32_t gpie;
2054
2055         /* only set up it on X550EM_X */
2056         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2057                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2058                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2059                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2060                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2061                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2062         }
2063 }
2064
2065 /*
2066  * Configure device link speed and setup link.
2067  * It returns 0 on success.
2068  */
2069 static int
2070 ixgbe_dev_start(struct rte_eth_dev *dev)
2071 {
2072         struct ixgbe_hw *hw =
2073                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2074         struct ixgbe_vf_info *vfinfo =
2075                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2076         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2077         uint32_t intr_vector = 0;
2078         int err, link_up = 0, negotiate = 0;
2079         uint32_t speed = 0;
2080         int mask = 0;
2081         int status;
2082         uint16_t vf, idx;
2083
2084         PMD_INIT_FUNC_TRACE();
2085
2086         /* IXGBE devices don't support half duplex */
2087         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
2088                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
2089                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
2090                              dev->data->dev_conf.link_duplex,
2091                              dev->data->port_id);
2092                 return -EINVAL;
2093         }
2094
2095         /* disable uio/vfio intr/eventfd mapping */
2096         rte_intr_disable(intr_handle);
2097
2098         /* stop adapter */
2099         hw->adapter_stopped = 0;
2100         ixgbe_stop_adapter(hw);
2101
2102         /* reinitialize adapter
2103          * this calls reset and start */
2104         status = ixgbe_pf_reset_hw(hw);
2105         if (status != 0)
2106                 return -1;
2107         hw->mac.ops.start_hw(hw);
2108         hw->mac.get_link_status = true;
2109
2110         /* configure PF module if SRIOV enabled */
2111         ixgbe_pf_host_configure(dev);
2112
2113         ixgbe_dev_phy_intr_setup(dev);
2114
2115         /* check and configure queue intr-vector mapping */
2116         if ((rte_intr_cap_multiple(intr_handle) ||
2117              !RTE_ETH_DEV_SRIOV(dev).active) &&
2118             dev->data->dev_conf.intr_conf.rxq != 0) {
2119                 intr_vector = dev->data->nb_rx_queues;
2120                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2121                         return -1;
2122         }
2123
2124         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2125                 intr_handle->intr_vec =
2126                         rte_zmalloc("intr_vec",
2127                                     dev->data->nb_rx_queues * sizeof(int), 0);
2128                 if (intr_handle->intr_vec == NULL) {
2129                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2130                                      " intr_vec\n", dev->data->nb_rx_queues);
2131                         return -ENOMEM;
2132                 }
2133         }
2134
2135         /* confiugre msix for sleep until rx interrupt */
2136         ixgbe_configure_msix(dev);
2137
2138         /* initialize transmission unit */
2139         ixgbe_dev_tx_init(dev);
2140
2141         /* This can fail when allocating mbufs for descriptor rings */
2142         err = ixgbe_dev_rx_init(dev);
2143         if (err) {
2144                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2145                 goto error;
2146         }
2147
2148         err = ixgbe_dev_rxtx_start(dev);
2149         if (err < 0) {
2150                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2151                 goto error;
2152         }
2153
2154         /* Skip link setup if loopback mode is enabled for 82599. */
2155         if (hw->mac.type == ixgbe_mac_82599EB &&
2156                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2157                 goto skip_link_setup;
2158
2159         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2160                 err = hw->mac.ops.setup_sfp(hw);
2161                 if (err)
2162                         goto error;
2163         }
2164
2165         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2166                 /* Turn on the copper */
2167                 ixgbe_set_phy_power(hw, true);
2168         } else {
2169                 /* Turn on the laser */
2170                 ixgbe_enable_tx_laser(hw);
2171         }
2172
2173         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2174         if (err)
2175                 goto error;
2176         dev->data->dev_link.link_status = link_up;
2177
2178         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2179         if (err)
2180                 goto error;
2181
2182         switch(dev->data->dev_conf.link_speed) {
2183         case ETH_LINK_SPEED_AUTONEG:
2184                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2185                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2186                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2187                 break;
2188         case ETH_LINK_SPEED_100:
2189                 /*
2190                  * Invalid for 82598 but error will be detected by
2191                  * ixgbe_setup_link()
2192                  */
2193                 speed = IXGBE_LINK_SPEED_100_FULL;
2194                 break;
2195         case ETH_LINK_SPEED_1000:
2196                 speed = IXGBE_LINK_SPEED_1GB_FULL;
2197                 break;
2198         case ETH_LINK_SPEED_10000:
2199                 speed = IXGBE_LINK_SPEED_10GB_FULL;
2200                 break;
2201         default:
2202                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2203                              dev->data->dev_conf.link_speed,
2204                              dev->data->port_id);
2205                 goto error;
2206         }
2207
2208         err = ixgbe_setup_link(hw, speed, link_up);
2209         if (err)
2210                 goto error;
2211
2212 skip_link_setup:
2213
2214         if (rte_intr_allow_others(intr_handle)) {
2215                 /* check if lsc interrupt is enabled */
2216                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2217                         ixgbe_dev_lsc_interrupt_setup(dev);
2218         } else {
2219                 rte_intr_callback_unregister(intr_handle,
2220                                              ixgbe_dev_interrupt_handler,
2221                                              (void *)dev);
2222                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2223                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2224                                      " no intr multiplex\n");
2225         }
2226
2227         /* check if rxq interrupt is enabled */
2228         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2229             rte_intr_dp_is_en(intr_handle))
2230                 ixgbe_dev_rxq_interrupt_setup(dev);
2231
2232         /* enable uio/vfio intr/eventfd mapping */
2233         rte_intr_enable(intr_handle);
2234
2235         /* resume enabled intr since hw reset */
2236         ixgbe_enable_intr(dev);
2237
2238         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2239                 ETH_VLAN_EXTEND_MASK;
2240         ixgbe_vlan_offload_set(dev, mask);
2241
2242         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2243                 /* Enable vlan filtering for VMDq */
2244                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2245         }
2246
2247         /* Configure DCB hw */
2248         ixgbe_configure_dcb(dev);
2249
2250         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2251                 err = ixgbe_fdir_configure(dev);
2252                 if (err)
2253                         goto error;
2254         }
2255
2256         /* Restore vf rate limit */
2257         if (vfinfo != NULL) {
2258                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2259                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2260                                 if (vfinfo[vf].tx_rate[idx] != 0)
2261                                         ixgbe_set_vf_rate_limit(dev, vf,
2262                                                 vfinfo[vf].tx_rate[idx],
2263                                                 1 << idx);
2264         }
2265
2266         ixgbe_restore_statistics_mapping(dev);
2267
2268         return 0;
2269
2270 error:
2271         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2272         ixgbe_dev_clear_queues(dev);
2273         return -EIO;
2274 }
2275
2276 /*
2277  * Stop device: disable rx and tx functions to allow for reconfiguring.
2278  */
2279 static void
2280 ixgbe_dev_stop(struct rte_eth_dev *dev)
2281 {
2282         struct rte_eth_link link;
2283         struct ixgbe_hw *hw =
2284                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2285         struct ixgbe_vf_info *vfinfo =
2286                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2287         struct ixgbe_filter_info *filter_info =
2288                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2289         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2290         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2291         int vf;
2292
2293         PMD_INIT_FUNC_TRACE();
2294
2295         /* disable interrupts */
2296         ixgbe_disable_intr(hw);
2297
2298         /* reset the NIC */
2299         ixgbe_pf_reset_hw(hw);
2300         hw->adapter_stopped = 0;
2301
2302         /* stop adapter */
2303         ixgbe_stop_adapter(hw);
2304
2305         for (vf = 0; vfinfo != NULL &&
2306                      vf < dev->pci_dev->max_vfs; vf++)
2307                 vfinfo[vf].clear_to_send = false;
2308
2309         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2310                 /* Turn off the copper */
2311                 ixgbe_set_phy_power(hw, false);
2312         } else {
2313                 /* Turn off the laser */
2314                 ixgbe_disable_tx_laser(hw);
2315         }
2316
2317         ixgbe_dev_clear_queues(dev);
2318
2319         /* Clear stored conf */
2320         dev->data->scattered_rx = 0;
2321         dev->data->lro = 0;
2322
2323         /* Clear recorded link status */
2324         memset(&link, 0, sizeof(link));
2325         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2326
2327         /* Remove all ntuple filters of the device */
2328         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2329              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2330                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2331                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2332                              p_5tuple, entries);
2333                 rte_free(p_5tuple);
2334         }
2335         memset(filter_info->fivetuple_mask, 0,
2336                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2337
2338         if (!rte_intr_allow_others(intr_handle))
2339                 /* resume to the default handler */
2340                 rte_intr_callback_register(intr_handle,
2341                                            ixgbe_dev_interrupt_handler,
2342                                            (void *)dev);
2343
2344         /* Clean datapath event and queue/vec mapping */
2345         rte_intr_efd_disable(intr_handle);
2346         if (intr_handle->intr_vec != NULL) {
2347                 rte_free(intr_handle->intr_vec);
2348                 intr_handle->intr_vec = NULL;
2349         }
2350 }
2351
2352 /*
2353  * Set device link up: enable tx.
2354  */
2355 static int
2356 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2357 {
2358         struct ixgbe_hw *hw =
2359                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2360         if (hw->mac.type == ixgbe_mac_82599EB) {
2361 #ifdef RTE_NIC_BYPASS
2362                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2363                         /* Not suported in bypass mode */
2364                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2365                                      "by device id 0x%x", hw->device_id);
2366                         return -ENOTSUP;
2367                 }
2368 #endif
2369         }
2370
2371         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2372                 /* Turn on the copper */
2373                 ixgbe_set_phy_power(hw, true);
2374         } else {
2375                 /* Turn on the laser */
2376                 ixgbe_enable_tx_laser(hw);
2377         }
2378
2379         return 0;
2380 }
2381
2382 /*
2383  * Set device link down: disable tx.
2384  */
2385 static int
2386 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2387 {
2388         struct ixgbe_hw *hw =
2389                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2390         if (hw->mac.type == ixgbe_mac_82599EB) {
2391 #ifdef RTE_NIC_BYPASS
2392                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2393                         /* Not suported in bypass mode */
2394                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2395                                      "by device id 0x%x", hw->device_id);
2396                         return -ENOTSUP;
2397                 }
2398 #endif
2399         }
2400
2401         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2402                 /* Turn off the copper */
2403                 ixgbe_set_phy_power(hw, false);
2404         } else {
2405                 /* Turn off the laser */
2406                 ixgbe_disable_tx_laser(hw);
2407         }
2408
2409         return 0;
2410 }
2411
2412 /*
2413  * Reest and stop device.
2414  */
2415 static void
2416 ixgbe_dev_close(struct rte_eth_dev *dev)
2417 {
2418         struct ixgbe_hw *hw =
2419                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2420
2421         PMD_INIT_FUNC_TRACE();
2422
2423         ixgbe_pf_reset_hw(hw);
2424
2425         ixgbe_dev_stop(dev);
2426         hw->adapter_stopped = 1;
2427
2428         ixgbe_dev_free_queues(dev);
2429
2430         ixgbe_disable_pcie_master(hw);
2431
2432         /* reprogram the RAR[0] in case user changed it. */
2433         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2434 }
2435
2436 static void
2437 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2438                            struct ixgbe_hw_stats *hw_stats,
2439                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2440                            uint64_t *total_qprc, uint64_t *total_qprdc)
2441 {
2442         uint32_t bprc, lxon, lxoff, total;
2443         uint32_t delta_gprc = 0;
2444         unsigned i;
2445         /* Workaround for RX byte count not including CRC bytes when CRC
2446 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2447          * is disabled.
2448 +        */
2449         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2450                         IXGBE_HLREG0_RXCRCSTRP);
2451
2452         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2453         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2454         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2455         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2456
2457         for (i = 0; i < 8; i++) {
2458                 uint32_t mp;
2459                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2460                 /* global total per queue */
2461                 hw_stats->mpc[i] += mp;
2462                 /* Running comprehensive total for stats display */
2463                 *total_missed_rx += hw_stats->mpc[i];
2464                 if (hw->mac.type == ixgbe_mac_82598EB) {
2465                         hw_stats->rnbc[i] +=
2466                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2467                         hw_stats->pxonrxc[i] +=
2468                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2469                         hw_stats->pxoffrxc[i] +=
2470                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2471                 } else {
2472                         hw_stats->pxonrxc[i] +=
2473                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2474                         hw_stats->pxoffrxc[i] +=
2475                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2476                         hw_stats->pxon2offc[i] +=
2477                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2478                 }
2479                 hw_stats->pxontxc[i] +=
2480                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2481                 hw_stats->pxofftxc[i] +=
2482                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2483         }
2484         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2485                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2486                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2487                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2488
2489                 delta_gprc += delta_qprc;
2490
2491                 hw_stats->qprc[i] += delta_qprc;
2492                 hw_stats->qptc[i] += delta_qptc;
2493
2494                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2495                 hw_stats->qbrc[i] +=
2496                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2497                 if (crc_strip == 0)
2498                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2499
2500                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2501                 hw_stats->qbtc[i] +=
2502                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2503
2504                 hw_stats->qprdc[i] += delta_qprdc;
2505                 *total_qprdc += hw_stats->qprdc[i];
2506
2507                 *total_qprc += hw_stats->qprc[i];
2508                 *total_qbrc += hw_stats->qbrc[i];
2509         }
2510         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2511         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2512         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2513
2514         /*
2515          * An errata states that gprc actually counts good + missed packets:
2516          * Workaround to set gprc to summated queue packet receives
2517          */
2518         hw_stats->gprc = *total_qprc;
2519
2520         if (hw->mac.type != ixgbe_mac_82598EB) {
2521                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2522                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2523                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2524                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2525                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2526                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2527                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2528                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2529         } else {
2530                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2531                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2532                 /* 82598 only has a counter in the high register */
2533                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2534                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2535                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2536         }
2537         uint64_t old_tpr = hw_stats->tpr;
2538
2539         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2540         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2541
2542         if (crc_strip == 0)
2543                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2544
2545         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2546         hw_stats->gptc += delta_gptc;
2547         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2548         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2549
2550         /*
2551          * Workaround: mprc hardware is incorrectly counting
2552          * broadcasts, so for now we subtract those.
2553          */
2554         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2555         hw_stats->bprc += bprc;
2556         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2557         if (hw->mac.type == ixgbe_mac_82598EB)
2558                 hw_stats->mprc -= bprc;
2559
2560         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2561         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2562         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2563         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2564         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2565         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2566
2567         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2568         hw_stats->lxontxc += lxon;
2569         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2570         hw_stats->lxofftxc += lxoff;
2571         total = lxon + lxoff;
2572
2573         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2574         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2575         hw_stats->gptc -= total;
2576         hw_stats->mptc -= total;
2577         hw_stats->ptc64 -= total;
2578         hw_stats->gotc -= total * ETHER_MIN_LEN;
2579
2580         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2581         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2582         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2583         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2584         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2585         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2586         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2587         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2588         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2589         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2590         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2591         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2592         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2593         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2594         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2595         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2596         /* Only read FCOE on 82599 */
2597         if (hw->mac.type != ixgbe_mac_82598EB) {
2598                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2599                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2600                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2601                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2602                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2603         }
2604
2605         /* Flow Director Stats registers */
2606         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2607         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2608 }
2609
2610 /*
2611  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2612  */
2613 static void
2614 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2615 {
2616         struct ixgbe_hw *hw =
2617                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2618         struct ixgbe_hw_stats *hw_stats =
2619                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2620         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2621         unsigned i;
2622
2623         total_missed_rx = 0;
2624         total_qbrc = 0;
2625         total_qprc = 0;
2626         total_qprdc = 0;
2627
2628         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2629                         &total_qprc, &total_qprdc);
2630
2631         if (stats == NULL)
2632                 return;
2633
2634         /* Fill out the rte_eth_stats statistics structure */
2635         stats->ipackets = total_qprc;
2636         stats->ibytes = total_qbrc;
2637         stats->opackets = hw_stats->gptc;
2638         stats->obytes = hw_stats->gotc;
2639
2640         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2641                 stats->q_ipackets[i] = hw_stats->qprc[i];
2642                 stats->q_opackets[i] = hw_stats->qptc[i];
2643                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2644                 stats->q_obytes[i] = hw_stats->qbtc[i];
2645                 stats->q_errors[i] = hw_stats->qprdc[i];
2646         }
2647
2648         /* Rx Errors */
2649         stats->imissed  = total_missed_rx;
2650         stats->ierrors  = hw_stats->crcerrs +
2651                           hw_stats->mspdc +
2652                           hw_stats->rlec +
2653                           hw_stats->ruc +
2654                           hw_stats->roc +
2655                           total_missed_rx +
2656                           hw_stats->illerrc +
2657                           hw_stats->errbc +
2658                           hw_stats->rfc +
2659                           hw_stats->fccrc +
2660                           hw_stats->fclast;
2661
2662         /* Tx Errors */
2663         stats->oerrors  = 0;
2664 }
2665
2666 static void
2667 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2668 {
2669         struct ixgbe_hw_stats *stats =
2670                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2671
2672         /* HW registers are cleared on read */
2673         ixgbe_dev_stats_get(dev, NULL);
2674
2675         /* Reset software totals */
2676         memset(stats, 0, sizeof(*stats));
2677 }
2678
2679 /* This function calculates the number of xstats based on the current config */
2680 static unsigned
2681 ixgbe_xstats_calc_num(void) {
2682         return IXGBE_NB_HW_STATS + (IXGBE_NB_RXQ_PRIO_STATS * 8) +
2683                 (IXGBE_NB_TXQ_PRIO_STATS * 8);
2684 }
2685
2686 static int
2687 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2688                                          unsigned n)
2689 {
2690         struct ixgbe_hw *hw =
2691                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2692         struct ixgbe_hw_stats *hw_stats =
2693                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2694         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2695         unsigned i, stat, count = 0;
2696
2697         count = ixgbe_xstats_calc_num();
2698
2699         if (n < count)
2700                 return count;
2701
2702         total_missed_rx = 0;
2703         total_qbrc = 0;
2704         total_qprc = 0;
2705         total_qprdc = 0;
2706
2707         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2708                                    &total_qprc, &total_qprdc);
2709
2710         /* If this is a reset xstats is NULL, and we have cleared the
2711          * registers by reading them.
2712          */
2713         if (!xstats)
2714                 return 0;
2715
2716         /* Extended stats from ixgbe_hw_stats */
2717         count = 0;
2718         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2719                 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2720                          rte_ixgbe_stats_strings[i].name);
2721                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2722                                 rte_ixgbe_stats_strings[i].offset);
2723                 count++;
2724         }
2725
2726         /* RX Priority Stats */
2727         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2728                 for (i = 0; i < 8; i++) {
2729                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2730                                  "rx_priority%u_%s", i,
2731                                  rte_ixgbe_rxq_strings[stat].name);
2732                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2733                                         rte_ixgbe_rxq_strings[stat].offset +
2734                                         (sizeof(uint64_t) * i));
2735                         count++;
2736                 }
2737         }
2738
2739         /* TX Priority Stats */
2740         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2741                 for (i = 0; i < 8; i++) {
2742                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2743                                  "tx_priority%u_%s", i,
2744                                  rte_ixgbe_txq_strings[stat].name);
2745                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2746                                         rte_ixgbe_txq_strings[stat].offset +
2747                                         (sizeof(uint64_t) * i));
2748                         count++;
2749                 }
2750         }
2751
2752         return count;
2753 }
2754
2755 static void
2756 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2757 {
2758         struct ixgbe_hw_stats *stats =
2759                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2760
2761         unsigned count = ixgbe_xstats_calc_num();
2762
2763         /* HW registers are cleared on read */
2764         ixgbe_dev_xstats_get(dev, NULL, count);
2765
2766         /* Reset software totals */
2767         memset(stats, 0, sizeof(*stats));
2768 }
2769
2770 static void
2771 ixgbevf_update_stats(struct rte_eth_dev *dev)
2772 {
2773         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2774         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2775                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2776
2777         /* Good Rx packet, include VF loopback */
2778         UPDATE_VF_STAT(IXGBE_VFGPRC,
2779             hw_stats->last_vfgprc, hw_stats->vfgprc);
2780
2781         /* Good Rx octets, include VF loopback */
2782         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2783             hw_stats->last_vfgorc, hw_stats->vfgorc);
2784
2785         /* Good Tx packet, include VF loopback */
2786         UPDATE_VF_STAT(IXGBE_VFGPTC,
2787             hw_stats->last_vfgptc, hw_stats->vfgptc);
2788
2789         /* Good Tx octets, include VF loopback */
2790         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2791             hw_stats->last_vfgotc, hw_stats->vfgotc);
2792
2793         /* Rx Multicst Packet */
2794         UPDATE_VF_STAT(IXGBE_VFMPRC,
2795             hw_stats->last_vfmprc, hw_stats->vfmprc);
2796 }
2797
2798 static int
2799 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2800                        unsigned n)
2801 {
2802         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2803                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2804         unsigned i;
2805
2806         if (n < IXGBEVF_NB_XSTATS)
2807                 return IXGBEVF_NB_XSTATS;
2808
2809         ixgbevf_update_stats(dev);
2810
2811         if (!xstats)
2812                 return 0;
2813
2814         /* Extended stats */
2815         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2816                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2817                          "%s", rte_ixgbevf_stats_strings[i].name);
2818                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2819                         rte_ixgbevf_stats_strings[i].offset);
2820         }
2821
2822         return IXGBEVF_NB_XSTATS;
2823 }
2824
2825 static void
2826 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2827 {
2828         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2829                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2830
2831         ixgbevf_update_stats(dev);
2832
2833         if (stats == NULL)
2834                 return;
2835
2836         stats->ipackets = hw_stats->vfgprc;
2837         stats->ibytes = hw_stats->vfgorc;
2838         stats->opackets = hw_stats->vfgptc;
2839         stats->obytes = hw_stats->vfgotc;
2840         stats->imcasts = hw_stats->vfmprc;
2841         /* stats->imcasts should be removed as imcasts is deprecated */
2842 }
2843
2844 static void
2845 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2846 {
2847         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2848                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2849
2850         /* Sync HW register to the last stats */
2851         ixgbevf_dev_stats_get(dev, NULL);
2852
2853         /* reset HW current stats*/
2854         hw_stats->vfgprc = 0;
2855         hw_stats->vfgorc = 0;
2856         hw_stats->vfgptc = 0;
2857         hw_stats->vfgotc = 0;
2858         hw_stats->vfmprc = 0;
2859
2860 }
2861
2862 static void
2863 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2864 {
2865         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2866
2867         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2868         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2869         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2870         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2871         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2872         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2873         dev_info->max_vfs = dev->pci_dev->max_vfs;
2874         if (hw->mac.type == ixgbe_mac_82598EB)
2875                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2876         else
2877                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2878         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2879         dev_info->rx_offload_capa =
2880                 DEV_RX_OFFLOAD_VLAN_STRIP |
2881                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2882                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2883                 DEV_RX_OFFLOAD_TCP_CKSUM;
2884
2885         /*
2886          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2887          * mode.
2888          */
2889         if ((hw->mac.type == ixgbe_mac_82599EB ||
2890              hw->mac.type == ixgbe_mac_X540) &&
2891             !RTE_ETH_DEV_SRIOV(dev).active)
2892                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2893
2894         if (hw->mac.type == ixgbe_mac_X550 ||
2895             hw->mac.type == ixgbe_mac_X550EM_x)
2896                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2897
2898         dev_info->tx_offload_capa =
2899                 DEV_TX_OFFLOAD_VLAN_INSERT |
2900                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2901                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2902                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2903                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2904                 DEV_TX_OFFLOAD_TCP_TSO;
2905
2906         if (hw->mac.type == ixgbe_mac_X550 ||
2907             hw->mac.type == ixgbe_mac_X550EM_x)
2908                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2909
2910         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2911                 .rx_thresh = {
2912                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2913                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2914                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2915                 },
2916                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2917                 .rx_drop_en = 0,
2918         };
2919
2920         dev_info->default_txconf = (struct rte_eth_txconf) {
2921                 .tx_thresh = {
2922                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2923                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2924                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2925                 },
2926                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2927                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2928                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2929                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2930         };
2931
2932         dev_info->rx_desc_lim = rx_desc_lim;
2933         dev_info->tx_desc_lim = tx_desc_lim;
2934
2935         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2936         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2937         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2938 }
2939
2940 static void
2941 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2942                      struct rte_eth_dev_info *dev_info)
2943 {
2944         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2945
2946         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2947         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2948         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2949         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2950         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2951         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2952         dev_info->max_vfs = dev->pci_dev->max_vfs;
2953         if (hw->mac.type == ixgbe_mac_82598EB)
2954                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2955         else
2956                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2957         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2958                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2959                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2960                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2961         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2962                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2963                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2964                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2965                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2966                                 DEV_TX_OFFLOAD_TCP_TSO;
2967
2968         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2969                 .rx_thresh = {
2970                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2971                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2972                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2973                 },
2974                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2975                 .rx_drop_en = 0,
2976         };
2977
2978         dev_info->default_txconf = (struct rte_eth_txconf) {
2979                 .tx_thresh = {
2980                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2981                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2982                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2983                 },
2984                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2985                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2986                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2987                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2988         };
2989
2990         dev_info->rx_desc_lim = rx_desc_lim;
2991         dev_info->tx_desc_lim = tx_desc_lim;
2992 }
2993
2994 /* return 0 means link status changed, -1 means not changed */
2995 static int
2996 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2997 {
2998         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2999         struct rte_eth_link link, old;
3000         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3001         int link_up;
3002         int diag;
3003
3004         link.link_status = 0;
3005         link.link_speed = 0;
3006         link.link_duplex = 0;
3007         memset(&old, 0, sizeof(old));
3008         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3009
3010         hw->mac.get_link_status = true;
3011
3012         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3013         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3014                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3015         else
3016                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3017
3018         if (diag != 0) {
3019                 link.link_speed = ETH_LINK_SPEED_100;
3020                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3021                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3022                 if (link.link_status == old.link_status)
3023                         return -1;
3024                 return 0;
3025         }
3026
3027         if (link_up == 0) {
3028                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3029                 if (link.link_status == old.link_status)
3030                         return -1;
3031                 return 0;
3032         }
3033         link.link_status = 1;
3034         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3035
3036         switch (link_speed) {
3037         default:
3038         case IXGBE_LINK_SPEED_UNKNOWN:
3039                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3040                 link.link_speed = ETH_LINK_SPEED_100;
3041                 break;
3042
3043         case IXGBE_LINK_SPEED_100_FULL:
3044                 link.link_speed = ETH_LINK_SPEED_100;
3045                 break;
3046
3047         case IXGBE_LINK_SPEED_1GB_FULL:
3048                 link.link_speed = ETH_LINK_SPEED_1000;
3049                 break;
3050
3051         case IXGBE_LINK_SPEED_10GB_FULL:
3052                 link.link_speed = ETH_LINK_SPEED_10000;
3053                 break;
3054         }
3055         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3056
3057         if (link.link_status == old.link_status)
3058                 return -1;
3059
3060         return 0;
3061 }
3062
3063 static void
3064 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3065 {
3066         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3067         uint32_t fctrl;
3068
3069         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3070         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3071         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3072 }
3073
3074 static void
3075 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3076 {
3077         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3078         uint32_t fctrl;
3079
3080         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3081         fctrl &= (~IXGBE_FCTRL_UPE);
3082         if (dev->data->all_multicast == 1)
3083                 fctrl |= IXGBE_FCTRL_MPE;
3084         else
3085                 fctrl &= (~IXGBE_FCTRL_MPE);
3086         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3087 }
3088
3089 static void
3090 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3091 {
3092         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3093         uint32_t fctrl;
3094
3095         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3096         fctrl |= IXGBE_FCTRL_MPE;
3097         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3098 }
3099
3100 static void
3101 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3102 {
3103         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3104         uint32_t fctrl;
3105
3106         if (dev->data->promiscuous == 1)
3107                 return; /* must remain in all_multicast mode */
3108
3109         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3110         fctrl &= (~IXGBE_FCTRL_MPE);
3111         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3112 }
3113
3114 /**
3115  * It clears the interrupt causes and enables the interrupt.
3116  * It will be called once only during nic initialized.
3117  *
3118  * @param dev
3119  *  Pointer to struct rte_eth_dev.
3120  *
3121  * @return
3122  *  - On success, zero.
3123  *  - On failure, a negative value.
3124  */
3125 static int
3126 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3127 {
3128         struct ixgbe_interrupt *intr =
3129                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3130
3131         ixgbe_dev_link_status_print(dev);
3132         intr->mask |= IXGBE_EICR_LSC;
3133
3134         return 0;
3135 }
3136
3137 /**
3138  * It clears the interrupt causes and enables the interrupt.
3139  * It will be called once only during nic initialized.
3140  *
3141  * @param dev
3142  *  Pointer to struct rte_eth_dev.
3143  *
3144  * @return
3145  *  - On success, zero.
3146  *  - On failure, a negative value.
3147  */
3148 static int
3149 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3150 {
3151         struct ixgbe_interrupt *intr =
3152                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3153
3154         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3155
3156         return 0;
3157 }
3158
3159 /*
3160  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3161  *
3162  * @param dev
3163  *  Pointer to struct rte_eth_dev.
3164  *
3165  * @return
3166  *  - On success, zero.
3167  *  - On failure, a negative value.
3168  */
3169 static int
3170 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3171 {
3172         uint32_t eicr;
3173         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3174         struct ixgbe_interrupt *intr =
3175                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3176
3177         /* clear all cause mask */
3178         ixgbe_disable_intr(hw);
3179
3180         /* read-on-clear nic registers here */
3181         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3182         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3183
3184         intr->flags = 0;
3185
3186         /* set flag for async link update */
3187         if (eicr & IXGBE_EICR_LSC)
3188                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3189
3190         if (eicr & IXGBE_EICR_MAILBOX)
3191                 intr->flags |= IXGBE_FLAG_MAILBOX;
3192
3193         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3194             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3195             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3196                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3197
3198         return 0;
3199 }
3200
3201 /**
3202  * It gets and then prints the link status.
3203  *
3204  * @param dev
3205  *  Pointer to struct rte_eth_dev.
3206  *
3207  * @return
3208  *  - On success, zero.
3209  *  - On failure, a negative value.
3210  */
3211 static void
3212 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3213 {
3214         struct rte_eth_link link;
3215
3216         memset(&link, 0, sizeof(link));
3217         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3218         if (link.link_status) {
3219                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3220                                         (int)(dev->data->port_id),
3221                                         (unsigned)link.link_speed,
3222                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3223                                         "full-duplex" : "half-duplex");
3224         } else {
3225                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3226                                 (int)(dev->data->port_id));
3227         }
3228         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3229                                 dev->pci_dev->addr.domain,
3230                                 dev->pci_dev->addr.bus,
3231                                 dev->pci_dev->addr.devid,
3232                                 dev->pci_dev->addr.function);
3233 }
3234
3235 /*
3236  * It executes link_update after knowing an interrupt occurred.
3237  *
3238  * @param dev
3239  *  Pointer to struct rte_eth_dev.
3240  *
3241  * @return
3242  *  - On success, zero.
3243  *  - On failure, a negative value.
3244  */
3245 static int
3246 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3247 {
3248         struct ixgbe_interrupt *intr =
3249                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3250         int64_t timeout;
3251         struct rte_eth_link link;
3252         int intr_enable_delay = false;
3253         struct ixgbe_hw *hw =
3254                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3255
3256         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3257
3258         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3259                 ixgbe_pf_mbx_process(dev);
3260                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3261         }
3262
3263         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3264                 ixgbe_handle_lasi(hw);
3265                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3266         }
3267
3268         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3269                 /* get the link status before link update, for predicting later */
3270                 memset(&link, 0, sizeof(link));
3271                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3272
3273                 ixgbe_dev_link_update(dev, 0);
3274
3275                 /* likely to up */
3276                 if (!link.link_status)
3277                         /* handle it 1 sec later, wait it being stable */
3278                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3279                 /* likely to down */
3280                 else
3281                         /* handle it 4 sec later, wait it being stable */
3282                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3283
3284                 ixgbe_dev_link_status_print(dev);
3285
3286                 intr_enable_delay = true;
3287         }
3288
3289         if (intr_enable_delay) {
3290                 if (rte_eal_alarm_set(timeout * 1000,
3291                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3292                         PMD_DRV_LOG(ERR, "Error setting alarm");
3293         } else {
3294                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3295                 ixgbe_enable_intr(dev);
3296                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3297         }
3298
3299
3300         return 0;
3301 }
3302
3303 /**
3304  * Interrupt handler which shall be registered for alarm callback for delayed
3305  * handling specific interrupt to wait for the stable nic state. As the
3306  * NIC interrupt state is not stable for ixgbe after link is just down,
3307  * it needs to wait 4 seconds to get the stable status.
3308  *
3309  * @param handle
3310  *  Pointer to interrupt handle.
3311  * @param param
3312  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3313  *
3314  * @return
3315  *  void
3316  */
3317 static void
3318 ixgbe_dev_interrupt_delayed_handler(void *param)
3319 {
3320         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3321         struct ixgbe_interrupt *intr =
3322                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3323         struct ixgbe_hw *hw =
3324                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3325         uint32_t eicr;
3326
3327         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3328         if (eicr & IXGBE_EICR_MAILBOX)
3329                 ixgbe_pf_mbx_process(dev);
3330
3331         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3332                 ixgbe_handle_lasi(hw);
3333                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3334         }
3335
3336         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3337                 ixgbe_dev_link_update(dev, 0);
3338                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3339                 ixgbe_dev_link_status_print(dev);
3340                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3341         }
3342
3343         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3344         ixgbe_enable_intr(dev);
3345         rte_intr_enable(&(dev->pci_dev->intr_handle));
3346 }
3347
3348 /**
3349  * Interrupt handler triggered by NIC  for handling
3350  * specific interrupt.
3351  *
3352  * @param handle
3353  *  Pointer to interrupt handle.
3354  * @param param
3355  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3356  *
3357  * @return
3358  *  void
3359  */
3360 static void
3361 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3362                             void *param)
3363 {
3364         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3365
3366         ixgbe_dev_interrupt_get_status(dev);
3367         ixgbe_dev_interrupt_action(dev);
3368 }
3369
3370 static int
3371 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3372 {
3373         struct ixgbe_hw *hw;
3374
3375         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3376         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3377 }
3378
3379 static int
3380 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3381 {
3382         struct ixgbe_hw *hw;
3383
3384         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3385         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3386 }
3387
3388 static int
3389 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3390 {
3391         struct ixgbe_hw *hw;
3392         uint32_t mflcn_reg;
3393         uint32_t fccfg_reg;
3394         int rx_pause;
3395         int tx_pause;
3396
3397         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3398
3399         fc_conf->pause_time = hw->fc.pause_time;
3400         fc_conf->high_water = hw->fc.high_water[0];
3401         fc_conf->low_water = hw->fc.low_water[0];
3402         fc_conf->send_xon = hw->fc.send_xon;
3403         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3404
3405         /*
3406          * Return rx_pause status according to actual setting of
3407          * MFLCN register.
3408          */
3409         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3410         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3411                 rx_pause = 1;
3412         else
3413                 rx_pause = 0;
3414
3415         /*
3416          * Return tx_pause status according to actual setting of
3417          * FCCFG register.
3418          */
3419         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3420         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3421                 tx_pause = 1;
3422         else
3423                 tx_pause = 0;
3424
3425         if (rx_pause && tx_pause)
3426                 fc_conf->mode = RTE_FC_FULL;
3427         else if (rx_pause)
3428                 fc_conf->mode = RTE_FC_RX_PAUSE;
3429         else if (tx_pause)
3430                 fc_conf->mode = RTE_FC_TX_PAUSE;
3431         else
3432                 fc_conf->mode = RTE_FC_NONE;
3433
3434         return 0;
3435 }
3436
3437 static int
3438 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3439 {
3440         struct ixgbe_hw *hw;
3441         int err;
3442         uint32_t rx_buf_size;
3443         uint32_t max_high_water;
3444         uint32_t mflcn;
3445         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3446                 ixgbe_fc_none,
3447                 ixgbe_fc_rx_pause,
3448                 ixgbe_fc_tx_pause,
3449                 ixgbe_fc_full
3450         };
3451
3452         PMD_INIT_FUNC_TRACE();
3453
3454         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3455         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3456         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3457
3458         /*
3459          * At least reserve one Ethernet frame for watermark
3460          * high_water/low_water in kilo bytes for ixgbe
3461          */
3462         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3463         if ((fc_conf->high_water > max_high_water) ||
3464                 (fc_conf->high_water < fc_conf->low_water)) {
3465                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3466                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3467                 return -EINVAL;
3468         }
3469
3470         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3471         hw->fc.pause_time     = fc_conf->pause_time;
3472         hw->fc.high_water[0]  = fc_conf->high_water;
3473         hw->fc.low_water[0]   = fc_conf->low_water;
3474         hw->fc.send_xon       = fc_conf->send_xon;
3475         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3476
3477         err = ixgbe_fc_enable(hw);
3478
3479         /* Not negotiated is not an error case */
3480         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3481
3482                 /* check if we want to forward MAC frames - driver doesn't have native
3483                  * capability to do that, so we'll write the registers ourselves */
3484
3485                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3486
3487                 /* set or clear MFLCN.PMCF bit depending on configuration */
3488                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3489                         mflcn |= IXGBE_MFLCN_PMCF;
3490                 else
3491                         mflcn &= ~IXGBE_MFLCN_PMCF;
3492
3493                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3494                 IXGBE_WRITE_FLUSH(hw);
3495
3496                 return 0;
3497         }
3498
3499         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3500         return -EIO;
3501 }
3502
3503 /**
3504  *  ixgbe_pfc_enable_generic - Enable flow control
3505  *  @hw: pointer to hardware structure
3506  *  @tc_num: traffic class number
3507  *  Enable flow control according to the current settings.
3508  */
3509 static int
3510 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3511 {
3512         int ret_val = 0;
3513         uint32_t mflcn_reg, fccfg_reg;
3514         uint32_t reg;
3515         uint32_t fcrtl, fcrth;
3516         uint8_t i;
3517         uint8_t nb_rx_en;
3518
3519         /* Validate the water mark configuration */
3520         if (!hw->fc.pause_time) {
3521                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3522                 goto out;
3523         }
3524
3525         /* Low water mark of zero causes XOFF floods */
3526         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3527                  /* High/Low water can not be 0 */
3528                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3529                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3530                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3531                         goto out;
3532                 }
3533
3534                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3535                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3536                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3537                         goto out;
3538                 }
3539         }
3540         /* Negotiate the fc mode to use */
3541         ixgbe_fc_autoneg(hw);
3542
3543         /* Disable any previous flow control settings */
3544         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3545         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3546
3547         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3548         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3549
3550         switch (hw->fc.current_mode) {
3551         case ixgbe_fc_none:
3552                 /*
3553                  * If the count of enabled RX Priority Flow control >1,
3554                  * and the TX pause can not be disabled
3555                  */
3556                 nb_rx_en = 0;
3557                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3558                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3559                         if (reg & IXGBE_FCRTH_FCEN)
3560                                 nb_rx_en++;
3561                 }
3562                 if (nb_rx_en > 1)
3563                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3564                 break;
3565         case ixgbe_fc_rx_pause:
3566                 /*
3567                  * Rx Flow control is enabled and Tx Flow control is
3568                  * disabled by software override. Since there really
3569                  * isn't a way to advertise that we are capable of RX
3570                  * Pause ONLY, we will advertise that we support both
3571                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3572                  * disable the adapter's ability to send PAUSE frames.
3573                  */
3574                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3575                 /*
3576                  * If the count of enabled RX Priority Flow control >1,
3577                  * and the TX pause can not be disabled
3578                  */
3579                 nb_rx_en = 0;
3580                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3581                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3582                         if (reg & IXGBE_FCRTH_FCEN)
3583                                 nb_rx_en++;
3584                 }
3585                 if (nb_rx_en > 1)
3586                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3587                 break;
3588         case ixgbe_fc_tx_pause:
3589                 /*
3590                  * Tx Flow control is enabled, and Rx Flow control is
3591                  * disabled by software override.
3592                  */
3593                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3594                 break;
3595         case ixgbe_fc_full:
3596                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3597                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3598                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3599                 break;
3600         default:
3601                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3602                 ret_val = IXGBE_ERR_CONFIG;
3603                 goto out;
3604                 break;
3605         }
3606
3607         /* Set 802.3x based flow control settings. */
3608         mflcn_reg |= IXGBE_MFLCN_DPF;
3609         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3610         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3611
3612         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3613         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3614                 hw->fc.high_water[tc_num]) {
3615                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3616                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3617                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3618         } else {
3619                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3620                 /*
3621                  * In order to prevent Tx hangs when the internal Tx
3622                  * switch is enabled we must set the high water mark
3623                  * to the maximum FCRTH value.  This allows the Tx
3624                  * switch to function even under heavy Rx workloads.
3625                  */
3626                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3627         }
3628         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3629
3630         /* Configure pause time (2 TCs per register) */
3631         reg = hw->fc.pause_time * 0x00010001;
3632         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3633                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3634
3635         /* Configure flow control refresh threshold value */
3636         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3637
3638 out:
3639         return ret_val;
3640 }
3641
3642 static int
3643 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3644 {
3645         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3646         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3647
3648         if (hw->mac.type != ixgbe_mac_82598EB) {
3649                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3650         }
3651         return ret_val;
3652 }
3653
3654 static int
3655 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3656 {
3657         int err;
3658         uint32_t rx_buf_size;
3659         uint32_t max_high_water;
3660         uint8_t tc_num;
3661         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3662         struct ixgbe_hw *hw =
3663                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3664         struct ixgbe_dcb_config *dcb_config =
3665                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3666
3667         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3668                 ixgbe_fc_none,
3669                 ixgbe_fc_rx_pause,
3670                 ixgbe_fc_tx_pause,
3671                 ixgbe_fc_full
3672         };
3673
3674         PMD_INIT_FUNC_TRACE();
3675
3676         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3677         tc_num = map[pfc_conf->priority];
3678         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3679         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3680         /*
3681          * At least reserve one Ethernet frame for watermark
3682          * high_water/low_water in kilo bytes for ixgbe
3683          */
3684         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3685         if ((pfc_conf->fc.high_water > max_high_water) ||
3686             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3687                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3688                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3689                 return -EINVAL;
3690         }
3691
3692         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3693         hw->fc.pause_time = pfc_conf->fc.pause_time;
3694         hw->fc.send_xon = pfc_conf->fc.send_xon;
3695         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3696         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3697
3698         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3699
3700         /* Not negotiated is not an error case */
3701         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3702                 return 0;
3703
3704         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3705         return -EIO;
3706 }
3707
3708 static int
3709 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3710                           struct rte_eth_rss_reta_entry64 *reta_conf,
3711                           uint16_t reta_size)
3712 {
3713         uint8_t i, j, mask;
3714         uint32_t reta, r;
3715         uint16_t idx, shift;
3716         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3717         uint16_t sp_reta_size;
3718         uint32_t reta_reg;
3719
3720         PMD_INIT_FUNC_TRACE();
3721
3722         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3723                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3724                         "NIC.");
3725                 return -ENOTSUP;
3726         }
3727
3728         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3729         if (reta_size != sp_reta_size) {
3730                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3731                         "(%d) doesn't match the number hardware can supported "
3732                         "(%d)\n", reta_size, sp_reta_size);
3733                 return -EINVAL;
3734         }
3735
3736         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3737                 idx = i / RTE_RETA_GROUP_SIZE;
3738                 shift = i % RTE_RETA_GROUP_SIZE;
3739                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3740                                                 IXGBE_4_BIT_MASK);
3741                 if (!mask)
3742                         continue;
3743                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3744                 if (mask == IXGBE_4_BIT_MASK)
3745                         r = 0;
3746                 else
3747                         r = IXGBE_READ_REG(hw, reta_reg);
3748                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3749                         if (mask & (0x1 << j))
3750                                 reta |= reta_conf[idx].reta[shift + j] <<
3751                                                         (CHAR_BIT * j);
3752                         else
3753                                 reta |= r & (IXGBE_8_BIT_MASK <<
3754                                                 (CHAR_BIT * j));
3755                 }
3756                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3757         }
3758
3759         return 0;
3760 }
3761
3762 static int
3763 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3764                          struct rte_eth_rss_reta_entry64 *reta_conf,
3765                          uint16_t reta_size)
3766 {
3767         uint8_t i, j, mask;
3768         uint32_t reta;
3769         uint16_t idx, shift;
3770         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3771         uint16_t sp_reta_size;
3772         uint32_t reta_reg;
3773
3774         PMD_INIT_FUNC_TRACE();
3775         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3776         if (reta_size != sp_reta_size) {
3777                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3778                         "(%d) doesn't match the number hardware can supported "
3779                         "(%d)\n", reta_size, sp_reta_size);
3780                 return -EINVAL;
3781         }
3782
3783         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3784                 idx = i / RTE_RETA_GROUP_SIZE;
3785                 shift = i % RTE_RETA_GROUP_SIZE;
3786                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3787                                                 IXGBE_4_BIT_MASK);
3788                 if (!mask)
3789                         continue;
3790
3791                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3792                 reta = IXGBE_READ_REG(hw, reta_reg);
3793                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3794                         if (mask & (0x1 << j))
3795                                 reta_conf[idx].reta[shift + j] =
3796                                         ((reta >> (CHAR_BIT * j)) &
3797                                                 IXGBE_8_BIT_MASK);
3798                 }
3799         }
3800
3801         return 0;
3802 }
3803
3804 static void
3805 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3806                                 uint32_t index, uint32_t pool)
3807 {
3808         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3809         uint32_t enable_addr = 1;
3810
3811         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3812 }
3813
3814 static void
3815 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3816 {
3817         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3818
3819         ixgbe_clear_rar(hw, index);
3820 }
3821
3822 static void
3823 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3824 {
3825         ixgbe_remove_rar(dev, 0);
3826
3827         ixgbe_add_rar(dev, addr, 0, 0);
3828 }
3829
3830 static int
3831 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3832 {
3833         uint32_t hlreg0;
3834         uint32_t maxfrs;
3835         struct ixgbe_hw *hw;
3836         struct rte_eth_dev_info dev_info;
3837         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3838
3839         ixgbe_dev_info_get(dev, &dev_info);
3840
3841         /* check that mtu is within the allowed range */
3842         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3843                 return -EINVAL;
3844
3845         /* refuse mtu that requires the support of scattered packets when this
3846          * feature has not been enabled before. */
3847         if (!dev->data->scattered_rx &&
3848             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3849              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3850                 return -EINVAL;
3851
3852         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3853         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3854
3855         /* switch to jumbo mode if needed */
3856         if (frame_size > ETHER_MAX_LEN) {
3857                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3858                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3859         } else {
3860                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3861                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3862         }
3863         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3864
3865         /* update max frame size */
3866         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3867
3868         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3869         maxfrs &= 0x0000FFFF;
3870         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3871         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3872
3873         return 0;
3874 }
3875
3876 /*
3877  * Virtual Function operations
3878  */
3879 static void
3880 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3881 {
3882         PMD_INIT_FUNC_TRACE();
3883
3884         /* Clear interrupt mask to stop from interrupts being generated */
3885         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3886
3887         IXGBE_WRITE_FLUSH(hw);
3888 }
3889
3890 static void
3891 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3892 {
3893         PMD_INIT_FUNC_TRACE();
3894
3895         /* VF enable interrupt autoclean */
3896         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3897         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3898         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3899
3900         IXGBE_WRITE_FLUSH(hw);
3901 }
3902
3903 static int
3904 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3905 {
3906         struct rte_eth_conf* conf = &dev->data->dev_conf;
3907         struct ixgbe_adapter *adapter =
3908                         (struct ixgbe_adapter *)dev->data->dev_private;
3909
3910         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3911                      dev->data->port_id);
3912
3913         /*
3914          * VF has no ability to enable/disable HW CRC
3915          * Keep the persistent behavior the same as Host PF
3916          */
3917 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3918         if (!conf->rxmode.hw_strip_crc) {
3919                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3920                 conf->rxmode.hw_strip_crc = 1;
3921         }
3922 #else
3923         if (conf->rxmode.hw_strip_crc) {
3924                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3925                 conf->rxmode.hw_strip_crc = 0;
3926         }
3927 #endif
3928
3929         /*
3930          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3931          * allocation or vector Rx preconditions we will reset it.
3932          */
3933         adapter->rx_bulk_alloc_allowed = true;
3934         adapter->rx_vec_allowed = true;
3935
3936         return 0;
3937 }
3938
3939 static int
3940 ixgbevf_dev_start(struct rte_eth_dev *dev)
3941 {
3942         struct ixgbe_hw *hw =
3943                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3944         uint32_t intr_vector = 0;
3945         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3946
3947         int err, mask = 0;
3948
3949         PMD_INIT_FUNC_TRACE();
3950
3951         hw->mac.ops.reset_hw(hw);
3952         hw->mac.get_link_status = true;
3953
3954         /* negotiate mailbox API version to use with the PF. */
3955         ixgbevf_negotiate_api(hw);
3956
3957         ixgbevf_dev_tx_init(dev);
3958
3959         /* This can fail when allocating mbufs for descriptor rings */
3960         err = ixgbevf_dev_rx_init(dev);
3961         if (err) {
3962                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3963                 ixgbe_dev_clear_queues(dev);
3964                 return err;
3965         }
3966
3967         /* Set vfta */
3968         ixgbevf_set_vfta_all(dev,1);
3969
3970         /* Set HW strip */
3971         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3972                 ETH_VLAN_EXTEND_MASK;
3973         ixgbevf_vlan_offload_set(dev, mask);
3974
3975         ixgbevf_dev_rxtx_start(dev);
3976
3977         /* check and configure queue intr-vector mapping */
3978         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3979                 intr_vector = dev->data->nb_rx_queues;
3980                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3981                         return -1;
3982         }
3983
3984         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3985                 intr_handle->intr_vec =
3986                         rte_zmalloc("intr_vec",
3987                                     dev->data->nb_rx_queues * sizeof(int), 0);
3988                 if (intr_handle->intr_vec == NULL) {
3989                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3990                                      " intr_vec\n", dev->data->nb_rx_queues);
3991                         return -ENOMEM;
3992                 }
3993         }
3994         ixgbevf_configure_msix(dev);
3995
3996         rte_intr_enable(intr_handle);
3997
3998         /* Re-enable interrupt for VF */
3999         ixgbevf_intr_enable(hw);
4000
4001         return 0;
4002 }
4003
4004 static void
4005 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4006 {
4007         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4008         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4009
4010         PMD_INIT_FUNC_TRACE();
4011
4012         hw->adapter_stopped = 1;
4013         ixgbe_stop_adapter(hw);
4014
4015         /*
4016           * Clear what we set, but we still keep shadow_vfta to
4017           * restore after device starts
4018           */
4019         ixgbevf_set_vfta_all(dev,0);
4020
4021         /* Clear stored conf */
4022         dev->data->scattered_rx = 0;
4023
4024         ixgbe_dev_clear_queues(dev);
4025
4026         /* Clean datapath event and queue/vec mapping */
4027         rte_intr_efd_disable(intr_handle);
4028         if (intr_handle->intr_vec != NULL) {
4029                 rte_free(intr_handle->intr_vec);
4030                 intr_handle->intr_vec = NULL;
4031         }
4032 }
4033
4034 static void
4035 ixgbevf_dev_close(struct rte_eth_dev *dev)
4036 {
4037         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4038
4039         PMD_INIT_FUNC_TRACE();
4040
4041         ixgbe_reset_hw(hw);
4042
4043         ixgbevf_dev_stop(dev);
4044
4045         ixgbe_dev_free_queues(dev);
4046
4047         /* reprogram the RAR[0] in case user changed it. */
4048         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
4049 }
4050
4051 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4052 {
4053         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4054         struct ixgbe_vfta * shadow_vfta =
4055                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4056         int i = 0, j = 0, vfta = 0, mask = 1;
4057
4058         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
4059                 vfta = shadow_vfta->vfta[i];
4060                 if (vfta) {
4061                         mask = 1;
4062                         for (j = 0; j < 32; j++){
4063                                 if (vfta & mask)
4064                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
4065                                 mask<<=1;
4066                         }
4067                 }
4068         }
4069
4070 }
4071
4072 static int
4073 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4074 {
4075         struct ixgbe_hw *hw =
4076                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4077         struct ixgbe_vfta * shadow_vfta =
4078                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4079         uint32_t vid_idx = 0;
4080         uint32_t vid_bit = 0;
4081         int ret = 0;
4082
4083         PMD_INIT_FUNC_TRACE();
4084
4085         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4086         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4087         if (ret) {
4088                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4089                 return ret;
4090         }
4091         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4092         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4093
4094         /* Save what we set and retore it after device reset */
4095         if (on)
4096                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4097         else
4098                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4099
4100         return 0;
4101 }
4102
4103 static void
4104 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4105 {
4106         struct ixgbe_hw *hw =
4107                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4108         uint32_t ctrl;
4109
4110         PMD_INIT_FUNC_TRACE();
4111
4112         if (queue >= hw->mac.max_rx_queues)
4113                 return;
4114
4115         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4116         if (on)
4117                 ctrl |= IXGBE_RXDCTL_VME;
4118         else
4119                 ctrl &= ~IXGBE_RXDCTL_VME;
4120         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4121
4122         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4123 }
4124
4125 static void
4126 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4127 {
4128         struct ixgbe_hw *hw =
4129                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4130         uint16_t i;
4131         int on = 0;
4132
4133         /* VF function only support hw strip feature, others are not support */
4134         if (mask & ETH_VLAN_STRIP_MASK) {
4135                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4136
4137                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4138                         ixgbevf_vlan_strip_queue_set(dev,i,on);
4139         }
4140 }
4141
4142 static int
4143 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4144 {
4145         uint32_t reg_val;
4146
4147         /* we only need to do this if VMDq is enabled */
4148         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4149         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4150                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4151                 return -1;
4152         }
4153
4154         return 0;
4155 }
4156
4157 static uint32_t
4158 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4159 {
4160         uint32_t vector = 0;
4161         switch (hw->mac.mc_filter_type) {
4162         case 0:   /* use bits [47:36] of the address */
4163                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4164                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4165                 break;
4166         case 1:   /* use bits [46:35] of the address */
4167                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4168                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4169                 break;
4170         case 2:   /* use bits [45:34] of the address */
4171                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4172                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4173                 break;
4174         case 3:   /* use bits [43:32] of the address */
4175                 vector = ((uc_addr->addr_bytes[4]) |
4176                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4177                 break;
4178         default:  /* Invalid mc_filter_type */
4179                 break;
4180         }
4181
4182         /* vector can only be 12-bits or boundary will be exceeded */
4183         vector &= 0xFFF;
4184         return vector;
4185 }
4186
4187 static int
4188 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4189                                uint8_t on)
4190 {
4191         uint32_t vector;
4192         uint32_t uta_idx;
4193         uint32_t reg_val;
4194         uint32_t uta_shift;
4195         uint32_t rc;
4196         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4197         const uint32_t ixgbe_uta_bit_shift = 5;
4198         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4199         const uint32_t bit1 = 0x1;
4200
4201         struct ixgbe_hw *hw =
4202                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4203         struct ixgbe_uta_info *uta_info =
4204                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4205
4206         /* The UTA table only exists on 82599 hardware and newer */
4207         if (hw->mac.type < ixgbe_mac_82599EB)
4208                 return -ENOTSUP;
4209
4210         vector = ixgbe_uta_vector(hw,mac_addr);
4211         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4212         uta_shift = vector & ixgbe_uta_bit_mask;
4213
4214         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4215         if (rc == on)
4216                 return 0;
4217
4218         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4219         if (on) {
4220                 uta_info->uta_in_use++;
4221                 reg_val |= (bit1 << uta_shift);
4222                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4223         } else {
4224                 uta_info->uta_in_use--;
4225                 reg_val &= ~(bit1 << uta_shift);
4226                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4227         }
4228
4229         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4230
4231         if (uta_info->uta_in_use > 0)
4232                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4233                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4234         else
4235                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4236
4237         return 0;
4238 }
4239
4240 static int
4241 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4242 {
4243         int i;
4244         struct ixgbe_hw *hw =
4245                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4246         struct ixgbe_uta_info *uta_info =
4247                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4248
4249         /* The UTA table only exists on 82599 hardware and newer */
4250         if (hw->mac.type < ixgbe_mac_82599EB)
4251                 return -ENOTSUP;
4252
4253         if (on) {
4254                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4255                         uta_info->uta_shadow[i] = ~0;
4256                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4257                 }
4258         } else {
4259                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4260                         uta_info->uta_shadow[i] = 0;
4261                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4262                 }
4263         }
4264         return 0;
4265
4266 }
4267
4268 uint32_t
4269 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4270 {
4271         uint32_t new_val = orig_val;
4272
4273         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4274                 new_val |= IXGBE_VMOLR_AUPE;
4275         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4276                 new_val |= IXGBE_VMOLR_ROMPE;
4277         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4278                 new_val |= IXGBE_VMOLR_ROPE;
4279         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4280                 new_val |= IXGBE_VMOLR_BAM;
4281         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4282                 new_val |= IXGBE_VMOLR_MPE;
4283
4284         return new_val;
4285 }
4286
4287 static int
4288 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4289                                uint16_t rx_mask, uint8_t on)
4290 {
4291         int val = 0;
4292
4293         struct ixgbe_hw *hw =
4294                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4295         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4296
4297         if (hw->mac.type == ixgbe_mac_82598EB) {
4298                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4299                              " on 82599 hardware and newer");
4300                 return -ENOTSUP;
4301         }
4302         if (ixgbe_vmdq_mode_check(hw) < 0)
4303                 return -ENOTSUP;
4304
4305         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4306
4307         if (on)
4308                 vmolr |= val;
4309         else
4310                 vmolr &= ~val;
4311
4312         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4313
4314         return 0;
4315 }
4316
4317 static int
4318 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4319 {
4320         uint32_t reg,addr;
4321         uint32_t val;
4322         const uint8_t bit1 = 0x1;
4323
4324         struct ixgbe_hw *hw =
4325                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4326
4327         if (ixgbe_vmdq_mode_check(hw) < 0)
4328                 return -ENOTSUP;
4329
4330         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4331         reg = IXGBE_READ_REG(hw, addr);
4332         val = bit1 << pool;
4333
4334         if (on)
4335                 reg |= val;
4336         else
4337                 reg &= ~val;
4338
4339         IXGBE_WRITE_REG(hw, addr,reg);
4340
4341         return 0;
4342 }
4343
4344 static int
4345 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4346 {
4347         uint32_t reg,addr;
4348         uint32_t val;
4349         const uint8_t bit1 = 0x1;
4350
4351         struct ixgbe_hw *hw =
4352                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4353
4354         if (ixgbe_vmdq_mode_check(hw) < 0)
4355                 return -ENOTSUP;
4356
4357         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4358         reg = IXGBE_READ_REG(hw, addr);
4359         val = bit1 << pool;
4360
4361         if (on)
4362                 reg |= val;
4363         else
4364                 reg &= ~val;
4365
4366         IXGBE_WRITE_REG(hw, addr,reg);
4367
4368         return 0;
4369 }
4370
4371 static int
4372 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4373                         uint64_t pool_mask, uint8_t vlan_on)
4374 {
4375         int ret = 0;
4376         uint16_t pool_idx;
4377         struct ixgbe_hw *hw =
4378                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4379
4380         if (ixgbe_vmdq_mode_check(hw) < 0)
4381                 return -ENOTSUP;
4382         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4383                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4384                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4385                         if (ret < 0)
4386                                 return ret;
4387         }
4388
4389         return ret;
4390 }
4391
4392 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4393 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4394 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4395 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4396 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4397         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4398         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4399
4400 static int
4401 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4402                         struct rte_eth_mirror_conf *mirror_conf,
4403                         uint8_t rule_id, uint8_t on)
4404 {
4405         uint32_t mr_ctl,vlvf;
4406         uint32_t mp_lsb = 0;
4407         uint32_t mv_msb = 0;
4408         uint32_t mv_lsb = 0;
4409         uint32_t mp_msb = 0;
4410         uint8_t i = 0;
4411         int reg_index = 0;
4412         uint64_t vlan_mask = 0;
4413
4414         const uint8_t pool_mask_offset = 32;
4415         const uint8_t vlan_mask_offset = 32;
4416         const uint8_t dst_pool_offset = 8;
4417         const uint8_t rule_mr_offset  = 4;
4418         const uint8_t mirror_rule_mask= 0x0F;
4419
4420         struct ixgbe_mirror_info *mr_info =
4421                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4422         struct ixgbe_hw *hw =
4423                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4424         uint8_t mirror_type = 0;
4425
4426         if (ixgbe_vmdq_mode_check(hw) < 0)
4427                 return -ENOTSUP;
4428
4429         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4430                 return -EINVAL;
4431
4432         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4433                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4434                         mirror_conf->rule_type);
4435                 return -EINVAL;
4436         }
4437
4438         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4439                 mirror_type |= IXGBE_MRCTL_VLME;
4440                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4441                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4442                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4443                                 /* search vlan id related pool vlan filter index */
4444                                 reg_index = ixgbe_find_vlvf_slot(hw,
4445                                                 mirror_conf->vlan.vlan_id[i]);
4446                                 if (reg_index < 0)
4447                                         return -EINVAL;
4448                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4449                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4450                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4451                                       mirror_conf->vlan.vlan_id[i]))
4452                                         vlan_mask |= (1ULL << reg_index);
4453                                 else
4454                                         return -EINVAL;
4455                         }
4456                 }
4457
4458                 if (on) {
4459                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4460                         mv_msb = vlan_mask >> vlan_mask_offset;
4461
4462                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4463                                                 mirror_conf->vlan.vlan_mask;
4464                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4465                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4466                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4467                                                 mirror_conf->vlan.vlan_id[i];
4468                         }
4469                 } else {
4470                         mv_lsb = 0;
4471                         mv_msb = 0;
4472                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4473                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4474                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4475                 }
4476         }
4477
4478         /*
4479          * if enable pool mirror, write related pool mask register,if disable
4480          * pool mirror, clear PFMRVM register
4481          */
4482         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4483                 mirror_type |= IXGBE_MRCTL_VPME;
4484                 if (on) {
4485                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4486                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4487                         mr_info->mr_conf[rule_id].pool_mask =
4488                                         mirror_conf->pool_mask;
4489
4490                 } else {
4491                         mp_lsb = 0;
4492                         mp_msb = 0;
4493                         mr_info->mr_conf[rule_id].pool_mask = 0;
4494                 }
4495         }
4496         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4497                 mirror_type |= IXGBE_MRCTL_UPME;
4498         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4499                 mirror_type |= IXGBE_MRCTL_DPME;
4500
4501         /* read  mirror control register and recalculate it */
4502         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4503
4504         if (on) {
4505                 mr_ctl |= mirror_type;
4506                 mr_ctl &= mirror_rule_mask;
4507                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4508         } else
4509                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4510
4511         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4512         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4513
4514         /* write mirrror control  register */
4515         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4516
4517         /* write pool mirrror control  register */
4518         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4519                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4520                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4521                                 mp_msb);
4522         }
4523         /* write VLAN mirrror control  register */
4524         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4525                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4526                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4527                                 mv_msb);
4528         }
4529
4530         return 0;
4531 }
4532
4533 static int
4534 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4535 {
4536         int mr_ctl = 0;
4537         uint32_t lsb_val = 0;
4538         uint32_t msb_val = 0;
4539         const uint8_t rule_mr_offset = 4;
4540
4541         struct ixgbe_hw *hw =
4542                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4543         struct ixgbe_mirror_info *mr_info =
4544                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4545
4546         if (ixgbe_vmdq_mode_check(hw) < 0)
4547                 return -ENOTSUP;
4548
4549         memset(&mr_info->mr_conf[rule_id], 0,
4550                 sizeof(struct rte_eth_mirror_conf));
4551
4552         /* clear PFVMCTL register */
4553         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4554
4555         /* clear pool mask register */
4556         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4557         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4558
4559         /* clear vlan mask register */
4560         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4561         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4562
4563         return 0;
4564 }
4565
4566 static int
4567 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4568 {
4569         uint32_t mask;
4570         struct ixgbe_hw *hw =
4571                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4572
4573         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4574         mask |= (1 << IXGBE_MISC_VEC_ID);
4575         RTE_SET_USED(queue_id);
4576         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4577
4578         rte_intr_enable(&dev->pci_dev->intr_handle);
4579
4580         return 0;
4581 }
4582
4583 static int
4584 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4585 {
4586         uint32_t mask;
4587         struct ixgbe_hw *hw =
4588                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4589
4590         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4591         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4592         RTE_SET_USED(queue_id);
4593         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4594
4595         return 0;
4596 }
4597
4598 static int
4599 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4600 {
4601         uint32_t mask;
4602         struct ixgbe_hw *hw =
4603                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4604         struct ixgbe_interrupt *intr =
4605                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4606
4607         if (queue_id < 16) {
4608                 ixgbe_disable_intr(hw);
4609                 intr->mask |= (1 << queue_id);
4610                 ixgbe_enable_intr(dev);
4611         } else if (queue_id < 32) {
4612                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4613                 mask &= (1 << queue_id);
4614                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4615         } else if (queue_id < 64) {
4616                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4617                 mask &= (1 << (queue_id - 32));
4618                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4619         }
4620         rte_intr_enable(&dev->pci_dev->intr_handle);
4621
4622         return 0;
4623 }
4624
4625 static int
4626 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4627 {
4628         uint32_t mask;
4629         struct ixgbe_hw *hw =
4630                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4631         struct ixgbe_interrupt *intr =
4632                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4633
4634         if (queue_id < 16) {
4635                 ixgbe_disable_intr(hw);
4636                 intr->mask &= ~(1 << queue_id);
4637                 ixgbe_enable_intr(dev);
4638         } else if (queue_id < 32) {
4639                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4640                 mask &= ~(1 << queue_id);
4641                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4642         } else if (queue_id < 64) {
4643                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4644                 mask &= ~(1 << (queue_id - 32));
4645                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4646         }
4647
4648         return 0;
4649 }
4650
4651 static void
4652 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4653                      uint8_t queue, uint8_t msix_vector)
4654 {
4655         uint32_t tmp, idx;
4656
4657         if (direction == -1) {
4658                 /* other causes */
4659                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4660                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4661                 tmp &= ~0xFF;
4662                 tmp |= msix_vector;
4663                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4664         } else {
4665                 /* rx or tx cause */
4666                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4667                 idx = ((16 * (queue & 1)) + (8 * direction));
4668                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4669                 tmp &= ~(0xFF << idx);
4670                 tmp |= (msix_vector << idx);
4671                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4672         }
4673 }
4674
4675 /**
4676  * set the IVAR registers, mapping interrupt causes to vectors
4677  * @param hw
4678  *  pointer to ixgbe_hw struct
4679  * @direction
4680  *  0 for Rx, 1 for Tx, -1 for other causes
4681  * @queue
4682  *  queue to map the corresponding interrupt to
4683  * @msix_vector
4684  *  the vector to map to the corresponding queue
4685  */
4686 static void
4687 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4688                    uint8_t queue, uint8_t msix_vector)
4689 {
4690         uint32_t tmp, idx;
4691
4692         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4693         if (hw->mac.type == ixgbe_mac_82598EB) {
4694                 if (direction == -1)
4695                         direction = 0;
4696                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4697                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4698                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4699                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4700                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4701         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4702                         (hw->mac.type == ixgbe_mac_X540)) {
4703                 if (direction == -1) {
4704                         /* other causes */
4705                         idx = ((queue & 1) * 8);
4706                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4707                         tmp &= ~(0xFF << idx);
4708                         tmp |= (msix_vector << idx);
4709                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4710                 } else {
4711                         /* rx or tx causes */
4712                         idx = ((16 * (queue & 1)) + (8 * direction));
4713                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4714                         tmp &= ~(0xFF << idx);
4715                         tmp |= (msix_vector << idx);
4716                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4717                 }
4718         }
4719 }
4720
4721 static void
4722 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4723 {
4724         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4725         struct ixgbe_hw *hw =
4726                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4727         uint32_t q_idx;
4728         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4729
4730         /* won't configure msix register if no mapping is done
4731          * between intr vector and event fd.
4732          */
4733         if (!rte_intr_dp_is_en(intr_handle))
4734                 return;
4735
4736         /* Configure all RX queues of VF */
4737         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4738                 /* Force all queue use vector 0,
4739                  * as IXGBE_VF_MAXMSIVECOTR = 1
4740                  */
4741                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4742                 intr_handle->intr_vec[q_idx] = vector_idx;
4743         }
4744
4745         /* Configure VF other cause ivar */
4746         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4747 }
4748
4749 /**
4750  * Sets up the hardware to properly generate MSI-X interrupts
4751  * @hw
4752  *  board private structure
4753  */
4754 static void
4755 ixgbe_configure_msix(struct rte_eth_dev *dev)
4756 {
4757         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4758         struct ixgbe_hw *hw =
4759                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4760         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4761         uint32_t vec = IXGBE_MISC_VEC_ID;
4762         uint32_t mask;
4763         uint32_t gpie;
4764
4765         /* won't configure msix register if no mapping is done
4766          * between intr vector and event fd
4767          */
4768         if (!rte_intr_dp_is_en(intr_handle))
4769                 return;
4770
4771         if (rte_intr_allow_others(intr_handle))
4772                 vec = base = IXGBE_RX_VEC_START;
4773
4774         /* setup GPIE for MSI-x mode */
4775         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4776         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4777                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4778         /* auto clearing and auto setting corresponding bits in EIMS
4779          * when MSI-X interrupt is triggered
4780          */
4781         if (hw->mac.type == ixgbe_mac_82598EB) {
4782                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4783         } else {
4784                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4785                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4786         }
4787         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4788
4789         /* Populate the IVAR table and set the ITR values to the
4790          * corresponding register.
4791          */
4792         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4793              queue_id++) {
4794                 /* by default, 1:1 mapping */
4795                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4796                 intr_handle->intr_vec[queue_id] = vec;
4797                 if (vec < base + intr_handle->nb_efd - 1)
4798                         vec++;
4799         }
4800
4801         switch (hw->mac.type) {
4802         case ixgbe_mac_82598EB:
4803                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4804                                    IXGBE_MISC_VEC_ID);
4805                 break;
4806         case ixgbe_mac_82599EB:
4807         case ixgbe_mac_X540:
4808                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4809                 break;
4810         default:
4811                 break;
4812         }
4813         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4814                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4815
4816         /* set up to autoclear timer, and the vectors */
4817         mask = IXGBE_EIMS_ENABLE_MASK;
4818         mask &= ~(IXGBE_EIMS_OTHER |
4819                   IXGBE_EIMS_MAILBOX |
4820                   IXGBE_EIMS_LSC);
4821
4822         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4823 }
4824
4825 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4826         uint16_t queue_idx, uint16_t tx_rate)
4827 {
4828         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4829         uint32_t rf_dec, rf_int;
4830         uint32_t bcnrc_val;
4831         uint16_t link_speed = dev->data->dev_link.link_speed;
4832
4833         if (queue_idx >= hw->mac.max_tx_queues)
4834                 return -EINVAL;
4835
4836         if (tx_rate != 0) {
4837                 /* Calculate the rate factor values to set */
4838                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4839                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4840                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4841
4842                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4843                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4844                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4845                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4846         } else {
4847                 bcnrc_val = 0;
4848         }
4849
4850         /*
4851          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4852          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4853          * set as 0x4.
4854          */
4855         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4856                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4857                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4858                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4859                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4860         else
4861                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4862                         IXGBE_MMW_SIZE_DEFAULT);
4863
4864         /* Set RTTBCNRC of queue X */
4865         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4866         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4867         IXGBE_WRITE_FLUSH(hw);
4868
4869         return 0;
4870 }
4871
4872 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4873         uint16_t tx_rate, uint64_t q_msk)
4874 {
4875         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4876         struct ixgbe_vf_info *vfinfo =
4877                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4878         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4879         uint32_t queue_stride =
4880                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4881         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4882         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4883         uint16_t total_rate = 0;
4884
4885         if (queue_end >= hw->mac.max_tx_queues)
4886                 return -EINVAL;
4887
4888         if (vfinfo != NULL) {
4889                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4890                         if (vf_idx == vf)
4891                                 continue;
4892                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4893                                 idx++)
4894                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4895                 }
4896         } else
4897                 return -EINVAL;
4898
4899         /* Store tx_rate for this vf. */
4900         for (idx = 0; idx < nb_q_per_pool; idx++) {
4901                 if (((uint64_t)0x1 << idx) & q_msk) {
4902                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
4903                                 vfinfo[vf].tx_rate[idx] = tx_rate;
4904                         total_rate += tx_rate;
4905                 }
4906         }
4907
4908         if (total_rate > dev->data->dev_link.link_speed) {
4909                 /*
4910                  * Reset stored TX rate of the VF if it causes exceed
4911                  * link speed.
4912                  */
4913                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4914                 return -EINVAL;
4915         }
4916
4917         /* Set RTTBCNRC of each queue/pool for vf X  */
4918         for (; queue_idx <= queue_end; queue_idx++) {
4919                 if (0x1 & q_msk)
4920                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4921                 q_msk = q_msk >> 1;
4922         }
4923
4924         return 0;
4925 }
4926
4927 static void
4928 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4929                      __attribute__((unused)) uint32_t index,
4930                      __attribute__((unused)) uint32_t pool)
4931 {
4932         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4933         int diag;
4934
4935         /*
4936          * On a 82599 VF, adding again the same MAC addr is not an idempotent
4937          * operation. Trap this case to avoid exhausting the [very limited]
4938          * set of PF resources used to store VF MAC addresses.
4939          */
4940         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4941                 return;
4942         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4943         if (diag == 0)
4944                 return;
4945         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4946 }
4947
4948 static void
4949 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4950 {
4951         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4952         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4953         struct ether_addr *mac_addr;
4954         uint32_t i;
4955         int diag;
4956
4957         /*
4958          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4959          * not support the deletion of a given MAC address.
4960          * Instead, it imposes to delete all MAC addresses, then to add again
4961          * all MAC addresses with the exception of the one to be deleted.
4962          */
4963         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4964
4965         /*
4966          * Add again all MAC addresses, with the exception of the deleted one
4967          * and of the permanent MAC address.
4968          */
4969         for (i = 0, mac_addr = dev->data->mac_addrs;
4970              i < hw->mac.num_rar_entries; i++, mac_addr++) {
4971                 /* Skip the deleted MAC address */
4972                 if (i == index)
4973                         continue;
4974                 /* Skip NULL MAC addresses */
4975                 if (is_zero_ether_addr(mac_addr))
4976                         continue;
4977                 /* Skip the permanent MAC address */
4978                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4979                         continue;
4980                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4981                 if (diag != 0)
4982                         PMD_DRV_LOG(ERR,
4983                                     "Adding again MAC address "
4984                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
4985                                     "diag=%d",
4986                                     mac_addr->addr_bytes[0],
4987                                     mac_addr->addr_bytes[1],
4988                                     mac_addr->addr_bytes[2],
4989                                     mac_addr->addr_bytes[3],
4990                                     mac_addr->addr_bytes[4],
4991                                     mac_addr->addr_bytes[5],
4992                                     diag);
4993         }
4994 }
4995
4996 static void
4997 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4998 {
4999         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5000
5001         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5002 }
5003
5004 #define MAC_TYPE_FILTER_SUP(type)    do {\
5005         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5006                 (type) != ixgbe_mac_X550)\
5007                 return -ENOTSUP;\
5008 } while (0)
5009
5010 static int
5011 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5012                         struct rte_eth_syn_filter *filter,
5013                         bool add)
5014 {
5015         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5016         uint32_t synqf;
5017
5018         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5019                 return -EINVAL;
5020
5021         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5022
5023         if (add) {
5024                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5025                         return -EINVAL;
5026                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5027                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5028
5029                 if (filter->hig_pri)
5030                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5031                 else
5032                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5033         } else {
5034                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5035                         return -ENOENT;
5036                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5037         }
5038         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5039         IXGBE_WRITE_FLUSH(hw);
5040         return 0;
5041 }
5042
5043 static int
5044 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5045                         struct rte_eth_syn_filter *filter)
5046 {
5047         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5048         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5049
5050         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5051                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5052                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5053                 return 0;
5054         }
5055         return -ENOENT;
5056 }
5057
5058 static int
5059 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5060                         enum rte_filter_op filter_op,
5061                         void *arg)
5062 {
5063         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5064         int ret;
5065
5066         MAC_TYPE_FILTER_SUP(hw->mac.type);
5067
5068         if (filter_op == RTE_ETH_FILTER_NOP)
5069                 return 0;
5070
5071         if (arg == NULL) {
5072                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5073                             filter_op);
5074                 return -EINVAL;
5075         }
5076
5077         switch (filter_op) {
5078         case RTE_ETH_FILTER_ADD:
5079                 ret = ixgbe_syn_filter_set(dev,
5080                                 (struct rte_eth_syn_filter *)arg,
5081                                 TRUE);
5082                 break;
5083         case RTE_ETH_FILTER_DELETE:
5084                 ret = ixgbe_syn_filter_set(dev,
5085                                 (struct rte_eth_syn_filter *)arg,
5086                                 FALSE);
5087                 break;
5088         case RTE_ETH_FILTER_GET:
5089                 ret = ixgbe_syn_filter_get(dev,
5090                                 (struct rte_eth_syn_filter *)arg);
5091                 break;
5092         default:
5093                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5094                 ret = -EINVAL;
5095                 break;
5096         }
5097
5098         return ret;
5099 }
5100
5101
5102 static inline enum ixgbe_5tuple_protocol
5103 convert_protocol_type(uint8_t protocol_value)
5104 {
5105         if (protocol_value == IPPROTO_TCP)
5106                 return IXGBE_FILTER_PROTOCOL_TCP;
5107         else if (protocol_value == IPPROTO_UDP)
5108                 return IXGBE_FILTER_PROTOCOL_UDP;
5109         else if (protocol_value == IPPROTO_SCTP)
5110                 return IXGBE_FILTER_PROTOCOL_SCTP;
5111         else
5112                 return IXGBE_FILTER_PROTOCOL_NONE;
5113 }
5114
5115 /*
5116  * add a 5tuple filter
5117  *
5118  * @param
5119  * dev: Pointer to struct rte_eth_dev.
5120  * index: the index the filter allocates.
5121  * filter: ponter to the filter that will be added.
5122  * rx_queue: the queue id the filter assigned to.
5123  *
5124  * @return
5125  *    - On success, zero.
5126  *    - On failure, a negative value.
5127  */
5128 static int
5129 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5130                         struct ixgbe_5tuple_filter *filter)
5131 {
5132         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5133         struct ixgbe_filter_info *filter_info =
5134                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5135         int i, idx, shift;
5136         uint32_t ftqf, sdpqf;
5137         uint32_t l34timir = 0;
5138         uint8_t mask = 0xff;
5139
5140         /*
5141          * look for an unused 5tuple filter index,
5142          * and insert the filter to list.
5143          */
5144         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5145                 idx = i / (sizeof(uint32_t) * NBBY);
5146                 shift = i % (sizeof(uint32_t) * NBBY);
5147                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5148                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5149                         filter->index = i;
5150                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5151                                           filter,
5152                                           entries);
5153                         break;
5154                 }
5155         }
5156         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5157                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5158                 return -ENOSYS;
5159         }
5160
5161         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5162                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5163         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5164
5165         ftqf = (uint32_t)(filter->filter_info.proto &
5166                 IXGBE_FTQF_PROTOCOL_MASK);
5167         ftqf |= (uint32_t)((filter->filter_info.priority &
5168                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5169         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5170                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5171         if (filter->filter_info.dst_ip_mask == 0)
5172                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5173         if (filter->filter_info.src_port_mask == 0)
5174                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5175         if (filter->filter_info.dst_port_mask == 0)
5176                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5177         if (filter->filter_info.proto_mask == 0)
5178                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5179         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5180         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5181         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5182
5183         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5184         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5185         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5186         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5187
5188         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5189         l34timir |= (uint32_t)(filter->queue <<
5190                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5191         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5192         return 0;
5193 }
5194
5195 /*
5196  * remove a 5tuple filter
5197  *
5198  * @param
5199  * dev: Pointer to struct rte_eth_dev.
5200  * filter: the pointer of the filter will be removed.
5201  */
5202 static void
5203 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5204                         struct ixgbe_5tuple_filter *filter)
5205 {
5206         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5207         struct ixgbe_filter_info *filter_info =
5208                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5209         uint16_t index = filter->index;
5210
5211         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5212                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5213         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5214         rte_free(filter);
5215
5216         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5217         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5218         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5219         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5220         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5221 }
5222
5223 static int
5224 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5225 {
5226         struct ixgbe_hw *hw;
5227         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5228
5229         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5230
5231         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5232                 return -EINVAL;
5233
5234         /* refuse mtu that requires the support of scattered packets when this
5235          * feature has not been enabled before. */
5236         if (!dev->data->scattered_rx &&
5237             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5238              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5239                 return -EINVAL;
5240
5241         /*
5242          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5243          * request of the version 2.0 of the mailbox API.
5244          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5245          * of the mailbox API.
5246          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5247          * prior to 3.11.33 which contains the following change:
5248          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5249          */
5250         ixgbevf_rlpml_set_vf(hw, max_frame);
5251
5252         /* update max frame size */
5253         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5254         return 0;
5255 }
5256
5257 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5258         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5259                 return -ENOTSUP;\
5260 } while (0)
5261
5262 static inline struct ixgbe_5tuple_filter *
5263 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5264                         struct ixgbe_5tuple_filter_info *key)
5265 {
5266         struct ixgbe_5tuple_filter *it;
5267
5268         TAILQ_FOREACH(it, filter_list, entries) {
5269                 if (memcmp(key, &it->filter_info,
5270                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5271                         return it;
5272                 }
5273         }
5274         return NULL;
5275 }
5276
5277 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5278 static inline int
5279 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5280                         struct ixgbe_5tuple_filter_info *filter_info)
5281 {
5282         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5283                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5284                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5285                 return -EINVAL;
5286
5287         switch (filter->dst_ip_mask) {
5288         case UINT32_MAX:
5289                 filter_info->dst_ip_mask = 0;
5290                 filter_info->dst_ip = filter->dst_ip;
5291                 break;
5292         case 0:
5293                 filter_info->dst_ip_mask = 1;
5294                 break;
5295         default:
5296                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5297                 return -EINVAL;
5298         }
5299
5300         switch (filter->src_ip_mask) {
5301         case UINT32_MAX:
5302                 filter_info->src_ip_mask = 0;
5303                 filter_info->src_ip = filter->src_ip;
5304                 break;
5305         case 0:
5306                 filter_info->src_ip_mask = 1;
5307                 break;
5308         default:
5309                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5310                 return -EINVAL;
5311         }
5312
5313         switch (filter->dst_port_mask) {
5314         case UINT16_MAX:
5315                 filter_info->dst_port_mask = 0;
5316                 filter_info->dst_port = filter->dst_port;
5317                 break;
5318         case 0:
5319                 filter_info->dst_port_mask = 1;
5320                 break;
5321         default:
5322                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5323                 return -EINVAL;
5324         }
5325
5326         switch (filter->src_port_mask) {
5327         case UINT16_MAX:
5328                 filter_info->src_port_mask = 0;
5329                 filter_info->src_port = filter->src_port;
5330                 break;
5331         case 0:
5332                 filter_info->src_port_mask = 1;
5333                 break;
5334         default:
5335                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5336                 return -EINVAL;
5337         }
5338
5339         switch (filter->proto_mask) {
5340         case UINT8_MAX:
5341                 filter_info->proto_mask = 0;
5342                 filter_info->proto =
5343                         convert_protocol_type(filter->proto);
5344                 break;
5345         case 0:
5346                 filter_info->proto_mask = 1;
5347                 break;
5348         default:
5349                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5350                 return -EINVAL;
5351         }
5352
5353         filter_info->priority = (uint8_t)filter->priority;
5354         return 0;
5355 }
5356
5357 /*
5358  * add or delete a ntuple filter
5359  *
5360  * @param
5361  * dev: Pointer to struct rte_eth_dev.
5362  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5363  * add: if true, add filter, if false, remove filter
5364  *
5365  * @return
5366  *    - On success, zero.
5367  *    - On failure, a negative value.
5368  */
5369 static int
5370 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5371                         struct rte_eth_ntuple_filter *ntuple_filter,
5372                         bool add)
5373 {
5374         struct ixgbe_filter_info *filter_info =
5375                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5376         struct ixgbe_5tuple_filter_info filter_5tuple;
5377         struct ixgbe_5tuple_filter *filter;
5378         int ret;
5379
5380         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5381                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5382                 return -EINVAL;
5383         }
5384
5385         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5386         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5387         if (ret < 0)
5388                 return ret;
5389
5390         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5391                                          &filter_5tuple);
5392         if (filter != NULL && add) {
5393                 PMD_DRV_LOG(ERR, "filter exists.");
5394                 return -EEXIST;
5395         }
5396         if (filter == NULL && !add) {
5397                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5398                 return -ENOENT;
5399         }
5400
5401         if (add) {
5402                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5403                                 sizeof(struct ixgbe_5tuple_filter), 0);
5404                 if (filter == NULL)
5405                         return -ENOMEM;
5406                 (void)rte_memcpy(&filter->filter_info,
5407                                  &filter_5tuple,
5408                                  sizeof(struct ixgbe_5tuple_filter_info));
5409                 filter->queue = ntuple_filter->queue;
5410                 ret = ixgbe_add_5tuple_filter(dev, filter);
5411                 if (ret < 0) {
5412                         rte_free(filter);
5413                         return ret;
5414                 }
5415         } else
5416                 ixgbe_remove_5tuple_filter(dev, filter);
5417
5418         return 0;
5419 }
5420
5421 /*
5422  * get a ntuple filter
5423  *
5424  * @param
5425  * dev: Pointer to struct rte_eth_dev.
5426  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5427  *
5428  * @return
5429  *    - On success, zero.
5430  *    - On failure, a negative value.
5431  */
5432 static int
5433 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5434                         struct rte_eth_ntuple_filter *ntuple_filter)
5435 {
5436         struct ixgbe_filter_info *filter_info =
5437                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5438         struct ixgbe_5tuple_filter_info filter_5tuple;
5439         struct ixgbe_5tuple_filter *filter;
5440         int ret;
5441
5442         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5443                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5444                 return -EINVAL;
5445         }
5446
5447         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5448         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5449         if (ret < 0)
5450                 return ret;
5451
5452         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5453                                          &filter_5tuple);
5454         if (filter == NULL) {
5455                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5456                 return -ENOENT;
5457         }
5458         ntuple_filter->queue = filter->queue;
5459         return 0;
5460 }
5461
5462 /*
5463  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5464  * @dev: pointer to rte_eth_dev structure
5465  * @filter_op:operation will be taken.
5466  * @arg: a pointer to specific structure corresponding to the filter_op
5467  *
5468  * @return
5469  *    - On success, zero.
5470  *    - On failure, a negative value.
5471  */
5472 static int
5473 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5474                                 enum rte_filter_op filter_op,
5475                                 void *arg)
5476 {
5477         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5478         int ret;
5479
5480         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5481
5482         if (filter_op == RTE_ETH_FILTER_NOP)
5483                 return 0;
5484
5485         if (arg == NULL) {
5486                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5487                             filter_op);
5488                 return -EINVAL;
5489         }
5490
5491         switch (filter_op) {
5492         case RTE_ETH_FILTER_ADD:
5493                 ret = ixgbe_add_del_ntuple_filter(dev,
5494                         (struct rte_eth_ntuple_filter *)arg,
5495                         TRUE);
5496                 break;
5497         case RTE_ETH_FILTER_DELETE:
5498                 ret = ixgbe_add_del_ntuple_filter(dev,
5499                         (struct rte_eth_ntuple_filter *)arg,
5500                         FALSE);
5501                 break;
5502         case RTE_ETH_FILTER_GET:
5503                 ret = ixgbe_get_ntuple_filter(dev,
5504                         (struct rte_eth_ntuple_filter *)arg);
5505                 break;
5506         default:
5507                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5508                 ret = -EINVAL;
5509                 break;
5510         }
5511         return ret;
5512 }
5513
5514 static inline int
5515 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5516                         uint16_t ethertype)
5517 {
5518         int i;
5519
5520         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5521                 if (filter_info->ethertype_filters[i] == ethertype &&
5522                     (filter_info->ethertype_mask & (1 << i)))
5523                         return i;
5524         }
5525         return -1;
5526 }
5527
5528 static inline int
5529 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5530                         uint16_t ethertype)
5531 {
5532         int i;
5533
5534         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5535                 if (!(filter_info->ethertype_mask & (1 << i))) {
5536                         filter_info->ethertype_mask |= 1 << i;
5537                         filter_info->ethertype_filters[i] = ethertype;
5538                         return i;
5539                 }
5540         }
5541         return -1;
5542 }
5543
5544 static inline int
5545 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5546                         uint8_t idx)
5547 {
5548         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5549                 return -1;
5550         filter_info->ethertype_mask &= ~(1 << idx);
5551         filter_info->ethertype_filters[idx] = 0;
5552         return idx;
5553 }
5554
5555 static int
5556 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5557                         struct rte_eth_ethertype_filter *filter,
5558                         bool add)
5559 {
5560         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5561         struct ixgbe_filter_info *filter_info =
5562                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5563         uint32_t etqf = 0;
5564         uint32_t etqs = 0;
5565         int ret;
5566
5567         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5568                 return -EINVAL;
5569
5570         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5571                 filter->ether_type == ETHER_TYPE_IPv6) {
5572                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5573                         " ethertype filter.", filter->ether_type);
5574                 return -EINVAL;
5575         }
5576
5577         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5578                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5579                 return -EINVAL;
5580         }
5581         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5582                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5583                 return -EINVAL;
5584         }
5585
5586         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5587         if (ret >= 0 && add) {
5588                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5589                             filter->ether_type);
5590                 return -EEXIST;
5591         }
5592         if (ret < 0 && !add) {
5593                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5594                             filter->ether_type);
5595                 return -ENOENT;
5596         }
5597
5598         if (add) {
5599                 ret = ixgbe_ethertype_filter_insert(filter_info,
5600                         filter->ether_type);
5601                 if (ret < 0) {
5602                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5603                         return -ENOSYS;
5604                 }
5605                 etqf = IXGBE_ETQF_FILTER_EN;
5606                 etqf |= (uint32_t)filter->ether_type;
5607                 etqs |= (uint32_t)((filter->queue <<
5608                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5609                                     IXGBE_ETQS_RX_QUEUE);
5610                 etqs |= IXGBE_ETQS_QUEUE_EN;
5611         } else {
5612                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5613                 if (ret < 0)
5614                         return -ENOSYS;
5615         }
5616         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5617         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5618         IXGBE_WRITE_FLUSH(hw);
5619
5620         return 0;
5621 }
5622
5623 static int
5624 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5625                         struct rte_eth_ethertype_filter *filter)
5626 {
5627         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5628         struct ixgbe_filter_info *filter_info =
5629                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5630         uint32_t etqf, etqs;
5631         int ret;
5632
5633         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5634         if (ret < 0) {
5635                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5636                             filter->ether_type);
5637                 return -ENOENT;
5638         }
5639
5640         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5641         if (etqf & IXGBE_ETQF_FILTER_EN) {
5642                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5643                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5644                 filter->flags = 0;
5645                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5646                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5647                 return 0;
5648         }
5649         return -ENOENT;
5650 }
5651
5652 /*
5653  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5654  * @dev: pointer to rte_eth_dev structure
5655  * @filter_op:operation will be taken.
5656  * @arg: a pointer to specific structure corresponding to the filter_op
5657  */
5658 static int
5659 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5660                                 enum rte_filter_op filter_op,
5661                                 void *arg)
5662 {
5663         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5664         int ret;
5665
5666         MAC_TYPE_FILTER_SUP(hw->mac.type);
5667
5668         if (filter_op == RTE_ETH_FILTER_NOP)
5669                 return 0;
5670
5671         if (arg == NULL) {
5672                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5673                             filter_op);
5674                 return -EINVAL;
5675         }
5676
5677         switch (filter_op) {
5678         case RTE_ETH_FILTER_ADD:
5679                 ret = ixgbe_add_del_ethertype_filter(dev,
5680                         (struct rte_eth_ethertype_filter *)arg,
5681                         TRUE);
5682                 break;
5683         case RTE_ETH_FILTER_DELETE:
5684                 ret = ixgbe_add_del_ethertype_filter(dev,
5685                         (struct rte_eth_ethertype_filter *)arg,
5686                         FALSE);
5687                 break;
5688         case RTE_ETH_FILTER_GET:
5689                 ret = ixgbe_get_ethertype_filter(dev,
5690                         (struct rte_eth_ethertype_filter *)arg);
5691                 break;
5692         default:
5693                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5694                 ret = -EINVAL;
5695                 break;
5696         }
5697         return ret;
5698 }
5699
5700 static int
5701 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5702                      enum rte_filter_type filter_type,
5703                      enum rte_filter_op filter_op,
5704                      void *arg)
5705 {
5706         int ret = -EINVAL;
5707
5708         switch (filter_type) {
5709         case RTE_ETH_FILTER_NTUPLE:
5710                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5711                 break;
5712         case RTE_ETH_FILTER_ETHERTYPE:
5713                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5714                 break;
5715         case RTE_ETH_FILTER_SYN:
5716                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5717                 break;
5718         case RTE_ETH_FILTER_FDIR:
5719                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5720                 break;
5721         case RTE_ETH_FILTER_L2_TUNNEL:
5722                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5723                 break;
5724         default:
5725                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5726                                                         filter_type);
5727                 break;
5728         }
5729
5730         return ret;
5731 }
5732
5733 static u8 *
5734 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5735                         u8 **mc_addr_ptr, u32 *vmdq)
5736 {
5737         u8 *mc_addr;
5738
5739         *vmdq = 0;
5740         mc_addr = *mc_addr_ptr;
5741         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5742         return mc_addr;
5743 }
5744
5745 static int
5746 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5747                           struct ether_addr *mc_addr_set,
5748                           uint32_t nb_mc_addr)
5749 {
5750         struct ixgbe_hw *hw;
5751         u8 *mc_addr_list;
5752
5753         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5754         mc_addr_list = (u8 *)mc_addr_set;
5755         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5756                                          ixgbe_dev_addr_list_itr, TRUE);
5757 }
5758
5759 static uint64_t
5760 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5761 {
5762         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5763         uint64_t systime_cycles;
5764
5765         switch (hw->mac.type) {
5766         case ixgbe_mac_X550:
5767                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5768                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5769                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5770                                 * NSEC_PER_SEC;
5771                 break;
5772         default:
5773                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5774                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5775                                 << 32;
5776         }
5777
5778         return systime_cycles;
5779 }
5780
5781 static uint64_t
5782 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5783 {
5784         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5785         uint64_t rx_tstamp_cycles;
5786
5787         switch (hw->mac.type) {
5788         case ixgbe_mac_X550:
5789                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5790                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5791                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5792                                 * NSEC_PER_SEC;
5793                 break;
5794         default:
5795                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5796                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5797                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5798                                 << 32;
5799         }
5800
5801         return rx_tstamp_cycles;
5802 }
5803
5804 static uint64_t
5805 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5806 {
5807         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5808         uint64_t tx_tstamp_cycles;
5809
5810         switch (hw->mac.type) {
5811         case ixgbe_mac_X550:
5812                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5813                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5814                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5815                                 * NSEC_PER_SEC;
5816                 break;
5817         default:
5818                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5819                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5820                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5821                                 << 32;
5822         }
5823
5824         return tx_tstamp_cycles;
5825 }
5826
5827 static void
5828 ixgbe_start_timecounters(struct rte_eth_dev *dev)
5829 {
5830         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5831         struct ixgbe_adapter *adapter =
5832                 (struct ixgbe_adapter *)dev->data->dev_private;
5833         struct rte_eth_link link;
5834         uint32_t incval = 0;
5835         uint32_t shift = 0;
5836
5837         /* Get current link speed. */
5838         memset(&link, 0, sizeof(link));
5839         ixgbe_dev_link_update(dev, 1);
5840         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
5841
5842         switch (link.link_speed) {
5843         case ETH_LINK_SPEED_100:
5844                 incval = IXGBE_INCVAL_100;
5845                 shift = IXGBE_INCVAL_SHIFT_100;
5846                 break;
5847         case ETH_LINK_SPEED_1000:
5848                 incval = IXGBE_INCVAL_1GB;
5849                 shift = IXGBE_INCVAL_SHIFT_1GB;
5850                 break;
5851         case ETH_LINK_SPEED_10000:
5852         default:
5853                 incval = IXGBE_INCVAL_10GB;
5854                 shift = IXGBE_INCVAL_SHIFT_10GB;
5855                 break;
5856         }
5857
5858         switch (hw->mac.type) {
5859         case ixgbe_mac_X550:
5860                 /* Independent of link speed. */
5861                 incval = 1;
5862                 /* Cycles read will be interpreted as ns. */
5863                 shift = 0;
5864                 /* Fall-through */
5865         case ixgbe_mac_X540:
5866                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
5867                 break;
5868         case ixgbe_mac_82599EB:
5869                 incval >>= IXGBE_INCVAL_SHIFT_82599;
5870                 shift -= IXGBE_INCVAL_SHIFT_82599;
5871                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
5872                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
5873                 break;
5874         default:
5875                 /* Not supported. */
5876                 return;
5877         }
5878
5879         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5880         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5881         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5882
5883         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5884         adapter->systime_tc.cc_shift = shift;
5885         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5886
5887         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5888         adapter->rx_tstamp_tc.cc_shift = shift;
5889         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5890
5891         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5892         adapter->tx_tstamp_tc.cc_shift = shift;
5893         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5894 }
5895
5896 static int
5897 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5898 {
5899         struct ixgbe_adapter *adapter =
5900                         (struct ixgbe_adapter *)dev->data->dev_private;
5901
5902         adapter->systime_tc.nsec += delta;
5903         adapter->rx_tstamp_tc.nsec += delta;
5904         adapter->tx_tstamp_tc.nsec += delta;
5905
5906         return 0;
5907 }
5908
5909 static int
5910 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5911 {
5912         uint64_t ns;
5913         struct ixgbe_adapter *adapter =
5914                         (struct ixgbe_adapter *)dev->data->dev_private;
5915
5916         ns = rte_timespec_to_ns(ts);
5917         /* Set the timecounters to a new value. */
5918         adapter->systime_tc.nsec = ns;
5919         adapter->rx_tstamp_tc.nsec = ns;
5920         adapter->tx_tstamp_tc.nsec = ns;
5921
5922         return 0;
5923 }
5924
5925 static int
5926 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5927 {
5928         uint64_t ns, systime_cycles;
5929         struct ixgbe_adapter *adapter =
5930                         (struct ixgbe_adapter *)dev->data->dev_private;
5931
5932         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
5933         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5934         *ts = rte_ns_to_timespec(ns);
5935
5936         return 0;
5937 }
5938
5939 static int
5940 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5941 {
5942         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5943         uint32_t tsync_ctl;
5944         uint32_t tsauxc;
5945
5946         /* Stop the timesync system time. */
5947         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
5948         /* Reset the timesync system time value. */
5949         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
5950         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
5951
5952         /* Enable system time for platforms where it isn't on by default. */
5953         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5954         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5955         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5956
5957         ixgbe_start_timecounters(dev);
5958
5959         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5960         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5961                         (ETHER_TYPE_1588 |
5962                          IXGBE_ETQF_FILTER_EN |
5963                          IXGBE_ETQF_1588));
5964
5965         /* Enable timestamping of received PTP packets. */
5966         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5967         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5968         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5969
5970         /* Enable timestamping of transmitted PTP packets. */
5971         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5972         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5973         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5974
5975         IXGBE_WRITE_FLUSH(hw);
5976
5977         return 0;
5978 }
5979
5980 static int
5981 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5982 {
5983         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5984         uint32_t tsync_ctl;
5985
5986         /* Disable timestamping of transmitted PTP packets. */
5987         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5988         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5989         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5990
5991         /* Disable timestamping of received PTP packets. */
5992         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5993         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5994         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5995
5996         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5997         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5998
5999         /* Stop incrementating the System Time registers. */
6000         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6001
6002         return 0;
6003 }
6004
6005 static int
6006 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6007                                  struct timespec *timestamp,
6008                                  uint32_t flags __rte_unused)
6009 {
6010         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6011         struct ixgbe_adapter *adapter =
6012                 (struct ixgbe_adapter *)dev->data->dev_private;
6013         uint32_t tsync_rxctl;
6014         uint64_t rx_tstamp_cycles;
6015         uint64_t ns;
6016
6017         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6018         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6019                 return -EINVAL;
6020
6021         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6022         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6023         *timestamp = rte_ns_to_timespec(ns);
6024
6025         return  0;
6026 }
6027
6028 static int
6029 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6030                                  struct timespec *timestamp)
6031 {
6032         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6033         struct ixgbe_adapter *adapter =
6034                 (struct ixgbe_adapter *)dev->data->dev_private;
6035         uint32_t tsync_txctl;
6036         uint64_t tx_tstamp_cycles;
6037         uint64_t ns;
6038
6039         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6040         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6041                 return -EINVAL;
6042
6043         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6044         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6045         *timestamp = rte_ns_to_timespec(ns);
6046
6047         return 0;
6048 }
6049
6050 static int
6051 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6052 {
6053         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6054         int count = 0;
6055         int g_ind = 0;
6056         const struct reg_info *reg_group;
6057         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6058                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6059
6060         while ((reg_group = reg_set[g_ind++]))
6061                 count += ixgbe_regs_group_count(reg_group);
6062
6063         return count;
6064 }
6065
6066 static int
6067 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6068 {
6069         int count = 0;
6070         int g_ind = 0;
6071         const struct reg_info *reg_group;
6072
6073         while ((reg_group = ixgbevf_regs[g_ind++]))
6074                 count += ixgbe_regs_group_count(reg_group);
6075
6076         return count;
6077 }
6078
6079 static int
6080 ixgbe_get_regs(struct rte_eth_dev *dev,
6081               struct rte_dev_reg_info *regs)
6082 {
6083         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6084         uint32_t *data = regs->data;
6085         int g_ind = 0;
6086         int count = 0;
6087         const struct reg_info *reg_group;
6088         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6089                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6090
6091         /* Support only full register dump */
6092         if ((regs->length == 0) ||
6093             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6094                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6095                         hw->device_id;
6096                 while ((reg_group = reg_set[g_ind++]))
6097                         count += ixgbe_read_regs_group(dev, &data[count],
6098                                 reg_group);
6099                 return 0;
6100         }
6101
6102         return -ENOTSUP;
6103 }
6104
6105 static int
6106 ixgbevf_get_regs(struct rte_eth_dev *dev,
6107                 struct rte_dev_reg_info *regs)
6108 {
6109         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6110         uint32_t *data = regs->data;
6111         int g_ind = 0;
6112         int count = 0;
6113         const struct reg_info *reg_group;
6114
6115         /* Support only full register dump */
6116         if ((regs->length == 0) ||
6117             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6118                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6119                         hw->device_id;
6120                 while ((reg_group = ixgbevf_regs[g_ind++]))
6121                         count += ixgbe_read_regs_group(dev, &data[count],
6122                                                       reg_group);
6123                 return 0;
6124         }
6125
6126         return -ENOTSUP;
6127 }
6128
6129 static int
6130 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6131 {
6132         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6133
6134         /* Return unit is byte count */
6135         return hw->eeprom.word_size * 2;
6136 }
6137
6138 static int
6139 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6140                 struct rte_dev_eeprom_info *in_eeprom)
6141 {
6142         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6143         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6144         uint16_t *data = in_eeprom->data;
6145         int first, length;
6146
6147         first = in_eeprom->offset >> 1;
6148         length = in_eeprom->length >> 1;
6149         if ((first > hw->eeprom.word_size) ||
6150             ((first + length) > hw->eeprom.word_size))
6151                 return -EINVAL;
6152
6153         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6154
6155         return eeprom->ops.read_buffer(hw, first, length, data);
6156 }
6157
6158 static int
6159 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6160                 struct rte_dev_eeprom_info *in_eeprom)
6161 {
6162         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6163         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6164         uint16_t *data = in_eeprom->data;
6165         int first, length;
6166
6167         first = in_eeprom->offset >> 1;
6168         length = in_eeprom->length >> 1;
6169         if ((first > hw->eeprom.word_size) ||
6170             ((first + length) > hw->eeprom.word_size))
6171                 return -EINVAL;
6172
6173         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6174
6175         return eeprom->ops.write_buffer(hw,  first, length, data);
6176 }
6177
6178 uint16_t
6179 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6180         switch (mac_type) {
6181         case ixgbe_mac_X550:
6182         case ixgbe_mac_X550EM_x:
6183         case ixgbe_mac_X550EM_a:
6184                 return ETH_RSS_RETA_SIZE_512;
6185         case ixgbe_mac_X550_vf:
6186         case ixgbe_mac_X550EM_x_vf:
6187         case ixgbe_mac_X550EM_a_vf:
6188                 return ETH_RSS_RETA_SIZE_64;
6189         default:
6190                 return ETH_RSS_RETA_SIZE_128;
6191         }
6192 }
6193
6194 uint32_t
6195 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6196         switch (mac_type) {
6197         case ixgbe_mac_X550:
6198         case ixgbe_mac_X550EM_x:
6199         case ixgbe_mac_X550EM_a:
6200                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6201                         return IXGBE_RETA(reta_idx >> 2);
6202                 else
6203                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6204         case ixgbe_mac_X550_vf:
6205         case ixgbe_mac_X550EM_x_vf:
6206         case ixgbe_mac_X550EM_a_vf:
6207                 return IXGBE_VFRETA(reta_idx >> 2);
6208         default:
6209                 return IXGBE_RETA(reta_idx >> 2);
6210         }
6211 }
6212
6213 uint32_t
6214 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6215         switch (mac_type) {
6216         case ixgbe_mac_X550_vf:
6217         case ixgbe_mac_X550EM_x_vf:
6218         case ixgbe_mac_X550EM_a_vf:
6219                 return IXGBE_VFMRQC;
6220         default:
6221                 return IXGBE_MRQC;
6222         }
6223 }
6224
6225 uint32_t
6226 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6227         switch (mac_type) {
6228         case ixgbe_mac_X550_vf:
6229         case ixgbe_mac_X550EM_x_vf:
6230         case ixgbe_mac_X550EM_a_vf:
6231                 return IXGBE_VFRSSRK(i);
6232         default:
6233                 return IXGBE_RSSRK(i);
6234         }
6235 }
6236
6237 bool
6238 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6239         switch (mac_type) {
6240         case ixgbe_mac_82599_vf:
6241         case ixgbe_mac_X540_vf:
6242                 return 0;
6243         default:
6244                 return 1;
6245         }
6246 }
6247
6248 static int
6249 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6250                         struct rte_eth_dcb_info *dcb_info)
6251 {
6252         struct ixgbe_dcb_config *dcb_config =
6253                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6254         struct ixgbe_dcb_tc_config *tc;
6255         uint8_t i, j;
6256
6257         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6258                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6259         else
6260                 dcb_info->nb_tcs = 1;
6261
6262         if (dcb_config->vt_mode) { /* vt is enabled*/
6263                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6264                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6265                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6266                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6267                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6268                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6269                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6270                                                 i * dcb_info->nb_tcs + j;
6271                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6272                                 dcb_info->tc_queue.tc_txq[i][j].base =
6273                                                 i * dcb_info->nb_tcs + j;
6274                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6275                         }
6276                 }
6277         } else { /* vt is disabled*/
6278                 struct rte_eth_dcb_rx_conf *rx_conf =
6279                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6280                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6281                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6282                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6283                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6284                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6285                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6286                         }
6287                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6288                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6289                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6290                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6291                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6292                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6293                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6294                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6295                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6296                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6297                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6298                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6299                         }
6300                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6301                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6302                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6303                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6304                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6305                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6306                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6307                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6308                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6309                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6310                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6311                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6312                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6313                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6314                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6315                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6316                 }
6317         }
6318         for (i = 0; i < dcb_info->nb_tcs; i++) {
6319                 tc = &dcb_config->tc_config[i];
6320                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6321         }
6322         return 0;
6323 }
6324
6325 /* Update e-tag ether type */
6326 static int
6327 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6328                             uint16_t ether_type)
6329 {
6330         uint32_t etag_etype;
6331
6332         if (hw->mac.type != ixgbe_mac_X550 &&
6333             hw->mac.type != ixgbe_mac_X550EM_x) {
6334                 return -ENOTSUP;
6335         }
6336
6337         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6338         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6339         etag_etype |= ether_type;
6340         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6341         IXGBE_WRITE_FLUSH(hw);
6342
6343         return 0;
6344 }
6345
6346 /* Config l2 tunnel ether type */
6347 static int
6348 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6349                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6350 {
6351         int ret = 0;
6352         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6353
6354         if (l2_tunnel == NULL)
6355                 return -EINVAL;
6356
6357         switch (l2_tunnel->l2_tunnel_type) {
6358         case RTE_L2_TUNNEL_TYPE_E_TAG:
6359                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6360                 break;
6361         default:
6362                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6363                 ret = -EINVAL;
6364                 break;
6365         }
6366
6367         return ret;
6368 }
6369
6370 /* Enable e-tag tunnel */
6371 static int
6372 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6373 {
6374         uint32_t etag_etype;
6375
6376         if (hw->mac.type != ixgbe_mac_X550 &&
6377             hw->mac.type != ixgbe_mac_X550EM_x) {
6378                 return -ENOTSUP;
6379         }
6380
6381         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6382         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6383         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6384         IXGBE_WRITE_FLUSH(hw);
6385
6386         return 0;
6387 }
6388
6389 /* Enable l2 tunnel */
6390 static int
6391 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6392                            enum rte_eth_tunnel_type l2_tunnel_type)
6393 {
6394         int ret = 0;
6395         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6396
6397         switch (l2_tunnel_type) {
6398         case RTE_L2_TUNNEL_TYPE_E_TAG:
6399                 ret = ixgbe_e_tag_enable(hw);
6400                 break;
6401         default:
6402                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6403                 ret = -EINVAL;
6404                 break;
6405         }
6406
6407         return ret;
6408 }
6409
6410 /* Disable e-tag tunnel */
6411 static int
6412 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6413 {
6414         uint32_t etag_etype;
6415
6416         if (hw->mac.type != ixgbe_mac_X550 &&
6417             hw->mac.type != ixgbe_mac_X550EM_x) {
6418                 return -ENOTSUP;
6419         }
6420
6421         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6422         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6423         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6424         IXGBE_WRITE_FLUSH(hw);
6425
6426         return 0;
6427 }
6428
6429 /* Disable l2 tunnel */
6430 static int
6431 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6432                             enum rte_eth_tunnel_type l2_tunnel_type)
6433 {
6434         int ret = 0;
6435         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6436
6437         switch (l2_tunnel_type) {
6438         case RTE_L2_TUNNEL_TYPE_E_TAG:
6439                 ret = ixgbe_e_tag_disable(hw);
6440                 break;
6441         default:
6442                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6443                 ret = -EINVAL;
6444                 break;
6445         }
6446
6447         return ret;
6448 }
6449
6450 static int
6451 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6452                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6453 {
6454         int ret = 0;
6455         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6456         uint32_t i, rar_entries;
6457         uint32_t rar_low, rar_high;
6458
6459         if (hw->mac.type != ixgbe_mac_X550 &&
6460             hw->mac.type != ixgbe_mac_X550EM_x) {
6461                 return -ENOTSUP;
6462         }
6463
6464         rar_entries = ixgbe_get_num_rx_addrs(hw);
6465
6466         for (i = 1; i < rar_entries; i++) {
6467                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6468                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6469                 if ((rar_high & IXGBE_RAH_AV) &&
6470                     (rar_high & IXGBE_RAH_ADTYPE) &&
6471                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6472                      l2_tunnel->tunnel_id)) {
6473                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6474                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6475
6476                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6477
6478                         return ret;
6479                 }
6480         }
6481
6482         return ret;
6483 }
6484
6485 static int
6486 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6487                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6488 {
6489         int ret = 0;
6490         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6491         uint32_t i, rar_entries;
6492         uint32_t rar_low, rar_high;
6493
6494         if (hw->mac.type != ixgbe_mac_X550 &&
6495             hw->mac.type != ixgbe_mac_X550EM_x) {
6496                 return -ENOTSUP;
6497         }
6498
6499         /* One entry for one tunnel. Try to remove potential existing entry. */
6500         ixgbe_e_tag_filter_del(dev, l2_tunnel);
6501
6502         rar_entries = ixgbe_get_num_rx_addrs(hw);
6503
6504         for (i = 1; i < rar_entries; i++) {
6505                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6506                 if (rar_high & IXGBE_RAH_AV) {
6507                         continue;
6508                 } else {
6509                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6510                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6511                         rar_low = l2_tunnel->tunnel_id;
6512
6513                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6514                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6515
6516                         return ret;
6517                 }
6518         }
6519
6520         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6521                      " Please remove a rule before adding a new one.");
6522         return -EINVAL;
6523 }
6524
6525 /* Add l2 tunnel filter */
6526 static int
6527 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6528                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6529 {
6530         int ret = 0;
6531
6532         switch (l2_tunnel->l2_tunnel_type) {
6533         case RTE_L2_TUNNEL_TYPE_E_TAG:
6534                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6535                 break;
6536         default:
6537                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6538                 ret = -EINVAL;
6539                 break;
6540         }
6541
6542         return ret;
6543 }
6544
6545 /* Delete l2 tunnel filter */
6546 static int
6547 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6548                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6549 {
6550         int ret = 0;
6551
6552         switch (l2_tunnel->l2_tunnel_type) {
6553         case RTE_L2_TUNNEL_TYPE_E_TAG:
6554                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6555                 break;
6556         default:
6557                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6558                 ret = -EINVAL;
6559                 break;
6560         }
6561
6562         return ret;
6563 }
6564
6565 /**
6566  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6567  * @dev: pointer to rte_eth_dev structure
6568  * @filter_op:operation will be taken.
6569  * @arg: a pointer to specific structure corresponding to the filter_op
6570  */
6571 static int
6572 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6573                                   enum rte_filter_op filter_op,
6574                                   void *arg)
6575 {
6576         int ret = 0;
6577
6578         if (filter_op == RTE_ETH_FILTER_NOP)
6579                 return 0;
6580
6581         if (arg == NULL) {
6582                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6583                             filter_op);
6584                 return -EINVAL;
6585         }
6586
6587         switch (filter_op) {
6588         case RTE_ETH_FILTER_ADD:
6589                 ret = ixgbe_dev_l2_tunnel_filter_add
6590                         (dev,
6591                          (struct rte_eth_l2_tunnel_conf *)arg);
6592                 break;
6593         case RTE_ETH_FILTER_DELETE:
6594                 ret = ixgbe_dev_l2_tunnel_filter_del
6595                         (dev,
6596                          (struct rte_eth_l2_tunnel_conf *)arg);
6597                 break;
6598         default:
6599                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6600                 ret = -EINVAL;
6601                 break;
6602         }
6603         return ret;
6604 }
6605
6606 static int
6607 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6608 {
6609         int ret = 0;
6610         uint32_t ctrl;
6611         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6612
6613         if (hw->mac.type != ixgbe_mac_X550 &&
6614             hw->mac.type != ixgbe_mac_X550EM_x) {
6615                 return -ENOTSUP;
6616         }
6617
6618         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6619         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6620         if (en)
6621                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6622         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6623
6624         return ret;
6625 }
6626
6627 /* Enable l2 tunnel forwarding */
6628 static int
6629 ixgbe_dev_l2_tunnel_forwarding_enable
6630         (struct rte_eth_dev *dev,
6631          enum rte_eth_tunnel_type l2_tunnel_type)
6632 {
6633         int ret = 0;
6634
6635         switch (l2_tunnel_type) {
6636         case RTE_L2_TUNNEL_TYPE_E_TAG:
6637                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6638                 break;
6639         default:
6640                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6641                 ret = -EINVAL;
6642                 break;
6643         }
6644
6645         return ret;
6646 }
6647
6648 /* Disable l2 tunnel forwarding */
6649 static int
6650 ixgbe_dev_l2_tunnel_forwarding_disable
6651         (struct rte_eth_dev *dev,
6652          enum rte_eth_tunnel_type l2_tunnel_type)
6653 {
6654         int ret = 0;
6655
6656         switch (l2_tunnel_type) {
6657         case RTE_L2_TUNNEL_TYPE_E_TAG:
6658                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6659                 break;
6660         default:
6661                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6662                 ret = -EINVAL;
6663                 break;
6664         }
6665
6666         return ret;
6667 }
6668
6669 static int
6670 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6671                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
6672                              bool en)
6673 {
6674         int ret = 0;
6675         uint32_t vmtir, vmvir;
6676         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6677
6678         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6679                 PMD_DRV_LOG(ERR,
6680                             "VF id %u should be less than %u",
6681                             l2_tunnel->vf_id,
6682                             dev->pci_dev->max_vfs);
6683                 return -EINVAL;
6684         }
6685
6686         if (hw->mac.type != ixgbe_mac_X550 &&
6687             hw->mac.type != ixgbe_mac_X550EM_x) {
6688                 return -ENOTSUP;
6689         }
6690
6691         if (en)
6692                 vmtir = l2_tunnel->tunnel_id;
6693         else
6694                 vmtir = 0;
6695
6696         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6697
6698         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6699         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6700         if (en)
6701                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6702         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6703
6704         return ret;
6705 }
6706
6707 /* Enable l2 tunnel tag insertion */
6708 static int
6709 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6710                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
6711 {
6712         int ret = 0;
6713
6714         switch (l2_tunnel->l2_tunnel_type) {
6715         case RTE_L2_TUNNEL_TYPE_E_TAG:
6716                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6717                 break;
6718         default:
6719                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6720                 ret = -EINVAL;
6721                 break;
6722         }
6723
6724         return ret;
6725 }
6726
6727 /* Disable l2 tunnel tag insertion */
6728 static int
6729 ixgbe_dev_l2_tunnel_insertion_disable
6730         (struct rte_eth_dev *dev,
6731          struct rte_eth_l2_tunnel_conf *l2_tunnel)
6732 {
6733         int ret = 0;
6734
6735         switch (l2_tunnel->l2_tunnel_type) {
6736         case RTE_L2_TUNNEL_TYPE_E_TAG:
6737                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6738                 break;
6739         default:
6740                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6741                 ret = -EINVAL;
6742                 break;
6743         }
6744
6745         return ret;
6746 }
6747
6748 static int
6749 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6750                              bool en)
6751 {
6752         int ret = 0;
6753         uint32_t qde;
6754         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6755
6756         if (hw->mac.type != ixgbe_mac_X550 &&
6757             hw->mac.type != ixgbe_mac_X550EM_x) {
6758                 return -ENOTSUP;
6759         }
6760
6761         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
6762         if (en)
6763                 qde |= IXGBE_QDE_STRIP_TAG;
6764         else
6765                 qde &= ~IXGBE_QDE_STRIP_TAG;
6766         qde &= ~IXGBE_QDE_READ;
6767         qde |= IXGBE_QDE_WRITE;
6768         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
6769
6770         return ret;
6771 }
6772
6773 /* Enable l2 tunnel tag stripping */
6774 static int
6775 ixgbe_dev_l2_tunnel_stripping_enable
6776         (struct rte_eth_dev *dev,
6777          enum rte_eth_tunnel_type l2_tunnel_type)
6778 {
6779         int ret = 0;
6780
6781         switch (l2_tunnel_type) {
6782         case RTE_L2_TUNNEL_TYPE_E_TAG:
6783                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
6784                 break;
6785         default:
6786                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6787                 ret = -EINVAL;
6788                 break;
6789         }
6790
6791         return ret;
6792 }
6793
6794 /* Disable l2 tunnel tag stripping */
6795 static int
6796 ixgbe_dev_l2_tunnel_stripping_disable
6797         (struct rte_eth_dev *dev,
6798          enum rte_eth_tunnel_type l2_tunnel_type)
6799 {
6800         int ret = 0;
6801
6802         switch (l2_tunnel_type) {
6803         case RTE_L2_TUNNEL_TYPE_E_TAG:
6804                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
6805                 break;
6806         default:
6807                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6808                 ret = -EINVAL;
6809                 break;
6810         }
6811
6812         return ret;
6813 }
6814
6815 /* Enable/disable l2 tunnel offload functions */
6816 static int
6817 ixgbe_dev_l2_tunnel_offload_set
6818         (struct rte_eth_dev *dev,
6819          struct rte_eth_l2_tunnel_conf *l2_tunnel,
6820          uint32_t mask,
6821          uint8_t en)
6822 {
6823         int ret = 0;
6824
6825         if (l2_tunnel == NULL)
6826                 return -EINVAL;
6827
6828         ret = -EINVAL;
6829         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
6830                 if (en)
6831                         ret = ixgbe_dev_l2_tunnel_enable(
6832                                 dev,
6833                                 l2_tunnel->l2_tunnel_type);
6834                 else
6835                         ret = ixgbe_dev_l2_tunnel_disable(
6836                                 dev,
6837                                 l2_tunnel->l2_tunnel_type);
6838         }
6839
6840         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
6841                 if (en)
6842                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
6843                                 dev,
6844                                 l2_tunnel);
6845                 else
6846                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
6847                                 dev,
6848                                 l2_tunnel);
6849         }
6850
6851         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
6852                 if (en)
6853                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
6854                                 dev,
6855                                 l2_tunnel->l2_tunnel_type);
6856                 else
6857                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
6858                                 dev,
6859                                 l2_tunnel->l2_tunnel_type);
6860         }
6861
6862         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
6863                 if (en)
6864                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
6865                                 dev,
6866                                 l2_tunnel->l2_tunnel_type);
6867                 else
6868                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
6869                                 dev,
6870                                 l2_tunnel->l2_tunnel_type);
6871         }
6872
6873         return ret;
6874 }
6875
6876 static int
6877 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
6878                         uint16_t port)
6879 {
6880         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
6881         IXGBE_WRITE_FLUSH(hw);
6882
6883         return 0;
6884 }
6885
6886 /* There's only one register for VxLAN UDP port.
6887  * So, we cannot add several ports. Will update it.
6888  */
6889 static int
6890 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
6891                      uint16_t port)
6892 {
6893         if (port == 0) {
6894                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
6895                 return -EINVAL;
6896         }
6897
6898         return ixgbe_update_vxlan_port(hw, port);
6899 }
6900
6901 /* We cannot delete the VxLAN port. For there's a register for VxLAN
6902  * UDP port, it must have a value.
6903  * So, will reset it to the original value 0.
6904  */
6905 static int
6906 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
6907                      uint16_t port)
6908 {
6909         uint16_t cur_port;
6910
6911         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
6912
6913         if (cur_port != port) {
6914                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
6915                 return -EINVAL;
6916         }
6917
6918         return ixgbe_update_vxlan_port(hw, 0);
6919 }
6920
6921 /* Add UDP tunneling port */
6922 static int
6923 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6924                               struct rte_eth_udp_tunnel *udp_tunnel)
6925 {
6926         int ret = 0;
6927         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6928
6929         if (hw->mac.type != ixgbe_mac_X550 &&
6930             hw->mac.type != ixgbe_mac_X550EM_x) {
6931                 return -ENOTSUP;
6932         }
6933
6934         if (udp_tunnel == NULL)
6935                 return -EINVAL;
6936
6937         switch (udp_tunnel->prot_type) {
6938         case RTE_TUNNEL_TYPE_VXLAN:
6939                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
6940                 break;
6941
6942         case RTE_TUNNEL_TYPE_GENEVE:
6943         case RTE_TUNNEL_TYPE_TEREDO:
6944                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6945                 ret = -EINVAL;
6946                 break;
6947
6948         default:
6949                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6950                 ret = -EINVAL;
6951                 break;
6952         }
6953
6954         return ret;
6955 }
6956
6957 /* Remove UDP tunneling port */
6958 static int
6959 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6960                               struct rte_eth_udp_tunnel *udp_tunnel)
6961 {
6962         int ret = 0;
6963         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6964
6965         if (hw->mac.type != ixgbe_mac_X550 &&
6966             hw->mac.type != ixgbe_mac_X550EM_x) {
6967                 return -ENOTSUP;
6968         }
6969
6970         if (udp_tunnel == NULL)
6971                 return -EINVAL;
6972
6973         switch (udp_tunnel->prot_type) {
6974         case RTE_TUNNEL_TYPE_VXLAN:
6975                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
6976                 break;
6977         case RTE_TUNNEL_TYPE_GENEVE:
6978         case RTE_TUNNEL_TYPE_TEREDO:
6979                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6980                 ret = -EINVAL;
6981                 break;
6982         default:
6983                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6984                 ret = -EINVAL;
6985                 break;
6986         }
6987
6988         return ret;
6989 }
6990
6991 /* ixgbevf_update_xcast_mode - Update Multicast mode
6992  * @hw: pointer to the HW structure
6993  * @netdev: pointer to net device structure
6994  * @xcast_mode: new multicast mode
6995  *
6996  * Updates the Multicast Mode of VF.
6997  */
6998 static int ixgbevf_update_xcast_mode(struct ixgbe_hw *hw,
6999                                      int xcast_mode)
7000 {
7001         struct ixgbe_mbx_info *mbx = &hw->mbx;
7002         u32 msgbuf[2];
7003         s32 err;
7004
7005         switch (hw->api_version) {
7006         case ixgbe_mbox_api_12:
7007                 break;
7008         default:
7009                 return -EOPNOTSUPP;
7010         }
7011
7012         msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
7013         msgbuf[1] = xcast_mode;
7014
7015         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
7016         if (err)
7017                 return err;
7018
7019         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
7020         if (err)
7021                 return err;
7022
7023         msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
7024         if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
7025                 return -EPERM;
7026
7027         return 0;
7028 }
7029
7030 static void
7031 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7032 {
7033         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7034
7035         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7036 }
7037
7038 static void
7039 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7040 {
7041         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7042
7043         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7044 }
7045
7046 static struct rte_driver rte_ixgbe_driver = {
7047         .type = PMD_PDEV,
7048         .init = rte_ixgbe_pmd_init,
7049 };
7050
7051 static struct rte_driver rte_ixgbevf_driver = {
7052         .type = PMD_PDEV,
7053         .init = rte_ixgbevf_pmd_init,
7054 };
7055
7056 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
7057 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);