drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_eal.h>
  26 #include <rte_alarm.h>
  27 #include <rte_ether.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_malloc.h>
  31 #include <rte_random.h>
  32 #include <rte_dev.h>
  33 #include <rte_hash_crc.h>
  34 #ifdef RTE_LIBRTE_SECURITY
  35 #include <rte_security_driver.h>
  36 #endif
  37
  38 #include "ixgbe_logs.h"
  39 #include "base/ixgbe_api.h"
  40 #include "base/ixgbe_vf.h"
  41 #include "base/ixgbe_common.h"
  42 #include "ixgbe_ethdev.h"
  43 #include "ixgbe_bypass.h"
  44 #include "ixgbe_rxtx.h"
  45 #include "base/ixgbe_type.h"
  46 #include "base/ixgbe_phy.h"
  47 #include "ixgbe_regs.h"
  48
  49 /*
  50  * High threshold controlling when to start sending XOFF frames. Must be at
  51  * least 8 bytes less than receive packet buffer size. This value is in units
  52  * of 1024 bytes.
  53  */
  54 #define IXGBE_FC_HI    0x80
  55
  56 /*
  57  * Low threshold controlling when to start sending XON frames. This value is
  58  * in units of 1024 bytes.
  59  */
  60 #define IXGBE_FC_LO    0x40
  61
  62 /* Timer value included in XOFF frames. */
  63 #define IXGBE_FC_PAUSE 0x680
  64
  65 /*Default value of Max Rx Queue*/
  66 #define IXGBE_MAX_RX_QUEUE_NUM 128
  67
  68 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  69 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  70 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  71
  72 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  73 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  74 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  75
  76 /*
  77  *  Default values for RX/TX configuration
  78  */
  79 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  80 #define IXGBE_DEFAULT_RX_PTHRESH      8
  81 #define IXGBE_DEFAULT_RX_HTHRESH      8
  82 #define IXGBE_DEFAULT_RX_WTHRESH      0
  83
  84 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  85 #define IXGBE_DEFAULT_TX_PTHRESH      32
  86 #define IXGBE_DEFAULT_TX_HTHRESH      0
  87 #define IXGBE_DEFAULT_TX_WTHRESH      0
  88 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  89
  90 /* Bit shift and mask */
  91 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  92 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  93 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  94 #define IXGBE_8_BIT_MASK   UINT8_MAX
  95
  96 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  97
  98 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
  99
 100 /* Additional timesync values. */
 101 #define NSEC_PER_SEC             1000000000L
 102 #define IXGBE_INCVAL_10GB        0x66666666
 103 #define IXGBE_INCVAL_1GB         0x40000000
 104 #define IXGBE_INCVAL_100         0x50000000
 105 #define IXGBE_INCVAL_SHIFT_10GB  28
 106 #define IXGBE_INCVAL_SHIFT_1GB   24
 107 #define IXGBE_INCVAL_SHIFT_100   21
 108 #define IXGBE_INCVAL_SHIFT_82599 7
 109 #define IXGBE_INCPER_SHIFT_82599 24
 110
 111 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 112
 113 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 114 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 115 #define IXGBE_ETAG_ETYPE                       0x00005084
 116 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 117 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 118 #define IXGBE_RAH_ADTYPE                       0x40000000
 119 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 120 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 121 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 122 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 123 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 124 #define IXGBE_VTEICR_MASK                      0x07
 125
 126 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 127 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 128
 129 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 130 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 131 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 132 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 133 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 134 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 135 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 136 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 137 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 139 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 142 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 143 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 146 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 148                                 int wait_to_complete);
 149 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 150                                 struct rte_eth_stats *stats);
 151 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 152                                 struct rte_eth_xstat *xstats, unsigned n);
 153 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 154                                   struct rte_eth_xstat *xstats, unsigned n);
 155 static int
 156 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 157                 uint64_t *values, unsigned int n);
 158 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 159 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 160 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 161         struct rte_eth_xstat_name *xstats_names,
 162         unsigned int size);
 163 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 164         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 165 static int ixgbe_dev_xstats_get_names_by_id(
 166         struct rte_eth_dev *dev,
 167         struct rte_eth_xstat_name *xstats_names,
 168         const uint64_t *ids,
 169         unsigned int limit);
 170 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 171                                              uint16_t queue_id,
 172                                              uint8_t stat_idx,
 173                                              uint8_t is_rx);
 174 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 175                                  size_t fw_size);
 176 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 177                                struct rte_eth_dev_info *dev_info);
 178 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 179 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 180                                  struct rte_eth_dev_info *dev_info);
 181 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 182
 183 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 184                 uint16_t vlan_id, int on);
 185 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 186                                enum rte_vlan_type vlan_type,
 187                                uint16_t tpid_id);
 188 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 189                 uint16_t queue, bool on);
 190 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 191                 int on);
 192 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 193                                                   int mask);
 194 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 195 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 200
 201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 204                                struct rte_eth_fc_conf *fc_conf);
 205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 206                                struct rte_eth_fc_conf *fc_conf);
 207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 208                 struct rte_eth_pfc_conf *pfc_conf);
 209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 210                         struct rte_eth_rss_reta_entry64 *reta_conf,
 211                         uint16_t reta_size);
 212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 213                         struct rte_eth_rss_reta_entry64 *reta_conf,
 214                         uint16_t reta_size);
 215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 217 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 218 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 220 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 221                                       struct rte_intr_handle *handle);
 222 static void ixgbe_dev_interrupt_handler(void *param);
 223 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 224 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 225                          uint32_t index, uint32_t pool);
 226 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 227 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 228                                            struct ether_addr *mac_addr);
 229 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 230 static bool is_device_supported(struct rte_eth_dev *dev,
 231                                 struct rte_pci_driver *drv);
 232
 233 /* For Virtual Function support */
 234 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 235 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 236 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 237 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 238 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 239                                    int wait_to_complete);
 240 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 241 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 242 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 243 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 244 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 245 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 246                 struct rte_eth_stats *stats);
 247 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 248 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 249                 uint16_t vlan_id, int on);
 250 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 251                 uint16_t queue, int on);
 252 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 253 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 254 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 255 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 256                                             uint16_t queue_id);
 257 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 258                                              uint16_t queue_id);
 259 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 260                                  uint8_t queue, uint8_t msix_vector);
 261 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 262 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 263 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 264
 265 /* For Eth VMDQ APIs support */
 266 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 267                 ether_addr * mac_addr, uint8_t on);
 268 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 269 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 270                 struct rte_eth_mirror_conf *mirror_conf,
 271                 uint8_t rule_id, uint8_t on);
 272 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 273                 uint8_t rule_id);
 274 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 275                                           uint16_t queue_id);
 276 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 277                                            uint16_t queue_id);
 278 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 279                                uint8_t queue, uint8_t msix_vector);
 280 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 281
 282 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 283                                 struct ether_addr *mac_addr,
 284                                 uint32_t index, uint32_t pool);
 285 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 286 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 287                                              struct ether_addr *mac_addr);
 288 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 289                         struct rte_eth_syn_filter *filter);
 290 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 291                         enum rte_filter_op filter_op,
 292                         void *arg);
 293 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 294                         struct ixgbe_5tuple_filter *filter);
 295 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 296                         struct ixgbe_5tuple_filter *filter);
 297 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 298                                 enum rte_filter_op filter_op,
 299                                 void *arg);
 300 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 301                         struct rte_eth_ntuple_filter *filter);
 302 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 303                                 enum rte_filter_op filter_op,
 304                                 void *arg);
 305 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 306                         struct rte_eth_ethertype_filter *filter);
 307 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 308                      enum rte_filter_type filter_type,
 309                      enum rte_filter_op filter_op,
 310                      void *arg);
 311 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 312
 313 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 314                                       struct ether_addr *mc_addr_set,
 315                                       uint32_t nb_mc_addr);
 316 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 317                                    struct rte_eth_dcb_info *dcb_info);
 318
 319 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 320 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 321                             struct rte_dev_reg_info *regs);
 322 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 323 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 324                                 struct rte_dev_eeprom_info *eeprom);
 325 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 326                                 struct rte_dev_eeprom_info *eeprom);
 327
 328 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 329                                  struct rte_eth_dev_module_info *modinfo);
 330 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 331                                    struct rte_dev_eeprom_info *info);
 332
 333 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 334 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 335                                 struct rte_dev_reg_info *regs);
 336
 337 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 338 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 339 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 340                                             struct timespec *timestamp,
 341                                             uint32_t flags);
 342 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 343                                             struct timespec *timestamp);
 344 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 345 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 346                                    struct timespec *timestamp);
 347 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 348                                    const struct timespec *timestamp);
 349 static void ixgbevf_dev_interrupt_handler(void *param);
 350
 351 static int ixgbe_dev_l2_tunnel_eth_type_conf
 352         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 353 static int ixgbe_dev_l2_tunnel_offload_set
 354         (struct rte_eth_dev *dev,
 355          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 356          uint32_t mask,
 357          uint8_t en);
 358 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 359                                              enum rte_filter_op filter_op,
 360                                              void *arg);
 361
 362 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 363                                          struct rte_eth_udp_tunnel *udp_tunnel);
 364 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 365                                          struct rte_eth_udp_tunnel *udp_tunnel);
 366 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 367 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 368
 369 /*
 370  * Define VF Stats MACRO for Non "cleared on read" register
 371  */
 372 #define UPDATE_VF_STAT(reg, last, cur)                          \
 373 {                                                               \
 374         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 375         cur += (latest - last) & UINT_MAX;                      \
 376         last = latest;                                          \
 377 }
 378
 379 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 380 {                                                                \
 381         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 382         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 383         u64 latest = ((new_msb << 32) | new_lsb);                \
 384         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 385         last = latest;                                           \
 386 }
 387
 388 #define IXGBE_SET_HWSTRIP(h, q) do {\
 389                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 390                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 391                 (h)->bitmap[idx] |= 1 << bit;\
 392         } while (0)
 393
 394 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 395                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 396                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 397                 (h)->bitmap[idx] &= ~(1 << bit);\
 398         } while (0)
 399
 400 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 401                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 402                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 403                 (r) = (h)->bitmap[idx] >> bit & 1;\
 404         } while (0)
 405
 406 int ixgbe_logtype_init;
 407 int ixgbe_logtype_driver;
 408
 409 /*
 410  * The set of PCI devices this driver supports
 411  */
 412 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 461 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 463 #endif
 464         { .vendor_id = 0, /* sentinel */ },
 465 };
 466
 467 /*
 468  * The set of PCI devices this driver supports (for 82599 VF)
 469  */
 470 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 481         { .vendor_id = 0, /* sentinel */ },
 482 };
 483
 484 static const struct rte_eth_desc_lim rx_desc_lim = {
 485         .nb_max = IXGBE_MAX_RING_DESC,
 486         .nb_min = IXGBE_MIN_RING_DESC,
 487         .nb_align = IXGBE_RXD_ALIGN,
 488 };
 489
 490 static const struct rte_eth_desc_lim tx_desc_lim = {
 491         .nb_max = IXGBE_MAX_RING_DESC,
 492         .nb_min = IXGBE_MIN_RING_DESC,
 493         .nb_align = IXGBE_TXD_ALIGN,
 494         .nb_seg_max = IXGBE_TX_MAX_SEG,
 495         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 496 };
 497
 498 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 499         .dev_configure        = ixgbe_dev_configure,
 500         .dev_start            = ixgbe_dev_start,
 501         .dev_stop             = ixgbe_dev_stop,
 502         .dev_set_link_up    = ixgbe_dev_set_link_up,
 503         .dev_set_link_down  = ixgbe_dev_set_link_down,
 504         .dev_close            = ixgbe_dev_close,
 505         .dev_reset            = ixgbe_dev_reset,
 506         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 507         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 508         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 509         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 510         .link_update          = ixgbe_dev_link_update,
 511         .stats_get            = ixgbe_dev_stats_get,
 512         .xstats_get           = ixgbe_dev_xstats_get,
 513         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 514         .stats_reset          = ixgbe_dev_stats_reset,
 515         .xstats_reset         = ixgbe_dev_xstats_reset,
 516         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 517         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 518         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 519         .fw_version_get       = ixgbe_fw_version_get,
 520         .dev_infos_get        = ixgbe_dev_info_get,
 521         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 522         .mtu_set              = ixgbe_dev_mtu_set,
 523         .vlan_filter_set      = ixgbe_vlan_filter_set,
 524         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 525         .vlan_offload_set     = ixgbe_vlan_offload_set,
 526         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 527         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 528         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 529         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 530         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 531         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 532         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 533         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 534         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 535         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 536         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 537         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 538         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 539         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 540         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 541         .dev_led_on           = ixgbe_dev_led_on,
 542         .dev_led_off          = ixgbe_dev_led_off,
 543         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 544         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 545         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 546         .mac_addr_add         = ixgbe_add_rar,
 547         .mac_addr_remove      = ixgbe_remove_rar,
 548         .mac_addr_set         = ixgbe_set_default_mac_addr,
 549         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 550         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 551         .mirror_rule_set      = ixgbe_mirror_rule_set,
 552         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 553         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 554         .reta_update          = ixgbe_dev_rss_reta_update,
 555         .reta_query           = ixgbe_dev_rss_reta_query,
 556         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 557         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 558         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 559         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 560         .rxq_info_get         = ixgbe_rxq_info_get,
 561         .txq_info_get         = ixgbe_txq_info_get,
 562         .timesync_enable      = ixgbe_timesync_enable,
 563         .timesync_disable     = ixgbe_timesync_disable,
 564         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 565         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 566         .get_reg              = ixgbe_get_regs,
 567         .get_eeprom_length    = ixgbe_get_eeprom_length,
 568         .get_eeprom           = ixgbe_get_eeprom,
 569         .set_eeprom           = ixgbe_set_eeprom,
 570         .get_module_info      = ixgbe_get_module_info,
 571         .get_module_eeprom    = ixgbe_get_module_eeprom,
 572         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 573         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 574         .timesync_read_time   = ixgbe_timesync_read_time,
 575         .timesync_write_time  = ixgbe_timesync_write_time,
 576         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 577         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 578         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 579         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 580         .tm_ops_get           = ixgbe_tm_ops_get,
 581 };
 582
 583 /*
 584  * dev_ops for virtual function, bare necessities for basic vf
 585  * operation have been implemented
 586  */
 587 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 588         .dev_configure        = ixgbevf_dev_configure,
 589         .dev_start            = ixgbevf_dev_start,
 590         .dev_stop             = ixgbevf_dev_stop,
 591         .link_update          = ixgbevf_dev_link_update,
 592         .stats_get            = ixgbevf_dev_stats_get,
 593         .xstats_get           = ixgbevf_dev_xstats_get,
 594         .stats_reset          = ixgbevf_dev_stats_reset,
 595         .xstats_reset         = ixgbevf_dev_stats_reset,
 596         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 597         .dev_close            = ixgbevf_dev_close,
 598         .dev_reset            = ixgbevf_dev_reset,
 599         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 600         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 601         .dev_infos_get        = ixgbevf_dev_info_get,
 602         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 603         .mtu_set              = ixgbevf_dev_set_mtu,
 604         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 605         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 606         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 607         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 608         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 609         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 610         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 611         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 612         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 613         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 614         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 615         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 616         .mac_addr_add         = ixgbevf_add_mac_addr,
 617         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 618         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 619         .rxq_info_get         = ixgbe_rxq_info_get,
 620         .txq_info_get         = ixgbe_txq_info_get,
 621         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 622         .get_reg              = ixgbevf_get_regs,
 623         .reta_update          = ixgbe_dev_rss_reta_update,
 624         .reta_query           = ixgbe_dev_rss_reta_query,
 625         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 626         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 627 };
 628
 629 /* store statistics names and its offset in stats structure */
 630 struct rte_ixgbe_xstats_name_off {
 631         char name[RTE_ETH_XSTATS_NAME_SIZE];
 632         unsigned offset;
 633 };
 634
 635 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 636         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 637         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 638         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 639         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 640         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 641         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 642         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 643         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 644         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 645         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 646         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 647         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 648         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 649         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 650         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 651                 prc1023)},
 652         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 653                 prc1522)},
 654         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 655         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 656         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 657         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 658         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 659         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 660         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 661         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 662         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 663         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 664         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 665         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 666         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 667         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 668         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 669         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 670         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 671                 ptc1023)},
 672         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 673                 ptc1522)},
 674         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 675         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 676         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 677         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 678
 679         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 680                 fdirustat_add)},
 681         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 682                 fdirustat_remove)},
 683         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 684                 fdirfstat_fadd)},
 685         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 686                 fdirfstat_fremove)},
 687         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 688                 fdirmatch)},
 689         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 690                 fdirmiss)},
 691
 692         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 693         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 694         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 695                 fclast)},
 696         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 697         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 698         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 699         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 700         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 701                 fcoe_noddp)},
 702         {"rx_fcoe_no_direct_data_placement_ext_buff",
 703                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 704
 705         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 706                 lxontxc)},
 707         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 708                 lxonrxc)},
 709         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 710                 lxofftxc)},
 711         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 712                 lxoffrxc)},
 713         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 714 };
 715
 716 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 717                            sizeof(rte_ixgbe_stats_strings[0]))
 718
 719 /* MACsec statistics */
 720 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 721         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 722                 out_pkts_untagged)},
 723         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 724                 out_pkts_encrypted)},
 725         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 726                 out_pkts_protected)},
 727         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 728                 out_octets_encrypted)},
 729         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 730                 out_octets_protected)},
 731         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 732                 in_pkts_untagged)},
 733         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 734                 in_pkts_badtag)},
 735         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 736                 in_pkts_nosci)},
 737         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 738                 in_pkts_unknownsci)},
 739         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 740                 in_octets_decrypted)},
 741         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 742                 in_octets_validated)},
 743         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 744                 in_pkts_unchecked)},
 745         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 746                 in_pkts_delayed)},
 747         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_late)},
 749         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 750                 in_pkts_ok)},
 751         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 752                 in_pkts_invalid)},
 753         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_notvalid)},
 755         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_unusedsa)},
 757         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_notusingsa)},
 759 };
 760
 761 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 762                            sizeof(rte_ixgbe_macsec_strings[0]))
 763
 764 /* Per-queue statistics */
 765 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 766         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 767         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 768         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 769         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 770 };
 771
 772 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 773                            sizeof(rte_ixgbe_rxq_strings[0]))
 774 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 775
 776 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 777         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 778         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 779         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 780                 pxon2offc)},
 781 };
 782
 783 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 784                            sizeof(rte_ixgbe_txq_strings[0]))
 785 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 786
 787 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 788         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 789 };
 790
 791 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 792                 sizeof(rte_ixgbevf_stats_strings[0]))
 793
 794 /*
 795  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 796  */
 797 static inline int
 798 ixgbe_is_sfp(struct ixgbe_hw *hw)
 799 {
 800         switch (hw->phy.type) {
 801         case ixgbe_phy_sfp_avago:
 802         case ixgbe_phy_sfp_ftl:
 803         case ixgbe_phy_sfp_intel:
 804         case ixgbe_phy_sfp_unknown:
 805         case ixgbe_phy_sfp_passive_tyco:
 806         case ixgbe_phy_sfp_passive_unknown:
 807                 return 1;
 808         default:
 809                 return 0;
 810         }
 811 }
 812
 813 static inline int32_t
 814 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 815 {
 816         uint32_t ctrl_ext;
 817         int32_t status;
 818
 819         status = ixgbe_reset_hw(hw);
 820
 821         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 822         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 823         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 824         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 825         IXGBE_WRITE_FLUSH(hw);
 826
 827         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 828                 status = IXGBE_SUCCESS;
 829         return status;
 830 }
 831
 832 static inline void
 833 ixgbe_enable_intr(struct rte_eth_dev *dev)
 834 {
 835         struct ixgbe_interrupt *intr =
 836                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 837         struct ixgbe_hw *hw =
 838                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 839
 840         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 841         IXGBE_WRITE_FLUSH(hw);
 842 }
 843
 844 /*
 845  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 846  */
 847 static void
 848 ixgbe_disable_intr(struct ixgbe_hw *hw)
 849 {
 850         PMD_INIT_FUNC_TRACE();
 851
 852         if (hw->mac.type == ixgbe_mac_82598EB) {
 853                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 854         } else {
 855                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 856                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 857                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 858         }
 859         IXGBE_WRITE_FLUSH(hw);
 860 }
 861
 862 /*
 863  * This function resets queue statistics mapping registers.
 864  * From Niantic datasheet, Initialization of Statistics section:
 865  * "...if software requires the queue counters, the RQSMR and TQSM registers
 866  * must be re-programmed following a device reset.
 867  */
 868 static void
 869 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 870 {
 871         uint32_t i;
 872
 873         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 874                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 875                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 876         }
 877 }
 878
 879
 880 static int
 881 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 882                                   uint16_t queue_id,
 883                                   uint8_t stat_idx,
 884                                   uint8_t is_rx)
 885 {
 886 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 887 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 888 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 889
 890         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 891         struct ixgbe_stat_mapping_registers *stat_mappings =
 892                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 893         uint32_t qsmr_mask = 0;
 894         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 895         uint32_t q_map;
 896         uint8_t n, offset;
 897
 898         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 899                 (hw->mac.type != ixgbe_mac_X540) &&
 900                 (hw->mac.type != ixgbe_mac_X550) &&
 901                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 902                 (hw->mac.type != ixgbe_mac_X550EM_a))
 903                 return -ENOSYS;
 904
 905         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 906                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 907                      queue_id, stat_idx);
 908
 909         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 910         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 911                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 912                 return -EIO;
 913         }
 914         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 915
 916         /* Now clear any previous stat_idx set */
 917         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 918         if (!is_rx)
 919                 stat_mappings->tqsm[n] &= ~clearing_mask;
 920         else
 921                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 922
 923         q_map = (uint32_t)stat_idx;
 924         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 925         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 926         if (!is_rx)
 927                 stat_mappings->tqsm[n] |= qsmr_mask;
 928         else
 929                 stat_mappings->rqsmr[n] |= qsmr_mask;
 930
 931         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 932                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 933                      queue_id, stat_idx);
 934         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 935                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 936
 937         /* Now write the mapping in the appropriate register */
 938         if (is_rx) {
 939                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 940                              stat_mappings->rqsmr[n], n);
 941                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 942         } else {
 943                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 944                              stat_mappings->tqsm[n], n);
 945                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 946         }
 947         return 0;
 948 }
 949
 950 static void
 951 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 952 {
 953         struct ixgbe_stat_mapping_registers *stat_mappings =
 954                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 955         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 956         int i;
 957
 958         /* write whatever was in stat mapping table to the NIC */
 959         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 960                 /* rx */
 961                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 962
 963                 /* tx */
 964                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 965         }
 966 }
 967
 968 static void
 969 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 970 {
 971         uint8_t i;
 972         struct ixgbe_dcb_tc_config *tc;
 973         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 974
 975         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 976         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 977         for (i = 0; i < dcb_max_tc; i++) {
 978                 tc = &dcb_config->tc_config[i];
 979                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 980                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 981                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 982                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 983                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 984                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 985                 tc->pfc = ixgbe_dcb_pfc_disabled;
 986         }
 987
 988         /* Initialize default user to priority mapping, UPx->TC0 */
 989         tc = &dcb_config->tc_config[0];
 990         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 991         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 992         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 993                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 994                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 995         }
 996         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 997         dcb_config->pfc_mode_enable = false;
 998         dcb_config->vt_mode = true;
 999         dcb_config->round_robin_enable = false;
1000         /* support all DCB capabilities in 82599 */
1001         dcb_config->support.capabilities = 0xFF;
1002
1003         /*we only support 4 Tcs for X540, X550 */
1004         if (hw->mac.type == ixgbe_mac_X540 ||
1005                 hw->mac.type == ixgbe_mac_X550 ||
1006                 hw->mac.type == ixgbe_mac_X550EM_x ||
1007                 hw->mac.type == ixgbe_mac_X550EM_a) {
1008                 dcb_config->num_tcs.pg_tcs = 4;
1009                 dcb_config->num_tcs.pfc_tcs = 4;
1010         }
1011 }
1012
1013 /*
1014  * Ensure that all locks are released before first NVM or PHY access
1015  */
1016 static void
1017 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1018 {
1019         uint16_t mask;
1020
1021         /*
1022          * Phy lock should not fail in this early stage. If this is the case,
1023          * it is due to an improper exit of the application.
1024          * So force the release of the faulty lock. Release of common lock
1025          * is done automatically by swfw_sync function.
1026          */
1027         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1028         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1029                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1030         }
1031         ixgbe_release_swfw_semaphore(hw, mask);
1032
1033         /*
1034          * These ones are more tricky since they are common to all ports; but
1035          * swfw_sync retries last long enough (1s) to be almost sure that if
1036          * lock can not be taken it is due to an improper lock of the
1037          * semaphore.
1038          */
1039         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1040         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1041                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1042         }
1043         ixgbe_release_swfw_semaphore(hw, mask);
1044 }
1045
1046 /*
1047  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1048  * It returns 0 on success.
1049  */
1050 static int
1051 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1052 {
1053         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1054         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1055         struct ixgbe_hw *hw =
1056                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1057         struct ixgbe_vfta *shadow_vfta =
1058                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1059         struct ixgbe_hwstrip *hwstrip =
1060                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1061         struct ixgbe_dcb_config *dcb_config =
1062                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1063         struct ixgbe_filter_info *filter_info =
1064                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1065         struct ixgbe_bw_conf *bw_conf =
1066                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1067         uint32_t ctrl_ext;
1068         uint16_t csum;
1069         int diag, i;
1070
1071         PMD_INIT_FUNC_TRACE();
1072
1073         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1074         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1075         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1076         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1077
1078         /*
1079          * For secondary processes, we don't initialise any further as primary
1080          * has already done this work. Only check we don't need a different
1081          * RX and TX function.
1082          */
1083         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1084                 struct ixgbe_tx_queue *txq;
1085                 /* TX queue function in primary, set by last queue initialized
1086                  * Tx queue may not initialized by primary process
1087                  */
1088                 if (eth_dev->data->tx_queues) {
1089                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1090                         ixgbe_set_tx_function(eth_dev, txq);
1091                 } else {
1092                         /* Use default TX function if we get here */
1093                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1094                                      "Using default TX function.");
1095                 }
1096
1097                 ixgbe_set_rx_function(eth_dev);
1098
1099                 return 0;
1100         }
1101
1102         rte_eth_copy_pci_info(eth_dev, pci_dev);
1103
1104         /* Vendor and Device ID need to be set before init of shared code */
1105         hw->device_id = pci_dev->id.device_id;
1106         hw->vendor_id = pci_dev->id.vendor_id;
1107         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1108         hw->allow_unsupported_sfp = 1;
1109
1110         /* Initialize the shared code (base driver) */
1111 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1112         diag = ixgbe_bypass_init_shared_code(hw);
1113 #else
1114         diag = ixgbe_init_shared_code(hw);
1115 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1116
1117         if (diag != IXGBE_SUCCESS) {
1118                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1119                 return -EIO;
1120         }
1121
1122         /* pick up the PCI bus settings for reporting later */
1123         ixgbe_get_bus_info(hw);
1124
1125         /* Unlock any pending hardware semaphore */
1126         ixgbe_swfw_lock_reset(hw);
1127
1128 #ifdef RTE_LIBRTE_SECURITY
1129         /* Initialize security_ctx only for primary process*/
1130         if (ixgbe_ipsec_ctx_create(eth_dev))
1131                 return -ENOMEM;
1132 #endif
1133
1134         /* Initialize DCB configuration*/
1135         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1136         ixgbe_dcb_init(hw, dcb_config);
1137         /* Get Hardware Flow Control setting */
1138         hw->fc.requested_mode = ixgbe_fc_full;
1139         hw->fc.current_mode = ixgbe_fc_full;
1140         hw->fc.pause_time = IXGBE_FC_PAUSE;
1141         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1142                 hw->fc.low_water[i] = IXGBE_FC_LO;
1143                 hw->fc.high_water[i] = IXGBE_FC_HI;
1144         }
1145         hw->fc.send_xon = 1;
1146
1147         /* Make sure we have a good EEPROM before we read from it */
1148         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1149         if (diag != IXGBE_SUCCESS) {
1150                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1151                 return -EIO;
1152         }
1153
1154 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1155         diag = ixgbe_bypass_init_hw(hw);
1156 #else
1157         diag = ixgbe_init_hw(hw);
1158 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1159
1160         /*
1161          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1162          * is called too soon after the kernel driver unbinding/binding occurs.
1163          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1164          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1165          * also called. See ixgbe_identify_phy_82599(). The reason for the
1166          * failure is not known, and only occuts when virtualisation features
1167          * are disabled in the bios. A delay of 100ms  was found to be enough by
1168          * trial-and-error, and is doubled to be safe.
1169          */
1170         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1171                 rte_delay_ms(200);
1172                 diag = ixgbe_init_hw(hw);
1173         }
1174
1175         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1176                 diag = IXGBE_SUCCESS;
1177
1178         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1179                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1180                              "LOM.  Please be aware there may be issues associated "
1181                              "with your hardware.");
1182                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1183                              "please contact your Intel or hardware representative "
1184                              "who provided you with this hardware.");
1185         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1186                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1187         if (diag) {
1188                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1189                 return -EIO;
1190         }
1191
1192         /* Reset the hw statistics */
1193         ixgbe_dev_stats_reset(eth_dev);
1194
1195         /* disable interrupt */
1196         ixgbe_disable_intr(hw);
1197
1198         /* reset mappings for queue statistics hw counters*/
1199         ixgbe_reset_qstat_mappings(hw);
1200
1201         /* Allocate memory for storing MAC addresses */
1202         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1203                                                hw->mac.num_rar_entries, 0);
1204         if (eth_dev->data->mac_addrs == NULL) {
1205                 PMD_INIT_LOG(ERR,
1206                              "Failed to allocate %u bytes needed to store "
1207                              "MAC addresses",
1208                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1209                 return -ENOMEM;
1210         }
1211         /* Copy the permanent MAC address */
1212         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1213                         &eth_dev->data->mac_addrs[0]);
1214
1215         /* Allocate memory for storing hash filter MAC addresses */
1216         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1217                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1218         if (eth_dev->data->hash_mac_addrs == NULL) {
1219                 PMD_INIT_LOG(ERR,
1220                              "Failed to allocate %d bytes needed to store MAC addresses",
1221                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1222                 return -ENOMEM;
1223         }
1224
1225         /* initialize the vfta */
1226         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1227
1228         /* initialize the hw strip bitmap*/
1229         memset(hwstrip, 0, sizeof(*hwstrip));
1230
1231         /* initialize PF if max_vfs not zero */
1232         ixgbe_pf_host_init(eth_dev);
1233
1234         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1235         /* let hardware know driver is loaded */
1236         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1237         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1238         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1239         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1240         IXGBE_WRITE_FLUSH(hw);
1241
1242         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1243                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1244                              (int) hw->mac.type, (int) hw->phy.type,
1245                              (int) hw->phy.sfp_type);
1246         else
1247                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1248                              (int) hw->mac.type, (int) hw->phy.type);
1249
1250         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1251                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1252                      pci_dev->id.device_id);
1253
1254         rte_intr_callback_register(intr_handle,
1255                                    ixgbe_dev_interrupt_handler, eth_dev);
1256
1257         /* enable uio/vfio intr/eventfd mapping */
1258         rte_intr_enable(intr_handle);
1259
1260         /* enable support intr */
1261         ixgbe_enable_intr(eth_dev);
1262
1263         /* initialize filter info */
1264         memset(filter_info, 0,
1265                sizeof(struct ixgbe_filter_info));
1266
1267         /* initialize 5tuple filter list */
1268         TAILQ_INIT(&filter_info->fivetuple_list);
1269
1270         /* initialize flow director filter list & hash */
1271         ixgbe_fdir_filter_init(eth_dev);
1272
1273         /* initialize l2 tunnel filter list & hash */
1274         ixgbe_l2_tn_filter_init(eth_dev);
1275
1276         /* initialize flow filter lists */
1277         ixgbe_filterlist_init();
1278
1279         /* initialize bandwidth configuration info */
1280         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1281
1282         /* initialize Traffic Manager configuration */
1283         ixgbe_tm_conf_init(eth_dev);
1284
1285         return 0;
1286 }
1287
1288 static int
1289 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1290 {
1291         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1292         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1293         struct ixgbe_hw *hw;
1294         int retries = 0;
1295         int ret;
1296
1297         PMD_INIT_FUNC_TRACE();
1298
1299         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1300                 return -EPERM;
1301
1302         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1303
1304         if (hw->adapter_stopped == 0)
1305                 ixgbe_dev_close(eth_dev);
1306
1307         eth_dev->dev_ops = NULL;
1308         eth_dev->rx_pkt_burst = NULL;
1309         eth_dev->tx_pkt_burst = NULL;
1310
1311         /* Unlock any pending hardware semaphore */
1312         ixgbe_swfw_lock_reset(hw);
1313
1314         /* disable uio intr before callback unregister */
1315         rte_intr_disable(intr_handle);
1316
1317         do {
1318                 ret = rte_intr_callback_unregister(intr_handle,
1319                                 ixgbe_dev_interrupt_handler, eth_dev);
1320                 if (ret >= 0) {
1321                         break;
1322                 } else if (ret != -EAGAIN) {
1323                         PMD_INIT_LOG(ERR,
1324                                 "intr callback unregister failed: %d",
1325                                 ret);
1326                         return ret;
1327                 }
1328                 rte_delay_ms(100);
1329         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1330
1331         /* uninitialize PF if max_vfs not zero */
1332         ixgbe_pf_host_uninit(eth_dev);
1333
1334         rte_free(eth_dev->data->mac_addrs);
1335         eth_dev->data->mac_addrs = NULL;
1336
1337         rte_free(eth_dev->data->hash_mac_addrs);
1338         eth_dev->data->hash_mac_addrs = NULL;
1339
1340         /* remove all the fdir filters & hash */
1341         ixgbe_fdir_filter_uninit(eth_dev);
1342
1343         /* remove all the L2 tunnel filters & hash */
1344         ixgbe_l2_tn_filter_uninit(eth_dev);
1345
1346         /* Remove all ntuple filters of the device */
1347         ixgbe_ntuple_filter_uninit(eth_dev);
1348
1349         /* clear all the filters list */
1350         ixgbe_filterlist_flush();
1351
1352         /* Remove all Traffic Manager configuration */
1353         ixgbe_tm_conf_uninit(eth_dev);
1354
1355 #ifdef RTE_LIBRTE_SECURITY
1356         rte_free(eth_dev->security_ctx);
1357 #endif
1358
1359         return 0;
1360 }
1361
1362 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1363 {
1364         struct ixgbe_filter_info *filter_info =
1365                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1366         struct ixgbe_5tuple_filter *p_5tuple;
1367
1368         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1369                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1370                              p_5tuple,
1371                              entries);
1372                 rte_free(p_5tuple);
1373         }
1374         memset(filter_info->fivetuple_mask, 0,
1375                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1376
1377         return 0;
1378 }
1379
1380 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1381 {
1382         struct ixgbe_hw_fdir_info *fdir_info =
1383                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1384         struct ixgbe_fdir_filter *fdir_filter;
1385
1386                 if (fdir_info->hash_map)
1387                 rte_free(fdir_info->hash_map);
1388         if (fdir_info->hash_handle)
1389                 rte_hash_free(fdir_info->hash_handle);
1390
1391         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1392                 TAILQ_REMOVE(&fdir_info->fdir_list,
1393                              fdir_filter,
1394                              entries);
1395                 rte_free(fdir_filter);
1396         }
1397
1398         return 0;
1399 }
1400
1401 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1402 {
1403         struct ixgbe_l2_tn_info *l2_tn_info =
1404                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1405         struct ixgbe_l2_tn_filter *l2_tn_filter;
1406
1407         if (l2_tn_info->hash_map)
1408                 rte_free(l2_tn_info->hash_map);
1409         if (l2_tn_info->hash_handle)
1410                 rte_hash_free(l2_tn_info->hash_handle);
1411
1412         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1413                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1414                              l2_tn_filter,
1415                              entries);
1416                 rte_free(l2_tn_filter);
1417         }
1418
1419         return 0;
1420 }
1421
1422 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1423 {
1424         struct ixgbe_hw_fdir_info *fdir_info =
1425                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1426         char fdir_hash_name[RTE_HASH_NAMESIZE];
1427         struct rte_hash_parameters fdir_hash_params = {
1428                 .name = fdir_hash_name,
1429                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1430                 .key_len = sizeof(union ixgbe_atr_input),
1431                 .hash_func = rte_hash_crc,
1432                 .hash_func_init_val = 0,
1433                 .socket_id = rte_socket_id(),
1434         };
1435
1436         TAILQ_INIT(&fdir_info->fdir_list);
1437         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1438                  "fdir_%s", eth_dev->device->name);
1439         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1440         if (!fdir_info->hash_handle) {
1441                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1442                 return -EINVAL;
1443         }
1444         fdir_info->hash_map = rte_zmalloc("ixgbe",
1445                                           sizeof(struct ixgbe_fdir_filter *) *
1446                                           IXGBE_MAX_FDIR_FILTER_NUM,
1447                                           0);
1448         if (!fdir_info->hash_map) {
1449                 PMD_INIT_LOG(ERR,
1450                              "Failed to allocate memory for fdir hash map!");
1451                 return -ENOMEM;
1452         }
1453         fdir_info->mask_added = FALSE;
1454
1455         return 0;
1456 }
1457
1458 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1459 {
1460         struct ixgbe_l2_tn_info *l2_tn_info =
1461                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1462         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1463         struct rte_hash_parameters l2_tn_hash_params = {
1464                 .name = l2_tn_hash_name,
1465                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1466                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1467                 .hash_func = rte_hash_crc,
1468                 .hash_func_init_val = 0,
1469                 .socket_id = rte_socket_id(),
1470         };
1471
1472         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1473         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1474                  "l2_tn_%s", eth_dev->device->name);
1475         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1476         if (!l2_tn_info->hash_handle) {
1477                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1478                 return -EINVAL;
1479         }
1480         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1481                                    sizeof(struct ixgbe_l2_tn_filter *) *
1482                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1483                                    0);
1484         if (!l2_tn_info->hash_map) {
1485                 PMD_INIT_LOG(ERR,
1486                         "Failed to allocate memory for L2 TN hash map!");
1487                 return -ENOMEM;
1488         }
1489         l2_tn_info->e_tag_en = FALSE;
1490         l2_tn_info->e_tag_fwd_en = FALSE;
1491         l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG;
1492
1493         return 0;
1494 }
1495 /*
1496  * Negotiate mailbox API version with the PF.
1497  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1498  * Then we try to negotiate starting with the most recent one.
1499  * If all negotiation attempts fail, then we will proceed with
1500  * the default one (ixgbe_mbox_api_10).
1501  */
1502 static void
1503 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1504 {
1505         int32_t i;
1506
1507         /* start with highest supported, proceed down */
1508         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1509                 ixgbe_mbox_api_12,
1510                 ixgbe_mbox_api_11,
1511                 ixgbe_mbox_api_10,
1512         };
1513
1514         for (i = 0;
1515                         i != RTE_DIM(sup_ver) &&
1516                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1517                         i++)
1518                 ;
1519 }
1520
1521 static void
1522 generate_random_mac_addr(struct ether_addr *mac_addr)
1523 {
1524         uint64_t random;
1525
1526         /* Set Organizationally Unique Identifier (OUI) prefix. */
1527         mac_addr->addr_bytes[0] = 0x00;
1528         mac_addr->addr_bytes[1] = 0x09;
1529         mac_addr->addr_bytes[2] = 0xC0;
1530         /* Force indication of locally assigned MAC address. */
1531         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1532         /* Generate the last 3 bytes of the MAC address with a random number. */
1533         random = rte_rand();
1534         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1535 }
1536
1537 /*
1538  * Virtual Function device init
1539  */
1540 static int
1541 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1542 {
1543         int diag;
1544         uint32_t tc, tcs;
1545         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1546         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1547         struct ixgbe_hw *hw =
1548                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1549         struct ixgbe_vfta *shadow_vfta =
1550                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1551         struct ixgbe_hwstrip *hwstrip =
1552                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1553         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1554
1555         PMD_INIT_FUNC_TRACE();
1556
1557         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1558         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1559         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1560
1561         /* for secondary processes, we don't initialise any further as primary
1562          * has already done this work. Only check we don't need a different
1563          * RX function
1564          */
1565         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1566                 struct ixgbe_tx_queue *txq;
1567                 /* TX queue function in primary, set by last queue initialized
1568                  * Tx queue may not initialized by primary process
1569                  */
1570                 if (eth_dev->data->tx_queues) {
1571                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1572                         ixgbe_set_tx_function(eth_dev, txq);
1573                 } else {
1574                         /* Use default TX function if we get here */
1575                         PMD_INIT_LOG(NOTICE,
1576                                      "No TX queues configured yet. Using default TX function.");
1577                 }
1578
1579                 ixgbe_set_rx_function(eth_dev);
1580
1581                 return 0;
1582         }
1583
1584         rte_eth_copy_pci_info(eth_dev, pci_dev);
1585
1586         hw->device_id = pci_dev->id.device_id;
1587         hw->vendor_id = pci_dev->id.vendor_id;
1588         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1589
1590         /* initialize the vfta */
1591         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1592
1593         /* initialize the hw strip bitmap*/
1594         memset(hwstrip, 0, sizeof(*hwstrip));
1595
1596         /* Initialize the shared code (base driver) */
1597         diag = ixgbe_init_shared_code(hw);
1598         if (diag != IXGBE_SUCCESS) {
1599                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1600                 return -EIO;
1601         }
1602
1603         /* init_mailbox_params */
1604         hw->mbx.ops.init_params(hw);
1605
1606         /* Reset the hw statistics */
1607         ixgbevf_dev_stats_reset(eth_dev);
1608
1609         /* Disable the interrupts for VF */
1610         ixgbevf_intr_disable(eth_dev);
1611
1612         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1613         diag = hw->mac.ops.reset_hw(hw);
1614
1615         /*
1616          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1617          * the underlying PF driver has not assigned a MAC address to the VF.
1618          * In this case, assign a random MAC address.
1619          */
1620         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1621                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1622                 /*
1623                  * This error code will be propagated to the app by
1624                  * rte_eth_dev_reset, so use a public error code rather than
1625                  * the internal-only IXGBE_ERR_RESET_FAILED
1626                  */
1627                 return -EAGAIN;
1628         }
1629
1630         /* negotiate mailbox API version to use with the PF. */
1631         ixgbevf_negotiate_api(hw);
1632
1633         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1634         ixgbevf_get_queues(hw, &tcs, &tc);
1635
1636         /* Allocate memory for storing MAC addresses */
1637         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1638                                                hw->mac.num_rar_entries, 0);
1639         if (eth_dev->data->mac_addrs == NULL) {
1640                 PMD_INIT_LOG(ERR,
1641                              "Failed to allocate %u bytes needed to store "
1642                              "MAC addresses",
1643                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1644                 return -ENOMEM;
1645         }
1646
1647         /* Generate a random MAC address, if none was assigned by PF. */
1648         if (is_zero_ether_addr(perm_addr)) {
1649                 generate_random_mac_addr(perm_addr);
1650                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1651                 if (diag) {
1652                         rte_free(eth_dev->data->mac_addrs);
1653                         eth_dev->data->mac_addrs = NULL;
1654                         return diag;
1655                 }
1656                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1657                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1658                              "%02x:%02x:%02x:%02x:%02x:%02x",
1659                              perm_addr->addr_bytes[0],
1660                              perm_addr->addr_bytes[1],
1661                              perm_addr->addr_bytes[2],
1662                              perm_addr->addr_bytes[3],
1663                              perm_addr->addr_bytes[4],
1664                              perm_addr->addr_bytes[5]);
1665         }
1666
1667         /* Copy the permanent MAC address */
1668         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1669
1670         /* reset the hardware with the new settings */
1671         diag = hw->mac.ops.start_hw(hw);
1672         switch (diag) {
1673         case  0:
1674                 break;
1675
1676         default:
1677                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1678                 return -EIO;
1679         }
1680
1681         rte_intr_callback_register(intr_handle,
1682                                    ixgbevf_dev_interrupt_handler, eth_dev);
1683         rte_intr_enable(intr_handle);
1684         ixgbevf_intr_enable(eth_dev);
1685
1686         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1687                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1688                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1689
1690         return 0;
1691 }
1692
1693 /* Virtual Function device uninit */
1694
1695 static int
1696 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1697 {
1698         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1699         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1700         struct ixgbe_hw *hw;
1701
1702         PMD_INIT_FUNC_TRACE();
1703
1704         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1705                 return -EPERM;
1706
1707         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1708
1709         if (hw->adapter_stopped == 0)
1710                 ixgbevf_dev_close(eth_dev);
1711
1712         eth_dev->dev_ops = NULL;
1713         eth_dev->rx_pkt_burst = NULL;
1714         eth_dev->tx_pkt_burst = NULL;
1715
1716         /* Disable the interrupts for VF */
1717         ixgbevf_intr_disable(eth_dev);
1718
1719         rte_free(eth_dev->data->mac_addrs);
1720         eth_dev->data->mac_addrs = NULL;
1721
1722         rte_intr_disable(intr_handle);
1723         rte_intr_callback_unregister(intr_handle,
1724                                      ixgbevf_dev_interrupt_handler, eth_dev);
1725
1726         return 0;
1727 }
1728
1729 static int
1730 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1731                 struct rte_pci_device *pci_dev)
1732 {
1733         char name[RTE_ETH_NAME_MAX_LEN];
1734         struct rte_eth_dev *pf_ethdev;
1735         struct rte_eth_devargs eth_da;
1736         int i, retval;
1737
1738         if (pci_dev->device.devargs) {
1739                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1740                                 &eth_da);
1741                 if (retval)
1742                         return retval;
1743         } else
1744                 memset(&eth_da, 0, sizeof(eth_da));
1745
1746         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1747                 sizeof(struct ixgbe_adapter),
1748                 eth_dev_pci_specific_init, pci_dev,
1749                 eth_ixgbe_dev_init, NULL);
1750
1751         if (retval || eth_da.nb_representor_ports < 1)
1752                 return retval;
1753
1754         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1755         if (pf_ethdev == NULL)
1756                 return -ENODEV;
1757
1758         /* probe VF representor ports */
1759         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1760                 struct ixgbe_vf_info *vfinfo;
1761                 struct ixgbe_vf_representor representor;
1762
1763                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1764                         pf_ethdev->data->dev_private);
1765                 if (vfinfo == NULL) {
1766                         PMD_DRV_LOG(ERR,
1767                                 "no virtual functions supported by PF");
1768                         break;
1769                 }
1770
1771                 representor.vf_id = eth_da.representor_ports[i];
1772                 representor.switch_domain_id = vfinfo->switch_domain_id;
1773                 representor.pf_ethdev = pf_ethdev;
1774
1775                 /* representor port net_bdf_port */
1776                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1777                         pci_dev->device.name,
1778                         eth_da.representor_ports[i]);
1779
1780                 retval = rte_eth_dev_create(&pci_dev->device, name,
1781                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1782                         ixgbe_vf_representor_init, &representor);
1783
1784                 if (retval)
1785                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1786                                 "representor %s.", name);
1787         }
1788
1789         return 0;
1790 }
1791
1792 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1793 {
1794         struct rte_eth_dev *ethdev;
1795
1796         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1797         if (!ethdev)
1798                 return -ENODEV;
1799
1800         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1801                 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1802         else
1803                 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1804 }
1805
1806 static struct rte_pci_driver rte_ixgbe_pmd = {
1807         .id_table = pci_id_ixgbe_map,
1808         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1809                      RTE_PCI_DRV_IOVA_AS_VA,
1810         .probe = eth_ixgbe_pci_probe,
1811         .remove = eth_ixgbe_pci_remove,
1812 };
1813
1814 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1815         struct rte_pci_device *pci_dev)
1816 {
1817         return rte_eth_dev_pci_generic_probe(pci_dev,
1818                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1819 }
1820
1821 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1822 {
1823         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1824 }
1825
1826 /*
1827  * virtual function driver struct
1828  */
1829 static struct rte_pci_driver rte_ixgbevf_pmd = {
1830         .id_table = pci_id_ixgbevf_map,
1831         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1832         .probe = eth_ixgbevf_pci_probe,
1833         .remove = eth_ixgbevf_pci_remove,
1834 };
1835
1836 static int
1837 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1838 {
1839         struct ixgbe_hw *hw =
1840                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1841         struct ixgbe_vfta *shadow_vfta =
1842                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1843         uint32_t vfta;
1844         uint32_t vid_idx;
1845         uint32_t vid_bit;
1846
1847         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1848         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1849         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1850         if (on)
1851                 vfta |= vid_bit;
1852         else
1853                 vfta &= ~vid_bit;
1854         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1855
1856         /* update local VFTA copy */
1857         shadow_vfta->vfta[vid_idx] = vfta;
1858
1859         return 0;
1860 }
1861
1862 static void
1863 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1864 {
1865         if (on)
1866                 ixgbe_vlan_hw_strip_enable(dev, queue);
1867         else
1868                 ixgbe_vlan_hw_strip_disable(dev, queue);
1869 }
1870
1871 static int
1872 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1873                     enum rte_vlan_type vlan_type,
1874                     uint16_t tpid)
1875 {
1876         struct ixgbe_hw *hw =
1877                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1878         int ret = 0;
1879         uint32_t reg;
1880         uint32_t qinq;
1881
1882         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1883         qinq &= IXGBE_DMATXCTL_GDV;
1884
1885         switch (vlan_type) {
1886         case ETH_VLAN_TYPE_INNER:
1887                 if (qinq) {
1888                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1889                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1890                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1891                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1892                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1893                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1894                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1895                 } else {
1896                         ret = -ENOTSUP;
1897                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1898                                     " by single VLAN");
1899                 }
1900                 break;
1901         case ETH_VLAN_TYPE_OUTER:
1902                 if (qinq) {
1903                         /* Only the high 16-bits is valid */
1904                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1905                                         IXGBE_EXVET_VET_EXT_SHIFT);
1906                 } else {
1907                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1908                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1909                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1910                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1911                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1912                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1913                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1914                 }
1915
1916                 break;
1917         default:
1918                 ret = -EINVAL;
1919                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1920                 break;
1921         }
1922
1923         return ret;
1924 }
1925
1926 void
1927 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1928 {
1929         struct ixgbe_hw *hw =
1930                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1931         uint32_t vlnctrl;
1932
1933         PMD_INIT_FUNC_TRACE();
1934
1935         /* Filter Table Disable */
1936         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1937         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1938
1939         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1940 }
1941
1942 void
1943 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1944 {
1945         struct ixgbe_hw *hw =
1946                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1947         struct ixgbe_vfta *shadow_vfta =
1948                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1949         uint32_t vlnctrl;
1950         uint16_t i;
1951
1952         PMD_INIT_FUNC_TRACE();
1953
1954         /* Filter Table Enable */
1955         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1956         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1957         vlnctrl |= IXGBE_VLNCTRL_VFE;
1958
1959         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1960
1961         /* write whatever is in local vfta copy */
1962         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1963                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1964 }
1965
1966 static void
1967 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1968 {
1969         struct ixgbe_hwstrip *hwstrip =
1970                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1971         struct ixgbe_rx_queue *rxq;
1972
1973         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1974                 return;
1975
1976         if (on)
1977                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1978         else
1979                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1980
1981         if (queue >= dev->data->nb_rx_queues)
1982                 return;
1983
1984         rxq = dev->data->rx_queues[queue];
1985
1986         if (on) {
1987                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1988                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1989         } else {
1990                 rxq->vlan_flags = PKT_RX_VLAN;
1991                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1992         }
1993 }
1994
1995 static void
1996 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1997 {
1998         struct ixgbe_hw *hw =
1999                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2000         uint32_t ctrl;
2001
2002         PMD_INIT_FUNC_TRACE();
2003
2004         if (hw->mac.type == ixgbe_mac_82598EB) {
2005                 /* No queue level support */
2006                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2007                 return;
2008         }
2009
2010         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2011         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2012         ctrl &= ~IXGBE_RXDCTL_VME;
2013         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2014
2015         /* record those setting for HW strip per queue */
2016         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2017 }
2018
2019 static void
2020 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2021 {
2022         struct ixgbe_hw *hw =
2023                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2024         uint32_t ctrl;
2025
2026         PMD_INIT_FUNC_TRACE();
2027
2028         if (hw->mac.type == ixgbe_mac_82598EB) {
2029                 /* No queue level supported */
2030                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2031                 return;
2032         }
2033
2034         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2035         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2036         ctrl |= IXGBE_RXDCTL_VME;
2037         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2038
2039         /* record those setting for HW strip per queue */
2040         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2041 }
2042
2043 static void
2044 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2045 {
2046         struct ixgbe_hw *hw =
2047                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2048         uint32_t ctrl;
2049
2050         PMD_INIT_FUNC_TRACE();
2051
2052         /* DMATXCTRL: Geric Double VLAN Disable */
2053         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2054         ctrl &= ~IXGBE_DMATXCTL_GDV;
2055         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2056
2057         /* CTRL_EXT: Global Double VLAN Disable */
2058         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2059         ctrl &= ~IXGBE_EXTENDED_VLAN;
2060         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2061
2062 }
2063
2064 static void
2065 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2066 {
2067         struct ixgbe_hw *hw =
2068                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2069         uint32_t ctrl;
2070
2071         PMD_INIT_FUNC_TRACE();
2072
2073         /* DMATXCTRL: Geric Double VLAN Enable */
2074         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2075         ctrl |= IXGBE_DMATXCTL_GDV;
2076         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2077
2078         /* CTRL_EXT: Global Double VLAN Enable */
2079         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2080         ctrl |= IXGBE_EXTENDED_VLAN;
2081         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2082
2083         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2084         if (hw->mac.type == ixgbe_mac_X550 ||
2085             hw->mac.type == ixgbe_mac_X550EM_x ||
2086             hw->mac.type == ixgbe_mac_X550EM_a) {
2087                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2088                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2089                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2090         }
2091
2092         /*
2093          * VET EXT field in the EXVET register = 0x8100 by default
2094          * So no need to change. Same to VT field of DMATXCTL register
2095          */
2096 }
2097
2098 void
2099 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2100 {
2101         struct ixgbe_hw *hw =
2102                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2103         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2104         uint32_t ctrl;
2105         uint16_t i;
2106         struct ixgbe_rx_queue *rxq;
2107         bool on;
2108
2109         PMD_INIT_FUNC_TRACE();
2110
2111         if (hw->mac.type == ixgbe_mac_82598EB) {
2112                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2113                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2114                         ctrl |= IXGBE_VLNCTRL_VME;
2115                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2116                 } else {
2117                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2118                         ctrl &= ~IXGBE_VLNCTRL_VME;
2119                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2120                 }
2121         } else {
2122                 /*
2123                  * Other 10G NIC, the VLAN strip can be setup
2124                  * per queue in RXDCTL
2125                  */
2126                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2127                         rxq = dev->data->rx_queues[i];
2128                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2129                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2130                                 ctrl |= IXGBE_RXDCTL_VME;
2131                                 on = TRUE;
2132                         } else {
2133                                 ctrl &= ~IXGBE_RXDCTL_VME;
2134                                 on = FALSE;
2135                         }
2136                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2137
2138                         /* record those setting for HW strip per queue */
2139                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2140                 }
2141         }
2142 }
2143
2144 static void
2145 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2146 {
2147         uint16_t i;
2148         struct rte_eth_rxmode *rxmode;
2149         struct ixgbe_rx_queue *rxq;
2150
2151         if (mask & ETH_VLAN_STRIP_MASK) {
2152                 rxmode = &dev->data->dev_conf.rxmode;
2153                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2154                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2155                                 rxq = dev->data->rx_queues[i];
2156                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2157                         }
2158                 else
2159                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2160                                 rxq = dev->data->rx_queues[i];
2161                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2162                         }
2163         }
2164 }
2165
2166 static int
2167 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2168 {
2169         struct rte_eth_rxmode *rxmode;
2170         rxmode = &dev->data->dev_conf.rxmode;
2171
2172         if (mask & ETH_VLAN_STRIP_MASK) {
2173                 ixgbe_vlan_hw_strip_config(dev);
2174         }
2175
2176         if (mask & ETH_VLAN_FILTER_MASK) {
2177                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2178                         ixgbe_vlan_hw_filter_enable(dev);
2179                 else
2180                         ixgbe_vlan_hw_filter_disable(dev);
2181         }
2182
2183         if (mask & ETH_VLAN_EXTEND_MASK) {
2184                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2185                         ixgbe_vlan_hw_extend_enable(dev);
2186                 else
2187                         ixgbe_vlan_hw_extend_disable(dev);
2188         }
2189
2190         return 0;
2191 }
2192
2193 static int
2194 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2195 {
2196         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2197
2198         ixgbe_vlan_offload_config(dev, mask);
2199
2200         return 0;
2201 }
2202
2203 static void
2204 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2205 {
2206         struct ixgbe_hw *hw =
2207                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2208         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2209         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2210
2211         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2212         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2213 }
2214
2215 static int
2216 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2217 {
2218         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2219
2220         switch (nb_rx_q) {
2221         case 1:
2222         case 2:
2223                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2224                 break;
2225         case 4:
2226                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2227                 break;
2228         default:
2229                 return -EINVAL;
2230         }
2231
2232         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2233                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2234         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2235                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2236         return 0;
2237 }
2238
2239 static int
2240 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2241 {
2242         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2243         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2244         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2245         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2246
2247         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2248                 /* check multi-queue mode */
2249                 switch (dev_conf->rxmode.mq_mode) {
2250                 case ETH_MQ_RX_VMDQ_DCB:
2251                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2252                         break;
2253                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2254                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2255                         PMD_INIT_LOG(ERR, "SRIOV active,"
2256                                         " unsupported mq_mode rx %d.",
2257                                         dev_conf->rxmode.mq_mode);
2258                         return -EINVAL;
2259                 case ETH_MQ_RX_RSS:
2260                 case ETH_MQ_RX_VMDQ_RSS:
2261                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2262                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2263                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2264                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2265                                                 " invalid queue number"
2266                                                 " for VMDQ RSS, allowed"
2267                                                 " value are 1, 2 or 4.");
2268                                         return -EINVAL;
2269                                 }
2270                         break;
2271                 case ETH_MQ_RX_VMDQ_ONLY:
2272                 case ETH_MQ_RX_NONE:
2273                         /* if nothing mq mode configure, use default scheme */
2274                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2275                         break;
2276                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2277                         /* SRIOV only works in VMDq enable mode */
2278                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2279                                         " wrong mq_mode rx %d.",
2280                                         dev_conf->rxmode.mq_mode);
2281                         return -EINVAL;
2282                 }
2283
2284                 switch (dev_conf->txmode.mq_mode) {
2285                 case ETH_MQ_TX_VMDQ_DCB:
2286                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2287                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2288                         break;
2289                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2290                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2291                         break;
2292                 }
2293
2294                 /* check valid queue number */
2295                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2296                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2297                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2298                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2299                                         " must be less than or equal to %d.",
2300                                         nb_rx_q, nb_tx_q,
2301                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2302                         return -EINVAL;
2303                 }
2304         } else {
2305                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2306                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2307                                           " not supported.");
2308                         return -EINVAL;
2309                 }
2310                 /* check configuration for vmdb+dcb mode */
2311                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2312                         const struct rte_eth_vmdq_dcb_conf *conf;
2313
2314                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2315                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2316                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2317                                 return -EINVAL;
2318                         }
2319                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2320                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2321                                conf->nb_queue_pools == ETH_32_POOLS)) {
2322                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2323                                                 " nb_queue_pools must be %d or %d.",
2324                                                 ETH_16_POOLS, ETH_32_POOLS);
2325                                 return -EINVAL;
2326                         }
2327                 }
2328                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2329                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2330
2331                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2332                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2333                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2334                                 return -EINVAL;
2335                         }
2336                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2337                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2338                                conf->nb_queue_pools == ETH_32_POOLS)) {
2339                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2340                                                 " nb_queue_pools != %d and"
2341                                                 " nb_queue_pools != %d.",
2342                                                 ETH_16_POOLS, ETH_32_POOLS);
2343                                 return -EINVAL;
2344                         }
2345                 }
2346
2347                 /* For DCB mode check our configuration before we go further */
2348                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2349                         const struct rte_eth_dcb_rx_conf *conf;
2350
2351                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2352                         if (!(conf->nb_tcs == ETH_4_TCS ||
2353                                conf->nb_tcs == ETH_8_TCS)) {
2354                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2355                                                 " and nb_tcs != %d.",
2356                                                 ETH_4_TCS, ETH_8_TCS);
2357                                 return -EINVAL;
2358                         }
2359                 }
2360
2361                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2362                         const struct rte_eth_dcb_tx_conf *conf;
2363
2364                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2365                         if (!(conf->nb_tcs == ETH_4_TCS ||
2366                                conf->nb_tcs == ETH_8_TCS)) {
2367                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2368                                                 " and nb_tcs != %d.",
2369                                                 ETH_4_TCS, ETH_8_TCS);
2370                                 return -EINVAL;
2371                         }
2372                 }
2373
2374                 /*
2375                  * When DCB/VT is off, maximum number of queues changes,
2376                  * except for 82598EB, which remains constant.
2377                  */
2378                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2379                                 hw->mac.type != ixgbe_mac_82598EB) {
2380                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2381                                 PMD_INIT_LOG(ERR,
2382                                              "Neither VT nor DCB are enabled, "
2383                                              "nb_tx_q > %d.",
2384                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2385                                 return -EINVAL;
2386                         }
2387                 }
2388         }
2389         return 0;
2390 }
2391
2392 static int
2393 ixgbe_dev_configure(struct rte_eth_dev *dev)
2394 {
2395         struct ixgbe_interrupt *intr =
2396                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2397         struct ixgbe_adapter *adapter =
2398                 (struct ixgbe_adapter *)dev->data->dev_private;
2399         int ret;
2400
2401         PMD_INIT_FUNC_TRACE();
2402         /* multipe queue mode checking */
2403         ret  = ixgbe_check_mq_mode(dev);
2404         if (ret != 0) {
2405                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2406                             ret);
2407                 return ret;
2408         }
2409
2410         /* set flag to update link status after init */
2411         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2412
2413         /*
2414          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2415          * allocation or vector Rx preconditions we will reset it.
2416          */
2417         adapter->rx_bulk_alloc_allowed = true;
2418         adapter->rx_vec_allowed = true;
2419
2420         return 0;
2421 }
2422
2423 static void
2424 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2425 {
2426         struct ixgbe_hw *hw =
2427                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2428         struct ixgbe_interrupt *intr =
2429                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2430         uint32_t gpie;
2431
2432         /* only set up it on X550EM_X */
2433         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2434                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2435                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2436                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2437                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2438                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2439         }
2440 }
2441
2442 int
2443 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2444                         uint16_t tx_rate, uint64_t q_msk)
2445 {
2446         struct ixgbe_hw *hw;
2447         struct ixgbe_vf_info *vfinfo;
2448         struct rte_eth_link link;
2449         uint8_t  nb_q_per_pool;
2450         uint32_t queue_stride;
2451         uint32_t queue_idx, idx = 0, vf_idx;
2452         uint32_t queue_end;
2453         uint16_t total_rate = 0;
2454         struct rte_pci_device *pci_dev;
2455
2456         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2457         rte_eth_link_get_nowait(dev->data->port_id, &link);
2458
2459         if (vf >= pci_dev->max_vfs)
2460                 return -EINVAL;
2461
2462         if (tx_rate > link.link_speed)
2463                 return -EINVAL;
2464
2465         if (q_msk == 0)
2466                 return 0;
2467
2468         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2469         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2470         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2471         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2472         queue_idx = vf * queue_stride;
2473         queue_end = queue_idx + nb_q_per_pool - 1;
2474         if (queue_end >= hw->mac.max_tx_queues)
2475                 return -EINVAL;
2476
2477         if (vfinfo) {
2478                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2479                         if (vf_idx == vf)
2480                                 continue;
2481                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2482                                 idx++)
2483                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2484                 }
2485         } else {
2486                 return -EINVAL;
2487         }
2488
2489         /* Store tx_rate for this vf. */
2490         for (idx = 0; idx < nb_q_per_pool; idx++) {
2491                 if (((uint64_t)0x1 << idx) & q_msk) {
2492                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2493                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2494                         total_rate += tx_rate;
2495                 }
2496         }
2497
2498         if (total_rate > dev->data->dev_link.link_speed) {
2499                 /* Reset stored TX rate of the VF if it causes exceed
2500                  * link speed.
2501                  */
2502                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2503                 return -EINVAL;
2504         }
2505
2506         /* Set RTTBCNRC of each queue/pool for vf X  */
2507         for (; queue_idx <= queue_end; queue_idx++) {
2508                 if (0x1 & q_msk)
2509                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2510                 q_msk = q_msk >> 1;
2511         }
2512
2513         return 0;
2514 }
2515
2516 /*
2517  * Configure device link speed and setup link.
2518  * It returns 0 on success.
2519  */
2520 static int
2521 ixgbe_dev_start(struct rte_eth_dev *dev)
2522 {
2523         struct ixgbe_hw *hw =
2524                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2525         struct ixgbe_vf_info *vfinfo =
2526                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2527         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2528         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2529         uint32_t intr_vector = 0;
2530         int err, link_up = 0, negotiate = 0;
2531         uint32_t speed = 0;
2532         uint32_t allowed_speeds = 0;
2533         int mask = 0;
2534         int status;
2535         uint16_t vf, idx;
2536         uint32_t *link_speeds;
2537         struct ixgbe_tm_conf *tm_conf =
2538                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2539
2540         PMD_INIT_FUNC_TRACE();
2541
2542         /* IXGBE devices don't support:
2543         *    - half duplex (checked afterwards for valid speeds)
2544         *    - fixed speed: TODO implement
2545         */
2546         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2547                 PMD_INIT_LOG(ERR,
2548                 "Invalid link_speeds for port %u, fix speed not supported",
2549                                 dev->data->port_id);
2550                 return -EINVAL;
2551         }
2552
2553         /* disable uio/vfio intr/eventfd mapping */
2554         rte_intr_disable(intr_handle);
2555
2556         /* stop adapter */
2557         hw->adapter_stopped = 0;
2558         ixgbe_stop_adapter(hw);
2559
2560         /* reinitialize adapter
2561          * this calls reset and start
2562          */
2563         status = ixgbe_pf_reset_hw(hw);
2564         if (status != 0)
2565                 return -1;
2566         hw->mac.ops.start_hw(hw);
2567         hw->mac.get_link_status = true;
2568
2569         /* configure PF module if SRIOV enabled */
2570         ixgbe_pf_host_configure(dev);
2571
2572         ixgbe_dev_phy_intr_setup(dev);
2573
2574         /* check and configure queue intr-vector mapping */
2575         if ((rte_intr_cap_multiple(intr_handle) ||
2576              !RTE_ETH_DEV_SRIOV(dev).active) &&
2577             dev->data->dev_conf.intr_conf.rxq != 0) {
2578                 intr_vector = dev->data->nb_rx_queues;
2579                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2580                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2581                                         IXGBE_MAX_INTR_QUEUE_NUM);
2582                         return -ENOTSUP;
2583                 }
2584                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2585                         return -1;
2586         }
2587
2588         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2589                 intr_handle->intr_vec =
2590                         rte_zmalloc("intr_vec",
2591                                     dev->data->nb_rx_queues * sizeof(int), 0);
2592                 if (intr_handle->intr_vec == NULL) {
2593                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2594                                      " intr_vec", dev->data->nb_rx_queues);
2595                         return -ENOMEM;
2596                 }
2597         }
2598
2599         /* confiugre msix for sleep until rx interrupt */
2600         ixgbe_configure_msix(dev);
2601
2602         /* initialize transmission unit */
2603         ixgbe_dev_tx_init(dev);
2604
2605         /* This can fail when allocating mbufs for descriptor rings */
2606         err = ixgbe_dev_rx_init(dev);
2607         if (err) {
2608                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2609                 goto error;
2610         }
2611
2612         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2613                 ETH_VLAN_EXTEND_MASK;
2614         err = ixgbe_vlan_offload_config(dev, mask);
2615         if (err) {
2616                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2617                 goto error;
2618         }
2619
2620         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2621                 /* Enable vlan filtering for VMDq */
2622                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2623         }
2624
2625         /* Configure DCB hw */
2626         ixgbe_configure_dcb(dev);
2627
2628         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2629                 err = ixgbe_fdir_configure(dev);
2630                 if (err)
2631                         goto error;
2632         }
2633
2634         /* Restore vf rate limit */
2635         if (vfinfo != NULL) {
2636                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2637                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2638                                 if (vfinfo[vf].tx_rate[idx] != 0)
2639                                         ixgbe_set_vf_rate_limit(
2640                                                 dev, vf,
2641                                                 vfinfo[vf].tx_rate[idx],
2642                                                 1 << idx);
2643         }
2644
2645         ixgbe_restore_statistics_mapping(dev);
2646
2647         err = ixgbe_dev_rxtx_start(dev);
2648         if (err < 0) {
2649                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2650                 goto error;
2651         }
2652
2653         /* Skip link setup if loopback mode is enabled for 82599. */
2654         if (hw->mac.type == ixgbe_mac_82599EB &&
2655                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2656                 goto skip_link_setup;
2657
2658         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2659                 err = hw->mac.ops.setup_sfp(hw);
2660                 if (err)
2661                         goto error;
2662         }
2663
2664         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2665                 /* Turn on the copper */
2666                 ixgbe_set_phy_power(hw, true);
2667         } else {
2668                 /* Turn on the laser */
2669                 ixgbe_enable_tx_laser(hw);
2670         }
2671
2672         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2673         if (err)
2674                 goto error;
2675         dev->data->dev_link.link_status = link_up;
2676
2677         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2678         if (err)
2679                 goto error;
2680
2681         switch (hw->mac.type) {
2682         case ixgbe_mac_X550:
2683         case ixgbe_mac_X550EM_x:
2684         case ixgbe_mac_X550EM_a:
2685                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2686                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2687                         ETH_LINK_SPEED_10G;
2688                 break;
2689         default:
2690                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2691                         ETH_LINK_SPEED_10G;
2692         }
2693
2694         link_speeds = &dev->data->dev_conf.link_speeds;
2695         if (*link_speeds & ~allowed_speeds) {
2696                 PMD_INIT_LOG(ERR, "Invalid link setting");
2697                 goto error;
2698         }
2699
2700         speed = 0x0;
2701         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2702                 switch (hw->mac.type) {
2703                 case ixgbe_mac_82598EB:
2704                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2705                         break;
2706                 case ixgbe_mac_82599EB:
2707                 case ixgbe_mac_X540:
2708                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2709                         break;
2710                 case ixgbe_mac_X550:
2711                 case ixgbe_mac_X550EM_x:
2712                 case ixgbe_mac_X550EM_a:
2713                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2714                         break;
2715                 default:
2716                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2717                 }
2718         } else {
2719                 if (*link_speeds & ETH_LINK_SPEED_10G)
2720                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2721                 if (*link_speeds & ETH_LINK_SPEED_5G)
2722                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2723                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2724                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2725                 if (*link_speeds & ETH_LINK_SPEED_1G)
2726                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2727                 if (*link_speeds & ETH_LINK_SPEED_100M)
2728                         speed |= IXGBE_LINK_SPEED_100_FULL;
2729         }
2730
2731         err = ixgbe_setup_link(hw, speed, link_up);
2732         if (err)
2733                 goto error;
2734
2735         ixgbe_dev_link_update(dev, 0);
2736
2737 skip_link_setup:
2738
2739         if (rte_intr_allow_others(intr_handle)) {
2740                 /* check if lsc interrupt is enabled */
2741                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2742                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2743                 else
2744                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2745                 ixgbe_dev_macsec_interrupt_setup(dev);
2746         } else {
2747                 rte_intr_callback_unregister(intr_handle,
2748                                              ixgbe_dev_interrupt_handler, dev);
2749                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2750                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2751                                      " no intr multiplex");
2752         }
2753
2754         /* check if rxq interrupt is enabled */
2755         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2756             rte_intr_dp_is_en(intr_handle))
2757                 ixgbe_dev_rxq_interrupt_setup(dev);
2758
2759         /* enable uio/vfio intr/eventfd mapping */
2760         rte_intr_enable(intr_handle);
2761
2762         /* resume enabled intr since hw reset */
2763         ixgbe_enable_intr(dev);
2764         ixgbe_l2_tunnel_conf(dev);
2765         ixgbe_filter_restore(dev);
2766
2767         if (tm_conf->root && !tm_conf->committed)
2768                 PMD_DRV_LOG(WARNING,
2769                             "please call hierarchy_commit() "
2770                             "before starting the port");
2771
2772         return 0;
2773
2774 error:
2775         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2776         ixgbe_dev_clear_queues(dev);
2777         return -EIO;
2778 }
2779
2780 /*
2781  * Stop device: disable rx and tx functions to allow for reconfiguring.
2782  */
2783 static void
2784 ixgbe_dev_stop(struct rte_eth_dev *dev)
2785 {
2786         struct rte_eth_link link;
2787         struct ixgbe_hw *hw =
2788                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2789         struct ixgbe_vf_info *vfinfo =
2790                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2791         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2792         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2793         int vf;
2794         struct ixgbe_tm_conf *tm_conf =
2795                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2796
2797         PMD_INIT_FUNC_TRACE();
2798
2799         /* disable interrupts */
2800         ixgbe_disable_intr(hw);
2801
2802         /* reset the NIC */
2803         ixgbe_pf_reset_hw(hw);
2804         hw->adapter_stopped = 0;
2805
2806         /* stop adapter */
2807         ixgbe_stop_adapter(hw);
2808
2809         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2810                 vfinfo[vf].clear_to_send = false;
2811
2812         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2813                 /* Turn off the copper */
2814                 ixgbe_set_phy_power(hw, false);
2815         } else {
2816                 /* Turn off the laser */
2817                 ixgbe_disable_tx_laser(hw);
2818         }
2819
2820         ixgbe_dev_clear_queues(dev);
2821
2822         /* Clear stored conf */
2823         dev->data->scattered_rx = 0;
2824         dev->data->lro = 0;
2825
2826         /* Clear recorded link status */
2827         memset(&link, 0, sizeof(link));
2828         rte_eth_linkstatus_set(dev, &link);
2829
2830         if (!rte_intr_allow_others(intr_handle))
2831                 /* resume to the default handler */
2832                 rte_intr_callback_register(intr_handle,
2833                                            ixgbe_dev_interrupt_handler,
2834                                            (void *)dev);
2835
2836         /* Clean datapath event and queue/vec mapping */
2837         rte_intr_efd_disable(intr_handle);
2838         if (intr_handle->intr_vec != NULL) {
2839                 rte_free(intr_handle->intr_vec);
2840                 intr_handle->intr_vec = NULL;
2841         }
2842
2843         /* reset hierarchy commit */
2844         tm_conf->committed = false;
2845 }
2846
2847 /*
2848  * Set device link up: enable tx.
2849  */
2850 static int
2851 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2852 {
2853         struct ixgbe_hw *hw =
2854                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2855         if (hw->mac.type == ixgbe_mac_82599EB) {
2856 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2857                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2858                         /* Not suported in bypass mode */
2859                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2860                                      "by device id 0x%x", hw->device_id);
2861                         return -ENOTSUP;
2862                 }
2863 #endif
2864         }
2865
2866         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2867                 /* Turn on the copper */
2868                 ixgbe_set_phy_power(hw, true);
2869         } else {
2870                 /* Turn on the laser */
2871                 ixgbe_enable_tx_laser(hw);
2872         }
2873
2874         return 0;
2875 }
2876
2877 /*
2878  * Set device link down: disable tx.
2879  */
2880 static int
2881 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2882 {
2883         struct ixgbe_hw *hw =
2884                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2885         if (hw->mac.type == ixgbe_mac_82599EB) {
2886 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2887                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2888                         /* Not suported in bypass mode */
2889                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2890                                      "by device id 0x%x", hw->device_id);
2891                         return -ENOTSUP;
2892                 }
2893 #endif
2894         }
2895
2896         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2897                 /* Turn off the copper */
2898                 ixgbe_set_phy_power(hw, false);
2899         } else {
2900                 /* Turn off the laser */
2901                 ixgbe_disable_tx_laser(hw);
2902         }
2903
2904         return 0;
2905 }
2906
2907 /*
2908  * Reset and stop device.
2909  */
2910 static void
2911 ixgbe_dev_close(struct rte_eth_dev *dev)
2912 {
2913         struct ixgbe_hw *hw =
2914                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2915
2916         PMD_INIT_FUNC_TRACE();
2917
2918         ixgbe_pf_reset_hw(hw);
2919
2920         ixgbe_dev_stop(dev);
2921         hw->adapter_stopped = 1;
2922
2923         ixgbe_dev_free_queues(dev);
2924
2925         ixgbe_disable_pcie_master(hw);
2926
2927         /* reprogram the RAR[0] in case user changed it. */
2928         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2929 }
2930
2931 /*
2932  * Reset PF device.
2933  */
2934 static int
2935 ixgbe_dev_reset(struct rte_eth_dev *dev)
2936 {
2937         int ret;
2938
2939         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2940          * its VF to make them align with it. The detailed notification
2941          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2942          * To avoid unexpected behavior in VF, currently reset of PF with
2943          * SR-IOV activation is not supported. It might be supported later.
2944          */
2945         if (dev->data->sriov.active)
2946                 return -ENOTSUP;
2947
2948         ret = eth_ixgbe_dev_uninit(dev);
2949         if (ret)
2950                 return ret;
2951
2952         ret = eth_ixgbe_dev_init(dev, NULL);
2953
2954         return ret;
2955 }
2956
2957 static void
2958 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2959                            struct ixgbe_hw_stats *hw_stats,
2960                            struct ixgbe_macsec_stats *macsec_stats,
2961                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2962                            uint64_t *total_qprc, uint64_t *total_qprdc)
2963 {
2964         uint32_t bprc, lxon, lxoff, total;
2965         uint32_t delta_gprc = 0;
2966         unsigned i;
2967         /* Workaround for RX byte count not including CRC bytes when CRC
2968          * strip is enabled. CRC bytes are removed from counters when crc_strip
2969          * is disabled.
2970          */
2971         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2972                         IXGBE_HLREG0_RXCRCSTRP);
2973
2974         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2975         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2976         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2977         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2978
2979         for (i = 0; i < 8; i++) {
2980                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2981
2982                 /* global total per queue */
2983                 hw_stats->mpc[i] += mp;
2984                 /* Running comprehensive total for stats display */
2985                 *total_missed_rx += hw_stats->mpc[i];
2986                 if (hw->mac.type == ixgbe_mac_82598EB) {
2987                         hw_stats->rnbc[i] +=
2988                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2989                         hw_stats->pxonrxc[i] +=
2990                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2991                         hw_stats->pxoffrxc[i] +=
2992                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2993                 } else {
2994                         hw_stats->pxonrxc[i] +=
2995                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2996                         hw_stats->pxoffrxc[i] +=
2997                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2998                         hw_stats->pxon2offc[i] +=
2999                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3000                 }
3001                 hw_stats->pxontxc[i] +=
3002                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3003                 hw_stats->pxofftxc[i] +=
3004                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3005         }
3006         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3007                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3008                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3009                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3010
3011                 delta_gprc += delta_qprc;
3012
3013                 hw_stats->qprc[i] += delta_qprc;
3014                 hw_stats->qptc[i] += delta_qptc;
3015
3016                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3017                 hw_stats->qbrc[i] +=
3018                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3019                 if (crc_strip == 0)
3020                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
3021
3022                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3023                 hw_stats->qbtc[i] +=
3024                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3025
3026                 hw_stats->qprdc[i] += delta_qprdc;
3027                 *total_qprdc += hw_stats->qprdc[i];
3028
3029                 *total_qprc += hw_stats->qprc[i];
3030                 *total_qbrc += hw_stats->qbrc[i];
3031         }
3032         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3033         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3034         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3035
3036         /*
3037          * An errata states that gprc actually counts good + missed packets:
3038          * Workaround to set gprc to summated queue packet receives
3039          */
3040         hw_stats->gprc = *total_qprc;
3041
3042         if (hw->mac.type != ixgbe_mac_82598EB) {
3043                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3044                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3045                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3046                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3047                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3048                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3049                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3050                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3051         } else {
3052                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3053                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3054                 /* 82598 only has a counter in the high register */
3055                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3056                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3057                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3058         }
3059         uint64_t old_tpr = hw_stats->tpr;
3060
3061         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3062         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3063
3064         if (crc_strip == 0)
3065                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3066
3067         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3068         hw_stats->gptc += delta_gptc;
3069         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3070         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3071
3072         /*
3073          * Workaround: mprc hardware is incorrectly counting
3074          * broadcasts, so for now we subtract those.
3075          */
3076         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3077         hw_stats->bprc += bprc;
3078         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3079         if (hw->mac.type == ixgbe_mac_82598EB)
3080                 hw_stats->mprc -= bprc;
3081
3082         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3083         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3084         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3085         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3086         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3087         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3088
3089         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3090         hw_stats->lxontxc += lxon;
3091         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3092         hw_stats->lxofftxc += lxoff;
3093         total = lxon + lxoff;
3094
3095         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3096         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3097         hw_stats->gptc -= total;
3098         hw_stats->mptc -= total;
3099         hw_stats->ptc64 -= total;
3100         hw_stats->gotc -= total * ETHER_MIN_LEN;
3101
3102         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3103         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3104         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3105         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3106         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3107         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3108         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3109         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3110         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3111         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3112         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3113         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3114         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3115         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3116         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3117         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3118         /* Only read FCOE on 82599 */
3119         if (hw->mac.type != ixgbe_mac_82598EB) {
3120                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3121                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3122                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3123                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3124                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3125         }
3126
3127         /* Flow Director Stats registers */
3128         if (hw->mac.type != ixgbe_mac_82598EB) {
3129                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3130                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3131                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3132                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3133                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3134                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3135                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3136                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3137                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3138                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3139         }
3140         /* MACsec Stats registers */
3141         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3142         macsec_stats->out_pkts_encrypted +=
3143                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3144         macsec_stats->out_pkts_protected +=
3145                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3146         macsec_stats->out_octets_encrypted +=
3147                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3148         macsec_stats->out_octets_protected +=
3149                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3150         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3151         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3152         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3153         macsec_stats->in_pkts_unknownsci +=
3154                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3155         macsec_stats->in_octets_decrypted +=
3156                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3157         macsec_stats->in_octets_validated +=
3158                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3159         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3160         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3161         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3162         for (i = 0; i < 2; i++) {
3163                 macsec_stats->in_pkts_ok +=
3164                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3165                 macsec_stats->in_pkts_invalid +=
3166                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3167                 macsec_stats->in_pkts_notvalid +=
3168                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3169         }
3170         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3171         macsec_stats->in_pkts_notusingsa +=
3172                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3173 }
3174
3175 /*
3176  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3177  */
3178 static int
3179 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3180 {
3181         struct ixgbe_hw *hw =
3182                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3183         struct ixgbe_hw_stats *hw_stats =
3184                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3185         struct ixgbe_macsec_stats *macsec_stats =
3186                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3187                                 dev->data->dev_private);
3188         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3189         unsigned i;
3190
3191         total_missed_rx = 0;
3192         total_qbrc = 0;
3193         total_qprc = 0;
3194         total_qprdc = 0;
3195
3196         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3197                         &total_qbrc, &total_qprc, &total_qprdc);
3198
3199         if (stats == NULL)
3200                 return -EINVAL;
3201
3202         /* Fill out the rte_eth_stats statistics structure */
3203         stats->ipackets = total_qprc;
3204         stats->ibytes = total_qbrc;
3205         stats->opackets = hw_stats->gptc;
3206         stats->obytes = hw_stats->gotc;
3207
3208         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3209                 stats->q_ipackets[i] = hw_stats->qprc[i];
3210                 stats->q_opackets[i] = hw_stats->qptc[i];
3211                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3212                 stats->q_obytes[i] = hw_stats->qbtc[i];
3213                 stats->q_errors[i] = hw_stats->qprdc[i];
3214         }
3215
3216         /* Rx Errors */
3217         stats->imissed  = total_missed_rx;
3218         stats->ierrors  = hw_stats->crcerrs +
3219                           hw_stats->mspdc +
3220                           hw_stats->rlec +
3221                           hw_stats->ruc +
3222                           hw_stats->roc +
3223                           hw_stats->illerrc +
3224                           hw_stats->errbc +
3225                           hw_stats->rfc +
3226                           hw_stats->fccrc +
3227                           hw_stats->fclast;
3228
3229         /* Tx Errors */
3230         stats->oerrors  = 0;
3231         return 0;
3232 }
3233
3234 static void
3235 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3236 {
3237         struct ixgbe_hw_stats *stats =
3238                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3239
3240         /* HW registers are cleared on read */
3241         ixgbe_dev_stats_get(dev, NULL);
3242
3243         /* Reset software totals */
3244         memset(stats, 0, sizeof(*stats));
3245 }
3246
3247 /* This function calculates the number of xstats based on the current config */
3248 static unsigned
3249 ixgbe_xstats_calc_num(void) {
3250         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3251                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3252                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3253 }
3254
3255 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3256         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3257 {
3258         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3259         unsigned stat, i, count;
3260
3261         if (xstats_names != NULL) {
3262                 count = 0;
3263
3264                 /* Note: limit >= cnt_stats checked upstream
3265                  * in rte_eth_xstats_names()
3266                  */
3267
3268                 /* Extended stats from ixgbe_hw_stats */
3269                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3270                         snprintf(xstats_names[count].name,
3271                                 sizeof(xstats_names[count].name),
3272                                 "%s",
3273                                 rte_ixgbe_stats_strings[i].name);
3274                         count++;
3275                 }
3276
3277                 /* MACsec Stats */
3278                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3279                         snprintf(xstats_names[count].name,
3280                                 sizeof(xstats_names[count].name),
3281                                 "%s",
3282                                 rte_ixgbe_macsec_strings[i].name);
3283                         count++;
3284                 }
3285
3286                 /* RX Priority Stats */
3287                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3288                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3289                                 snprintf(xstats_names[count].name,
3290                                         sizeof(xstats_names[count].name),
3291                                         "rx_priority%u_%s", i,
3292                                         rte_ixgbe_rxq_strings[stat].name);
3293                                 count++;
3294                         }
3295                 }
3296
3297                 /* TX Priority Stats */
3298                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3299                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3300                                 snprintf(xstats_names[count].name,
3301                                         sizeof(xstats_names[count].name),
3302                                         "tx_priority%u_%s", i,
3303                                         rte_ixgbe_txq_strings[stat].name);
3304                                 count++;
3305                         }
3306                 }
3307         }
3308         return cnt_stats;
3309 }
3310
3311 static int ixgbe_dev_xstats_get_names_by_id(
3312         struct rte_eth_dev *dev,
3313         struct rte_eth_xstat_name *xstats_names,
3314         const uint64_t *ids,
3315         unsigned int limit)
3316 {
3317         if (!ids) {
3318                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3319                 unsigned int stat, i, count;
3320
3321                 if (xstats_names != NULL) {
3322                         count = 0;
3323
3324                         /* Note: limit >= cnt_stats checked upstream
3325                          * in rte_eth_xstats_names()
3326                          */
3327
3328                         /* Extended stats from ixgbe_hw_stats */
3329                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3330                                 snprintf(xstats_names[count].name,
3331                                         sizeof(xstats_names[count].name),
3332                                         "%s",
3333                                         rte_ixgbe_stats_strings[i].name);
3334                                 count++;
3335                         }
3336
3337                         /* MACsec Stats */
3338                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3339                                 snprintf(xstats_names[count].name,
3340                                         sizeof(xstats_names[count].name),
3341                                         "%s",
3342                                         rte_ixgbe_macsec_strings[i].name);
3343                                 count++;
3344                         }
3345
3346                         /* RX Priority Stats */
3347                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3348                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3349                                         snprintf(xstats_names[count].name,
3350                                             sizeof(xstats_names[count].name),
3351                                             "rx_priority%u_%s", i,
3352                                             rte_ixgbe_rxq_strings[stat].name);
3353                                         count++;
3354                                 }
3355                         }
3356
3357                         /* TX Priority Stats */
3358                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3359                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3360                                         snprintf(xstats_names[count].name,
3361                                             sizeof(xstats_names[count].name),
3362                                             "tx_priority%u_%s", i,
3363                                             rte_ixgbe_txq_strings[stat].name);
3364                                         count++;
3365                                 }
3366                         }
3367                 }
3368                 return cnt_stats;
3369         }
3370
3371         uint16_t i;
3372         uint16_t size = ixgbe_xstats_calc_num();
3373         struct rte_eth_xstat_name xstats_names_copy[size];
3374
3375         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3376                         size);
3377
3378         for (i = 0; i < limit; i++) {
3379                 if (ids[i] >= size) {
3380                         PMD_INIT_LOG(ERR, "id value isn't valid");
3381                         return -1;
3382                 }
3383                 strcpy(xstats_names[i].name,
3384                                 xstats_names_copy[ids[i]].name);
3385         }
3386         return limit;
3387 }
3388
3389 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3390         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3391 {
3392         unsigned i;
3393
3394         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3395                 return -ENOMEM;
3396
3397         if (xstats_names != NULL)
3398                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3399                         snprintf(xstats_names[i].name,
3400                                 sizeof(xstats_names[i].name),
3401                                 "%s", rte_ixgbevf_stats_strings[i].name);
3402         return IXGBEVF_NB_XSTATS;
3403 }
3404
3405 static int
3406 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3407                                          unsigned n)
3408 {
3409         struct ixgbe_hw *hw =
3410                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3411         struct ixgbe_hw_stats *hw_stats =
3412                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3413         struct ixgbe_macsec_stats *macsec_stats =
3414                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3415                                 dev->data->dev_private);
3416         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3417         unsigned i, stat, count = 0;
3418
3419         count = ixgbe_xstats_calc_num();
3420
3421         if (n < count)
3422                 return count;
3423
3424         total_missed_rx = 0;
3425         total_qbrc = 0;
3426         total_qprc = 0;
3427         total_qprdc = 0;
3428
3429         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3430                         &total_qbrc, &total_qprc, &total_qprdc);
3431
3432         /* If this is a reset xstats is NULL, and we have cleared the
3433          * registers by reading them.
3434          */
3435         if (!xstats)
3436                 return 0;
3437
3438         /* Extended stats from ixgbe_hw_stats */
3439         count = 0;
3440         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3441                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3442                                 rte_ixgbe_stats_strings[i].offset);
3443                 xstats[count].id = count;
3444                 count++;
3445         }
3446
3447         /* MACsec Stats */
3448         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3449                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3450                                 rte_ixgbe_macsec_strings[i].offset);
3451                 xstats[count].id = count;
3452                 count++;
3453         }
3454
3455         /* RX Priority Stats */
3456         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3457                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3458                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3459                                         rte_ixgbe_rxq_strings[stat].offset +
3460                                         (sizeof(uint64_t) * i));
3461                         xstats[count].id = count;
3462                         count++;
3463                 }
3464         }
3465
3466         /* TX Priority Stats */
3467         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3468                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3469                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3470                                         rte_ixgbe_txq_strings[stat].offset +
3471                                         (sizeof(uint64_t) * i));
3472                         xstats[count].id = count;
3473                         count++;
3474                 }
3475         }
3476         return count;
3477 }
3478
3479 static int
3480 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3481                 uint64_t *values, unsigned int n)
3482 {
3483         if (!ids) {
3484                 struct ixgbe_hw *hw =
3485                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3486                 struct ixgbe_hw_stats *hw_stats =
3487                                 IXGBE_DEV_PRIVATE_TO_STATS(
3488                                                 dev->data->dev_private);
3489                 struct ixgbe_macsec_stats *macsec_stats =
3490                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3491                                         dev->data->dev_private);
3492                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3493                 unsigned int i, stat, count = 0;
3494
3495                 count = ixgbe_xstats_calc_num();
3496
3497                 if (!ids && n < count)
3498                         return count;
3499
3500                 total_missed_rx = 0;
3501                 total_qbrc = 0;
3502                 total_qprc = 0;
3503                 total_qprdc = 0;
3504
3505                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3506                                 &total_missed_rx, &total_qbrc, &total_qprc,
3507                                 &total_qprdc);
3508
3509                 /* If this is a reset xstats is NULL, and we have cleared the
3510                  * registers by reading them.
3511                  */
3512                 if (!ids && !values)
3513                         return 0;
3514
3515                 /* Extended stats from ixgbe_hw_stats */
3516                 count = 0;
3517                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3518                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3519                                         rte_ixgbe_stats_strings[i].offset);
3520                         count++;
3521                 }
3522
3523                 /* MACsec Stats */
3524                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3525                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3526                                         rte_ixgbe_macsec_strings[i].offset);
3527                         count++;
3528                 }
3529
3530                 /* RX Priority Stats */
3531                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3532                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3533                                 values[count] =
3534                                         *(uint64_t *)(((char *)hw_stats) +
3535                                         rte_ixgbe_rxq_strings[stat].offset +
3536                                         (sizeof(uint64_t) * i));
3537                                 count++;
3538                         }
3539                 }
3540
3541                 /* TX Priority Stats */
3542                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3543                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3544                                 values[count] =
3545                                         *(uint64_t *)(((char *)hw_stats) +
3546                                         rte_ixgbe_txq_strings[stat].offset +
3547                                         (sizeof(uint64_t) * i));
3548                                 count++;
3549                         }
3550                 }
3551                 return count;
3552         }
3553
3554         uint16_t i;
3555         uint16_t size = ixgbe_xstats_calc_num();
3556         uint64_t values_copy[size];
3557
3558         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3559
3560         for (i = 0; i < n; i++) {
3561                 if (ids[i] >= size) {
3562                         PMD_INIT_LOG(ERR, "id value isn't valid");
3563                         return -1;
3564                 }
3565                 values[i] = values_copy[ids[i]];
3566         }
3567         return n;
3568 }
3569
3570 static void
3571 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3572 {
3573         struct ixgbe_hw_stats *stats =
3574                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3575         struct ixgbe_macsec_stats *macsec_stats =
3576                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3577                                 dev->data->dev_private);
3578
3579         unsigned count = ixgbe_xstats_calc_num();
3580
3581         /* HW registers are cleared on read */
3582         ixgbe_dev_xstats_get(dev, NULL, count);
3583
3584         /* Reset software totals */
3585         memset(stats, 0, sizeof(*stats));
3586         memset(macsec_stats, 0, sizeof(*macsec_stats));
3587 }
3588
3589 static void
3590 ixgbevf_update_stats(struct rte_eth_dev *dev)
3591 {
3592         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3593         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3594                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3595
3596         /* Good Rx packet, include VF loopback */
3597         UPDATE_VF_STAT(IXGBE_VFGPRC,
3598             hw_stats->last_vfgprc, hw_stats->vfgprc);
3599
3600         /* Good Rx octets, include VF loopback */
3601         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3602             hw_stats->last_vfgorc, hw_stats->vfgorc);
3603
3604         /* Good Tx packet, include VF loopback */
3605         UPDATE_VF_STAT(IXGBE_VFGPTC,
3606             hw_stats->last_vfgptc, hw_stats->vfgptc);
3607
3608         /* Good Tx octets, include VF loopback */
3609         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3610             hw_stats->last_vfgotc, hw_stats->vfgotc);
3611
3612         /* Rx Multicst Packet */
3613         UPDATE_VF_STAT(IXGBE_VFMPRC,
3614             hw_stats->last_vfmprc, hw_stats->vfmprc);
3615 }
3616
3617 static int
3618 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3619                        unsigned n)
3620 {
3621         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3622                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3623         unsigned i;
3624
3625         if (n < IXGBEVF_NB_XSTATS)
3626                 return IXGBEVF_NB_XSTATS;
3627
3628         ixgbevf_update_stats(dev);
3629
3630         if (!xstats)
3631                 return 0;
3632
3633         /* Extended stats */
3634         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3635                 xstats[i].id = i;
3636                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3637                         rte_ixgbevf_stats_strings[i].offset);
3638         }
3639
3640         return IXGBEVF_NB_XSTATS;
3641 }
3642
3643 static int
3644 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3645 {
3646         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3647                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3648
3649         ixgbevf_update_stats(dev);
3650
3651         if (stats == NULL)
3652                 return -EINVAL;
3653
3654         stats->ipackets = hw_stats->vfgprc;
3655         stats->ibytes = hw_stats->vfgorc;
3656         stats->opackets = hw_stats->vfgptc;
3657         stats->obytes = hw_stats->vfgotc;
3658         return 0;
3659 }
3660
3661 static void
3662 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3663 {
3664         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3665                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3666
3667         /* Sync HW register to the last stats */
3668         ixgbevf_dev_stats_get(dev, NULL);
3669
3670         /* reset HW current stats*/
3671         hw_stats->vfgprc = 0;
3672         hw_stats->vfgorc = 0;
3673         hw_stats->vfgptc = 0;
3674         hw_stats->vfgotc = 0;
3675 }
3676
3677 static int
3678 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3679 {
3680         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3681         u16 eeprom_verh, eeprom_verl;
3682         u32 etrack_id;
3683         int ret;
3684
3685         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3686         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3687
3688         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3689         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3690
3691         ret += 1; /* add the size of '\0' */
3692         if (fw_size < (u32)ret)
3693                 return ret;
3694         else
3695                 return 0;
3696 }
3697
3698 static void
3699 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3700 {
3701         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3702         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3703         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3704
3705         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3706         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3707         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3708                 /*
3709                  * When DCB/VT is off, maximum number of queues changes,
3710                  * except for 82598EB, which remains constant.
3711                  */
3712                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3713                                 hw->mac.type != ixgbe_mac_82598EB)
3714                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3715         }
3716         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3717         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3718         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3719         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3720         dev_info->max_vfs = pci_dev->max_vfs;
3721         if (hw->mac.type == ixgbe_mac_82598EB)
3722                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3723         else
3724                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3725         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3726         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3727         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3728                                      dev_info->rx_queue_offload_capa);
3729         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3730         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3731
3732         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3733                 .rx_thresh = {
3734                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3735                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3736                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3737                 },
3738                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3739                 .rx_drop_en = 0,
3740                 .offloads = 0,
3741         };
3742
3743         dev_info->default_txconf = (struct rte_eth_txconf) {
3744                 .tx_thresh = {
3745                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3746                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3747                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3748                 },
3749                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3750                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3751                 .offloads = 0,
3752         };
3753
3754         dev_info->rx_desc_lim = rx_desc_lim;
3755         dev_info->tx_desc_lim = tx_desc_lim;
3756
3757         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3758         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3759         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3760
3761         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3762         if (hw->mac.type == ixgbe_mac_X540 ||
3763             hw->mac.type == ixgbe_mac_X540_vf ||
3764             hw->mac.type == ixgbe_mac_X550 ||
3765             hw->mac.type == ixgbe_mac_X550_vf) {
3766                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3767         }
3768         if (hw->mac.type == ixgbe_mac_X550) {
3769                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3770                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3771         }
3772
3773         /* Driver-preferred Rx/Tx parameters */
3774         dev_info->default_rxportconf.burst_size = 32;
3775         dev_info->default_txportconf.burst_size = 32;
3776         dev_info->default_rxportconf.nb_queues = 1;
3777         dev_info->default_txportconf.nb_queues = 1;
3778         dev_info->default_rxportconf.ring_size = 256;
3779         dev_info->default_txportconf.ring_size = 256;
3780 }
3781
3782 static const uint32_t *
3783 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3784 {
3785         static const uint32_t ptypes[] = {
3786                 /* For non-vec functions,
3787                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3788                  * for vec functions,
3789                  * refers to _recv_raw_pkts_vec().
3790                  */
3791                 RTE_PTYPE_L2_ETHER,
3792                 RTE_PTYPE_L3_IPV4,
3793                 RTE_PTYPE_L3_IPV4_EXT,
3794                 RTE_PTYPE_L3_IPV6,
3795                 RTE_PTYPE_L3_IPV6_EXT,
3796                 RTE_PTYPE_L4_SCTP,
3797                 RTE_PTYPE_L4_TCP,
3798                 RTE_PTYPE_L4_UDP,
3799                 RTE_PTYPE_TUNNEL_IP,
3800                 RTE_PTYPE_INNER_L3_IPV6,
3801                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3802                 RTE_PTYPE_INNER_L4_TCP,
3803                 RTE_PTYPE_INNER_L4_UDP,
3804                 RTE_PTYPE_UNKNOWN
3805         };
3806
3807         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3808             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3809             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3810             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3811                 return ptypes;
3812
3813 #if defined(RTE_ARCH_X86)
3814         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3815             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3816                 return ptypes;
3817 #endif
3818         return NULL;
3819 }
3820
3821 static void
3822 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3823                      struct rte_eth_dev_info *dev_info)
3824 {
3825         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3826         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3827
3828         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3829         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3830         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3831         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3832         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3833         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3834         dev_info->max_vfs = pci_dev->max_vfs;
3835         if (hw->mac.type == ixgbe_mac_82598EB)
3836                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3837         else
3838                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3839         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3840         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3841                                      dev_info->rx_queue_offload_capa);
3842         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3843         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3844
3845         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3846                 .rx_thresh = {
3847                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3848                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3849                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3850                 },
3851                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3852                 .rx_drop_en = 0,
3853                 .offloads = 0,
3854         };
3855
3856         dev_info->default_txconf = (struct rte_eth_txconf) {
3857                 .tx_thresh = {
3858                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3859                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3860                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3861                 },
3862                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3863                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3864                 .offloads = 0,
3865         };
3866
3867         dev_info->rx_desc_lim = rx_desc_lim;
3868         dev_info->tx_desc_lim = tx_desc_lim;
3869 }
3870
3871 static int
3872 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3873                    int *link_up, int wait_to_complete)
3874 {
3875         /**
3876          * for a quick link status checking, wait_to_compelet == 0,
3877          * skip PF link status checking
3878          */
3879         bool no_pflink_check = wait_to_complete == 0;
3880         struct ixgbe_mbx_info *mbx = &hw->mbx;
3881         struct ixgbe_mac_info *mac = &hw->mac;
3882         uint32_t links_reg, in_msg;
3883         int ret_val = 0;
3884
3885         /* If we were hit with a reset drop the link */
3886         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3887                 mac->get_link_status = true;
3888
3889         if (!mac->get_link_status)
3890                 goto out;
3891
3892         /* if link status is down no point in checking to see if pf is up */
3893         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3894         if (!(links_reg & IXGBE_LINKS_UP))
3895                 goto out;
3896
3897         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3898          * before the link status is correct
3899          */
3900         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3901                 int i;
3902
3903                 for (i = 0; i < 5; i++) {
3904                         rte_delay_us(100);
3905                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3906
3907                         if (!(links_reg & IXGBE_LINKS_UP))
3908                                 goto out;
3909                 }
3910         }
3911
3912         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3913         case IXGBE_LINKS_SPEED_10G_82599:
3914                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3915                 if (hw->mac.type >= ixgbe_mac_X550) {
3916                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3917                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3918                 }
3919                 break;
3920         case IXGBE_LINKS_SPEED_1G_82599:
3921                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3922                 break;
3923         case IXGBE_LINKS_SPEED_100_82599:
3924                 *speed = IXGBE_LINK_SPEED_100_FULL;
3925                 if (hw->mac.type == ixgbe_mac_X550) {
3926                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3927                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3928                 }
3929                 break;
3930         case IXGBE_LINKS_SPEED_10_X550EM_A:
3931                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3932                 /* Since Reserved in older MAC's */
3933                 if (hw->mac.type >= ixgbe_mac_X550)
3934                         *speed = IXGBE_LINK_SPEED_10_FULL;
3935                 break;
3936         default:
3937                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3938         }
3939
3940         if (no_pflink_check) {
3941                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3942                         mac->get_link_status = true;
3943                 else
3944                         mac->get_link_status = false;
3945
3946                 goto out;
3947         }
3948         /* if the read failed it could just be a mailbox collision, best wait
3949          * until we are called again and don't report an error
3950          */
3951         if (mbx->ops.read(hw, &in_msg, 1, 0))
3952                 goto out;
3953
3954         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3955                 /* msg is not CTS and is NACK we must have lost CTS status */
3956                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3957                         ret_val = -1;
3958                 goto out;
3959         }
3960
3961         /* the pf is talking, if we timed out in the past we reinit */
3962         if (!mbx->timeout) {
3963                 ret_val = -1;
3964                 goto out;
3965         }
3966
3967         /* if we passed all the tests above then the link is up and we no
3968          * longer need to check for link
3969          */
3970         mac->get_link_status = false;
3971
3972 out:
3973         *link_up = !mac->get_link_status;
3974         return ret_val;
3975 }
3976
3977 /* return 0 means link status changed, -1 means not changed */
3978 int
3979 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3980                             int wait_to_complete, int vf)
3981 {
3982         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3983         struct rte_eth_link link;
3984         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3985         struct ixgbe_interrupt *intr =
3986                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3987         int link_up;
3988         int diag;
3989         u32 speed = 0;
3990         int wait = 1;
3991         bool autoneg = false;
3992
3993         memset(&link, 0, sizeof(link));
3994         link.link_status = ETH_LINK_DOWN;
3995         link.link_speed = ETH_SPEED_NUM_NONE;
3996         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3997         link.link_autoneg = ETH_LINK_AUTONEG;
3998
3999         hw->mac.get_link_status = true;
4000
4001         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
4002                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4003                 speed = hw->phy.autoneg_advertised;
4004                 if (!speed)
4005                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4006                 ixgbe_setup_link(hw, speed, true);
4007         }
4008
4009         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4010         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4011                 wait = 0;
4012
4013         if (vf)
4014                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4015         else
4016                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4017
4018         if (diag != 0) {
4019                 link.link_speed = ETH_SPEED_NUM_100M;
4020                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4021                 return rte_eth_linkstatus_set(dev, &link);
4022         }
4023
4024         if (link_up == 0) {
4025                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4026                 return rte_eth_linkstatus_set(dev, &link);
4027         }
4028
4029         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4030         link.link_status = ETH_LINK_UP;
4031         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4032
4033         switch (link_speed) {
4034         default:
4035         case IXGBE_LINK_SPEED_UNKNOWN:
4036                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4037                 link.link_speed = ETH_SPEED_NUM_100M;
4038                 break;
4039
4040         case IXGBE_LINK_SPEED_100_FULL:
4041                 link.link_speed = ETH_SPEED_NUM_100M;
4042                 break;
4043
4044         case IXGBE_LINK_SPEED_1GB_FULL:
4045                 link.link_speed = ETH_SPEED_NUM_1G;
4046                 break;
4047
4048         case IXGBE_LINK_SPEED_2_5GB_FULL:
4049                 link.link_speed = ETH_SPEED_NUM_2_5G;
4050                 break;
4051
4052         case IXGBE_LINK_SPEED_5GB_FULL:
4053                 link.link_speed = ETH_SPEED_NUM_5G;
4054                 break;
4055
4056         case IXGBE_LINK_SPEED_10GB_FULL:
4057                 link.link_speed = ETH_SPEED_NUM_10G;
4058                 break;
4059         }
4060
4061         return rte_eth_linkstatus_set(dev, &link);
4062 }
4063
4064 static int
4065 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4066 {
4067         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4068 }
4069
4070 static int
4071 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4072 {
4073         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4074 }
4075
4076 static void
4077 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4078 {
4079         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4080         uint32_t fctrl;
4081
4082         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4083         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4084         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4085 }
4086
4087 static void
4088 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4089 {
4090         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4091         uint32_t fctrl;
4092
4093         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4094         fctrl &= (~IXGBE_FCTRL_UPE);
4095         if (dev->data->all_multicast == 1)
4096                 fctrl |= IXGBE_FCTRL_MPE;
4097         else
4098                 fctrl &= (~IXGBE_FCTRL_MPE);
4099         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4100 }
4101
4102 static void
4103 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4104 {
4105         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4106         uint32_t fctrl;
4107
4108         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4109         fctrl |= IXGBE_FCTRL_MPE;
4110         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4111 }
4112
4113 static void
4114 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4115 {
4116         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4117         uint32_t fctrl;
4118
4119         if (dev->data->promiscuous == 1)
4120                 return; /* must remain in all_multicast mode */
4121
4122         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4123         fctrl &= (~IXGBE_FCTRL_MPE);
4124         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4125 }
4126
4127 /**
4128  * It clears the interrupt causes and enables the interrupt.
4129  * It will be called once only during nic initialized.
4130  *
4131  * @param dev
4132  *  Pointer to struct rte_eth_dev.
4133  * @param on
4134  *  Enable or Disable.
4135  *
4136  * @return
4137  *  - On success, zero.
4138  *  - On failure, a negative value.
4139  */
4140 static int
4141 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4142 {
4143         struct ixgbe_interrupt *intr =
4144                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4145
4146         ixgbe_dev_link_status_print(dev);
4147         if (on)
4148                 intr->mask |= IXGBE_EICR_LSC;
4149         else
4150                 intr->mask &= ~IXGBE_EICR_LSC;
4151
4152         return 0;
4153 }
4154
4155 /**
4156  * It clears the interrupt causes and enables the interrupt.
4157  * It will be called once only during nic initialized.
4158  *
4159  * @param dev
4160  *  Pointer to struct rte_eth_dev.
4161  *
4162  * @return
4163  *  - On success, zero.
4164  *  - On failure, a negative value.
4165  */
4166 static int
4167 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4168 {
4169         struct ixgbe_interrupt *intr =
4170                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4171
4172         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4173
4174         return 0;
4175 }
4176
4177 /**
4178  * It clears the interrupt causes and enables the interrupt.
4179  * It will be called once only during nic initialized.
4180  *
4181  * @param dev
4182  *  Pointer to struct rte_eth_dev.
4183  *
4184  * @return
4185  *  - On success, zero.
4186  *  - On failure, a negative value.
4187  */
4188 static int
4189 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4190 {
4191         struct ixgbe_interrupt *intr =
4192                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4193
4194         intr->mask |= IXGBE_EICR_LINKSEC;
4195
4196         return 0;
4197 }
4198
4199 /*
4200  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4201  *
4202  * @param dev
4203  *  Pointer to struct rte_eth_dev.
4204  *
4205  * @return
4206  *  - On success, zero.
4207  *  - On failure, a negative value.
4208  */
4209 static int
4210 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4211 {
4212         uint32_t eicr;
4213         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4214         struct ixgbe_interrupt *intr =
4215                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4216
4217         /* clear all cause mask */
4218         ixgbe_disable_intr(hw);
4219
4220         /* read-on-clear nic registers here */
4221         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4222         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4223
4224         intr->flags = 0;
4225
4226         /* set flag for async link update */
4227         if (eicr & IXGBE_EICR_LSC)
4228                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4229
4230         if (eicr & IXGBE_EICR_MAILBOX)
4231                 intr->flags |= IXGBE_FLAG_MAILBOX;
4232
4233         if (eicr & IXGBE_EICR_LINKSEC)
4234                 intr->flags |= IXGBE_FLAG_MACSEC;
4235
4236         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4237             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4238             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4239                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4240
4241         return 0;
4242 }
4243
4244 /**
4245  * It gets and then prints the link status.
4246  *
4247  * @param dev
4248  *  Pointer to struct rte_eth_dev.
4249  *
4250  * @return
4251  *  - On success, zero.
4252  *  - On failure, a negative value.
4253  */
4254 static void
4255 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4256 {
4257         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4258         struct rte_eth_link link;
4259
4260         rte_eth_linkstatus_get(dev, &link);
4261
4262         if (link.link_status) {
4263                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4264                                         (int)(dev->data->port_id),
4265                                         (unsigned)link.link_speed,
4266                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4267                                         "full-duplex" : "half-duplex");
4268         } else {
4269                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4270                                 (int)(dev->data->port_id));
4271         }
4272         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4273                                 pci_dev->addr.domain,
4274                                 pci_dev->addr.bus,
4275                                 pci_dev->addr.devid,
4276                                 pci_dev->addr.function);
4277 }
4278
4279 /*
4280  * It executes link_update after knowing an interrupt occurred.
4281  *
4282  * @param dev
4283  *  Pointer to struct rte_eth_dev.
4284  *
4285  * @return
4286  *  - On success, zero.
4287  *  - On failure, a negative value.
4288  */
4289 static int
4290 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4291                            struct rte_intr_handle *intr_handle)
4292 {
4293         struct ixgbe_interrupt *intr =
4294                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4295         int64_t timeout;
4296         struct ixgbe_hw *hw =
4297                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4298
4299         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4300
4301         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4302                 ixgbe_pf_mbx_process(dev);
4303                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4304         }
4305
4306         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4307                 ixgbe_handle_lasi(hw);
4308                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4309         }
4310
4311         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4312                 struct rte_eth_link link;
4313
4314                 /* get the link status before link update, for predicting later */
4315                 rte_eth_linkstatus_get(dev, &link);
4316
4317                 ixgbe_dev_link_update(dev, 0);
4318
4319                 /* likely to up */
4320                 if (!link.link_status)
4321                         /* handle it 1 sec later, wait it being stable */
4322                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4323                 /* likely to down */
4324                 else
4325                         /* handle it 4 sec later, wait it being stable */
4326                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4327
4328                 ixgbe_dev_link_status_print(dev);
4329                 if (rte_eal_alarm_set(timeout * 1000,
4330                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4331                         PMD_DRV_LOG(ERR, "Error setting alarm");
4332                 else {
4333                         /* remember original mask */
4334                         intr->mask_original = intr->mask;
4335                         /* only disable lsc interrupt */
4336                         intr->mask &= ~IXGBE_EIMS_LSC;
4337                 }
4338         }
4339
4340         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4341         ixgbe_enable_intr(dev);
4342         rte_intr_enable(intr_handle);
4343
4344         return 0;
4345 }
4346
4347 /**
4348  * Interrupt handler which shall be registered for alarm callback for delayed
4349  * handling specific interrupt to wait for the stable nic state. As the
4350  * NIC interrupt state is not stable for ixgbe after link is just down,
4351  * it needs to wait 4 seconds to get the stable status.
4352  *
4353  * @param handle
4354  *  Pointer to interrupt handle.
4355  * @param param
4356  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4357  *
4358  * @return
4359  *  void
4360  */
4361 static void
4362 ixgbe_dev_interrupt_delayed_handler(void *param)
4363 {
4364         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4365         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4366         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4367         struct ixgbe_interrupt *intr =
4368                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4369         struct ixgbe_hw *hw =
4370                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4371         uint32_t eicr;
4372
4373         ixgbe_disable_intr(hw);
4374
4375         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4376         if (eicr & IXGBE_EICR_MAILBOX)
4377                 ixgbe_pf_mbx_process(dev);
4378
4379         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4380                 ixgbe_handle_lasi(hw);
4381                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4382         }
4383
4384         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4385                 ixgbe_dev_link_update(dev, 0);
4386                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4387                 ixgbe_dev_link_status_print(dev);
4388                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4389                                               NULL);
4390         }
4391
4392         if (intr->flags & IXGBE_FLAG_MACSEC) {
4393                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4394                                               NULL);
4395                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4396         }
4397
4398         /* restore original mask */
4399         intr->mask = intr->mask_original;
4400         intr->mask_original = 0;
4401
4402         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4403         ixgbe_enable_intr(dev);
4404         rte_intr_enable(intr_handle);
4405 }
4406
4407 /**
4408  * Interrupt handler triggered by NIC  for handling
4409  * specific interrupt.
4410  *
4411  * @param handle
4412  *  Pointer to interrupt handle.
4413  * @param param
4414  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4415  *
4416  * @return
4417  *  void
4418  */
4419 static void
4420 ixgbe_dev_interrupt_handler(void *param)
4421 {
4422         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4423
4424         ixgbe_dev_interrupt_get_status(dev);
4425         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4426 }
4427
4428 static int
4429 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4430 {
4431         struct ixgbe_hw *hw;
4432
4433         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4434         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4435 }
4436
4437 static int
4438 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4439 {
4440         struct ixgbe_hw *hw;
4441
4442         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4443         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4444 }
4445
4446 static int
4447 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4448 {
4449         struct ixgbe_hw *hw;
4450         uint32_t mflcn_reg;
4451         uint32_t fccfg_reg;
4452         int rx_pause;
4453         int tx_pause;
4454
4455         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4456
4457         fc_conf->pause_time = hw->fc.pause_time;
4458         fc_conf->high_water = hw->fc.high_water[0];
4459         fc_conf->low_water = hw->fc.low_water[0];
4460         fc_conf->send_xon = hw->fc.send_xon;
4461         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4462
4463         /*
4464          * Return rx_pause status according to actual setting of
4465          * MFLCN register.
4466          */
4467         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4468         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4469                 rx_pause = 1;
4470         else
4471                 rx_pause = 0;
4472
4473         /*
4474          * Return tx_pause status according to actual setting of
4475          * FCCFG register.
4476          */
4477         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4478         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4479                 tx_pause = 1;
4480         else
4481                 tx_pause = 0;
4482
4483         if (rx_pause && tx_pause)
4484                 fc_conf->mode = RTE_FC_FULL;
4485         else if (rx_pause)
4486                 fc_conf->mode = RTE_FC_RX_PAUSE;
4487         else if (tx_pause)
4488                 fc_conf->mode = RTE_FC_TX_PAUSE;
4489         else
4490                 fc_conf->mode = RTE_FC_NONE;
4491
4492         return 0;
4493 }
4494
4495 static int
4496 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4497 {
4498         struct ixgbe_hw *hw;
4499         int err;
4500         uint32_t rx_buf_size;
4501         uint32_t max_high_water;
4502         uint32_t mflcn;
4503         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4504                 ixgbe_fc_none,
4505                 ixgbe_fc_rx_pause,
4506                 ixgbe_fc_tx_pause,
4507                 ixgbe_fc_full
4508         };
4509
4510         PMD_INIT_FUNC_TRACE();
4511
4512         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4513         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4514         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4515
4516         /*
4517          * At least reserve one Ethernet frame for watermark
4518          * high_water/low_water in kilo bytes for ixgbe
4519          */
4520         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4521         if ((fc_conf->high_water > max_high_water) ||
4522                 (fc_conf->high_water < fc_conf->low_water)) {
4523                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4524                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4525                 return -EINVAL;
4526         }
4527
4528         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4529         hw->fc.pause_time     = fc_conf->pause_time;
4530         hw->fc.high_water[0]  = fc_conf->high_water;
4531         hw->fc.low_water[0]   = fc_conf->low_water;
4532         hw->fc.send_xon       = fc_conf->send_xon;
4533         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4534
4535         err = ixgbe_fc_enable(hw);
4536
4537         /* Not negotiated is not an error case */
4538         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4539
4540                 /* check if we want to forward MAC frames - driver doesn't have native
4541                  * capability to do that, so we'll write the registers ourselves */
4542
4543                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4544
4545                 /* set or clear MFLCN.PMCF bit depending on configuration */
4546                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4547                         mflcn |= IXGBE_MFLCN_PMCF;
4548                 else
4549                         mflcn &= ~IXGBE_MFLCN_PMCF;
4550
4551                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4552                 IXGBE_WRITE_FLUSH(hw);
4553
4554                 return 0;
4555         }
4556
4557         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4558         return -EIO;
4559 }
4560
4561 /**
4562  *  ixgbe_pfc_enable_generic - Enable flow control
4563  *  @hw: pointer to hardware structure
4564  *  @tc_num: traffic class number
4565  *  Enable flow control according to the current settings.
4566  */
4567 static int
4568 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4569 {
4570         int ret_val = 0;
4571         uint32_t mflcn_reg, fccfg_reg;
4572         uint32_t reg;
4573         uint32_t fcrtl, fcrth;
4574         uint8_t i;
4575         uint8_t nb_rx_en;
4576
4577         /* Validate the water mark configuration */
4578         if (!hw->fc.pause_time) {
4579                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4580                 goto out;
4581         }
4582
4583         /* Low water mark of zero causes XOFF floods */
4584         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4585                  /* High/Low water can not be 0 */
4586                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4587                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4588                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4589                         goto out;
4590                 }
4591
4592                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4593                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4594                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4595                         goto out;
4596                 }
4597         }
4598         /* Negotiate the fc mode to use */
4599         ixgbe_fc_autoneg(hw);
4600
4601         /* Disable any previous flow control settings */
4602         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4603         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4604
4605         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4606         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4607
4608         switch (hw->fc.current_mode) {
4609         case ixgbe_fc_none:
4610                 /*
4611                  * If the count of enabled RX Priority Flow control >1,
4612                  * and the TX pause can not be disabled
4613                  */
4614                 nb_rx_en = 0;
4615                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4616                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4617                         if (reg & IXGBE_FCRTH_FCEN)
4618                                 nb_rx_en++;
4619                 }
4620                 if (nb_rx_en > 1)
4621                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4622                 break;
4623         case ixgbe_fc_rx_pause:
4624                 /*
4625                  * Rx Flow control is enabled and Tx Flow control is
4626                  * disabled by software override. Since there really
4627                  * isn't a way to advertise that we are capable of RX
4628                  * Pause ONLY, we will advertise that we support both
4629                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4630                  * disable the adapter's ability to send PAUSE frames.
4631                  */
4632                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4633                 /*
4634                  * If the count of enabled RX Priority Flow control >1,
4635                  * and the TX pause can not be disabled
4636                  */
4637                 nb_rx_en = 0;
4638                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4639                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4640                         if (reg & IXGBE_FCRTH_FCEN)
4641                                 nb_rx_en++;
4642                 }
4643                 if (nb_rx_en > 1)
4644                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4645                 break;
4646         case ixgbe_fc_tx_pause:
4647                 /*
4648                  * Tx Flow control is enabled, and Rx Flow control is
4649                  * disabled by software override.
4650                  */
4651                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4652                 break;
4653         case ixgbe_fc_full:
4654                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4655                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4656                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4657                 break;
4658         default:
4659                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4660                 ret_val = IXGBE_ERR_CONFIG;
4661                 goto out;
4662         }
4663
4664         /* Set 802.3x based flow control settings. */
4665         mflcn_reg |= IXGBE_MFLCN_DPF;
4666         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4667         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4668
4669         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4670         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4671                 hw->fc.high_water[tc_num]) {
4672                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4673                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4674                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4675         } else {
4676                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4677                 /*
4678                  * In order to prevent Tx hangs when the internal Tx
4679                  * switch is enabled we must set the high water mark
4680                  * to the maximum FCRTH value.  This allows the Tx
4681                  * switch to function even under heavy Rx workloads.
4682                  */
4683                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4684         }
4685         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4686
4687         /* Configure pause time (2 TCs per register) */
4688         reg = hw->fc.pause_time * 0x00010001;
4689         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4690                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4691
4692         /* Configure flow control refresh threshold value */
4693         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4694
4695 out:
4696         return ret_val;
4697 }
4698
4699 static int
4700 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4701 {
4702         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4703         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4704
4705         if (hw->mac.type != ixgbe_mac_82598EB) {
4706                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4707         }
4708         return ret_val;
4709 }
4710
4711 static int
4712 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4713 {
4714         int err;
4715         uint32_t rx_buf_size;
4716         uint32_t max_high_water;
4717         uint8_t tc_num;
4718         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4719         struct ixgbe_hw *hw =
4720                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4721         struct ixgbe_dcb_config *dcb_config =
4722                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4723
4724         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4725                 ixgbe_fc_none,
4726                 ixgbe_fc_rx_pause,
4727                 ixgbe_fc_tx_pause,
4728                 ixgbe_fc_full
4729         };
4730
4731         PMD_INIT_FUNC_TRACE();
4732
4733         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4734         tc_num = map[pfc_conf->priority];
4735         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4736         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4737         /*
4738          * At least reserve one Ethernet frame for watermark
4739          * high_water/low_water in kilo bytes for ixgbe
4740          */
4741         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4742         if ((pfc_conf->fc.high_water > max_high_water) ||
4743             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4744                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4745                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4746                 return -EINVAL;
4747         }
4748
4749         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4750         hw->fc.pause_time = pfc_conf->fc.pause_time;
4751         hw->fc.send_xon = pfc_conf->fc.send_xon;
4752         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4753         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4754
4755         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4756
4757         /* Not negotiated is not an error case */
4758         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4759                 return 0;
4760
4761         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4762         return -EIO;
4763 }
4764
4765 static int
4766 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4767                           struct rte_eth_rss_reta_entry64 *reta_conf,
4768                           uint16_t reta_size)
4769 {
4770         uint16_t i, sp_reta_size;
4771         uint8_t j, mask;
4772         uint32_t reta, r;
4773         uint16_t idx, shift;
4774         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4775         uint32_t reta_reg;
4776
4777         PMD_INIT_FUNC_TRACE();
4778
4779         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4780                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4781                         "NIC.");
4782                 return -ENOTSUP;
4783         }
4784
4785         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4786         if (reta_size != sp_reta_size) {
4787                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4788                         "(%d) doesn't match the number hardware can supported "
4789                         "(%d)", reta_size, sp_reta_size);
4790                 return -EINVAL;
4791         }
4792
4793         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4794                 idx = i / RTE_RETA_GROUP_SIZE;
4795                 shift = i % RTE_RETA_GROUP_SIZE;
4796                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4797                                                 IXGBE_4_BIT_MASK);
4798                 if (!mask)
4799                         continue;
4800                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4801                 if (mask == IXGBE_4_BIT_MASK)
4802                         r = 0;
4803                 else
4804                         r = IXGBE_READ_REG(hw, reta_reg);
4805                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4806                         if (mask & (0x1 << j))
4807                                 reta |= reta_conf[idx].reta[shift + j] <<
4808                                                         (CHAR_BIT * j);
4809                         else
4810                                 reta |= r & (IXGBE_8_BIT_MASK <<
4811                                                 (CHAR_BIT * j));
4812                 }
4813                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4814         }
4815
4816         return 0;
4817 }
4818
4819 static int
4820 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4821                          struct rte_eth_rss_reta_entry64 *reta_conf,
4822                          uint16_t reta_size)
4823 {
4824         uint16_t i, sp_reta_size;
4825         uint8_t j, mask;
4826         uint32_t reta;
4827         uint16_t idx, shift;
4828         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4829         uint32_t reta_reg;
4830
4831         PMD_INIT_FUNC_TRACE();
4832         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4833         if (reta_size != sp_reta_size) {
4834                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4835                         "(%d) doesn't match the number hardware can supported "
4836                         "(%d)", reta_size, sp_reta_size);
4837                 return -EINVAL;
4838         }
4839
4840         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4841                 idx = i / RTE_RETA_GROUP_SIZE;
4842                 shift = i % RTE_RETA_GROUP_SIZE;
4843                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4844                                                 IXGBE_4_BIT_MASK);
4845                 if (!mask)
4846                         continue;
4847
4848                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4849                 reta = IXGBE_READ_REG(hw, reta_reg);
4850                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4851                         if (mask & (0x1 << j))
4852                                 reta_conf[idx].reta[shift + j] =
4853                                         ((reta >> (CHAR_BIT * j)) &
4854                                                 IXGBE_8_BIT_MASK);
4855                 }
4856         }
4857
4858         return 0;
4859 }
4860
4861 static int
4862 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4863                                 uint32_t index, uint32_t pool)
4864 {
4865         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4866         uint32_t enable_addr = 1;
4867
4868         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4869                              pool, enable_addr);
4870 }
4871
4872 static void
4873 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4874 {
4875         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4876
4877         ixgbe_clear_rar(hw, index);
4878 }
4879
4880 static int
4881 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4882 {
4883         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4884
4885         ixgbe_remove_rar(dev, 0);
4886         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4887
4888         return 0;
4889 }
4890
4891 static bool
4892 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4893 {
4894         if (strcmp(dev->device->driver->name, drv->driver.name))
4895                 return false;
4896
4897         return true;
4898 }
4899
4900 bool
4901 is_ixgbe_supported(struct rte_eth_dev *dev)
4902 {
4903         return is_device_supported(dev, &rte_ixgbe_pmd);
4904 }
4905
4906 static int
4907 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4908 {
4909         uint32_t hlreg0;
4910         uint32_t maxfrs;
4911         struct ixgbe_hw *hw;
4912         struct rte_eth_dev_info dev_info;
4913         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4914         struct rte_eth_dev_data *dev_data = dev->data;
4915
4916         ixgbe_dev_info_get(dev, &dev_info);
4917
4918         /* check that mtu is within the allowed range */
4919         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4920                 return -EINVAL;
4921
4922         /* If device is started, refuse mtu that requires the support of
4923          * scattered packets when this feature has not been enabled before.
4924          */
4925         if (dev_data->dev_started && !dev_data->scattered_rx &&
4926             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4927              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4928                 PMD_INIT_LOG(ERR, "Stop port first.");
4929                 return -EINVAL;
4930         }
4931
4932         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4933         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4934
4935         /* switch to jumbo mode if needed */
4936         if (frame_size > ETHER_MAX_LEN) {
4937                 dev->data->dev_conf.rxmode.offloads |=
4938                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4939                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4940         } else {
4941                 dev->data->dev_conf.rxmode.offloads &=
4942                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4943                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4944         }
4945         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4946
4947         /* update max frame size */
4948         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4949
4950         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4951         maxfrs &= 0x0000FFFF;
4952         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4953         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4954
4955         return 0;
4956 }
4957
4958 /*
4959  * Virtual Function operations
4960  */
4961 static void
4962 ixgbevf_intr_disable(struct rte_eth_dev *dev)
4963 {
4964         struct ixgbe_interrupt *intr =
4965                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4966         struct ixgbe_hw *hw =
4967                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4968
4969         PMD_INIT_FUNC_TRACE();
4970
4971         /* Clear interrupt mask to stop from interrupts being generated */
4972         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4973
4974         IXGBE_WRITE_FLUSH(hw);
4975
4976         /* Clear mask value. */
4977         intr->mask = 0;
4978 }
4979
4980 static void
4981 ixgbevf_intr_enable(struct rte_eth_dev *dev)
4982 {
4983         struct ixgbe_interrupt *intr =
4984                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4985         struct ixgbe_hw *hw =
4986                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4987
4988         PMD_INIT_FUNC_TRACE();
4989
4990         /* VF enable interrupt autoclean */
4991         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4992         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4993         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4994
4995         IXGBE_WRITE_FLUSH(hw);
4996
4997         /* Save IXGBE_VTEIMS value to mask. */
4998         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
4999 }
5000
5001 static int
5002 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5003 {
5004         struct rte_eth_conf *conf = &dev->data->dev_conf;
5005         struct ixgbe_adapter *adapter =
5006                         (struct ixgbe_adapter *)dev->data->dev_private;
5007
5008         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5009                      dev->data->port_id);
5010
5011         /*
5012          * VF has no ability to enable/disable HW CRC
5013          * Keep the persistent behavior the same as Host PF
5014          */
5015 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5016         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5017                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5018                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5019         }
5020 #else
5021         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5022                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5023                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5024         }
5025 #endif
5026
5027         /*
5028          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5029          * allocation or vector Rx preconditions we will reset it.
5030          */
5031         adapter->rx_bulk_alloc_allowed = true;
5032         adapter->rx_vec_allowed = true;
5033
5034         return 0;
5035 }
5036
5037 static int
5038 ixgbevf_dev_start(struct rte_eth_dev *dev)
5039 {
5040         struct ixgbe_hw *hw =
5041                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5042         uint32_t intr_vector = 0;
5043         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5044         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5045
5046         int err, mask = 0;
5047
5048         PMD_INIT_FUNC_TRACE();
5049
5050         err = hw->mac.ops.reset_hw(hw);
5051         if (err) {
5052                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5053                 return err;
5054         }
5055         hw->mac.get_link_status = true;
5056
5057         /* negotiate mailbox API version to use with the PF. */
5058         ixgbevf_negotiate_api(hw);
5059
5060         ixgbevf_dev_tx_init(dev);
5061
5062         /* This can fail when allocating mbufs for descriptor rings */
5063         err = ixgbevf_dev_rx_init(dev);
5064         if (err) {
5065                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5066                 ixgbe_dev_clear_queues(dev);
5067                 return err;
5068         }
5069
5070         /* Set vfta */
5071         ixgbevf_set_vfta_all(dev, 1);
5072
5073         /* Set HW strip */
5074         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5075                 ETH_VLAN_EXTEND_MASK;
5076         err = ixgbevf_vlan_offload_config(dev, mask);
5077         if (err) {
5078                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5079                 ixgbe_dev_clear_queues(dev);
5080                 return err;
5081         }
5082
5083         ixgbevf_dev_rxtx_start(dev);
5084
5085         ixgbevf_dev_link_update(dev, 0);
5086
5087         /* check and configure queue intr-vector mapping */
5088         if (rte_intr_cap_multiple(intr_handle) &&
5089             dev->data->dev_conf.intr_conf.rxq) {
5090                 /* According to datasheet, only vector 0/1/2 can be used,
5091                  * now only one vector is used for Rx queue
5092                  */
5093                 intr_vector = 1;
5094                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5095                         return -1;
5096         }
5097
5098         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5099                 intr_handle->intr_vec =
5100                         rte_zmalloc("intr_vec",
5101                                     dev->data->nb_rx_queues * sizeof(int), 0);
5102                 if (intr_handle->intr_vec == NULL) {
5103                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5104                                      " intr_vec", dev->data->nb_rx_queues);
5105                         return -ENOMEM;
5106                 }
5107         }
5108         ixgbevf_configure_msix(dev);
5109
5110         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5111          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5112          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5113          * is not cleared, it will fail when following rte_intr_enable( ) tries
5114          * to map Rx queue interrupt to other VFIO vectors.
5115          * So clear uio/vfio intr/evevnfd first to avoid failure.
5116          */
5117         rte_intr_disable(intr_handle);
5118
5119         rte_intr_enable(intr_handle);
5120
5121         /* Re-enable interrupt for VF */
5122         ixgbevf_intr_enable(dev);
5123
5124         return 0;
5125 }
5126
5127 static void
5128 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5129 {
5130         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5131         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5132         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5133
5134         PMD_INIT_FUNC_TRACE();
5135
5136         ixgbevf_intr_disable(dev);
5137
5138         hw->adapter_stopped = 1;
5139         ixgbe_stop_adapter(hw);
5140
5141         /*
5142           * Clear what we set, but we still keep shadow_vfta to
5143           * restore after device starts
5144           */
5145         ixgbevf_set_vfta_all(dev, 0);
5146
5147         /* Clear stored conf */
5148         dev->data->scattered_rx = 0;
5149
5150         ixgbe_dev_clear_queues(dev);
5151
5152         /* Clean datapath event and queue/vec mapping */
5153         rte_intr_efd_disable(intr_handle);
5154         if (intr_handle->intr_vec != NULL) {
5155                 rte_free(intr_handle->intr_vec);
5156                 intr_handle->intr_vec = NULL;
5157         }
5158 }
5159
5160 static void
5161 ixgbevf_dev_close(struct rte_eth_dev *dev)
5162 {
5163         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5164
5165         PMD_INIT_FUNC_TRACE();
5166
5167         ixgbe_reset_hw(hw);
5168
5169         ixgbevf_dev_stop(dev);
5170
5171         ixgbe_dev_free_queues(dev);
5172
5173         /**
5174          * Remove the VF MAC address ro ensure
5175          * that the VF traffic goes to the PF
5176          * after stop, close and detach of the VF
5177          **/
5178         ixgbevf_remove_mac_addr(dev, 0);
5179 }
5180
5181 /*
5182  * Reset VF device
5183  */
5184 static int
5185 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5186 {
5187         int ret;
5188
5189         ret = eth_ixgbevf_dev_uninit(dev);
5190         if (ret)
5191                 return ret;
5192
5193         ret = eth_ixgbevf_dev_init(dev);
5194
5195         return ret;
5196 }
5197
5198 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5199 {
5200         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5201         struct ixgbe_vfta *shadow_vfta =
5202                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5203         int i = 0, j = 0, vfta = 0, mask = 1;
5204
5205         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5206                 vfta = shadow_vfta->vfta[i];
5207                 if (vfta) {
5208                         mask = 1;
5209                         for (j = 0; j < 32; j++) {
5210                                 if (vfta & mask)
5211                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5212                                                        on, false);
5213                                 mask <<= 1;
5214                         }
5215                 }
5216         }
5217
5218 }
5219
5220 static int
5221 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5222 {
5223         struct ixgbe_hw *hw =
5224                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5225         struct ixgbe_vfta *shadow_vfta =
5226                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5227         uint32_t vid_idx = 0;
5228         uint32_t vid_bit = 0;
5229         int ret = 0;
5230
5231         PMD_INIT_FUNC_TRACE();
5232
5233         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5234         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5235         if (ret) {
5236                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5237                 return ret;
5238         }
5239         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5240         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5241
5242         /* Save what we set and retore it after device reset */
5243         if (on)
5244                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5245         else
5246                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5247
5248         return 0;
5249 }
5250
5251 static void
5252 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5253 {
5254         struct ixgbe_hw *hw =
5255                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5256         uint32_t ctrl;
5257
5258         PMD_INIT_FUNC_TRACE();
5259
5260         if (queue >= hw->mac.max_rx_queues)
5261                 return;
5262
5263         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5264         if (on)
5265                 ctrl |= IXGBE_RXDCTL_VME;
5266         else
5267                 ctrl &= ~IXGBE_RXDCTL_VME;
5268         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5269
5270         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5271 }
5272
5273 static int
5274 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5275 {
5276         struct ixgbe_rx_queue *rxq;
5277         uint16_t i;
5278         int on = 0;
5279
5280         /* VF function only support hw strip feature, others are not support */
5281         if (mask & ETH_VLAN_STRIP_MASK) {
5282                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5283                         rxq = dev->data->rx_queues[i];
5284                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5285                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5286                 }
5287         }
5288
5289         return 0;
5290 }
5291
5292 static int
5293 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5294 {
5295         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5296
5297         ixgbevf_vlan_offload_config(dev, mask);
5298
5299         return 0;
5300 }
5301
5302 int
5303 ixgbe_vt_check(struct ixgbe_hw *hw)
5304 {
5305         uint32_t reg_val;
5306
5307         /* if Virtualization Technology is enabled */
5308         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5309         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5310                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5311                 return -1;
5312         }
5313
5314         return 0;
5315 }
5316
5317 static uint32_t
5318 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5319 {
5320         uint32_t vector = 0;
5321
5322         switch (hw->mac.mc_filter_type) {
5323         case 0:   /* use bits [47:36] of the address */
5324                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5325                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5326                 break;
5327         case 1:   /* use bits [46:35] of the address */
5328                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5329                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5330                 break;
5331         case 2:   /* use bits [45:34] of the address */
5332                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5333                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5334                 break;
5335         case 3:   /* use bits [43:32] of the address */
5336                 vector = ((uc_addr->addr_bytes[4]) |
5337                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5338                 break;
5339         default:  /* Invalid mc_filter_type */
5340                 break;
5341         }
5342
5343         /* vector can only be 12-bits or boundary will be exceeded */
5344         vector &= 0xFFF;
5345         return vector;
5346 }
5347
5348 static int
5349 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5350                         uint8_t on)
5351 {
5352         uint32_t vector;
5353         uint32_t uta_idx;
5354         uint32_t reg_val;
5355         uint32_t uta_shift;
5356         uint32_t rc;
5357         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5358         const uint32_t ixgbe_uta_bit_shift = 5;
5359         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5360         const uint32_t bit1 = 0x1;
5361
5362         struct ixgbe_hw *hw =
5363                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5364         struct ixgbe_uta_info *uta_info =
5365                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5366
5367         /* The UTA table only exists on 82599 hardware and newer */
5368         if (hw->mac.type < ixgbe_mac_82599EB)
5369                 return -ENOTSUP;
5370
5371         vector = ixgbe_uta_vector(hw, mac_addr);
5372         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5373         uta_shift = vector & ixgbe_uta_bit_mask;
5374
5375         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5376         if (rc == on)
5377                 return 0;
5378
5379         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5380         if (on) {
5381                 uta_info->uta_in_use++;
5382                 reg_val |= (bit1 << uta_shift);
5383                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5384         } else {
5385                 uta_info->uta_in_use--;
5386                 reg_val &= ~(bit1 << uta_shift);
5387                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5388         }
5389
5390         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5391
5392         if (uta_info->uta_in_use > 0)
5393                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5394                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5395         else
5396                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5397
5398         return 0;
5399 }
5400
5401 static int
5402 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5403 {
5404         int i;
5405         struct ixgbe_hw *hw =
5406                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5407         struct ixgbe_uta_info *uta_info =
5408                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5409
5410         /* The UTA table only exists on 82599 hardware and newer */
5411         if (hw->mac.type < ixgbe_mac_82599EB)
5412                 return -ENOTSUP;
5413
5414         if (on) {
5415                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5416                         uta_info->uta_shadow[i] = ~0;
5417                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5418                 }
5419         } else {
5420                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5421                         uta_info->uta_shadow[i] = 0;
5422                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5423                 }
5424         }
5425         return 0;
5426
5427 }
5428
5429 uint32_t
5430 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5431 {
5432         uint32_t new_val = orig_val;
5433
5434         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5435                 new_val |= IXGBE_VMOLR_AUPE;
5436         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5437                 new_val |= IXGBE_VMOLR_ROMPE;
5438         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5439                 new_val |= IXGBE_VMOLR_ROPE;
5440         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5441                 new_val |= IXGBE_VMOLR_BAM;
5442         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5443                 new_val |= IXGBE_VMOLR_MPE;
5444
5445         return new_val;
5446 }
5447
5448 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5449 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5450 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5451 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5452 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5453         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5454         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5455
5456 static int
5457 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5458                       struct rte_eth_mirror_conf *mirror_conf,
5459                       uint8_t rule_id, uint8_t on)
5460 {
5461         uint32_t mr_ctl, vlvf;
5462         uint32_t mp_lsb = 0;
5463         uint32_t mv_msb = 0;
5464         uint32_t mv_lsb = 0;
5465         uint32_t mp_msb = 0;
5466         uint8_t i = 0;
5467         int reg_index = 0;
5468         uint64_t vlan_mask = 0;
5469
5470         const uint8_t pool_mask_offset = 32;
5471         const uint8_t vlan_mask_offset = 32;
5472         const uint8_t dst_pool_offset = 8;
5473         const uint8_t rule_mr_offset  = 4;
5474         const uint8_t mirror_rule_mask = 0x0F;
5475
5476         struct ixgbe_mirror_info *mr_info =
5477                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5478         struct ixgbe_hw *hw =
5479                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5480         uint8_t mirror_type = 0;
5481
5482         if (ixgbe_vt_check(hw) < 0)
5483                 return -ENOTSUP;
5484
5485         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5486                 return -EINVAL;
5487
5488         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5489                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5490                             mirror_conf->rule_type);
5491                 return -EINVAL;
5492         }
5493
5494         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5495                 mirror_type |= IXGBE_MRCTL_VLME;
5496                 /* Check if vlan id is valid and find conresponding VLAN ID
5497                  * index in VLVF
5498                  */
5499                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5500                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5501                                 /* search vlan id related pool vlan filter
5502                                  * index
5503                                  */
5504                                 reg_index = ixgbe_find_vlvf_slot(
5505                                                 hw,
5506                                                 mirror_conf->vlan.vlan_id[i],
5507                                                 false);
5508                                 if (reg_index < 0)
5509                                         return -EINVAL;
5510                                 vlvf = IXGBE_READ_REG(hw,
5511                                                       IXGBE_VLVF(reg_index));
5512                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5513                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5514                                       mirror_conf->vlan.vlan_id[i]))
5515                                         vlan_mask |= (1ULL << reg_index);
5516                                 else
5517                                         return -EINVAL;
5518                         }
5519                 }
5520
5521                 if (on) {
5522                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5523                         mv_msb = vlan_mask >> vlan_mask_offset;
5524
5525                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5526                                                 mirror_conf->vlan.vlan_mask;
5527                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5528                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5529                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5530                                                 mirror_conf->vlan.vlan_id[i];
5531                         }
5532                 } else {
5533                         mv_lsb = 0;
5534                         mv_msb = 0;
5535                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5536                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5537                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5538                 }
5539         }
5540
5541         /**
5542          * if enable pool mirror, write related pool mask register,if disable
5543          * pool mirror, clear PFMRVM register
5544          */
5545         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5546                 mirror_type |= IXGBE_MRCTL_VPME;
5547                 if (on) {
5548                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5549                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5550                         mr_info->mr_conf[rule_id].pool_mask =
5551                                         mirror_conf->pool_mask;
5552
5553                 } else {
5554                         mp_lsb = 0;
5555                         mp_msb = 0;
5556                         mr_info->mr_conf[rule_id].pool_mask = 0;
5557                 }
5558         }
5559         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5560                 mirror_type |= IXGBE_MRCTL_UPME;
5561         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5562                 mirror_type |= IXGBE_MRCTL_DPME;
5563
5564         /* read  mirror control register and recalculate it */
5565         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5566
5567         if (on) {
5568                 mr_ctl |= mirror_type;
5569                 mr_ctl &= mirror_rule_mask;
5570                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5571         } else {
5572                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5573         }
5574
5575         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5576         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5577
5578         /* write mirrror control  register */
5579         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5580
5581         /* write pool mirrror control  register */
5582         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5583                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5584                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5585                                 mp_msb);
5586         }
5587         /* write VLAN mirrror control  register */
5588         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5589                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5590                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5591                                 mv_msb);
5592         }
5593
5594         return 0;
5595 }
5596
5597 static int
5598 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5599 {
5600         int mr_ctl = 0;
5601         uint32_t lsb_val = 0;
5602         uint32_t msb_val = 0;
5603         const uint8_t rule_mr_offset = 4;
5604
5605         struct ixgbe_hw *hw =
5606                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5607         struct ixgbe_mirror_info *mr_info =
5608                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5609
5610         if (ixgbe_vt_check(hw) < 0)
5611                 return -ENOTSUP;
5612
5613         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5614                 return -EINVAL;
5615
5616         memset(&mr_info->mr_conf[rule_id], 0,
5617                sizeof(struct rte_eth_mirror_conf));
5618
5619         /* clear PFVMCTL register */
5620         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5621
5622         /* clear pool mask register */
5623         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5624         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5625
5626         /* clear vlan mask register */
5627         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5628         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5629
5630         return 0;
5631 }
5632
5633 static int
5634 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5635 {
5636         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5637         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5638         struct ixgbe_interrupt *intr =
5639                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5640         struct ixgbe_hw *hw =
5641                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5642         uint32_t vec = IXGBE_MISC_VEC_ID;
5643
5644         if (rte_intr_allow_others(intr_handle))
5645                 vec = IXGBE_RX_VEC_START;
5646         intr->mask |= (1 << vec);
5647         RTE_SET_USED(queue_id);
5648         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5649
5650         rte_intr_enable(intr_handle);
5651
5652         return 0;
5653 }
5654
5655 static int
5656 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5657 {
5658         struct ixgbe_interrupt *intr =
5659                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5660         struct ixgbe_hw *hw =
5661                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5662         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5663         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5664         uint32_t vec = IXGBE_MISC_VEC_ID;
5665
5666         if (rte_intr_allow_others(intr_handle))
5667                 vec = IXGBE_RX_VEC_START;
5668         intr->mask &= ~(1 << vec);
5669         RTE_SET_USED(queue_id);
5670         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5671
5672         return 0;
5673 }
5674
5675 static int
5676 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5677 {
5678         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5679         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5680         uint32_t mask;
5681         struct ixgbe_hw *hw =
5682                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5683         struct ixgbe_interrupt *intr =
5684                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5685
5686         if (queue_id < 16) {
5687                 ixgbe_disable_intr(hw);
5688                 intr->mask |= (1 << queue_id);
5689                 ixgbe_enable_intr(dev);
5690         } else if (queue_id < 32) {
5691                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5692                 mask &= (1 << queue_id);
5693                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5694         } else if (queue_id < 64) {
5695                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5696                 mask &= (1 << (queue_id - 32));
5697                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5698         }
5699         rte_intr_enable(intr_handle);
5700
5701         return 0;
5702 }
5703
5704 static int
5705 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5706 {
5707         uint32_t mask;
5708         struct ixgbe_hw *hw =
5709                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5710         struct ixgbe_interrupt *intr =
5711                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5712
5713         if (queue_id < 16) {
5714                 ixgbe_disable_intr(hw);
5715                 intr->mask &= ~(1 << queue_id);
5716                 ixgbe_enable_intr(dev);
5717         } else if (queue_id < 32) {
5718                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5719                 mask &= ~(1 << queue_id);
5720                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5721         } else if (queue_id < 64) {
5722                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5723                 mask &= ~(1 << (queue_id - 32));
5724                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5725         }
5726
5727         return 0;
5728 }
5729
5730 static void
5731 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5732                      uint8_t queue, uint8_t msix_vector)
5733 {
5734         uint32_t tmp, idx;
5735
5736         if (direction == -1) {
5737                 /* other causes */
5738                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5739                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5740                 tmp &= ~0xFF;
5741                 tmp |= msix_vector;
5742                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5743         } else {
5744                 /* rx or tx cause */
5745                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5746                 idx = ((16 * (queue & 1)) + (8 * direction));
5747                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5748                 tmp &= ~(0xFF << idx);
5749                 tmp |= (msix_vector << idx);
5750                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5751         }
5752 }
5753
5754 /**
5755  * set the IVAR registers, mapping interrupt causes to vectors
5756  * @param hw
5757  *  pointer to ixgbe_hw struct
5758  * @direction
5759  *  0 for Rx, 1 for Tx, -1 for other causes
5760  * @queue
5761  *  queue to map the corresponding interrupt to
5762  * @msix_vector
5763  *  the vector to map to the corresponding queue
5764  */
5765 static void
5766 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5767                    uint8_t queue, uint8_t msix_vector)
5768 {
5769         uint32_t tmp, idx;
5770
5771         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5772         if (hw->mac.type == ixgbe_mac_82598EB) {
5773                 if (direction == -1)
5774                         direction = 0;
5775                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5776                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5777                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5778                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5779                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5780         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5781                         (hw->mac.type == ixgbe_mac_X540) ||
5782                         (hw->mac.type == ixgbe_mac_X550)) {
5783                 if (direction == -1) {
5784                         /* other causes */
5785                         idx = ((queue & 1) * 8);
5786                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5787                         tmp &= ~(0xFF << idx);
5788                         tmp |= (msix_vector << idx);
5789                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5790                 } else {
5791                         /* rx or tx causes */
5792                         idx = ((16 * (queue & 1)) + (8 * direction));
5793                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5794                         tmp &= ~(0xFF << idx);
5795                         tmp |= (msix_vector << idx);
5796                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5797                 }
5798         }
5799 }
5800
5801 static void
5802 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5803 {
5804         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5805         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5806         struct ixgbe_hw *hw =
5807                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5808         uint32_t q_idx;
5809         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5810         uint32_t base = IXGBE_MISC_VEC_ID;
5811
5812         /* Configure VF other cause ivar */
5813         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5814
5815         /* won't configure msix register if no mapping is done
5816          * between intr vector and event fd.
5817          */
5818         if (!rte_intr_dp_is_en(intr_handle))
5819                 return;
5820
5821         if (rte_intr_allow_others(intr_handle)) {
5822                 base = IXGBE_RX_VEC_START;
5823                 vector_idx = IXGBE_RX_VEC_START;
5824         }
5825
5826         /* Configure all RX queues of VF */
5827         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5828                 /* Force all queue use vector 0,
5829                  * as IXGBE_VF_MAXMSIVECOTR = 1
5830                  */
5831                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5832                 intr_handle->intr_vec[q_idx] = vector_idx;
5833                 if (vector_idx < base + intr_handle->nb_efd - 1)
5834                         vector_idx++;
5835         }
5836
5837         /* As RX queue setting above show, all queues use the vector 0.
5838          * Set only the ITR value of IXGBE_MISC_VEC_ID.
5839          */
5840         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5841                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5842                         | IXGBE_EITR_CNT_WDIS);
5843 }
5844
5845 /**
5846  * Sets up the hardware to properly generate MSI-X interrupts
5847  * @hw
5848  *  board private structure
5849  */
5850 static void
5851 ixgbe_configure_msix(struct rte_eth_dev *dev)
5852 {
5853         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5854         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5855         struct ixgbe_hw *hw =
5856                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5857         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5858         uint32_t vec = IXGBE_MISC_VEC_ID;
5859         uint32_t mask;
5860         uint32_t gpie;
5861
5862         /* won't configure msix register if no mapping is done
5863          * between intr vector and event fd
5864          * but if misx has been enabled already, need to configure
5865          * auto clean, auto mask and throttling.
5866          */
5867         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5868         if (!rte_intr_dp_is_en(intr_handle) &&
5869             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
5870                 return;
5871
5872         if (rte_intr_allow_others(intr_handle))
5873                 vec = base = IXGBE_RX_VEC_START;
5874
5875         /* setup GPIE for MSI-x mode */
5876         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5877         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5878                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5879         /* auto clearing and auto setting corresponding bits in EIMS
5880          * when MSI-X interrupt is triggered
5881          */
5882         if (hw->mac.type == ixgbe_mac_82598EB) {
5883                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5884         } else {
5885                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5886                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5887         }
5888         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5889
5890         /* Populate the IVAR table and set the ITR values to the
5891          * corresponding register.
5892          */
5893         if (rte_intr_dp_is_en(intr_handle)) {
5894                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5895                         queue_id++) {
5896                         /* by default, 1:1 mapping */
5897                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5898                         intr_handle->intr_vec[queue_id] = vec;
5899                         if (vec < base + intr_handle->nb_efd - 1)
5900                                 vec++;
5901                 }
5902
5903                 switch (hw->mac.type) {
5904                 case ixgbe_mac_82598EB:
5905                         ixgbe_set_ivar_map(hw, -1,
5906                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
5907                                            IXGBE_MISC_VEC_ID);
5908                         break;
5909                 case ixgbe_mac_82599EB:
5910                 case ixgbe_mac_X540:
5911                 case ixgbe_mac_X550:
5912                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5913                         break;
5914                 default:
5915                         break;
5916                 }
5917         }
5918         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5919                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5920                         | IXGBE_EITR_CNT_WDIS);
5921
5922         /* set up to autoclear timer, and the vectors */
5923         mask = IXGBE_EIMS_ENABLE_MASK;
5924         mask &= ~(IXGBE_EIMS_OTHER |
5925                   IXGBE_EIMS_MAILBOX |
5926                   IXGBE_EIMS_LSC);
5927
5928         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5929 }
5930
5931 int
5932 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5933                            uint16_t queue_idx, uint16_t tx_rate)
5934 {
5935         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5936         struct rte_eth_rxmode *rxmode;
5937         uint32_t rf_dec, rf_int;
5938         uint32_t bcnrc_val;
5939         uint16_t link_speed = dev->data->dev_link.link_speed;
5940
5941         if (queue_idx >= hw->mac.max_tx_queues)
5942                 return -EINVAL;
5943
5944         if (tx_rate != 0) {
5945                 /* Calculate the rate factor values to set */
5946                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5947                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5948                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5949
5950                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5951                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5952                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5953                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5954         } else {
5955                 bcnrc_val = 0;
5956         }
5957
5958         rxmode = &dev->data->dev_conf.rxmode;
5959         /*
5960          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5961          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5962          * set as 0x4.
5963          */
5964         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
5965             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
5966                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5967                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5968         else
5969                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5970                         IXGBE_MMW_SIZE_DEFAULT);
5971
5972         /* Set RTTBCNRC of queue X */
5973         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5974         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5975         IXGBE_WRITE_FLUSH(hw);
5976
5977         return 0;
5978 }
5979
5980 static int
5981 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5982                      __attribute__((unused)) uint32_t index,
5983                      __attribute__((unused)) uint32_t pool)
5984 {
5985         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5986         int diag;
5987
5988         /*
5989          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5990          * operation. Trap this case to avoid exhausting the [very limited]
5991          * set of PF resources used to store VF MAC addresses.
5992          */
5993         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5994                 return -1;
5995         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5996         if (diag != 0)
5997                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5998                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5999                             mac_addr->addr_bytes[0],
6000                             mac_addr->addr_bytes[1],
6001                             mac_addr->addr_bytes[2],
6002                             mac_addr->addr_bytes[3],
6003                             mac_addr->addr_bytes[4],
6004                             mac_addr->addr_bytes[5],
6005                             diag);
6006         return diag;
6007 }
6008
6009 static void
6010 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6011 {
6012         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6013         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
6014         struct ether_addr *mac_addr;
6015         uint32_t i;
6016         int diag;
6017
6018         /*
6019          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6020          * not support the deletion of a given MAC address.
6021          * Instead, it imposes to delete all MAC addresses, then to add again
6022          * all MAC addresses with the exception of the one to be deleted.
6023          */
6024         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6025
6026         /*
6027          * Add again all MAC addresses, with the exception of the deleted one
6028          * and of the permanent MAC address.
6029          */
6030         for (i = 0, mac_addr = dev->data->mac_addrs;
6031              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6032                 /* Skip the deleted MAC address */
6033                 if (i == index)
6034                         continue;
6035                 /* Skip NULL MAC addresses */
6036                 if (is_zero_ether_addr(mac_addr))
6037                         continue;
6038                 /* Skip the permanent MAC address */
6039                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
6040                         continue;
6041                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6042                 if (diag != 0)
6043                         PMD_DRV_LOG(ERR,
6044                                     "Adding again MAC address "
6045                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6046                                     "diag=%d",
6047                                     mac_addr->addr_bytes[0],
6048                                     mac_addr->addr_bytes[1],
6049                                     mac_addr->addr_bytes[2],
6050                                     mac_addr->addr_bytes[3],
6051                                     mac_addr->addr_bytes[4],
6052                                     mac_addr->addr_bytes[5],
6053                                     diag);
6054         }
6055 }
6056
6057 static int
6058 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
6059 {
6060         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6061
6062         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6063
6064         return 0;
6065 }
6066
6067 int
6068 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6069                         struct rte_eth_syn_filter *filter,
6070                         bool add)
6071 {
6072         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6073         struct ixgbe_filter_info *filter_info =
6074                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6075         uint32_t syn_info;
6076         uint32_t synqf;
6077
6078         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6079                 return -EINVAL;
6080
6081         syn_info = filter_info->syn_info;
6082
6083         if (add) {
6084                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6085                         return -EINVAL;
6086                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6087                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6088
6089                 if (filter->hig_pri)
6090                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6091                 else
6092                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6093         } else {
6094                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6095                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6096                         return -ENOENT;
6097                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6098         }
6099
6100         filter_info->syn_info = synqf;
6101         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6102         IXGBE_WRITE_FLUSH(hw);
6103         return 0;
6104 }
6105
6106 static int
6107 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6108                         struct rte_eth_syn_filter *filter)
6109 {
6110         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6111         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6112
6113         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6114                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6115                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6116                 return 0;
6117         }
6118         return -ENOENT;
6119 }
6120
6121 static int
6122 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6123                         enum rte_filter_op filter_op,
6124                         void *arg)
6125 {
6126         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6127         int ret;
6128
6129         MAC_TYPE_FILTER_SUP(hw->mac.type);
6130
6131         if (filter_op == RTE_ETH_FILTER_NOP)
6132                 return 0;
6133
6134         if (arg == NULL) {
6135                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6136                             filter_op);
6137                 return -EINVAL;
6138         }
6139
6140         switch (filter_op) {
6141         case RTE_ETH_FILTER_ADD:
6142                 ret = ixgbe_syn_filter_set(dev,
6143                                 (struct rte_eth_syn_filter *)arg,
6144                                 TRUE);
6145                 break;
6146         case RTE_ETH_FILTER_DELETE:
6147                 ret = ixgbe_syn_filter_set(dev,
6148                                 (struct rte_eth_syn_filter *)arg,
6149                                 FALSE);
6150                 break;
6151         case RTE_ETH_FILTER_GET:
6152                 ret = ixgbe_syn_filter_get(dev,
6153                                 (struct rte_eth_syn_filter *)arg);
6154                 break;
6155         default:
6156                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6157                 ret = -EINVAL;
6158                 break;
6159         }
6160
6161         return ret;
6162 }
6163
6164
6165 static inline enum ixgbe_5tuple_protocol
6166 convert_protocol_type(uint8_t protocol_value)
6167 {
6168         if (protocol_value == IPPROTO_TCP)
6169                 return IXGBE_FILTER_PROTOCOL_TCP;
6170         else if (protocol_value == IPPROTO_UDP)
6171                 return IXGBE_FILTER_PROTOCOL_UDP;
6172         else if (protocol_value == IPPROTO_SCTP)
6173                 return IXGBE_FILTER_PROTOCOL_SCTP;
6174         else
6175                 return IXGBE_FILTER_PROTOCOL_NONE;
6176 }
6177
6178 /* inject a 5-tuple filter to HW */
6179 static inline void
6180 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6181                            struct ixgbe_5tuple_filter *filter)
6182 {
6183         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6184         int i;
6185         uint32_t ftqf, sdpqf;
6186         uint32_t l34timir = 0;
6187         uint8_t mask = 0xff;
6188
6189         i = filter->index;
6190
6191         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6192                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6193         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6194
6195         ftqf = (uint32_t)(filter->filter_info.proto &
6196                 IXGBE_FTQF_PROTOCOL_MASK);
6197         ftqf |= (uint32_t)((filter->filter_info.priority &
6198                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6199         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6200                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6201         if (filter->filter_info.dst_ip_mask == 0)
6202                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6203         if (filter->filter_info.src_port_mask == 0)
6204                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6205         if (filter->filter_info.dst_port_mask == 0)
6206                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6207         if (filter->filter_info.proto_mask == 0)
6208                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6209         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6210         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6211         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6212
6213         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6214         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6215         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6216         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6217
6218         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6219         l34timir |= (uint32_t)(filter->queue <<
6220                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6221         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6222 }
6223
6224 /*
6225  * add a 5tuple filter
6226  *
6227  * @param
6228  * dev: Pointer to struct rte_eth_dev.
6229  * index: the index the filter allocates.
6230  * filter: ponter to the filter that will be added.
6231  * rx_queue: the queue id the filter assigned to.
6232  *
6233  * @return
6234  *    - On success, zero.
6235  *    - On failure, a negative value.
6236  */
6237 static int
6238 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6239                         struct ixgbe_5tuple_filter *filter)
6240 {
6241         struct ixgbe_filter_info *filter_info =
6242                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6243         int i, idx, shift;
6244
6245         /*
6246          * look for an unused 5tuple filter index,
6247          * and insert the filter to list.
6248          */
6249         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6250                 idx = i / (sizeof(uint32_t) * NBBY);
6251                 shift = i % (sizeof(uint32_t) * NBBY);
6252                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6253                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6254                         filter->index = i;
6255                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6256                                           filter,
6257                                           entries);
6258                         break;
6259                 }
6260         }
6261         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6262                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6263                 return -ENOSYS;
6264         }
6265
6266         ixgbe_inject_5tuple_filter(dev, filter);
6267
6268         return 0;
6269 }
6270
6271 /*
6272  * remove a 5tuple filter
6273  *
6274  * @param
6275  * dev: Pointer to struct rte_eth_dev.
6276  * filter: the pointer of the filter will be removed.
6277  */
6278 static void
6279 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6280                         struct ixgbe_5tuple_filter *filter)
6281 {
6282         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6283         struct ixgbe_filter_info *filter_info =
6284                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6285         uint16_t index = filter->index;
6286
6287         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6288                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6289         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6290         rte_free(filter);
6291
6292         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6293         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6294         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6295         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6296         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6297 }
6298
6299 static int
6300 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6301 {
6302         struct ixgbe_hw *hw;
6303         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6304         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6305
6306         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6307
6308         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6309                 return -EINVAL;
6310
6311         /* refuse mtu that requires the support of scattered packets when this
6312          * feature has not been enabled before.
6313          */
6314         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6315             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6316              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6317                 return -EINVAL;
6318
6319         /*
6320          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6321          * request of the version 2.0 of the mailbox API.
6322          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6323          * of the mailbox API.
6324          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6325          * prior to 3.11.33 which contains the following change:
6326          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6327          */
6328         ixgbevf_rlpml_set_vf(hw, max_frame);
6329
6330         /* update max frame size */
6331         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6332         return 0;
6333 }
6334
6335 static inline struct ixgbe_5tuple_filter *
6336 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6337                         struct ixgbe_5tuple_filter_info *key)
6338 {
6339         struct ixgbe_5tuple_filter *it;
6340
6341         TAILQ_FOREACH(it, filter_list, entries) {
6342                 if (memcmp(key, &it->filter_info,
6343                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6344                         return it;
6345                 }
6346         }
6347         return NULL;
6348 }
6349
6350 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6351 static inline int
6352 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6353                         struct ixgbe_5tuple_filter_info *filter_info)
6354 {
6355         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6356                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6357                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6358                 return -EINVAL;
6359
6360         switch (filter->dst_ip_mask) {
6361         case UINT32_MAX:
6362                 filter_info->dst_ip_mask = 0;
6363                 filter_info->dst_ip = filter->dst_ip;
6364                 break;
6365         case 0:
6366                 filter_info->dst_ip_mask = 1;
6367                 break;
6368         default:
6369                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6370                 return -EINVAL;
6371         }
6372
6373         switch (filter->src_ip_mask) {
6374         case UINT32_MAX:
6375                 filter_info->src_ip_mask = 0;
6376                 filter_info->src_ip = filter->src_ip;
6377                 break;
6378         case 0:
6379                 filter_info->src_ip_mask = 1;
6380                 break;
6381         default:
6382                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6383                 return -EINVAL;
6384         }
6385
6386         switch (filter->dst_port_mask) {
6387         case UINT16_MAX:
6388                 filter_info->dst_port_mask = 0;
6389                 filter_info->dst_port = filter->dst_port;
6390                 break;
6391         case 0:
6392                 filter_info->dst_port_mask = 1;
6393                 break;
6394         default:
6395                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6396                 return -EINVAL;
6397         }
6398
6399         switch (filter->src_port_mask) {
6400         case UINT16_MAX:
6401                 filter_info->src_port_mask = 0;
6402                 filter_info->src_port = filter->src_port;
6403                 break;
6404         case 0:
6405                 filter_info->src_port_mask = 1;
6406                 break;
6407         default:
6408                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6409                 return -EINVAL;
6410         }
6411
6412         switch (filter->proto_mask) {
6413         case UINT8_MAX:
6414                 filter_info->proto_mask = 0;
6415                 filter_info->proto =
6416                         convert_protocol_type(filter->proto);
6417                 break;
6418         case 0:
6419                 filter_info->proto_mask = 1;
6420                 break;
6421         default:
6422                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6423                 return -EINVAL;
6424         }
6425
6426         filter_info->priority = (uint8_t)filter->priority;
6427         return 0;
6428 }
6429
6430 /*
6431  * add or delete a ntuple filter
6432  *
6433  * @param
6434  * dev: Pointer to struct rte_eth_dev.
6435  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6436  * add: if true, add filter, if false, remove filter
6437  *
6438  * @return
6439  *    - On success, zero.
6440  *    - On failure, a negative value.
6441  */
6442 int
6443 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6444                         struct rte_eth_ntuple_filter *ntuple_filter,
6445                         bool add)
6446 {
6447         struct ixgbe_filter_info *filter_info =
6448                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6449         struct ixgbe_5tuple_filter_info filter_5tuple;
6450         struct ixgbe_5tuple_filter *filter;
6451         int ret;
6452
6453         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6454                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6455                 return -EINVAL;
6456         }
6457
6458         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6459         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6460         if (ret < 0)
6461                 return ret;
6462
6463         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6464                                          &filter_5tuple);
6465         if (filter != NULL && add) {
6466                 PMD_DRV_LOG(ERR, "filter exists.");
6467                 return -EEXIST;
6468         }
6469         if (filter == NULL && !add) {
6470                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6471                 return -ENOENT;
6472         }
6473
6474         if (add) {
6475                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6476                                 sizeof(struct ixgbe_5tuple_filter), 0);
6477                 if (filter == NULL)
6478                         return -ENOMEM;
6479                 rte_memcpy(&filter->filter_info,
6480                                  &filter_5tuple,
6481                                  sizeof(struct ixgbe_5tuple_filter_info));
6482                 filter->queue = ntuple_filter->queue;
6483                 ret = ixgbe_add_5tuple_filter(dev, filter);
6484                 if (ret < 0) {
6485                         rte_free(filter);
6486                         return ret;
6487                 }
6488         } else
6489                 ixgbe_remove_5tuple_filter(dev, filter);
6490
6491         return 0;
6492 }
6493
6494 /*
6495  * get a ntuple filter
6496  *
6497  * @param
6498  * dev: Pointer to struct rte_eth_dev.
6499  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6500  *
6501  * @return
6502  *    - On success, zero.
6503  *    - On failure, a negative value.
6504  */
6505 static int
6506 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6507                         struct rte_eth_ntuple_filter *ntuple_filter)
6508 {
6509         struct ixgbe_filter_info *filter_info =
6510                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6511         struct ixgbe_5tuple_filter_info filter_5tuple;
6512         struct ixgbe_5tuple_filter *filter;
6513         int ret;
6514
6515         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6516                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6517                 return -EINVAL;
6518         }
6519
6520         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6521         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6522         if (ret < 0)
6523                 return ret;
6524
6525         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6526                                          &filter_5tuple);
6527         if (filter == NULL) {
6528                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6529                 return -ENOENT;
6530         }
6531         ntuple_filter->queue = filter->queue;
6532         return 0;
6533 }
6534
6535 /*
6536  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6537  * @dev: pointer to rte_eth_dev structure
6538  * @filter_op:operation will be taken.
6539  * @arg: a pointer to specific structure corresponding to the filter_op
6540  *
6541  * @return
6542  *    - On success, zero.
6543  *    - On failure, a negative value.
6544  */
6545 static int
6546 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6547                                 enum rte_filter_op filter_op,
6548                                 void *arg)
6549 {
6550         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6551         int ret;
6552
6553         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6554
6555         if (filter_op == RTE_ETH_FILTER_NOP)
6556                 return 0;
6557
6558         if (arg == NULL) {
6559                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6560                             filter_op);
6561                 return -EINVAL;
6562         }
6563
6564         switch (filter_op) {
6565         case RTE_ETH_FILTER_ADD:
6566                 ret = ixgbe_add_del_ntuple_filter(dev,
6567                         (struct rte_eth_ntuple_filter *)arg,
6568                         TRUE);
6569                 break;
6570         case RTE_ETH_FILTER_DELETE:
6571                 ret = ixgbe_add_del_ntuple_filter(dev,
6572                         (struct rte_eth_ntuple_filter *)arg,
6573                         FALSE);
6574                 break;
6575         case RTE_ETH_FILTER_GET:
6576                 ret = ixgbe_get_ntuple_filter(dev,
6577                         (struct rte_eth_ntuple_filter *)arg);
6578                 break;
6579         default:
6580                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6581                 ret = -EINVAL;
6582                 break;
6583         }
6584         return ret;
6585 }
6586
6587 int
6588 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6589                         struct rte_eth_ethertype_filter *filter,
6590                         bool add)
6591 {
6592         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6593         struct ixgbe_filter_info *filter_info =
6594                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6595         uint32_t etqf = 0;
6596         uint32_t etqs = 0;
6597         int ret;
6598         struct ixgbe_ethertype_filter ethertype_filter;
6599
6600         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6601                 return -EINVAL;
6602
6603         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6604                 filter->ether_type == ETHER_TYPE_IPv6) {
6605                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6606                         " ethertype filter.", filter->ether_type);
6607                 return -EINVAL;
6608         }
6609
6610         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6611                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6612                 return -EINVAL;
6613         }
6614         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6615                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6616                 return -EINVAL;
6617         }
6618
6619         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6620         if (ret >= 0 && add) {
6621                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6622                             filter->ether_type);
6623                 return -EEXIST;
6624         }
6625         if (ret < 0 && !add) {
6626                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6627                             filter->ether_type);
6628                 return -ENOENT;
6629         }
6630
6631         if (add) {
6632                 etqf = IXGBE_ETQF_FILTER_EN;
6633                 etqf |= (uint32_t)filter->ether_type;
6634                 etqs |= (uint32_t)((filter->queue <<
6635                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6636                                     IXGBE_ETQS_RX_QUEUE);
6637                 etqs |= IXGBE_ETQS_QUEUE_EN;
6638
6639                 ethertype_filter.ethertype = filter->ether_type;
6640                 ethertype_filter.etqf = etqf;
6641                 ethertype_filter.etqs = etqs;
6642                 ethertype_filter.conf = FALSE;
6643                 ret = ixgbe_ethertype_filter_insert(filter_info,
6644                                                     &ethertype_filter);
6645                 if (ret < 0) {
6646                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6647                         return -ENOSPC;
6648                 }
6649         } else {
6650                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6651                 if (ret < 0)
6652                         return -ENOSYS;
6653         }
6654         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6655         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6656         IXGBE_WRITE_FLUSH(hw);
6657
6658         return 0;
6659 }
6660
6661 static int
6662 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6663                         struct rte_eth_ethertype_filter *filter)
6664 {
6665         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6666         struct ixgbe_filter_info *filter_info =
6667                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6668         uint32_t etqf, etqs;
6669         int ret;
6670
6671         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6672         if (ret < 0) {
6673                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6674                             filter->ether_type);
6675                 return -ENOENT;
6676         }
6677
6678         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6679         if (etqf & IXGBE_ETQF_FILTER_EN) {
6680                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6681                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6682                 filter->flags = 0;
6683                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6684                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6685                 return 0;
6686         }
6687         return -ENOENT;
6688 }
6689
6690 /*
6691  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6692  * @dev: pointer to rte_eth_dev structure
6693  * @filter_op:operation will be taken.
6694  * @arg: a pointer to specific structure corresponding to the filter_op
6695  */
6696 static int
6697 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6698                                 enum rte_filter_op filter_op,
6699                                 void *arg)
6700 {
6701         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6702         int ret;
6703
6704         MAC_TYPE_FILTER_SUP(hw->mac.type);
6705
6706         if (filter_op == RTE_ETH_FILTER_NOP)
6707                 return 0;
6708
6709         if (arg == NULL) {
6710                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6711                             filter_op);
6712                 return -EINVAL;
6713         }
6714
6715         switch (filter_op) {
6716         case RTE_ETH_FILTER_ADD:
6717                 ret = ixgbe_add_del_ethertype_filter(dev,
6718                         (struct rte_eth_ethertype_filter *)arg,
6719                         TRUE);
6720                 break;
6721         case RTE_ETH_FILTER_DELETE:
6722                 ret = ixgbe_add_del_ethertype_filter(dev,
6723                         (struct rte_eth_ethertype_filter *)arg,
6724                         FALSE);
6725                 break;
6726         case RTE_ETH_FILTER_GET:
6727                 ret = ixgbe_get_ethertype_filter(dev,
6728                         (struct rte_eth_ethertype_filter *)arg);
6729                 break;
6730         default:
6731                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6732                 ret = -EINVAL;
6733                 break;
6734         }
6735         return ret;
6736 }
6737
6738 static int
6739 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6740                      enum rte_filter_type filter_type,
6741                      enum rte_filter_op filter_op,
6742                      void *arg)
6743 {
6744         int ret = 0;
6745
6746         switch (filter_type) {
6747         case RTE_ETH_FILTER_NTUPLE:
6748                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6749                 break;
6750         case RTE_ETH_FILTER_ETHERTYPE:
6751                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6752                 break;
6753         case RTE_ETH_FILTER_SYN:
6754                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6755                 break;
6756         case RTE_ETH_FILTER_FDIR:
6757                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6758                 break;
6759         case RTE_ETH_FILTER_L2_TUNNEL:
6760                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6761                 break;
6762         case RTE_ETH_FILTER_GENERIC:
6763                 if (filter_op != RTE_ETH_FILTER_GET)
6764                         return -EINVAL;
6765                 *(const void **)arg = &ixgbe_flow_ops;
6766                 break;
6767         default:
6768                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6769                                                         filter_type);
6770                 ret = -EINVAL;
6771                 break;
6772         }
6773
6774         return ret;
6775 }
6776
6777 static u8 *
6778 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6779                         u8 **mc_addr_ptr, u32 *vmdq)
6780 {
6781         u8 *mc_addr;
6782
6783         *vmdq = 0;
6784         mc_addr = *mc_addr_ptr;
6785         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6786         return mc_addr;
6787 }
6788
6789 static int
6790 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6791                           struct ether_addr *mc_addr_set,
6792                           uint32_t nb_mc_addr)
6793 {
6794         struct ixgbe_hw *hw;
6795         u8 *mc_addr_list;
6796
6797         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6798         mc_addr_list = (u8 *)mc_addr_set;
6799         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6800                                          ixgbe_dev_addr_list_itr, TRUE);
6801 }
6802
6803 static uint64_t
6804 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6805 {
6806         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6807         uint64_t systime_cycles;
6808
6809         switch (hw->mac.type) {
6810         case ixgbe_mac_X550:
6811         case ixgbe_mac_X550EM_x:
6812         case ixgbe_mac_X550EM_a:
6813                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6814                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6815                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6816                                 * NSEC_PER_SEC;
6817                 break;
6818         default:
6819                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6820                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6821                                 << 32;
6822         }
6823
6824         return systime_cycles;
6825 }
6826
6827 static uint64_t
6828 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6829 {
6830         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6831         uint64_t rx_tstamp_cycles;
6832
6833         switch (hw->mac.type) {
6834         case ixgbe_mac_X550:
6835         case ixgbe_mac_X550EM_x:
6836         case ixgbe_mac_X550EM_a:
6837                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6838                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6839                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6840                                 * NSEC_PER_SEC;
6841                 break;
6842         default:
6843                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6844                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6845                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6846                                 << 32;
6847         }
6848
6849         return rx_tstamp_cycles;
6850 }
6851
6852 static uint64_t
6853 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6854 {
6855         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6856         uint64_t tx_tstamp_cycles;
6857
6858         switch (hw->mac.type) {
6859         case ixgbe_mac_X550:
6860         case ixgbe_mac_X550EM_x:
6861         case ixgbe_mac_X550EM_a:
6862                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6863                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6864                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6865                                 * NSEC_PER_SEC;
6866                 break;
6867         default:
6868                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6869                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6870                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6871                                 << 32;
6872         }
6873
6874         return tx_tstamp_cycles;
6875 }
6876
6877 static void
6878 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6879 {
6880         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6881         struct ixgbe_adapter *adapter =
6882                 (struct ixgbe_adapter *)dev->data->dev_private;
6883         struct rte_eth_link link;
6884         uint32_t incval = 0;
6885         uint32_t shift = 0;
6886
6887         /* Get current link speed. */
6888         ixgbe_dev_link_update(dev, 1);
6889         rte_eth_linkstatus_get(dev, &link);
6890
6891         switch (link.link_speed) {
6892         case ETH_SPEED_NUM_100M:
6893                 incval = IXGBE_INCVAL_100;
6894                 shift = IXGBE_INCVAL_SHIFT_100;
6895                 break;
6896         case ETH_SPEED_NUM_1G:
6897                 incval = IXGBE_INCVAL_1GB;
6898                 shift = IXGBE_INCVAL_SHIFT_1GB;
6899                 break;
6900         case ETH_SPEED_NUM_10G:
6901         default:
6902                 incval = IXGBE_INCVAL_10GB;
6903                 shift = IXGBE_INCVAL_SHIFT_10GB;
6904                 break;
6905         }
6906
6907         switch (hw->mac.type) {
6908         case ixgbe_mac_X550:
6909         case ixgbe_mac_X550EM_x:
6910         case ixgbe_mac_X550EM_a:
6911                 /* Independent of link speed. */
6912                 incval = 1;
6913                 /* Cycles read will be interpreted as ns. */
6914                 shift = 0;
6915                 /* Fall-through */
6916         case ixgbe_mac_X540:
6917                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6918                 break;
6919         case ixgbe_mac_82599EB:
6920                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6921                 shift -= IXGBE_INCVAL_SHIFT_82599;
6922                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6923                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6924                 break;
6925         default:
6926                 /* Not supported. */
6927                 return;
6928         }
6929
6930         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6931         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6932         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6933
6934         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6935         adapter->systime_tc.cc_shift = shift;
6936         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6937
6938         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6939         adapter->rx_tstamp_tc.cc_shift = shift;
6940         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6941
6942         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6943         adapter->tx_tstamp_tc.cc_shift = shift;
6944         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6945 }
6946
6947 static int
6948 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6949 {
6950         struct ixgbe_adapter *adapter =
6951                         (struct ixgbe_adapter *)dev->data->dev_private;
6952
6953         adapter->systime_tc.nsec += delta;
6954         adapter->rx_tstamp_tc.nsec += delta;
6955         adapter->tx_tstamp_tc.nsec += delta;
6956
6957         return 0;
6958 }
6959
6960 static int
6961 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6962 {
6963         uint64_t ns;
6964         struct ixgbe_adapter *adapter =
6965                         (struct ixgbe_adapter *)dev->data->dev_private;
6966
6967         ns = rte_timespec_to_ns(ts);
6968         /* Set the timecounters to a new value. */
6969         adapter->systime_tc.nsec = ns;
6970         adapter->rx_tstamp_tc.nsec = ns;
6971         adapter->tx_tstamp_tc.nsec = ns;
6972
6973         return 0;
6974 }
6975
6976 static int
6977 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6978 {
6979         uint64_t ns, systime_cycles;
6980         struct ixgbe_adapter *adapter =
6981                         (struct ixgbe_adapter *)dev->data->dev_private;
6982
6983         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6984         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6985         *ts = rte_ns_to_timespec(ns);
6986
6987         return 0;
6988 }
6989
6990 static int
6991 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6992 {
6993         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6994         uint32_t tsync_ctl;
6995         uint32_t tsauxc;
6996
6997         /* Stop the timesync system time. */
6998         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6999         /* Reset the timesync system time value. */
7000         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7001         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7002
7003         /* Enable system time for platforms where it isn't on by default. */
7004         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7005         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7006         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7007
7008         ixgbe_start_timecounters(dev);
7009
7010         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7011         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7012                         (ETHER_TYPE_1588 |
7013                          IXGBE_ETQF_FILTER_EN |
7014                          IXGBE_ETQF_1588));
7015
7016         /* Enable timestamping of received PTP packets. */
7017         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7018         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7019         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7020
7021         /* Enable timestamping of transmitted PTP packets. */
7022         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7023         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7024         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7025
7026         IXGBE_WRITE_FLUSH(hw);
7027
7028         return 0;
7029 }
7030
7031 static int
7032 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7033 {
7034         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7035         uint32_t tsync_ctl;
7036
7037         /* Disable timestamping of transmitted PTP packets. */
7038         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7039         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7040         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7041
7042         /* Disable timestamping of received PTP packets. */
7043         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7044         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7045         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7046
7047         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7048         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7049
7050         /* Stop incrementating the System Time registers. */
7051         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7052
7053         return 0;
7054 }
7055
7056 static int
7057 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7058                                  struct timespec *timestamp,
7059                                  uint32_t flags __rte_unused)
7060 {
7061         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7062         struct ixgbe_adapter *adapter =
7063                 (struct ixgbe_adapter *)dev->data->dev_private;
7064         uint32_t tsync_rxctl;
7065         uint64_t rx_tstamp_cycles;
7066         uint64_t ns;
7067
7068         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7069         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7070                 return -EINVAL;
7071
7072         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7073         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7074         *timestamp = rte_ns_to_timespec(ns);
7075
7076         return  0;
7077 }
7078
7079 static int
7080 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7081                                  struct timespec *timestamp)
7082 {
7083         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7084         struct ixgbe_adapter *adapter =
7085                 (struct ixgbe_adapter *)dev->data->dev_private;
7086         uint32_t tsync_txctl;
7087         uint64_t tx_tstamp_cycles;
7088         uint64_t ns;
7089
7090         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7091         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7092                 return -EINVAL;
7093
7094         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7095         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7096         *timestamp = rte_ns_to_timespec(ns);
7097
7098         return 0;
7099 }
7100
7101 static int
7102 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7103 {
7104         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7105         int count = 0;
7106         int g_ind = 0;
7107         const struct reg_info *reg_group;
7108         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7109                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7110
7111         while ((reg_group = reg_set[g_ind++]))
7112                 count += ixgbe_regs_group_count(reg_group);
7113
7114         return count;
7115 }
7116
7117 static int
7118 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7119 {
7120         int count = 0;
7121         int g_ind = 0;
7122         const struct reg_info *reg_group;
7123
7124         while ((reg_group = ixgbevf_regs[g_ind++]))
7125                 count += ixgbe_regs_group_count(reg_group);
7126
7127         return count;
7128 }
7129
7130 static int
7131 ixgbe_get_regs(struct rte_eth_dev *dev,
7132               struct rte_dev_reg_info *regs)
7133 {
7134         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7135         uint32_t *data = regs->data;
7136         int g_ind = 0;
7137         int count = 0;
7138         const struct reg_info *reg_group;
7139         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7140                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7141
7142         if (data == NULL) {
7143                 regs->length = ixgbe_get_reg_length(dev);
7144                 regs->width = sizeof(uint32_t);
7145                 return 0;
7146         }
7147
7148         /* Support only full register dump */
7149         if ((regs->length == 0) ||
7150             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7151                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7152                         hw->device_id;
7153                 while ((reg_group = reg_set[g_ind++]))
7154                         count += ixgbe_read_regs_group(dev, &data[count],
7155                                 reg_group);
7156                 return 0;
7157         }
7158
7159         return -ENOTSUP;
7160 }
7161
7162 static int
7163 ixgbevf_get_regs(struct rte_eth_dev *dev,
7164                 struct rte_dev_reg_info *regs)
7165 {
7166         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7167         uint32_t *data = regs->data;
7168         int g_ind = 0;
7169         int count = 0;
7170         const struct reg_info *reg_group;
7171
7172         if (data == NULL) {
7173                 regs->length = ixgbevf_get_reg_length(dev);
7174                 regs->width = sizeof(uint32_t);
7175                 return 0;
7176         }
7177
7178         /* Support only full register dump */
7179         if ((regs->length == 0) ||
7180             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7181                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7182                         hw->device_id;
7183                 while ((reg_group = ixgbevf_regs[g_ind++]))
7184                         count += ixgbe_read_regs_group(dev, &data[count],
7185                                                       reg_group);
7186                 return 0;
7187         }
7188
7189         return -ENOTSUP;
7190 }
7191
7192 static int
7193 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7194 {
7195         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7196
7197         /* Return unit is byte count */
7198         return hw->eeprom.word_size * 2;
7199 }
7200
7201 static int
7202 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7203                 struct rte_dev_eeprom_info *in_eeprom)
7204 {
7205         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7206         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7207         uint16_t *data = in_eeprom->data;
7208         int first, length;
7209
7210         first = in_eeprom->offset >> 1;
7211         length = in_eeprom->length >> 1;
7212         if ((first > hw->eeprom.word_size) ||
7213             ((first + length) > hw->eeprom.word_size))
7214                 return -EINVAL;
7215
7216         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7217
7218         return eeprom->ops.read_buffer(hw, first, length, data);
7219 }
7220
7221 static int
7222 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7223                 struct rte_dev_eeprom_info *in_eeprom)
7224 {
7225         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7226         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7227         uint16_t *data = in_eeprom->data;
7228         int first, length;
7229
7230         first = in_eeprom->offset >> 1;
7231         length = in_eeprom->length >> 1;
7232         if ((first > hw->eeprom.word_size) ||
7233             ((first + length) > hw->eeprom.word_size))
7234                 return -EINVAL;
7235
7236         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7237
7238         return eeprom->ops.write_buffer(hw,  first, length, data);
7239 }
7240
7241 static int
7242 ixgbe_get_module_info(struct rte_eth_dev *dev,
7243                       struct rte_eth_dev_module_info *modinfo)
7244 {
7245         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7246         uint32_t status;
7247         uint8_t sff8472_rev, addr_mode;
7248         bool page_swap = false;
7249
7250         /* Check whether we support SFF-8472 or not */
7251         status = hw->phy.ops.read_i2c_eeprom(hw,
7252                                              IXGBE_SFF_SFF_8472_COMP,
7253                                              &sff8472_rev);
7254         if (status != 0)
7255                 return -EIO;
7256
7257         /* addressing mode is not supported */
7258         status = hw->phy.ops.read_i2c_eeprom(hw,
7259                                              IXGBE_SFF_SFF_8472_SWAP,
7260                                              &addr_mode);
7261         if (status != 0)
7262                 return -EIO;
7263
7264         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7265                 PMD_DRV_LOG(ERR,
7266                             "Address change required to access page 0xA2, "
7267                             "but not supported. Please report the module "
7268                             "type to the driver maintainers.");
7269                 page_swap = true;
7270         }
7271
7272         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7273                 /* We have a SFP, but it does not support SFF-8472 */
7274                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7275                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7276         } else {
7277                 /* We have a SFP which supports a revision of SFF-8472. */
7278                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7279                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7280         }
7281
7282         return 0;
7283 }
7284
7285 static int
7286 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7287                         struct rte_dev_eeprom_info *info)
7288 {
7289         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7290         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7291         uint8_t databyte = 0xFF;
7292         uint8_t *data = info->data;
7293         uint32_t i = 0;
7294
7295         if (info->length == 0)
7296                 return -EINVAL;
7297
7298         for (i = info->offset; i < info->offset + info->length; i++) {
7299                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7300                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7301                 else
7302                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7303
7304                 if (status != 0)
7305                         return -EIO;
7306
7307                 data[i - info->offset] = databyte;
7308         }
7309
7310         return 0;
7311 }
7312
7313 uint16_t
7314 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7315         switch (mac_type) {
7316         case ixgbe_mac_X550:
7317         case ixgbe_mac_X550EM_x:
7318         case ixgbe_mac_X550EM_a:
7319                 return ETH_RSS_RETA_SIZE_512;
7320         case ixgbe_mac_X550_vf:
7321         case ixgbe_mac_X550EM_x_vf:
7322         case ixgbe_mac_X550EM_a_vf:
7323                 return ETH_RSS_RETA_SIZE_64;
7324         default:
7325                 return ETH_RSS_RETA_SIZE_128;
7326         }
7327 }
7328
7329 uint32_t
7330 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7331         switch (mac_type) {
7332         case ixgbe_mac_X550:
7333         case ixgbe_mac_X550EM_x:
7334         case ixgbe_mac_X550EM_a:
7335                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7336                         return IXGBE_RETA(reta_idx >> 2);
7337                 else
7338                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7339         case ixgbe_mac_X550_vf:
7340         case ixgbe_mac_X550EM_x_vf:
7341         case ixgbe_mac_X550EM_a_vf:
7342                 return IXGBE_VFRETA(reta_idx >> 2);
7343         default:
7344                 return IXGBE_RETA(reta_idx >> 2);
7345         }
7346 }
7347
7348 uint32_t
7349 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7350         switch (mac_type) {
7351         case ixgbe_mac_X550_vf:
7352         case ixgbe_mac_X550EM_x_vf:
7353         case ixgbe_mac_X550EM_a_vf:
7354                 return IXGBE_VFMRQC;
7355         default:
7356                 return IXGBE_MRQC;
7357         }
7358 }
7359
7360 uint32_t
7361 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7362         switch (mac_type) {
7363         case ixgbe_mac_X550_vf:
7364         case ixgbe_mac_X550EM_x_vf:
7365         case ixgbe_mac_X550EM_a_vf:
7366                 return IXGBE_VFRSSRK(i);
7367         default:
7368                 return IXGBE_RSSRK(i);
7369         }
7370 }
7371
7372 bool
7373 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7374         switch (mac_type) {
7375         case ixgbe_mac_82599_vf:
7376         case ixgbe_mac_X540_vf:
7377                 return 0;
7378         default:
7379                 return 1;
7380         }
7381 }
7382
7383 static int
7384 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7385                         struct rte_eth_dcb_info *dcb_info)
7386 {
7387         struct ixgbe_dcb_config *dcb_config =
7388                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7389         struct ixgbe_dcb_tc_config *tc;
7390         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7391         uint8_t nb_tcs;
7392         uint8_t i, j;
7393
7394         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7395                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7396         else
7397                 dcb_info->nb_tcs = 1;
7398
7399         tc_queue = &dcb_info->tc_queue;
7400         nb_tcs = dcb_info->nb_tcs;
7401
7402         if (dcb_config->vt_mode) { /* vt is enabled*/
7403                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7404                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7405                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7406                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7407                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7408                         for (j = 0; j < nb_tcs; j++) {
7409                                 tc_queue->tc_rxq[0][j].base = j;
7410                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7411                                 tc_queue->tc_txq[0][j].base = j;
7412                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7413                         }
7414                 } else {
7415                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7416                                 for (j = 0; j < nb_tcs; j++) {
7417                                         tc_queue->tc_rxq[i][j].base =
7418                                                 i * nb_tcs + j;
7419                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7420                                         tc_queue->tc_txq[i][j].base =
7421                                                 i * nb_tcs + j;
7422                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7423                                 }
7424                         }
7425                 }
7426         } else { /* vt is disabled*/
7427                 struct rte_eth_dcb_rx_conf *rx_conf =
7428                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7429                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7430                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7431                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7432                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7433                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7434                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7435                         }
7436                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7437                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7438                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7439                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7440                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7441                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7442                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7443                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7444                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7445                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7446                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7447                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7448                         }
7449                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7450                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7451                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7452                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7453                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7454                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7455                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7456                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7457                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7458                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7459                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7460                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7461                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7462                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7463                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7464                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7465                 }
7466         }
7467         for (i = 0; i < dcb_info->nb_tcs; i++) {
7468                 tc = &dcb_config->tc_config[i];
7469                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7470         }
7471         return 0;
7472 }
7473
7474 /* Update e-tag ether type */
7475 static int
7476 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7477                             uint16_t ether_type)
7478 {
7479         uint32_t etag_etype;
7480
7481         if (hw->mac.type != ixgbe_mac_X550 &&
7482             hw->mac.type != ixgbe_mac_X550EM_x &&
7483             hw->mac.type != ixgbe_mac_X550EM_a) {
7484                 return -ENOTSUP;
7485         }
7486
7487         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7488         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7489         etag_etype |= ether_type;
7490         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7491         IXGBE_WRITE_FLUSH(hw);
7492
7493         return 0;
7494 }
7495
7496 /* Config l2 tunnel ether type */
7497 static int
7498 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7499                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7500 {
7501         int ret = 0;
7502         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7503         struct ixgbe_l2_tn_info *l2_tn_info =
7504                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7505
7506         if (l2_tunnel == NULL)
7507                 return -EINVAL;
7508
7509         switch (l2_tunnel->l2_tunnel_type) {
7510         case RTE_L2_TUNNEL_TYPE_E_TAG:
7511                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7512                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7513                 break;
7514         default:
7515                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7516                 ret = -EINVAL;
7517                 break;
7518         }
7519
7520         return ret;
7521 }
7522
7523 /* Enable e-tag tunnel */
7524 static int
7525 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7526 {
7527         uint32_t etag_etype;
7528
7529         if (hw->mac.type != ixgbe_mac_X550 &&
7530             hw->mac.type != ixgbe_mac_X550EM_x &&
7531             hw->mac.type != ixgbe_mac_X550EM_a) {
7532                 return -ENOTSUP;
7533         }
7534
7535         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7536         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7537         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7538         IXGBE_WRITE_FLUSH(hw);
7539
7540         return 0;
7541 }
7542
7543 /* Enable l2 tunnel */
7544 static int
7545 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7546                            enum rte_eth_tunnel_type l2_tunnel_type)
7547 {
7548         int ret = 0;
7549         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7550         struct ixgbe_l2_tn_info *l2_tn_info =
7551                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7552
7553         switch (l2_tunnel_type) {
7554         case RTE_L2_TUNNEL_TYPE_E_TAG:
7555                 l2_tn_info->e_tag_en = TRUE;
7556                 ret = ixgbe_e_tag_enable(hw);
7557                 break;
7558         default:
7559                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7560                 ret = -EINVAL;
7561                 break;
7562         }
7563
7564         return ret;
7565 }
7566
7567 /* Disable e-tag tunnel */
7568 static int
7569 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7570 {
7571         uint32_t etag_etype;
7572
7573         if (hw->mac.type != ixgbe_mac_X550 &&
7574             hw->mac.type != ixgbe_mac_X550EM_x &&
7575             hw->mac.type != ixgbe_mac_X550EM_a) {
7576                 return -ENOTSUP;
7577         }
7578
7579         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7580         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7581         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7582         IXGBE_WRITE_FLUSH(hw);
7583
7584         return 0;
7585 }
7586
7587 /* Disable l2 tunnel */
7588 static int
7589 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7590                             enum rte_eth_tunnel_type l2_tunnel_type)
7591 {
7592         int ret = 0;
7593         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7594         struct ixgbe_l2_tn_info *l2_tn_info =
7595                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7596
7597         switch (l2_tunnel_type) {
7598         case RTE_L2_TUNNEL_TYPE_E_TAG:
7599                 l2_tn_info->e_tag_en = FALSE;
7600                 ret = ixgbe_e_tag_disable(hw);
7601                 break;
7602         default:
7603                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7604                 ret = -EINVAL;
7605                 break;
7606         }
7607
7608         return ret;
7609 }
7610
7611 static int
7612 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7613                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7614 {
7615         int ret = 0;
7616         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7617         uint32_t i, rar_entries;
7618         uint32_t rar_low, rar_high;
7619
7620         if (hw->mac.type != ixgbe_mac_X550 &&
7621             hw->mac.type != ixgbe_mac_X550EM_x &&
7622             hw->mac.type != ixgbe_mac_X550EM_a) {
7623                 return -ENOTSUP;
7624         }
7625
7626         rar_entries = ixgbe_get_num_rx_addrs(hw);
7627
7628         for (i = 1; i < rar_entries; i++) {
7629                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7630                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7631                 if ((rar_high & IXGBE_RAH_AV) &&
7632                     (rar_high & IXGBE_RAH_ADTYPE) &&
7633                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7634                      l2_tunnel->tunnel_id)) {
7635                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7636                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7637
7638                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7639
7640                         return ret;
7641                 }
7642         }
7643
7644         return ret;
7645 }
7646
7647 static int
7648 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7649                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7650 {
7651         int ret = 0;
7652         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7653         uint32_t i, rar_entries;
7654         uint32_t rar_low, rar_high;
7655
7656         if (hw->mac.type != ixgbe_mac_X550 &&
7657             hw->mac.type != ixgbe_mac_X550EM_x &&
7658             hw->mac.type != ixgbe_mac_X550EM_a) {
7659                 return -ENOTSUP;
7660         }
7661
7662         /* One entry for one tunnel. Try to remove potential existing entry. */
7663         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7664
7665         rar_entries = ixgbe_get_num_rx_addrs(hw);
7666
7667         for (i = 1; i < rar_entries; i++) {
7668                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7669                 if (rar_high & IXGBE_RAH_AV) {
7670                         continue;
7671                 } else {
7672                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7673                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7674                         rar_low = l2_tunnel->tunnel_id;
7675
7676                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7677                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7678
7679                         return ret;
7680                 }
7681         }
7682
7683         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7684                      " Please remove a rule before adding a new one.");
7685         return -EINVAL;
7686 }
7687
7688 static inline struct ixgbe_l2_tn_filter *
7689 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7690                           struct ixgbe_l2_tn_key *key)
7691 {
7692         int ret;
7693
7694         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7695         if (ret < 0)
7696                 return NULL;
7697
7698         return l2_tn_info->hash_map[ret];
7699 }
7700
7701 static inline int
7702 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7703                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7704 {
7705         int ret;
7706
7707         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7708                                &l2_tn_filter->key);
7709
7710         if (ret < 0) {
7711                 PMD_DRV_LOG(ERR,
7712                             "Failed to insert L2 tunnel filter"
7713                             " to hash table %d!",
7714                             ret);
7715                 return ret;
7716         }
7717
7718         l2_tn_info->hash_map[ret] = l2_tn_filter;
7719
7720         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7721
7722         return 0;
7723 }
7724
7725 static inline int
7726 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7727                           struct ixgbe_l2_tn_key *key)
7728 {
7729         int ret;
7730         struct ixgbe_l2_tn_filter *l2_tn_filter;
7731
7732         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7733
7734         if (ret < 0) {
7735                 PMD_DRV_LOG(ERR,
7736                             "No such L2 tunnel filter to delete %d!",
7737                             ret);
7738                 return ret;
7739         }
7740
7741         l2_tn_filter = l2_tn_info->hash_map[ret];
7742         l2_tn_info->hash_map[ret] = NULL;
7743
7744         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7745         rte_free(l2_tn_filter);
7746
7747         return 0;
7748 }
7749
7750 /* Add l2 tunnel filter */
7751 int
7752 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7753                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7754                                bool restore)
7755 {
7756         int ret;
7757         struct ixgbe_l2_tn_info *l2_tn_info =
7758                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7759         struct ixgbe_l2_tn_key key;
7760         struct ixgbe_l2_tn_filter *node;
7761
7762         if (!restore) {
7763                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7764                 key.tn_id = l2_tunnel->tunnel_id;
7765
7766                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7767
7768                 if (node) {
7769                         PMD_DRV_LOG(ERR,
7770                                     "The L2 tunnel filter already exists!");
7771                         return -EINVAL;
7772                 }
7773
7774                 node = rte_zmalloc("ixgbe_l2_tn",
7775                                    sizeof(struct ixgbe_l2_tn_filter),
7776                                    0);
7777                 if (!node)
7778                         return -ENOMEM;
7779
7780                 rte_memcpy(&node->key,
7781                                  &key,
7782                                  sizeof(struct ixgbe_l2_tn_key));
7783                 node->pool = l2_tunnel->pool;
7784                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7785                 if (ret < 0) {
7786                         rte_free(node);
7787                         return ret;
7788                 }
7789         }
7790
7791         switch (l2_tunnel->l2_tunnel_type) {
7792         case RTE_L2_TUNNEL_TYPE_E_TAG:
7793                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7794                 break;
7795         default:
7796                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7797                 ret = -EINVAL;
7798                 break;
7799         }
7800
7801         if ((!restore) && (ret < 0))
7802                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7803
7804         return ret;
7805 }
7806
7807 /* Delete l2 tunnel filter */
7808 int
7809 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7810                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7811 {
7812         int ret;
7813         struct ixgbe_l2_tn_info *l2_tn_info =
7814                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7815         struct ixgbe_l2_tn_key key;
7816
7817         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7818         key.tn_id = l2_tunnel->tunnel_id;
7819         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7820         if (ret < 0)
7821                 return ret;
7822
7823         switch (l2_tunnel->l2_tunnel_type) {
7824         case RTE_L2_TUNNEL_TYPE_E_TAG:
7825                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7826                 break;
7827         default:
7828                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7829                 ret = -EINVAL;
7830                 break;
7831         }
7832
7833         return ret;
7834 }
7835
7836 /**
7837  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7838  * @dev: pointer to rte_eth_dev structure
7839  * @filter_op:operation will be taken.
7840  * @arg: a pointer to specific structure corresponding to the filter_op
7841  */
7842 static int
7843 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7844                                   enum rte_filter_op filter_op,
7845                                   void *arg)
7846 {
7847         int ret;
7848
7849         if (filter_op == RTE_ETH_FILTER_NOP)
7850                 return 0;
7851
7852         if (arg == NULL) {
7853                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7854                             filter_op);
7855                 return -EINVAL;
7856         }
7857
7858         switch (filter_op) {
7859         case RTE_ETH_FILTER_ADD:
7860                 ret = ixgbe_dev_l2_tunnel_filter_add
7861                         (dev,
7862                          (struct rte_eth_l2_tunnel_conf *)arg,
7863                          FALSE);
7864                 break;
7865         case RTE_ETH_FILTER_DELETE:
7866                 ret = ixgbe_dev_l2_tunnel_filter_del
7867                         (dev,
7868                          (struct rte_eth_l2_tunnel_conf *)arg);
7869                 break;
7870         default:
7871                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7872                 ret = -EINVAL;
7873                 break;
7874         }
7875         return ret;
7876 }
7877
7878 static int
7879 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7880 {
7881         int ret = 0;
7882         uint32_t ctrl;
7883         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7884
7885         if (hw->mac.type != ixgbe_mac_X550 &&
7886             hw->mac.type != ixgbe_mac_X550EM_x &&
7887             hw->mac.type != ixgbe_mac_X550EM_a) {
7888                 return -ENOTSUP;
7889         }
7890
7891         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7892         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7893         if (en)
7894                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7895         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7896
7897         return ret;
7898 }
7899
7900 /* Enable l2 tunnel forwarding */
7901 static int
7902 ixgbe_dev_l2_tunnel_forwarding_enable
7903         (struct rte_eth_dev *dev,
7904          enum rte_eth_tunnel_type l2_tunnel_type)
7905 {
7906         struct ixgbe_l2_tn_info *l2_tn_info =
7907                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7908         int ret = 0;
7909
7910         switch (l2_tunnel_type) {
7911         case RTE_L2_TUNNEL_TYPE_E_TAG:
7912                 l2_tn_info->e_tag_fwd_en = TRUE;
7913                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7914                 break;
7915         default:
7916                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7917                 ret = -EINVAL;
7918                 break;
7919         }
7920
7921         return ret;
7922 }
7923
7924 /* Disable l2 tunnel forwarding */
7925 static int
7926 ixgbe_dev_l2_tunnel_forwarding_disable
7927         (struct rte_eth_dev *dev,
7928          enum rte_eth_tunnel_type l2_tunnel_type)
7929 {
7930         struct ixgbe_l2_tn_info *l2_tn_info =
7931                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7932         int ret = 0;
7933
7934         switch (l2_tunnel_type) {
7935         case RTE_L2_TUNNEL_TYPE_E_TAG:
7936                 l2_tn_info->e_tag_fwd_en = FALSE;
7937                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7938                 break;
7939         default:
7940                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7941                 ret = -EINVAL;
7942                 break;
7943         }
7944
7945         return ret;
7946 }
7947
7948 static int
7949 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7950                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7951                              bool en)
7952 {
7953         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7954         int ret = 0;
7955         uint32_t vmtir, vmvir;
7956         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7957
7958         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7959                 PMD_DRV_LOG(ERR,
7960                             "VF id %u should be less than %u",
7961                             l2_tunnel->vf_id,
7962                             pci_dev->max_vfs);
7963                 return -EINVAL;
7964         }
7965
7966         if (hw->mac.type != ixgbe_mac_X550 &&
7967             hw->mac.type != ixgbe_mac_X550EM_x &&
7968             hw->mac.type != ixgbe_mac_X550EM_a) {
7969                 return -ENOTSUP;
7970         }
7971
7972         if (en)
7973                 vmtir = l2_tunnel->tunnel_id;
7974         else
7975                 vmtir = 0;
7976
7977         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7978
7979         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7980         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7981         if (en)
7982                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7983         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7984
7985         return ret;
7986 }
7987
7988 /* Enable l2 tunnel tag insertion */
7989 static int
7990 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7991                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7992 {
7993         int ret = 0;
7994
7995         switch (l2_tunnel->l2_tunnel_type) {
7996         case RTE_L2_TUNNEL_TYPE_E_TAG:
7997                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7998                 break;
7999         default:
8000                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8001                 ret = -EINVAL;
8002                 break;
8003         }
8004
8005         return ret;
8006 }
8007
8008 /* Disable l2 tunnel tag insertion */
8009 static int
8010 ixgbe_dev_l2_tunnel_insertion_disable
8011         (struct rte_eth_dev *dev,
8012          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8013 {
8014         int ret = 0;
8015
8016         switch (l2_tunnel->l2_tunnel_type) {
8017         case RTE_L2_TUNNEL_TYPE_E_TAG:
8018                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8019                 break;
8020         default:
8021                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8022                 ret = -EINVAL;
8023                 break;
8024         }
8025
8026         return ret;
8027 }
8028
8029 static int
8030 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8031                              bool en)
8032 {
8033         int ret = 0;
8034         uint32_t qde;
8035         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8036
8037         if (hw->mac.type != ixgbe_mac_X550 &&
8038             hw->mac.type != ixgbe_mac_X550EM_x &&
8039             hw->mac.type != ixgbe_mac_X550EM_a) {
8040                 return -ENOTSUP;
8041         }
8042
8043         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8044         if (en)
8045                 qde |= IXGBE_QDE_STRIP_TAG;
8046         else
8047                 qde &= ~IXGBE_QDE_STRIP_TAG;
8048         qde &= ~IXGBE_QDE_READ;
8049         qde |= IXGBE_QDE_WRITE;
8050         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8051
8052         return ret;
8053 }
8054
8055 /* Enable l2 tunnel tag stripping */
8056 static int
8057 ixgbe_dev_l2_tunnel_stripping_enable
8058         (struct rte_eth_dev *dev,
8059          enum rte_eth_tunnel_type l2_tunnel_type)
8060 {
8061         int ret = 0;
8062
8063         switch (l2_tunnel_type) {
8064         case RTE_L2_TUNNEL_TYPE_E_TAG:
8065                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8066                 break;
8067         default:
8068                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8069                 ret = -EINVAL;
8070                 break;
8071         }
8072
8073         return ret;
8074 }
8075
8076 /* Disable l2 tunnel tag stripping */
8077 static int
8078 ixgbe_dev_l2_tunnel_stripping_disable
8079         (struct rte_eth_dev *dev,
8080          enum rte_eth_tunnel_type l2_tunnel_type)
8081 {
8082         int ret = 0;
8083
8084         switch (l2_tunnel_type) {
8085         case RTE_L2_TUNNEL_TYPE_E_TAG:
8086                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8087                 break;
8088         default:
8089                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8090                 ret = -EINVAL;
8091                 break;
8092         }
8093
8094         return ret;
8095 }
8096
8097 /* Enable/disable l2 tunnel offload functions */
8098 static int
8099 ixgbe_dev_l2_tunnel_offload_set
8100         (struct rte_eth_dev *dev,
8101          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8102          uint32_t mask,
8103          uint8_t en)
8104 {
8105         int ret = 0;
8106
8107         if (l2_tunnel == NULL)
8108                 return -EINVAL;
8109
8110         ret = -EINVAL;
8111         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8112                 if (en)
8113                         ret = ixgbe_dev_l2_tunnel_enable(
8114                                 dev,
8115                                 l2_tunnel->l2_tunnel_type);
8116                 else
8117                         ret = ixgbe_dev_l2_tunnel_disable(
8118                                 dev,
8119                                 l2_tunnel->l2_tunnel_type);
8120         }
8121
8122         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8123                 if (en)
8124                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8125                                 dev,
8126                                 l2_tunnel);
8127                 else
8128                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8129                                 dev,
8130                                 l2_tunnel);
8131         }
8132
8133         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8134                 if (en)
8135                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8136                                 dev,
8137                                 l2_tunnel->l2_tunnel_type);
8138                 else
8139                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8140                                 dev,
8141                                 l2_tunnel->l2_tunnel_type);
8142         }
8143
8144         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8145                 if (en)
8146                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8147                                 dev,
8148                                 l2_tunnel->l2_tunnel_type);
8149                 else
8150                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8151                                 dev,
8152                                 l2_tunnel->l2_tunnel_type);
8153         }
8154
8155         return ret;
8156 }
8157
8158 static int
8159 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8160                         uint16_t port)
8161 {
8162         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8163         IXGBE_WRITE_FLUSH(hw);
8164
8165         return 0;
8166 }
8167
8168 /* There's only one register for VxLAN UDP port.
8169  * So, we cannot add several ports. Will update it.
8170  */
8171 static int
8172 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8173                      uint16_t port)
8174 {
8175         if (port == 0) {
8176                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8177                 return -EINVAL;
8178         }
8179
8180         return ixgbe_update_vxlan_port(hw, port);
8181 }
8182
8183 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8184  * UDP port, it must have a value.
8185  * So, will reset it to the original value 0.
8186  */
8187 static int
8188 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8189                      uint16_t port)
8190 {
8191         uint16_t cur_port;
8192
8193         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8194
8195         if (cur_port != port) {
8196                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8197                 return -EINVAL;
8198         }
8199
8200         return ixgbe_update_vxlan_port(hw, 0);
8201 }
8202
8203 /* Add UDP tunneling port */
8204 static int
8205 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8206                               struct rte_eth_udp_tunnel *udp_tunnel)
8207 {
8208         int ret = 0;
8209         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8210
8211         if (hw->mac.type != ixgbe_mac_X550 &&
8212             hw->mac.type != ixgbe_mac_X550EM_x &&
8213             hw->mac.type != ixgbe_mac_X550EM_a) {
8214                 return -ENOTSUP;
8215         }
8216
8217         if (udp_tunnel == NULL)
8218                 return -EINVAL;
8219
8220         switch (udp_tunnel->prot_type) {
8221         case RTE_TUNNEL_TYPE_VXLAN:
8222                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8223                 break;
8224
8225         case RTE_TUNNEL_TYPE_GENEVE:
8226         case RTE_TUNNEL_TYPE_TEREDO:
8227                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8228                 ret = -EINVAL;
8229                 break;
8230
8231         default:
8232                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8233                 ret = -EINVAL;
8234                 break;
8235         }
8236
8237         return ret;
8238 }
8239
8240 /* Remove UDP tunneling port */
8241 static int
8242 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8243                               struct rte_eth_udp_tunnel *udp_tunnel)
8244 {
8245         int ret = 0;
8246         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8247
8248         if (hw->mac.type != ixgbe_mac_X550 &&
8249             hw->mac.type != ixgbe_mac_X550EM_x &&
8250             hw->mac.type != ixgbe_mac_X550EM_a) {
8251                 return -ENOTSUP;
8252         }
8253
8254         if (udp_tunnel == NULL)
8255                 return -EINVAL;
8256
8257         switch (udp_tunnel->prot_type) {
8258         case RTE_TUNNEL_TYPE_VXLAN:
8259                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8260                 break;
8261         case RTE_TUNNEL_TYPE_GENEVE:
8262         case RTE_TUNNEL_TYPE_TEREDO:
8263                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8264                 ret = -EINVAL;
8265                 break;
8266         default:
8267                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8268                 ret = -EINVAL;
8269                 break;
8270         }
8271
8272         return ret;
8273 }
8274
8275 static void
8276 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8277 {
8278         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8279
8280         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8281 }
8282
8283 static void
8284 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8285 {
8286         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8287
8288         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8289 }
8290
8291 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8292 {
8293         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8294         u32 in_msg = 0;
8295
8296         /* peek the message first */
8297         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8298
8299         /* PF reset VF event */
8300         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8301                 /* dummy mbx read to ack pf */
8302                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8303                         return;
8304                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8305                                               NULL);
8306         }
8307 }
8308
8309 static int
8310 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8311 {
8312         uint32_t eicr;
8313         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8314         struct ixgbe_interrupt *intr =
8315                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8316         ixgbevf_intr_disable(dev);
8317
8318         /* read-on-clear nic registers here */
8319         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8320         intr->flags = 0;
8321
8322         /* only one misc vector supported - mailbox */
8323         eicr &= IXGBE_VTEICR_MASK;
8324         if (eicr == IXGBE_MISC_VEC_ID)
8325                 intr->flags |= IXGBE_FLAG_MAILBOX;
8326
8327         return 0;
8328 }
8329
8330 static int
8331 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8332 {
8333         struct ixgbe_interrupt *intr =
8334                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8335
8336         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8337                 ixgbevf_mbx_process(dev);
8338                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8339         }
8340
8341         ixgbevf_intr_enable(dev);
8342
8343         return 0;
8344 }
8345
8346 static void
8347 ixgbevf_dev_interrupt_handler(void *param)
8348 {
8349         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8350
8351         ixgbevf_dev_interrupt_get_status(dev);
8352         ixgbevf_dev_interrupt_action(dev);
8353 }
8354
8355 /**
8356  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8357  *  @hw: pointer to hardware structure
8358  *
8359  *  Stops the transmit data path and waits for the HW to internally empty
8360  *  the Tx security block
8361  **/
8362 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8363 {
8364 #define IXGBE_MAX_SECTX_POLL 40
8365
8366         int i;
8367         int sectxreg;
8368
8369         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8370         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8371         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8372         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8373                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8374                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8375                         break;
8376                 /* Use interrupt-safe sleep just in case */
8377                 usec_delay(1000);
8378         }
8379
8380         /* For informational purposes only */
8381         if (i >= IXGBE_MAX_SECTX_POLL)
8382                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8383                          "path fully disabled.  Continuing with init.");
8384
8385         return IXGBE_SUCCESS;
8386 }
8387
8388 /**
8389  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8390  *  @hw: pointer to hardware structure
8391  *
8392  *  Enables the transmit data path.
8393  **/
8394 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8395 {
8396         uint32_t sectxreg;
8397
8398         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8399         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8400         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8401         IXGBE_WRITE_FLUSH(hw);
8402
8403         return IXGBE_SUCCESS;
8404 }
8405
8406 /* restore n-tuple filter */
8407 static inline void
8408 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8409 {
8410         struct ixgbe_filter_info *filter_info =
8411                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8412         struct ixgbe_5tuple_filter *node;
8413
8414         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8415                 ixgbe_inject_5tuple_filter(dev, node);
8416         }
8417 }
8418
8419 /* restore ethernet type filter */
8420 static inline void
8421 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8422 {
8423         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8424         struct ixgbe_filter_info *filter_info =
8425                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8426         int i;
8427
8428         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8429                 if (filter_info->ethertype_mask & (1 << i)) {
8430                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8431                                         filter_info->ethertype_filters[i].etqf);
8432                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8433                                         filter_info->ethertype_filters[i].etqs);
8434                         IXGBE_WRITE_FLUSH(hw);
8435                 }
8436         }
8437 }
8438
8439 /* restore SYN filter */
8440 static inline void
8441 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8442 {
8443         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8444         struct ixgbe_filter_info *filter_info =
8445                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8446         uint32_t synqf;
8447
8448         synqf = filter_info->syn_info;
8449
8450         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8451                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8452                 IXGBE_WRITE_FLUSH(hw);
8453         }
8454 }
8455
8456 /* restore L2 tunnel filter */
8457 static inline void
8458 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8459 {
8460         struct ixgbe_l2_tn_info *l2_tn_info =
8461                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8462         struct ixgbe_l2_tn_filter *node;
8463         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8464
8465         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8466                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8467                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8468                 l2_tn_conf.pool           = node->pool;
8469                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8470         }
8471 }
8472
8473 /* restore rss filter */
8474 static inline void
8475 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8476 {
8477         struct ixgbe_filter_info *filter_info =
8478                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8479
8480         if (filter_info->rss_info.conf.queue_num)
8481                 ixgbe_config_rss_filter(dev,
8482                         &filter_info->rss_info, TRUE);
8483 }
8484
8485 static int
8486 ixgbe_filter_restore(struct rte_eth_dev *dev)
8487 {
8488         ixgbe_ntuple_filter_restore(dev);
8489         ixgbe_ethertype_filter_restore(dev);
8490         ixgbe_syn_filter_restore(dev);
8491         ixgbe_fdir_filter_restore(dev);
8492         ixgbe_l2_tn_filter_restore(dev);
8493         ixgbe_rss_filter_restore(dev);
8494
8495         return 0;
8496 }
8497
8498 static void
8499 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8500 {
8501         struct ixgbe_l2_tn_info *l2_tn_info =
8502                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8503         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8504
8505         if (l2_tn_info->e_tag_en)
8506                 (void)ixgbe_e_tag_enable(hw);
8507
8508         if (l2_tn_info->e_tag_fwd_en)
8509                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8510
8511         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8512 }
8513
8514 /* remove all the n-tuple filters */
8515 void
8516 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8517 {
8518         struct ixgbe_filter_info *filter_info =
8519                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8520         struct ixgbe_5tuple_filter *p_5tuple;
8521
8522         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8523                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8524 }
8525
8526 /* remove all the ether type filters */
8527 void
8528 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8529 {
8530         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8531         struct ixgbe_filter_info *filter_info =
8532                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8533         int i;
8534
8535         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8536                 if (filter_info->ethertype_mask & (1 << i) &&
8537                     !filter_info->ethertype_filters[i].conf) {
8538                         (void)ixgbe_ethertype_filter_remove(filter_info,
8539                                                             (uint8_t)i);
8540                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8541                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8542                         IXGBE_WRITE_FLUSH(hw);
8543                 }
8544         }
8545 }
8546
8547 /* remove the SYN filter */
8548 void
8549 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8550 {
8551         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8552         struct ixgbe_filter_info *filter_info =
8553                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8554
8555         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8556                 filter_info->syn_info = 0;
8557
8558                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8559                 IXGBE_WRITE_FLUSH(hw);
8560         }
8561 }
8562
8563 /* remove all the L2 tunnel filters */
8564 int
8565 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8566 {
8567         struct ixgbe_l2_tn_info *l2_tn_info =
8568                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8569         struct ixgbe_l2_tn_filter *l2_tn_filter;
8570         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8571         int ret = 0;
8572
8573         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8574                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8575                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8576                 l2_tn_conf.pool           = l2_tn_filter->pool;
8577                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8578                 if (ret < 0)
8579                         return ret;
8580         }
8581
8582         return 0;
8583 }
8584
8585 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8586 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8587 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8588 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8589 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8590 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8591
8592 RTE_INIT(ixgbe_init_log)
8593 {
8594         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8595         if (ixgbe_logtype_init >= 0)
8596                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8597         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8598         if (ixgbe_logtype_driver >= 0)
8599                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8600 }