drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define NSEC_PER_SEC             1000000000L
 130 #define IXGBE_INCVAL_10GB        0x66666666
 131 #define IXGBE_INCVAL_1GB         0x40000000
 132 #define IXGBE_INCVAL_100         0x50000000
 133 #define IXGBE_INCVAL_SHIFT_10GB  28
 134 #define IXGBE_INCVAL_SHIFT_1GB   24
 135 #define IXGBE_INCVAL_SHIFT_100   21
 136 #define IXGBE_INCVAL_SHIFT_82599 7
 137 #define IXGBE_INCPER_SHIFT_82599 24
 138
 139 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 143 #define DEFAULT_ETAG_ETYPE                     0x893f
 144 #define IXGBE_ETAG_ETYPE                       0x00005084
 145 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 146 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 147 #define IXGBE_RAH_ADTYPE                       0x40000000
 148 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 149 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 152 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 153
 154 enum ixgbevf_xcast_modes {
 155         IXGBEVF_XCAST_MODE_NONE = 0,
 156         IXGBEVF_XCAST_MODE_MULTI,
 157         IXGBEVF_XCAST_MODE_ALLMULTI,
 158 };
 159
 160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 162 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 163 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 164 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 165 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 166 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 167 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 168 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 169 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 171 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 172 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 173                                 int wait_to_complete);
 174 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 175                                 struct rte_eth_stats *stats);
 176 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 177                                 struct rte_eth_xstats *xstats, unsigned n);
 178 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 179                                   struct rte_eth_xstats *xstats, unsigned n);
 180 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 181 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 182 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 183                                              uint16_t queue_id,
 184                                              uint8_t stat_idx,
 185                                              uint8_t is_rx);
 186 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 187                                struct rte_eth_dev_info *dev_info);
 188 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                  struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 202 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 203 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 204 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 205 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 206
 207 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 208 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 209 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 210                                struct rte_eth_fc_conf *fc_conf);
 211 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 212                                struct rte_eth_fc_conf *fc_conf);
 213 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 214                 struct rte_eth_pfc_conf *pfc_conf);
 215 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 216                         struct rte_eth_rss_reta_entry64 *reta_conf,
 217                         uint16_t reta_size);
 218 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 222 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 223 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 224 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 226 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 227                 void *param);
 228 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 229 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 230                 uint32_t index, uint32_t pool);
 231 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 232 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 233                                            struct ether_addr *mac_addr);
 234 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 235
 236 /* For Virtual Function support */
 237 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 238 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 239 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 240 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 241 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 242 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 243 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 244 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 245 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 246                 struct rte_eth_stats *stats);
 247 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 248 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 249                 uint16_t vlan_id, int on);
 250 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 251                 uint16_t queue, int on);
 252 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 253 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 254 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 255                                             uint16_t queue_id);
 256 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 257                                              uint16_t queue_id);
 258 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 259                                  uint8_t queue, uint8_t msix_vector);
 260 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 261 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 262 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 263
 264 /* For Eth VMDQ APIs support */
 265 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 266                 ether_addr* mac_addr,uint8_t on);
 267 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 268 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 269                 uint16_t rx_mask, uint8_t on);
 270 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 271 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 272 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 273                 uint64_t pool_mask,uint8_t vlan_on);
 274 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 275                 struct rte_eth_mirror_conf *mirror_conf,
 276                 uint8_t rule_id, uint8_t on);
 277 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 278                 uint8_t rule_id);
 279 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 280                                           uint16_t queue_id);
 281 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 282                                            uint16_t queue_id);
 283 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 284                                uint8_t queue, uint8_t msix_vector);
 285 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 286
 287 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 288                 uint16_t queue_idx, uint16_t tx_rate);
 289 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 290                 uint16_t tx_rate, uint64_t q_msk);
 291
 292 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 293                                  struct ether_addr *mac_addr,
 294                                  uint32_t index, uint32_t pool);
 295 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 296 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 297                                              struct ether_addr *mac_addr);
 298 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 299                         struct rte_eth_syn_filter *filter,
 300                         bool add);
 301 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 302                         struct rte_eth_syn_filter *filter);
 303 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 304                         enum rte_filter_op filter_op,
 305                         void *arg);
 306 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 307                         struct ixgbe_5tuple_filter *filter);
 308 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 309                         struct ixgbe_5tuple_filter *filter);
 310 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 311                         struct rte_eth_ntuple_filter *filter,
 312                         bool add);
 313 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 314                                 enum rte_filter_op filter_op,
 315                                 void *arg);
 316 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 317                         struct rte_eth_ntuple_filter *filter);
 318 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 319                         struct rte_eth_ethertype_filter *filter,
 320                         bool add);
 321 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 322                                 enum rte_filter_op filter_op,
 323                                 void *arg);
 324 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 325                         struct rte_eth_ethertype_filter *filter);
 326 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 327                      enum rte_filter_type filter_type,
 328                      enum rte_filter_op filter_op,
 329                      void *arg);
 330 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 331
 332 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 333                                       struct ether_addr *mc_addr_set,
 334                                       uint32_t nb_mc_addr);
 335 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 336                                    struct rte_eth_dcb_info *dcb_info);
 337
 338 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 339 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 340                             struct rte_dev_reg_info *regs);
 341 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 342 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 343                                 struct rte_dev_eeprom_info *eeprom);
 344 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 345                                 struct rte_dev_eeprom_info *eeprom);
 346
 347 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 348 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 349                                 struct rte_dev_reg_info *regs);
 350
 351 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 352 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 354                                             struct timespec *timestamp,
 355                                             uint32_t flags);
 356 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 357                                             struct timespec *timestamp);
 358 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 359 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 360                                    struct timespec *timestamp);
 361 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 362                                    const struct timespec *timestamp);
 363
 364 static int ixgbe_dev_l2_tunnel_eth_type_conf
 365         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 366 static int ixgbe_dev_l2_tunnel_offload_set
 367         (struct rte_eth_dev *dev,
 368          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 369          uint32_t mask,
 370          uint8_t en);
 371 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 372                                              enum rte_filter_op filter_op,
 373                                              void *arg);
 374
 375 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 376                                          struct rte_eth_udp_tunnel *udp_tunnel);
 377 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379
 380 /*
 381  * Define VF Stats MACRO for Non "cleared on read" register
 382  */
 383 #define UPDATE_VF_STAT(reg, last, cur)                          \
 384 {                                                               \
 385         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 386         cur += (latest - last) & UINT_MAX;                      \
 387         last = latest;                                          \
 388 }
 389
 390 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 391 {                                                                \
 392         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 393         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 394         u64 latest = ((new_msb << 32) | new_lsb);                \
 395         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 396         last = latest;                                           \
 397 }
 398
 399 #define IXGBE_SET_HWSTRIP(h, q) do{\
 400                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 401                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 402                 (h)->bitmap[idx] |= 1 << bit;\
 403         } while (0)
 404
 405 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 406                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 407                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 408                 (h)->bitmap[idx] &= ~(1 << bit);\
 409         } while (0)
 410
 411 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 412                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 413                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 414                 (r) = (h)->bitmap[idx] >> bit & 1;\
 415         } while (0)
 416
 417 /*
 418  * The set of PCI devices this driver supports
 419  */
 420 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 421
 422 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 423 #include "rte_pci_dev_ids.h"
 424
 425 { .vendor_id = 0, /* sentinel */ },
 426 };
 427
 428
 429 /*
 430  * The set of PCI devices this driver supports (for 82599 VF)
 431  */
 432 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 433
 434 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 435 #include "rte_pci_dev_ids.h"
 436 { .vendor_id = 0, /* sentinel */ },
 437
 438 };
 439
 440 static const struct rte_eth_desc_lim rx_desc_lim = {
 441         .nb_max = IXGBE_MAX_RING_DESC,
 442         .nb_min = IXGBE_MIN_RING_DESC,
 443         .nb_align = IXGBE_RXD_ALIGN,
 444 };
 445
 446 static const struct rte_eth_desc_lim tx_desc_lim = {
 447         .nb_max = IXGBE_MAX_RING_DESC,
 448         .nb_min = IXGBE_MIN_RING_DESC,
 449         .nb_align = IXGBE_TXD_ALIGN,
 450 };
 451
 452 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 453         .dev_configure        = ixgbe_dev_configure,
 454         .dev_start            = ixgbe_dev_start,
 455         .dev_stop             = ixgbe_dev_stop,
 456         .dev_set_link_up    = ixgbe_dev_set_link_up,
 457         .dev_set_link_down  = ixgbe_dev_set_link_down,
 458         .dev_close            = ixgbe_dev_close,
 459         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 460         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 461         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 462         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 463         .link_update          = ixgbe_dev_link_update,
 464         .stats_get            = ixgbe_dev_stats_get,
 465         .xstats_get           = ixgbe_dev_xstats_get,
 466         .stats_reset          = ixgbe_dev_stats_reset,
 467         .xstats_reset         = ixgbe_dev_xstats_reset,
 468         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 469         .dev_infos_get        = ixgbe_dev_info_get,
 470         .mtu_set              = ixgbe_dev_mtu_set,
 471         .vlan_filter_set      = ixgbe_vlan_filter_set,
 472         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 473         .vlan_offload_set     = ixgbe_vlan_offload_set,
 474         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 475         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 476         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 477         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 478         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 479         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 480         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 481         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 482         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 483         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 484         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 485         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 486         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 487         .dev_led_on           = ixgbe_dev_led_on,
 488         .dev_led_off          = ixgbe_dev_led_off,
 489         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 490         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 491         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 492         .mac_addr_add         = ixgbe_add_rar,
 493         .mac_addr_remove      = ixgbe_remove_rar,
 494         .mac_addr_set         = ixgbe_set_default_mac_addr,
 495         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 496         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 497         .mirror_rule_set      = ixgbe_mirror_rule_set,
 498         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 499         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 500         .set_vf_rx            = ixgbe_set_pool_rx,
 501         .set_vf_tx            = ixgbe_set_pool_tx,
 502         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 503         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 504         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 505         .reta_update          = ixgbe_dev_rss_reta_update,
 506         .reta_query           = ixgbe_dev_rss_reta_query,
 507 #ifdef RTE_NIC_BYPASS
 508         .bypass_init          = ixgbe_bypass_init,
 509         .bypass_state_set     = ixgbe_bypass_state_store,
 510         .bypass_state_show    = ixgbe_bypass_state_show,
 511         .bypass_event_set     = ixgbe_bypass_event_store,
 512         .bypass_event_show    = ixgbe_bypass_event_show,
 513         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 514         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 515         .bypass_ver_show      = ixgbe_bypass_ver_show,
 516         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 517 #endif /* RTE_NIC_BYPASS */
 518         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 519         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 520         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 521         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 522         .rxq_info_get         = ixgbe_rxq_info_get,
 523         .txq_info_get         = ixgbe_txq_info_get,
 524         .timesync_enable      = ixgbe_timesync_enable,
 525         .timesync_disable     = ixgbe_timesync_disable,
 526         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 527         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 528         .get_reg_length       = ixgbe_get_reg_length,
 529         .get_reg              = ixgbe_get_regs,
 530         .get_eeprom_length    = ixgbe_get_eeprom_length,
 531         .get_eeprom           = ixgbe_get_eeprom,
 532         .set_eeprom           = ixgbe_set_eeprom,
 533         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 534         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 535         .timesync_read_time   = ixgbe_timesync_read_time,
 536         .timesync_write_time  = ixgbe_timesync_write_time,
 537         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 538         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 539         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 540         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 541 };
 542
 543 /*
 544  * dev_ops for virtual function, bare necessities for basic vf
 545  * operation have been implemented
 546  */
 547 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 548         .dev_configure        = ixgbevf_dev_configure,
 549         .dev_start            = ixgbevf_dev_start,
 550         .dev_stop             = ixgbevf_dev_stop,
 551         .link_update          = ixgbe_dev_link_update,
 552         .stats_get            = ixgbevf_dev_stats_get,
 553         .xstats_get           = ixgbevf_dev_xstats_get,
 554         .stats_reset          = ixgbevf_dev_stats_reset,
 555         .xstats_reset         = ixgbevf_dev_stats_reset,
 556         .dev_close            = ixgbevf_dev_close,
 557         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 558         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 559         .dev_infos_get        = ixgbevf_dev_info_get,
 560         .mtu_set              = ixgbevf_dev_set_mtu,
 561         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 562         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 563         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 564         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 565         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 566         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 567         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 568         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 569         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 570         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 571         .mac_addr_add         = ixgbevf_add_mac_addr,
 572         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 573         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 574         .rxq_info_get         = ixgbe_rxq_info_get,
 575         .txq_info_get         = ixgbe_txq_info_get,
 576         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 577         .get_reg_length       = ixgbevf_get_reg_length,
 578         .get_reg              = ixgbevf_get_regs,
 579         .reta_update          = ixgbe_dev_rss_reta_update,
 580         .reta_query           = ixgbe_dev_rss_reta_query,
 581         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 582         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 583 };
 584
 585 /* store statistics names and its offset in stats structure */
 586 struct rte_ixgbe_xstats_name_off {
 587         char name[RTE_ETH_XSTATS_NAME_SIZE];
 588         unsigned offset;
 589 };
 590
 591 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 592         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 593         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 594         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 595         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 596         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 597         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 598         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 599         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 600         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 601         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 602         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 603         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 604         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 605         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 606         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 607                 prc1023)},
 608         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 609                 prc1522)},
 610         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 611         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 612         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 613         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 614         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 615         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 616         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 617         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 618         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 619         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 620         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 621         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 622         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 623         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 624         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 625         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 626         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 627                 ptc1023)},
 628         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 629                 ptc1522)},
 630         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 631         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 632         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 633         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 634
 635         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 636                 fdirustat_add)},
 637         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 638                 fdirustat_remove)},
 639         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 640                 fdirfstat_fadd)},
 641         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 642                 fdirfstat_fremove)},
 643         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 644                 fdirmatch)},
 645         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 646                 fdirmiss)},
 647
 648         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 649         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 650         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 651                 fclast)},
 652         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 653         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 654         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 655         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 656         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 657                 fcoe_noddp)},
 658         {"rx_fcoe_no_direct_data_placement_ext_buff",
 659                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 660
 661         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 662                 lxontxc)},
 663         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 664                 lxonrxc)},
 665         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 666                 lxofftxc)},
 667         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 668                 lxoffrxc)},
 669         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 670 };
 671
 672 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 673                            sizeof(rte_ixgbe_stats_strings[0]))
 674
 675 /* Per-queue statistics */
 676 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 677         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 678         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 679         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 680         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 681 };
 682
 683 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 684                            sizeof(rte_ixgbe_rxq_strings[0]))
 685
 686 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 687         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 688         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 689         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 690                 pxon2offc)},
 691 };
 692
 693 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 694                            sizeof(rte_ixgbe_txq_strings[0]))
 695
 696 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 697         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 698 };
 699
 700 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 701                 sizeof(rte_ixgbevf_stats_strings[0]))
 702
 703 /**
 704  * Atomically reads the link status information from global
 705  * structure rte_eth_dev.
 706  *
 707  * @param dev
 708  *   - Pointer to the structure rte_eth_dev to read from.
 709  *   - Pointer to the buffer to be saved with the link status.
 710  *
 711  * @return
 712  *   - On success, zero.
 713  *   - On failure, negative value.
 714  */
 715 static inline int
 716 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 717                                 struct rte_eth_link *link)
 718 {
 719         struct rte_eth_link *dst = link;
 720         struct rte_eth_link *src = &(dev->data->dev_link);
 721
 722         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 723                                         *(uint64_t *)src) == 0)
 724                 return -1;
 725
 726         return 0;
 727 }
 728
 729 /**
 730  * Atomically writes the link status information into global
 731  * structure rte_eth_dev.
 732  *
 733  * @param dev
 734  *   - Pointer to the structure rte_eth_dev to read from.
 735  *   - Pointer to the buffer to be saved with the link status.
 736  *
 737  * @return
 738  *   - On success, zero.
 739  *   - On failure, negative value.
 740  */
 741 static inline int
 742 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 743                                 struct rte_eth_link *link)
 744 {
 745         struct rte_eth_link *dst = &(dev->data->dev_link);
 746         struct rte_eth_link *src = link;
 747
 748         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 749                                         *(uint64_t *)src) == 0)
 750                 return -1;
 751
 752         return 0;
 753 }
 754
 755 /*
 756  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 757  */
 758 static inline int
 759 ixgbe_is_sfp(struct ixgbe_hw *hw)
 760 {
 761         switch (hw->phy.type) {
 762         case ixgbe_phy_sfp_avago:
 763         case ixgbe_phy_sfp_ftl:
 764         case ixgbe_phy_sfp_intel:
 765         case ixgbe_phy_sfp_unknown:
 766         case ixgbe_phy_sfp_passive_tyco:
 767         case ixgbe_phy_sfp_passive_unknown:
 768                 return 1;
 769         default:
 770                 return 0;
 771         }
 772 }
 773
 774 static inline int32_t
 775 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 776 {
 777         uint32_t ctrl_ext;
 778         int32_t status;
 779
 780         status = ixgbe_reset_hw(hw);
 781
 782         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 783         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 784         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 785         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 786         IXGBE_WRITE_FLUSH(hw);
 787
 788         return status;
 789 }
 790
 791 static inline void
 792 ixgbe_enable_intr(struct rte_eth_dev *dev)
 793 {
 794         struct ixgbe_interrupt *intr =
 795                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 796         struct ixgbe_hw *hw =
 797                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 798
 799         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 800         IXGBE_WRITE_FLUSH(hw);
 801 }
 802
 803 /*
 804  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 805  */
 806 static void
 807 ixgbe_disable_intr(struct ixgbe_hw *hw)
 808 {
 809         PMD_INIT_FUNC_TRACE();
 810
 811         if (hw->mac.type == ixgbe_mac_82598EB) {
 812                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 813         } else {
 814                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 815                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 816                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 817         }
 818         IXGBE_WRITE_FLUSH(hw);
 819 }
 820
 821 /*
 822  * This function resets queue statistics mapping registers.
 823  * From Niantic datasheet, Initialization of Statistics section:
 824  * "...if software requires the queue counters, the RQSMR and TQSM registers
 825  * must be re-programmed following a device reset.
 826  */
 827 static void
 828 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 829 {
 830         uint32_t i;
 831
 832         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 833                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 834                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 835         }
 836 }
 837
 838
 839 static int
 840 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 841                                   uint16_t queue_id,
 842                                   uint8_t stat_idx,
 843                                   uint8_t is_rx)
 844 {
 845 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 846 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 847 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 848
 849         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 850         struct ixgbe_stat_mapping_registers *stat_mappings =
 851                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 852         uint32_t qsmr_mask = 0;
 853         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 854         uint32_t q_map;
 855         uint8_t n, offset;
 856
 857         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 858                 (hw->mac.type != ixgbe_mac_X540) &&
 859                 (hw->mac.type != ixgbe_mac_X550) &&
 860                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 861                 (hw->mac.type != ixgbe_mac_X550EM_a))
 862                 return -ENOSYS;
 863
 864         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 865                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 866                      queue_id, stat_idx);
 867
 868         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 869         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 870                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 871                 return -EIO;
 872         }
 873         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 874
 875         /* Now clear any previous stat_idx set */
 876         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 877         if (!is_rx)
 878                 stat_mappings->tqsm[n] &= ~clearing_mask;
 879         else
 880                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 881
 882         q_map = (uint32_t)stat_idx;
 883         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 884         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 885         if (!is_rx)
 886                 stat_mappings->tqsm[n] |= qsmr_mask;
 887         else
 888                 stat_mappings->rqsmr[n] |= qsmr_mask;
 889
 890         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 891                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 892                      queue_id, stat_idx);
 893         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 894                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 895
 896         /* Now write the mapping in the appropriate register */
 897         if (is_rx) {
 898                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 899                              stat_mappings->rqsmr[n], n);
 900                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 901         }
 902         else {
 903                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 904                              stat_mappings->tqsm[n], n);
 905                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 906         }
 907         return 0;
 908 }
 909
 910 static void
 911 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 912 {
 913         struct ixgbe_stat_mapping_registers *stat_mappings =
 914                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 915         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 916         int i;
 917
 918         /* write whatever was in stat mapping table to the NIC */
 919         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 920                 /* rx */
 921                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 922
 923                 /* tx */
 924                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 925         }
 926 }
 927
 928 static void
 929 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 930 {
 931         uint8_t i;
 932         struct ixgbe_dcb_tc_config *tc;
 933         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 934
 935         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 936         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 937         for (i = 0; i < dcb_max_tc; i++) {
 938                 tc = &dcb_config->tc_config[i];
 939                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 940                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 941                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 942                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 943                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 944                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 945                 tc->pfc = ixgbe_dcb_pfc_disabled;
 946         }
 947
 948         /* Initialize default user to priority mapping, UPx->TC0 */
 949         tc = &dcb_config->tc_config[0];
 950         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 951         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 952         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 953                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 954                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 955         }
 956         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 957         dcb_config->pfc_mode_enable = false;
 958         dcb_config->vt_mode = true;
 959         dcb_config->round_robin_enable = false;
 960         /* support all DCB capabilities in 82599 */
 961         dcb_config->support.capabilities = 0xFF;
 962
 963         /*we only support 4 Tcs for X540, X550 */
 964         if (hw->mac.type == ixgbe_mac_X540 ||
 965                 hw->mac.type == ixgbe_mac_X550 ||
 966                 hw->mac.type == ixgbe_mac_X550EM_x ||
 967                 hw->mac.type == ixgbe_mac_X550EM_a) {
 968                 dcb_config->num_tcs.pg_tcs = 4;
 969                 dcb_config->num_tcs.pfc_tcs = 4;
 970         }
 971 }
 972
 973 /*
 974  * Ensure that all locks are released before first NVM or PHY access
 975  */
 976 static void
 977 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 978 {
 979         uint16_t mask;
 980
 981         /*
 982          * Phy lock should not fail in this early stage. If this is the case,
 983          * it is due to an improper exit of the application.
 984          * So force the release of the faulty lock. Release of common lock
 985          * is done automatically by swfw_sync function.
 986          */
 987         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 988         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 989                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 990         }
 991         ixgbe_release_swfw_semaphore(hw, mask);
 992
 993         /*
 994          * These ones are more tricky since they are common to all ports; but
 995          * swfw_sync retries last long enough (1s) to be almost sure that if
 996          * lock can not be taken it is due to an improper lock of the
 997          * semaphore.
 998          */
 999         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1000         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1001                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1002         }
1003         ixgbe_release_swfw_semaphore(hw, mask);
1004 }
1005
1006 /*
1007  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1008  * It returns 0 on success.
1009  */
1010 static int
1011 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1012 {
1013         struct rte_pci_device *pci_dev;
1014         struct ixgbe_hw *hw =
1015                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1016         struct ixgbe_vfta * shadow_vfta =
1017                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1018         struct ixgbe_hwstrip *hwstrip =
1019                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1020         struct ixgbe_dcb_config *dcb_config =
1021                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1022         struct ixgbe_filter_info *filter_info =
1023                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1024         uint32_t ctrl_ext;
1025         uint16_t csum;
1026         int diag, i;
1027
1028         PMD_INIT_FUNC_TRACE();
1029
1030         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1031         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1032         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1033
1034         /*
1035          * For secondary processes, we don't initialise any further as primary
1036          * has already done this work. Only check we don't need a different
1037          * RX and TX function.
1038          */
1039         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1040                 struct ixgbe_tx_queue *txq;
1041                 /* TX queue function in primary, set by last queue initialized
1042                  * Tx queue may not initialized by primary process */
1043                 if (eth_dev->data->tx_queues) {
1044                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1045                         ixgbe_set_tx_function(eth_dev, txq);
1046                 } else {
1047                         /* Use default TX function if we get here */
1048                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1049                                              "Using default TX function.");
1050                 }
1051
1052                 ixgbe_set_rx_function(eth_dev);
1053
1054                 return 0;
1055         }
1056         pci_dev = eth_dev->pci_dev;
1057
1058         rte_eth_copy_pci_info(eth_dev, pci_dev);
1059
1060         /* Vendor and Device ID need to be set before init of shared code */
1061         hw->device_id = pci_dev->id.device_id;
1062         hw->vendor_id = pci_dev->id.vendor_id;
1063         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1064         hw->allow_unsupported_sfp = 1;
1065
1066         /* Initialize the shared code (base driver) */
1067 #ifdef RTE_NIC_BYPASS
1068         diag = ixgbe_bypass_init_shared_code(hw);
1069 #else
1070         diag = ixgbe_init_shared_code(hw);
1071 #endif /* RTE_NIC_BYPASS */
1072
1073         if (diag != IXGBE_SUCCESS) {
1074                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1075                 return -EIO;
1076         }
1077
1078         /* pick up the PCI bus settings for reporting later */
1079         ixgbe_get_bus_info(hw);
1080
1081         /* Unlock any pending hardware semaphore */
1082         ixgbe_swfw_lock_reset(hw);
1083
1084         /* Initialize DCB configuration*/
1085         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1086         ixgbe_dcb_init(hw,dcb_config);
1087         /* Get Hardware Flow Control setting */
1088         hw->fc.requested_mode = ixgbe_fc_full;
1089         hw->fc.current_mode = ixgbe_fc_full;
1090         hw->fc.pause_time = IXGBE_FC_PAUSE;
1091         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1092                 hw->fc.low_water[i] = IXGBE_FC_LO;
1093                 hw->fc.high_water[i] = IXGBE_FC_HI;
1094         }
1095         hw->fc.send_xon = 1;
1096
1097         /* Make sure we have a good EEPROM before we read from it */
1098         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1099         if (diag != IXGBE_SUCCESS) {
1100                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1101                 return -EIO;
1102         }
1103
1104 #ifdef RTE_NIC_BYPASS
1105         diag = ixgbe_bypass_init_hw(hw);
1106 #else
1107         diag = ixgbe_init_hw(hw);
1108 #endif /* RTE_NIC_BYPASS */
1109
1110         /*
1111          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1112          * is called too soon after the kernel driver unbinding/binding occurs.
1113          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1114          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1115          * also called. See ixgbe_identify_phy_82599(). The reason for the
1116          * failure is not known, and only occuts when virtualisation features
1117          * are disabled in the bios. A delay of 100ms  was found to be enough by
1118          * trial-and-error, and is doubled to be safe.
1119          */
1120         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1121                 rte_delay_ms(200);
1122                 diag = ixgbe_init_hw(hw);
1123         }
1124
1125         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1126                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1127                     "LOM.  Please be aware there may be issues associated "
1128                     "with your hardware.");
1129                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1130                     "please contact your Intel or hardware representative "
1131                     "who provided you with this hardware.");
1132         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1133                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1134         if (diag) {
1135                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1136                 return -EIO;
1137         }
1138
1139         /* Reset the hw statistics */
1140         ixgbe_dev_stats_reset(eth_dev);
1141
1142         /* disable interrupt */
1143         ixgbe_disable_intr(hw);
1144
1145         /* reset mappings for queue statistics hw counters*/
1146         ixgbe_reset_qstat_mappings(hw);
1147
1148         /* Allocate memory for storing MAC addresses */
1149         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1150                         hw->mac.num_rar_entries, 0);
1151         if (eth_dev->data->mac_addrs == NULL) {
1152                 PMD_INIT_LOG(ERR,
1153                         "Failed to allocate %u bytes needed to store "
1154                         "MAC addresses",
1155                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1156                 return -ENOMEM;
1157         }
1158         /* Copy the permanent MAC address */
1159         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1160                         &eth_dev->data->mac_addrs[0]);
1161
1162         /* Allocate memory for storing hash filter MAC addresses */
1163         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1164                         IXGBE_VMDQ_NUM_UC_MAC, 0);
1165         if (eth_dev->data->hash_mac_addrs == NULL) {
1166                 PMD_INIT_LOG(ERR,
1167                         "Failed to allocate %d bytes needed to store MAC addresses",
1168                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1169                 return -ENOMEM;
1170         }
1171
1172         /* initialize the vfta */
1173         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1174
1175         /* initialize the hw strip bitmap*/
1176         memset(hwstrip, 0, sizeof(*hwstrip));
1177
1178         /* initialize PF if max_vfs not zero */
1179         ixgbe_pf_host_init(eth_dev);
1180
1181         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1182         /* let hardware know driver is loaded */
1183         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1184         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1185         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1186         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1187         IXGBE_WRITE_FLUSH(hw);
1188
1189         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1190                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1191                              (int) hw->mac.type, (int) hw->phy.type,
1192                              (int) hw->phy.sfp_type);
1193         else
1194                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1195                              (int) hw->mac.type, (int) hw->phy.type);
1196
1197         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1198                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1199                         pci_dev->id.device_id);
1200
1201         rte_intr_callback_register(&pci_dev->intr_handle,
1202                                    ixgbe_dev_interrupt_handler,
1203                                    (void *)eth_dev);
1204
1205         /* enable uio/vfio intr/eventfd mapping */
1206         rte_intr_enable(&pci_dev->intr_handle);
1207
1208         /* enable support intr */
1209         ixgbe_enable_intr(eth_dev);
1210
1211         /* initialize 5tuple filter list */
1212         TAILQ_INIT(&filter_info->fivetuple_list);
1213         memset(filter_info->fivetuple_mask, 0,
1214                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1215
1216         return 0;
1217 }
1218
1219 static int
1220 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1221 {
1222         struct rte_pci_device *pci_dev;
1223         struct ixgbe_hw *hw;
1224
1225         PMD_INIT_FUNC_TRACE();
1226
1227         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1228                 return -EPERM;
1229
1230         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1231         pci_dev = eth_dev->pci_dev;
1232
1233         if (hw->adapter_stopped == 0)
1234                 ixgbe_dev_close(eth_dev);
1235
1236         eth_dev->dev_ops = NULL;
1237         eth_dev->rx_pkt_burst = NULL;
1238         eth_dev->tx_pkt_burst = NULL;
1239
1240         /* Unlock any pending hardware semaphore */
1241         ixgbe_swfw_lock_reset(hw);
1242
1243         /* disable uio intr before callback unregister */
1244         rte_intr_disable(&(pci_dev->intr_handle));
1245         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1246                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1247
1248         /* uninitialize PF if max_vfs not zero */
1249         ixgbe_pf_host_uninit(eth_dev);
1250
1251         rte_free(eth_dev->data->mac_addrs);
1252         eth_dev->data->mac_addrs = NULL;
1253
1254         rte_free(eth_dev->data->hash_mac_addrs);
1255         eth_dev->data->hash_mac_addrs = NULL;
1256
1257         return 0;
1258 }
1259
1260 /*
1261  * Negotiate mailbox API version with the PF.
1262  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1263  * Then we try to negotiate starting with the most recent one.
1264  * If all negotiation attempts fail, then we will proceed with
1265  * the default one (ixgbe_mbox_api_10).
1266  */
1267 static void
1268 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1269 {
1270         int32_t i;
1271
1272         /* start with highest supported, proceed down */
1273         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1274                 ixgbe_mbox_api_12,
1275                 ixgbe_mbox_api_11,
1276                 ixgbe_mbox_api_10,
1277         };
1278
1279         for (i = 0;
1280                         i != RTE_DIM(sup_ver) &&
1281                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1282                         i++)
1283                 ;
1284 }
1285
1286 static void
1287 generate_random_mac_addr(struct ether_addr *mac_addr)
1288 {
1289         uint64_t random;
1290
1291         /* Set Organizationally Unique Identifier (OUI) prefix. */
1292         mac_addr->addr_bytes[0] = 0x00;
1293         mac_addr->addr_bytes[1] = 0x09;
1294         mac_addr->addr_bytes[2] = 0xC0;
1295         /* Force indication of locally assigned MAC address. */
1296         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1297         /* Generate the last 3 bytes of the MAC address with a random number. */
1298         random = rte_rand();
1299         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1300 }
1301
1302 /*
1303  * Virtual Function device init
1304  */
1305 static int
1306 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1307 {
1308         int diag;
1309         uint32_t tc, tcs;
1310         struct rte_pci_device *pci_dev;
1311         struct ixgbe_hw *hw =
1312                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1313         struct ixgbe_vfta * shadow_vfta =
1314                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1315         struct ixgbe_hwstrip *hwstrip =
1316                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1317         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1318
1319         PMD_INIT_FUNC_TRACE();
1320
1321         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1322         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1323         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1324
1325         /* for secondary processes, we don't initialise any further as primary
1326          * has already done this work. Only check we don't need a different
1327          * RX function */
1328         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1329                 struct ixgbe_tx_queue *txq;
1330                 /* TX queue function in primary, set by last queue initialized
1331                  * Tx queue may not initialized by primary process
1332                  */
1333                 if (eth_dev->data->tx_queues) {
1334                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1335                         ixgbe_set_tx_function(eth_dev, txq);
1336                 } else {
1337                         /* Use default TX function if we get here */
1338                         PMD_INIT_LOG(NOTICE,
1339                                 "No TX queues configured yet. Using default TX function.");
1340                 }
1341
1342                 ixgbe_set_rx_function(eth_dev);
1343
1344                 return 0;
1345         }
1346
1347         pci_dev = eth_dev->pci_dev;
1348
1349         rte_eth_copy_pci_info(eth_dev, pci_dev);
1350
1351         hw->device_id = pci_dev->id.device_id;
1352         hw->vendor_id = pci_dev->id.vendor_id;
1353         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1354
1355         /* initialize the vfta */
1356         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1357
1358         /* initialize the hw strip bitmap*/
1359         memset(hwstrip, 0, sizeof(*hwstrip));
1360
1361         /* Initialize the shared code (base driver) */
1362         diag = ixgbe_init_shared_code(hw);
1363         if (diag != IXGBE_SUCCESS) {
1364                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1365                 return -EIO;
1366         }
1367
1368         /* init_mailbox_params */
1369         hw->mbx.ops.init_params(hw);
1370
1371         /* Reset the hw statistics */
1372         ixgbevf_dev_stats_reset(eth_dev);
1373
1374         /* Disable the interrupts for VF */
1375         ixgbevf_intr_disable(hw);
1376
1377         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1378         diag = hw->mac.ops.reset_hw(hw);
1379
1380         /*
1381          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1382          * the underlying PF driver has not assigned a MAC address to the VF.
1383          * In this case, assign a random MAC address.
1384          */
1385         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1386                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1387                 return diag;
1388         }
1389
1390         /* negotiate mailbox API version to use with the PF. */
1391         ixgbevf_negotiate_api(hw);
1392
1393         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1394         ixgbevf_get_queues(hw, &tcs, &tc);
1395
1396         /* Allocate memory for storing MAC addresses */
1397         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1398                         hw->mac.num_rar_entries, 0);
1399         if (eth_dev->data->mac_addrs == NULL) {
1400                 PMD_INIT_LOG(ERR,
1401                         "Failed to allocate %u bytes needed to store "
1402                         "MAC addresses",
1403                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1404                 return -ENOMEM;
1405         }
1406
1407         /* Generate a random MAC address, if none was assigned by PF. */
1408         if (is_zero_ether_addr(perm_addr)) {
1409                 generate_random_mac_addr(perm_addr);
1410                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1411                 if (diag) {
1412                         rte_free(eth_dev->data->mac_addrs);
1413                         eth_dev->data->mac_addrs = NULL;
1414                         return diag;
1415                 }
1416                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1417                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1418                              "%02x:%02x:%02x:%02x:%02x:%02x",
1419                              perm_addr->addr_bytes[0],
1420                              perm_addr->addr_bytes[1],
1421                              perm_addr->addr_bytes[2],
1422                              perm_addr->addr_bytes[3],
1423                              perm_addr->addr_bytes[4],
1424                              perm_addr->addr_bytes[5]);
1425         }
1426
1427         /* Copy the permanent MAC address */
1428         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1429
1430         /* reset the hardware with the new settings */
1431         diag = hw->mac.ops.start_hw(hw);
1432         switch (diag) {
1433                 case  0:
1434                         break;
1435
1436                 default:
1437                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1438                         return -EIO;
1439         }
1440
1441         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1442                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1443                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1444
1445         return 0;
1446 }
1447
1448 /* Virtual Function device uninit */
1449
1450 static int
1451 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1452 {
1453         struct ixgbe_hw *hw;
1454
1455         PMD_INIT_FUNC_TRACE();
1456
1457         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1458                 return -EPERM;
1459
1460         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1461
1462         if (hw->adapter_stopped == 0)
1463                 ixgbevf_dev_close(eth_dev);
1464
1465         eth_dev->dev_ops = NULL;
1466         eth_dev->rx_pkt_burst = NULL;
1467         eth_dev->tx_pkt_burst = NULL;
1468
1469         /* Disable the interrupts for VF */
1470         ixgbevf_intr_disable(hw);
1471
1472         rte_free(eth_dev->data->mac_addrs);
1473         eth_dev->data->mac_addrs = NULL;
1474
1475         return 0;
1476 }
1477
1478 static struct eth_driver rte_ixgbe_pmd = {
1479         .pci_drv = {
1480                 .name = "rte_ixgbe_pmd",
1481                 .id_table = pci_id_ixgbe_map,
1482                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1483                         RTE_PCI_DRV_DETACHABLE,
1484         },
1485         .eth_dev_init = eth_ixgbe_dev_init,
1486         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1487         .dev_private_size = sizeof(struct ixgbe_adapter),
1488 };
1489
1490 /*
1491  * virtual function driver struct
1492  */
1493 static struct eth_driver rte_ixgbevf_pmd = {
1494         .pci_drv = {
1495                 .name = "rte_ixgbevf_pmd",
1496                 .id_table = pci_id_ixgbevf_map,
1497                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1498         },
1499         .eth_dev_init = eth_ixgbevf_dev_init,
1500         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1501         .dev_private_size = sizeof(struct ixgbe_adapter),
1502 };
1503
1504 /*
1505  * Driver initialization routine.
1506  * Invoked once at EAL init time.
1507  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1508  */
1509 static int
1510 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1511 {
1512         PMD_INIT_FUNC_TRACE();
1513
1514         rte_eth_driver_register(&rte_ixgbe_pmd);
1515         return 0;
1516 }
1517
1518 /*
1519  * VF Driver initialization routine.
1520  * Invoked one at EAL init time.
1521  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1522  */
1523 static int
1524 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1525 {
1526         PMD_INIT_FUNC_TRACE();
1527
1528         rte_eth_driver_register(&rte_ixgbevf_pmd);
1529         return 0;
1530 }
1531
1532 static int
1533 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1534 {
1535         struct ixgbe_hw *hw =
1536                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1537         struct ixgbe_vfta * shadow_vfta =
1538                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1539         uint32_t vfta;
1540         uint32_t vid_idx;
1541         uint32_t vid_bit;
1542
1543         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1544         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1545         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1546         if (on)
1547                 vfta |= vid_bit;
1548         else
1549                 vfta &= ~vid_bit;
1550         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1551
1552         /* update local VFTA copy */
1553         shadow_vfta->vfta[vid_idx] = vfta;
1554
1555         return 0;
1556 }
1557
1558 static void
1559 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1560 {
1561         if (on)
1562                 ixgbe_vlan_hw_strip_enable(dev, queue);
1563         else
1564                 ixgbe_vlan_hw_strip_disable(dev, queue);
1565 }
1566
1567 static int
1568 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1569                     enum rte_vlan_type vlan_type,
1570                     uint16_t tpid)
1571 {
1572         struct ixgbe_hw *hw =
1573                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1574         int ret = 0;
1575
1576         switch (vlan_type) {
1577         case ETH_VLAN_TYPE_INNER:
1578                 /* Only the high 16-bits is valid */
1579                 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1580                 break;
1581         default:
1582                 ret = -EINVAL;
1583                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
1584                 break;
1585         }
1586
1587         return ret;
1588 }
1589
1590 void
1591 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1592 {
1593         struct ixgbe_hw *hw =
1594                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1595         uint32_t vlnctrl;
1596
1597         PMD_INIT_FUNC_TRACE();
1598
1599         /* Filter Table Disable */
1600         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1601         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1602
1603         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1604 }
1605
1606 void
1607 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1608 {
1609         struct ixgbe_hw *hw =
1610                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1611         struct ixgbe_vfta * shadow_vfta =
1612                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1613         uint32_t vlnctrl;
1614         uint16_t i;
1615
1616         PMD_INIT_FUNC_TRACE();
1617
1618         /* Filter Table Enable */
1619         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1620         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1621         vlnctrl |= IXGBE_VLNCTRL_VFE;
1622
1623         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1624
1625         /* write whatever is in local vfta copy */
1626         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1627                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1628 }
1629
1630 static void
1631 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1632 {
1633         struct ixgbe_hwstrip *hwstrip =
1634                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1635
1636         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1637                 return;
1638
1639         if (on)
1640                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1641         else
1642                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1643 }
1644
1645 static void
1646 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1647 {
1648         struct ixgbe_hw *hw =
1649                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1650         uint32_t ctrl;
1651
1652         PMD_INIT_FUNC_TRACE();
1653
1654         if (hw->mac.type == ixgbe_mac_82598EB) {
1655                 /* No queue level support */
1656                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1657                 return;
1658         }
1659         else {
1660                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1661                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1662                 ctrl &= ~IXGBE_RXDCTL_VME;
1663                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1664         }
1665         /* record those setting for HW strip per queue */
1666         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1667 }
1668
1669 static void
1670 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1671 {
1672         struct ixgbe_hw *hw =
1673                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1674         uint32_t ctrl;
1675
1676         PMD_INIT_FUNC_TRACE();
1677
1678         if (hw->mac.type == ixgbe_mac_82598EB) {
1679                 /* No queue level supported */
1680                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1681                 return;
1682         }
1683         else {
1684                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1685                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1686                 ctrl |= IXGBE_RXDCTL_VME;
1687                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1688         }
1689         /* record those setting for HW strip per queue */
1690         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1691 }
1692
1693 void
1694 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1695 {
1696         struct ixgbe_hw *hw =
1697                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1698         uint32_t ctrl;
1699         uint16_t i;
1700
1701         PMD_INIT_FUNC_TRACE();
1702
1703         if (hw->mac.type == ixgbe_mac_82598EB) {
1704                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1705                 ctrl &= ~IXGBE_VLNCTRL_VME;
1706                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1707         }
1708         else {
1709                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1710                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1711                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1712                         ctrl &= ~IXGBE_RXDCTL_VME;
1713                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1714
1715                         /* record those setting for HW strip per queue */
1716                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1717                 }
1718         }
1719 }
1720
1721 void
1722 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1723 {
1724         struct ixgbe_hw *hw =
1725                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1726         uint32_t ctrl;
1727         uint16_t i;
1728
1729         PMD_INIT_FUNC_TRACE();
1730
1731         if (hw->mac.type == ixgbe_mac_82598EB) {
1732                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1733                 ctrl |= IXGBE_VLNCTRL_VME;
1734                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1735         }
1736         else {
1737                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1738                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1739                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1740                         ctrl |= IXGBE_RXDCTL_VME;
1741                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1742
1743                         /* record those setting for HW strip per queue */
1744                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1745                 }
1746         }
1747 }
1748
1749 static void
1750 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1751 {
1752         struct ixgbe_hw *hw =
1753                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1754         uint32_t ctrl;
1755
1756         PMD_INIT_FUNC_TRACE();
1757
1758         /* DMATXCTRL: Geric Double VLAN Disable */
1759         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1760         ctrl &= ~IXGBE_DMATXCTL_GDV;
1761         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1762
1763         /* CTRL_EXT: Global Double VLAN Disable */
1764         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1765         ctrl &= ~IXGBE_EXTENDED_VLAN;
1766         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1767
1768 }
1769
1770 static void
1771 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1772 {
1773         struct ixgbe_hw *hw =
1774                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1775         uint32_t ctrl;
1776
1777         PMD_INIT_FUNC_TRACE();
1778
1779         /* DMATXCTRL: Geric Double VLAN Enable */
1780         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1781         ctrl |= IXGBE_DMATXCTL_GDV;
1782         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1783
1784         /* CTRL_EXT: Global Double VLAN Enable */
1785         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1786         ctrl |= IXGBE_EXTENDED_VLAN;
1787         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1788
1789         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1790         if (hw->mac.type == ixgbe_mac_X550 ||
1791             hw->mac.type == ixgbe_mac_X550EM_x) {
1792                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1793                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1794                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1795         }
1796
1797         /*
1798          * VET EXT field in the EXVET register = 0x8100 by default
1799          * So no need to change. Same to VT field of DMATXCTL register
1800          */
1801 }
1802
1803 static void
1804 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1805 {
1806         if (mask & ETH_VLAN_STRIP_MASK) {
1807                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1808                         ixgbe_vlan_hw_strip_enable_all(dev);
1809                 else
1810                         ixgbe_vlan_hw_strip_disable_all(dev);
1811         }
1812
1813         if (mask & ETH_VLAN_FILTER_MASK) {
1814                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1815                         ixgbe_vlan_hw_filter_enable(dev);
1816                 else
1817                         ixgbe_vlan_hw_filter_disable(dev);
1818         }
1819
1820         if (mask & ETH_VLAN_EXTEND_MASK) {
1821                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1822                         ixgbe_vlan_hw_extend_enable(dev);
1823                 else
1824                         ixgbe_vlan_hw_extend_disable(dev);
1825         }
1826 }
1827
1828 static void
1829 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1830 {
1831         struct ixgbe_hw *hw =
1832                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1833         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1834         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1835         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1836         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1837 }
1838
1839 static int
1840 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1841 {
1842         switch (nb_rx_q) {
1843         case 1:
1844         case 2:
1845                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1846                 break;
1847         case 4:
1848                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1849                 break;
1850         default:
1851                 return -EINVAL;
1852         }
1853
1854         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1855         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1856
1857         return 0;
1858 }
1859
1860 static int
1861 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1862 {
1863         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1864         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1865         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1866
1867         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1868                 /* check multi-queue mode */
1869                 switch (dev_conf->rxmode.mq_mode) {
1870                 case ETH_MQ_RX_VMDQ_DCB:
1871                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1872                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1873                         PMD_INIT_LOG(ERR, "SRIOV active,"
1874                                         " unsupported mq_mode rx %d.",
1875                                         dev_conf->rxmode.mq_mode);
1876                         return -EINVAL;
1877                 case ETH_MQ_RX_RSS:
1878                 case ETH_MQ_RX_VMDQ_RSS:
1879                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1880                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1881                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1882                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1883                                                 " invalid queue number"
1884                                                 " for VMDQ RSS, allowed"
1885                                                 " value are 1, 2 or 4.");
1886                                         return -EINVAL;
1887                                 }
1888                         break;
1889                 case ETH_MQ_RX_VMDQ_ONLY:
1890                 case ETH_MQ_RX_NONE:
1891                         /* if nothing mq mode configure, use default scheme */
1892                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1893                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1894                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1895                         break;
1896                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1897                         /* SRIOV only works in VMDq enable mode */
1898                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1899                                         " wrong mq_mode rx %d.",
1900                                         dev_conf->rxmode.mq_mode);
1901                         return -EINVAL;
1902                 }
1903
1904                 switch (dev_conf->txmode.mq_mode) {
1905                 case ETH_MQ_TX_VMDQ_DCB:
1906                         /* DCB VMDQ in SRIOV mode, not implement yet */
1907                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1908                                         " unsupported VMDQ mq_mode tx %d.",
1909                                         dev_conf->txmode.mq_mode);
1910                         return -EINVAL;
1911                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1912                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1913                         break;
1914                 }
1915
1916                 /* check valid queue number */
1917                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1918                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1919                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1920                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1921                                         " must be less than or equal to %d.",
1922                                         nb_rx_q, nb_tx_q,
1923                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1924                         return -EINVAL;
1925                 }
1926         } else {
1927                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1928                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1929                                           " not supported.");
1930                         return -EINVAL;
1931                 }
1932                 /* check configuration for vmdb+dcb mode */
1933                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1934                         const struct rte_eth_vmdq_dcb_conf *conf;
1935
1936                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1937                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1938                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1939                                 return -EINVAL;
1940                         }
1941                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1942                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1943                                conf->nb_queue_pools == ETH_32_POOLS)) {
1944                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1945                                                 " nb_queue_pools must be %d or %d.",
1946                                                 ETH_16_POOLS, ETH_32_POOLS);
1947                                 return -EINVAL;
1948                         }
1949                 }
1950                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1951                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1952
1953                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1954                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1955                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1956                                 return -EINVAL;
1957                         }
1958                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1959                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1960                                conf->nb_queue_pools == ETH_32_POOLS)) {
1961                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1962                                                 " nb_queue_pools != %d and"
1963                                                 " nb_queue_pools != %d.",
1964                                                 ETH_16_POOLS, ETH_32_POOLS);
1965                                 return -EINVAL;
1966                         }
1967                 }
1968
1969                 /* For DCB mode check our configuration before we go further */
1970                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1971                         const struct rte_eth_dcb_rx_conf *conf;
1972
1973                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1974                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1975                                                  IXGBE_DCB_NB_QUEUES);
1976                                 return -EINVAL;
1977                         }
1978                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1979                         if (!(conf->nb_tcs == ETH_4_TCS ||
1980                                conf->nb_tcs == ETH_8_TCS)) {
1981                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1982                                                 " and nb_tcs != %d.",
1983                                                 ETH_4_TCS, ETH_8_TCS);
1984                                 return -EINVAL;
1985                         }
1986                 }
1987
1988                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1989                         const struct rte_eth_dcb_tx_conf *conf;
1990
1991                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1992                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1993                                                  IXGBE_DCB_NB_QUEUES);
1994                                 return -EINVAL;
1995                         }
1996                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1997                         if (!(conf->nb_tcs == ETH_4_TCS ||
1998                                conf->nb_tcs == ETH_8_TCS)) {
1999                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2000                                                 " and nb_tcs != %d.",
2001                                                 ETH_4_TCS, ETH_8_TCS);
2002                                 return -EINVAL;
2003                         }
2004                 }
2005         }
2006         return 0;
2007 }
2008
2009 static int
2010 ixgbe_dev_configure(struct rte_eth_dev *dev)
2011 {
2012         struct ixgbe_interrupt *intr =
2013                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2014         struct ixgbe_adapter *adapter =
2015                 (struct ixgbe_adapter *)dev->data->dev_private;
2016         int ret;
2017
2018         PMD_INIT_FUNC_TRACE();
2019         /* multipe queue mode checking */
2020         ret  = ixgbe_check_mq_mode(dev);
2021         if (ret != 0) {
2022                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2023                             ret);
2024                 return ret;
2025         }
2026
2027         /* set flag to update link status after init */
2028         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2029
2030         /*
2031          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2032          * allocation or vector Rx preconditions we will reset it.
2033          */
2034         adapter->rx_bulk_alloc_allowed = true;
2035         adapter->rx_vec_allowed = true;
2036
2037         return 0;
2038 }
2039
2040 static void
2041 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2042 {
2043         struct ixgbe_hw *hw =
2044                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2045         struct ixgbe_interrupt *intr =
2046                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2047         uint32_t gpie;
2048
2049         /* only set up it on X550EM_X */
2050         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2051                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2052                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2053                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2054                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2055                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2056         }
2057 }
2058
2059 /*
2060  * Configure device link speed and setup link.
2061  * It returns 0 on success.
2062  */
2063 static int
2064 ixgbe_dev_start(struct rte_eth_dev *dev)
2065 {
2066         struct ixgbe_hw *hw =
2067                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2068         struct ixgbe_vf_info *vfinfo =
2069                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2070         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2071         uint32_t intr_vector = 0;
2072         int err, link_up = 0, negotiate = 0;
2073         uint32_t speed = 0;
2074         int mask = 0;
2075         int status;
2076         uint16_t vf, idx;
2077
2078         PMD_INIT_FUNC_TRACE();
2079
2080         /* IXGBE devices don't support half duplex */
2081         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
2082                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
2083                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
2084                              dev->data->dev_conf.link_duplex,
2085                              dev->data->port_id);
2086                 return -EINVAL;
2087         }
2088
2089         /* disable uio/vfio intr/eventfd mapping */
2090         rte_intr_disable(intr_handle);
2091
2092         /* stop adapter */
2093         hw->adapter_stopped = 0;
2094         ixgbe_stop_adapter(hw);
2095
2096         /* reinitialize adapter
2097          * this calls reset and start */
2098         status = ixgbe_pf_reset_hw(hw);
2099         if (status != 0)
2100                 return -1;
2101         hw->mac.ops.start_hw(hw);
2102         hw->mac.get_link_status = true;
2103
2104         /* configure PF module if SRIOV enabled */
2105         ixgbe_pf_host_configure(dev);
2106
2107         ixgbe_dev_phy_intr_setup(dev);
2108
2109         /* check and configure queue intr-vector mapping */
2110         if ((rte_intr_cap_multiple(intr_handle) ||
2111              !RTE_ETH_DEV_SRIOV(dev).active) &&
2112             dev->data->dev_conf.intr_conf.rxq != 0) {
2113                 intr_vector = dev->data->nb_rx_queues;
2114                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2115                         return -1;
2116         }
2117
2118         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2119                 intr_handle->intr_vec =
2120                         rte_zmalloc("intr_vec",
2121                                     dev->data->nb_rx_queues * sizeof(int), 0);
2122                 if (intr_handle->intr_vec == NULL) {
2123                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2124                                      " intr_vec\n", dev->data->nb_rx_queues);
2125                         return -ENOMEM;
2126                 }
2127         }
2128
2129         /* confiugre msix for sleep until rx interrupt */
2130         ixgbe_configure_msix(dev);
2131
2132         /* initialize transmission unit */
2133         ixgbe_dev_tx_init(dev);
2134
2135         /* This can fail when allocating mbufs for descriptor rings */
2136         err = ixgbe_dev_rx_init(dev);
2137         if (err) {
2138                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2139                 goto error;
2140         }
2141
2142         err = ixgbe_dev_rxtx_start(dev);
2143         if (err < 0) {
2144                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2145                 goto error;
2146         }
2147
2148         /* Skip link setup if loopback mode is enabled for 82599. */
2149         if (hw->mac.type == ixgbe_mac_82599EB &&
2150                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2151                 goto skip_link_setup;
2152
2153         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2154                 err = hw->mac.ops.setup_sfp(hw);
2155                 if (err)
2156                         goto error;
2157         }
2158
2159         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2160                 /* Turn on the copper */
2161                 ixgbe_set_phy_power(hw, true);
2162         } else {
2163                 /* Turn on the laser */
2164                 ixgbe_enable_tx_laser(hw);
2165         }
2166
2167         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2168         if (err)
2169                 goto error;
2170         dev->data->dev_link.link_status = link_up;
2171
2172         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2173         if (err)
2174                 goto error;
2175
2176         switch(dev->data->dev_conf.link_speed) {
2177         case ETH_LINK_SPEED_AUTONEG:
2178                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2179                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2180                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2181                 break;
2182         case ETH_LINK_SPEED_100:
2183                 /*
2184                  * Invalid for 82598 but error will be detected by
2185                  * ixgbe_setup_link()
2186                  */
2187                 speed = IXGBE_LINK_SPEED_100_FULL;
2188                 break;
2189         case ETH_LINK_SPEED_1000:
2190                 speed = IXGBE_LINK_SPEED_1GB_FULL;
2191                 break;
2192         case ETH_LINK_SPEED_10000:
2193                 speed = IXGBE_LINK_SPEED_10GB_FULL;
2194                 break;
2195         default:
2196                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2197                              dev->data->dev_conf.link_speed,
2198                              dev->data->port_id);
2199                 goto error;
2200         }
2201
2202         err = ixgbe_setup_link(hw, speed, link_up);
2203         if (err)
2204                 goto error;
2205
2206 skip_link_setup:
2207
2208         if (rte_intr_allow_others(intr_handle)) {
2209                 /* check if lsc interrupt is enabled */
2210                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2211                         ixgbe_dev_lsc_interrupt_setup(dev);
2212         } else {
2213                 rte_intr_callback_unregister(intr_handle,
2214                                              ixgbe_dev_interrupt_handler,
2215                                              (void *)dev);
2216                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2217                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2218                                      " no intr multiplex\n");
2219         }
2220
2221         /* check if rxq interrupt is enabled */
2222         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2223             rte_intr_dp_is_en(intr_handle))
2224                 ixgbe_dev_rxq_interrupt_setup(dev);
2225
2226         /* enable uio/vfio intr/eventfd mapping */
2227         rte_intr_enable(intr_handle);
2228
2229         /* resume enabled intr since hw reset */
2230         ixgbe_enable_intr(dev);
2231
2232         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2233                 ETH_VLAN_EXTEND_MASK;
2234         ixgbe_vlan_offload_set(dev, mask);
2235
2236         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2237                 /* Enable vlan filtering for VMDq */
2238                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2239         }
2240
2241         /* Configure DCB hw */
2242         ixgbe_configure_dcb(dev);
2243
2244         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2245                 err = ixgbe_fdir_configure(dev);
2246                 if (err)
2247                         goto error;
2248         }
2249
2250         /* Restore vf rate limit */
2251         if (vfinfo != NULL) {
2252                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2253                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2254                                 if (vfinfo[vf].tx_rate[idx] != 0)
2255                                         ixgbe_set_vf_rate_limit(dev, vf,
2256                                                 vfinfo[vf].tx_rate[idx],
2257                                                 1 << idx);
2258         }
2259
2260         ixgbe_restore_statistics_mapping(dev);
2261
2262         return 0;
2263
2264 error:
2265         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2266         ixgbe_dev_clear_queues(dev);
2267         return -EIO;
2268 }
2269
2270 /*
2271  * Stop device: disable rx and tx functions to allow for reconfiguring.
2272  */
2273 static void
2274 ixgbe_dev_stop(struct rte_eth_dev *dev)
2275 {
2276         struct rte_eth_link link;
2277         struct ixgbe_hw *hw =
2278                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2279         struct ixgbe_vf_info *vfinfo =
2280                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2281         struct ixgbe_filter_info *filter_info =
2282                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2283         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2284         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2285         int vf;
2286
2287         PMD_INIT_FUNC_TRACE();
2288
2289         /* disable interrupts */
2290         ixgbe_disable_intr(hw);
2291
2292         /* reset the NIC */
2293         ixgbe_pf_reset_hw(hw);
2294         hw->adapter_stopped = 0;
2295
2296         /* stop adapter */
2297         ixgbe_stop_adapter(hw);
2298
2299         for (vf = 0; vfinfo != NULL &&
2300                      vf < dev->pci_dev->max_vfs; vf++)
2301                 vfinfo[vf].clear_to_send = false;
2302
2303         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2304                 /* Turn off the copper */
2305                 ixgbe_set_phy_power(hw, false);
2306         } else {
2307                 /* Turn off the laser */
2308                 ixgbe_disable_tx_laser(hw);
2309         }
2310
2311         ixgbe_dev_clear_queues(dev);
2312
2313         /* Clear stored conf */
2314         dev->data->scattered_rx = 0;
2315         dev->data->lro = 0;
2316
2317         /* Clear recorded link status */
2318         memset(&link, 0, sizeof(link));
2319         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2320
2321         /* Remove all ntuple filters of the device */
2322         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2323              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2324                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2325                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2326                              p_5tuple, entries);
2327                 rte_free(p_5tuple);
2328         }
2329         memset(filter_info->fivetuple_mask, 0,
2330                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2331
2332         if (!rte_intr_allow_others(intr_handle))
2333                 /* resume to the default handler */
2334                 rte_intr_callback_register(intr_handle,
2335                                            ixgbe_dev_interrupt_handler,
2336                                            (void *)dev);
2337
2338         /* Clean datapath event and queue/vec mapping */
2339         rte_intr_efd_disable(intr_handle);
2340         if (intr_handle->intr_vec != NULL) {
2341                 rte_free(intr_handle->intr_vec);
2342                 intr_handle->intr_vec = NULL;
2343         }
2344 }
2345
2346 /*
2347  * Set device link up: enable tx.
2348  */
2349 static int
2350 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2351 {
2352         struct ixgbe_hw *hw =
2353                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2354         if (hw->mac.type == ixgbe_mac_82599EB) {
2355 #ifdef RTE_NIC_BYPASS
2356                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2357                         /* Not suported in bypass mode */
2358                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2359                                      "by device id 0x%x", hw->device_id);
2360                         return -ENOTSUP;
2361                 }
2362 #endif
2363         }
2364
2365         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2366                 /* Turn on the copper */
2367                 ixgbe_set_phy_power(hw, true);
2368         } else {
2369                 /* Turn on the laser */
2370                 ixgbe_enable_tx_laser(hw);
2371         }
2372
2373         return 0;
2374 }
2375
2376 /*
2377  * Set device link down: disable tx.
2378  */
2379 static int
2380 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2381 {
2382         struct ixgbe_hw *hw =
2383                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2384         if (hw->mac.type == ixgbe_mac_82599EB) {
2385 #ifdef RTE_NIC_BYPASS
2386                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2387                         /* Not suported in bypass mode */
2388                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2389                                      "by device id 0x%x", hw->device_id);
2390                         return -ENOTSUP;
2391                 }
2392 #endif
2393         }
2394
2395         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2396                 /* Turn off the copper */
2397                 ixgbe_set_phy_power(hw, false);
2398         } else {
2399                 /* Turn off the laser */
2400                 ixgbe_disable_tx_laser(hw);
2401         }
2402
2403         return 0;
2404 }
2405
2406 /*
2407  * Reest and stop device.
2408  */
2409 static void
2410 ixgbe_dev_close(struct rte_eth_dev *dev)
2411 {
2412         struct ixgbe_hw *hw =
2413                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2414
2415         PMD_INIT_FUNC_TRACE();
2416
2417         ixgbe_pf_reset_hw(hw);
2418
2419         ixgbe_dev_stop(dev);
2420         hw->adapter_stopped = 1;
2421
2422         ixgbe_dev_free_queues(dev);
2423
2424         ixgbe_disable_pcie_master(hw);
2425
2426         /* reprogram the RAR[0] in case user changed it. */
2427         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2428 }
2429
2430 static void
2431 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2432                            struct ixgbe_hw_stats *hw_stats,
2433                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2434                            uint64_t *total_qprc, uint64_t *total_qprdc)
2435 {
2436         uint32_t bprc, lxon, lxoff, total;
2437         uint32_t delta_gprc = 0;
2438         unsigned i;
2439         /* Workaround for RX byte count not including CRC bytes when CRC
2440 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2441          * is disabled.
2442 +        */
2443         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2444                         IXGBE_HLREG0_RXCRCSTRP);
2445
2446         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2447         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2448         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2449         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2450
2451         for (i = 0; i < 8; i++) {
2452                 uint32_t mp;
2453                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2454                 /* global total per queue */
2455                 hw_stats->mpc[i] += mp;
2456                 /* Running comprehensive total for stats display */
2457                 *total_missed_rx += hw_stats->mpc[i];
2458                 if (hw->mac.type == ixgbe_mac_82598EB) {
2459                         hw_stats->rnbc[i] +=
2460                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2461                         hw_stats->pxonrxc[i] +=
2462                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2463                         hw_stats->pxoffrxc[i] +=
2464                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2465                 } else {
2466                         hw_stats->pxonrxc[i] +=
2467                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2468                         hw_stats->pxoffrxc[i] +=
2469                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2470                         hw_stats->pxon2offc[i] +=
2471                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2472                 }
2473                 hw_stats->pxontxc[i] +=
2474                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2475                 hw_stats->pxofftxc[i] +=
2476                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2477         }
2478         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2479                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2480                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2481                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2482
2483                 delta_gprc += delta_qprc;
2484
2485                 hw_stats->qprc[i] += delta_qprc;
2486                 hw_stats->qptc[i] += delta_qptc;
2487
2488                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2489                 hw_stats->qbrc[i] +=
2490                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2491                 if (crc_strip == 0)
2492                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2493
2494                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2495                 hw_stats->qbtc[i] +=
2496                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2497
2498                 hw_stats->qprdc[i] += delta_qprdc;
2499                 *total_qprdc += hw_stats->qprdc[i];
2500
2501                 *total_qprc += hw_stats->qprc[i];
2502                 *total_qbrc += hw_stats->qbrc[i];
2503         }
2504         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2505         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2506         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2507
2508         /*
2509          * An errata states that gprc actually counts good + missed packets:
2510          * Workaround to set gprc to summated queue packet receives
2511          */
2512         hw_stats->gprc = *total_qprc;
2513
2514         if (hw->mac.type != ixgbe_mac_82598EB) {
2515                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2516                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2517                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2518                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2519                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2520                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2521                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2522                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2523         } else {
2524                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2525                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2526                 /* 82598 only has a counter in the high register */
2527                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2528                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2529                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2530         }
2531         uint64_t old_tpr = hw_stats->tpr;
2532
2533         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2534         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2535
2536         if (crc_strip == 0)
2537                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2538
2539         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2540         hw_stats->gptc += delta_gptc;
2541         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2542         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2543
2544         /*
2545          * Workaround: mprc hardware is incorrectly counting
2546          * broadcasts, so for now we subtract those.
2547          */
2548         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2549         hw_stats->bprc += bprc;
2550         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2551         if (hw->mac.type == ixgbe_mac_82598EB)
2552                 hw_stats->mprc -= bprc;
2553
2554         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2555         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2556         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2557         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2558         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2559         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2560
2561         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2562         hw_stats->lxontxc += lxon;
2563         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2564         hw_stats->lxofftxc += lxoff;
2565         total = lxon + lxoff;
2566
2567         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2568         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2569         hw_stats->gptc -= total;
2570         hw_stats->mptc -= total;
2571         hw_stats->ptc64 -= total;
2572         hw_stats->gotc -= total * ETHER_MIN_LEN;
2573
2574         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2575         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2576         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2577         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2578         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2579         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2580         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2581         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2582         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2583         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2584         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2585         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2586         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2587         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2588         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2589         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2590         /* Only read FCOE on 82599 */
2591         if (hw->mac.type != ixgbe_mac_82598EB) {
2592                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2593                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2594                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2595                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2596                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2597         }
2598
2599         /* Flow Director Stats registers */
2600         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2601         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2602 }
2603
2604 /*
2605  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2606  */
2607 static void
2608 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2609 {
2610         struct ixgbe_hw *hw =
2611                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2612         struct ixgbe_hw_stats *hw_stats =
2613                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2614         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2615         unsigned i;
2616
2617         total_missed_rx = 0;
2618         total_qbrc = 0;
2619         total_qprc = 0;
2620         total_qprdc = 0;
2621
2622         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2623                         &total_qprc, &total_qprdc);
2624
2625         if (stats == NULL)
2626                 return;
2627
2628         /* Fill out the rte_eth_stats statistics structure */
2629         stats->ipackets = total_qprc;
2630         stats->ibytes = total_qbrc;
2631         stats->opackets = hw_stats->gptc;
2632         stats->obytes = hw_stats->gotc;
2633
2634         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2635                 stats->q_ipackets[i] = hw_stats->qprc[i];
2636                 stats->q_opackets[i] = hw_stats->qptc[i];
2637                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2638                 stats->q_obytes[i] = hw_stats->qbtc[i];
2639                 stats->q_errors[i] = hw_stats->qprdc[i];
2640         }
2641
2642         /* Rx Errors */
2643         stats->imissed  = total_missed_rx;
2644         stats->ierrors  = hw_stats->crcerrs +
2645                           hw_stats->mspdc +
2646                           hw_stats->rlec +
2647                           hw_stats->ruc +
2648                           hw_stats->roc +
2649                           hw_stats->illerrc +
2650                           hw_stats->errbc +
2651                           hw_stats->rfc +
2652                           hw_stats->fccrc +
2653                           hw_stats->fclast;
2654
2655         /* Tx Errors */
2656         stats->oerrors  = 0;
2657 }
2658
2659 static void
2660 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2661 {
2662         struct ixgbe_hw_stats *stats =
2663                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2664
2665         /* HW registers are cleared on read */
2666         ixgbe_dev_stats_get(dev, NULL);
2667
2668         /* Reset software totals */
2669         memset(stats, 0, sizeof(*stats));
2670 }
2671
2672 /* This function calculates the number of xstats based on the current config */
2673 static unsigned
2674 ixgbe_xstats_calc_num(void) {
2675         return IXGBE_NB_HW_STATS + (IXGBE_NB_RXQ_PRIO_STATS * 8) +
2676                 (IXGBE_NB_TXQ_PRIO_STATS * 8);
2677 }
2678
2679 static int
2680 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2681                                          unsigned n)
2682 {
2683         struct ixgbe_hw *hw =
2684                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2685         struct ixgbe_hw_stats *hw_stats =
2686                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2687         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2688         unsigned i, stat, count = 0;
2689
2690         count = ixgbe_xstats_calc_num();
2691
2692         if (n < count)
2693                 return count;
2694
2695         total_missed_rx = 0;
2696         total_qbrc = 0;
2697         total_qprc = 0;
2698         total_qprdc = 0;
2699
2700         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2701                                    &total_qprc, &total_qprdc);
2702
2703         /* If this is a reset xstats is NULL, and we have cleared the
2704          * registers by reading them.
2705          */
2706         if (!xstats)
2707                 return 0;
2708
2709         /* Extended stats from ixgbe_hw_stats */
2710         count = 0;
2711         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2712                 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2713                          rte_ixgbe_stats_strings[i].name);
2714                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2715                                 rte_ixgbe_stats_strings[i].offset);
2716                 count++;
2717         }
2718
2719         /* RX Priority Stats */
2720         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2721                 for (i = 0; i < 8; i++) {
2722                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2723                                  "rx_priority%u_%s", i,
2724                                  rte_ixgbe_rxq_strings[stat].name);
2725                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2726                                         rte_ixgbe_rxq_strings[stat].offset +
2727                                         (sizeof(uint64_t) * i));
2728                         count++;
2729                 }
2730         }
2731
2732         /* TX Priority Stats */
2733         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2734                 for (i = 0; i < 8; i++) {
2735                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2736                                  "tx_priority%u_%s", i,
2737                                  rte_ixgbe_txq_strings[stat].name);
2738                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2739                                         rte_ixgbe_txq_strings[stat].offset +
2740                                         (sizeof(uint64_t) * i));
2741                         count++;
2742                 }
2743         }
2744
2745         return count;
2746 }
2747
2748 static void
2749 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2750 {
2751         struct ixgbe_hw_stats *stats =
2752                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2753
2754         unsigned count = ixgbe_xstats_calc_num();
2755
2756         /* HW registers are cleared on read */
2757         ixgbe_dev_xstats_get(dev, NULL, count);
2758
2759         /* Reset software totals */
2760         memset(stats, 0, sizeof(*stats));
2761 }
2762
2763 static void
2764 ixgbevf_update_stats(struct rte_eth_dev *dev)
2765 {
2766         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2767         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2768                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2769
2770         /* Good Rx packet, include VF loopback */
2771         UPDATE_VF_STAT(IXGBE_VFGPRC,
2772             hw_stats->last_vfgprc, hw_stats->vfgprc);
2773
2774         /* Good Rx octets, include VF loopback */
2775         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2776             hw_stats->last_vfgorc, hw_stats->vfgorc);
2777
2778         /* Good Tx packet, include VF loopback */
2779         UPDATE_VF_STAT(IXGBE_VFGPTC,
2780             hw_stats->last_vfgptc, hw_stats->vfgptc);
2781
2782         /* Good Tx octets, include VF loopback */
2783         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2784             hw_stats->last_vfgotc, hw_stats->vfgotc);
2785
2786         /* Rx Multicst Packet */
2787         UPDATE_VF_STAT(IXGBE_VFMPRC,
2788             hw_stats->last_vfmprc, hw_stats->vfmprc);
2789 }
2790
2791 static int
2792 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2793                        unsigned n)
2794 {
2795         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2796                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2797         unsigned i;
2798
2799         if (n < IXGBEVF_NB_XSTATS)
2800                 return IXGBEVF_NB_XSTATS;
2801
2802         ixgbevf_update_stats(dev);
2803
2804         if (!xstats)
2805                 return 0;
2806
2807         /* Extended stats */
2808         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2809                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2810                          "%s", rte_ixgbevf_stats_strings[i].name);
2811                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2812                         rte_ixgbevf_stats_strings[i].offset);
2813         }
2814
2815         return IXGBEVF_NB_XSTATS;
2816 }
2817
2818 static void
2819 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2820 {
2821         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2822                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2823
2824         ixgbevf_update_stats(dev);
2825
2826         if (stats == NULL)
2827                 return;
2828
2829         stats->ipackets = hw_stats->vfgprc;
2830         stats->ibytes = hw_stats->vfgorc;
2831         stats->opackets = hw_stats->vfgptc;
2832         stats->obytes = hw_stats->vfgotc;
2833         stats->imcasts = hw_stats->vfmprc;
2834         /* stats->imcasts should be removed as imcasts is deprecated */
2835 }
2836
2837 static void
2838 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2839 {
2840         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2841                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2842
2843         /* Sync HW register to the last stats */
2844         ixgbevf_dev_stats_get(dev, NULL);
2845
2846         /* reset HW current stats*/
2847         hw_stats->vfgprc = 0;
2848         hw_stats->vfgorc = 0;
2849         hw_stats->vfgptc = 0;
2850         hw_stats->vfgotc = 0;
2851         hw_stats->vfmprc = 0;
2852
2853 }
2854
2855 static void
2856 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2857 {
2858         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2859
2860         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2861         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2862         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2863         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2864         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2865         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2866         dev_info->max_vfs = dev->pci_dev->max_vfs;
2867         if (hw->mac.type == ixgbe_mac_82598EB)
2868                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2869         else
2870                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2871         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2872         dev_info->rx_offload_capa =
2873                 DEV_RX_OFFLOAD_VLAN_STRIP |
2874                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2875                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2876                 DEV_RX_OFFLOAD_TCP_CKSUM;
2877
2878         /*
2879          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2880          * mode.
2881          */
2882         if ((hw->mac.type == ixgbe_mac_82599EB ||
2883              hw->mac.type == ixgbe_mac_X540) &&
2884             !RTE_ETH_DEV_SRIOV(dev).active)
2885                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2886
2887         if (hw->mac.type == ixgbe_mac_X550 ||
2888             hw->mac.type == ixgbe_mac_X550EM_x)
2889                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2890
2891         dev_info->tx_offload_capa =
2892                 DEV_TX_OFFLOAD_VLAN_INSERT |
2893                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2894                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2895                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2896                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2897                 DEV_TX_OFFLOAD_TCP_TSO;
2898
2899         if (hw->mac.type == ixgbe_mac_X550 ||
2900             hw->mac.type == ixgbe_mac_X550EM_x)
2901                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2902
2903         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2904                 .rx_thresh = {
2905                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2906                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2907                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2908                 },
2909                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2910                 .rx_drop_en = 0,
2911         };
2912
2913         dev_info->default_txconf = (struct rte_eth_txconf) {
2914                 .tx_thresh = {
2915                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2916                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2917                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2918                 },
2919                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2920                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2921                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2922                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2923         };
2924
2925         dev_info->rx_desc_lim = rx_desc_lim;
2926         dev_info->tx_desc_lim = tx_desc_lim;
2927
2928         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2929         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2930         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2931 }
2932
2933 static void
2934 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2935                      struct rte_eth_dev_info *dev_info)
2936 {
2937         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2938
2939         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2940         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2941         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2942         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2943         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2944         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2945         dev_info->max_vfs = dev->pci_dev->max_vfs;
2946         if (hw->mac.type == ixgbe_mac_82598EB)
2947                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2948         else
2949                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2950         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2951                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2952                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2953                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2954         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2955                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2956                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2957                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2958                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2959                                 DEV_TX_OFFLOAD_TCP_TSO;
2960
2961         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2962                 .rx_thresh = {
2963                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2964                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2965                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2966                 },
2967                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2968                 .rx_drop_en = 0,
2969         };
2970
2971         dev_info->default_txconf = (struct rte_eth_txconf) {
2972                 .tx_thresh = {
2973                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2974                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2975                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2976                 },
2977                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2978                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2979                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2980                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2981         };
2982
2983         dev_info->rx_desc_lim = rx_desc_lim;
2984         dev_info->tx_desc_lim = tx_desc_lim;
2985 }
2986
2987 /* return 0 means link status changed, -1 means not changed */
2988 static int
2989 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2990 {
2991         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2992         struct rte_eth_link link, old;
2993         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2994         int link_up;
2995         int diag;
2996
2997         link.link_status = 0;
2998         link.link_speed = 0;
2999         link.link_duplex = 0;
3000         memset(&old, 0, sizeof(old));
3001         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3002
3003         hw->mac.get_link_status = true;
3004
3005         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3006         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3007                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3008         else
3009                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3010
3011         if (diag != 0) {
3012                 link.link_speed = ETH_LINK_SPEED_100;
3013                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3014                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3015                 if (link.link_status == old.link_status)
3016                         return -1;
3017                 return 0;
3018         }
3019
3020         if (link_up == 0) {
3021                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3022                 if (link.link_status == old.link_status)
3023                         return -1;
3024                 return 0;
3025         }
3026         link.link_status = 1;
3027         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3028
3029         switch (link_speed) {
3030         default:
3031         case IXGBE_LINK_SPEED_UNKNOWN:
3032                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3033                 link.link_speed = ETH_LINK_SPEED_100;
3034                 break;
3035
3036         case IXGBE_LINK_SPEED_100_FULL:
3037                 link.link_speed = ETH_LINK_SPEED_100;
3038                 break;
3039
3040         case IXGBE_LINK_SPEED_1GB_FULL:
3041                 link.link_speed = ETH_LINK_SPEED_1000;
3042                 break;
3043
3044         case IXGBE_LINK_SPEED_10GB_FULL:
3045                 link.link_speed = ETH_LINK_SPEED_10000;
3046                 break;
3047         }
3048         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3049
3050         if (link.link_status == old.link_status)
3051                 return -1;
3052
3053         return 0;
3054 }
3055
3056 static void
3057 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3058 {
3059         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3060         uint32_t fctrl;
3061
3062         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3063         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3064         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3065 }
3066
3067 static void
3068 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3069 {
3070         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3071         uint32_t fctrl;
3072
3073         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3074         fctrl &= (~IXGBE_FCTRL_UPE);
3075         if (dev->data->all_multicast == 1)
3076                 fctrl |= IXGBE_FCTRL_MPE;
3077         else
3078                 fctrl &= (~IXGBE_FCTRL_MPE);
3079         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3080 }
3081
3082 static void
3083 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3084 {
3085         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3086         uint32_t fctrl;
3087
3088         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3089         fctrl |= IXGBE_FCTRL_MPE;
3090         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3091 }
3092
3093 static void
3094 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3095 {
3096         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3097         uint32_t fctrl;
3098
3099         if (dev->data->promiscuous == 1)
3100                 return; /* must remain in all_multicast mode */
3101
3102         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3103         fctrl &= (~IXGBE_FCTRL_MPE);
3104         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3105 }
3106
3107 /**
3108  * It clears the interrupt causes and enables the interrupt.
3109  * It will be called once only during nic initialized.
3110  *
3111  * @param dev
3112  *  Pointer to struct rte_eth_dev.
3113  *
3114  * @return
3115  *  - On success, zero.
3116  *  - On failure, a negative value.
3117  */
3118 static int
3119 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3120 {
3121         struct ixgbe_interrupt *intr =
3122                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3123
3124         ixgbe_dev_link_status_print(dev);
3125         intr->mask |= IXGBE_EICR_LSC;
3126
3127         return 0;
3128 }
3129
3130 /**
3131  * It clears the interrupt causes and enables the interrupt.
3132  * It will be called once only during nic initialized.
3133  *
3134  * @param dev
3135  *  Pointer to struct rte_eth_dev.
3136  *
3137  * @return
3138  *  - On success, zero.
3139  *  - On failure, a negative value.
3140  */
3141 static int
3142 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3143 {
3144         struct ixgbe_interrupt *intr =
3145                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3146
3147         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3148
3149         return 0;
3150 }
3151
3152 /*
3153  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3154  *
3155  * @param dev
3156  *  Pointer to struct rte_eth_dev.
3157  *
3158  * @return
3159  *  - On success, zero.
3160  *  - On failure, a negative value.
3161  */
3162 static int
3163 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3164 {
3165         uint32_t eicr;
3166         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3167         struct ixgbe_interrupt *intr =
3168                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3169
3170         /* clear all cause mask */
3171         ixgbe_disable_intr(hw);
3172
3173         /* read-on-clear nic registers here */
3174         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3175         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3176
3177         intr->flags = 0;
3178
3179         /* set flag for async link update */
3180         if (eicr & IXGBE_EICR_LSC)
3181                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3182
3183         if (eicr & IXGBE_EICR_MAILBOX)
3184                 intr->flags |= IXGBE_FLAG_MAILBOX;
3185
3186         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3187             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3188             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3189                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3190
3191         return 0;
3192 }
3193
3194 /**
3195  * It gets and then prints the link status.
3196  *
3197  * @param dev
3198  *  Pointer to struct rte_eth_dev.
3199  *
3200  * @return
3201  *  - On success, zero.
3202  *  - On failure, a negative value.
3203  */
3204 static void
3205 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3206 {
3207         struct rte_eth_link link;
3208
3209         memset(&link, 0, sizeof(link));
3210         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3211         if (link.link_status) {
3212                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3213                                         (int)(dev->data->port_id),
3214                                         (unsigned)link.link_speed,
3215                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3216                                         "full-duplex" : "half-duplex");
3217         } else {
3218                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3219                                 (int)(dev->data->port_id));
3220         }
3221         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3222                                 dev->pci_dev->addr.domain,
3223                                 dev->pci_dev->addr.bus,
3224                                 dev->pci_dev->addr.devid,
3225                                 dev->pci_dev->addr.function);
3226 }
3227
3228 /*
3229  * It executes link_update after knowing an interrupt occurred.
3230  *
3231  * @param dev
3232  *  Pointer to struct rte_eth_dev.
3233  *
3234  * @return
3235  *  - On success, zero.
3236  *  - On failure, a negative value.
3237  */
3238 static int
3239 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3240 {
3241         struct ixgbe_interrupt *intr =
3242                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3243         int64_t timeout;
3244         struct rte_eth_link link;
3245         int intr_enable_delay = false;
3246         struct ixgbe_hw *hw =
3247                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3248
3249         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3250
3251         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3252                 ixgbe_pf_mbx_process(dev);
3253                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3254         }
3255
3256         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3257                 ixgbe_handle_lasi(hw);
3258                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3259         }
3260
3261         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3262                 /* get the link status before link update, for predicting later */
3263                 memset(&link, 0, sizeof(link));
3264                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3265
3266                 ixgbe_dev_link_update(dev, 0);
3267
3268                 /* likely to up */
3269                 if (!link.link_status)
3270                         /* handle it 1 sec later, wait it being stable */
3271                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3272                 /* likely to down */
3273                 else
3274                         /* handle it 4 sec later, wait it being stable */
3275                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3276
3277                 ixgbe_dev_link_status_print(dev);
3278
3279                 intr_enable_delay = true;
3280         }
3281
3282         if (intr_enable_delay) {
3283                 if (rte_eal_alarm_set(timeout * 1000,
3284                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3285                         PMD_DRV_LOG(ERR, "Error setting alarm");
3286         } else {
3287                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3288                 ixgbe_enable_intr(dev);
3289                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3290         }
3291
3292
3293         return 0;
3294 }
3295
3296 /**
3297  * Interrupt handler which shall be registered for alarm callback for delayed
3298  * handling specific interrupt to wait for the stable nic state. As the
3299  * NIC interrupt state is not stable for ixgbe after link is just down,
3300  * it needs to wait 4 seconds to get the stable status.
3301  *
3302  * @param handle
3303  *  Pointer to interrupt handle.
3304  * @param param
3305  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3306  *
3307  * @return
3308  *  void
3309  */
3310 static void
3311 ixgbe_dev_interrupt_delayed_handler(void *param)
3312 {
3313         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3314         struct ixgbe_interrupt *intr =
3315                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3316         struct ixgbe_hw *hw =
3317                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3318         uint32_t eicr;
3319
3320         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3321         if (eicr & IXGBE_EICR_MAILBOX)
3322                 ixgbe_pf_mbx_process(dev);
3323
3324         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3325                 ixgbe_handle_lasi(hw);
3326                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3327         }
3328
3329         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3330                 ixgbe_dev_link_update(dev, 0);
3331                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3332                 ixgbe_dev_link_status_print(dev);
3333                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3334         }
3335
3336         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3337         ixgbe_enable_intr(dev);
3338         rte_intr_enable(&(dev->pci_dev->intr_handle));
3339 }
3340
3341 /**
3342  * Interrupt handler triggered by NIC  for handling
3343  * specific interrupt.
3344  *
3345  * @param handle
3346  *  Pointer to interrupt handle.
3347  * @param param
3348  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3349  *
3350  * @return
3351  *  void
3352  */
3353 static void
3354 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3355                             void *param)
3356 {
3357         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3358
3359         ixgbe_dev_interrupt_get_status(dev);
3360         ixgbe_dev_interrupt_action(dev);
3361 }
3362
3363 static int
3364 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3365 {
3366         struct ixgbe_hw *hw;
3367
3368         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3369         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3370 }
3371
3372 static int
3373 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3374 {
3375         struct ixgbe_hw *hw;
3376
3377         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3378         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3379 }
3380
3381 static int
3382 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3383 {
3384         struct ixgbe_hw *hw;
3385         uint32_t mflcn_reg;
3386         uint32_t fccfg_reg;
3387         int rx_pause;
3388         int tx_pause;
3389
3390         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3391
3392         fc_conf->pause_time = hw->fc.pause_time;
3393         fc_conf->high_water = hw->fc.high_water[0];
3394         fc_conf->low_water = hw->fc.low_water[0];
3395         fc_conf->send_xon = hw->fc.send_xon;
3396         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3397
3398         /*
3399          * Return rx_pause status according to actual setting of
3400          * MFLCN register.
3401          */
3402         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3403         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3404                 rx_pause = 1;
3405         else
3406                 rx_pause = 0;
3407
3408         /*
3409          * Return tx_pause status according to actual setting of
3410          * FCCFG register.
3411          */
3412         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3413         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3414                 tx_pause = 1;
3415         else
3416                 tx_pause = 0;
3417
3418         if (rx_pause && tx_pause)
3419                 fc_conf->mode = RTE_FC_FULL;
3420         else if (rx_pause)
3421                 fc_conf->mode = RTE_FC_RX_PAUSE;
3422         else if (tx_pause)
3423                 fc_conf->mode = RTE_FC_TX_PAUSE;
3424         else
3425                 fc_conf->mode = RTE_FC_NONE;
3426
3427         return 0;
3428 }
3429
3430 static int
3431 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3432 {
3433         struct ixgbe_hw *hw;
3434         int err;
3435         uint32_t rx_buf_size;
3436         uint32_t max_high_water;
3437         uint32_t mflcn;
3438         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3439                 ixgbe_fc_none,
3440                 ixgbe_fc_rx_pause,
3441                 ixgbe_fc_tx_pause,
3442                 ixgbe_fc_full
3443         };
3444
3445         PMD_INIT_FUNC_TRACE();
3446
3447         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3448         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3449         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3450
3451         /*
3452          * At least reserve one Ethernet frame for watermark
3453          * high_water/low_water in kilo bytes for ixgbe
3454          */
3455         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3456         if ((fc_conf->high_water > max_high_water) ||
3457                 (fc_conf->high_water < fc_conf->low_water)) {
3458                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3459                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3460                 return -EINVAL;
3461         }
3462
3463         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3464         hw->fc.pause_time     = fc_conf->pause_time;
3465         hw->fc.high_water[0]  = fc_conf->high_water;
3466         hw->fc.low_water[0]   = fc_conf->low_water;
3467         hw->fc.send_xon       = fc_conf->send_xon;
3468         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3469
3470         err = ixgbe_fc_enable(hw);
3471
3472         /* Not negotiated is not an error case */
3473         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3474
3475                 /* check if we want to forward MAC frames - driver doesn't have native
3476                  * capability to do that, so we'll write the registers ourselves */
3477
3478                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3479
3480                 /* set or clear MFLCN.PMCF bit depending on configuration */
3481                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3482                         mflcn |= IXGBE_MFLCN_PMCF;
3483                 else
3484                         mflcn &= ~IXGBE_MFLCN_PMCF;
3485
3486                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3487                 IXGBE_WRITE_FLUSH(hw);
3488
3489                 return 0;
3490         }
3491
3492         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3493         return -EIO;
3494 }
3495
3496 /**
3497  *  ixgbe_pfc_enable_generic - Enable flow control
3498  *  @hw: pointer to hardware structure
3499  *  @tc_num: traffic class number
3500  *  Enable flow control according to the current settings.
3501  */
3502 static int
3503 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3504 {
3505         int ret_val = 0;
3506         uint32_t mflcn_reg, fccfg_reg;
3507         uint32_t reg;
3508         uint32_t fcrtl, fcrth;
3509         uint8_t i;
3510         uint8_t nb_rx_en;
3511
3512         /* Validate the water mark configuration */
3513         if (!hw->fc.pause_time) {
3514                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3515                 goto out;
3516         }
3517
3518         /* Low water mark of zero causes XOFF floods */
3519         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3520                  /* High/Low water can not be 0 */
3521                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3522                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3523                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3524                         goto out;
3525                 }
3526
3527                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3528                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3529                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3530                         goto out;
3531                 }
3532         }
3533         /* Negotiate the fc mode to use */
3534         ixgbe_fc_autoneg(hw);
3535
3536         /* Disable any previous flow control settings */
3537         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3538         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3539
3540         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3541         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3542
3543         switch (hw->fc.current_mode) {
3544         case ixgbe_fc_none:
3545                 /*
3546                  * If the count of enabled RX Priority Flow control >1,
3547                  * and the TX pause can not be disabled
3548                  */
3549                 nb_rx_en = 0;
3550                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3551                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3552                         if (reg & IXGBE_FCRTH_FCEN)
3553                                 nb_rx_en++;
3554                 }
3555                 if (nb_rx_en > 1)
3556                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3557                 break;
3558         case ixgbe_fc_rx_pause:
3559                 /*
3560                  * Rx Flow control is enabled and Tx Flow control is
3561                  * disabled by software override. Since there really
3562                  * isn't a way to advertise that we are capable of RX
3563                  * Pause ONLY, we will advertise that we support both
3564                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3565                  * disable the adapter's ability to send PAUSE frames.
3566                  */
3567                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3568                 /*
3569                  * If the count of enabled RX Priority Flow control >1,
3570                  * and the TX pause can not be disabled
3571                  */
3572                 nb_rx_en = 0;
3573                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3574                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3575                         if (reg & IXGBE_FCRTH_FCEN)
3576                                 nb_rx_en++;
3577                 }
3578                 if (nb_rx_en > 1)
3579                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3580                 break;
3581         case ixgbe_fc_tx_pause:
3582                 /*
3583                  * Tx Flow control is enabled, and Rx Flow control is
3584                  * disabled by software override.
3585                  */
3586                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3587                 break;
3588         case ixgbe_fc_full:
3589                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3590                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3591                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3592                 break;
3593         default:
3594                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3595                 ret_val = IXGBE_ERR_CONFIG;
3596                 goto out;
3597                 break;
3598         }
3599
3600         /* Set 802.3x based flow control settings. */
3601         mflcn_reg |= IXGBE_MFLCN_DPF;
3602         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3603         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3604
3605         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3606         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3607                 hw->fc.high_water[tc_num]) {
3608                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3609                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3610                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3611         } else {
3612                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3613                 /*
3614                  * In order to prevent Tx hangs when the internal Tx
3615                  * switch is enabled we must set the high water mark
3616                  * to the maximum FCRTH value.  This allows the Tx
3617                  * switch to function even under heavy Rx workloads.
3618                  */
3619                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3620         }
3621         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3622
3623         /* Configure pause time (2 TCs per register) */
3624         reg = hw->fc.pause_time * 0x00010001;
3625         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3626                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3627
3628         /* Configure flow control refresh threshold value */
3629         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3630
3631 out:
3632         return ret_val;
3633 }
3634
3635 static int
3636 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3637 {
3638         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3639         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3640
3641         if (hw->mac.type != ixgbe_mac_82598EB) {
3642                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3643         }
3644         return ret_val;
3645 }
3646
3647 static int
3648 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3649 {
3650         int err;
3651         uint32_t rx_buf_size;
3652         uint32_t max_high_water;
3653         uint8_t tc_num;
3654         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3655         struct ixgbe_hw *hw =
3656                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3657         struct ixgbe_dcb_config *dcb_config =
3658                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3659
3660         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3661                 ixgbe_fc_none,
3662                 ixgbe_fc_rx_pause,
3663                 ixgbe_fc_tx_pause,
3664                 ixgbe_fc_full
3665         };
3666
3667         PMD_INIT_FUNC_TRACE();
3668
3669         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3670         tc_num = map[pfc_conf->priority];
3671         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3672         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3673         /*
3674          * At least reserve one Ethernet frame for watermark
3675          * high_water/low_water in kilo bytes for ixgbe
3676          */
3677         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3678         if ((pfc_conf->fc.high_water > max_high_water) ||
3679             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3680                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3681                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3682                 return -EINVAL;
3683         }
3684
3685         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3686         hw->fc.pause_time = pfc_conf->fc.pause_time;
3687         hw->fc.send_xon = pfc_conf->fc.send_xon;
3688         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3689         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3690
3691         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3692
3693         /* Not negotiated is not an error case */
3694         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3695                 return 0;
3696
3697         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3698         return -EIO;
3699 }
3700
3701 static int
3702 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3703                           struct rte_eth_rss_reta_entry64 *reta_conf,
3704                           uint16_t reta_size)
3705 {
3706         uint8_t i, j, mask;
3707         uint32_t reta, r;
3708         uint16_t idx, shift;
3709         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3710         uint16_t sp_reta_size;
3711         uint32_t reta_reg;
3712
3713         PMD_INIT_FUNC_TRACE();
3714
3715         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3716                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3717                         "NIC.");
3718                 return -ENOTSUP;
3719         }
3720
3721         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3722         if (reta_size != sp_reta_size) {
3723                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3724                         "(%d) doesn't match the number hardware can supported "
3725                         "(%d)\n", reta_size, sp_reta_size);
3726                 return -EINVAL;
3727         }
3728
3729         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3730                 idx = i / RTE_RETA_GROUP_SIZE;
3731                 shift = i % RTE_RETA_GROUP_SIZE;
3732                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3733                                                 IXGBE_4_BIT_MASK);
3734                 if (!mask)
3735                         continue;
3736                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3737                 if (mask == IXGBE_4_BIT_MASK)
3738                         r = 0;
3739                 else
3740                         r = IXGBE_READ_REG(hw, reta_reg);
3741                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3742                         if (mask & (0x1 << j))
3743                                 reta |= reta_conf[idx].reta[shift + j] <<
3744                                                         (CHAR_BIT * j);
3745                         else
3746                                 reta |= r & (IXGBE_8_BIT_MASK <<
3747                                                 (CHAR_BIT * j));
3748                 }
3749                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3750         }
3751
3752         return 0;
3753 }
3754
3755 static int
3756 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3757                          struct rte_eth_rss_reta_entry64 *reta_conf,
3758                          uint16_t reta_size)
3759 {
3760         uint8_t i, j, mask;
3761         uint32_t reta;
3762         uint16_t idx, shift;
3763         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3764         uint16_t sp_reta_size;
3765         uint32_t reta_reg;
3766
3767         PMD_INIT_FUNC_TRACE();
3768         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3769         if (reta_size != sp_reta_size) {
3770                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3771                         "(%d) doesn't match the number hardware can supported "
3772                         "(%d)\n", reta_size, sp_reta_size);
3773                 return -EINVAL;
3774         }
3775
3776         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3777                 idx = i / RTE_RETA_GROUP_SIZE;
3778                 shift = i % RTE_RETA_GROUP_SIZE;
3779                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3780                                                 IXGBE_4_BIT_MASK);
3781                 if (!mask)
3782                         continue;
3783
3784                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3785                 reta = IXGBE_READ_REG(hw, reta_reg);
3786                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3787                         if (mask & (0x1 << j))
3788                                 reta_conf[idx].reta[shift + j] =
3789                                         ((reta >> (CHAR_BIT * j)) &
3790                                                 IXGBE_8_BIT_MASK);
3791                 }
3792         }
3793
3794         return 0;
3795 }
3796
3797 static void
3798 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3799                                 uint32_t index, uint32_t pool)
3800 {
3801         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3802         uint32_t enable_addr = 1;
3803
3804         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3805 }
3806
3807 static void
3808 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3809 {
3810         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3811
3812         ixgbe_clear_rar(hw, index);
3813 }
3814
3815 static void
3816 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3817 {
3818         ixgbe_remove_rar(dev, 0);
3819
3820         ixgbe_add_rar(dev, addr, 0, 0);
3821 }
3822
3823 static int
3824 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3825 {
3826         uint32_t hlreg0;
3827         uint32_t maxfrs;
3828         struct ixgbe_hw *hw;
3829         struct rte_eth_dev_info dev_info;
3830         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3831
3832         ixgbe_dev_info_get(dev, &dev_info);
3833
3834         /* check that mtu is within the allowed range */
3835         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3836                 return -EINVAL;
3837
3838         /* refuse mtu that requires the support of scattered packets when this
3839          * feature has not been enabled before. */
3840         if (!dev->data->scattered_rx &&
3841             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3842              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3843                 return -EINVAL;
3844
3845         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3846         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3847
3848         /* switch to jumbo mode if needed */
3849         if (frame_size > ETHER_MAX_LEN) {
3850                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3851                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3852         } else {
3853                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3854                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3855         }
3856         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3857
3858         /* update max frame size */
3859         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3860
3861         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3862         maxfrs &= 0x0000FFFF;
3863         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3864         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3865
3866         return 0;
3867 }
3868
3869 /*
3870  * Virtual Function operations
3871  */
3872 static void
3873 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3874 {
3875         PMD_INIT_FUNC_TRACE();
3876
3877         /* Clear interrupt mask to stop from interrupts being generated */
3878         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3879
3880         IXGBE_WRITE_FLUSH(hw);
3881 }
3882
3883 static void
3884 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3885 {
3886         PMD_INIT_FUNC_TRACE();
3887
3888         /* VF enable interrupt autoclean */
3889         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3890         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3891         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3892
3893         IXGBE_WRITE_FLUSH(hw);
3894 }
3895
3896 static int
3897 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3898 {
3899         struct rte_eth_conf* conf = &dev->data->dev_conf;
3900         struct ixgbe_adapter *adapter =
3901                         (struct ixgbe_adapter *)dev->data->dev_private;
3902
3903         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3904                      dev->data->port_id);
3905
3906         /*
3907          * VF has no ability to enable/disable HW CRC
3908          * Keep the persistent behavior the same as Host PF
3909          */
3910 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3911         if (!conf->rxmode.hw_strip_crc) {
3912                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3913                 conf->rxmode.hw_strip_crc = 1;
3914         }
3915 #else
3916         if (conf->rxmode.hw_strip_crc) {
3917                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3918                 conf->rxmode.hw_strip_crc = 0;
3919         }
3920 #endif
3921
3922         /*
3923          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3924          * allocation or vector Rx preconditions we will reset it.
3925          */
3926         adapter->rx_bulk_alloc_allowed = true;
3927         adapter->rx_vec_allowed = true;
3928
3929         return 0;
3930 }
3931
3932 static int
3933 ixgbevf_dev_start(struct rte_eth_dev *dev)
3934 {
3935         struct ixgbe_hw *hw =
3936                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3937         uint32_t intr_vector = 0;
3938         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3939
3940         int err, mask = 0;
3941
3942         PMD_INIT_FUNC_TRACE();
3943
3944         hw->mac.ops.reset_hw(hw);
3945         hw->mac.get_link_status = true;
3946
3947         /* negotiate mailbox API version to use with the PF. */
3948         ixgbevf_negotiate_api(hw);
3949
3950         ixgbevf_dev_tx_init(dev);
3951
3952         /* This can fail when allocating mbufs for descriptor rings */
3953         err = ixgbevf_dev_rx_init(dev);
3954         if (err) {
3955                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3956                 ixgbe_dev_clear_queues(dev);
3957                 return err;
3958         }
3959
3960         /* Set vfta */
3961         ixgbevf_set_vfta_all(dev,1);
3962
3963         /* Set HW strip */
3964         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3965                 ETH_VLAN_EXTEND_MASK;
3966         ixgbevf_vlan_offload_set(dev, mask);
3967
3968         ixgbevf_dev_rxtx_start(dev);
3969
3970         /* check and configure queue intr-vector mapping */
3971         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3972                 intr_vector = dev->data->nb_rx_queues;
3973                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3974                         return -1;
3975         }
3976
3977         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3978                 intr_handle->intr_vec =
3979                         rte_zmalloc("intr_vec",
3980                                     dev->data->nb_rx_queues * sizeof(int), 0);
3981                 if (intr_handle->intr_vec == NULL) {
3982                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3983                                      " intr_vec\n", dev->data->nb_rx_queues);
3984                         return -ENOMEM;
3985                 }
3986         }
3987         ixgbevf_configure_msix(dev);
3988
3989         rte_intr_enable(intr_handle);
3990
3991         /* Re-enable interrupt for VF */
3992         ixgbevf_intr_enable(hw);
3993
3994         return 0;
3995 }
3996
3997 static void
3998 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3999 {
4000         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4001         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4002
4003         PMD_INIT_FUNC_TRACE();
4004
4005         hw->adapter_stopped = 1;
4006         ixgbe_stop_adapter(hw);
4007
4008         /*
4009           * Clear what we set, but we still keep shadow_vfta to
4010           * restore after device starts
4011           */
4012         ixgbevf_set_vfta_all(dev,0);
4013
4014         /* Clear stored conf */
4015         dev->data->scattered_rx = 0;
4016
4017         ixgbe_dev_clear_queues(dev);
4018
4019         /* Clean datapath event and queue/vec mapping */
4020         rte_intr_efd_disable(intr_handle);
4021         if (intr_handle->intr_vec != NULL) {
4022                 rte_free(intr_handle->intr_vec);
4023                 intr_handle->intr_vec = NULL;
4024         }
4025 }
4026
4027 static void
4028 ixgbevf_dev_close(struct rte_eth_dev *dev)
4029 {
4030         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4031
4032         PMD_INIT_FUNC_TRACE();
4033
4034         ixgbe_reset_hw(hw);
4035
4036         ixgbevf_dev_stop(dev);
4037
4038         ixgbe_dev_free_queues(dev);
4039
4040         /**
4041          * Remove the VF MAC address ro ensure
4042          * that the VF traffic goes to the PF
4043          * after stop, close and detach of the VF
4044          **/
4045         ixgbevf_remove_mac_addr(dev, 0);
4046 }
4047
4048 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4049 {
4050         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4051         struct ixgbe_vfta * shadow_vfta =
4052                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4053         int i = 0, j = 0, vfta = 0, mask = 1;
4054
4055         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
4056                 vfta = shadow_vfta->vfta[i];
4057                 if (vfta) {
4058                         mask = 1;
4059                         for (j = 0; j < 32; j++){
4060                                 if (vfta & mask)
4061                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
4062                                 mask<<=1;
4063                         }
4064                 }
4065         }
4066
4067 }
4068
4069 static int
4070 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4071 {
4072         struct ixgbe_hw *hw =
4073                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4074         struct ixgbe_vfta * shadow_vfta =
4075                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4076         uint32_t vid_idx = 0;
4077         uint32_t vid_bit = 0;
4078         int ret = 0;
4079
4080         PMD_INIT_FUNC_TRACE();
4081
4082         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4083         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4084         if (ret) {
4085                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4086                 return ret;
4087         }
4088         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4089         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4090
4091         /* Save what we set and retore it after device reset */
4092         if (on)
4093                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4094         else
4095                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4096
4097         return 0;
4098 }
4099
4100 static void
4101 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4102 {
4103         struct ixgbe_hw *hw =
4104                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4105         uint32_t ctrl;
4106
4107         PMD_INIT_FUNC_TRACE();
4108
4109         if (queue >= hw->mac.max_rx_queues)
4110                 return;
4111
4112         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4113         if (on)
4114                 ctrl |= IXGBE_RXDCTL_VME;
4115         else
4116                 ctrl &= ~IXGBE_RXDCTL_VME;
4117         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4118
4119         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4120 }
4121
4122 static void
4123 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4124 {
4125         struct ixgbe_hw *hw =
4126                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4127         uint16_t i;
4128         int on = 0;
4129
4130         /* VF function only support hw strip feature, others are not support */
4131         if (mask & ETH_VLAN_STRIP_MASK) {
4132                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4133
4134                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4135                         ixgbevf_vlan_strip_queue_set(dev,i,on);
4136         }
4137 }
4138
4139 static int
4140 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4141 {
4142         uint32_t reg_val;
4143
4144         /* we only need to do this if VMDq is enabled */
4145         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4146         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4147                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4148                 return -1;
4149         }
4150
4151         return 0;
4152 }
4153
4154 static uint32_t
4155 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4156 {
4157         uint32_t vector = 0;
4158         switch (hw->mac.mc_filter_type) {
4159         case 0:   /* use bits [47:36] of the address */
4160                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4161                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4162                 break;
4163         case 1:   /* use bits [46:35] of the address */
4164                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4165                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4166                 break;
4167         case 2:   /* use bits [45:34] of the address */
4168                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4169                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4170                 break;
4171         case 3:   /* use bits [43:32] of the address */
4172                 vector = ((uc_addr->addr_bytes[4]) |
4173                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4174                 break;
4175         default:  /* Invalid mc_filter_type */
4176                 break;
4177         }
4178
4179         /* vector can only be 12-bits or boundary will be exceeded */
4180         vector &= 0xFFF;
4181         return vector;
4182 }
4183
4184 static int
4185 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4186                                uint8_t on)
4187 {
4188         uint32_t vector;
4189         uint32_t uta_idx;
4190         uint32_t reg_val;
4191         uint32_t uta_shift;
4192         uint32_t rc;
4193         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4194         const uint32_t ixgbe_uta_bit_shift = 5;
4195         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4196         const uint32_t bit1 = 0x1;
4197
4198         struct ixgbe_hw *hw =
4199                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4200         struct ixgbe_uta_info *uta_info =
4201                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4202
4203         /* The UTA table only exists on 82599 hardware and newer */
4204         if (hw->mac.type < ixgbe_mac_82599EB)
4205                 return -ENOTSUP;
4206
4207         vector = ixgbe_uta_vector(hw,mac_addr);
4208         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4209         uta_shift = vector & ixgbe_uta_bit_mask;
4210
4211         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4212         if (rc == on)
4213                 return 0;
4214
4215         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4216         if (on) {
4217                 uta_info->uta_in_use++;
4218                 reg_val |= (bit1 << uta_shift);
4219                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4220         } else {
4221                 uta_info->uta_in_use--;
4222                 reg_val &= ~(bit1 << uta_shift);
4223                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4224         }
4225
4226         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4227
4228         if (uta_info->uta_in_use > 0)
4229                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4230                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4231         else
4232                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4233
4234         return 0;
4235 }
4236
4237 static int
4238 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4239 {
4240         int i;
4241         struct ixgbe_hw *hw =
4242                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4243         struct ixgbe_uta_info *uta_info =
4244                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4245
4246         /* The UTA table only exists on 82599 hardware and newer */
4247         if (hw->mac.type < ixgbe_mac_82599EB)
4248                 return -ENOTSUP;
4249
4250         if (on) {
4251                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4252                         uta_info->uta_shadow[i] = ~0;
4253                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4254                 }
4255         } else {
4256                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4257                         uta_info->uta_shadow[i] = 0;
4258                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4259                 }
4260         }
4261         return 0;
4262
4263 }
4264
4265 uint32_t
4266 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4267 {
4268         uint32_t new_val = orig_val;
4269
4270         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4271                 new_val |= IXGBE_VMOLR_AUPE;
4272         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4273                 new_val |= IXGBE_VMOLR_ROMPE;
4274         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4275                 new_val |= IXGBE_VMOLR_ROPE;
4276         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4277                 new_val |= IXGBE_VMOLR_BAM;
4278         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4279                 new_val |= IXGBE_VMOLR_MPE;
4280
4281         return new_val;
4282 }
4283
4284 static int
4285 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4286                                uint16_t rx_mask, uint8_t on)
4287 {
4288         int val = 0;
4289
4290         struct ixgbe_hw *hw =
4291                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4292         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4293
4294         if (hw->mac.type == ixgbe_mac_82598EB) {
4295                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4296                              " on 82599 hardware and newer");
4297                 return -ENOTSUP;
4298         }
4299         if (ixgbe_vmdq_mode_check(hw) < 0)
4300                 return -ENOTSUP;
4301
4302         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4303
4304         if (on)
4305                 vmolr |= val;
4306         else
4307                 vmolr &= ~val;
4308
4309         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4310
4311         return 0;
4312 }
4313
4314 static int
4315 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4316 {
4317         uint32_t reg,addr;
4318         uint32_t val;
4319         const uint8_t bit1 = 0x1;
4320
4321         struct ixgbe_hw *hw =
4322                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4323
4324         if (ixgbe_vmdq_mode_check(hw) < 0)
4325                 return -ENOTSUP;
4326
4327         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4328         reg = IXGBE_READ_REG(hw, addr);
4329         val = bit1 << pool;
4330
4331         if (on)
4332                 reg |= val;
4333         else
4334                 reg &= ~val;
4335
4336         IXGBE_WRITE_REG(hw, addr,reg);
4337
4338         return 0;
4339 }
4340
4341 static int
4342 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4343 {
4344         uint32_t reg,addr;
4345         uint32_t val;
4346         const uint8_t bit1 = 0x1;
4347
4348         struct ixgbe_hw *hw =
4349                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4350
4351         if (ixgbe_vmdq_mode_check(hw) < 0)
4352                 return -ENOTSUP;
4353
4354         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4355         reg = IXGBE_READ_REG(hw, addr);
4356         val = bit1 << pool;
4357
4358         if (on)
4359                 reg |= val;
4360         else
4361                 reg &= ~val;
4362
4363         IXGBE_WRITE_REG(hw, addr,reg);
4364
4365         return 0;
4366 }
4367
4368 static int
4369 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4370                         uint64_t pool_mask, uint8_t vlan_on)
4371 {
4372         int ret = 0;
4373         uint16_t pool_idx;
4374         struct ixgbe_hw *hw =
4375                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4376
4377         if (ixgbe_vmdq_mode_check(hw) < 0)
4378                 return -ENOTSUP;
4379         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4380                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4381                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4382                         if (ret < 0)
4383                                 return ret;
4384         }
4385
4386         return ret;
4387 }
4388
4389 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4390 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4391 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4392 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4393 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4394         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4395         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4396
4397 static int
4398 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4399                         struct rte_eth_mirror_conf *mirror_conf,
4400                         uint8_t rule_id, uint8_t on)
4401 {
4402         uint32_t mr_ctl,vlvf;
4403         uint32_t mp_lsb = 0;
4404         uint32_t mv_msb = 0;
4405         uint32_t mv_lsb = 0;
4406         uint32_t mp_msb = 0;
4407         uint8_t i = 0;
4408         int reg_index = 0;
4409         uint64_t vlan_mask = 0;
4410
4411         const uint8_t pool_mask_offset = 32;
4412         const uint8_t vlan_mask_offset = 32;
4413         const uint8_t dst_pool_offset = 8;
4414         const uint8_t rule_mr_offset  = 4;
4415         const uint8_t mirror_rule_mask= 0x0F;
4416
4417         struct ixgbe_mirror_info *mr_info =
4418                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4419         struct ixgbe_hw *hw =
4420                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4421         uint8_t mirror_type = 0;
4422
4423         if (ixgbe_vmdq_mode_check(hw) < 0)
4424                 return -ENOTSUP;
4425
4426         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4427                 return -EINVAL;
4428
4429         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4430                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4431                         mirror_conf->rule_type);
4432                 return -EINVAL;
4433         }
4434
4435         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4436                 mirror_type |= IXGBE_MRCTL_VLME;
4437                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4438                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4439                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4440                                 /* search vlan id related pool vlan filter index */
4441                                 reg_index = ixgbe_find_vlvf_slot(hw,
4442                                                 mirror_conf->vlan.vlan_id[i]);
4443                                 if (reg_index < 0)
4444                                         return -EINVAL;
4445                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4446                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4447                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4448                                       mirror_conf->vlan.vlan_id[i]))
4449                                         vlan_mask |= (1ULL << reg_index);
4450                                 else
4451                                         return -EINVAL;
4452                         }
4453                 }
4454
4455                 if (on) {
4456                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4457                         mv_msb = vlan_mask >> vlan_mask_offset;
4458
4459                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4460                                                 mirror_conf->vlan.vlan_mask;
4461                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4462                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4463                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4464                                                 mirror_conf->vlan.vlan_id[i];
4465                         }
4466                 } else {
4467                         mv_lsb = 0;
4468                         mv_msb = 0;
4469                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4470                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4471                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4472                 }
4473         }
4474
4475         /*
4476          * if enable pool mirror, write related pool mask register,if disable
4477          * pool mirror, clear PFMRVM register
4478          */
4479         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4480                 mirror_type |= IXGBE_MRCTL_VPME;
4481                 if (on) {
4482                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4483                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4484                         mr_info->mr_conf[rule_id].pool_mask =
4485                                         mirror_conf->pool_mask;
4486
4487                 } else {
4488                         mp_lsb = 0;
4489                         mp_msb = 0;
4490                         mr_info->mr_conf[rule_id].pool_mask = 0;
4491                 }
4492         }
4493         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4494                 mirror_type |= IXGBE_MRCTL_UPME;
4495         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4496                 mirror_type |= IXGBE_MRCTL_DPME;
4497
4498         /* read  mirror control register and recalculate it */
4499         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4500
4501         if (on) {
4502                 mr_ctl |= mirror_type;
4503                 mr_ctl &= mirror_rule_mask;
4504                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4505         } else
4506                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4507
4508         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4509         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4510
4511         /* write mirrror control  register */
4512         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4513
4514         /* write pool mirrror control  register */
4515         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4516                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4517                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4518                                 mp_msb);
4519         }
4520         /* write VLAN mirrror control  register */
4521         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4522                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4523                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4524                                 mv_msb);
4525         }
4526
4527         return 0;
4528 }
4529
4530 static int
4531 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4532 {
4533         int mr_ctl = 0;
4534         uint32_t lsb_val = 0;
4535         uint32_t msb_val = 0;
4536         const uint8_t rule_mr_offset = 4;
4537
4538         struct ixgbe_hw *hw =
4539                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4540         struct ixgbe_mirror_info *mr_info =
4541                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4542
4543         if (ixgbe_vmdq_mode_check(hw) < 0)
4544                 return -ENOTSUP;
4545
4546         memset(&mr_info->mr_conf[rule_id], 0,
4547                 sizeof(struct rte_eth_mirror_conf));
4548
4549         /* clear PFVMCTL register */
4550         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4551
4552         /* clear pool mask register */
4553         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4554         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4555
4556         /* clear vlan mask register */
4557         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4558         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4559
4560         return 0;
4561 }
4562
4563 static int
4564 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4565 {
4566         uint32_t mask;
4567         struct ixgbe_hw *hw =
4568                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4569
4570         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4571         mask |= (1 << IXGBE_MISC_VEC_ID);
4572         RTE_SET_USED(queue_id);
4573         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4574
4575         rte_intr_enable(&dev->pci_dev->intr_handle);
4576
4577         return 0;
4578 }
4579
4580 static int
4581 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4582 {
4583         uint32_t mask;
4584         struct ixgbe_hw *hw =
4585                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4586
4587         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4588         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4589         RTE_SET_USED(queue_id);
4590         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4591
4592         return 0;
4593 }
4594
4595 static int
4596 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4597 {
4598         uint32_t mask;
4599         struct ixgbe_hw *hw =
4600                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4601         struct ixgbe_interrupt *intr =
4602                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4603
4604         if (queue_id < 16) {
4605                 ixgbe_disable_intr(hw);
4606                 intr->mask |= (1 << queue_id);
4607                 ixgbe_enable_intr(dev);
4608         } else if (queue_id < 32) {
4609                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4610                 mask &= (1 << queue_id);
4611                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4612         } else if (queue_id < 64) {
4613                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4614                 mask &= (1 << (queue_id - 32));
4615                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4616         }
4617         rte_intr_enable(&dev->pci_dev->intr_handle);
4618
4619         return 0;
4620 }
4621
4622 static int
4623 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4624 {
4625         uint32_t mask;
4626         struct ixgbe_hw *hw =
4627                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4628         struct ixgbe_interrupt *intr =
4629                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4630
4631         if (queue_id < 16) {
4632                 ixgbe_disable_intr(hw);
4633                 intr->mask &= ~(1 << queue_id);
4634                 ixgbe_enable_intr(dev);
4635         } else if (queue_id < 32) {
4636                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4637                 mask &= ~(1 << queue_id);
4638                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4639         } else if (queue_id < 64) {
4640                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4641                 mask &= ~(1 << (queue_id - 32));
4642                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4643         }
4644
4645         return 0;
4646 }
4647
4648 static void
4649 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4650                      uint8_t queue, uint8_t msix_vector)
4651 {
4652         uint32_t tmp, idx;
4653
4654         if (direction == -1) {
4655                 /* other causes */
4656                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4657                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4658                 tmp &= ~0xFF;
4659                 tmp |= msix_vector;
4660                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4661         } else {
4662                 /* rx or tx cause */
4663                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4664                 idx = ((16 * (queue & 1)) + (8 * direction));
4665                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4666                 tmp &= ~(0xFF << idx);
4667                 tmp |= (msix_vector << idx);
4668                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4669         }
4670 }
4671
4672 /**
4673  * set the IVAR registers, mapping interrupt causes to vectors
4674  * @param hw
4675  *  pointer to ixgbe_hw struct
4676  * @direction
4677  *  0 for Rx, 1 for Tx, -1 for other causes
4678  * @queue
4679  *  queue to map the corresponding interrupt to
4680  * @msix_vector
4681  *  the vector to map to the corresponding queue
4682  */
4683 static void
4684 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4685                    uint8_t queue, uint8_t msix_vector)
4686 {
4687         uint32_t tmp, idx;
4688
4689         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4690         if (hw->mac.type == ixgbe_mac_82598EB) {
4691                 if (direction == -1)
4692                         direction = 0;
4693                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4694                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4695                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4696                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4697                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4698         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4699                         (hw->mac.type == ixgbe_mac_X540)) {
4700                 if (direction == -1) {
4701                         /* other causes */
4702                         idx = ((queue & 1) * 8);
4703                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4704                         tmp &= ~(0xFF << idx);
4705                         tmp |= (msix_vector << idx);
4706                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4707                 } else {
4708                         /* rx or tx causes */
4709                         idx = ((16 * (queue & 1)) + (8 * direction));
4710                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4711                         tmp &= ~(0xFF << idx);
4712                         tmp |= (msix_vector << idx);
4713                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4714                 }
4715         }
4716 }
4717
4718 static void
4719 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4720 {
4721         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4722         struct ixgbe_hw *hw =
4723                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4724         uint32_t q_idx;
4725         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4726
4727         /* won't configure msix register if no mapping is done
4728          * between intr vector and event fd.
4729          */
4730         if (!rte_intr_dp_is_en(intr_handle))
4731                 return;
4732
4733         /* Configure all RX queues of VF */
4734         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4735                 /* Force all queue use vector 0,
4736                  * as IXGBE_VF_MAXMSIVECOTR = 1
4737                  */
4738                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4739                 intr_handle->intr_vec[q_idx] = vector_idx;
4740         }
4741
4742         /* Configure VF other cause ivar */
4743         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4744 }
4745
4746 /**
4747  * Sets up the hardware to properly generate MSI-X interrupts
4748  * @hw
4749  *  board private structure
4750  */
4751 static void
4752 ixgbe_configure_msix(struct rte_eth_dev *dev)
4753 {
4754         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4755         struct ixgbe_hw *hw =
4756                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4757         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4758         uint32_t vec = IXGBE_MISC_VEC_ID;
4759         uint32_t mask;
4760         uint32_t gpie;
4761
4762         /* won't configure msix register if no mapping is done
4763          * between intr vector and event fd
4764          */
4765         if (!rte_intr_dp_is_en(intr_handle))
4766                 return;
4767
4768         if (rte_intr_allow_others(intr_handle))
4769                 vec = base = IXGBE_RX_VEC_START;
4770
4771         /* setup GPIE for MSI-x mode */
4772         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4773         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4774                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4775         /* auto clearing and auto setting corresponding bits in EIMS
4776          * when MSI-X interrupt is triggered
4777          */
4778         if (hw->mac.type == ixgbe_mac_82598EB) {
4779                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4780         } else {
4781                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4782                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4783         }
4784         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4785
4786         /* Populate the IVAR table and set the ITR values to the
4787          * corresponding register.
4788          */
4789         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4790              queue_id++) {
4791                 /* by default, 1:1 mapping */
4792                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4793                 intr_handle->intr_vec[queue_id] = vec;
4794                 if (vec < base + intr_handle->nb_efd - 1)
4795                         vec++;
4796         }
4797
4798         switch (hw->mac.type) {
4799         case ixgbe_mac_82598EB:
4800                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4801                                    IXGBE_MISC_VEC_ID);
4802                 break;
4803         case ixgbe_mac_82599EB:
4804         case ixgbe_mac_X540:
4805                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4806                 break;
4807         default:
4808                 break;
4809         }
4810         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4811                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4812
4813         /* set up to autoclear timer, and the vectors */
4814         mask = IXGBE_EIMS_ENABLE_MASK;
4815         mask &= ~(IXGBE_EIMS_OTHER |
4816                   IXGBE_EIMS_MAILBOX |
4817                   IXGBE_EIMS_LSC);
4818
4819         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4820 }
4821
4822 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4823         uint16_t queue_idx, uint16_t tx_rate)
4824 {
4825         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4826         uint32_t rf_dec, rf_int;
4827         uint32_t bcnrc_val;
4828         uint16_t link_speed = dev->data->dev_link.link_speed;
4829
4830         if (queue_idx >= hw->mac.max_tx_queues)
4831                 return -EINVAL;
4832
4833         if (tx_rate != 0) {
4834                 /* Calculate the rate factor values to set */
4835                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4836                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4837                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4838
4839                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4840                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4841                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4842                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4843         } else {
4844                 bcnrc_val = 0;
4845         }
4846
4847         /*
4848          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4849          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4850          * set as 0x4.
4851          */
4852         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4853                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4854                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4855                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4856                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4857         else
4858                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4859                         IXGBE_MMW_SIZE_DEFAULT);
4860
4861         /* Set RTTBCNRC of queue X */
4862         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4863         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4864         IXGBE_WRITE_FLUSH(hw);
4865
4866         return 0;
4867 }
4868
4869 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4870         uint16_t tx_rate, uint64_t q_msk)
4871 {
4872         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4873         struct ixgbe_vf_info *vfinfo =
4874                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4875         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4876         uint32_t queue_stride =
4877                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4878         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4879         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4880         uint16_t total_rate = 0;
4881
4882         if (queue_end >= hw->mac.max_tx_queues)
4883                 return -EINVAL;
4884
4885         if (vfinfo != NULL) {
4886                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4887                         if (vf_idx == vf)
4888                                 continue;
4889                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4890                                 idx++)
4891                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4892                 }
4893         } else
4894                 return -EINVAL;
4895
4896         /* Store tx_rate for this vf. */
4897         for (idx = 0; idx < nb_q_per_pool; idx++) {
4898                 if (((uint64_t)0x1 << idx) & q_msk) {
4899                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
4900                                 vfinfo[vf].tx_rate[idx] = tx_rate;
4901                         total_rate += tx_rate;
4902                 }
4903         }
4904
4905         if (total_rate > dev->data->dev_link.link_speed) {
4906                 /*
4907                  * Reset stored TX rate of the VF if it causes exceed
4908                  * link speed.
4909                  */
4910                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4911                 return -EINVAL;
4912         }
4913
4914         /* Set RTTBCNRC of each queue/pool for vf X  */
4915         for (; queue_idx <= queue_end; queue_idx++) {
4916                 if (0x1 & q_msk)
4917                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4918                 q_msk = q_msk >> 1;
4919         }
4920
4921         return 0;
4922 }
4923
4924 static void
4925 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4926                      __attribute__((unused)) uint32_t index,
4927                      __attribute__((unused)) uint32_t pool)
4928 {
4929         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4930         int diag;
4931
4932         /*
4933          * On a 82599 VF, adding again the same MAC addr is not an idempotent
4934          * operation. Trap this case to avoid exhausting the [very limited]
4935          * set of PF resources used to store VF MAC addresses.
4936          */
4937         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4938                 return;
4939         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4940         if (diag == 0)
4941                 return;
4942         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4943 }
4944
4945 static void
4946 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4947 {
4948         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4949         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4950         struct ether_addr *mac_addr;
4951         uint32_t i;
4952         int diag;
4953
4954         /*
4955          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4956          * not support the deletion of a given MAC address.
4957          * Instead, it imposes to delete all MAC addresses, then to add again
4958          * all MAC addresses with the exception of the one to be deleted.
4959          */
4960         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4961
4962         /*
4963          * Add again all MAC addresses, with the exception of the deleted one
4964          * and of the permanent MAC address.
4965          */
4966         for (i = 0, mac_addr = dev->data->mac_addrs;
4967              i < hw->mac.num_rar_entries; i++, mac_addr++) {
4968                 /* Skip the deleted MAC address */
4969                 if (i == index)
4970                         continue;
4971                 /* Skip NULL MAC addresses */
4972                 if (is_zero_ether_addr(mac_addr))
4973                         continue;
4974                 /* Skip the permanent MAC address */
4975                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4976                         continue;
4977                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4978                 if (diag != 0)
4979                         PMD_DRV_LOG(ERR,
4980                                     "Adding again MAC address "
4981                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
4982                                     "diag=%d",
4983                                     mac_addr->addr_bytes[0],
4984                                     mac_addr->addr_bytes[1],
4985                                     mac_addr->addr_bytes[2],
4986                                     mac_addr->addr_bytes[3],
4987                                     mac_addr->addr_bytes[4],
4988                                     mac_addr->addr_bytes[5],
4989                                     diag);
4990         }
4991 }
4992
4993 static void
4994 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4995 {
4996         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4997
4998         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4999 }
5000
5001 #define MAC_TYPE_FILTER_SUP(type)    do {\
5002         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5003                 (type) != ixgbe_mac_X550)\
5004                 return -ENOTSUP;\
5005 } while (0)
5006
5007 static int
5008 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5009                         struct rte_eth_syn_filter *filter,
5010                         bool add)
5011 {
5012         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5013         uint32_t synqf;
5014
5015         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5016                 return -EINVAL;
5017
5018         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5019
5020         if (add) {
5021                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5022                         return -EINVAL;
5023                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5024                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5025
5026                 if (filter->hig_pri)
5027                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5028                 else
5029                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5030         } else {
5031                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5032                         return -ENOENT;
5033                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5034         }
5035         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5036         IXGBE_WRITE_FLUSH(hw);
5037         return 0;
5038 }
5039
5040 static int
5041 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5042                         struct rte_eth_syn_filter *filter)
5043 {
5044         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5045         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5046
5047         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5048                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5049                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5050                 return 0;
5051         }
5052         return -ENOENT;
5053 }
5054
5055 static int
5056 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5057                         enum rte_filter_op filter_op,
5058                         void *arg)
5059 {
5060         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5061         int ret;
5062
5063         MAC_TYPE_FILTER_SUP(hw->mac.type);
5064
5065         if (filter_op == RTE_ETH_FILTER_NOP)
5066                 return 0;
5067
5068         if (arg == NULL) {
5069                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5070                             filter_op);
5071                 return -EINVAL;
5072         }
5073
5074         switch (filter_op) {
5075         case RTE_ETH_FILTER_ADD:
5076                 ret = ixgbe_syn_filter_set(dev,
5077                                 (struct rte_eth_syn_filter *)arg,
5078                                 TRUE);
5079                 break;
5080         case RTE_ETH_FILTER_DELETE:
5081                 ret = ixgbe_syn_filter_set(dev,
5082                                 (struct rte_eth_syn_filter *)arg,
5083                                 FALSE);
5084                 break;
5085         case RTE_ETH_FILTER_GET:
5086                 ret = ixgbe_syn_filter_get(dev,
5087                                 (struct rte_eth_syn_filter *)arg);
5088                 break;
5089         default:
5090                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5091                 ret = -EINVAL;
5092                 break;
5093         }
5094
5095         return ret;
5096 }
5097
5098
5099 static inline enum ixgbe_5tuple_protocol
5100 convert_protocol_type(uint8_t protocol_value)
5101 {
5102         if (protocol_value == IPPROTO_TCP)
5103                 return IXGBE_FILTER_PROTOCOL_TCP;
5104         else if (protocol_value == IPPROTO_UDP)
5105                 return IXGBE_FILTER_PROTOCOL_UDP;
5106         else if (protocol_value == IPPROTO_SCTP)
5107                 return IXGBE_FILTER_PROTOCOL_SCTP;
5108         else
5109                 return IXGBE_FILTER_PROTOCOL_NONE;
5110 }
5111
5112 /*
5113  * add a 5tuple filter
5114  *
5115  * @param
5116  * dev: Pointer to struct rte_eth_dev.
5117  * index: the index the filter allocates.
5118  * filter: ponter to the filter that will be added.
5119  * rx_queue: the queue id the filter assigned to.
5120  *
5121  * @return
5122  *    - On success, zero.
5123  *    - On failure, a negative value.
5124  */
5125 static int
5126 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5127                         struct ixgbe_5tuple_filter *filter)
5128 {
5129         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5130         struct ixgbe_filter_info *filter_info =
5131                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5132         int i, idx, shift;
5133         uint32_t ftqf, sdpqf;
5134         uint32_t l34timir = 0;
5135         uint8_t mask = 0xff;
5136
5137         /*
5138          * look for an unused 5tuple filter index,
5139          * and insert the filter to list.
5140          */
5141         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5142                 idx = i / (sizeof(uint32_t) * NBBY);
5143                 shift = i % (sizeof(uint32_t) * NBBY);
5144                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5145                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5146                         filter->index = i;
5147                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5148                                           filter,
5149                                           entries);
5150                         break;
5151                 }
5152         }
5153         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5154                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5155                 return -ENOSYS;
5156         }
5157
5158         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5159                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5160         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5161
5162         ftqf = (uint32_t)(filter->filter_info.proto &
5163                 IXGBE_FTQF_PROTOCOL_MASK);
5164         ftqf |= (uint32_t)((filter->filter_info.priority &
5165                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5166         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5167                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5168         if (filter->filter_info.dst_ip_mask == 0)
5169                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5170         if (filter->filter_info.src_port_mask == 0)
5171                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5172         if (filter->filter_info.dst_port_mask == 0)
5173                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5174         if (filter->filter_info.proto_mask == 0)
5175                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5176         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5177         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5178         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5179
5180         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5181         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5182         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5183         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5184
5185         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5186         l34timir |= (uint32_t)(filter->queue <<
5187                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5188         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5189         return 0;
5190 }
5191
5192 /*
5193  * remove a 5tuple filter
5194  *
5195  * @param
5196  * dev: Pointer to struct rte_eth_dev.
5197  * filter: the pointer of the filter will be removed.
5198  */
5199 static void
5200 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5201                         struct ixgbe_5tuple_filter *filter)
5202 {
5203         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5204         struct ixgbe_filter_info *filter_info =
5205                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5206         uint16_t index = filter->index;
5207
5208         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5209                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5210         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5211         rte_free(filter);
5212
5213         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5214         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5215         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5216         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5217         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5218 }
5219
5220 static int
5221 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5222 {
5223         struct ixgbe_hw *hw;
5224         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5225
5226         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5227
5228         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5229                 return -EINVAL;
5230
5231         /* refuse mtu that requires the support of scattered packets when this
5232          * feature has not been enabled before. */
5233         if (!dev->data->scattered_rx &&
5234             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5235              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5236                 return -EINVAL;
5237
5238         /*
5239          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5240          * request of the version 2.0 of the mailbox API.
5241          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5242          * of the mailbox API.
5243          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5244          * prior to 3.11.33 which contains the following change:
5245          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5246          */
5247         ixgbevf_rlpml_set_vf(hw, max_frame);
5248
5249         /* update max frame size */
5250         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5251         return 0;
5252 }
5253
5254 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5255         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5256                 return -ENOTSUP;\
5257 } while (0)
5258
5259 static inline struct ixgbe_5tuple_filter *
5260 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5261                         struct ixgbe_5tuple_filter_info *key)
5262 {
5263         struct ixgbe_5tuple_filter *it;
5264
5265         TAILQ_FOREACH(it, filter_list, entries) {
5266                 if (memcmp(key, &it->filter_info,
5267                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5268                         return it;
5269                 }
5270         }
5271         return NULL;
5272 }
5273
5274 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5275 static inline int
5276 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5277                         struct ixgbe_5tuple_filter_info *filter_info)
5278 {
5279         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5280                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5281                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5282                 return -EINVAL;
5283
5284         switch (filter->dst_ip_mask) {
5285         case UINT32_MAX:
5286                 filter_info->dst_ip_mask = 0;
5287                 filter_info->dst_ip = filter->dst_ip;
5288                 break;
5289         case 0:
5290                 filter_info->dst_ip_mask = 1;
5291                 break;
5292         default:
5293                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5294                 return -EINVAL;
5295         }
5296
5297         switch (filter->src_ip_mask) {
5298         case UINT32_MAX:
5299                 filter_info->src_ip_mask = 0;
5300                 filter_info->src_ip = filter->src_ip;
5301                 break;
5302         case 0:
5303                 filter_info->src_ip_mask = 1;
5304                 break;
5305         default:
5306                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5307                 return -EINVAL;
5308         }
5309
5310         switch (filter->dst_port_mask) {
5311         case UINT16_MAX:
5312                 filter_info->dst_port_mask = 0;
5313                 filter_info->dst_port = filter->dst_port;
5314                 break;
5315         case 0:
5316                 filter_info->dst_port_mask = 1;
5317                 break;
5318         default:
5319                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5320                 return -EINVAL;
5321         }
5322
5323         switch (filter->src_port_mask) {
5324         case UINT16_MAX:
5325                 filter_info->src_port_mask = 0;
5326                 filter_info->src_port = filter->src_port;
5327                 break;
5328         case 0:
5329                 filter_info->src_port_mask = 1;
5330                 break;
5331         default:
5332                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5333                 return -EINVAL;
5334         }
5335
5336         switch (filter->proto_mask) {
5337         case UINT8_MAX:
5338                 filter_info->proto_mask = 0;
5339                 filter_info->proto =
5340                         convert_protocol_type(filter->proto);
5341                 break;
5342         case 0:
5343                 filter_info->proto_mask = 1;
5344                 break;
5345         default:
5346                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5347                 return -EINVAL;
5348         }
5349
5350         filter_info->priority = (uint8_t)filter->priority;
5351         return 0;
5352 }
5353
5354 /*
5355  * add or delete a ntuple filter
5356  *
5357  * @param
5358  * dev: Pointer to struct rte_eth_dev.
5359  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5360  * add: if true, add filter, if false, remove filter
5361  *
5362  * @return
5363  *    - On success, zero.
5364  *    - On failure, a negative value.
5365  */
5366 static int
5367 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5368                         struct rte_eth_ntuple_filter *ntuple_filter,
5369                         bool add)
5370 {
5371         struct ixgbe_filter_info *filter_info =
5372                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5373         struct ixgbe_5tuple_filter_info filter_5tuple;
5374         struct ixgbe_5tuple_filter *filter;
5375         int ret;
5376
5377         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5378                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5379                 return -EINVAL;
5380         }
5381
5382         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5383         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5384         if (ret < 0)
5385                 return ret;
5386
5387         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5388                                          &filter_5tuple);
5389         if (filter != NULL && add) {
5390                 PMD_DRV_LOG(ERR, "filter exists.");
5391                 return -EEXIST;
5392         }
5393         if (filter == NULL && !add) {
5394                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5395                 return -ENOENT;
5396         }
5397
5398         if (add) {
5399                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5400                                 sizeof(struct ixgbe_5tuple_filter), 0);
5401                 if (filter == NULL)
5402                         return -ENOMEM;
5403                 (void)rte_memcpy(&filter->filter_info,
5404                                  &filter_5tuple,
5405                                  sizeof(struct ixgbe_5tuple_filter_info));
5406                 filter->queue = ntuple_filter->queue;
5407                 ret = ixgbe_add_5tuple_filter(dev, filter);
5408                 if (ret < 0) {
5409                         rte_free(filter);
5410                         return ret;
5411                 }
5412         } else
5413                 ixgbe_remove_5tuple_filter(dev, filter);
5414
5415         return 0;
5416 }
5417
5418 /*
5419  * get a ntuple filter
5420  *
5421  * @param
5422  * dev: Pointer to struct rte_eth_dev.
5423  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5424  *
5425  * @return
5426  *    - On success, zero.
5427  *    - On failure, a negative value.
5428  */
5429 static int
5430 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5431                         struct rte_eth_ntuple_filter *ntuple_filter)
5432 {
5433         struct ixgbe_filter_info *filter_info =
5434                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5435         struct ixgbe_5tuple_filter_info filter_5tuple;
5436         struct ixgbe_5tuple_filter *filter;
5437         int ret;
5438
5439         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5440                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5441                 return -EINVAL;
5442         }
5443
5444         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5445         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5446         if (ret < 0)
5447                 return ret;
5448
5449         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5450                                          &filter_5tuple);
5451         if (filter == NULL) {
5452                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5453                 return -ENOENT;
5454         }
5455         ntuple_filter->queue = filter->queue;
5456         return 0;
5457 }
5458
5459 /*
5460  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5461  * @dev: pointer to rte_eth_dev structure
5462  * @filter_op:operation will be taken.
5463  * @arg: a pointer to specific structure corresponding to the filter_op
5464  *
5465  * @return
5466  *    - On success, zero.
5467  *    - On failure, a negative value.
5468  */
5469 static int
5470 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5471                                 enum rte_filter_op filter_op,
5472                                 void *arg)
5473 {
5474         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5475         int ret;
5476
5477         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5478
5479         if (filter_op == RTE_ETH_FILTER_NOP)
5480                 return 0;
5481
5482         if (arg == NULL) {
5483                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5484                             filter_op);
5485                 return -EINVAL;
5486         }
5487
5488         switch (filter_op) {
5489         case RTE_ETH_FILTER_ADD:
5490                 ret = ixgbe_add_del_ntuple_filter(dev,
5491                         (struct rte_eth_ntuple_filter *)arg,
5492                         TRUE);
5493                 break;
5494         case RTE_ETH_FILTER_DELETE:
5495                 ret = ixgbe_add_del_ntuple_filter(dev,
5496                         (struct rte_eth_ntuple_filter *)arg,
5497                         FALSE);
5498                 break;
5499         case RTE_ETH_FILTER_GET:
5500                 ret = ixgbe_get_ntuple_filter(dev,
5501                         (struct rte_eth_ntuple_filter *)arg);
5502                 break;
5503         default:
5504                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5505                 ret = -EINVAL;
5506                 break;
5507         }
5508         return ret;
5509 }
5510
5511 static inline int
5512 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5513                         uint16_t ethertype)
5514 {
5515         int i;
5516
5517         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5518                 if (filter_info->ethertype_filters[i] == ethertype &&
5519                     (filter_info->ethertype_mask & (1 << i)))
5520                         return i;
5521         }
5522         return -1;
5523 }
5524
5525 static inline int
5526 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5527                         uint16_t ethertype)
5528 {
5529         int i;
5530
5531         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5532                 if (!(filter_info->ethertype_mask & (1 << i))) {
5533                         filter_info->ethertype_mask |= 1 << i;
5534                         filter_info->ethertype_filters[i] = ethertype;
5535                         return i;
5536                 }
5537         }
5538         return -1;
5539 }
5540
5541 static inline int
5542 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5543                         uint8_t idx)
5544 {
5545         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5546                 return -1;
5547         filter_info->ethertype_mask &= ~(1 << idx);
5548         filter_info->ethertype_filters[idx] = 0;
5549         return idx;
5550 }
5551
5552 static int
5553 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5554                         struct rte_eth_ethertype_filter *filter,
5555                         bool add)
5556 {
5557         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5558         struct ixgbe_filter_info *filter_info =
5559                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5560         uint32_t etqf = 0;
5561         uint32_t etqs = 0;
5562         int ret;
5563
5564         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5565                 return -EINVAL;
5566
5567         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5568                 filter->ether_type == ETHER_TYPE_IPv6) {
5569                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5570                         " ethertype filter.", filter->ether_type);
5571                 return -EINVAL;
5572         }
5573
5574         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5575                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5576                 return -EINVAL;
5577         }
5578         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5579                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5580                 return -EINVAL;
5581         }
5582
5583         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5584         if (ret >= 0 && add) {
5585                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5586                             filter->ether_type);
5587                 return -EEXIST;
5588         }
5589         if (ret < 0 && !add) {
5590                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5591                             filter->ether_type);
5592                 return -ENOENT;
5593         }
5594
5595         if (add) {
5596                 ret = ixgbe_ethertype_filter_insert(filter_info,
5597                         filter->ether_type);
5598                 if (ret < 0) {
5599                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5600                         return -ENOSYS;
5601                 }
5602                 etqf = IXGBE_ETQF_FILTER_EN;
5603                 etqf |= (uint32_t)filter->ether_type;
5604                 etqs |= (uint32_t)((filter->queue <<
5605                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5606                                     IXGBE_ETQS_RX_QUEUE);
5607                 etqs |= IXGBE_ETQS_QUEUE_EN;
5608         } else {
5609                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5610                 if (ret < 0)
5611                         return -ENOSYS;
5612         }
5613         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5614         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5615         IXGBE_WRITE_FLUSH(hw);
5616
5617         return 0;
5618 }
5619
5620 static int
5621 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5622                         struct rte_eth_ethertype_filter *filter)
5623 {
5624         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5625         struct ixgbe_filter_info *filter_info =
5626                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5627         uint32_t etqf, etqs;
5628         int ret;
5629
5630         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5631         if (ret < 0) {
5632                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5633                             filter->ether_type);
5634                 return -ENOENT;
5635         }
5636
5637         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5638         if (etqf & IXGBE_ETQF_FILTER_EN) {
5639                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5640                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5641                 filter->flags = 0;
5642                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5643                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5644                 return 0;
5645         }
5646         return -ENOENT;
5647 }
5648
5649 /*
5650  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5651  * @dev: pointer to rte_eth_dev structure
5652  * @filter_op:operation will be taken.
5653  * @arg: a pointer to specific structure corresponding to the filter_op
5654  */
5655 static int
5656 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5657                                 enum rte_filter_op filter_op,
5658                                 void *arg)
5659 {
5660         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5661         int ret;
5662
5663         MAC_TYPE_FILTER_SUP(hw->mac.type);
5664
5665         if (filter_op == RTE_ETH_FILTER_NOP)
5666                 return 0;
5667
5668         if (arg == NULL) {
5669                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5670                             filter_op);
5671                 return -EINVAL;
5672         }
5673
5674         switch (filter_op) {
5675         case RTE_ETH_FILTER_ADD:
5676                 ret = ixgbe_add_del_ethertype_filter(dev,
5677                         (struct rte_eth_ethertype_filter *)arg,
5678                         TRUE);
5679                 break;
5680         case RTE_ETH_FILTER_DELETE:
5681                 ret = ixgbe_add_del_ethertype_filter(dev,
5682                         (struct rte_eth_ethertype_filter *)arg,
5683                         FALSE);
5684                 break;
5685         case RTE_ETH_FILTER_GET:
5686                 ret = ixgbe_get_ethertype_filter(dev,
5687                         (struct rte_eth_ethertype_filter *)arg);
5688                 break;
5689         default:
5690                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5691                 ret = -EINVAL;
5692                 break;
5693         }
5694         return ret;
5695 }
5696
5697 static int
5698 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5699                      enum rte_filter_type filter_type,
5700                      enum rte_filter_op filter_op,
5701                      void *arg)
5702 {
5703         int ret = -EINVAL;
5704
5705         switch (filter_type) {
5706         case RTE_ETH_FILTER_NTUPLE:
5707                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5708                 break;
5709         case RTE_ETH_FILTER_ETHERTYPE:
5710                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5711                 break;
5712         case RTE_ETH_FILTER_SYN:
5713                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5714                 break;
5715         case RTE_ETH_FILTER_FDIR:
5716                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5717                 break;
5718         case RTE_ETH_FILTER_L2_TUNNEL:
5719                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5720                 break;
5721         default:
5722                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5723                                                         filter_type);
5724                 break;
5725         }
5726
5727         return ret;
5728 }
5729
5730 static u8 *
5731 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5732                         u8 **mc_addr_ptr, u32 *vmdq)
5733 {
5734         u8 *mc_addr;
5735
5736         *vmdq = 0;
5737         mc_addr = *mc_addr_ptr;
5738         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5739         return mc_addr;
5740 }
5741
5742 static int
5743 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5744                           struct ether_addr *mc_addr_set,
5745                           uint32_t nb_mc_addr)
5746 {
5747         struct ixgbe_hw *hw;
5748         u8 *mc_addr_list;
5749
5750         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5751         mc_addr_list = (u8 *)mc_addr_set;
5752         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5753                                          ixgbe_dev_addr_list_itr, TRUE);
5754 }
5755
5756 static uint64_t
5757 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5758 {
5759         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5760         uint64_t systime_cycles;
5761
5762         switch (hw->mac.type) {
5763         case ixgbe_mac_X550:
5764                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5765                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5766                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5767                                 * NSEC_PER_SEC;
5768                 break;
5769         default:
5770                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5771                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5772                                 << 32;
5773         }
5774
5775         return systime_cycles;
5776 }
5777
5778 static uint64_t
5779 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5780 {
5781         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5782         uint64_t rx_tstamp_cycles;
5783
5784         switch (hw->mac.type) {
5785         case ixgbe_mac_X550:
5786                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5787                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5788                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5789                                 * NSEC_PER_SEC;
5790                 break;
5791         default:
5792                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5793                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5794                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5795                                 << 32;
5796         }
5797
5798         return rx_tstamp_cycles;
5799 }
5800
5801 static uint64_t
5802 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5803 {
5804         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5805         uint64_t tx_tstamp_cycles;
5806
5807         switch (hw->mac.type) {
5808         case ixgbe_mac_X550:
5809                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5810                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5811                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5812                                 * NSEC_PER_SEC;
5813                 break;
5814         default:
5815                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5816                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5817                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5818                                 << 32;
5819         }
5820
5821         return tx_tstamp_cycles;
5822 }
5823
5824 static void
5825 ixgbe_start_timecounters(struct rte_eth_dev *dev)
5826 {
5827         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5828         struct ixgbe_adapter *adapter =
5829                 (struct ixgbe_adapter *)dev->data->dev_private;
5830         struct rte_eth_link link;
5831         uint32_t incval = 0;
5832         uint32_t shift = 0;
5833
5834         /* Get current link speed. */
5835         memset(&link, 0, sizeof(link));
5836         ixgbe_dev_link_update(dev, 1);
5837         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
5838
5839         switch (link.link_speed) {
5840         case ETH_LINK_SPEED_100:
5841                 incval = IXGBE_INCVAL_100;
5842                 shift = IXGBE_INCVAL_SHIFT_100;
5843                 break;
5844         case ETH_LINK_SPEED_1000:
5845                 incval = IXGBE_INCVAL_1GB;
5846                 shift = IXGBE_INCVAL_SHIFT_1GB;
5847                 break;
5848         case ETH_LINK_SPEED_10000:
5849         default:
5850                 incval = IXGBE_INCVAL_10GB;
5851                 shift = IXGBE_INCVAL_SHIFT_10GB;
5852                 break;
5853         }
5854
5855         switch (hw->mac.type) {
5856         case ixgbe_mac_X550:
5857                 /* Independent of link speed. */
5858                 incval = 1;
5859                 /* Cycles read will be interpreted as ns. */
5860                 shift = 0;
5861                 /* Fall-through */
5862         case ixgbe_mac_X540:
5863                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
5864                 break;
5865         case ixgbe_mac_82599EB:
5866                 incval >>= IXGBE_INCVAL_SHIFT_82599;
5867                 shift -= IXGBE_INCVAL_SHIFT_82599;
5868                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
5869                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
5870                 break;
5871         default:
5872                 /* Not supported. */
5873                 return;
5874         }
5875
5876         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5877         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5878         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5879
5880         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5881         adapter->systime_tc.cc_shift = shift;
5882         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5883
5884         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5885         adapter->rx_tstamp_tc.cc_shift = shift;
5886         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5887
5888         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5889         adapter->tx_tstamp_tc.cc_shift = shift;
5890         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5891 }
5892
5893 static int
5894 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5895 {
5896         struct ixgbe_adapter *adapter =
5897                         (struct ixgbe_adapter *)dev->data->dev_private;
5898
5899         adapter->systime_tc.nsec += delta;
5900         adapter->rx_tstamp_tc.nsec += delta;
5901         adapter->tx_tstamp_tc.nsec += delta;
5902
5903         return 0;
5904 }
5905
5906 static int
5907 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5908 {
5909         uint64_t ns;
5910         struct ixgbe_adapter *adapter =
5911                         (struct ixgbe_adapter *)dev->data->dev_private;
5912
5913         ns = rte_timespec_to_ns(ts);
5914         /* Set the timecounters to a new value. */
5915         adapter->systime_tc.nsec = ns;
5916         adapter->rx_tstamp_tc.nsec = ns;
5917         adapter->tx_tstamp_tc.nsec = ns;
5918
5919         return 0;
5920 }
5921
5922 static int
5923 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5924 {
5925         uint64_t ns, systime_cycles;
5926         struct ixgbe_adapter *adapter =
5927                         (struct ixgbe_adapter *)dev->data->dev_private;
5928
5929         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
5930         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5931         *ts = rte_ns_to_timespec(ns);
5932
5933         return 0;
5934 }
5935
5936 static int
5937 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5938 {
5939         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5940         uint32_t tsync_ctl;
5941         uint32_t tsauxc;
5942
5943         /* Stop the timesync system time. */
5944         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
5945         /* Reset the timesync system time value. */
5946         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
5947         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
5948
5949         /* Enable system time for platforms where it isn't on by default. */
5950         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5951         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5952         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5953
5954         ixgbe_start_timecounters(dev);
5955
5956         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5957         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5958                         (ETHER_TYPE_1588 |
5959                          IXGBE_ETQF_FILTER_EN |
5960                          IXGBE_ETQF_1588));
5961
5962         /* Enable timestamping of received PTP packets. */
5963         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5964         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5965         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5966
5967         /* Enable timestamping of transmitted PTP packets. */
5968         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5969         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5970         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5971
5972         IXGBE_WRITE_FLUSH(hw);
5973
5974         return 0;
5975 }
5976
5977 static int
5978 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5979 {
5980         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5981         uint32_t tsync_ctl;
5982
5983         /* Disable timestamping of transmitted PTP packets. */
5984         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5985         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5986         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5987
5988         /* Disable timestamping of received PTP packets. */
5989         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5990         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5991         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5992
5993         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5994         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5995
5996         /* Stop incrementating the System Time registers. */
5997         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5998
5999         return 0;
6000 }
6001
6002 static int
6003 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6004                                  struct timespec *timestamp,
6005                                  uint32_t flags __rte_unused)
6006 {
6007         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6008         struct ixgbe_adapter *adapter =
6009                 (struct ixgbe_adapter *)dev->data->dev_private;
6010         uint32_t tsync_rxctl;
6011         uint64_t rx_tstamp_cycles;
6012         uint64_t ns;
6013
6014         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6015         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6016                 return -EINVAL;
6017
6018         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6019         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6020         *timestamp = rte_ns_to_timespec(ns);
6021
6022         return  0;
6023 }
6024
6025 static int
6026 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6027                                  struct timespec *timestamp)
6028 {
6029         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6030         struct ixgbe_adapter *adapter =
6031                 (struct ixgbe_adapter *)dev->data->dev_private;
6032         uint32_t tsync_txctl;
6033         uint64_t tx_tstamp_cycles;
6034         uint64_t ns;
6035
6036         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6037         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6038                 return -EINVAL;
6039
6040         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6041         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6042         *timestamp = rte_ns_to_timespec(ns);
6043
6044         return 0;
6045 }
6046
6047 static int
6048 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6049 {
6050         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6051         int count = 0;
6052         int g_ind = 0;
6053         const struct reg_info *reg_group;
6054         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6055                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6056
6057         while ((reg_group = reg_set[g_ind++]))
6058                 count += ixgbe_regs_group_count(reg_group);
6059
6060         return count;
6061 }
6062
6063 static int
6064 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6065 {
6066         int count = 0;
6067         int g_ind = 0;
6068         const struct reg_info *reg_group;
6069
6070         while ((reg_group = ixgbevf_regs[g_ind++]))
6071                 count += ixgbe_regs_group_count(reg_group);
6072
6073         return count;
6074 }
6075
6076 static int
6077 ixgbe_get_regs(struct rte_eth_dev *dev,
6078               struct rte_dev_reg_info *regs)
6079 {
6080         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6081         uint32_t *data = regs->data;
6082         int g_ind = 0;
6083         int count = 0;
6084         const struct reg_info *reg_group;
6085         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6086                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6087
6088         /* Support only full register dump */
6089         if ((regs->length == 0) ||
6090             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6091                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6092                         hw->device_id;
6093                 while ((reg_group = reg_set[g_ind++]))
6094                         count += ixgbe_read_regs_group(dev, &data[count],
6095                                 reg_group);
6096                 return 0;
6097         }
6098
6099         return -ENOTSUP;
6100 }
6101
6102 static int
6103 ixgbevf_get_regs(struct rte_eth_dev *dev,
6104                 struct rte_dev_reg_info *regs)
6105 {
6106         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6107         uint32_t *data = regs->data;
6108         int g_ind = 0;
6109         int count = 0;
6110         const struct reg_info *reg_group;
6111
6112         /* Support only full register dump */
6113         if ((regs->length == 0) ||
6114             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6115                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6116                         hw->device_id;
6117                 while ((reg_group = ixgbevf_regs[g_ind++]))
6118                         count += ixgbe_read_regs_group(dev, &data[count],
6119                                                       reg_group);
6120                 return 0;
6121         }
6122
6123         return -ENOTSUP;
6124 }
6125
6126 static int
6127 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6128 {
6129         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6130
6131         /* Return unit is byte count */
6132         return hw->eeprom.word_size * 2;
6133 }
6134
6135 static int
6136 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6137                 struct rte_dev_eeprom_info *in_eeprom)
6138 {
6139         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6140         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6141         uint16_t *data = in_eeprom->data;
6142         int first, length;
6143
6144         first = in_eeprom->offset >> 1;
6145         length = in_eeprom->length >> 1;
6146         if ((first > hw->eeprom.word_size) ||
6147             ((first + length) > hw->eeprom.word_size))
6148                 return -EINVAL;
6149
6150         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6151
6152         return eeprom->ops.read_buffer(hw, first, length, data);
6153 }
6154
6155 static int
6156 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6157                 struct rte_dev_eeprom_info *in_eeprom)
6158 {
6159         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6160         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6161         uint16_t *data = in_eeprom->data;
6162         int first, length;
6163
6164         first = in_eeprom->offset >> 1;
6165         length = in_eeprom->length >> 1;
6166         if ((first > hw->eeprom.word_size) ||
6167             ((first + length) > hw->eeprom.word_size))
6168                 return -EINVAL;
6169
6170         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6171
6172         return eeprom->ops.write_buffer(hw,  first, length, data);
6173 }
6174
6175 uint16_t
6176 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6177         switch (mac_type) {
6178         case ixgbe_mac_X550:
6179         case ixgbe_mac_X550EM_x:
6180         case ixgbe_mac_X550EM_a:
6181                 return ETH_RSS_RETA_SIZE_512;
6182         case ixgbe_mac_X550_vf:
6183         case ixgbe_mac_X550EM_x_vf:
6184         case ixgbe_mac_X550EM_a_vf:
6185                 return ETH_RSS_RETA_SIZE_64;
6186         default:
6187                 return ETH_RSS_RETA_SIZE_128;
6188         }
6189 }
6190
6191 uint32_t
6192 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6193         switch (mac_type) {
6194         case ixgbe_mac_X550:
6195         case ixgbe_mac_X550EM_x:
6196         case ixgbe_mac_X550EM_a:
6197                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6198                         return IXGBE_RETA(reta_idx >> 2);
6199                 else
6200                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6201         case ixgbe_mac_X550_vf:
6202         case ixgbe_mac_X550EM_x_vf:
6203         case ixgbe_mac_X550EM_a_vf:
6204                 return IXGBE_VFRETA(reta_idx >> 2);
6205         default:
6206                 return IXGBE_RETA(reta_idx >> 2);
6207         }
6208 }
6209
6210 uint32_t
6211 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6212         switch (mac_type) {
6213         case ixgbe_mac_X550_vf:
6214         case ixgbe_mac_X550EM_x_vf:
6215         case ixgbe_mac_X550EM_a_vf:
6216                 return IXGBE_VFMRQC;
6217         default:
6218                 return IXGBE_MRQC;
6219         }
6220 }
6221
6222 uint32_t
6223 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6224         switch (mac_type) {
6225         case ixgbe_mac_X550_vf:
6226         case ixgbe_mac_X550EM_x_vf:
6227         case ixgbe_mac_X550EM_a_vf:
6228                 return IXGBE_VFRSSRK(i);
6229         default:
6230                 return IXGBE_RSSRK(i);
6231         }
6232 }
6233
6234 bool
6235 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6236         switch (mac_type) {
6237         case ixgbe_mac_82599_vf:
6238         case ixgbe_mac_X540_vf:
6239                 return 0;
6240         default:
6241                 return 1;
6242         }
6243 }
6244
6245 static int
6246 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6247                         struct rte_eth_dcb_info *dcb_info)
6248 {
6249         struct ixgbe_dcb_config *dcb_config =
6250                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6251         struct ixgbe_dcb_tc_config *tc;
6252         uint8_t i, j;
6253
6254         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6255                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6256         else
6257                 dcb_info->nb_tcs = 1;
6258
6259         if (dcb_config->vt_mode) { /* vt is enabled*/
6260                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6261                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6262                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6263                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6264                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6265                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6266                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6267                                                 i * dcb_info->nb_tcs + j;
6268                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6269                                 dcb_info->tc_queue.tc_txq[i][j].base =
6270                                                 i * dcb_info->nb_tcs + j;
6271                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6272                         }
6273                 }
6274         } else { /* vt is disabled*/
6275                 struct rte_eth_dcb_rx_conf *rx_conf =
6276                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6277                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6278                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6279                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6280                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6281                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6282                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6283                         }
6284                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6285                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6286                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6287                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6288                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6289                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6290                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6291                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6292                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6293                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6294                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6295                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6296                         }
6297                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6298                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6299                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6300                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6301                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6302                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6303                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6304                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6305                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6306                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6307                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6308                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6309                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6310                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6311                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6312                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6313                 }
6314         }
6315         for (i = 0; i < dcb_info->nb_tcs; i++) {
6316                 tc = &dcb_config->tc_config[i];
6317                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6318         }
6319         return 0;
6320 }
6321
6322 /* Update e-tag ether type */
6323 static int
6324 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6325                             uint16_t ether_type)
6326 {
6327         uint32_t etag_etype;
6328
6329         if (hw->mac.type != ixgbe_mac_X550 &&
6330             hw->mac.type != ixgbe_mac_X550EM_x) {
6331                 return -ENOTSUP;
6332         }
6333
6334         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6335         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6336         etag_etype |= ether_type;
6337         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6338         IXGBE_WRITE_FLUSH(hw);
6339
6340         return 0;
6341 }
6342
6343 /* Config l2 tunnel ether type */
6344 static int
6345 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6346                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6347 {
6348         int ret = 0;
6349         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6350
6351         if (l2_tunnel == NULL)
6352                 return -EINVAL;
6353
6354         switch (l2_tunnel->l2_tunnel_type) {
6355         case RTE_L2_TUNNEL_TYPE_E_TAG:
6356                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6357                 break;
6358         default:
6359                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6360                 ret = -EINVAL;
6361                 break;
6362         }
6363
6364         return ret;
6365 }
6366
6367 /* Enable e-tag tunnel */
6368 static int
6369 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6370 {
6371         uint32_t etag_etype;
6372
6373         if (hw->mac.type != ixgbe_mac_X550 &&
6374             hw->mac.type != ixgbe_mac_X550EM_x) {
6375                 return -ENOTSUP;
6376         }
6377
6378         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6379         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6380         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6381         IXGBE_WRITE_FLUSH(hw);
6382
6383         return 0;
6384 }
6385
6386 /* Enable l2 tunnel */
6387 static int
6388 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6389                            enum rte_eth_tunnel_type l2_tunnel_type)
6390 {
6391         int ret = 0;
6392         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6393
6394         switch (l2_tunnel_type) {
6395         case RTE_L2_TUNNEL_TYPE_E_TAG:
6396                 ret = ixgbe_e_tag_enable(hw);
6397                 break;
6398         default:
6399                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6400                 ret = -EINVAL;
6401                 break;
6402         }
6403
6404         return ret;
6405 }
6406
6407 /* Disable e-tag tunnel */
6408 static int
6409 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6410 {
6411         uint32_t etag_etype;
6412
6413         if (hw->mac.type != ixgbe_mac_X550 &&
6414             hw->mac.type != ixgbe_mac_X550EM_x) {
6415                 return -ENOTSUP;
6416         }
6417
6418         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6419         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6420         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6421         IXGBE_WRITE_FLUSH(hw);
6422
6423         return 0;
6424 }
6425
6426 /* Disable l2 tunnel */
6427 static int
6428 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6429                             enum rte_eth_tunnel_type l2_tunnel_type)
6430 {
6431         int ret = 0;
6432         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6433
6434         switch (l2_tunnel_type) {
6435         case RTE_L2_TUNNEL_TYPE_E_TAG:
6436                 ret = ixgbe_e_tag_disable(hw);
6437                 break;
6438         default:
6439                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6440                 ret = -EINVAL;
6441                 break;
6442         }
6443
6444         return ret;
6445 }
6446
6447 static int
6448 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6449                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6450 {
6451         int ret = 0;
6452         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6453         uint32_t i, rar_entries;
6454         uint32_t rar_low, rar_high;
6455
6456         if (hw->mac.type != ixgbe_mac_X550 &&
6457             hw->mac.type != ixgbe_mac_X550EM_x) {
6458                 return -ENOTSUP;
6459         }
6460
6461         rar_entries = ixgbe_get_num_rx_addrs(hw);
6462
6463         for (i = 1; i < rar_entries; i++) {
6464                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6465                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6466                 if ((rar_high & IXGBE_RAH_AV) &&
6467                     (rar_high & IXGBE_RAH_ADTYPE) &&
6468                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6469                      l2_tunnel->tunnel_id)) {
6470                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6471                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6472
6473                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6474
6475                         return ret;
6476                 }
6477         }
6478
6479         return ret;
6480 }
6481
6482 static int
6483 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6484                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6485 {
6486         int ret = 0;
6487         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6488         uint32_t i, rar_entries;
6489         uint32_t rar_low, rar_high;
6490
6491         if (hw->mac.type != ixgbe_mac_X550 &&
6492             hw->mac.type != ixgbe_mac_X550EM_x) {
6493                 return -ENOTSUP;
6494         }
6495
6496         /* One entry for one tunnel. Try to remove potential existing entry. */
6497         ixgbe_e_tag_filter_del(dev, l2_tunnel);
6498
6499         rar_entries = ixgbe_get_num_rx_addrs(hw);
6500
6501         for (i = 1; i < rar_entries; i++) {
6502                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6503                 if (rar_high & IXGBE_RAH_AV) {
6504                         continue;
6505                 } else {
6506                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6507                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6508                         rar_low = l2_tunnel->tunnel_id;
6509
6510                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6511                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6512
6513                         return ret;
6514                 }
6515         }
6516
6517         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6518                      " Please remove a rule before adding a new one.");
6519         return -EINVAL;
6520 }
6521
6522 /* Add l2 tunnel filter */
6523 static int
6524 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6525                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6526 {
6527         int ret = 0;
6528
6529         switch (l2_tunnel->l2_tunnel_type) {
6530         case RTE_L2_TUNNEL_TYPE_E_TAG:
6531                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6532                 break;
6533         default:
6534                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6535                 ret = -EINVAL;
6536                 break;
6537         }
6538
6539         return ret;
6540 }
6541
6542 /* Delete l2 tunnel filter */
6543 static int
6544 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6545                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6546 {
6547         int ret = 0;
6548
6549         switch (l2_tunnel->l2_tunnel_type) {
6550         case RTE_L2_TUNNEL_TYPE_E_TAG:
6551                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6552                 break;
6553         default:
6554                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6555                 ret = -EINVAL;
6556                 break;
6557         }
6558
6559         return ret;
6560 }
6561
6562 /**
6563  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6564  * @dev: pointer to rte_eth_dev structure
6565  * @filter_op:operation will be taken.
6566  * @arg: a pointer to specific structure corresponding to the filter_op
6567  */
6568 static int
6569 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6570                                   enum rte_filter_op filter_op,
6571                                   void *arg)
6572 {
6573         int ret = 0;
6574
6575         if (filter_op == RTE_ETH_FILTER_NOP)
6576                 return 0;
6577
6578         if (arg == NULL) {
6579                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6580                             filter_op);
6581                 return -EINVAL;
6582         }
6583
6584         switch (filter_op) {
6585         case RTE_ETH_FILTER_ADD:
6586                 ret = ixgbe_dev_l2_tunnel_filter_add
6587                         (dev,
6588                          (struct rte_eth_l2_tunnel_conf *)arg);
6589                 break;
6590         case RTE_ETH_FILTER_DELETE:
6591                 ret = ixgbe_dev_l2_tunnel_filter_del
6592                         (dev,
6593                          (struct rte_eth_l2_tunnel_conf *)arg);
6594                 break;
6595         default:
6596                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6597                 ret = -EINVAL;
6598                 break;
6599         }
6600         return ret;
6601 }
6602
6603 static int
6604 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6605 {
6606         int ret = 0;
6607         uint32_t ctrl;
6608         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6609
6610         if (hw->mac.type != ixgbe_mac_X550 &&
6611             hw->mac.type != ixgbe_mac_X550EM_x) {
6612                 return -ENOTSUP;
6613         }
6614
6615         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6616         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6617         if (en)
6618                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6619         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6620
6621         return ret;
6622 }
6623
6624 /* Enable l2 tunnel forwarding */
6625 static int
6626 ixgbe_dev_l2_tunnel_forwarding_enable
6627         (struct rte_eth_dev *dev,
6628          enum rte_eth_tunnel_type l2_tunnel_type)
6629 {
6630         int ret = 0;
6631
6632         switch (l2_tunnel_type) {
6633         case RTE_L2_TUNNEL_TYPE_E_TAG:
6634                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6635                 break;
6636         default:
6637                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6638                 ret = -EINVAL;
6639                 break;
6640         }
6641
6642         return ret;
6643 }
6644
6645 /* Disable l2 tunnel forwarding */
6646 static int
6647 ixgbe_dev_l2_tunnel_forwarding_disable
6648         (struct rte_eth_dev *dev,
6649          enum rte_eth_tunnel_type l2_tunnel_type)
6650 {
6651         int ret = 0;
6652
6653         switch (l2_tunnel_type) {
6654         case RTE_L2_TUNNEL_TYPE_E_TAG:
6655                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6656                 break;
6657         default:
6658                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6659                 ret = -EINVAL;
6660                 break;
6661         }
6662
6663         return ret;
6664 }
6665
6666 static int
6667 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6668                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
6669                              bool en)
6670 {
6671         int ret = 0;
6672         uint32_t vmtir, vmvir;
6673         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6674
6675         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6676                 PMD_DRV_LOG(ERR,
6677                             "VF id %u should be less than %u",
6678                             l2_tunnel->vf_id,
6679                             dev->pci_dev->max_vfs);
6680                 return -EINVAL;
6681         }
6682
6683         if (hw->mac.type != ixgbe_mac_X550 &&
6684             hw->mac.type != ixgbe_mac_X550EM_x) {
6685                 return -ENOTSUP;
6686         }
6687
6688         if (en)
6689                 vmtir = l2_tunnel->tunnel_id;
6690         else
6691                 vmtir = 0;
6692
6693         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6694
6695         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6696         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6697         if (en)
6698                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6699         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6700
6701         return ret;
6702 }
6703
6704 /* Enable l2 tunnel tag insertion */
6705 static int
6706 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6707                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
6708 {
6709         int ret = 0;
6710
6711         switch (l2_tunnel->l2_tunnel_type) {
6712         case RTE_L2_TUNNEL_TYPE_E_TAG:
6713                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6714                 break;
6715         default:
6716                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6717                 ret = -EINVAL;
6718                 break;
6719         }
6720
6721         return ret;
6722 }
6723
6724 /* Disable l2 tunnel tag insertion */
6725 static int
6726 ixgbe_dev_l2_tunnel_insertion_disable
6727         (struct rte_eth_dev *dev,
6728          struct rte_eth_l2_tunnel_conf *l2_tunnel)
6729 {
6730         int ret = 0;
6731
6732         switch (l2_tunnel->l2_tunnel_type) {
6733         case RTE_L2_TUNNEL_TYPE_E_TAG:
6734                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6735                 break;
6736         default:
6737                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6738                 ret = -EINVAL;
6739                 break;
6740         }
6741
6742         return ret;
6743 }
6744
6745 static int
6746 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6747                              bool en)
6748 {
6749         int ret = 0;
6750         uint32_t qde;
6751         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6752
6753         if (hw->mac.type != ixgbe_mac_X550 &&
6754             hw->mac.type != ixgbe_mac_X550EM_x) {
6755                 return -ENOTSUP;
6756         }
6757
6758         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
6759         if (en)
6760                 qde |= IXGBE_QDE_STRIP_TAG;
6761         else
6762                 qde &= ~IXGBE_QDE_STRIP_TAG;
6763         qde &= ~IXGBE_QDE_READ;
6764         qde |= IXGBE_QDE_WRITE;
6765         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
6766
6767         return ret;
6768 }
6769
6770 /* Enable l2 tunnel tag stripping */
6771 static int
6772 ixgbe_dev_l2_tunnel_stripping_enable
6773         (struct rte_eth_dev *dev,
6774          enum rte_eth_tunnel_type l2_tunnel_type)
6775 {
6776         int ret = 0;
6777
6778         switch (l2_tunnel_type) {
6779         case RTE_L2_TUNNEL_TYPE_E_TAG:
6780                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
6781                 break;
6782         default:
6783                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6784                 ret = -EINVAL;
6785                 break;
6786         }
6787
6788         return ret;
6789 }
6790
6791 /* Disable l2 tunnel tag stripping */
6792 static int
6793 ixgbe_dev_l2_tunnel_stripping_disable
6794         (struct rte_eth_dev *dev,
6795          enum rte_eth_tunnel_type l2_tunnel_type)
6796 {
6797         int ret = 0;
6798
6799         switch (l2_tunnel_type) {
6800         case RTE_L2_TUNNEL_TYPE_E_TAG:
6801                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
6802                 break;
6803         default:
6804                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6805                 ret = -EINVAL;
6806                 break;
6807         }
6808
6809         return ret;
6810 }
6811
6812 /* Enable/disable l2 tunnel offload functions */
6813 static int
6814 ixgbe_dev_l2_tunnel_offload_set
6815         (struct rte_eth_dev *dev,
6816          struct rte_eth_l2_tunnel_conf *l2_tunnel,
6817          uint32_t mask,
6818          uint8_t en)
6819 {
6820         int ret = 0;
6821
6822         if (l2_tunnel == NULL)
6823                 return -EINVAL;
6824
6825         ret = -EINVAL;
6826         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
6827                 if (en)
6828                         ret = ixgbe_dev_l2_tunnel_enable(
6829                                 dev,
6830                                 l2_tunnel->l2_tunnel_type);
6831                 else
6832                         ret = ixgbe_dev_l2_tunnel_disable(
6833                                 dev,
6834                                 l2_tunnel->l2_tunnel_type);
6835         }
6836
6837         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
6838                 if (en)
6839                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
6840                                 dev,
6841                                 l2_tunnel);
6842                 else
6843                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
6844                                 dev,
6845                                 l2_tunnel);
6846         }
6847
6848         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
6849                 if (en)
6850                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
6851                                 dev,
6852                                 l2_tunnel->l2_tunnel_type);
6853                 else
6854                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
6855                                 dev,
6856                                 l2_tunnel->l2_tunnel_type);
6857         }
6858
6859         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
6860                 if (en)
6861                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
6862                                 dev,
6863                                 l2_tunnel->l2_tunnel_type);
6864                 else
6865                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
6866                                 dev,
6867                                 l2_tunnel->l2_tunnel_type);
6868         }
6869
6870         return ret;
6871 }
6872
6873 static int
6874 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
6875                         uint16_t port)
6876 {
6877         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
6878         IXGBE_WRITE_FLUSH(hw);
6879
6880         return 0;
6881 }
6882
6883 /* There's only one register for VxLAN UDP port.
6884  * So, we cannot add several ports. Will update it.
6885  */
6886 static int
6887 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
6888                      uint16_t port)
6889 {
6890         if (port == 0) {
6891                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
6892                 return -EINVAL;
6893         }
6894
6895         return ixgbe_update_vxlan_port(hw, port);
6896 }
6897
6898 /* We cannot delete the VxLAN port. For there's a register for VxLAN
6899  * UDP port, it must have a value.
6900  * So, will reset it to the original value 0.
6901  */
6902 static int
6903 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
6904                      uint16_t port)
6905 {
6906         uint16_t cur_port;
6907
6908         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
6909
6910         if (cur_port != port) {
6911                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
6912                 return -EINVAL;
6913         }
6914
6915         return ixgbe_update_vxlan_port(hw, 0);
6916 }
6917
6918 /* Add UDP tunneling port */
6919 static int
6920 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6921                               struct rte_eth_udp_tunnel *udp_tunnel)
6922 {
6923         int ret = 0;
6924         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6925
6926         if (hw->mac.type != ixgbe_mac_X550 &&
6927             hw->mac.type != ixgbe_mac_X550EM_x) {
6928                 return -ENOTSUP;
6929         }
6930
6931         if (udp_tunnel == NULL)
6932                 return -EINVAL;
6933
6934         switch (udp_tunnel->prot_type) {
6935         case RTE_TUNNEL_TYPE_VXLAN:
6936                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
6937                 break;
6938
6939         case RTE_TUNNEL_TYPE_GENEVE:
6940         case RTE_TUNNEL_TYPE_TEREDO:
6941                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6942                 ret = -EINVAL;
6943                 break;
6944
6945         default:
6946                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6947                 ret = -EINVAL;
6948                 break;
6949         }
6950
6951         return ret;
6952 }
6953
6954 /* Remove UDP tunneling port */
6955 static int
6956 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6957                               struct rte_eth_udp_tunnel *udp_tunnel)
6958 {
6959         int ret = 0;
6960         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6961
6962         if (hw->mac.type != ixgbe_mac_X550 &&
6963             hw->mac.type != ixgbe_mac_X550EM_x) {
6964                 return -ENOTSUP;
6965         }
6966
6967         if (udp_tunnel == NULL)
6968                 return -EINVAL;
6969
6970         switch (udp_tunnel->prot_type) {
6971         case RTE_TUNNEL_TYPE_VXLAN:
6972                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
6973                 break;
6974         case RTE_TUNNEL_TYPE_GENEVE:
6975         case RTE_TUNNEL_TYPE_TEREDO:
6976                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6977                 ret = -EINVAL;
6978                 break;
6979         default:
6980                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6981                 ret = -EINVAL;
6982                 break;
6983         }
6984
6985         return ret;
6986 }
6987
6988 /* ixgbevf_update_xcast_mode - Update Multicast mode
6989  * @hw: pointer to the HW structure
6990  * @netdev: pointer to net device structure
6991  * @xcast_mode: new multicast mode
6992  *
6993  * Updates the Multicast Mode of VF.
6994  */
6995 static int ixgbevf_update_xcast_mode(struct ixgbe_hw *hw,
6996                                      int xcast_mode)
6997 {
6998         struct ixgbe_mbx_info *mbx = &hw->mbx;
6999         u32 msgbuf[2];
7000         s32 err;
7001
7002         switch (hw->api_version) {
7003         case ixgbe_mbox_api_12:
7004                 break;
7005         default:
7006                 return -EOPNOTSUPP;
7007         }
7008
7009         msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
7010         msgbuf[1] = xcast_mode;
7011
7012         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
7013         if (err)
7014                 return err;
7015
7016         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
7017         if (err)
7018                 return err;
7019
7020         msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
7021         if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
7022                 return -EPERM;
7023
7024         return 0;
7025 }
7026
7027 static void
7028 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7029 {
7030         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7031
7032         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7033 }
7034
7035 static void
7036 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7037 {
7038         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7039
7040         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7041 }
7042
7043 static struct rte_driver rte_ixgbe_driver = {
7044         .type = PMD_PDEV,
7045         .init = rte_ixgbe_pmd_init,
7046 };
7047
7048 static struct rte_driver rte_ixgbevf_driver = {
7049         .type = PMD_PDEV,
7050         .init = rte_ixgbevf_pmd_init,
7051 };
7052
7053 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
7054 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);