drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIBRTE_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void ixgbe_dev_setup_link_alarm_handler(void *param);
 233
 234 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 235                         struct rte_ether_addr *mac_addr,
 236                         uint32_t index, uint32_t pool);
 237 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 238 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 239                                            struct rte_ether_addr *mac_addr);
 240 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 241 static bool is_device_supported(struct rte_eth_dev *dev,
 242                                 struct rte_pci_driver *drv);
 243
 244 /* For Virtual Function support */
 245 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 246 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 247 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 248 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 249 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 250                                    int wait_to_complete);
 251 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 252 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 253 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 254 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 255 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 256 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 257                 struct rte_eth_stats *stats);
 258 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 259 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 260                 uint16_t vlan_id, int on);
 261 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 262                 uint16_t queue, int on);
 263 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 264 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 265 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 266 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 267                                             uint16_t queue_id);
 268 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 269                                              uint16_t queue_id);
 270 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 271                                  uint8_t queue, uint8_t msix_vector);
 272 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 273 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 274 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 277
 278 /* For Eth VMDQ APIs support */
 279 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 280                 rte_ether_addr * mac_addr, uint8_t on);
 281 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 282 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 283                 struct rte_eth_mirror_conf *mirror_conf,
 284                 uint8_t rule_id, uint8_t on);
 285 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 286                 uint8_t rule_id);
 287 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 288                                           uint16_t queue_id);
 289 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 290                                            uint16_t queue_id);
 291 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 292                                uint8_t queue, uint8_t msix_vector);
 293 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 294
 295 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 296                                 struct rte_ether_addr *mac_addr,
 297                                 uint32_t index, uint32_t pool);
 298 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 299 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 300                                              struct rte_ether_addr *mac_addr);
 301 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 302                         struct rte_eth_syn_filter *filter);
 303 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 304                         enum rte_filter_op filter_op,
 305                         void *arg);
 306 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 307                         struct ixgbe_5tuple_filter *filter);
 308 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 309                         struct ixgbe_5tuple_filter *filter);
 310 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 311                                 enum rte_filter_op filter_op,
 312                                 void *arg);
 313 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 314                         struct rte_eth_ntuple_filter *filter);
 315 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 316                                 enum rte_filter_op filter_op,
 317                                 void *arg);
 318 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 319                         struct rte_eth_ethertype_filter *filter);
 320 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 321                      enum rte_filter_type filter_type,
 322                      enum rte_filter_op filter_op,
 323                      void *arg);
 324 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 325
 326 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 327                                       struct rte_ether_addr *mc_addr_set,
 328                                       uint32_t nb_mc_addr);
 329 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 330                                    struct rte_eth_dcb_info *dcb_info);
 331
 332 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 333 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 334                             struct rte_dev_reg_info *regs);
 335 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 336 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 337                                 struct rte_dev_eeprom_info *eeprom);
 338 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 339                                 struct rte_dev_eeprom_info *eeprom);
 340
 341 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 342                                  struct rte_eth_dev_module_info *modinfo);
 343 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 344                                    struct rte_dev_eeprom_info *info);
 345
 346 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 347 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 348                                 struct rte_dev_reg_info *regs);
 349
 350 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 351 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 352 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 353                                             struct timespec *timestamp,
 354                                             uint32_t flags);
 355 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 356                                             struct timespec *timestamp);
 357 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 358 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 359                                    struct timespec *timestamp);
 360 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 361                                    const struct timespec *timestamp);
 362 static void ixgbevf_dev_interrupt_handler(void *param);
 363
 364 static int ixgbe_dev_l2_tunnel_eth_type_conf
 365         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 366 static int ixgbe_dev_l2_tunnel_offload_set
 367         (struct rte_eth_dev *dev,
 368          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 369          uint32_t mask,
 370          uint8_t en);
 371 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 372                                              enum rte_filter_op filter_op,
 373                                              void *arg);
 374
 375 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 376                                          struct rte_eth_udp_tunnel *udp_tunnel);
 377 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 380 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 381 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
 382
 383 /*
 384  * Define VF Stats MACRO for Non "cleared on read" register
 385  */
 386 #define UPDATE_VF_STAT(reg, last, cur)                          \
 387 {                                                               \
 388         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 389         cur += (latest - last) & UINT_MAX;                      \
 390         last = latest;                                          \
 391 }
 392
 393 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 394 {                                                                \
 395         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 396         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 397         u64 latest = ((new_msb << 32) | new_lsb);                \
 398         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 399         last = latest;                                           \
 400 }
 401
 402 #define IXGBE_SET_HWSTRIP(h, q) do {\
 403                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 404                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 405                 (h)->bitmap[idx] |= 1 << bit;\
 406         } while (0)
 407
 408 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 409                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 410                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 411                 (h)->bitmap[idx] &= ~(1 << bit);\
 412         } while (0)
 413
 414 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 415                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 416                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 417                 (r) = (h)->bitmap[idx] >> bit & 1;\
 418         } while (0)
 419
 420 int ixgbe_logtype_init;
 421 int ixgbe_logtype_driver;
 422
 423 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
 424 int ixgbe_logtype_rx;
 425 #endif
 426 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
 427 int ixgbe_logtype_tx;
 428 #endif
 429 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
 430 int ixgbe_logtype_tx_free;
 431 #endif
 432
 433 /*
 434  * The set of PCI devices this driver supports
 435  */
 436 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 485 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 487 #endif
 488         { .vendor_id = 0, /* sentinel */ },
 489 };
 490
 491 /*
 492  * The set of PCI devices this driver supports (for 82599 VF)
 493  */
 494 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 504         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 505         { .vendor_id = 0, /* sentinel */ },
 506 };
 507
 508 static const struct rte_eth_desc_lim rx_desc_lim = {
 509         .nb_max = IXGBE_MAX_RING_DESC,
 510         .nb_min = IXGBE_MIN_RING_DESC,
 511         .nb_align = IXGBE_RXD_ALIGN,
 512 };
 513
 514 static const struct rte_eth_desc_lim tx_desc_lim = {
 515         .nb_max = IXGBE_MAX_RING_DESC,
 516         .nb_min = IXGBE_MIN_RING_DESC,
 517         .nb_align = IXGBE_TXD_ALIGN,
 518         .nb_seg_max = IXGBE_TX_MAX_SEG,
 519         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 520 };
 521
 522 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 523         .dev_configure        = ixgbe_dev_configure,
 524         .dev_start            = ixgbe_dev_start,
 525         .dev_stop             = ixgbe_dev_stop,
 526         .dev_set_link_up    = ixgbe_dev_set_link_up,
 527         .dev_set_link_down  = ixgbe_dev_set_link_down,
 528         .dev_close            = ixgbe_dev_close,
 529         .dev_reset            = ixgbe_dev_reset,
 530         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 531         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 532         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 533         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 534         .link_update          = ixgbe_dev_link_update,
 535         .stats_get            = ixgbe_dev_stats_get,
 536         .xstats_get           = ixgbe_dev_xstats_get,
 537         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 538         .stats_reset          = ixgbe_dev_stats_reset,
 539         .xstats_reset         = ixgbe_dev_xstats_reset,
 540         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 541         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 542         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 543         .fw_version_get       = ixgbe_fw_version_get,
 544         .dev_infos_get        = ixgbe_dev_info_get,
 545         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 546         .mtu_set              = ixgbe_dev_mtu_set,
 547         .vlan_filter_set      = ixgbe_vlan_filter_set,
 548         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 549         .vlan_offload_set     = ixgbe_vlan_offload_set,
 550         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 551         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 552         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 553         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 554         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 555         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 556         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 557         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 558         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 559         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 560         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 561         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 562         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 563         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 564         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 565         .dev_led_on           = ixgbe_dev_led_on,
 566         .dev_led_off          = ixgbe_dev_led_off,
 567         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 568         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 569         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 570         .mac_addr_add         = ixgbe_add_rar,
 571         .mac_addr_remove      = ixgbe_remove_rar,
 572         .mac_addr_set         = ixgbe_set_default_mac_addr,
 573         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 574         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 575         .mirror_rule_set      = ixgbe_mirror_rule_set,
 576         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 577         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 578         .reta_update          = ixgbe_dev_rss_reta_update,
 579         .reta_query           = ixgbe_dev_rss_reta_query,
 580         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 581         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 582         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 583         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 584         .rxq_info_get         = ixgbe_rxq_info_get,
 585         .txq_info_get         = ixgbe_txq_info_get,
 586         .timesync_enable      = ixgbe_timesync_enable,
 587         .timesync_disable     = ixgbe_timesync_disable,
 588         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 589         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 590         .get_reg              = ixgbe_get_regs,
 591         .get_eeprom_length    = ixgbe_get_eeprom_length,
 592         .get_eeprom           = ixgbe_get_eeprom,
 593         .set_eeprom           = ixgbe_set_eeprom,
 594         .get_module_info      = ixgbe_get_module_info,
 595         .get_module_eeprom    = ixgbe_get_module_eeprom,
 596         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 597         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 598         .timesync_read_time   = ixgbe_timesync_read_time,
 599         .timesync_write_time  = ixgbe_timesync_write_time,
 600         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 601         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 602         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 603         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 604         .tm_ops_get           = ixgbe_tm_ops_get,
 605 };
 606
 607 /*
 608  * dev_ops for virtual function, bare necessities for basic vf
 609  * operation have been implemented
 610  */
 611 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 612         .dev_configure        = ixgbevf_dev_configure,
 613         .dev_start            = ixgbevf_dev_start,
 614         .dev_stop             = ixgbevf_dev_stop,
 615         .link_update          = ixgbevf_dev_link_update,
 616         .stats_get            = ixgbevf_dev_stats_get,
 617         .xstats_get           = ixgbevf_dev_xstats_get,
 618         .stats_reset          = ixgbevf_dev_stats_reset,
 619         .xstats_reset         = ixgbevf_dev_stats_reset,
 620         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 621         .dev_close            = ixgbevf_dev_close,
 622         .dev_reset            = ixgbevf_dev_reset,
 623         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 624         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 625         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 626         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 627         .dev_infos_get        = ixgbevf_dev_info_get,
 628         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 629         .mtu_set              = ixgbevf_dev_set_mtu,
 630         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 631         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 632         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 633         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 634         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 635         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 636         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 637         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 638         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 639         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 640         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 641         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 642         .mac_addr_add         = ixgbevf_add_mac_addr,
 643         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 644         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 645         .rxq_info_get         = ixgbe_rxq_info_get,
 646         .txq_info_get         = ixgbe_txq_info_get,
 647         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 648         .get_reg              = ixgbevf_get_regs,
 649         .reta_update          = ixgbe_dev_rss_reta_update,
 650         .reta_query           = ixgbe_dev_rss_reta_query,
 651         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 652         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 653 };
 654
 655 /* store statistics names and its offset in stats structure */
 656 struct rte_ixgbe_xstats_name_off {
 657         char name[RTE_ETH_XSTATS_NAME_SIZE];
 658         unsigned offset;
 659 };
 660
 661 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 662         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 663         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 664         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 665         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 666         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 667         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 668         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 669         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 670         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 671         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 672         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 673         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 674         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 675         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 676         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 677                 prc1023)},
 678         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 679                 prc1522)},
 680         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 681         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 682         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 683         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 684         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 685         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 686         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 687         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 688         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 689         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 690         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 691         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 692         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 693         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 694         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 695         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 696         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 697                 ptc1023)},
 698         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 699                 ptc1522)},
 700         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 701         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 702         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 703         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 704
 705         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 706                 fdirustat_add)},
 707         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 708                 fdirustat_remove)},
 709         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 710                 fdirfstat_fadd)},
 711         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 712                 fdirfstat_fremove)},
 713         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 714                 fdirmatch)},
 715         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 716                 fdirmiss)},
 717
 718         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 719         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 720         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 721                 fclast)},
 722         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 723         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 724         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 725         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 726         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 727                 fcoe_noddp)},
 728         {"rx_fcoe_no_direct_data_placement_ext_buff",
 729                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 730
 731         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 732                 lxontxc)},
 733         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 734                 lxonrxc)},
 735         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 736                 lxofftxc)},
 737         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 738                 lxoffrxc)},
 739         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 740 };
 741
 742 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 743                            sizeof(rte_ixgbe_stats_strings[0]))
 744
 745 /* MACsec statistics */
 746 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 747         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 748                 out_pkts_untagged)},
 749         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 750                 out_pkts_encrypted)},
 751         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 752                 out_pkts_protected)},
 753         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 754                 out_octets_encrypted)},
 755         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 756                 out_octets_protected)},
 757         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_untagged)},
 759         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 760                 in_pkts_badtag)},
 761         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 762                 in_pkts_nosci)},
 763         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 764                 in_pkts_unknownsci)},
 765         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 766                 in_octets_decrypted)},
 767         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 768                 in_octets_validated)},
 769         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 770                 in_pkts_unchecked)},
 771         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 772                 in_pkts_delayed)},
 773         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 774                 in_pkts_late)},
 775         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 776                 in_pkts_ok)},
 777         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 778                 in_pkts_invalid)},
 779         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 780                 in_pkts_notvalid)},
 781         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 782                 in_pkts_unusedsa)},
 783         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 784                 in_pkts_notusingsa)},
 785 };
 786
 787 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 788                            sizeof(rte_ixgbe_macsec_strings[0]))
 789
 790 /* Per-queue statistics */
 791 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 792         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 793         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 794         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 795         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 796 };
 797
 798 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 799                            sizeof(rte_ixgbe_rxq_strings[0]))
 800 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 801
 802 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 803         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 804         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 805         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 806                 pxon2offc)},
 807 };
 808
 809 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 810                            sizeof(rte_ixgbe_txq_strings[0]))
 811 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 812
 813 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 814         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 815 };
 816
 817 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 818                 sizeof(rte_ixgbevf_stats_strings[0]))
 819
 820 /*
 821  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 822  */
 823 static inline int
 824 ixgbe_is_sfp(struct ixgbe_hw *hw)
 825 {
 826         switch (hw->phy.type) {
 827         case ixgbe_phy_sfp_avago:
 828         case ixgbe_phy_sfp_ftl:
 829         case ixgbe_phy_sfp_intel:
 830         case ixgbe_phy_sfp_unknown:
 831         case ixgbe_phy_sfp_passive_tyco:
 832         case ixgbe_phy_sfp_passive_unknown:
 833                 return 1;
 834         default:
 835                 return 0;
 836         }
 837 }
 838
 839 static inline int32_t
 840 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 841 {
 842         uint32_t ctrl_ext;
 843         int32_t status;
 844
 845         status = ixgbe_reset_hw(hw);
 846
 847         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 848         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 849         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 850         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 851         IXGBE_WRITE_FLUSH(hw);
 852
 853         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 854                 status = IXGBE_SUCCESS;
 855         return status;
 856 }
 857
 858 static inline void
 859 ixgbe_enable_intr(struct rte_eth_dev *dev)
 860 {
 861         struct ixgbe_interrupt *intr =
 862                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 863         struct ixgbe_hw *hw =
 864                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 865
 866         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 867         IXGBE_WRITE_FLUSH(hw);
 868 }
 869
 870 /*
 871  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 872  */
 873 static void
 874 ixgbe_disable_intr(struct ixgbe_hw *hw)
 875 {
 876         PMD_INIT_FUNC_TRACE();
 877
 878         if (hw->mac.type == ixgbe_mac_82598EB) {
 879                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 880         } else {
 881                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 882                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 883                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 884         }
 885         IXGBE_WRITE_FLUSH(hw);
 886 }
 887
 888 /*
 889  * This function resets queue statistics mapping registers.
 890  * From Niantic datasheet, Initialization of Statistics section:
 891  * "...if software requires the queue counters, the RQSMR and TQSM registers
 892  * must be re-programmed following a device reset.
 893  */
 894 static void
 895 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 896 {
 897         uint32_t i;
 898
 899         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 900                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 901                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 902         }
 903 }
 904
 905
 906 static int
 907 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 908                                   uint16_t queue_id,
 909                                   uint8_t stat_idx,
 910                                   uint8_t is_rx)
 911 {
 912 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 913 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 914 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 915
 916         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 917         struct ixgbe_stat_mapping_registers *stat_mappings =
 918                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 919         uint32_t qsmr_mask = 0;
 920         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 921         uint32_t q_map;
 922         uint8_t n, offset;
 923
 924         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 925                 (hw->mac.type != ixgbe_mac_X540) &&
 926                 (hw->mac.type != ixgbe_mac_X550) &&
 927                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 928                 (hw->mac.type != ixgbe_mac_X550EM_a))
 929                 return -ENOSYS;
 930
 931         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 932                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 933                      queue_id, stat_idx);
 934
 935         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 936         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 937                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 938                 return -EIO;
 939         }
 940         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 941
 942         /* Now clear any previous stat_idx set */
 943         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 944         if (!is_rx)
 945                 stat_mappings->tqsm[n] &= ~clearing_mask;
 946         else
 947                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 948
 949         q_map = (uint32_t)stat_idx;
 950         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 951         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 952         if (!is_rx)
 953                 stat_mappings->tqsm[n] |= qsmr_mask;
 954         else
 955                 stat_mappings->rqsmr[n] |= qsmr_mask;
 956
 957         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 958                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 959                      queue_id, stat_idx);
 960         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 961                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 962
 963         /* Now write the mapping in the appropriate register */
 964         if (is_rx) {
 965                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 966                              stat_mappings->rqsmr[n], n);
 967                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 968         } else {
 969                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 970                              stat_mappings->tqsm[n], n);
 971                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 972         }
 973         return 0;
 974 }
 975
 976 static void
 977 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 978 {
 979         struct ixgbe_stat_mapping_registers *stat_mappings =
 980                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 981         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 982         int i;
 983
 984         /* write whatever was in stat mapping table to the NIC */
 985         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 986                 /* rx */
 987                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 988
 989                 /* tx */
 990                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 991         }
 992 }
 993
 994 static void
 995 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 996 {
 997         uint8_t i;
 998         struct ixgbe_dcb_tc_config *tc;
 999         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1000
1001         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1002         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1003         for (i = 0; i < dcb_max_tc; i++) {
1004                 tc = &dcb_config->tc_config[i];
1005                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1006                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1007                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1008                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1009                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1010                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1011                 tc->pfc = ixgbe_dcb_pfc_disabled;
1012         }
1013
1014         /* Initialize default user to priority mapping, UPx->TC0 */
1015         tc = &dcb_config->tc_config[0];
1016         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1017         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1018         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1019                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1020                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1021         }
1022         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1023         dcb_config->pfc_mode_enable = false;
1024         dcb_config->vt_mode = true;
1025         dcb_config->round_robin_enable = false;
1026         /* support all DCB capabilities in 82599 */
1027         dcb_config->support.capabilities = 0xFF;
1028
1029         /*we only support 4 Tcs for X540, X550 */
1030         if (hw->mac.type == ixgbe_mac_X540 ||
1031                 hw->mac.type == ixgbe_mac_X550 ||
1032                 hw->mac.type == ixgbe_mac_X550EM_x ||
1033                 hw->mac.type == ixgbe_mac_X550EM_a) {
1034                 dcb_config->num_tcs.pg_tcs = 4;
1035                 dcb_config->num_tcs.pfc_tcs = 4;
1036         }
1037 }
1038
1039 /*
1040  * Ensure that all locks are released before first NVM or PHY access
1041  */
1042 static void
1043 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1044 {
1045         uint16_t mask;
1046
1047         /*
1048          * Phy lock should not fail in this early stage. If this is the case,
1049          * it is due to an improper exit of the application.
1050          * So force the release of the faulty lock. Release of common lock
1051          * is done automatically by swfw_sync function.
1052          */
1053         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1054         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1055                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1056         }
1057         ixgbe_release_swfw_semaphore(hw, mask);
1058
1059         /*
1060          * These ones are more tricky since they are common to all ports; but
1061          * swfw_sync retries last long enough (1s) to be almost sure that if
1062          * lock can not be taken it is due to an improper lock of the
1063          * semaphore.
1064          */
1065         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1066         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1067                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1068         }
1069         ixgbe_release_swfw_semaphore(hw, mask);
1070 }
1071
1072 /*
1073  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1074  * It returns 0 on success.
1075  */
1076 static int
1077 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1078 {
1079         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1080         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1081         struct ixgbe_hw *hw =
1082                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1083         struct ixgbe_vfta *shadow_vfta =
1084                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1085         struct ixgbe_hwstrip *hwstrip =
1086                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1087         struct ixgbe_dcb_config *dcb_config =
1088                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1089         struct ixgbe_filter_info *filter_info =
1090                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1091         struct ixgbe_bw_conf *bw_conf =
1092                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1093         uint32_t ctrl_ext;
1094         uint16_t csum;
1095         int diag, i;
1096
1097         PMD_INIT_FUNC_TRACE();
1098
1099         ixgbe_dev_macsec_setting_reset(eth_dev);
1100
1101         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1102         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1103         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1104         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1105
1106         /*
1107          * For secondary processes, we don't initialise any further as primary
1108          * has already done this work. Only check we don't need a different
1109          * RX and TX function.
1110          */
1111         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1112                 struct ixgbe_tx_queue *txq;
1113                 /* TX queue function in primary, set by last queue initialized
1114                  * Tx queue may not initialized by primary process
1115                  */
1116                 if (eth_dev->data->tx_queues) {
1117                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1118                         ixgbe_set_tx_function(eth_dev, txq);
1119                 } else {
1120                         /* Use default TX function if we get here */
1121                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1122                                      "Using default TX function.");
1123                 }
1124
1125                 ixgbe_set_rx_function(eth_dev);
1126
1127                 return 0;
1128         }
1129
1130         rte_eth_copy_pci_info(eth_dev, pci_dev);
1131
1132         /* Vendor and Device ID need to be set before init of shared code */
1133         hw->device_id = pci_dev->id.device_id;
1134         hw->vendor_id = pci_dev->id.vendor_id;
1135         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1136         hw->allow_unsupported_sfp = 1;
1137
1138         /* Initialize the shared code (base driver) */
1139 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1140         diag = ixgbe_bypass_init_shared_code(hw);
1141 #else
1142         diag = ixgbe_init_shared_code(hw);
1143 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1144
1145         if (diag != IXGBE_SUCCESS) {
1146                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1147                 return -EIO;
1148         }
1149
1150         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1151                 PMD_INIT_LOG(ERR, "\nERROR: "
1152                         "Firmware recovery mode detected. Limiting functionality.\n"
1153                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1154                         "User Guide for details on firmware recovery mode.");
1155                 return -EIO;
1156         }
1157
1158         /* pick up the PCI bus settings for reporting later */
1159         ixgbe_get_bus_info(hw);
1160
1161         /* Unlock any pending hardware semaphore */
1162         ixgbe_swfw_lock_reset(hw);
1163
1164 #ifdef RTE_LIBRTE_SECURITY
1165         /* Initialize security_ctx only for primary process*/
1166         if (ixgbe_ipsec_ctx_create(eth_dev))
1167                 return -ENOMEM;
1168 #endif
1169
1170         /* Initialize DCB configuration*/
1171         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1172         ixgbe_dcb_init(hw, dcb_config);
1173         /* Get Hardware Flow Control setting */
1174         hw->fc.requested_mode = ixgbe_fc_full;
1175         hw->fc.current_mode = ixgbe_fc_full;
1176         hw->fc.pause_time = IXGBE_FC_PAUSE;
1177         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1178                 hw->fc.low_water[i] = IXGBE_FC_LO;
1179                 hw->fc.high_water[i] = IXGBE_FC_HI;
1180         }
1181         hw->fc.send_xon = 1;
1182
1183         /* Make sure we have a good EEPROM before we read from it */
1184         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1185         if (diag != IXGBE_SUCCESS) {
1186                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1187                 return -EIO;
1188         }
1189
1190 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1191         diag = ixgbe_bypass_init_hw(hw);
1192 #else
1193         diag = ixgbe_init_hw(hw);
1194         hw->mac.autotry_restart = false;
1195 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1196
1197         /*
1198          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1199          * is called too soon after the kernel driver unbinding/binding occurs.
1200          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1201          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1202          * also called. See ixgbe_identify_phy_82599(). The reason for the
1203          * failure is not known, and only occuts when virtualisation features
1204          * are disabled in the bios. A delay of 100ms  was found to be enough by
1205          * trial-and-error, and is doubled to be safe.
1206          */
1207         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1208                 rte_delay_ms(200);
1209                 diag = ixgbe_init_hw(hw);
1210         }
1211
1212         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1213                 diag = IXGBE_SUCCESS;
1214
1215         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1216                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1217                              "LOM.  Please be aware there may be issues associated "
1218                              "with your hardware.");
1219                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1220                              "please contact your Intel or hardware representative "
1221                              "who provided you with this hardware.");
1222         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1223                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1224         if (diag) {
1225                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1226                 return -EIO;
1227         }
1228
1229         /* Reset the hw statistics */
1230         ixgbe_dev_stats_reset(eth_dev);
1231
1232         /* disable interrupt */
1233         ixgbe_disable_intr(hw);
1234
1235         /* reset mappings for queue statistics hw counters*/
1236         ixgbe_reset_qstat_mappings(hw);
1237
1238         /* Allocate memory for storing MAC addresses */
1239         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1240                                                hw->mac.num_rar_entries, 0);
1241         if (eth_dev->data->mac_addrs == NULL) {
1242                 PMD_INIT_LOG(ERR,
1243                              "Failed to allocate %u bytes needed to store "
1244                              "MAC addresses",
1245                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1246                 return -ENOMEM;
1247         }
1248         /* Copy the permanent MAC address */
1249         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1250                         &eth_dev->data->mac_addrs[0]);
1251
1252         /* Allocate memory for storing hash filter MAC addresses */
1253         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1254                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1255         if (eth_dev->data->hash_mac_addrs == NULL) {
1256                 PMD_INIT_LOG(ERR,
1257                              "Failed to allocate %d bytes needed to store MAC addresses",
1258                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1259                 return -ENOMEM;
1260         }
1261
1262         /* Pass the information to the rte_eth_dev_close() that it should also
1263          * release the private port resources.
1264          */
1265         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1266
1267         /* initialize the vfta */
1268         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1269
1270         /* initialize the hw strip bitmap*/
1271         memset(hwstrip, 0, sizeof(*hwstrip));
1272
1273         /* initialize PF if max_vfs not zero */
1274         ixgbe_pf_host_init(eth_dev);
1275
1276         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1277         /* let hardware know driver is loaded */
1278         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1279         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1280         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1281         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1282         IXGBE_WRITE_FLUSH(hw);
1283
1284         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1285                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1286                              (int) hw->mac.type, (int) hw->phy.type,
1287                              (int) hw->phy.sfp_type);
1288         else
1289                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1290                              (int) hw->mac.type, (int) hw->phy.type);
1291
1292         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1293                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1294                      pci_dev->id.device_id);
1295
1296         rte_intr_callback_register(intr_handle,
1297                                    ixgbe_dev_interrupt_handler, eth_dev);
1298
1299         /* enable uio/vfio intr/eventfd mapping */
1300         rte_intr_enable(intr_handle);
1301
1302         /* enable support intr */
1303         ixgbe_enable_intr(eth_dev);
1304
1305         ixgbe_dev_set_link_down(eth_dev);
1306
1307         /* initialize filter info */
1308         memset(filter_info, 0,
1309                sizeof(struct ixgbe_filter_info));
1310
1311         /* initialize 5tuple filter list */
1312         TAILQ_INIT(&filter_info->fivetuple_list);
1313
1314         /* initialize flow director filter list & hash */
1315         ixgbe_fdir_filter_init(eth_dev);
1316
1317         /* initialize l2 tunnel filter list & hash */
1318         ixgbe_l2_tn_filter_init(eth_dev);
1319
1320         /* initialize flow filter lists */
1321         ixgbe_filterlist_init();
1322
1323         /* initialize bandwidth configuration info */
1324         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1325
1326         /* initialize Traffic Manager configuration */
1327         ixgbe_tm_conf_init(eth_dev);
1328
1329         return 0;
1330 }
1331
1332 static int
1333 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1334 {
1335         PMD_INIT_FUNC_TRACE();
1336
1337         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1338                 return 0;
1339
1340         ixgbe_dev_close(eth_dev);
1341
1342         return 0;
1343 }
1344
1345 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1346 {
1347         struct ixgbe_filter_info *filter_info =
1348                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1349         struct ixgbe_5tuple_filter *p_5tuple;
1350
1351         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1352                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1353                              p_5tuple,
1354                              entries);
1355                 rte_free(p_5tuple);
1356         }
1357         memset(filter_info->fivetuple_mask, 0,
1358                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1359
1360         return 0;
1361 }
1362
1363 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1364 {
1365         struct ixgbe_hw_fdir_info *fdir_info =
1366                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1367         struct ixgbe_fdir_filter *fdir_filter;
1368
1369                 if (fdir_info->hash_map)
1370                 rte_free(fdir_info->hash_map);
1371         if (fdir_info->hash_handle)
1372                 rte_hash_free(fdir_info->hash_handle);
1373
1374         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1375                 TAILQ_REMOVE(&fdir_info->fdir_list,
1376                              fdir_filter,
1377                              entries);
1378                 rte_free(fdir_filter);
1379         }
1380
1381         return 0;
1382 }
1383
1384 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1385 {
1386         struct ixgbe_l2_tn_info *l2_tn_info =
1387                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1388         struct ixgbe_l2_tn_filter *l2_tn_filter;
1389
1390         if (l2_tn_info->hash_map)
1391                 rte_free(l2_tn_info->hash_map);
1392         if (l2_tn_info->hash_handle)
1393                 rte_hash_free(l2_tn_info->hash_handle);
1394
1395         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1396                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1397                              l2_tn_filter,
1398                              entries);
1399                 rte_free(l2_tn_filter);
1400         }
1401
1402         return 0;
1403 }
1404
1405 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1406 {
1407         struct ixgbe_hw_fdir_info *fdir_info =
1408                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1409         char fdir_hash_name[RTE_HASH_NAMESIZE];
1410         struct rte_hash_parameters fdir_hash_params = {
1411                 .name = fdir_hash_name,
1412                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1413                 .key_len = sizeof(union ixgbe_atr_input),
1414                 .hash_func = rte_hash_crc,
1415                 .hash_func_init_val = 0,
1416                 .socket_id = rte_socket_id(),
1417         };
1418
1419         TAILQ_INIT(&fdir_info->fdir_list);
1420         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1421                  "fdir_%s", eth_dev->device->name);
1422         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1423         if (!fdir_info->hash_handle) {
1424                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1425                 return -EINVAL;
1426         }
1427         fdir_info->hash_map = rte_zmalloc("ixgbe",
1428                                           sizeof(struct ixgbe_fdir_filter *) *
1429                                           IXGBE_MAX_FDIR_FILTER_NUM,
1430                                           0);
1431         if (!fdir_info->hash_map) {
1432                 PMD_INIT_LOG(ERR,
1433                              "Failed to allocate memory for fdir hash map!");
1434                 return -ENOMEM;
1435         }
1436         fdir_info->mask_added = FALSE;
1437
1438         return 0;
1439 }
1440
1441 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1442 {
1443         struct ixgbe_l2_tn_info *l2_tn_info =
1444                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1445         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1446         struct rte_hash_parameters l2_tn_hash_params = {
1447                 .name = l2_tn_hash_name,
1448                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1449                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1450                 .hash_func = rte_hash_crc,
1451                 .hash_func_init_val = 0,
1452                 .socket_id = rte_socket_id(),
1453         };
1454
1455         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1456         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1457                  "l2_tn_%s", eth_dev->device->name);
1458         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1459         if (!l2_tn_info->hash_handle) {
1460                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1461                 return -EINVAL;
1462         }
1463         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1464                                    sizeof(struct ixgbe_l2_tn_filter *) *
1465                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1466                                    0);
1467         if (!l2_tn_info->hash_map) {
1468                 PMD_INIT_LOG(ERR,
1469                         "Failed to allocate memory for L2 TN hash map!");
1470                 return -ENOMEM;
1471         }
1472         l2_tn_info->e_tag_en = FALSE;
1473         l2_tn_info->e_tag_fwd_en = FALSE;
1474         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1475
1476         return 0;
1477 }
1478 /*
1479  * Negotiate mailbox API version with the PF.
1480  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1481  * Then we try to negotiate starting with the most recent one.
1482  * If all negotiation attempts fail, then we will proceed with
1483  * the default one (ixgbe_mbox_api_10).
1484  */
1485 static void
1486 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1487 {
1488         int32_t i;
1489
1490         /* start with highest supported, proceed down */
1491         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1492                 ixgbe_mbox_api_13,
1493                 ixgbe_mbox_api_12,
1494                 ixgbe_mbox_api_11,
1495                 ixgbe_mbox_api_10,
1496         };
1497
1498         for (i = 0;
1499                         i != RTE_DIM(sup_ver) &&
1500                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1501                         i++)
1502                 ;
1503 }
1504
1505 static void
1506 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1507 {
1508         uint64_t random;
1509
1510         /* Set Organizationally Unique Identifier (OUI) prefix. */
1511         mac_addr->addr_bytes[0] = 0x00;
1512         mac_addr->addr_bytes[1] = 0x09;
1513         mac_addr->addr_bytes[2] = 0xC0;
1514         /* Force indication of locally assigned MAC address. */
1515         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1516         /* Generate the last 3 bytes of the MAC address with a random number. */
1517         random = rte_rand();
1518         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1519 }
1520
1521 static int
1522 devarg_handle_int(__rte_unused const char *key, const char *value,
1523                   void *extra_args)
1524 {
1525         uint16_t *n = extra_args;
1526
1527         if (value == NULL || extra_args == NULL)
1528                 return -EINVAL;
1529
1530         *n = (uint16_t)strtoul(value, NULL, 0);
1531         if (*n == USHRT_MAX && errno == ERANGE)
1532                 return -1;
1533
1534         return 0;
1535 }
1536
1537 static void
1538 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1539                       struct rte_devargs *devargs)
1540 {
1541         struct rte_kvargs *kvlist;
1542         uint16_t pflink_fullchk;
1543
1544         if (devargs == NULL)
1545                 return;
1546
1547         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1548         if (kvlist == NULL)
1549                 return;
1550
1551         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1552             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1553                                devarg_handle_int, &pflink_fullchk) == 0 &&
1554             pflink_fullchk == 1)
1555                 adapter->pflink_fullchk = 1;
1556
1557         rte_kvargs_free(kvlist);
1558 }
1559
1560 /*
1561  * Virtual Function device init
1562  */
1563 static int
1564 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1565 {
1566         int diag;
1567         uint32_t tc, tcs;
1568         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1569         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1570         struct ixgbe_hw *hw =
1571                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1572         struct ixgbe_vfta *shadow_vfta =
1573                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1574         struct ixgbe_hwstrip *hwstrip =
1575                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1576         struct rte_ether_addr *perm_addr =
1577                 (struct rte_ether_addr *)hw->mac.perm_addr;
1578
1579         PMD_INIT_FUNC_TRACE();
1580
1581         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1582         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1583         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1584
1585         /* for secondary processes, we don't initialise any further as primary
1586          * has already done this work. Only check we don't need a different
1587          * RX function
1588          */
1589         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1590                 struct ixgbe_tx_queue *txq;
1591                 /* TX queue function in primary, set by last queue initialized
1592                  * Tx queue may not initialized by primary process
1593                  */
1594                 if (eth_dev->data->tx_queues) {
1595                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1596                         ixgbe_set_tx_function(eth_dev, txq);
1597                 } else {
1598                         /* Use default TX function if we get here */
1599                         PMD_INIT_LOG(NOTICE,
1600                                      "No TX queues configured yet. Using default TX function.");
1601                 }
1602
1603                 ixgbe_set_rx_function(eth_dev);
1604
1605                 return 0;
1606         }
1607
1608         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1609                               pci_dev->device.devargs);
1610
1611         rte_eth_copy_pci_info(eth_dev, pci_dev);
1612
1613         hw->device_id = pci_dev->id.device_id;
1614         hw->vendor_id = pci_dev->id.vendor_id;
1615         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1616
1617         /* initialize the vfta */
1618         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1619
1620         /* initialize the hw strip bitmap*/
1621         memset(hwstrip, 0, sizeof(*hwstrip));
1622
1623         /* Initialize the shared code (base driver) */
1624         diag = ixgbe_init_shared_code(hw);
1625         if (diag != IXGBE_SUCCESS) {
1626                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1627                 return -EIO;
1628         }
1629
1630         /* init_mailbox_params */
1631         hw->mbx.ops.init_params(hw);
1632
1633         /* Reset the hw statistics */
1634         ixgbevf_dev_stats_reset(eth_dev);
1635
1636         /* Disable the interrupts for VF */
1637         ixgbevf_intr_disable(eth_dev);
1638
1639         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1640         diag = hw->mac.ops.reset_hw(hw);
1641
1642         /*
1643          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1644          * the underlying PF driver has not assigned a MAC address to the VF.
1645          * In this case, assign a random MAC address.
1646          */
1647         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1648                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1649                 /*
1650                  * This error code will be propagated to the app by
1651                  * rte_eth_dev_reset, so use a public error code rather than
1652                  * the internal-only IXGBE_ERR_RESET_FAILED
1653                  */
1654                 return -EAGAIN;
1655         }
1656
1657         /* negotiate mailbox API version to use with the PF. */
1658         ixgbevf_negotiate_api(hw);
1659
1660         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1661         ixgbevf_get_queues(hw, &tcs, &tc);
1662
1663         /* Allocate memory for storing MAC addresses */
1664         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1665                                                hw->mac.num_rar_entries, 0);
1666         if (eth_dev->data->mac_addrs == NULL) {
1667                 PMD_INIT_LOG(ERR,
1668                              "Failed to allocate %u bytes needed to store "
1669                              "MAC addresses",
1670                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1671                 return -ENOMEM;
1672         }
1673
1674         /* Pass the information to the rte_eth_dev_close() that it should also
1675          * release the private port resources.
1676          */
1677         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1678
1679         /* Generate a random MAC address, if none was assigned by PF. */
1680         if (rte_is_zero_ether_addr(perm_addr)) {
1681                 generate_random_mac_addr(perm_addr);
1682                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1683                 if (diag) {
1684                         rte_free(eth_dev->data->mac_addrs);
1685                         eth_dev->data->mac_addrs = NULL;
1686                         return diag;
1687                 }
1688                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1689                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1690                              "%02x:%02x:%02x:%02x:%02x:%02x",
1691                              perm_addr->addr_bytes[0],
1692                              perm_addr->addr_bytes[1],
1693                              perm_addr->addr_bytes[2],
1694                              perm_addr->addr_bytes[3],
1695                              perm_addr->addr_bytes[4],
1696                              perm_addr->addr_bytes[5]);
1697         }
1698
1699         /* Copy the permanent MAC address */
1700         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1701
1702         /* reset the hardware with the new settings */
1703         diag = hw->mac.ops.start_hw(hw);
1704         switch (diag) {
1705         case  0:
1706                 break;
1707
1708         default:
1709                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1710                 return -EIO;
1711         }
1712
1713         rte_intr_callback_register(intr_handle,
1714                                    ixgbevf_dev_interrupt_handler, eth_dev);
1715         rte_intr_enable(intr_handle);
1716         ixgbevf_intr_enable(eth_dev);
1717
1718         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1719                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1720                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1721
1722         return 0;
1723 }
1724
1725 /* Virtual Function device uninit */
1726
1727 static int
1728 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1729 {
1730         PMD_INIT_FUNC_TRACE();
1731
1732         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1733                 return 0;
1734
1735         ixgbevf_dev_close(eth_dev);
1736
1737         return 0;
1738 }
1739
1740 static int
1741 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1742                 struct rte_pci_device *pci_dev)
1743 {
1744         char name[RTE_ETH_NAME_MAX_LEN];
1745         struct rte_eth_dev *pf_ethdev;
1746         struct rte_eth_devargs eth_da;
1747         int i, retval;
1748
1749         if (pci_dev->device.devargs) {
1750                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1751                                 &eth_da);
1752                 if (retval)
1753                         return retval;
1754         } else
1755                 memset(&eth_da, 0, sizeof(eth_da));
1756
1757         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1758                 sizeof(struct ixgbe_adapter),
1759                 eth_dev_pci_specific_init, pci_dev,
1760                 eth_ixgbe_dev_init, NULL);
1761
1762         if (retval || eth_da.nb_representor_ports < 1)
1763                 return retval;
1764
1765         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1766         if (pf_ethdev == NULL)
1767                 return -ENODEV;
1768
1769         /* probe VF representor ports */
1770         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1771                 struct ixgbe_vf_info *vfinfo;
1772                 struct ixgbe_vf_representor representor;
1773
1774                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1775                         pf_ethdev->data->dev_private);
1776                 if (vfinfo == NULL) {
1777                         PMD_DRV_LOG(ERR,
1778                                 "no virtual functions supported by PF");
1779                         break;
1780                 }
1781
1782                 representor.vf_id = eth_da.representor_ports[i];
1783                 representor.switch_domain_id = vfinfo->switch_domain_id;
1784                 representor.pf_ethdev = pf_ethdev;
1785
1786                 /* representor port net_bdf_port */
1787                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1788                         pci_dev->device.name,
1789                         eth_da.representor_ports[i]);
1790
1791                 retval = rte_eth_dev_create(&pci_dev->device, name,
1792                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1793                         ixgbe_vf_representor_init, &representor);
1794
1795                 if (retval)
1796                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1797                                 "representor %s.", name);
1798         }
1799
1800         return 0;
1801 }
1802
1803 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1804 {
1805         struct rte_eth_dev *ethdev;
1806
1807         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1808         if (!ethdev)
1809                 return 0;
1810
1811         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1812                 return rte_eth_dev_pci_generic_remove(pci_dev,
1813                                         ixgbe_vf_representor_uninit);
1814         else
1815                 return rte_eth_dev_pci_generic_remove(pci_dev,
1816                                                 eth_ixgbe_dev_uninit);
1817 }
1818
1819 static struct rte_pci_driver rte_ixgbe_pmd = {
1820         .id_table = pci_id_ixgbe_map,
1821         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1822         .probe = eth_ixgbe_pci_probe,
1823         .remove = eth_ixgbe_pci_remove,
1824 };
1825
1826 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1827         struct rte_pci_device *pci_dev)
1828 {
1829         return rte_eth_dev_pci_generic_probe(pci_dev,
1830                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1831 }
1832
1833 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1834 {
1835         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1836 }
1837
1838 /*
1839  * virtual function driver struct
1840  */
1841 static struct rte_pci_driver rte_ixgbevf_pmd = {
1842         .id_table = pci_id_ixgbevf_map,
1843         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1844         .probe = eth_ixgbevf_pci_probe,
1845         .remove = eth_ixgbevf_pci_remove,
1846 };
1847
1848 static int
1849 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1850 {
1851         struct ixgbe_hw *hw =
1852                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1853         struct ixgbe_vfta *shadow_vfta =
1854                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1855         uint32_t vfta;
1856         uint32_t vid_idx;
1857         uint32_t vid_bit;
1858
1859         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1860         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1861         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1862         if (on)
1863                 vfta |= vid_bit;
1864         else
1865                 vfta &= ~vid_bit;
1866         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1867
1868         /* update local VFTA copy */
1869         shadow_vfta->vfta[vid_idx] = vfta;
1870
1871         return 0;
1872 }
1873
1874 static void
1875 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1876 {
1877         if (on)
1878                 ixgbe_vlan_hw_strip_enable(dev, queue);
1879         else
1880                 ixgbe_vlan_hw_strip_disable(dev, queue);
1881 }
1882
1883 static int
1884 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1885                     enum rte_vlan_type vlan_type,
1886                     uint16_t tpid)
1887 {
1888         struct ixgbe_hw *hw =
1889                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1890         int ret = 0;
1891         uint32_t reg;
1892         uint32_t qinq;
1893
1894         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1895         qinq &= IXGBE_DMATXCTL_GDV;
1896
1897         switch (vlan_type) {
1898         case ETH_VLAN_TYPE_INNER:
1899                 if (qinq) {
1900                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1901                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1902                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1903                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1904                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1905                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1906                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1907                 } else {
1908                         ret = -ENOTSUP;
1909                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1910                                     " by single VLAN");
1911                 }
1912                 break;
1913         case ETH_VLAN_TYPE_OUTER:
1914                 if (qinq) {
1915                         /* Only the high 16-bits is valid */
1916                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1917                                         IXGBE_EXVET_VET_EXT_SHIFT);
1918                 } else {
1919                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1920                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1921                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1922                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1923                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1924                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1925                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1926                 }
1927
1928                 break;
1929         default:
1930                 ret = -EINVAL;
1931                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1932                 break;
1933         }
1934
1935         return ret;
1936 }
1937
1938 void
1939 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1940 {
1941         struct ixgbe_hw *hw =
1942                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1943         uint32_t vlnctrl;
1944
1945         PMD_INIT_FUNC_TRACE();
1946
1947         /* Filter Table Disable */
1948         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1949         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1950
1951         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1952 }
1953
1954 void
1955 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1956 {
1957         struct ixgbe_hw *hw =
1958                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1959         struct ixgbe_vfta *shadow_vfta =
1960                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1961         uint32_t vlnctrl;
1962         uint16_t i;
1963
1964         PMD_INIT_FUNC_TRACE();
1965
1966         /* Filter Table Enable */
1967         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1968         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1969         vlnctrl |= IXGBE_VLNCTRL_VFE;
1970
1971         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1972
1973         /* write whatever is in local vfta copy */
1974         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1975                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1976 }
1977
1978 static void
1979 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1980 {
1981         struct ixgbe_hwstrip *hwstrip =
1982                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1983         struct ixgbe_rx_queue *rxq;
1984
1985         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1986                 return;
1987
1988         if (on)
1989                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1990         else
1991                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1992
1993         if (queue >= dev->data->nb_rx_queues)
1994                 return;
1995
1996         rxq = dev->data->rx_queues[queue];
1997
1998         if (on) {
1999                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2000                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2001         } else {
2002                 rxq->vlan_flags = PKT_RX_VLAN;
2003                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2004         }
2005 }
2006
2007 static void
2008 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2009 {
2010         struct ixgbe_hw *hw =
2011                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2012         uint32_t ctrl;
2013
2014         PMD_INIT_FUNC_TRACE();
2015
2016         if (hw->mac.type == ixgbe_mac_82598EB) {
2017                 /* No queue level support */
2018                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2019                 return;
2020         }
2021
2022         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2023         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2024         ctrl &= ~IXGBE_RXDCTL_VME;
2025         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2026
2027         /* record those setting for HW strip per queue */
2028         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2029 }
2030
2031 static void
2032 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2033 {
2034         struct ixgbe_hw *hw =
2035                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2036         uint32_t ctrl;
2037
2038         PMD_INIT_FUNC_TRACE();
2039
2040         if (hw->mac.type == ixgbe_mac_82598EB) {
2041                 /* No queue level supported */
2042                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2043                 return;
2044         }
2045
2046         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2047         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2048         ctrl |= IXGBE_RXDCTL_VME;
2049         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2050
2051         /* record those setting for HW strip per queue */
2052         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2053 }
2054
2055 static void
2056 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2057 {
2058         struct ixgbe_hw *hw =
2059                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2060         uint32_t ctrl;
2061
2062         PMD_INIT_FUNC_TRACE();
2063
2064         /* DMATXCTRL: Geric Double VLAN Disable */
2065         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2066         ctrl &= ~IXGBE_DMATXCTL_GDV;
2067         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2068
2069         /* CTRL_EXT: Global Double VLAN Disable */
2070         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2071         ctrl &= ~IXGBE_EXTENDED_VLAN;
2072         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2073
2074 }
2075
2076 static void
2077 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2078 {
2079         struct ixgbe_hw *hw =
2080                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2081         uint32_t ctrl;
2082
2083         PMD_INIT_FUNC_TRACE();
2084
2085         /* DMATXCTRL: Geric Double VLAN Enable */
2086         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2087         ctrl |= IXGBE_DMATXCTL_GDV;
2088         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2089
2090         /* CTRL_EXT: Global Double VLAN Enable */
2091         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2092         ctrl |= IXGBE_EXTENDED_VLAN;
2093         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2094
2095         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2096         if (hw->mac.type == ixgbe_mac_X550 ||
2097             hw->mac.type == ixgbe_mac_X550EM_x ||
2098             hw->mac.type == ixgbe_mac_X550EM_a) {
2099                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2100                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2101                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2102         }
2103
2104         /*
2105          * VET EXT field in the EXVET register = 0x8100 by default
2106          * So no need to change. Same to VT field of DMATXCTL register
2107          */
2108 }
2109
2110 void
2111 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2112 {
2113         struct ixgbe_hw *hw =
2114                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2115         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2116         uint32_t ctrl;
2117         uint16_t i;
2118         struct ixgbe_rx_queue *rxq;
2119         bool on;
2120
2121         PMD_INIT_FUNC_TRACE();
2122
2123         if (hw->mac.type == ixgbe_mac_82598EB) {
2124                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2125                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2126                         ctrl |= IXGBE_VLNCTRL_VME;
2127                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2128                 } else {
2129                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2130                         ctrl &= ~IXGBE_VLNCTRL_VME;
2131                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2132                 }
2133         } else {
2134                 /*
2135                  * Other 10G NIC, the VLAN strip can be setup
2136                  * per queue in RXDCTL
2137                  */
2138                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2139                         rxq = dev->data->rx_queues[i];
2140                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2141                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2142                                 ctrl |= IXGBE_RXDCTL_VME;
2143                                 on = TRUE;
2144                         } else {
2145                                 ctrl &= ~IXGBE_RXDCTL_VME;
2146                                 on = FALSE;
2147                         }
2148                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2149
2150                         /* record those setting for HW strip per queue */
2151                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2152                 }
2153         }
2154 }
2155
2156 static void
2157 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2158 {
2159         uint16_t i;
2160         struct rte_eth_rxmode *rxmode;
2161         struct ixgbe_rx_queue *rxq;
2162
2163         if (mask & ETH_VLAN_STRIP_MASK) {
2164                 rxmode = &dev->data->dev_conf.rxmode;
2165                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2166                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2167                                 rxq = dev->data->rx_queues[i];
2168                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2169                         }
2170                 else
2171                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2172                                 rxq = dev->data->rx_queues[i];
2173                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2174                         }
2175         }
2176 }
2177
2178 static int
2179 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2180 {
2181         struct rte_eth_rxmode *rxmode;
2182         rxmode = &dev->data->dev_conf.rxmode;
2183
2184         if (mask & ETH_VLAN_STRIP_MASK) {
2185                 ixgbe_vlan_hw_strip_config(dev);
2186         }
2187
2188         if (mask & ETH_VLAN_FILTER_MASK) {
2189                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2190                         ixgbe_vlan_hw_filter_enable(dev);
2191                 else
2192                         ixgbe_vlan_hw_filter_disable(dev);
2193         }
2194
2195         if (mask & ETH_VLAN_EXTEND_MASK) {
2196                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2197                         ixgbe_vlan_hw_extend_enable(dev);
2198                 else
2199                         ixgbe_vlan_hw_extend_disable(dev);
2200         }
2201
2202         return 0;
2203 }
2204
2205 static int
2206 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2207 {
2208         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2209
2210         ixgbe_vlan_offload_config(dev, mask);
2211
2212         return 0;
2213 }
2214
2215 static void
2216 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2217 {
2218         struct ixgbe_hw *hw =
2219                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2220         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2221         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2222
2223         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2224         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2225 }
2226
2227 static int
2228 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2229 {
2230         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2231
2232         switch (nb_rx_q) {
2233         case 1:
2234         case 2:
2235                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2236                 break;
2237         case 4:
2238                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2239                 break;
2240         default:
2241                 return -EINVAL;
2242         }
2243
2244         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2245                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2246         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2247                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2248         return 0;
2249 }
2250
2251 static int
2252 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2253 {
2254         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2255         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2256         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2257         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2258
2259         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2260                 /* check multi-queue mode */
2261                 switch (dev_conf->rxmode.mq_mode) {
2262                 case ETH_MQ_RX_VMDQ_DCB:
2263                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2264                         break;
2265                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2266                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2267                         PMD_INIT_LOG(ERR, "SRIOV active,"
2268                                         " unsupported mq_mode rx %d.",
2269                                         dev_conf->rxmode.mq_mode);
2270                         return -EINVAL;
2271                 case ETH_MQ_RX_RSS:
2272                 case ETH_MQ_RX_VMDQ_RSS:
2273                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2274                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2275                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2276                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2277                                                 " invalid queue number"
2278                                                 " for VMDQ RSS, allowed"
2279                                                 " value are 1, 2 or 4.");
2280                                         return -EINVAL;
2281                                 }
2282                         break;
2283                 case ETH_MQ_RX_VMDQ_ONLY:
2284                 case ETH_MQ_RX_NONE:
2285                         /* if nothing mq mode configure, use default scheme */
2286                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2287                         break;
2288                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2289                         /* SRIOV only works in VMDq enable mode */
2290                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2291                                         " wrong mq_mode rx %d.",
2292                                         dev_conf->rxmode.mq_mode);
2293                         return -EINVAL;
2294                 }
2295
2296                 switch (dev_conf->txmode.mq_mode) {
2297                 case ETH_MQ_TX_VMDQ_DCB:
2298                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2299                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2300                         break;
2301                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2302                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2303                         break;
2304                 }
2305
2306                 /* check valid queue number */
2307                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2308                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2309                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2310                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2311                                         " must be less than or equal to %d.",
2312                                         nb_rx_q, nb_tx_q,
2313                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2314                         return -EINVAL;
2315                 }
2316         } else {
2317                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2318                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2319                                           " not supported.");
2320                         return -EINVAL;
2321                 }
2322                 /* check configuration for vmdb+dcb mode */
2323                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2324                         const struct rte_eth_vmdq_dcb_conf *conf;
2325
2326                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2327                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2328                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2329                                 return -EINVAL;
2330                         }
2331                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2332                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2333                                conf->nb_queue_pools == ETH_32_POOLS)) {
2334                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2335                                                 " nb_queue_pools must be %d or %d.",
2336                                                 ETH_16_POOLS, ETH_32_POOLS);
2337                                 return -EINVAL;
2338                         }
2339                 }
2340                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2341                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2342
2343                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2344                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2345                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2346                                 return -EINVAL;
2347                         }
2348                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2349                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2350                                conf->nb_queue_pools == ETH_32_POOLS)) {
2351                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2352                                                 " nb_queue_pools != %d and"
2353                                                 " nb_queue_pools != %d.",
2354                                                 ETH_16_POOLS, ETH_32_POOLS);
2355                                 return -EINVAL;
2356                         }
2357                 }
2358
2359                 /* For DCB mode check our configuration before we go further */
2360                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2361                         const struct rte_eth_dcb_rx_conf *conf;
2362
2363                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2364                         if (!(conf->nb_tcs == ETH_4_TCS ||
2365                                conf->nb_tcs == ETH_8_TCS)) {
2366                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2367                                                 " and nb_tcs != %d.",
2368                                                 ETH_4_TCS, ETH_8_TCS);
2369                                 return -EINVAL;
2370                         }
2371                 }
2372
2373                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2374                         const struct rte_eth_dcb_tx_conf *conf;
2375
2376                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2377                         if (!(conf->nb_tcs == ETH_4_TCS ||
2378                                conf->nb_tcs == ETH_8_TCS)) {
2379                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2380                                                 " and nb_tcs != %d.",
2381                                                 ETH_4_TCS, ETH_8_TCS);
2382                                 return -EINVAL;
2383                         }
2384                 }
2385
2386                 /*
2387                  * When DCB/VT is off, maximum number of queues changes,
2388                  * except for 82598EB, which remains constant.
2389                  */
2390                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2391                                 hw->mac.type != ixgbe_mac_82598EB) {
2392                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2393                                 PMD_INIT_LOG(ERR,
2394                                              "Neither VT nor DCB are enabled, "
2395                                              "nb_tx_q > %d.",
2396                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2397                                 return -EINVAL;
2398                         }
2399                 }
2400         }
2401         return 0;
2402 }
2403
2404 static int
2405 ixgbe_dev_configure(struct rte_eth_dev *dev)
2406 {
2407         struct ixgbe_interrupt *intr =
2408                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2409         struct ixgbe_adapter *adapter = dev->data->dev_private;
2410         int ret;
2411
2412         PMD_INIT_FUNC_TRACE();
2413
2414         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2415                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2416
2417         /* multipe queue mode checking */
2418         ret  = ixgbe_check_mq_mode(dev);
2419         if (ret != 0) {
2420                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2421                             ret);
2422                 return ret;
2423         }
2424
2425         /* set flag to update link status after init */
2426         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2427
2428         /*
2429          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2430          * allocation or vector Rx preconditions we will reset it.
2431          */
2432         adapter->rx_bulk_alloc_allowed = true;
2433         adapter->rx_vec_allowed = true;
2434
2435         return 0;
2436 }
2437
2438 static void
2439 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2440 {
2441         struct ixgbe_hw *hw =
2442                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2443         struct ixgbe_interrupt *intr =
2444                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2445         uint32_t gpie;
2446
2447         /* only set up it on X550EM_X */
2448         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2449                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2450                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2451                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2452                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2453                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2454         }
2455 }
2456
2457 int
2458 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2459                         uint16_t tx_rate, uint64_t q_msk)
2460 {
2461         struct ixgbe_hw *hw;
2462         struct ixgbe_vf_info *vfinfo;
2463         struct rte_eth_link link;
2464         uint8_t  nb_q_per_pool;
2465         uint32_t queue_stride;
2466         uint32_t queue_idx, idx = 0, vf_idx;
2467         uint32_t queue_end;
2468         uint16_t total_rate = 0;
2469         struct rte_pci_device *pci_dev;
2470         int ret;
2471
2472         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2473         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2474         if (ret < 0)
2475                 return ret;
2476
2477         if (vf >= pci_dev->max_vfs)
2478                 return -EINVAL;
2479
2480         if (tx_rate > link.link_speed)
2481                 return -EINVAL;
2482
2483         if (q_msk == 0)
2484                 return 0;
2485
2486         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2487         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2488         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2489         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2490         queue_idx = vf * queue_stride;
2491         queue_end = queue_idx + nb_q_per_pool - 1;
2492         if (queue_end >= hw->mac.max_tx_queues)
2493                 return -EINVAL;
2494
2495         if (vfinfo) {
2496                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2497                         if (vf_idx == vf)
2498                                 continue;
2499                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2500                                 idx++)
2501                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2502                 }
2503         } else {
2504                 return -EINVAL;
2505         }
2506
2507         /* Store tx_rate for this vf. */
2508         for (idx = 0; idx < nb_q_per_pool; idx++) {
2509                 if (((uint64_t)0x1 << idx) & q_msk) {
2510                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2511                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2512                         total_rate += tx_rate;
2513                 }
2514         }
2515
2516         if (total_rate > dev->data->dev_link.link_speed) {
2517                 /* Reset stored TX rate of the VF if it causes exceed
2518                  * link speed.
2519                  */
2520                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2521                 return -EINVAL;
2522         }
2523
2524         /* Set RTTBCNRC of each queue/pool for vf X  */
2525         for (; queue_idx <= queue_end; queue_idx++) {
2526                 if (0x1 & q_msk)
2527                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2528                 q_msk = q_msk >> 1;
2529         }
2530
2531         return 0;
2532 }
2533
2534 /*
2535  * Configure device link speed and setup link.
2536  * It returns 0 on success.
2537  */
2538 static int
2539 ixgbe_dev_start(struct rte_eth_dev *dev)
2540 {
2541         struct ixgbe_hw *hw =
2542                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2543         struct ixgbe_vf_info *vfinfo =
2544                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2545         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2546         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2547         uint32_t intr_vector = 0;
2548         int err;
2549         bool link_up = false, negotiate = 0;
2550         uint32_t speed = 0;
2551         uint32_t allowed_speeds = 0;
2552         int mask = 0;
2553         int status;
2554         uint16_t vf, idx;
2555         uint32_t *link_speeds;
2556         struct ixgbe_tm_conf *tm_conf =
2557                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2558         struct ixgbe_macsec_setting *macsec_setting =
2559                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2560
2561         PMD_INIT_FUNC_TRACE();
2562
2563         /* Stop the link setup handler before resetting the HW. */
2564         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2565
2566         /* disable uio/vfio intr/eventfd mapping */
2567         rte_intr_disable(intr_handle);
2568
2569         /* stop adapter */
2570         hw->adapter_stopped = 0;
2571         ixgbe_stop_adapter(hw);
2572
2573         /* reinitialize adapter
2574          * this calls reset and start
2575          */
2576         status = ixgbe_pf_reset_hw(hw);
2577         if (status != 0)
2578                 return -1;
2579         hw->mac.ops.start_hw(hw);
2580         hw->mac.get_link_status = true;
2581
2582         /* configure PF module if SRIOV enabled */
2583         ixgbe_pf_host_configure(dev);
2584
2585         ixgbe_dev_phy_intr_setup(dev);
2586
2587         /* check and configure queue intr-vector mapping */
2588         if ((rte_intr_cap_multiple(intr_handle) ||
2589              !RTE_ETH_DEV_SRIOV(dev).active) &&
2590             dev->data->dev_conf.intr_conf.rxq != 0) {
2591                 intr_vector = dev->data->nb_rx_queues;
2592                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2593                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2594                                         IXGBE_MAX_INTR_QUEUE_NUM);
2595                         return -ENOTSUP;
2596                 }
2597                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2598                         return -1;
2599         }
2600
2601         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2602                 intr_handle->intr_vec =
2603                         rte_zmalloc("intr_vec",
2604                                     dev->data->nb_rx_queues * sizeof(int), 0);
2605                 if (intr_handle->intr_vec == NULL) {
2606                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2607                                      " intr_vec", dev->data->nb_rx_queues);
2608                         return -ENOMEM;
2609                 }
2610         }
2611
2612         /* confiugre msix for sleep until rx interrupt */
2613         ixgbe_configure_msix(dev);
2614
2615         /* initialize transmission unit */
2616         ixgbe_dev_tx_init(dev);
2617
2618         /* This can fail when allocating mbufs for descriptor rings */
2619         err = ixgbe_dev_rx_init(dev);
2620         if (err) {
2621                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2622                 goto error;
2623         }
2624
2625         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2626                 ETH_VLAN_EXTEND_MASK;
2627         err = ixgbe_vlan_offload_config(dev, mask);
2628         if (err) {
2629                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2630                 goto error;
2631         }
2632
2633         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2634                 /* Enable vlan filtering for VMDq */
2635                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2636         }
2637
2638         /* Configure DCB hw */
2639         ixgbe_configure_dcb(dev);
2640
2641         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2642                 err = ixgbe_fdir_configure(dev);
2643                 if (err)
2644                         goto error;
2645         }
2646
2647         /* Restore vf rate limit */
2648         if (vfinfo != NULL) {
2649                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2650                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2651                                 if (vfinfo[vf].tx_rate[idx] != 0)
2652                                         ixgbe_set_vf_rate_limit(
2653                                                 dev, vf,
2654                                                 vfinfo[vf].tx_rate[idx],
2655                                                 1 << idx);
2656         }
2657
2658         ixgbe_restore_statistics_mapping(dev);
2659
2660         err = ixgbe_dev_rxtx_start(dev);
2661         if (err < 0) {
2662                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2663                 goto error;
2664         }
2665
2666         /* Skip link setup if loopback mode is enabled. */
2667         if (dev->data->dev_conf.lpbk_mode != 0) {
2668                 err = ixgbe_check_supported_loopback_mode(dev);
2669                 if (err < 0) {
2670                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2671                         goto error;
2672                 } else {
2673                         goto skip_link_setup;
2674                 }
2675         }
2676
2677         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2678                 err = hw->mac.ops.setup_sfp(hw);
2679                 if (err)
2680                         goto error;
2681         }
2682
2683         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2684                 /* Turn on the copper */
2685                 ixgbe_set_phy_power(hw, true);
2686         } else {
2687                 /* Turn on the laser */
2688                 ixgbe_enable_tx_laser(hw);
2689         }
2690
2691         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2692         if (err)
2693                 goto error;
2694         dev->data->dev_link.link_status = link_up;
2695
2696         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2697         if (err)
2698                 goto error;
2699
2700         switch (hw->mac.type) {
2701         case ixgbe_mac_X550:
2702         case ixgbe_mac_X550EM_x:
2703         case ixgbe_mac_X550EM_a:
2704                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2705                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2706                         ETH_LINK_SPEED_10G;
2707                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2708                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2709                         allowed_speeds = ETH_LINK_SPEED_10M |
2710                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2711                 break;
2712         default:
2713                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2714                         ETH_LINK_SPEED_10G;
2715         }
2716
2717         link_speeds = &dev->data->dev_conf.link_speeds;
2718
2719         /* Ignore autoneg flag bit and check the validity of
2720          * link_speed
2721          */
2722         if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2723                 PMD_INIT_LOG(ERR, "Invalid link setting");
2724                 goto error;
2725         }
2726
2727         speed = 0x0;
2728         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2729                 switch (hw->mac.type) {
2730                 case ixgbe_mac_82598EB:
2731                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2732                         break;
2733                 case ixgbe_mac_82599EB:
2734                 case ixgbe_mac_X540:
2735                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2736                         break;
2737                 case ixgbe_mac_X550:
2738                 case ixgbe_mac_X550EM_x:
2739                 case ixgbe_mac_X550EM_a:
2740                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2741                         break;
2742                 default:
2743                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2744                 }
2745         } else {
2746                 if (*link_speeds & ETH_LINK_SPEED_10G)
2747                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2748                 if (*link_speeds & ETH_LINK_SPEED_5G)
2749                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2750                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2751                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2752                 if (*link_speeds & ETH_LINK_SPEED_1G)
2753                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2754                 if (*link_speeds & ETH_LINK_SPEED_100M)
2755                         speed |= IXGBE_LINK_SPEED_100_FULL;
2756                 if (*link_speeds & ETH_LINK_SPEED_10M)
2757                         speed |= IXGBE_LINK_SPEED_10_FULL;
2758         }
2759
2760         err = ixgbe_setup_link(hw, speed, link_up);
2761         if (err)
2762                 goto error;
2763
2764 skip_link_setup:
2765
2766         if (rte_intr_allow_others(intr_handle)) {
2767                 /* check if lsc interrupt is enabled */
2768                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2769                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2770                 else
2771                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2772                 ixgbe_dev_macsec_interrupt_setup(dev);
2773         } else {
2774                 rte_intr_callback_unregister(intr_handle,
2775                                              ixgbe_dev_interrupt_handler, dev);
2776                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2777                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2778                                      " no intr multiplex");
2779         }
2780
2781         /* check if rxq interrupt is enabled */
2782         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2783             rte_intr_dp_is_en(intr_handle))
2784                 ixgbe_dev_rxq_interrupt_setup(dev);
2785
2786         /* enable uio/vfio intr/eventfd mapping */
2787         rte_intr_enable(intr_handle);
2788
2789         /* resume enabled intr since hw reset */
2790         ixgbe_enable_intr(dev);
2791         ixgbe_l2_tunnel_conf(dev);
2792         ixgbe_filter_restore(dev);
2793
2794         if (tm_conf->root && !tm_conf->committed)
2795                 PMD_DRV_LOG(WARNING,
2796                             "please call hierarchy_commit() "
2797                             "before starting the port");
2798
2799         /* wait for the controller to acquire link */
2800         err = ixgbe_wait_for_link_up(hw);
2801         if (err)
2802                 goto error;
2803
2804         /*
2805          * Update link status right before return, because it may
2806          * start link configuration process in a separate thread.
2807          */
2808         ixgbe_dev_link_update(dev, 0);
2809
2810         /* setup the macsec setting register */
2811         if (macsec_setting->offload_en)
2812                 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2813
2814         return 0;
2815
2816 error:
2817         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2818         ixgbe_dev_clear_queues(dev);
2819         return -EIO;
2820 }
2821
2822 /*
2823  * Stop device: disable rx and tx functions to allow for reconfiguring.
2824  */
2825 static void
2826 ixgbe_dev_stop(struct rte_eth_dev *dev)
2827 {
2828         struct rte_eth_link link;
2829         struct ixgbe_adapter *adapter = dev->data->dev_private;
2830         struct ixgbe_hw *hw =
2831                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2832         struct ixgbe_vf_info *vfinfo =
2833                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2834         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2835         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2836         int vf;
2837         struct ixgbe_tm_conf *tm_conf =
2838                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2839
2840         if (hw->adapter_stopped)
2841                 return;
2842
2843         PMD_INIT_FUNC_TRACE();
2844
2845         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2846
2847         /* disable interrupts */
2848         ixgbe_disable_intr(hw);
2849
2850         /* reset the NIC */
2851         ixgbe_pf_reset_hw(hw);
2852         hw->adapter_stopped = 0;
2853
2854         /* stop adapter */
2855         ixgbe_stop_adapter(hw);
2856
2857         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2858                 vfinfo[vf].clear_to_send = false;
2859
2860         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2861                 /* Turn off the copper */
2862                 ixgbe_set_phy_power(hw, false);
2863         } else {
2864                 /* Turn off the laser */
2865                 ixgbe_disable_tx_laser(hw);
2866         }
2867
2868         ixgbe_dev_clear_queues(dev);
2869
2870         /* Clear stored conf */
2871         dev->data->scattered_rx = 0;
2872         dev->data->lro = 0;
2873
2874         /* Clear recorded link status */
2875         memset(&link, 0, sizeof(link));
2876         rte_eth_linkstatus_set(dev, &link);
2877
2878         if (!rte_intr_allow_others(intr_handle))
2879                 /* resume to the default handler */
2880                 rte_intr_callback_register(intr_handle,
2881                                            ixgbe_dev_interrupt_handler,
2882                                            (void *)dev);
2883
2884         /* Clean datapath event and queue/vec mapping */
2885         rte_intr_efd_disable(intr_handle);
2886         if (intr_handle->intr_vec != NULL) {
2887                 rte_free(intr_handle->intr_vec);
2888                 intr_handle->intr_vec = NULL;
2889         }
2890
2891         /* reset hierarchy commit */
2892         tm_conf->committed = false;
2893
2894         adapter->rss_reta_updated = 0;
2895
2896         hw->adapter_stopped = true;
2897 }
2898
2899 /*
2900  * Set device link up: enable tx.
2901  */
2902 static int
2903 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2904 {
2905         struct ixgbe_hw *hw =
2906                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2907         if (hw->mac.type == ixgbe_mac_82599EB) {
2908 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2909                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2910                         /* Not suported in bypass mode */
2911                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2912                                      "by device id 0x%x", hw->device_id);
2913                         return -ENOTSUP;
2914                 }
2915 #endif
2916         }
2917
2918         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2919                 /* Turn on the copper */
2920                 ixgbe_set_phy_power(hw, true);
2921         } else {
2922                 /* Turn on the laser */
2923                 ixgbe_enable_tx_laser(hw);
2924                 ixgbe_dev_link_update(dev, 0);
2925         }
2926
2927         return 0;
2928 }
2929
2930 /*
2931  * Set device link down: disable tx.
2932  */
2933 static int
2934 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2935 {
2936         struct ixgbe_hw *hw =
2937                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2938         if (hw->mac.type == ixgbe_mac_82599EB) {
2939 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2940                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2941                         /* Not suported in bypass mode */
2942                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2943                                      "by device id 0x%x", hw->device_id);
2944                         return -ENOTSUP;
2945                 }
2946 #endif
2947         }
2948
2949         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2950                 /* Turn off the copper */
2951                 ixgbe_set_phy_power(hw, false);
2952         } else {
2953                 /* Turn off the laser */
2954                 ixgbe_disable_tx_laser(hw);
2955                 ixgbe_dev_link_update(dev, 0);
2956         }
2957
2958         return 0;
2959 }
2960
2961 /*
2962  * Reset and stop device.
2963  */
2964 static void
2965 ixgbe_dev_close(struct rte_eth_dev *dev)
2966 {
2967         struct ixgbe_hw *hw =
2968                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2969         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2970         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2971         int retries = 0;
2972         int ret;
2973
2974         PMD_INIT_FUNC_TRACE();
2975
2976         ixgbe_pf_reset_hw(hw);
2977
2978         ixgbe_dev_stop(dev);
2979
2980         ixgbe_dev_free_queues(dev);
2981
2982         ixgbe_disable_pcie_master(hw);
2983
2984         /* reprogram the RAR[0] in case user changed it. */
2985         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2986
2987         dev->dev_ops = NULL;
2988         dev->rx_pkt_burst = NULL;
2989         dev->tx_pkt_burst = NULL;
2990
2991         /* Unlock any pending hardware semaphore */
2992         ixgbe_swfw_lock_reset(hw);
2993
2994         /* disable uio intr before callback unregister */
2995         rte_intr_disable(intr_handle);
2996
2997         do {
2998                 ret = rte_intr_callback_unregister(intr_handle,
2999                                 ixgbe_dev_interrupt_handler, dev);
3000                 if (ret >= 0 || ret == -ENOENT) {
3001                         break;
3002                 } else if (ret != -EAGAIN) {
3003                         PMD_INIT_LOG(ERR,
3004                                 "intr callback unregister failed: %d",
3005                                 ret);
3006                 }
3007                 rte_delay_ms(100);
3008         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3009
3010         /* cancel the delay handler before remove dev */
3011         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3012
3013         /* uninitialize PF if max_vfs not zero */
3014         ixgbe_pf_host_uninit(dev);
3015
3016         /* remove all the fdir filters & hash */
3017         ixgbe_fdir_filter_uninit(dev);
3018
3019         /* remove all the L2 tunnel filters & hash */
3020         ixgbe_l2_tn_filter_uninit(dev);
3021
3022         /* Remove all ntuple filters of the device */
3023         ixgbe_ntuple_filter_uninit(dev);
3024
3025         /* clear all the filters list */
3026         ixgbe_filterlist_flush();
3027
3028         /* Remove all Traffic Manager configuration */
3029         ixgbe_tm_conf_uninit(dev);
3030
3031 #ifdef RTE_LIBRTE_SECURITY
3032         rte_free(dev->security_ctx);
3033 #endif
3034
3035 }
3036
3037 /*
3038  * Reset PF device.
3039  */
3040 static int
3041 ixgbe_dev_reset(struct rte_eth_dev *dev)
3042 {
3043         int ret;
3044
3045         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3046          * its VF to make them align with it. The detailed notification
3047          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3048          * To avoid unexpected behavior in VF, currently reset of PF with
3049          * SR-IOV activation is not supported. It might be supported later.
3050          */
3051         if (dev->data->sriov.active)
3052                 return -ENOTSUP;
3053
3054         ret = eth_ixgbe_dev_uninit(dev);
3055         if (ret)
3056                 return ret;
3057
3058         ret = eth_ixgbe_dev_init(dev, NULL);
3059
3060         return ret;
3061 }
3062
3063 static void
3064 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3065                            struct ixgbe_hw_stats *hw_stats,
3066                            struct ixgbe_macsec_stats *macsec_stats,
3067                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3068                            uint64_t *total_qprc, uint64_t *total_qprdc)
3069 {
3070         uint32_t bprc, lxon, lxoff, total;
3071         uint32_t delta_gprc = 0;
3072         unsigned i;
3073         /* Workaround for RX byte count not including CRC bytes when CRC
3074          * strip is enabled. CRC bytes are removed from counters when crc_strip
3075          * is disabled.
3076          */
3077         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3078                         IXGBE_HLREG0_RXCRCSTRP);
3079
3080         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3081         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3082         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3083         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3084
3085         for (i = 0; i < 8; i++) {
3086                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3087
3088                 /* global total per queue */
3089                 hw_stats->mpc[i] += mp;
3090                 /* Running comprehensive total for stats display */
3091                 *total_missed_rx += hw_stats->mpc[i];
3092                 if (hw->mac.type == ixgbe_mac_82598EB) {
3093                         hw_stats->rnbc[i] +=
3094                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3095                         hw_stats->pxonrxc[i] +=
3096                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3097                         hw_stats->pxoffrxc[i] +=
3098                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3099                 } else {
3100                         hw_stats->pxonrxc[i] +=
3101                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3102                         hw_stats->pxoffrxc[i] +=
3103                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3104                         hw_stats->pxon2offc[i] +=
3105                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3106                 }
3107                 hw_stats->pxontxc[i] +=
3108                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3109                 hw_stats->pxofftxc[i] +=
3110                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3111         }
3112         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3113                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3114                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3115                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3116
3117                 delta_gprc += delta_qprc;
3118
3119                 hw_stats->qprc[i] += delta_qprc;
3120                 hw_stats->qptc[i] += delta_qptc;
3121
3122                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3123                 hw_stats->qbrc[i] +=
3124                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3125                 if (crc_strip == 0)
3126                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3127
3128                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3129                 hw_stats->qbtc[i] +=
3130                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3131
3132                 hw_stats->qprdc[i] += delta_qprdc;
3133                 *total_qprdc += hw_stats->qprdc[i];
3134
3135                 *total_qprc += hw_stats->qprc[i];
3136                 *total_qbrc += hw_stats->qbrc[i];
3137         }
3138         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3139         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3140         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3141
3142         /*
3143          * An errata states that gprc actually counts good + missed packets:
3144          * Workaround to set gprc to summated queue packet receives
3145          */
3146         hw_stats->gprc = *total_qprc;
3147
3148         if (hw->mac.type != ixgbe_mac_82598EB) {
3149                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3150                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3151                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3152                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3153                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3154                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3155                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3156                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3157         } else {
3158                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3159                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3160                 /* 82598 only has a counter in the high register */
3161                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3162                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3163                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3164         }
3165         uint64_t old_tpr = hw_stats->tpr;
3166
3167         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3168         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3169
3170         if (crc_strip == 0)
3171                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3172
3173         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3174         hw_stats->gptc += delta_gptc;
3175         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3176         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3177
3178         /*
3179          * Workaround: mprc hardware is incorrectly counting
3180          * broadcasts, so for now we subtract those.
3181          */
3182         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3183         hw_stats->bprc += bprc;
3184         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3185         if (hw->mac.type == ixgbe_mac_82598EB)
3186                 hw_stats->mprc -= bprc;
3187
3188         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3189         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3190         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3191         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3192         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3193         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3194
3195         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3196         hw_stats->lxontxc += lxon;
3197         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3198         hw_stats->lxofftxc += lxoff;
3199         total = lxon + lxoff;
3200
3201         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3202         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3203         hw_stats->gptc -= total;
3204         hw_stats->mptc -= total;
3205         hw_stats->ptc64 -= total;
3206         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3207
3208         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3209         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3210         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3211         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3212         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3213         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3214         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3215         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3216         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3217         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3218         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3219         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3220         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3221         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3222         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3223         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3224         /* Only read FCOE on 82599 */
3225         if (hw->mac.type != ixgbe_mac_82598EB) {
3226                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3227                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3228                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3229                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3230                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3231         }
3232
3233         /* Flow Director Stats registers */
3234         if (hw->mac.type != ixgbe_mac_82598EB) {
3235                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3236                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3237                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3238                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3239                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3240                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3241                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3242                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3243                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3244                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3245         }
3246         /* MACsec Stats registers */
3247         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3248         macsec_stats->out_pkts_encrypted +=
3249                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3250         macsec_stats->out_pkts_protected +=
3251                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3252         macsec_stats->out_octets_encrypted +=
3253                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3254         macsec_stats->out_octets_protected +=
3255                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3256         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3257         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3258         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3259         macsec_stats->in_pkts_unknownsci +=
3260                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3261         macsec_stats->in_octets_decrypted +=
3262                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3263         macsec_stats->in_octets_validated +=
3264                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3265         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3266         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3267         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3268         for (i = 0; i < 2; i++) {
3269                 macsec_stats->in_pkts_ok +=
3270                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3271                 macsec_stats->in_pkts_invalid +=
3272                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3273                 macsec_stats->in_pkts_notvalid +=
3274                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3275         }
3276         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3277         macsec_stats->in_pkts_notusingsa +=
3278                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3279 }
3280
3281 /*
3282  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3283  */
3284 static int
3285 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3286 {
3287         struct ixgbe_hw *hw =
3288                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3289         struct ixgbe_hw_stats *hw_stats =
3290                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3291         struct ixgbe_macsec_stats *macsec_stats =
3292                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3293                                 dev->data->dev_private);
3294         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3295         unsigned i;
3296
3297         total_missed_rx = 0;
3298         total_qbrc = 0;
3299         total_qprc = 0;
3300         total_qprdc = 0;
3301
3302         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3303                         &total_qbrc, &total_qprc, &total_qprdc);
3304
3305         if (stats == NULL)
3306                 return -EINVAL;
3307
3308         /* Fill out the rte_eth_stats statistics structure */
3309         stats->ipackets = total_qprc;
3310         stats->ibytes = total_qbrc;
3311         stats->opackets = hw_stats->gptc;
3312         stats->obytes = hw_stats->gotc;
3313
3314         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3315                 stats->q_ipackets[i] = hw_stats->qprc[i];
3316                 stats->q_opackets[i] = hw_stats->qptc[i];
3317                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3318                 stats->q_obytes[i] = hw_stats->qbtc[i];
3319                 stats->q_errors[i] = hw_stats->qprdc[i];
3320         }
3321
3322         /* Rx Errors */
3323         stats->imissed  = total_missed_rx;
3324         stats->ierrors  = hw_stats->crcerrs +
3325                           hw_stats->mspdc +
3326                           hw_stats->rlec +
3327                           hw_stats->ruc +
3328                           hw_stats->roc +
3329                           hw_stats->illerrc +
3330                           hw_stats->errbc +
3331                           hw_stats->rfc +
3332                           hw_stats->fccrc +
3333                           hw_stats->fclast;
3334
3335         /* Tx Errors */
3336         stats->oerrors  = 0;
3337         return 0;
3338 }
3339
3340 static int
3341 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3342 {
3343         struct ixgbe_hw_stats *stats =
3344                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3345
3346         /* HW registers are cleared on read */
3347         ixgbe_dev_stats_get(dev, NULL);
3348
3349         /* Reset software totals */
3350         memset(stats, 0, sizeof(*stats));
3351
3352         return 0;
3353 }
3354
3355 /* This function calculates the number of xstats based on the current config */
3356 static unsigned
3357 ixgbe_xstats_calc_num(void) {
3358         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3359                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3360                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3361 }
3362
3363 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3364         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3365 {
3366         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3367         unsigned stat, i, count;
3368
3369         if (xstats_names != NULL) {
3370                 count = 0;
3371
3372                 /* Note: limit >= cnt_stats checked upstream
3373                  * in rte_eth_xstats_names()
3374                  */
3375
3376                 /* Extended stats from ixgbe_hw_stats */
3377                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3378                         strlcpy(xstats_names[count].name,
3379                                 rte_ixgbe_stats_strings[i].name,
3380                                 sizeof(xstats_names[count].name));
3381                         count++;
3382                 }
3383
3384                 /* MACsec Stats */
3385                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3386                         strlcpy(xstats_names[count].name,
3387                                 rte_ixgbe_macsec_strings[i].name,
3388                                 sizeof(xstats_names[count].name));
3389                         count++;
3390                 }
3391
3392                 /* RX Priority Stats */
3393                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3394                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3395                                 snprintf(xstats_names[count].name,
3396                                         sizeof(xstats_names[count].name),
3397                                         "rx_priority%u_%s", i,
3398                                         rte_ixgbe_rxq_strings[stat].name);
3399                                 count++;
3400                         }
3401                 }
3402
3403                 /* TX Priority Stats */
3404                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3405                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3406                                 snprintf(xstats_names[count].name,
3407                                         sizeof(xstats_names[count].name),
3408                                         "tx_priority%u_%s", i,
3409                                         rte_ixgbe_txq_strings[stat].name);
3410                                 count++;
3411                         }
3412                 }
3413         }
3414         return cnt_stats;
3415 }
3416
3417 static int ixgbe_dev_xstats_get_names_by_id(
3418         struct rte_eth_dev *dev,
3419         struct rte_eth_xstat_name *xstats_names,
3420         const uint64_t *ids,
3421         unsigned int limit)
3422 {
3423         if (!ids) {
3424                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3425                 unsigned int stat, i, count;
3426
3427                 if (xstats_names != NULL) {
3428                         count = 0;
3429
3430                         /* Note: limit >= cnt_stats checked upstream
3431                          * in rte_eth_xstats_names()
3432                          */
3433
3434                         /* Extended stats from ixgbe_hw_stats */
3435                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3436                                 strlcpy(xstats_names[count].name,
3437                                         rte_ixgbe_stats_strings[i].name,
3438                                         sizeof(xstats_names[count].name));
3439                                 count++;
3440                         }
3441
3442                         /* MACsec Stats */
3443                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3444                                 strlcpy(xstats_names[count].name,
3445                                         rte_ixgbe_macsec_strings[i].name,
3446                                         sizeof(xstats_names[count].name));
3447                                 count++;
3448                         }
3449
3450                         /* RX Priority Stats */
3451                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3452                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3453                                         snprintf(xstats_names[count].name,
3454                                             sizeof(xstats_names[count].name),
3455                                             "rx_priority%u_%s", i,
3456                                             rte_ixgbe_rxq_strings[stat].name);
3457                                         count++;
3458                                 }
3459                         }
3460
3461                         /* TX Priority Stats */
3462                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3463                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3464                                         snprintf(xstats_names[count].name,
3465                                             sizeof(xstats_names[count].name),
3466                                             "tx_priority%u_%s", i,
3467                                             rte_ixgbe_txq_strings[stat].name);
3468                                         count++;
3469                                 }
3470                         }
3471                 }
3472                 return cnt_stats;
3473         }
3474
3475         uint16_t i;
3476         uint16_t size = ixgbe_xstats_calc_num();
3477         struct rte_eth_xstat_name xstats_names_copy[size];
3478
3479         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3480                         size);
3481
3482         for (i = 0; i < limit; i++) {
3483                 if (ids[i] >= size) {
3484                         PMD_INIT_LOG(ERR, "id value isn't valid");
3485                         return -1;
3486                 }
3487                 strcpy(xstats_names[i].name,
3488                                 xstats_names_copy[ids[i]].name);
3489         }
3490         return limit;
3491 }
3492
3493 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3494         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3495 {
3496         unsigned i;
3497
3498         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3499                 return -ENOMEM;
3500
3501         if (xstats_names != NULL)
3502                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3503                         strlcpy(xstats_names[i].name,
3504                                 rte_ixgbevf_stats_strings[i].name,
3505                                 sizeof(xstats_names[i].name));
3506         return IXGBEVF_NB_XSTATS;
3507 }
3508
3509 static int
3510 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3511                                          unsigned n)
3512 {
3513         struct ixgbe_hw *hw =
3514                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3515         struct ixgbe_hw_stats *hw_stats =
3516                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3517         struct ixgbe_macsec_stats *macsec_stats =
3518                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3519                                 dev->data->dev_private);
3520         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3521         unsigned i, stat, count = 0;
3522
3523         count = ixgbe_xstats_calc_num();
3524
3525         if (n < count)
3526                 return count;
3527
3528         total_missed_rx = 0;
3529         total_qbrc = 0;
3530         total_qprc = 0;
3531         total_qprdc = 0;
3532
3533         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3534                         &total_qbrc, &total_qprc, &total_qprdc);
3535
3536         /* If this is a reset xstats is NULL, and we have cleared the
3537          * registers by reading them.
3538          */
3539         if (!xstats)
3540                 return 0;
3541
3542         /* Extended stats from ixgbe_hw_stats */
3543         count = 0;
3544         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3545                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3546                                 rte_ixgbe_stats_strings[i].offset);
3547                 xstats[count].id = count;
3548                 count++;
3549         }
3550
3551         /* MACsec Stats */
3552         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3553                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3554                                 rte_ixgbe_macsec_strings[i].offset);
3555                 xstats[count].id = count;
3556                 count++;
3557         }
3558
3559         /* RX Priority Stats */
3560         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3561                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3562                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3563                                         rte_ixgbe_rxq_strings[stat].offset +
3564                                         (sizeof(uint64_t) * i));
3565                         xstats[count].id = count;
3566                         count++;
3567                 }
3568         }
3569
3570         /* TX Priority Stats */
3571         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3572                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3573                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3574                                         rte_ixgbe_txq_strings[stat].offset +
3575                                         (sizeof(uint64_t) * i));
3576                         xstats[count].id = count;
3577                         count++;
3578                 }
3579         }
3580         return count;
3581 }
3582
3583 static int
3584 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3585                 uint64_t *values, unsigned int n)
3586 {
3587         if (!ids) {
3588                 struct ixgbe_hw *hw =
3589                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3590                 struct ixgbe_hw_stats *hw_stats =
3591                                 IXGBE_DEV_PRIVATE_TO_STATS(
3592                                                 dev->data->dev_private);
3593                 struct ixgbe_macsec_stats *macsec_stats =
3594                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3595                                         dev->data->dev_private);
3596                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3597                 unsigned int i, stat, count = 0;
3598
3599                 count = ixgbe_xstats_calc_num();
3600
3601                 if (!ids && n < count)
3602                         return count;
3603
3604                 total_missed_rx = 0;
3605                 total_qbrc = 0;
3606                 total_qprc = 0;
3607                 total_qprdc = 0;
3608
3609                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3610                                 &total_missed_rx, &total_qbrc, &total_qprc,
3611                                 &total_qprdc);
3612
3613                 /* If this is a reset xstats is NULL, and we have cleared the
3614                  * registers by reading them.
3615                  */
3616                 if (!ids && !values)
3617                         return 0;
3618
3619                 /* Extended stats from ixgbe_hw_stats */
3620                 count = 0;
3621                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3622                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3623                                         rte_ixgbe_stats_strings[i].offset);
3624                         count++;
3625                 }
3626
3627                 /* MACsec Stats */
3628                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3629                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3630                                         rte_ixgbe_macsec_strings[i].offset);
3631                         count++;
3632                 }
3633
3634                 /* RX Priority Stats */
3635                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3636                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3637                                 values[count] =
3638                                         *(uint64_t *)(((char *)hw_stats) +
3639                                         rte_ixgbe_rxq_strings[stat].offset +
3640                                         (sizeof(uint64_t) * i));
3641                                 count++;
3642                         }
3643                 }
3644
3645                 /* TX Priority Stats */
3646                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3647                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3648                                 values[count] =
3649                                         *(uint64_t *)(((char *)hw_stats) +
3650                                         rte_ixgbe_txq_strings[stat].offset +
3651                                         (sizeof(uint64_t) * i));
3652                                 count++;
3653                         }
3654                 }
3655                 return count;
3656         }
3657
3658         uint16_t i;
3659         uint16_t size = ixgbe_xstats_calc_num();
3660         uint64_t values_copy[size];
3661
3662         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3663
3664         for (i = 0; i < n; i++) {
3665                 if (ids[i] >= size) {
3666                         PMD_INIT_LOG(ERR, "id value isn't valid");
3667                         return -1;
3668                 }
3669                 values[i] = values_copy[ids[i]];
3670         }
3671         return n;
3672 }
3673
3674 static int
3675 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3676 {
3677         struct ixgbe_hw_stats *stats =
3678                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3679         struct ixgbe_macsec_stats *macsec_stats =
3680                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3681                                 dev->data->dev_private);
3682
3683         unsigned count = ixgbe_xstats_calc_num();
3684
3685         /* HW registers are cleared on read */
3686         ixgbe_dev_xstats_get(dev, NULL, count);
3687
3688         /* Reset software totals */
3689         memset(stats, 0, sizeof(*stats));
3690         memset(macsec_stats, 0, sizeof(*macsec_stats));
3691
3692         return 0;
3693 }
3694
3695 static void
3696 ixgbevf_update_stats(struct rte_eth_dev *dev)
3697 {
3698         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3699         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3700                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3701
3702         /* Good Rx packet, include VF loopback */
3703         UPDATE_VF_STAT(IXGBE_VFGPRC,
3704             hw_stats->last_vfgprc, hw_stats->vfgprc);
3705
3706         /* Good Rx octets, include VF loopback */
3707         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3708             hw_stats->last_vfgorc, hw_stats->vfgorc);
3709
3710         /* Good Tx packet, include VF loopback */
3711         UPDATE_VF_STAT(IXGBE_VFGPTC,
3712             hw_stats->last_vfgptc, hw_stats->vfgptc);
3713
3714         /* Good Tx octets, include VF loopback */
3715         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3716             hw_stats->last_vfgotc, hw_stats->vfgotc);
3717
3718         /* Rx Multicst Packet */
3719         UPDATE_VF_STAT(IXGBE_VFMPRC,
3720             hw_stats->last_vfmprc, hw_stats->vfmprc);
3721 }
3722
3723 static int
3724 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3725                        unsigned n)
3726 {
3727         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3728                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3729         unsigned i;
3730
3731         if (n < IXGBEVF_NB_XSTATS)
3732                 return IXGBEVF_NB_XSTATS;
3733
3734         ixgbevf_update_stats(dev);
3735
3736         if (!xstats)
3737                 return 0;
3738
3739         /* Extended stats */
3740         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3741                 xstats[i].id = i;
3742                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3743                         rte_ixgbevf_stats_strings[i].offset);
3744         }
3745
3746         return IXGBEVF_NB_XSTATS;
3747 }
3748
3749 static int
3750 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3751 {
3752         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3753                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3754
3755         ixgbevf_update_stats(dev);
3756
3757         if (stats == NULL)
3758                 return -EINVAL;
3759
3760         stats->ipackets = hw_stats->vfgprc;
3761         stats->ibytes = hw_stats->vfgorc;
3762         stats->opackets = hw_stats->vfgptc;
3763         stats->obytes = hw_stats->vfgotc;
3764         return 0;
3765 }
3766
3767 static int
3768 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3769 {
3770         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3771                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3772
3773         /* Sync HW register to the last stats */
3774         ixgbevf_dev_stats_get(dev, NULL);
3775
3776         /* reset HW current stats*/
3777         hw_stats->vfgprc = 0;
3778         hw_stats->vfgorc = 0;
3779         hw_stats->vfgptc = 0;
3780         hw_stats->vfgotc = 0;
3781
3782         return 0;
3783 }
3784
3785 static int
3786 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3787 {
3788         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3789         u16 eeprom_verh, eeprom_verl;
3790         u32 etrack_id;
3791         int ret;
3792
3793         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3794         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3795
3796         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3797         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3798
3799         ret += 1; /* add the size of '\0' */
3800         if (fw_size < (u32)ret)
3801                 return ret;
3802         else
3803                 return 0;
3804 }
3805
3806 static int
3807 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3808 {
3809         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3810         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3811         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3812
3813         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3814         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3815         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3816                 /*
3817                  * When DCB/VT is off, maximum number of queues changes,
3818                  * except for 82598EB, which remains constant.
3819                  */
3820                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3821                                 hw->mac.type != ixgbe_mac_82598EB)
3822                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3823         }
3824         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3825         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3826         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3827         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3828         dev_info->max_vfs = pci_dev->max_vfs;
3829         if (hw->mac.type == ixgbe_mac_82598EB)
3830                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3831         else
3832                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3833         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3834         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3835         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3836         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3837         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3838                                      dev_info->rx_queue_offload_capa);
3839         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3840         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3841
3842         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3843                 .rx_thresh = {
3844                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3845                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3846                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3847                 },
3848                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3849                 .rx_drop_en = 0,
3850                 .offloads = 0,
3851         };
3852
3853         dev_info->default_txconf = (struct rte_eth_txconf) {
3854                 .tx_thresh = {
3855                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3856                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3857                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3858                 },
3859                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3860                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3861                 .offloads = 0,
3862         };
3863
3864         dev_info->rx_desc_lim = rx_desc_lim;
3865         dev_info->tx_desc_lim = tx_desc_lim;
3866
3867         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3868         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3869         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3870
3871         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3872         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3873                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3874                 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3875                         ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3876
3877         if (hw->mac.type == ixgbe_mac_X540 ||
3878             hw->mac.type == ixgbe_mac_X540_vf ||
3879             hw->mac.type == ixgbe_mac_X550 ||
3880             hw->mac.type == ixgbe_mac_X550_vf) {
3881                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3882         }
3883         if (hw->mac.type == ixgbe_mac_X550) {
3884                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3885                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3886         }
3887
3888         /* Driver-preferred Rx/Tx parameters */
3889         dev_info->default_rxportconf.burst_size = 32;
3890         dev_info->default_txportconf.burst_size = 32;
3891         dev_info->default_rxportconf.nb_queues = 1;
3892         dev_info->default_txportconf.nb_queues = 1;
3893         dev_info->default_rxportconf.ring_size = 256;
3894         dev_info->default_txportconf.ring_size = 256;
3895
3896         return 0;
3897 }
3898
3899 static const uint32_t *
3900 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3901 {
3902         static const uint32_t ptypes[] = {
3903                 /* For non-vec functions,
3904                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3905                  * for vec functions,
3906                  * refers to _recv_raw_pkts_vec().
3907                  */
3908                 RTE_PTYPE_L2_ETHER,
3909                 RTE_PTYPE_L3_IPV4,
3910                 RTE_PTYPE_L3_IPV4_EXT,
3911                 RTE_PTYPE_L3_IPV6,
3912                 RTE_PTYPE_L3_IPV6_EXT,
3913                 RTE_PTYPE_L4_SCTP,
3914                 RTE_PTYPE_L4_TCP,
3915                 RTE_PTYPE_L4_UDP,
3916                 RTE_PTYPE_TUNNEL_IP,
3917                 RTE_PTYPE_INNER_L3_IPV6,
3918                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3919                 RTE_PTYPE_INNER_L4_TCP,
3920                 RTE_PTYPE_INNER_L4_UDP,
3921                 RTE_PTYPE_UNKNOWN
3922         };
3923
3924         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3925             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3926             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3927             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3928                 return ptypes;
3929
3930 #if defined(RTE_ARCH_X86) || defined(RTE_MACHINE_CPUFLAG_NEON)
3931         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3932             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3933                 return ptypes;
3934 #endif
3935         return NULL;
3936 }
3937
3938 static int
3939 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3940                      struct rte_eth_dev_info *dev_info)
3941 {
3942         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3943         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3944
3945         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3946         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3947         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3948         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3949         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3950         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3951         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3952         dev_info->max_vfs = pci_dev->max_vfs;
3953         if (hw->mac.type == ixgbe_mac_82598EB)
3954                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3955         else
3956                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3957         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3958         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3959                                      dev_info->rx_queue_offload_capa);
3960         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3961         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3962         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3963         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3964         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3965
3966         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3967                 .rx_thresh = {
3968                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3969                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3970                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3971                 },
3972                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3973                 .rx_drop_en = 0,
3974                 .offloads = 0,
3975         };
3976
3977         dev_info->default_txconf = (struct rte_eth_txconf) {
3978                 .tx_thresh = {
3979                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3980                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3981                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3982                 },
3983                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3984                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3985                 .offloads = 0,
3986         };
3987
3988         dev_info->rx_desc_lim = rx_desc_lim;
3989         dev_info->tx_desc_lim = tx_desc_lim;
3990
3991         return 0;
3992 }
3993
3994 static int
3995 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3996                    bool *link_up, int wait_to_complete)
3997 {
3998         struct ixgbe_adapter *adapter = container_of(hw,
3999                                                      struct ixgbe_adapter, hw);
4000         struct ixgbe_mbx_info *mbx = &hw->mbx;
4001         struct ixgbe_mac_info *mac = &hw->mac;
4002         uint32_t links_reg, in_msg;
4003         int ret_val = 0;
4004
4005         /* If we were hit with a reset drop the link */
4006         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4007                 mac->get_link_status = true;
4008
4009         if (!mac->get_link_status)
4010                 goto out;
4011
4012         /* if link status is down no point in checking to see if pf is up */
4013         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4014         if (!(links_reg & IXGBE_LINKS_UP))
4015                 goto out;
4016
4017         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4018          * before the link status is correct
4019          */
4020         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4021                 int i;
4022
4023                 for (i = 0; i < 5; i++) {
4024                         rte_delay_us(100);
4025                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4026
4027                         if (!(links_reg & IXGBE_LINKS_UP))
4028                                 goto out;
4029                 }
4030         }
4031
4032         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4033         case IXGBE_LINKS_SPEED_10G_82599:
4034                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4035                 if (hw->mac.type >= ixgbe_mac_X550) {
4036                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4037                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4038                 }
4039                 break;
4040         case IXGBE_LINKS_SPEED_1G_82599:
4041                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4042                 break;
4043         case IXGBE_LINKS_SPEED_100_82599:
4044                 *speed = IXGBE_LINK_SPEED_100_FULL;
4045                 if (hw->mac.type == ixgbe_mac_X550) {
4046                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4047                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4048                 }
4049                 break;
4050         case IXGBE_LINKS_SPEED_10_X550EM_A:
4051                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4052                 /* Since Reserved in older MAC's */
4053                 if (hw->mac.type >= ixgbe_mac_X550)
4054                         *speed = IXGBE_LINK_SPEED_10_FULL;
4055                 break;
4056         default:
4057                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4058         }
4059
4060         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4061                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4062                         mac->get_link_status = true;
4063                 else
4064                         mac->get_link_status = false;
4065
4066                 goto out;
4067         }
4068
4069         /* if the read failed it could just be a mailbox collision, best wait
4070          * until we are called again and don't report an error
4071          */
4072         if (mbx->ops.read(hw, &in_msg, 1, 0))
4073                 goto out;
4074
4075         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4076                 /* msg is not CTS and is NACK we must have lost CTS status */
4077                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4078                         mac->get_link_status = false;
4079                 goto out;
4080         }
4081
4082         /* the pf is talking, if we timed out in the past we reinit */
4083         if (!mbx->timeout) {
4084                 ret_val = -1;
4085                 goto out;
4086         }
4087
4088         /* if we passed all the tests above then the link is up and we no
4089          * longer need to check for link
4090          */
4091         mac->get_link_status = false;
4092
4093 out:
4094         *link_up = !mac->get_link_status;
4095         return ret_val;
4096 }
4097
4098 static void
4099 ixgbe_dev_setup_link_alarm_handler(void *param)
4100 {
4101         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4102         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4103         struct ixgbe_interrupt *intr =
4104                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4105         u32 speed;
4106         bool autoneg = false;
4107
4108         speed = hw->phy.autoneg_advertised;
4109         if (!speed)
4110                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4111
4112         ixgbe_setup_link(hw, speed, true);
4113
4114         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4115 }
4116
4117 /*
4118  * In freebsd environment, nic_uio drivers do not support interrupts,
4119  * rte_intr_callback_register() will fail to register interrupts.
4120  * We can not make link status to change from down to up by interrupt
4121  * callback. So we need to wait for the controller to acquire link
4122  * when ports start.
4123  * It returns 0 on link up.
4124  */
4125 static int
4126 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4127 {
4128 #ifdef RTE_EXEC_ENV_FREEBSD
4129         const int nb_iter = 25;
4130 #else
4131         const int nb_iter = 0;
4132 #endif
4133         int err, i;
4134         bool link_up = false;
4135         uint32_t speed = 0;
4136
4137         for (i = 0; i < nb_iter; i++) {
4138                 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4139                 if (err)
4140                         return err;
4141                 if (link_up)
4142                         return 0;
4143                 msec_delay(200);
4144         }
4145         return 0;
4146 }
4147
4148 /* return 0 means link status changed, -1 means not changed */
4149 int
4150 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4151                             int wait_to_complete, int vf)
4152 {
4153         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4154         struct rte_eth_link link;
4155         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4156         struct ixgbe_interrupt *intr =
4157                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4158         bool link_up;
4159         int diag;
4160         int wait = 1;
4161         u32 esdp_reg;
4162
4163         memset(&link, 0, sizeof(link));
4164         link.link_status = ETH_LINK_DOWN;
4165         link.link_speed = ETH_SPEED_NUM_NONE;
4166         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4167         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4168                         ETH_LINK_SPEED_FIXED);
4169
4170         hw->mac.get_link_status = true;
4171
4172         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4173                 return rte_eth_linkstatus_set(dev, &link);
4174
4175         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4176         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4177                 wait = 0;
4178
4179         if (vf)
4180                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4181         else
4182                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4183
4184         if (diag != 0) {
4185                 link.link_speed = ETH_SPEED_NUM_100M;
4186                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4187                 return rte_eth_linkstatus_set(dev, &link);
4188         }
4189
4190         if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4191                 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4192                 if ((esdp_reg & IXGBE_ESDP_SDP3))
4193                         link_up = 0;
4194         }
4195
4196         if (link_up == 0) {
4197                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4198                         intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4199                         rte_eal_alarm_set(10,
4200                                 ixgbe_dev_setup_link_alarm_handler, dev);
4201                 }
4202                 return rte_eth_linkstatus_set(dev, &link);
4203         }
4204
4205         link.link_status = ETH_LINK_UP;
4206         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4207
4208         switch (link_speed) {
4209         default:
4210         case IXGBE_LINK_SPEED_UNKNOWN:
4211                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4212                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4213                         link.link_speed = ETH_SPEED_NUM_10M;
4214                 else
4215                         link.link_speed = ETH_SPEED_NUM_100M;
4216                 break;
4217
4218         case IXGBE_LINK_SPEED_100_FULL:
4219                 link.link_speed = ETH_SPEED_NUM_100M;
4220                 break;
4221
4222         case IXGBE_LINK_SPEED_1GB_FULL:
4223                 link.link_speed = ETH_SPEED_NUM_1G;
4224                 break;
4225
4226         case IXGBE_LINK_SPEED_2_5GB_FULL:
4227                 link.link_speed = ETH_SPEED_NUM_2_5G;
4228                 break;
4229
4230         case IXGBE_LINK_SPEED_5GB_FULL:
4231                 link.link_speed = ETH_SPEED_NUM_5G;
4232                 break;
4233
4234         case IXGBE_LINK_SPEED_10GB_FULL:
4235                 link.link_speed = ETH_SPEED_NUM_10G;
4236                 break;
4237         }
4238
4239         return rte_eth_linkstatus_set(dev, &link);
4240 }
4241
4242 static int
4243 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4244 {
4245         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4246 }
4247
4248 static int
4249 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4250 {
4251         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4252 }
4253
4254 static int
4255 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4256 {
4257         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4258         uint32_t fctrl;
4259
4260         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4261         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4262         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4263
4264         return 0;
4265 }
4266
4267 static int
4268 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4269 {
4270         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4271         uint32_t fctrl;
4272
4273         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4274         fctrl &= (~IXGBE_FCTRL_UPE);
4275         if (dev->data->all_multicast == 1)
4276                 fctrl |= IXGBE_FCTRL_MPE;
4277         else
4278                 fctrl &= (~IXGBE_FCTRL_MPE);
4279         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4280
4281         return 0;
4282 }
4283
4284 static int
4285 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4286 {
4287         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4288         uint32_t fctrl;
4289
4290         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4291         fctrl |= IXGBE_FCTRL_MPE;
4292         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4293
4294         return 0;
4295 }
4296
4297 static int
4298 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4299 {
4300         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4301         uint32_t fctrl;
4302
4303         if (dev->data->promiscuous == 1)
4304                 return 0; /* must remain in all_multicast mode */
4305
4306         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4307         fctrl &= (~IXGBE_FCTRL_MPE);
4308         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4309
4310         return 0;
4311 }
4312
4313 /**
4314  * It clears the interrupt causes and enables the interrupt.
4315  * It will be called once only during nic initialized.
4316  *
4317  * @param dev
4318  *  Pointer to struct rte_eth_dev.
4319  * @param on
4320  *  Enable or Disable.
4321  *
4322  * @return
4323  *  - On success, zero.
4324  *  - On failure, a negative value.
4325  */
4326 static int
4327 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4328 {
4329         struct ixgbe_interrupt *intr =
4330                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4331
4332         ixgbe_dev_link_status_print(dev);
4333         if (on)
4334                 intr->mask |= IXGBE_EICR_LSC;
4335         else
4336                 intr->mask &= ~IXGBE_EICR_LSC;
4337
4338         return 0;
4339 }
4340
4341 /**
4342  * It clears the interrupt causes and enables the interrupt.
4343  * It will be called once only during nic initialized.
4344  *
4345  * @param dev
4346  *  Pointer to struct rte_eth_dev.
4347  *
4348  * @return
4349  *  - On success, zero.
4350  *  - On failure, a negative value.
4351  */
4352 static int
4353 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4354 {
4355         struct ixgbe_interrupt *intr =
4356                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4357
4358         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4359
4360         return 0;
4361 }
4362
4363 /**
4364  * It clears the interrupt causes and enables the interrupt.
4365  * It will be called once only during nic initialized.
4366  *
4367  * @param dev
4368  *  Pointer to struct rte_eth_dev.
4369  *
4370  * @return
4371  *  - On success, zero.
4372  *  - On failure, a negative value.
4373  */
4374 static int
4375 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4376 {
4377         struct ixgbe_interrupt *intr =
4378                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4379
4380         intr->mask |= IXGBE_EICR_LINKSEC;
4381
4382         return 0;
4383 }
4384
4385 /*
4386  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4387  *
4388  * @param dev
4389  *  Pointer to struct rte_eth_dev.
4390  *
4391  * @return
4392  *  - On success, zero.
4393  *  - On failure, a negative value.
4394  */
4395 static int
4396 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4397 {
4398         uint32_t eicr;
4399         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4400         struct ixgbe_interrupt *intr =
4401                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4402
4403         /* clear all cause mask */
4404         ixgbe_disable_intr(hw);
4405
4406         /* read-on-clear nic registers here */
4407         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4408         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4409
4410         intr->flags = 0;
4411
4412         /* set flag for async link update */
4413         if (eicr & IXGBE_EICR_LSC)
4414                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4415
4416         if (eicr & IXGBE_EICR_MAILBOX)
4417                 intr->flags |= IXGBE_FLAG_MAILBOX;
4418
4419         if (eicr & IXGBE_EICR_LINKSEC)
4420                 intr->flags |= IXGBE_FLAG_MACSEC;
4421
4422         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4423             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4424             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4425                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4426
4427         return 0;
4428 }
4429
4430 /**
4431  * It gets and then prints the link status.
4432  *
4433  * @param dev
4434  *  Pointer to struct rte_eth_dev.
4435  *
4436  * @return
4437  *  - On success, zero.
4438  *  - On failure, a negative value.
4439  */
4440 static void
4441 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4442 {
4443         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4444         struct rte_eth_link link;
4445
4446         rte_eth_linkstatus_get(dev, &link);
4447
4448         if (link.link_status) {
4449                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4450                                         (int)(dev->data->port_id),
4451                                         (unsigned)link.link_speed,
4452                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4453                                         "full-duplex" : "half-duplex");
4454         } else {
4455                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4456                                 (int)(dev->data->port_id));
4457         }
4458         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4459                                 pci_dev->addr.domain,
4460                                 pci_dev->addr.bus,
4461                                 pci_dev->addr.devid,
4462                                 pci_dev->addr.function);
4463 }
4464
4465 /*
4466  * It executes link_update after knowing an interrupt occurred.
4467  *
4468  * @param dev
4469  *  Pointer to struct rte_eth_dev.
4470  *
4471  * @return
4472  *  - On success, zero.
4473  *  - On failure, a negative value.
4474  */
4475 static int
4476 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4477 {
4478         struct ixgbe_interrupt *intr =
4479                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4480         int64_t timeout;
4481         struct ixgbe_hw *hw =
4482                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4483
4484         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4485
4486         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4487                 ixgbe_pf_mbx_process(dev);
4488                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4489         }
4490
4491         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4492                 ixgbe_handle_lasi(hw);
4493                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4494         }
4495
4496         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4497                 struct rte_eth_link link;
4498
4499                 /* get the link status before link update, for predicting later */
4500                 rte_eth_linkstatus_get(dev, &link);
4501
4502                 ixgbe_dev_link_update(dev, 0);
4503
4504                 /* likely to up */
4505                 if (!link.link_status)
4506                         /* handle it 1 sec later, wait it being stable */
4507                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4508                 /* likely to down */
4509                 else
4510                         /* handle it 4 sec later, wait it being stable */
4511                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4512
4513                 ixgbe_dev_link_status_print(dev);
4514                 if (rte_eal_alarm_set(timeout * 1000,
4515                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4516                         PMD_DRV_LOG(ERR, "Error setting alarm");
4517                 else {
4518                         /* remember original mask */
4519                         intr->mask_original = intr->mask;
4520                         /* only disable lsc interrupt */
4521                         intr->mask &= ~IXGBE_EIMS_LSC;
4522                 }
4523         }
4524
4525         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4526         ixgbe_enable_intr(dev);
4527
4528         return 0;
4529 }
4530
4531 /**
4532  * Interrupt handler which shall be registered for alarm callback for delayed
4533  * handling specific interrupt to wait for the stable nic state. As the
4534  * NIC interrupt state is not stable for ixgbe after link is just down,
4535  * it needs to wait 4 seconds to get the stable status.
4536  *
4537  * @param handle
4538  *  Pointer to interrupt handle.
4539  * @param param
4540  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4541  *
4542  * @return
4543  *  void
4544  */
4545 static void
4546 ixgbe_dev_interrupt_delayed_handler(void *param)
4547 {
4548         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4549         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4550         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4551         struct ixgbe_interrupt *intr =
4552                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4553         struct ixgbe_hw *hw =
4554                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4555         uint32_t eicr;
4556
4557         ixgbe_disable_intr(hw);
4558
4559         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4560         if (eicr & IXGBE_EICR_MAILBOX)
4561                 ixgbe_pf_mbx_process(dev);
4562
4563         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4564                 ixgbe_handle_lasi(hw);
4565                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4566         }
4567
4568         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4569                 ixgbe_dev_link_update(dev, 0);
4570                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4571                 ixgbe_dev_link_status_print(dev);
4572                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4573                                               NULL);
4574         }
4575
4576         if (intr->flags & IXGBE_FLAG_MACSEC) {
4577                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4578                                               NULL);
4579                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4580         }
4581
4582         /* restore original mask */
4583         intr->mask = intr->mask_original;
4584         intr->mask_original = 0;
4585
4586         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4587         ixgbe_enable_intr(dev);
4588         rte_intr_ack(intr_handle);
4589 }
4590
4591 /**
4592  * Interrupt handler triggered by NIC  for handling
4593  * specific interrupt.
4594  *
4595  * @param handle
4596  *  Pointer to interrupt handle.
4597  * @param param
4598  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4599  *
4600  * @return
4601  *  void
4602  */
4603 static void
4604 ixgbe_dev_interrupt_handler(void *param)
4605 {
4606         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4607
4608         ixgbe_dev_interrupt_get_status(dev);
4609         ixgbe_dev_interrupt_action(dev);
4610 }
4611
4612 static int
4613 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4614 {
4615         struct ixgbe_hw *hw;
4616
4617         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4618         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4619 }
4620
4621 static int
4622 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4623 {
4624         struct ixgbe_hw *hw;
4625
4626         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4627         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4628 }
4629
4630 static int
4631 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4632 {
4633         struct ixgbe_hw *hw;
4634         uint32_t mflcn_reg;
4635         uint32_t fccfg_reg;
4636         int rx_pause;
4637         int tx_pause;
4638
4639         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4640
4641         fc_conf->pause_time = hw->fc.pause_time;
4642         fc_conf->high_water = hw->fc.high_water[0];
4643         fc_conf->low_water = hw->fc.low_water[0];
4644         fc_conf->send_xon = hw->fc.send_xon;
4645         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4646
4647         /*
4648          * Return rx_pause status according to actual setting of
4649          * MFLCN register.
4650          */
4651         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4652         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4653                 rx_pause = 1;
4654         else
4655                 rx_pause = 0;
4656
4657         /*
4658          * Return tx_pause status according to actual setting of
4659          * FCCFG register.
4660          */
4661         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4662         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4663                 tx_pause = 1;
4664         else
4665                 tx_pause = 0;
4666
4667         if (rx_pause && tx_pause)
4668                 fc_conf->mode = RTE_FC_FULL;
4669         else if (rx_pause)
4670                 fc_conf->mode = RTE_FC_RX_PAUSE;
4671         else if (tx_pause)
4672                 fc_conf->mode = RTE_FC_TX_PAUSE;
4673         else
4674                 fc_conf->mode = RTE_FC_NONE;
4675
4676         return 0;
4677 }
4678
4679 static int
4680 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4681 {
4682         struct ixgbe_hw *hw;
4683         int err;
4684         uint32_t rx_buf_size;
4685         uint32_t max_high_water;
4686         uint32_t mflcn;
4687         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4688                 ixgbe_fc_none,
4689                 ixgbe_fc_rx_pause,
4690                 ixgbe_fc_tx_pause,
4691                 ixgbe_fc_full
4692         };
4693
4694         PMD_INIT_FUNC_TRACE();
4695
4696         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4697         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4698         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4699
4700         /*
4701          * At least reserve one Ethernet frame for watermark
4702          * high_water/low_water in kilo bytes for ixgbe
4703          */
4704         max_high_water = (rx_buf_size -
4705                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4706         if ((fc_conf->high_water > max_high_water) ||
4707                 (fc_conf->high_water < fc_conf->low_water)) {
4708                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4709                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4710                 return -EINVAL;
4711         }
4712
4713         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4714         hw->fc.pause_time     = fc_conf->pause_time;
4715         hw->fc.high_water[0]  = fc_conf->high_water;
4716         hw->fc.low_water[0]   = fc_conf->low_water;
4717         hw->fc.send_xon       = fc_conf->send_xon;
4718         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4719
4720         err = ixgbe_fc_enable(hw);
4721
4722         /* Not negotiated is not an error case */
4723         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4724
4725                 /* check if we want to forward MAC frames - driver doesn't have native
4726                  * capability to do that, so we'll write the registers ourselves */
4727
4728                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4729
4730                 /* set or clear MFLCN.PMCF bit depending on configuration */
4731                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4732                         mflcn |= IXGBE_MFLCN_PMCF;
4733                 else
4734                         mflcn &= ~IXGBE_MFLCN_PMCF;
4735
4736                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4737                 IXGBE_WRITE_FLUSH(hw);
4738
4739                 return 0;
4740         }
4741
4742         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4743         return -EIO;
4744 }
4745
4746 /**
4747  *  ixgbe_pfc_enable_generic - Enable flow control
4748  *  @hw: pointer to hardware structure
4749  *  @tc_num: traffic class number
4750  *  Enable flow control according to the current settings.
4751  */
4752 static int
4753 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4754 {
4755         int ret_val = 0;
4756         uint32_t mflcn_reg, fccfg_reg;
4757         uint32_t reg;
4758         uint32_t fcrtl, fcrth;
4759         uint8_t i;
4760         uint8_t nb_rx_en;
4761
4762         /* Validate the water mark configuration */
4763         if (!hw->fc.pause_time) {
4764                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4765                 goto out;
4766         }
4767
4768         /* Low water mark of zero causes XOFF floods */
4769         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4770                  /* High/Low water can not be 0 */
4771                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4772                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4773                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4774                         goto out;
4775                 }
4776
4777                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4778                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4779                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4780                         goto out;
4781                 }
4782         }
4783         /* Negotiate the fc mode to use */
4784         ixgbe_fc_autoneg(hw);
4785
4786         /* Disable any previous flow control settings */
4787         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4788         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4789
4790         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4791         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4792
4793         switch (hw->fc.current_mode) {
4794         case ixgbe_fc_none:
4795                 /*
4796                  * If the count of enabled RX Priority Flow control >1,
4797                  * and the TX pause can not be disabled
4798                  */
4799                 nb_rx_en = 0;
4800                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4801                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4802                         if (reg & IXGBE_FCRTH_FCEN)
4803                                 nb_rx_en++;
4804                 }
4805                 if (nb_rx_en > 1)
4806                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4807                 break;
4808         case ixgbe_fc_rx_pause:
4809                 /*
4810                  * Rx Flow control is enabled and Tx Flow control is
4811                  * disabled by software override. Since there really
4812                  * isn't a way to advertise that we are capable of RX
4813                  * Pause ONLY, we will advertise that we support both
4814                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4815                  * disable the adapter's ability to send PAUSE frames.
4816                  */
4817                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4818                 /*
4819                  * If the count of enabled RX Priority Flow control >1,
4820                  * and the TX pause can not be disabled
4821                  */
4822                 nb_rx_en = 0;
4823                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4824                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4825                         if (reg & IXGBE_FCRTH_FCEN)
4826                                 nb_rx_en++;
4827                 }
4828                 if (nb_rx_en > 1)
4829                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4830                 break;
4831         case ixgbe_fc_tx_pause:
4832                 /*
4833                  * Tx Flow control is enabled, and Rx Flow control is
4834                  * disabled by software override.
4835                  */
4836                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4837                 break;
4838         case ixgbe_fc_full:
4839                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4840                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4841                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4842                 break;
4843         default:
4844                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4845                 ret_val = IXGBE_ERR_CONFIG;
4846                 goto out;
4847         }
4848
4849         /* Set 802.3x based flow control settings. */
4850         mflcn_reg |= IXGBE_MFLCN_DPF;
4851         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4852         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4853
4854         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4855         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4856                 hw->fc.high_water[tc_num]) {
4857                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4858                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4859                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4860         } else {
4861                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4862                 /*
4863                  * In order to prevent Tx hangs when the internal Tx
4864                  * switch is enabled we must set the high water mark
4865                  * to the maximum FCRTH value.  This allows the Tx
4866                  * switch to function even under heavy Rx workloads.
4867                  */
4868                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4869         }
4870         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4871
4872         /* Configure pause time (2 TCs per register) */
4873         reg = hw->fc.pause_time * 0x00010001;
4874         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4875                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4876
4877         /* Configure flow control refresh threshold value */
4878         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4879
4880 out:
4881         return ret_val;
4882 }
4883
4884 static int
4885 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4886 {
4887         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4888         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4889
4890         if (hw->mac.type != ixgbe_mac_82598EB) {
4891                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4892         }
4893         return ret_val;
4894 }
4895
4896 static int
4897 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4898 {
4899         int err;
4900         uint32_t rx_buf_size;
4901         uint32_t max_high_water;
4902         uint8_t tc_num;
4903         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4904         struct ixgbe_hw *hw =
4905                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4906         struct ixgbe_dcb_config *dcb_config =
4907                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4908
4909         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4910                 ixgbe_fc_none,
4911                 ixgbe_fc_rx_pause,
4912                 ixgbe_fc_tx_pause,
4913                 ixgbe_fc_full
4914         };
4915
4916         PMD_INIT_FUNC_TRACE();
4917
4918         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4919         tc_num = map[pfc_conf->priority];
4920         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4921         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4922         /*
4923          * At least reserve one Ethernet frame for watermark
4924          * high_water/low_water in kilo bytes for ixgbe
4925          */
4926         max_high_water = (rx_buf_size -
4927                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4928         if ((pfc_conf->fc.high_water > max_high_water) ||
4929             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4930                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4931                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4932                 return -EINVAL;
4933         }
4934
4935         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4936         hw->fc.pause_time = pfc_conf->fc.pause_time;
4937         hw->fc.send_xon = pfc_conf->fc.send_xon;
4938         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4939         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4940
4941         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4942
4943         /* Not negotiated is not an error case */
4944         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4945                 return 0;
4946
4947         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4948         return -EIO;
4949 }
4950
4951 static int
4952 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4953                           struct rte_eth_rss_reta_entry64 *reta_conf,
4954                           uint16_t reta_size)
4955 {
4956         uint16_t i, sp_reta_size;
4957         uint8_t j, mask;
4958         uint32_t reta, r;
4959         uint16_t idx, shift;
4960         struct ixgbe_adapter *adapter = dev->data->dev_private;
4961         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4962         uint32_t reta_reg;
4963
4964         PMD_INIT_FUNC_TRACE();
4965
4966         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4967                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4968                         "NIC.");
4969                 return -ENOTSUP;
4970         }
4971
4972         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4973         if (reta_size != sp_reta_size) {
4974                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4975                         "(%d) doesn't match the number hardware can supported "
4976                         "(%d)", reta_size, sp_reta_size);
4977                 return -EINVAL;
4978         }
4979
4980         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4981                 idx = i / RTE_RETA_GROUP_SIZE;
4982                 shift = i % RTE_RETA_GROUP_SIZE;
4983                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4984                                                 IXGBE_4_BIT_MASK);
4985                 if (!mask)
4986                         continue;
4987                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4988                 if (mask == IXGBE_4_BIT_MASK)
4989                         r = 0;
4990                 else
4991                         r = IXGBE_READ_REG(hw, reta_reg);
4992                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4993                         if (mask & (0x1 << j))
4994                                 reta |= reta_conf[idx].reta[shift + j] <<
4995                                                         (CHAR_BIT * j);
4996                         else
4997                                 reta |= r & (IXGBE_8_BIT_MASK <<
4998                                                 (CHAR_BIT * j));
4999                 }
5000                 IXGBE_WRITE_REG(hw, reta_reg, reta);
5001         }
5002         adapter->rss_reta_updated = 1;
5003
5004         return 0;
5005 }
5006
5007 static int
5008 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5009                          struct rte_eth_rss_reta_entry64 *reta_conf,
5010                          uint16_t reta_size)
5011 {
5012         uint16_t i, sp_reta_size;
5013         uint8_t j, mask;
5014         uint32_t reta;
5015         uint16_t idx, shift;
5016         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5017         uint32_t reta_reg;
5018
5019         PMD_INIT_FUNC_TRACE();
5020         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5021         if (reta_size != sp_reta_size) {
5022                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5023                         "(%d) doesn't match the number hardware can supported "
5024                         "(%d)", reta_size, sp_reta_size);
5025                 return -EINVAL;
5026         }
5027
5028         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5029                 idx = i / RTE_RETA_GROUP_SIZE;
5030                 shift = i % RTE_RETA_GROUP_SIZE;
5031                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5032                                                 IXGBE_4_BIT_MASK);
5033                 if (!mask)
5034                         continue;
5035
5036                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5037                 reta = IXGBE_READ_REG(hw, reta_reg);
5038                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5039                         if (mask & (0x1 << j))
5040                                 reta_conf[idx].reta[shift + j] =
5041                                         ((reta >> (CHAR_BIT * j)) &
5042                                                 IXGBE_8_BIT_MASK);
5043                 }
5044         }
5045
5046         return 0;
5047 }
5048
5049 static int
5050 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5051                                 uint32_t index, uint32_t pool)
5052 {
5053         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5054         uint32_t enable_addr = 1;
5055
5056         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5057                              pool, enable_addr);
5058 }
5059
5060 static void
5061 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5062 {
5063         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5064
5065         ixgbe_clear_rar(hw, index);
5066 }
5067
5068 static int
5069 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5070 {
5071         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5072
5073         ixgbe_remove_rar(dev, 0);
5074         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5075
5076         return 0;
5077 }
5078
5079 static bool
5080 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5081 {
5082         if (strcmp(dev->device->driver->name, drv->driver.name))
5083                 return false;
5084
5085         return true;
5086 }
5087
5088 bool
5089 is_ixgbe_supported(struct rte_eth_dev *dev)
5090 {
5091         return is_device_supported(dev, &rte_ixgbe_pmd);
5092 }
5093
5094 static int
5095 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5096 {
5097         uint32_t hlreg0;
5098         uint32_t maxfrs;
5099         struct ixgbe_hw *hw;
5100         struct rte_eth_dev_info dev_info;
5101         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5102         struct rte_eth_dev_data *dev_data = dev->data;
5103         int ret;
5104
5105         ret = ixgbe_dev_info_get(dev, &dev_info);
5106         if (ret != 0)
5107                 return ret;
5108
5109         /* check that mtu is within the allowed range */
5110         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5111                 return -EINVAL;
5112
5113         /* If device is started, refuse mtu that requires the support of
5114          * scattered packets when this feature has not been enabled before.
5115          */
5116         if (dev_data->dev_started && !dev_data->scattered_rx &&
5117             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5118              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5119                 PMD_INIT_LOG(ERR, "Stop port first.");
5120                 return -EINVAL;
5121         }
5122
5123         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5124         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5125
5126         /* switch to jumbo mode if needed */
5127         if (frame_size > RTE_ETHER_MAX_LEN) {
5128                 dev->data->dev_conf.rxmode.offloads |=
5129                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5130                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5131         } else {
5132                 dev->data->dev_conf.rxmode.offloads &=
5133                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5134                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5135         }
5136         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5137
5138         /* update max frame size */
5139         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5140
5141         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5142         maxfrs &= 0x0000FFFF;
5143         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5144         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5145
5146         return 0;
5147 }
5148
5149 /*
5150  * Virtual Function operations
5151  */
5152 static void
5153 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5154 {
5155         struct ixgbe_interrupt *intr =
5156                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5157         struct ixgbe_hw *hw =
5158                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5159
5160         PMD_INIT_FUNC_TRACE();
5161
5162         /* Clear interrupt mask to stop from interrupts being generated */
5163         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5164
5165         IXGBE_WRITE_FLUSH(hw);
5166
5167         /* Clear mask value. */
5168         intr->mask = 0;
5169 }
5170
5171 static void
5172 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5173 {
5174         struct ixgbe_interrupt *intr =
5175                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5176         struct ixgbe_hw *hw =
5177                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5178
5179         PMD_INIT_FUNC_TRACE();
5180
5181         /* VF enable interrupt autoclean */
5182         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5183         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5184         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5185
5186         IXGBE_WRITE_FLUSH(hw);
5187
5188         /* Save IXGBE_VTEIMS value to mask. */
5189         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5190 }
5191
5192 static int
5193 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5194 {
5195         struct rte_eth_conf *conf = &dev->data->dev_conf;
5196         struct ixgbe_adapter *adapter = dev->data->dev_private;
5197
5198         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5199                      dev->data->port_id);
5200
5201         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5202                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5203
5204         /*
5205          * VF has no ability to enable/disable HW CRC
5206          * Keep the persistent behavior the same as Host PF
5207          */
5208 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5209         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5210                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5211                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5212         }
5213 #else
5214         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5215                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5216                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5217         }
5218 #endif
5219
5220         /*
5221          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5222          * allocation or vector Rx preconditions we will reset it.
5223          */
5224         adapter->rx_bulk_alloc_allowed = true;
5225         adapter->rx_vec_allowed = true;
5226
5227         return 0;
5228 }
5229
5230 static int
5231 ixgbevf_dev_start(struct rte_eth_dev *dev)
5232 {
5233         struct ixgbe_hw *hw =
5234                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5235         uint32_t intr_vector = 0;
5236         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5237         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5238
5239         int err, mask = 0;
5240
5241         PMD_INIT_FUNC_TRACE();
5242
5243         /* Stop the link setup handler before resetting the HW. */
5244         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5245
5246         err = hw->mac.ops.reset_hw(hw);
5247         if (err) {
5248                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5249                 return err;
5250         }
5251         hw->mac.get_link_status = true;
5252
5253         /* negotiate mailbox API version to use with the PF. */
5254         ixgbevf_negotiate_api(hw);
5255
5256         ixgbevf_dev_tx_init(dev);
5257
5258         /* This can fail when allocating mbufs for descriptor rings */
5259         err = ixgbevf_dev_rx_init(dev);
5260         if (err) {
5261                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5262                 ixgbe_dev_clear_queues(dev);
5263                 return err;
5264         }
5265
5266         /* Set vfta */
5267         ixgbevf_set_vfta_all(dev, 1);
5268
5269         /* Set HW strip */
5270         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5271                 ETH_VLAN_EXTEND_MASK;
5272         err = ixgbevf_vlan_offload_config(dev, mask);
5273         if (err) {
5274                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5275                 ixgbe_dev_clear_queues(dev);
5276                 return err;
5277         }
5278
5279         ixgbevf_dev_rxtx_start(dev);
5280
5281         /* check and configure queue intr-vector mapping */
5282         if (rte_intr_cap_multiple(intr_handle) &&
5283             dev->data->dev_conf.intr_conf.rxq) {
5284                 /* According to datasheet, only vector 0/1/2 can be used,
5285                  * now only one vector is used for Rx queue
5286                  */
5287                 intr_vector = 1;
5288                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5289                         return -1;
5290         }
5291
5292         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5293                 intr_handle->intr_vec =
5294                         rte_zmalloc("intr_vec",
5295                                     dev->data->nb_rx_queues * sizeof(int), 0);
5296                 if (intr_handle->intr_vec == NULL) {
5297                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5298                                      " intr_vec", dev->data->nb_rx_queues);
5299                         return -ENOMEM;
5300                 }
5301         }
5302         ixgbevf_configure_msix(dev);
5303
5304         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5305          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5306          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5307          * is not cleared, it will fail when following rte_intr_enable( ) tries
5308          * to map Rx queue interrupt to other VFIO vectors.
5309          * So clear uio/vfio intr/evevnfd first to avoid failure.
5310          */
5311         rte_intr_disable(intr_handle);
5312
5313         rte_intr_enable(intr_handle);
5314
5315         /* Re-enable interrupt for VF */
5316         ixgbevf_intr_enable(dev);
5317
5318         /*
5319          * Update link status right before return, because it may
5320          * start link configuration process in a separate thread.
5321          */
5322         ixgbevf_dev_link_update(dev, 0);
5323
5324         hw->adapter_stopped = false;
5325
5326         return 0;
5327 }
5328
5329 static void
5330 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5331 {
5332         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5333         struct ixgbe_adapter *adapter = dev->data->dev_private;
5334         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5335         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5336
5337         if (hw->adapter_stopped)
5338                 return;
5339
5340         PMD_INIT_FUNC_TRACE();
5341
5342         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5343
5344         ixgbevf_intr_disable(dev);
5345
5346         hw->adapter_stopped = 1;
5347         ixgbe_stop_adapter(hw);
5348
5349         /*
5350           * Clear what we set, but we still keep shadow_vfta to
5351           * restore after device starts
5352           */
5353         ixgbevf_set_vfta_all(dev, 0);
5354
5355         /* Clear stored conf */
5356         dev->data->scattered_rx = 0;
5357
5358         ixgbe_dev_clear_queues(dev);
5359
5360         /* Clean datapath event and queue/vec mapping */
5361         rte_intr_efd_disable(intr_handle);
5362         if (intr_handle->intr_vec != NULL) {
5363                 rte_free(intr_handle->intr_vec);
5364                 intr_handle->intr_vec = NULL;
5365         }
5366
5367         adapter->rss_reta_updated = 0;
5368 }
5369
5370 static void
5371 ixgbevf_dev_close(struct rte_eth_dev *dev)
5372 {
5373         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5374         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5375         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5376
5377         PMD_INIT_FUNC_TRACE();
5378
5379         ixgbe_reset_hw(hw);
5380
5381         ixgbevf_dev_stop(dev);
5382
5383         ixgbe_dev_free_queues(dev);
5384
5385         /**
5386          * Remove the VF MAC address ro ensure
5387          * that the VF traffic goes to the PF
5388          * after stop, close and detach of the VF
5389          **/
5390         ixgbevf_remove_mac_addr(dev, 0);
5391
5392         dev->dev_ops = NULL;
5393         dev->rx_pkt_burst = NULL;
5394         dev->tx_pkt_burst = NULL;
5395
5396         rte_intr_disable(intr_handle);
5397         rte_intr_callback_unregister(intr_handle,
5398                                      ixgbevf_dev_interrupt_handler, dev);
5399 }
5400
5401 /*
5402  * Reset VF device
5403  */
5404 static int
5405 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5406 {
5407         int ret;
5408
5409         ret = eth_ixgbevf_dev_uninit(dev);
5410         if (ret)
5411                 return ret;
5412
5413         ret = eth_ixgbevf_dev_init(dev);
5414
5415         return ret;
5416 }
5417
5418 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5419 {
5420         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5421         struct ixgbe_vfta *shadow_vfta =
5422                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5423         int i = 0, j = 0, vfta = 0, mask = 1;
5424
5425         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5426                 vfta = shadow_vfta->vfta[i];
5427                 if (vfta) {
5428                         mask = 1;
5429                         for (j = 0; j < 32; j++) {
5430                                 if (vfta & mask)
5431                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5432                                                        on, false);
5433                                 mask <<= 1;
5434                         }
5435                 }
5436         }
5437
5438 }
5439
5440 static int
5441 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5442 {
5443         struct ixgbe_hw *hw =
5444                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5445         struct ixgbe_vfta *shadow_vfta =
5446                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5447         uint32_t vid_idx = 0;
5448         uint32_t vid_bit = 0;
5449         int ret = 0;
5450
5451         PMD_INIT_FUNC_TRACE();
5452
5453         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5454         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5455         if (ret) {
5456                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5457                 return ret;
5458         }
5459         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5460         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5461
5462         /* Save what we set and retore it after device reset */
5463         if (on)
5464                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5465         else
5466                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5467
5468         return 0;
5469 }
5470
5471 static void
5472 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5473 {
5474         struct ixgbe_hw *hw =
5475                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5476         uint32_t ctrl;
5477
5478         PMD_INIT_FUNC_TRACE();
5479
5480         if (queue >= hw->mac.max_rx_queues)
5481                 return;
5482
5483         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5484         if (on)
5485                 ctrl |= IXGBE_RXDCTL_VME;
5486         else
5487                 ctrl &= ~IXGBE_RXDCTL_VME;
5488         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5489
5490         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5491 }
5492
5493 static int
5494 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5495 {
5496         struct ixgbe_rx_queue *rxq;
5497         uint16_t i;
5498         int on = 0;
5499
5500         /* VF function only support hw strip feature, others are not support */
5501         if (mask & ETH_VLAN_STRIP_MASK) {
5502                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5503                         rxq = dev->data->rx_queues[i];
5504                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5505                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5506                 }
5507         }
5508
5509         return 0;
5510 }
5511
5512 static int
5513 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5514 {
5515         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5516
5517         ixgbevf_vlan_offload_config(dev, mask);
5518
5519         return 0;
5520 }
5521
5522 int
5523 ixgbe_vt_check(struct ixgbe_hw *hw)
5524 {
5525         uint32_t reg_val;
5526
5527         /* if Virtualization Technology is enabled */
5528         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5529         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5530                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5531                 return -1;
5532         }
5533
5534         return 0;
5535 }
5536
5537 static uint32_t
5538 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5539 {
5540         uint32_t vector = 0;
5541
5542         switch (hw->mac.mc_filter_type) {
5543         case 0:   /* use bits [47:36] of the address */
5544                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5545                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5546                 break;
5547         case 1:   /* use bits [46:35] of the address */
5548                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5549                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5550                 break;
5551         case 2:   /* use bits [45:34] of the address */
5552                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5553                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5554                 break;
5555         case 3:   /* use bits [43:32] of the address */
5556                 vector = ((uc_addr->addr_bytes[4]) |
5557                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5558                 break;
5559         default:  /* Invalid mc_filter_type */
5560                 break;
5561         }
5562
5563         /* vector can only be 12-bits or boundary will be exceeded */
5564         vector &= 0xFFF;
5565         return vector;
5566 }
5567
5568 static int
5569 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5570                         struct rte_ether_addr *mac_addr, uint8_t on)
5571 {
5572         uint32_t vector;
5573         uint32_t uta_idx;
5574         uint32_t reg_val;
5575         uint32_t uta_shift;
5576         uint32_t rc;
5577         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5578         const uint32_t ixgbe_uta_bit_shift = 5;
5579         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5580         const uint32_t bit1 = 0x1;
5581
5582         struct ixgbe_hw *hw =
5583                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5584         struct ixgbe_uta_info *uta_info =
5585                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5586
5587         /* The UTA table only exists on 82599 hardware and newer */
5588         if (hw->mac.type < ixgbe_mac_82599EB)
5589                 return -ENOTSUP;
5590
5591         vector = ixgbe_uta_vector(hw, mac_addr);
5592         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5593         uta_shift = vector & ixgbe_uta_bit_mask;
5594
5595         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5596         if (rc == on)
5597                 return 0;
5598
5599         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5600         if (on) {
5601                 uta_info->uta_in_use++;
5602                 reg_val |= (bit1 << uta_shift);
5603                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5604         } else {
5605                 uta_info->uta_in_use--;
5606                 reg_val &= ~(bit1 << uta_shift);
5607                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5608         }
5609
5610         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5611
5612         if (uta_info->uta_in_use > 0)
5613                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5614                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5615         else
5616                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5617
5618         return 0;
5619 }
5620
5621 static int
5622 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5623 {
5624         int i;
5625         struct ixgbe_hw *hw =
5626                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5627         struct ixgbe_uta_info *uta_info =
5628                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5629
5630         /* The UTA table only exists on 82599 hardware and newer */
5631         if (hw->mac.type < ixgbe_mac_82599EB)
5632                 return -ENOTSUP;
5633
5634         if (on) {
5635                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5636                         uta_info->uta_shadow[i] = ~0;
5637                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5638                 }
5639         } else {
5640                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5641                         uta_info->uta_shadow[i] = 0;
5642                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5643                 }
5644         }
5645         return 0;
5646
5647 }
5648
5649 uint32_t
5650 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5651 {
5652         uint32_t new_val = orig_val;
5653
5654         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5655                 new_val |= IXGBE_VMOLR_AUPE;
5656         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5657                 new_val |= IXGBE_VMOLR_ROMPE;
5658         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5659                 new_val |= IXGBE_VMOLR_ROPE;
5660         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5661                 new_val |= IXGBE_VMOLR_BAM;
5662         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5663                 new_val |= IXGBE_VMOLR_MPE;
5664
5665         return new_val;
5666 }
5667
5668 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5669 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5670 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5671 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5672 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5673         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5674         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5675
5676 static int
5677 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5678                       struct rte_eth_mirror_conf *mirror_conf,
5679                       uint8_t rule_id, uint8_t on)
5680 {
5681         uint32_t mr_ctl, vlvf;
5682         uint32_t mp_lsb = 0;
5683         uint32_t mv_msb = 0;
5684         uint32_t mv_lsb = 0;
5685         uint32_t mp_msb = 0;
5686         uint8_t i = 0;
5687         int reg_index = 0;
5688         uint64_t vlan_mask = 0;
5689
5690         const uint8_t pool_mask_offset = 32;
5691         const uint8_t vlan_mask_offset = 32;
5692         const uint8_t dst_pool_offset = 8;
5693         const uint8_t rule_mr_offset  = 4;
5694         const uint8_t mirror_rule_mask = 0x0F;
5695
5696         struct ixgbe_mirror_info *mr_info =
5697                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5698         struct ixgbe_hw *hw =
5699                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5700         uint8_t mirror_type = 0;
5701
5702         if (ixgbe_vt_check(hw) < 0)
5703                 return -ENOTSUP;
5704
5705         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5706                 return -EINVAL;
5707
5708         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5709                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5710                             mirror_conf->rule_type);
5711                 return -EINVAL;
5712         }
5713
5714         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5715                 mirror_type |= IXGBE_MRCTL_VLME;
5716                 /* Check if vlan id is valid and find conresponding VLAN ID
5717                  * index in VLVF
5718                  */
5719                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5720                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5721                                 /* search vlan id related pool vlan filter
5722                                  * index
5723                                  */
5724                                 reg_index = ixgbe_find_vlvf_slot(
5725                                                 hw,
5726                                                 mirror_conf->vlan.vlan_id[i],
5727                                                 false);
5728                                 if (reg_index < 0)
5729                                         return -EINVAL;
5730                                 vlvf = IXGBE_READ_REG(hw,
5731                                                       IXGBE_VLVF(reg_index));
5732                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5733                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5734                                       mirror_conf->vlan.vlan_id[i]))
5735                                         vlan_mask |= (1ULL << reg_index);
5736                                 else
5737                                         return -EINVAL;
5738                         }
5739                 }
5740
5741                 if (on) {
5742                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5743                         mv_msb = vlan_mask >> vlan_mask_offset;
5744
5745                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5746                                                 mirror_conf->vlan.vlan_mask;
5747                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5748                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5749                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5750                                                 mirror_conf->vlan.vlan_id[i];
5751                         }
5752                 } else {
5753                         mv_lsb = 0;
5754                         mv_msb = 0;
5755                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5756                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5757                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5758                 }
5759         }
5760
5761         /**
5762          * if enable pool mirror, write related pool mask register,if disable
5763          * pool mirror, clear PFMRVM register
5764          */
5765         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5766                 mirror_type |= IXGBE_MRCTL_VPME;
5767                 if (on) {
5768                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5769                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5770                         mr_info->mr_conf[rule_id].pool_mask =
5771                                         mirror_conf->pool_mask;
5772
5773                 } else {
5774                         mp_lsb = 0;
5775                         mp_msb = 0;
5776                         mr_info->mr_conf[rule_id].pool_mask = 0;
5777                 }
5778         }
5779         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5780                 mirror_type |= IXGBE_MRCTL_UPME;
5781         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5782                 mirror_type |= IXGBE_MRCTL_DPME;
5783
5784         /* read  mirror control register and recalculate it */
5785         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5786
5787         if (on) {
5788                 mr_ctl |= mirror_type;
5789                 mr_ctl &= mirror_rule_mask;
5790                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5791         } else {
5792                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5793         }
5794
5795         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5796         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5797
5798         /* write mirrror control  register */
5799         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5800
5801         /* write pool mirrror control  register */
5802         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5803                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5804                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5805                                 mp_msb);
5806         }
5807         /* write VLAN mirrror control  register */
5808         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5809                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5810                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5811                                 mv_msb);
5812         }
5813
5814         return 0;
5815 }
5816
5817 static int
5818 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5819 {
5820         int mr_ctl = 0;
5821         uint32_t lsb_val = 0;
5822         uint32_t msb_val = 0;
5823         const uint8_t rule_mr_offset = 4;
5824
5825         struct ixgbe_hw *hw =
5826                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5827         struct ixgbe_mirror_info *mr_info =
5828                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5829
5830         if (ixgbe_vt_check(hw) < 0)
5831                 return -ENOTSUP;
5832
5833         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5834                 return -EINVAL;
5835
5836         memset(&mr_info->mr_conf[rule_id], 0,
5837                sizeof(struct rte_eth_mirror_conf));
5838
5839         /* clear PFVMCTL register */
5840         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5841
5842         /* clear pool mask register */
5843         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5844         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5845
5846         /* clear vlan mask register */
5847         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5848         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5849
5850         return 0;
5851 }
5852
5853 static int
5854 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5855 {
5856         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5857         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5858         struct ixgbe_interrupt *intr =
5859                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5860         struct ixgbe_hw *hw =
5861                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5862         uint32_t vec = IXGBE_MISC_VEC_ID;
5863
5864         if (rte_intr_allow_others(intr_handle))
5865                 vec = IXGBE_RX_VEC_START;
5866         intr->mask |= (1 << vec);
5867         RTE_SET_USED(queue_id);
5868         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5869
5870         rte_intr_ack(intr_handle);
5871
5872         return 0;
5873 }
5874
5875 static int
5876 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5877 {
5878         struct ixgbe_interrupt *intr =
5879                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5880         struct ixgbe_hw *hw =
5881                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5882         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5883         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5884         uint32_t vec = IXGBE_MISC_VEC_ID;
5885
5886         if (rte_intr_allow_others(intr_handle))
5887                 vec = IXGBE_RX_VEC_START;
5888         intr->mask &= ~(1 << vec);
5889         RTE_SET_USED(queue_id);
5890         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5891
5892         return 0;
5893 }
5894
5895 static int
5896 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5897 {
5898         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5899         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5900         uint32_t mask;
5901         struct ixgbe_hw *hw =
5902                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5903         struct ixgbe_interrupt *intr =
5904                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5905
5906         if (queue_id < 16) {
5907                 ixgbe_disable_intr(hw);
5908                 intr->mask |= (1 << queue_id);
5909                 ixgbe_enable_intr(dev);
5910         } else if (queue_id < 32) {
5911                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5912                 mask &= (1 << queue_id);
5913                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5914         } else if (queue_id < 64) {
5915                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5916                 mask &= (1 << (queue_id - 32));
5917                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5918         }
5919         rte_intr_ack(intr_handle);
5920
5921         return 0;
5922 }
5923
5924 static int
5925 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5926 {
5927         uint32_t mask;
5928         struct ixgbe_hw *hw =
5929                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5930         struct ixgbe_interrupt *intr =
5931                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5932
5933         if (queue_id < 16) {
5934                 ixgbe_disable_intr(hw);
5935                 intr->mask &= ~(1 << queue_id);
5936                 ixgbe_enable_intr(dev);
5937         } else if (queue_id < 32) {
5938                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5939                 mask &= ~(1 << queue_id);
5940                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5941         } else if (queue_id < 64) {
5942                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5943                 mask &= ~(1 << (queue_id - 32));
5944                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5945         }
5946
5947         return 0;
5948 }
5949
5950 static void
5951 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5952                      uint8_t queue, uint8_t msix_vector)
5953 {
5954         uint32_t tmp, idx;
5955
5956         if (direction == -1) {
5957                 /* other causes */
5958                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5959                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5960                 tmp &= ~0xFF;
5961                 tmp |= msix_vector;
5962                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5963         } else {
5964                 /* rx or tx cause */
5965                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5966                 idx = ((16 * (queue & 1)) + (8 * direction));
5967                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5968                 tmp &= ~(0xFF << idx);
5969                 tmp |= (msix_vector << idx);
5970                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5971         }
5972 }
5973
5974 /**
5975  * set the IVAR registers, mapping interrupt causes to vectors
5976  * @param hw
5977  *  pointer to ixgbe_hw struct
5978  * @direction
5979  *  0 for Rx, 1 for Tx, -1 for other causes
5980  * @queue
5981  *  queue to map the corresponding interrupt to
5982  * @msix_vector
5983  *  the vector to map to the corresponding queue
5984  */
5985 static void
5986 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5987                    uint8_t queue, uint8_t msix_vector)
5988 {
5989         uint32_t tmp, idx;
5990
5991         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5992         if (hw->mac.type == ixgbe_mac_82598EB) {
5993                 if (direction == -1)
5994                         direction = 0;
5995                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5996                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5997                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5998                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5999                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6000         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6001                         (hw->mac.type == ixgbe_mac_X540) ||
6002                         (hw->mac.type == ixgbe_mac_X550) ||
6003                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
6004                 if (direction == -1) {
6005                         /* other causes */
6006                         idx = ((queue & 1) * 8);
6007                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6008                         tmp &= ~(0xFF << idx);
6009                         tmp |= (msix_vector << idx);
6010                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6011                 } else {
6012                         /* rx or tx causes */
6013                         idx = ((16 * (queue & 1)) + (8 * direction));
6014                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6015                         tmp &= ~(0xFF << idx);
6016                         tmp |= (msix_vector << idx);
6017                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6018                 }
6019         }
6020 }
6021
6022 static void
6023 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6024 {
6025         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6026         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6027         struct ixgbe_hw *hw =
6028                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6029         uint32_t q_idx;
6030         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6031         uint32_t base = IXGBE_MISC_VEC_ID;
6032
6033         /* Configure VF other cause ivar */
6034         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6035
6036         /* won't configure msix register if no mapping is done
6037          * between intr vector and event fd.
6038          */
6039         if (!rte_intr_dp_is_en(intr_handle))
6040                 return;
6041
6042         if (rte_intr_allow_others(intr_handle)) {
6043                 base = IXGBE_RX_VEC_START;
6044                 vector_idx = IXGBE_RX_VEC_START;
6045         }
6046
6047         /* Configure all RX queues of VF */
6048         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6049                 /* Force all queue use vector 0,
6050                  * as IXGBE_VF_MAXMSIVECOTR = 1
6051                  */
6052                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6053                 intr_handle->intr_vec[q_idx] = vector_idx;
6054                 if (vector_idx < base + intr_handle->nb_efd - 1)
6055                         vector_idx++;
6056         }
6057
6058         /* As RX queue setting above show, all queues use the vector 0.
6059          * Set only the ITR value of IXGBE_MISC_VEC_ID.
6060          */
6061         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6062                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6063                         | IXGBE_EITR_CNT_WDIS);
6064 }
6065
6066 /**
6067  * Sets up the hardware to properly generate MSI-X interrupts
6068  * @hw
6069  *  board private structure
6070  */
6071 static void
6072 ixgbe_configure_msix(struct rte_eth_dev *dev)
6073 {
6074         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6075         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6076         struct ixgbe_hw *hw =
6077                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6078         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6079         uint32_t vec = IXGBE_MISC_VEC_ID;
6080         uint32_t mask;
6081         uint32_t gpie;
6082
6083         /* won't configure msix register if no mapping is done
6084          * between intr vector and event fd
6085          * but if misx has been enabled already, need to configure
6086          * auto clean, auto mask and throttling.
6087          */
6088         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6089         if (!rte_intr_dp_is_en(intr_handle) &&
6090             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6091                 return;
6092
6093         if (rte_intr_allow_others(intr_handle))
6094                 vec = base = IXGBE_RX_VEC_START;
6095
6096         /* setup GPIE for MSI-x mode */
6097         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6098         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6099                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6100         /* auto clearing and auto setting corresponding bits in EIMS
6101          * when MSI-X interrupt is triggered
6102          */
6103         if (hw->mac.type == ixgbe_mac_82598EB) {
6104                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6105         } else {
6106                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6107                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6108         }
6109         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6110
6111         /* Populate the IVAR table and set the ITR values to the
6112          * corresponding register.
6113          */
6114         if (rte_intr_dp_is_en(intr_handle)) {
6115                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6116                         queue_id++) {
6117                         /* by default, 1:1 mapping */
6118                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6119                         intr_handle->intr_vec[queue_id] = vec;
6120                         if (vec < base + intr_handle->nb_efd - 1)
6121                                 vec++;
6122                 }
6123
6124                 switch (hw->mac.type) {
6125                 case ixgbe_mac_82598EB:
6126                         ixgbe_set_ivar_map(hw, -1,
6127                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6128                                            IXGBE_MISC_VEC_ID);
6129                         break;
6130                 case ixgbe_mac_82599EB:
6131                 case ixgbe_mac_X540:
6132                 case ixgbe_mac_X550:
6133                 case ixgbe_mac_X550EM_x:
6134                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6135                         break;
6136                 default:
6137                         break;
6138                 }
6139         }
6140         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6141                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6142                         | IXGBE_EITR_CNT_WDIS);
6143
6144         /* set up to autoclear timer, and the vectors */
6145         mask = IXGBE_EIMS_ENABLE_MASK;
6146         mask &= ~(IXGBE_EIMS_OTHER |
6147                   IXGBE_EIMS_MAILBOX |
6148                   IXGBE_EIMS_LSC);
6149
6150         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6151 }
6152
6153 int
6154 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6155                            uint16_t queue_idx, uint16_t tx_rate)
6156 {
6157         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6158         struct rte_eth_rxmode *rxmode;
6159         uint32_t rf_dec, rf_int;
6160         uint32_t bcnrc_val;
6161         uint16_t link_speed = dev->data->dev_link.link_speed;
6162
6163         if (queue_idx >= hw->mac.max_tx_queues)
6164                 return -EINVAL;
6165
6166         if (tx_rate != 0) {
6167                 /* Calculate the rate factor values to set */
6168                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6169                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6170                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6171
6172                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6173                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6174                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6175                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6176         } else {
6177                 bcnrc_val = 0;
6178         }
6179
6180         rxmode = &dev->data->dev_conf.rxmode;
6181         /*
6182          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6183          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6184          * set as 0x4.
6185          */
6186         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6187             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6188                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6189                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6190         else
6191                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6192                         IXGBE_MMW_SIZE_DEFAULT);
6193
6194         /* Set RTTBCNRC of queue X */
6195         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6196         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6197         IXGBE_WRITE_FLUSH(hw);
6198
6199         return 0;
6200 }
6201
6202 static int
6203 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6204                      __attribute__((unused)) uint32_t index,
6205                      __attribute__((unused)) uint32_t pool)
6206 {
6207         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6208         int diag;
6209
6210         /*
6211          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6212          * operation. Trap this case to avoid exhausting the [very limited]
6213          * set of PF resources used to store VF MAC addresses.
6214          */
6215         if (memcmp(hw->mac.perm_addr, mac_addr,
6216                         sizeof(struct rte_ether_addr)) == 0)
6217                 return -1;
6218         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6219         if (diag != 0)
6220                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6221                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6222                             mac_addr->addr_bytes[0],
6223                             mac_addr->addr_bytes[1],
6224                             mac_addr->addr_bytes[2],
6225                             mac_addr->addr_bytes[3],
6226                             mac_addr->addr_bytes[4],
6227                             mac_addr->addr_bytes[5],
6228                             diag);
6229         return diag;
6230 }
6231
6232 static void
6233 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6234 {
6235         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6236         struct rte_ether_addr *perm_addr =
6237                 (struct rte_ether_addr *)hw->mac.perm_addr;
6238         struct rte_ether_addr *mac_addr;
6239         uint32_t i;
6240         int diag;
6241
6242         /*
6243          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6244          * not support the deletion of a given MAC address.
6245          * Instead, it imposes to delete all MAC addresses, then to add again
6246          * all MAC addresses with the exception of the one to be deleted.
6247          */
6248         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6249
6250         /*
6251          * Add again all MAC addresses, with the exception of the deleted one
6252          * and of the permanent MAC address.
6253          */
6254         for (i = 0, mac_addr = dev->data->mac_addrs;
6255              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6256                 /* Skip the deleted MAC address */
6257                 if (i == index)
6258                         continue;
6259                 /* Skip NULL MAC addresses */
6260                 if (rte_is_zero_ether_addr(mac_addr))
6261                         continue;
6262                 /* Skip the permanent MAC address */
6263                 if (memcmp(perm_addr, mac_addr,
6264                                 sizeof(struct rte_ether_addr)) == 0)
6265                         continue;
6266                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6267                 if (diag != 0)
6268                         PMD_DRV_LOG(ERR,
6269                                     "Adding again MAC address "
6270                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6271                                     "diag=%d",
6272                                     mac_addr->addr_bytes[0],
6273                                     mac_addr->addr_bytes[1],
6274                                     mac_addr->addr_bytes[2],
6275                                     mac_addr->addr_bytes[3],
6276                                     mac_addr->addr_bytes[4],
6277                                     mac_addr->addr_bytes[5],
6278                                     diag);
6279         }
6280 }
6281
6282 static int
6283 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6284                         struct rte_ether_addr *addr)
6285 {
6286         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6287
6288         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6289
6290         return 0;
6291 }
6292
6293 int
6294 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6295                         struct rte_eth_syn_filter *filter,
6296                         bool add)
6297 {
6298         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6299         struct ixgbe_filter_info *filter_info =
6300                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6301         uint32_t syn_info;
6302         uint32_t synqf;
6303
6304         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6305                 return -EINVAL;
6306
6307         syn_info = filter_info->syn_info;
6308
6309         if (add) {
6310                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6311                         return -EINVAL;
6312                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6313                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6314
6315                 if (filter->hig_pri)
6316                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6317                 else
6318                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6319         } else {
6320                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6321                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6322                         return -ENOENT;
6323                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6324         }
6325
6326         filter_info->syn_info = synqf;
6327         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6328         IXGBE_WRITE_FLUSH(hw);
6329         return 0;
6330 }
6331
6332 static int
6333 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6334                         struct rte_eth_syn_filter *filter)
6335 {
6336         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6337         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6338
6339         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6340                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6341                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6342                 return 0;
6343         }
6344         return -ENOENT;
6345 }
6346
6347 static int
6348 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6349                         enum rte_filter_op filter_op,
6350                         void *arg)
6351 {
6352         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6353         int ret;
6354
6355         MAC_TYPE_FILTER_SUP(hw->mac.type);
6356
6357         if (filter_op == RTE_ETH_FILTER_NOP)
6358                 return 0;
6359
6360         if (arg == NULL) {
6361                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6362                             filter_op);
6363                 return -EINVAL;
6364         }
6365
6366         switch (filter_op) {
6367         case RTE_ETH_FILTER_ADD:
6368                 ret = ixgbe_syn_filter_set(dev,
6369                                 (struct rte_eth_syn_filter *)arg,
6370                                 TRUE);
6371                 break;
6372         case RTE_ETH_FILTER_DELETE:
6373                 ret = ixgbe_syn_filter_set(dev,
6374                                 (struct rte_eth_syn_filter *)arg,
6375                                 FALSE);
6376                 break;
6377         case RTE_ETH_FILTER_GET:
6378                 ret = ixgbe_syn_filter_get(dev,
6379                                 (struct rte_eth_syn_filter *)arg);
6380                 break;
6381         default:
6382                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6383                 ret = -EINVAL;
6384                 break;
6385         }
6386
6387         return ret;
6388 }
6389
6390
6391 static inline enum ixgbe_5tuple_protocol
6392 convert_protocol_type(uint8_t protocol_value)
6393 {
6394         if (protocol_value == IPPROTO_TCP)
6395                 return IXGBE_FILTER_PROTOCOL_TCP;
6396         else if (protocol_value == IPPROTO_UDP)
6397                 return IXGBE_FILTER_PROTOCOL_UDP;
6398         else if (protocol_value == IPPROTO_SCTP)
6399                 return IXGBE_FILTER_PROTOCOL_SCTP;
6400         else
6401                 return IXGBE_FILTER_PROTOCOL_NONE;
6402 }
6403
6404 /* inject a 5-tuple filter to HW */
6405 static inline void
6406 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6407                            struct ixgbe_5tuple_filter *filter)
6408 {
6409         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6410         int i;
6411         uint32_t ftqf, sdpqf;
6412         uint32_t l34timir = 0;
6413         uint8_t mask = 0xff;
6414
6415         i = filter->index;
6416
6417         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6418                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6419         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6420
6421         ftqf = (uint32_t)(filter->filter_info.proto &
6422                 IXGBE_FTQF_PROTOCOL_MASK);
6423         ftqf |= (uint32_t)((filter->filter_info.priority &
6424                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6425         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6426                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6427         if (filter->filter_info.dst_ip_mask == 0)
6428                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6429         if (filter->filter_info.src_port_mask == 0)
6430                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6431         if (filter->filter_info.dst_port_mask == 0)
6432                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6433         if (filter->filter_info.proto_mask == 0)
6434                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6435         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6436         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6437         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6438
6439         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6440         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6441         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6442         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6443
6444         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6445         l34timir |= (uint32_t)(filter->queue <<
6446                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6447         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6448 }
6449
6450 /*
6451  * add a 5tuple filter
6452  *
6453  * @param
6454  * dev: Pointer to struct rte_eth_dev.
6455  * index: the index the filter allocates.
6456  * filter: ponter to the filter that will be added.
6457  * rx_queue: the queue id the filter assigned to.
6458  *
6459  * @return
6460  *    - On success, zero.
6461  *    - On failure, a negative value.
6462  */
6463 static int
6464 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6465                         struct ixgbe_5tuple_filter *filter)
6466 {
6467         struct ixgbe_filter_info *filter_info =
6468                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6469         int i, idx, shift;
6470
6471         /*
6472          * look for an unused 5tuple filter index,
6473          * and insert the filter to list.
6474          */
6475         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6476                 idx = i / (sizeof(uint32_t) * NBBY);
6477                 shift = i % (sizeof(uint32_t) * NBBY);
6478                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6479                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6480                         filter->index = i;
6481                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6482                                           filter,
6483                                           entries);
6484                         break;
6485                 }
6486         }
6487         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6488                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6489                 return -ENOSYS;
6490         }
6491
6492         ixgbe_inject_5tuple_filter(dev, filter);
6493
6494         return 0;
6495 }
6496
6497 /*
6498  * remove a 5tuple filter
6499  *
6500  * @param
6501  * dev: Pointer to struct rte_eth_dev.
6502  * filter: the pointer of the filter will be removed.
6503  */
6504 static void
6505 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6506                         struct ixgbe_5tuple_filter *filter)
6507 {
6508         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6509         struct ixgbe_filter_info *filter_info =
6510                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6511         uint16_t index = filter->index;
6512
6513         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6514                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6515         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6516         rte_free(filter);
6517
6518         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6519         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6520         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6521         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6522         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6523 }
6524
6525 static int
6526 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6527 {
6528         struct ixgbe_hw *hw;
6529         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6530         struct rte_eth_dev_data *dev_data = dev->data;
6531
6532         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6533
6534         if (mtu < RTE_ETHER_MIN_MTU ||
6535                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6536                 return -EINVAL;
6537
6538         /* If device is started, refuse mtu that requires the support of
6539          * scattered packets when this feature has not been enabled before.
6540          */
6541         if (dev_data->dev_started && !dev_data->scattered_rx &&
6542             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6543              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6544                 PMD_INIT_LOG(ERR, "Stop port first.");
6545                 return -EINVAL;
6546         }
6547
6548         /*
6549          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6550          * request of the version 2.0 of the mailbox API.
6551          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6552          * of the mailbox API.
6553          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6554          * prior to 3.11.33 which contains the following change:
6555          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6556          */
6557         ixgbevf_rlpml_set_vf(hw, max_frame);
6558
6559         /* update max frame size */
6560         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6561         return 0;
6562 }
6563
6564 static inline struct ixgbe_5tuple_filter *
6565 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6566                         struct ixgbe_5tuple_filter_info *key)
6567 {
6568         struct ixgbe_5tuple_filter *it;
6569
6570         TAILQ_FOREACH(it, filter_list, entries) {
6571                 if (memcmp(key, &it->filter_info,
6572                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6573                         return it;
6574                 }
6575         }
6576         return NULL;
6577 }
6578
6579 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6580 static inline int
6581 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6582                         struct ixgbe_5tuple_filter_info *filter_info)
6583 {
6584         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6585                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6586                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6587                 return -EINVAL;
6588
6589         switch (filter->dst_ip_mask) {
6590         case UINT32_MAX:
6591                 filter_info->dst_ip_mask = 0;
6592                 filter_info->dst_ip = filter->dst_ip;
6593                 break;
6594         case 0:
6595                 filter_info->dst_ip_mask = 1;
6596                 break;
6597         default:
6598                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6599                 return -EINVAL;
6600         }
6601
6602         switch (filter->src_ip_mask) {
6603         case UINT32_MAX:
6604                 filter_info->src_ip_mask = 0;
6605                 filter_info->src_ip = filter->src_ip;
6606                 break;
6607         case 0:
6608                 filter_info->src_ip_mask = 1;
6609                 break;
6610         default:
6611                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6612                 return -EINVAL;
6613         }
6614
6615         switch (filter->dst_port_mask) {
6616         case UINT16_MAX:
6617                 filter_info->dst_port_mask = 0;
6618                 filter_info->dst_port = filter->dst_port;
6619                 break;
6620         case 0:
6621                 filter_info->dst_port_mask = 1;
6622                 break;
6623         default:
6624                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6625                 return -EINVAL;
6626         }
6627
6628         switch (filter->src_port_mask) {
6629         case UINT16_MAX:
6630                 filter_info->src_port_mask = 0;
6631                 filter_info->src_port = filter->src_port;
6632                 break;
6633         case 0:
6634                 filter_info->src_port_mask = 1;
6635                 break;
6636         default:
6637                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6638                 return -EINVAL;
6639         }
6640
6641         switch (filter->proto_mask) {
6642         case UINT8_MAX:
6643                 filter_info->proto_mask = 0;
6644                 filter_info->proto =
6645                         convert_protocol_type(filter->proto);
6646                 break;
6647         case 0:
6648                 filter_info->proto_mask = 1;
6649                 break;
6650         default:
6651                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6652                 return -EINVAL;
6653         }
6654
6655         filter_info->priority = (uint8_t)filter->priority;
6656         return 0;
6657 }
6658
6659 /*
6660  * add or delete a ntuple filter
6661  *
6662  * @param
6663  * dev: Pointer to struct rte_eth_dev.
6664  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6665  * add: if true, add filter, if false, remove filter
6666  *
6667  * @return
6668  *    - On success, zero.
6669  *    - On failure, a negative value.
6670  */
6671 int
6672 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6673                         struct rte_eth_ntuple_filter *ntuple_filter,
6674                         bool add)
6675 {
6676         struct ixgbe_filter_info *filter_info =
6677                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6678         struct ixgbe_5tuple_filter_info filter_5tuple;
6679         struct ixgbe_5tuple_filter *filter;
6680         int ret;
6681
6682         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6683                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6684                 return -EINVAL;
6685         }
6686
6687         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6688         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6689         if (ret < 0)
6690                 return ret;
6691
6692         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6693                                          &filter_5tuple);
6694         if (filter != NULL && add) {
6695                 PMD_DRV_LOG(ERR, "filter exists.");
6696                 return -EEXIST;
6697         }
6698         if (filter == NULL && !add) {
6699                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6700                 return -ENOENT;
6701         }
6702
6703         if (add) {
6704                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6705                                 sizeof(struct ixgbe_5tuple_filter), 0);
6706                 if (filter == NULL)
6707                         return -ENOMEM;
6708                 rte_memcpy(&filter->filter_info,
6709                                  &filter_5tuple,
6710                                  sizeof(struct ixgbe_5tuple_filter_info));
6711                 filter->queue = ntuple_filter->queue;
6712                 ret = ixgbe_add_5tuple_filter(dev, filter);
6713                 if (ret < 0) {
6714                         rte_free(filter);
6715                         return ret;
6716                 }
6717         } else
6718                 ixgbe_remove_5tuple_filter(dev, filter);
6719
6720         return 0;
6721 }
6722
6723 /*
6724  * get a ntuple filter
6725  *
6726  * @param
6727  * dev: Pointer to struct rte_eth_dev.
6728  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6729  *
6730  * @return
6731  *    - On success, zero.
6732  *    - On failure, a negative value.
6733  */
6734 static int
6735 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6736                         struct rte_eth_ntuple_filter *ntuple_filter)
6737 {
6738         struct ixgbe_filter_info *filter_info =
6739                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6740         struct ixgbe_5tuple_filter_info filter_5tuple;
6741         struct ixgbe_5tuple_filter *filter;
6742         int ret;
6743
6744         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6745                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6746                 return -EINVAL;
6747         }
6748
6749         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6750         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6751         if (ret < 0)
6752                 return ret;
6753
6754         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6755                                          &filter_5tuple);
6756         if (filter == NULL) {
6757                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6758                 return -ENOENT;
6759         }
6760         ntuple_filter->queue = filter->queue;
6761         return 0;
6762 }
6763
6764 /*
6765  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6766  * @dev: pointer to rte_eth_dev structure
6767  * @filter_op:operation will be taken.
6768  * @arg: a pointer to specific structure corresponding to the filter_op
6769  *
6770  * @return
6771  *    - On success, zero.
6772  *    - On failure, a negative value.
6773  */
6774 static int
6775 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6776                                 enum rte_filter_op filter_op,
6777                                 void *arg)
6778 {
6779         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6780         int ret;
6781
6782         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6783
6784         if (filter_op == RTE_ETH_FILTER_NOP)
6785                 return 0;
6786
6787         if (arg == NULL) {
6788                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6789                             filter_op);
6790                 return -EINVAL;
6791         }
6792
6793         switch (filter_op) {
6794         case RTE_ETH_FILTER_ADD:
6795                 ret = ixgbe_add_del_ntuple_filter(dev,
6796                         (struct rte_eth_ntuple_filter *)arg,
6797                         TRUE);
6798                 break;
6799         case RTE_ETH_FILTER_DELETE:
6800                 ret = ixgbe_add_del_ntuple_filter(dev,
6801                         (struct rte_eth_ntuple_filter *)arg,
6802                         FALSE);
6803                 break;
6804         case RTE_ETH_FILTER_GET:
6805                 ret = ixgbe_get_ntuple_filter(dev,
6806                         (struct rte_eth_ntuple_filter *)arg);
6807                 break;
6808         default:
6809                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6810                 ret = -EINVAL;
6811                 break;
6812         }
6813         return ret;
6814 }
6815
6816 int
6817 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6818                         struct rte_eth_ethertype_filter *filter,
6819                         bool add)
6820 {
6821         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6822         struct ixgbe_filter_info *filter_info =
6823                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6824         uint32_t etqf = 0;
6825         uint32_t etqs = 0;
6826         int ret;
6827         struct ixgbe_ethertype_filter ethertype_filter;
6828
6829         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6830                 return -EINVAL;
6831
6832         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6833                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6834                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6835                         " ethertype filter.", filter->ether_type);
6836                 return -EINVAL;
6837         }
6838
6839         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6840                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6841                 return -EINVAL;
6842         }
6843         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6844                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6845                 return -EINVAL;
6846         }
6847
6848         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6849         if (ret >= 0 && add) {
6850                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6851                             filter->ether_type);
6852                 return -EEXIST;
6853         }
6854         if (ret < 0 && !add) {
6855                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6856                             filter->ether_type);
6857                 return -ENOENT;
6858         }
6859
6860         if (add) {
6861                 etqf = IXGBE_ETQF_FILTER_EN;
6862                 etqf |= (uint32_t)filter->ether_type;
6863                 etqs |= (uint32_t)((filter->queue <<
6864                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6865                                     IXGBE_ETQS_RX_QUEUE);
6866                 etqs |= IXGBE_ETQS_QUEUE_EN;
6867
6868                 ethertype_filter.ethertype = filter->ether_type;
6869                 ethertype_filter.etqf = etqf;
6870                 ethertype_filter.etqs = etqs;
6871                 ethertype_filter.conf = FALSE;
6872                 ret = ixgbe_ethertype_filter_insert(filter_info,
6873                                                     &ethertype_filter);
6874                 if (ret < 0) {
6875                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6876                         return -ENOSPC;
6877                 }
6878         } else {
6879                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6880                 if (ret < 0)
6881                         return -ENOSYS;
6882         }
6883         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6884         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6885         IXGBE_WRITE_FLUSH(hw);
6886
6887         return 0;
6888 }
6889
6890 static int
6891 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6892                         struct rte_eth_ethertype_filter *filter)
6893 {
6894         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6895         struct ixgbe_filter_info *filter_info =
6896                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6897         uint32_t etqf, etqs;
6898         int ret;
6899
6900         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6901         if (ret < 0) {
6902                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6903                             filter->ether_type);
6904                 return -ENOENT;
6905         }
6906
6907         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6908         if (etqf & IXGBE_ETQF_FILTER_EN) {
6909                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6910                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6911                 filter->flags = 0;
6912                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6913                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6914                 return 0;
6915         }
6916         return -ENOENT;
6917 }
6918
6919 /*
6920  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6921  * @dev: pointer to rte_eth_dev structure
6922  * @filter_op:operation will be taken.
6923  * @arg: a pointer to specific structure corresponding to the filter_op
6924  */
6925 static int
6926 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6927                                 enum rte_filter_op filter_op,
6928                                 void *arg)
6929 {
6930         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6931         int ret;
6932
6933         MAC_TYPE_FILTER_SUP(hw->mac.type);
6934
6935         if (filter_op == RTE_ETH_FILTER_NOP)
6936                 return 0;
6937
6938         if (arg == NULL) {
6939                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6940                             filter_op);
6941                 return -EINVAL;
6942         }
6943
6944         switch (filter_op) {
6945         case RTE_ETH_FILTER_ADD:
6946                 ret = ixgbe_add_del_ethertype_filter(dev,
6947                         (struct rte_eth_ethertype_filter *)arg,
6948                         TRUE);
6949                 break;
6950         case RTE_ETH_FILTER_DELETE:
6951                 ret = ixgbe_add_del_ethertype_filter(dev,
6952                         (struct rte_eth_ethertype_filter *)arg,
6953                         FALSE);
6954                 break;
6955         case RTE_ETH_FILTER_GET:
6956                 ret = ixgbe_get_ethertype_filter(dev,
6957                         (struct rte_eth_ethertype_filter *)arg);
6958                 break;
6959         default:
6960                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6961                 ret = -EINVAL;
6962                 break;
6963         }
6964         return ret;
6965 }
6966
6967 static int
6968 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6969                      enum rte_filter_type filter_type,
6970                      enum rte_filter_op filter_op,
6971                      void *arg)
6972 {
6973         int ret = 0;
6974
6975         switch (filter_type) {
6976         case RTE_ETH_FILTER_NTUPLE:
6977                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6978                 break;
6979         case RTE_ETH_FILTER_ETHERTYPE:
6980                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6981                 break;
6982         case RTE_ETH_FILTER_SYN:
6983                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6984                 break;
6985         case RTE_ETH_FILTER_FDIR:
6986                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6987                 break;
6988         case RTE_ETH_FILTER_L2_TUNNEL:
6989                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6990                 break;
6991         case RTE_ETH_FILTER_GENERIC:
6992                 if (filter_op != RTE_ETH_FILTER_GET)
6993                         return -EINVAL;
6994                 *(const void **)arg = &ixgbe_flow_ops;
6995                 break;
6996         default:
6997                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6998                                                         filter_type);
6999                 ret = -EINVAL;
7000                 break;
7001         }
7002
7003         return ret;
7004 }
7005
7006 static u8 *
7007 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
7008                         u8 **mc_addr_ptr, u32 *vmdq)
7009 {
7010         u8 *mc_addr;
7011
7012         *vmdq = 0;
7013         mc_addr = *mc_addr_ptr;
7014         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
7015         return mc_addr;
7016 }
7017
7018 static int
7019 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
7020                           struct rte_ether_addr *mc_addr_set,
7021                           uint32_t nb_mc_addr)
7022 {
7023         struct ixgbe_hw *hw;
7024         u8 *mc_addr_list;
7025
7026         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7027         mc_addr_list = (u8 *)mc_addr_set;
7028         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
7029                                          ixgbe_dev_addr_list_itr, TRUE);
7030 }
7031
7032 static uint64_t
7033 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
7034 {
7035         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7036         uint64_t systime_cycles;
7037
7038         switch (hw->mac.type) {
7039         case ixgbe_mac_X550:
7040         case ixgbe_mac_X550EM_x:
7041         case ixgbe_mac_X550EM_a:
7042                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
7043                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7044                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7045                                 * NSEC_PER_SEC;
7046                 break;
7047         default:
7048                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7049                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7050                                 << 32;
7051         }
7052
7053         return systime_cycles;
7054 }
7055
7056 static uint64_t
7057 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7058 {
7059         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7060         uint64_t rx_tstamp_cycles;
7061
7062         switch (hw->mac.type) {
7063         case ixgbe_mac_X550:
7064         case ixgbe_mac_X550EM_x:
7065         case ixgbe_mac_X550EM_a:
7066                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7067                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7068                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7069                                 * NSEC_PER_SEC;
7070                 break;
7071         default:
7072                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7073                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7074                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7075                                 << 32;
7076         }
7077
7078         return rx_tstamp_cycles;
7079 }
7080
7081 static uint64_t
7082 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7083 {
7084         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7085         uint64_t tx_tstamp_cycles;
7086
7087         switch (hw->mac.type) {
7088         case ixgbe_mac_X550:
7089         case ixgbe_mac_X550EM_x:
7090         case ixgbe_mac_X550EM_a:
7091                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7092                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7093                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7094                                 * NSEC_PER_SEC;
7095                 break;
7096         default:
7097                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7098                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7099                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7100                                 << 32;
7101         }
7102
7103         return tx_tstamp_cycles;
7104 }
7105
7106 static void
7107 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7108 {
7109         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7110         struct ixgbe_adapter *adapter = dev->data->dev_private;
7111         struct rte_eth_link link;
7112         uint32_t incval = 0;
7113         uint32_t shift = 0;
7114
7115         /* Get current link speed. */
7116         ixgbe_dev_link_update(dev, 1);
7117         rte_eth_linkstatus_get(dev, &link);
7118
7119         switch (link.link_speed) {
7120         case ETH_SPEED_NUM_100M:
7121                 incval = IXGBE_INCVAL_100;
7122                 shift = IXGBE_INCVAL_SHIFT_100;
7123                 break;
7124         case ETH_SPEED_NUM_1G:
7125                 incval = IXGBE_INCVAL_1GB;
7126                 shift = IXGBE_INCVAL_SHIFT_1GB;
7127                 break;
7128         case ETH_SPEED_NUM_10G:
7129         default:
7130                 incval = IXGBE_INCVAL_10GB;
7131                 shift = IXGBE_INCVAL_SHIFT_10GB;
7132                 break;
7133         }
7134
7135         switch (hw->mac.type) {
7136         case ixgbe_mac_X550:
7137         case ixgbe_mac_X550EM_x:
7138         case ixgbe_mac_X550EM_a:
7139                 /* Independent of link speed. */
7140                 incval = 1;
7141                 /* Cycles read will be interpreted as ns. */
7142                 shift = 0;
7143                 /* Fall-through */
7144         case ixgbe_mac_X540:
7145                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7146                 break;
7147         case ixgbe_mac_82599EB:
7148                 incval >>= IXGBE_INCVAL_SHIFT_82599;
7149                 shift -= IXGBE_INCVAL_SHIFT_82599;
7150                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7151                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7152                 break;
7153         default:
7154                 /* Not supported. */
7155                 return;
7156         }
7157
7158         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7159         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7160         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7161
7162         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7163         adapter->systime_tc.cc_shift = shift;
7164         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7165
7166         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7167         adapter->rx_tstamp_tc.cc_shift = shift;
7168         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7169
7170         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7171         adapter->tx_tstamp_tc.cc_shift = shift;
7172         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7173 }
7174
7175 static int
7176 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7177 {
7178         struct ixgbe_adapter *adapter = dev->data->dev_private;
7179
7180         adapter->systime_tc.nsec += delta;
7181         adapter->rx_tstamp_tc.nsec += delta;
7182         adapter->tx_tstamp_tc.nsec += delta;
7183
7184         return 0;
7185 }
7186
7187 static int
7188 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7189 {
7190         uint64_t ns;
7191         struct ixgbe_adapter *adapter = dev->data->dev_private;
7192
7193         ns = rte_timespec_to_ns(ts);
7194         /* Set the timecounters to a new value. */
7195         adapter->systime_tc.nsec = ns;
7196         adapter->rx_tstamp_tc.nsec = ns;
7197         adapter->tx_tstamp_tc.nsec = ns;
7198
7199         return 0;
7200 }
7201
7202 static int
7203 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7204 {
7205         uint64_t ns, systime_cycles;
7206         struct ixgbe_adapter *adapter = dev->data->dev_private;
7207
7208         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7209         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7210         *ts = rte_ns_to_timespec(ns);
7211
7212         return 0;
7213 }
7214
7215 static int
7216 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7217 {
7218         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7219         uint32_t tsync_ctl;
7220         uint32_t tsauxc;
7221
7222         /* Stop the timesync system time. */
7223         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7224         /* Reset the timesync system time value. */
7225         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7226         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7227
7228         /* Enable system time for platforms where it isn't on by default. */
7229         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7230         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7231         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7232
7233         ixgbe_start_timecounters(dev);
7234
7235         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7236         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7237                         (RTE_ETHER_TYPE_1588 |
7238                          IXGBE_ETQF_FILTER_EN |
7239                          IXGBE_ETQF_1588));
7240
7241         /* Enable timestamping of received PTP packets. */
7242         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7243         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7244         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7245
7246         /* Enable timestamping of transmitted PTP packets. */
7247         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7248         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7249         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7250
7251         IXGBE_WRITE_FLUSH(hw);
7252
7253         return 0;
7254 }
7255
7256 static int
7257 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7258 {
7259         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7260         uint32_t tsync_ctl;
7261
7262         /* Disable timestamping of transmitted PTP packets. */
7263         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7264         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7265         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7266
7267         /* Disable timestamping of received PTP packets. */
7268         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7269         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7270         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7271
7272         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7273         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7274
7275         /* Stop incrementating the System Time registers. */
7276         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7277
7278         return 0;
7279 }
7280
7281 static int
7282 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7283                                  struct timespec *timestamp,
7284                                  uint32_t flags __rte_unused)
7285 {
7286         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7287         struct ixgbe_adapter *adapter = dev->data->dev_private;
7288         uint32_t tsync_rxctl;
7289         uint64_t rx_tstamp_cycles;
7290         uint64_t ns;
7291
7292         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7293         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7294                 return -EINVAL;
7295
7296         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7297         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7298         *timestamp = rte_ns_to_timespec(ns);
7299
7300         return  0;
7301 }
7302
7303 static int
7304 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7305                                  struct timespec *timestamp)
7306 {
7307         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7308         struct ixgbe_adapter *adapter = dev->data->dev_private;
7309         uint32_t tsync_txctl;
7310         uint64_t tx_tstamp_cycles;
7311         uint64_t ns;
7312
7313         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7314         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7315                 return -EINVAL;
7316
7317         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7318         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7319         *timestamp = rte_ns_to_timespec(ns);
7320
7321         return 0;
7322 }
7323
7324 static int
7325 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7326 {
7327         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7328         int count = 0;
7329         int g_ind = 0;
7330         const struct reg_info *reg_group;
7331         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7332                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7333
7334         while ((reg_group = reg_set[g_ind++]))
7335                 count += ixgbe_regs_group_count(reg_group);
7336
7337         return count;
7338 }
7339
7340 static int
7341 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7342 {
7343         int count = 0;
7344         int g_ind = 0;
7345         const struct reg_info *reg_group;
7346
7347         while ((reg_group = ixgbevf_regs[g_ind++]))
7348                 count += ixgbe_regs_group_count(reg_group);
7349
7350         return count;
7351 }
7352
7353 static int
7354 ixgbe_get_regs(struct rte_eth_dev *dev,
7355               struct rte_dev_reg_info *regs)
7356 {
7357         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7358         uint32_t *data = regs->data;
7359         int g_ind = 0;
7360         int count = 0;
7361         const struct reg_info *reg_group;
7362         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7363                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7364
7365         if (data == NULL) {
7366                 regs->length = ixgbe_get_reg_length(dev);
7367                 regs->width = sizeof(uint32_t);
7368                 return 0;
7369         }
7370
7371         /* Support only full register dump */
7372         if ((regs->length == 0) ||
7373             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7374                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7375                         hw->device_id;
7376                 while ((reg_group = reg_set[g_ind++]))
7377                         count += ixgbe_read_regs_group(dev, &data[count],
7378                                 reg_group);
7379                 return 0;
7380         }
7381
7382         return -ENOTSUP;
7383 }
7384
7385 static int
7386 ixgbevf_get_regs(struct rte_eth_dev *dev,
7387                 struct rte_dev_reg_info *regs)
7388 {
7389         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7390         uint32_t *data = regs->data;
7391         int g_ind = 0;
7392         int count = 0;
7393         const struct reg_info *reg_group;
7394
7395         if (data == NULL) {
7396                 regs->length = ixgbevf_get_reg_length(dev);
7397                 regs->width = sizeof(uint32_t);
7398                 return 0;
7399         }
7400
7401         /* Support only full register dump */
7402         if ((regs->length == 0) ||
7403             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7404                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7405                         hw->device_id;
7406                 while ((reg_group = ixgbevf_regs[g_ind++]))
7407                         count += ixgbe_read_regs_group(dev, &data[count],
7408                                                       reg_group);
7409                 return 0;
7410         }
7411
7412         return -ENOTSUP;
7413 }
7414
7415 static int
7416 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7417 {
7418         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7419
7420         /* Return unit is byte count */
7421         return hw->eeprom.word_size * 2;
7422 }
7423
7424 static int
7425 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7426                 struct rte_dev_eeprom_info *in_eeprom)
7427 {
7428         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7429         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7430         uint16_t *data = in_eeprom->data;
7431         int first, length;
7432
7433         first = in_eeprom->offset >> 1;
7434         length = in_eeprom->length >> 1;
7435         if ((first > hw->eeprom.word_size) ||
7436             ((first + length) > hw->eeprom.word_size))
7437                 return -EINVAL;
7438
7439         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7440
7441         return eeprom->ops.read_buffer(hw, first, length, data);
7442 }
7443
7444 static int
7445 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7446                 struct rte_dev_eeprom_info *in_eeprom)
7447 {
7448         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7449         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7450         uint16_t *data = in_eeprom->data;
7451         int first, length;
7452
7453         first = in_eeprom->offset >> 1;
7454         length = in_eeprom->length >> 1;
7455         if ((first > hw->eeprom.word_size) ||
7456             ((first + length) > hw->eeprom.word_size))
7457                 return -EINVAL;
7458
7459         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7460
7461         return eeprom->ops.write_buffer(hw,  first, length, data);
7462 }
7463
7464 static int
7465 ixgbe_get_module_info(struct rte_eth_dev *dev,
7466                       struct rte_eth_dev_module_info *modinfo)
7467 {
7468         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7469         uint32_t status;
7470         uint8_t sff8472_rev, addr_mode;
7471         bool page_swap = false;
7472
7473         /* Check whether we support SFF-8472 or not */
7474         status = hw->phy.ops.read_i2c_eeprom(hw,
7475                                              IXGBE_SFF_SFF_8472_COMP,
7476                                              &sff8472_rev);
7477         if (status != 0)
7478                 return -EIO;
7479
7480         /* addressing mode is not supported */
7481         status = hw->phy.ops.read_i2c_eeprom(hw,
7482                                              IXGBE_SFF_SFF_8472_SWAP,
7483                                              &addr_mode);
7484         if (status != 0)
7485                 return -EIO;
7486
7487         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7488                 PMD_DRV_LOG(ERR,
7489                             "Address change required to access page 0xA2, "
7490                             "but not supported. Please report the module "
7491                             "type to the driver maintainers.");
7492                 page_swap = true;
7493         }
7494
7495         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7496                 /* We have a SFP, but it does not support SFF-8472 */
7497                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7498                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7499         } else {
7500                 /* We have a SFP which supports a revision of SFF-8472. */
7501                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7502                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7503         }
7504
7505         return 0;
7506 }
7507
7508 static int
7509 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7510                         struct rte_dev_eeprom_info *info)
7511 {
7512         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7513         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7514         uint8_t databyte = 0xFF;
7515         uint8_t *data = info->data;
7516         uint32_t i = 0;
7517
7518         if (info->length == 0)
7519                 return -EINVAL;
7520
7521         for (i = info->offset; i < info->offset + info->length; i++) {
7522                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7523                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7524                 else
7525                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7526
7527                 if (status != 0)
7528                         return -EIO;
7529
7530                 data[i - info->offset] = databyte;
7531         }
7532
7533         return 0;
7534 }
7535
7536 uint16_t
7537 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7538         switch (mac_type) {
7539         case ixgbe_mac_X550:
7540         case ixgbe_mac_X550EM_x:
7541         case ixgbe_mac_X550EM_a:
7542                 return ETH_RSS_RETA_SIZE_512;
7543         case ixgbe_mac_X550_vf:
7544         case ixgbe_mac_X550EM_x_vf:
7545         case ixgbe_mac_X550EM_a_vf:
7546                 return ETH_RSS_RETA_SIZE_64;
7547         case ixgbe_mac_X540_vf:
7548         case ixgbe_mac_82599_vf:
7549                 return 0;
7550         default:
7551                 return ETH_RSS_RETA_SIZE_128;
7552         }
7553 }
7554
7555 uint32_t
7556 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7557         switch (mac_type) {
7558         case ixgbe_mac_X550:
7559         case ixgbe_mac_X550EM_x:
7560         case ixgbe_mac_X550EM_a:
7561                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7562                         return IXGBE_RETA(reta_idx >> 2);
7563                 else
7564                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7565         case ixgbe_mac_X550_vf:
7566         case ixgbe_mac_X550EM_x_vf:
7567         case ixgbe_mac_X550EM_a_vf:
7568                 return IXGBE_VFRETA(reta_idx >> 2);
7569         default:
7570                 return IXGBE_RETA(reta_idx >> 2);
7571         }
7572 }
7573
7574 uint32_t
7575 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7576         switch (mac_type) {
7577         case ixgbe_mac_X550_vf:
7578         case ixgbe_mac_X550EM_x_vf:
7579         case ixgbe_mac_X550EM_a_vf:
7580                 return IXGBE_VFMRQC;
7581         default:
7582                 return IXGBE_MRQC;
7583         }
7584 }
7585
7586 uint32_t
7587 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7588         switch (mac_type) {
7589         case ixgbe_mac_X550_vf:
7590         case ixgbe_mac_X550EM_x_vf:
7591         case ixgbe_mac_X550EM_a_vf:
7592                 return IXGBE_VFRSSRK(i);
7593         default:
7594                 return IXGBE_RSSRK(i);
7595         }
7596 }
7597
7598 bool
7599 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7600         switch (mac_type) {
7601         case ixgbe_mac_82599_vf:
7602         case ixgbe_mac_X540_vf:
7603                 return 0;
7604         default:
7605                 return 1;
7606         }
7607 }
7608
7609 static int
7610 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7611                         struct rte_eth_dcb_info *dcb_info)
7612 {
7613         struct ixgbe_dcb_config *dcb_config =
7614                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7615         struct ixgbe_dcb_tc_config *tc;
7616         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7617         uint8_t nb_tcs;
7618         uint8_t i, j;
7619
7620         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7621                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7622         else
7623                 dcb_info->nb_tcs = 1;
7624
7625         tc_queue = &dcb_info->tc_queue;
7626         nb_tcs = dcb_info->nb_tcs;
7627
7628         if (dcb_config->vt_mode) { /* vt is enabled*/
7629                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7630                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7631                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7632                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7633                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7634                         for (j = 0; j < nb_tcs; j++) {
7635                                 tc_queue->tc_rxq[0][j].base = j;
7636                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7637                                 tc_queue->tc_txq[0][j].base = j;
7638                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7639                         }
7640                 } else {
7641                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7642                                 for (j = 0; j < nb_tcs; j++) {
7643                                         tc_queue->tc_rxq[i][j].base =
7644                                                 i * nb_tcs + j;
7645                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7646                                         tc_queue->tc_txq[i][j].base =
7647                                                 i * nb_tcs + j;
7648                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7649                                 }
7650                         }
7651                 }
7652         } else { /* vt is disabled*/
7653                 struct rte_eth_dcb_rx_conf *rx_conf =
7654                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7655                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7656                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7657                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7658                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7659                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7660                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7661                         }
7662                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7663                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7664                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7665                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7666                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7667                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7668                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7669                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7670                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7671                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7672                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7673                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7674                         }
7675                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7676                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7677                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7678                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7679                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7680                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7681                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7682                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7683                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7684                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7685                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7686                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7687                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7688                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7689                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7690                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7691                 }
7692         }
7693         for (i = 0; i < dcb_info->nb_tcs; i++) {
7694                 tc = &dcb_config->tc_config[i];
7695                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7696         }
7697         return 0;
7698 }
7699
7700 /* Update e-tag ether type */
7701 static int
7702 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7703                             uint16_t ether_type)
7704 {
7705         uint32_t etag_etype;
7706
7707         if (hw->mac.type != ixgbe_mac_X550 &&
7708             hw->mac.type != ixgbe_mac_X550EM_x &&
7709             hw->mac.type != ixgbe_mac_X550EM_a) {
7710                 return -ENOTSUP;
7711         }
7712
7713         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7714         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7715         etag_etype |= ether_type;
7716         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7717         IXGBE_WRITE_FLUSH(hw);
7718
7719         return 0;
7720 }
7721
7722 /* Config l2 tunnel ether type */
7723 static int
7724 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7725                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7726 {
7727         int ret = 0;
7728         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7729         struct ixgbe_l2_tn_info *l2_tn_info =
7730                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7731
7732         if (l2_tunnel == NULL)
7733                 return -EINVAL;
7734
7735         switch (l2_tunnel->l2_tunnel_type) {
7736         case RTE_L2_TUNNEL_TYPE_E_TAG:
7737                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7738                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7739                 break;
7740         default:
7741                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7742                 ret = -EINVAL;
7743                 break;
7744         }
7745
7746         return ret;
7747 }
7748
7749 /* Enable e-tag tunnel */
7750 static int
7751 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7752 {
7753         uint32_t etag_etype;
7754
7755         if (hw->mac.type != ixgbe_mac_X550 &&
7756             hw->mac.type != ixgbe_mac_X550EM_x &&
7757             hw->mac.type != ixgbe_mac_X550EM_a) {
7758                 return -ENOTSUP;
7759         }
7760
7761         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7762         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7763         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7764         IXGBE_WRITE_FLUSH(hw);
7765
7766         return 0;
7767 }
7768
7769 /* Enable l2 tunnel */
7770 static int
7771 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7772                            enum rte_eth_tunnel_type l2_tunnel_type)
7773 {
7774         int ret = 0;
7775         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7776         struct ixgbe_l2_tn_info *l2_tn_info =
7777                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7778
7779         switch (l2_tunnel_type) {
7780         case RTE_L2_TUNNEL_TYPE_E_TAG:
7781                 l2_tn_info->e_tag_en = TRUE;
7782                 ret = ixgbe_e_tag_enable(hw);
7783                 break;
7784         default:
7785                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7786                 ret = -EINVAL;
7787                 break;
7788         }
7789
7790         return ret;
7791 }
7792
7793 /* Disable e-tag tunnel */
7794 static int
7795 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7796 {
7797         uint32_t etag_etype;
7798
7799         if (hw->mac.type != ixgbe_mac_X550 &&
7800             hw->mac.type != ixgbe_mac_X550EM_x &&
7801             hw->mac.type != ixgbe_mac_X550EM_a) {
7802                 return -ENOTSUP;
7803         }
7804
7805         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7806         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7807         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7808         IXGBE_WRITE_FLUSH(hw);
7809
7810         return 0;
7811 }
7812
7813 /* Disable l2 tunnel */
7814 static int
7815 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7816                             enum rte_eth_tunnel_type l2_tunnel_type)
7817 {
7818         int ret = 0;
7819         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7820         struct ixgbe_l2_tn_info *l2_tn_info =
7821                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7822
7823         switch (l2_tunnel_type) {
7824         case RTE_L2_TUNNEL_TYPE_E_TAG:
7825                 l2_tn_info->e_tag_en = FALSE;
7826                 ret = ixgbe_e_tag_disable(hw);
7827                 break;
7828         default:
7829                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7830                 ret = -EINVAL;
7831                 break;
7832         }
7833
7834         return ret;
7835 }
7836
7837 static int
7838 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7839                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7840 {
7841         int ret = 0;
7842         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7843         uint32_t i, rar_entries;
7844         uint32_t rar_low, rar_high;
7845
7846         if (hw->mac.type != ixgbe_mac_X550 &&
7847             hw->mac.type != ixgbe_mac_X550EM_x &&
7848             hw->mac.type != ixgbe_mac_X550EM_a) {
7849                 return -ENOTSUP;
7850         }
7851
7852         rar_entries = ixgbe_get_num_rx_addrs(hw);
7853
7854         for (i = 1; i < rar_entries; i++) {
7855                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7856                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7857                 if ((rar_high & IXGBE_RAH_AV) &&
7858                     (rar_high & IXGBE_RAH_ADTYPE) &&
7859                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7860                      l2_tunnel->tunnel_id)) {
7861                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7862                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7863
7864                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7865
7866                         return ret;
7867                 }
7868         }
7869
7870         return ret;
7871 }
7872
7873 static int
7874 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7875                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7876 {
7877         int ret = 0;
7878         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7879         uint32_t i, rar_entries;
7880         uint32_t rar_low, rar_high;
7881
7882         if (hw->mac.type != ixgbe_mac_X550 &&
7883             hw->mac.type != ixgbe_mac_X550EM_x &&
7884             hw->mac.type != ixgbe_mac_X550EM_a) {
7885                 return -ENOTSUP;
7886         }
7887
7888         /* One entry for one tunnel. Try to remove potential existing entry. */
7889         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7890
7891         rar_entries = ixgbe_get_num_rx_addrs(hw);
7892
7893         for (i = 1; i < rar_entries; i++) {
7894                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7895                 if (rar_high & IXGBE_RAH_AV) {
7896                         continue;
7897                 } else {
7898                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7899                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7900                         rar_low = l2_tunnel->tunnel_id;
7901
7902                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7903                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7904
7905                         return ret;
7906                 }
7907         }
7908
7909         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7910                      " Please remove a rule before adding a new one.");
7911         return -EINVAL;
7912 }
7913
7914 static inline struct ixgbe_l2_tn_filter *
7915 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7916                           struct ixgbe_l2_tn_key *key)
7917 {
7918         int ret;
7919
7920         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7921         if (ret < 0)
7922                 return NULL;
7923
7924         return l2_tn_info->hash_map[ret];
7925 }
7926
7927 static inline int
7928 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7929                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7930 {
7931         int ret;
7932
7933         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7934                                &l2_tn_filter->key);
7935
7936         if (ret < 0) {
7937                 PMD_DRV_LOG(ERR,
7938                             "Failed to insert L2 tunnel filter"
7939                             " to hash table %d!",
7940                             ret);
7941                 return ret;
7942         }
7943
7944         l2_tn_info->hash_map[ret] = l2_tn_filter;
7945
7946         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7947
7948         return 0;
7949 }
7950
7951 static inline int
7952 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7953                           struct ixgbe_l2_tn_key *key)
7954 {
7955         int ret;
7956         struct ixgbe_l2_tn_filter *l2_tn_filter;
7957
7958         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7959
7960         if (ret < 0) {
7961                 PMD_DRV_LOG(ERR,
7962                             "No such L2 tunnel filter to delete %d!",
7963                             ret);
7964                 return ret;
7965         }
7966
7967         l2_tn_filter = l2_tn_info->hash_map[ret];
7968         l2_tn_info->hash_map[ret] = NULL;
7969
7970         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7971         rte_free(l2_tn_filter);
7972
7973         return 0;
7974 }
7975
7976 /* Add l2 tunnel filter */
7977 int
7978 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7979                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7980                                bool restore)
7981 {
7982         int ret;
7983         struct ixgbe_l2_tn_info *l2_tn_info =
7984                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7985         struct ixgbe_l2_tn_key key;
7986         struct ixgbe_l2_tn_filter *node;
7987
7988         if (!restore) {
7989                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7990                 key.tn_id = l2_tunnel->tunnel_id;
7991
7992                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7993
7994                 if (node) {
7995                         PMD_DRV_LOG(ERR,
7996                                     "The L2 tunnel filter already exists!");
7997                         return -EINVAL;
7998                 }
7999
8000                 node = rte_zmalloc("ixgbe_l2_tn",
8001                                    sizeof(struct ixgbe_l2_tn_filter),
8002                                    0);
8003                 if (!node)
8004                         return -ENOMEM;
8005
8006                 rte_memcpy(&node->key,
8007                                  &key,
8008                                  sizeof(struct ixgbe_l2_tn_key));
8009                 node->pool = l2_tunnel->pool;
8010                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
8011                 if (ret < 0) {
8012                         rte_free(node);
8013                         return ret;
8014                 }
8015         }
8016
8017         switch (l2_tunnel->l2_tunnel_type) {
8018         case RTE_L2_TUNNEL_TYPE_E_TAG:
8019                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
8020                 break;
8021         default:
8022                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8023                 ret = -EINVAL;
8024                 break;
8025         }
8026
8027         if ((!restore) && (ret < 0))
8028                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8029
8030         return ret;
8031 }
8032
8033 /* Delete l2 tunnel filter */
8034 int
8035 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
8036                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
8037 {
8038         int ret;
8039         struct ixgbe_l2_tn_info *l2_tn_info =
8040                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8041         struct ixgbe_l2_tn_key key;
8042
8043         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8044         key.tn_id = l2_tunnel->tunnel_id;
8045         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8046         if (ret < 0)
8047                 return ret;
8048
8049         switch (l2_tunnel->l2_tunnel_type) {
8050         case RTE_L2_TUNNEL_TYPE_E_TAG:
8051                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
8052                 break;
8053         default:
8054                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8055                 ret = -EINVAL;
8056                 break;
8057         }
8058
8059         return ret;
8060 }
8061
8062 /**
8063  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8064  * @dev: pointer to rte_eth_dev structure
8065  * @filter_op:operation will be taken.
8066  * @arg: a pointer to specific structure corresponding to the filter_op
8067  */
8068 static int
8069 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8070                                   enum rte_filter_op filter_op,
8071                                   void *arg)
8072 {
8073         int ret;
8074
8075         if (filter_op == RTE_ETH_FILTER_NOP)
8076                 return 0;
8077
8078         if (arg == NULL) {
8079                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8080                             filter_op);
8081                 return -EINVAL;
8082         }
8083
8084         switch (filter_op) {
8085         case RTE_ETH_FILTER_ADD:
8086                 ret = ixgbe_dev_l2_tunnel_filter_add
8087                         (dev,
8088                          (struct rte_eth_l2_tunnel_conf *)arg,
8089                          FALSE);
8090                 break;
8091         case RTE_ETH_FILTER_DELETE:
8092                 ret = ixgbe_dev_l2_tunnel_filter_del
8093                         (dev,
8094                          (struct rte_eth_l2_tunnel_conf *)arg);
8095                 break;
8096         default:
8097                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8098                 ret = -EINVAL;
8099                 break;
8100         }
8101         return ret;
8102 }
8103
8104 static int
8105 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8106 {
8107         int ret = 0;
8108         uint32_t ctrl;
8109         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8110
8111         if (hw->mac.type != ixgbe_mac_X550 &&
8112             hw->mac.type != ixgbe_mac_X550EM_x &&
8113             hw->mac.type != ixgbe_mac_X550EM_a) {
8114                 return -ENOTSUP;
8115         }
8116
8117         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8118         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8119         if (en)
8120                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8121         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8122
8123         return ret;
8124 }
8125
8126 /* Enable l2 tunnel forwarding */
8127 static int
8128 ixgbe_dev_l2_tunnel_forwarding_enable
8129         (struct rte_eth_dev *dev,
8130          enum rte_eth_tunnel_type l2_tunnel_type)
8131 {
8132         struct ixgbe_l2_tn_info *l2_tn_info =
8133                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8134         int ret = 0;
8135
8136         switch (l2_tunnel_type) {
8137         case RTE_L2_TUNNEL_TYPE_E_TAG:
8138                 l2_tn_info->e_tag_fwd_en = TRUE;
8139                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8140                 break;
8141         default:
8142                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8143                 ret = -EINVAL;
8144                 break;
8145         }
8146
8147         return ret;
8148 }
8149
8150 /* Disable l2 tunnel forwarding */
8151 static int
8152 ixgbe_dev_l2_tunnel_forwarding_disable
8153         (struct rte_eth_dev *dev,
8154          enum rte_eth_tunnel_type l2_tunnel_type)
8155 {
8156         struct ixgbe_l2_tn_info *l2_tn_info =
8157                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8158         int ret = 0;
8159
8160         switch (l2_tunnel_type) {
8161         case RTE_L2_TUNNEL_TYPE_E_TAG:
8162                 l2_tn_info->e_tag_fwd_en = FALSE;
8163                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8164                 break;
8165         default:
8166                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8167                 ret = -EINVAL;
8168                 break;
8169         }
8170
8171         return ret;
8172 }
8173
8174 static int
8175 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8176                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
8177                              bool en)
8178 {
8179         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8180         int ret = 0;
8181         uint32_t vmtir, vmvir;
8182         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8183
8184         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8185                 PMD_DRV_LOG(ERR,
8186                             "VF id %u should be less than %u",
8187                             l2_tunnel->vf_id,
8188                             pci_dev->max_vfs);
8189                 return -EINVAL;
8190         }
8191
8192         if (hw->mac.type != ixgbe_mac_X550 &&
8193             hw->mac.type != ixgbe_mac_X550EM_x &&
8194             hw->mac.type != ixgbe_mac_X550EM_a) {
8195                 return -ENOTSUP;
8196         }
8197
8198         if (en)
8199                 vmtir = l2_tunnel->tunnel_id;
8200         else
8201                 vmtir = 0;
8202
8203         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8204
8205         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8206         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8207         if (en)
8208                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8209         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8210
8211         return ret;
8212 }
8213
8214 /* Enable l2 tunnel tag insertion */
8215 static int
8216 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8217                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8218 {
8219         int ret = 0;
8220
8221         switch (l2_tunnel->l2_tunnel_type) {
8222         case RTE_L2_TUNNEL_TYPE_E_TAG:
8223                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8224                 break;
8225         default:
8226                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8227                 ret = -EINVAL;
8228                 break;
8229         }
8230
8231         return ret;
8232 }
8233
8234 /* Disable l2 tunnel tag insertion */
8235 static int
8236 ixgbe_dev_l2_tunnel_insertion_disable
8237         (struct rte_eth_dev *dev,
8238          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8239 {
8240         int ret = 0;
8241
8242         switch (l2_tunnel->l2_tunnel_type) {
8243         case RTE_L2_TUNNEL_TYPE_E_TAG:
8244                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8245                 break;
8246         default:
8247                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8248                 ret = -EINVAL;
8249                 break;
8250         }
8251
8252         return ret;
8253 }
8254
8255 static int
8256 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8257                              bool en)
8258 {
8259         int ret = 0;
8260         uint32_t qde;
8261         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8262
8263         if (hw->mac.type != ixgbe_mac_X550 &&
8264             hw->mac.type != ixgbe_mac_X550EM_x &&
8265             hw->mac.type != ixgbe_mac_X550EM_a) {
8266                 return -ENOTSUP;
8267         }
8268
8269         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8270         if (en)
8271                 qde |= IXGBE_QDE_STRIP_TAG;
8272         else
8273                 qde &= ~IXGBE_QDE_STRIP_TAG;
8274         qde &= ~IXGBE_QDE_READ;
8275         qde |= IXGBE_QDE_WRITE;
8276         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8277
8278         return ret;
8279 }
8280
8281 /* Enable l2 tunnel tag stripping */
8282 static int
8283 ixgbe_dev_l2_tunnel_stripping_enable
8284         (struct rte_eth_dev *dev,
8285          enum rte_eth_tunnel_type l2_tunnel_type)
8286 {
8287         int ret = 0;
8288
8289         switch (l2_tunnel_type) {
8290         case RTE_L2_TUNNEL_TYPE_E_TAG:
8291                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8292                 break;
8293         default:
8294                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8295                 ret = -EINVAL;
8296                 break;
8297         }
8298
8299         return ret;
8300 }
8301
8302 /* Disable l2 tunnel tag stripping */
8303 static int
8304 ixgbe_dev_l2_tunnel_stripping_disable
8305         (struct rte_eth_dev *dev,
8306          enum rte_eth_tunnel_type l2_tunnel_type)
8307 {
8308         int ret = 0;
8309
8310         switch (l2_tunnel_type) {
8311         case RTE_L2_TUNNEL_TYPE_E_TAG:
8312                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8313                 break;
8314         default:
8315                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8316                 ret = -EINVAL;
8317                 break;
8318         }
8319
8320         return ret;
8321 }
8322
8323 /* Enable/disable l2 tunnel offload functions */
8324 static int
8325 ixgbe_dev_l2_tunnel_offload_set
8326         (struct rte_eth_dev *dev,
8327          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8328          uint32_t mask,
8329          uint8_t en)
8330 {
8331         int ret = 0;
8332
8333         if (l2_tunnel == NULL)
8334                 return -EINVAL;
8335
8336         ret = -EINVAL;
8337         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8338                 if (en)
8339                         ret = ixgbe_dev_l2_tunnel_enable(
8340                                 dev,
8341                                 l2_tunnel->l2_tunnel_type);
8342                 else
8343                         ret = ixgbe_dev_l2_tunnel_disable(
8344                                 dev,
8345                                 l2_tunnel->l2_tunnel_type);
8346         }
8347
8348         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8349                 if (en)
8350                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8351                                 dev,
8352                                 l2_tunnel);
8353                 else
8354                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8355                                 dev,
8356                                 l2_tunnel);
8357         }
8358
8359         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8360                 if (en)
8361                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8362                                 dev,
8363                                 l2_tunnel->l2_tunnel_type);
8364                 else
8365                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8366                                 dev,
8367                                 l2_tunnel->l2_tunnel_type);
8368         }
8369
8370         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8371                 if (en)
8372                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8373                                 dev,
8374                                 l2_tunnel->l2_tunnel_type);
8375                 else
8376                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8377                                 dev,
8378                                 l2_tunnel->l2_tunnel_type);
8379         }
8380
8381         return ret;
8382 }
8383
8384 static int
8385 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8386                         uint16_t port)
8387 {
8388         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8389         IXGBE_WRITE_FLUSH(hw);
8390
8391         return 0;
8392 }
8393
8394 /* There's only one register for VxLAN UDP port.
8395  * So, we cannot add several ports. Will update it.
8396  */
8397 static int
8398 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8399                      uint16_t port)
8400 {
8401         if (port == 0) {
8402                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8403                 return -EINVAL;
8404         }
8405
8406         return ixgbe_update_vxlan_port(hw, port);
8407 }
8408
8409 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8410  * UDP port, it must have a value.
8411  * So, will reset it to the original value 0.
8412  */
8413 static int
8414 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8415                      uint16_t port)
8416 {
8417         uint16_t cur_port;
8418
8419         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8420
8421         if (cur_port != port) {
8422                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8423                 return -EINVAL;
8424         }
8425
8426         return ixgbe_update_vxlan_port(hw, 0);
8427 }
8428
8429 /* Add UDP tunneling port */
8430 static int
8431 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8432                               struct rte_eth_udp_tunnel *udp_tunnel)
8433 {
8434         int ret = 0;
8435         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8436
8437         if (hw->mac.type != ixgbe_mac_X550 &&
8438             hw->mac.type != ixgbe_mac_X550EM_x &&
8439             hw->mac.type != ixgbe_mac_X550EM_a) {
8440                 return -ENOTSUP;
8441         }
8442
8443         if (udp_tunnel == NULL)
8444                 return -EINVAL;
8445
8446         switch (udp_tunnel->prot_type) {
8447         case RTE_TUNNEL_TYPE_VXLAN:
8448                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8449                 break;
8450
8451         case RTE_TUNNEL_TYPE_GENEVE:
8452         case RTE_TUNNEL_TYPE_TEREDO:
8453                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8454                 ret = -EINVAL;
8455                 break;
8456
8457         default:
8458                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8459                 ret = -EINVAL;
8460                 break;
8461         }
8462
8463         return ret;
8464 }
8465
8466 /* Remove UDP tunneling port */
8467 static int
8468 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8469                               struct rte_eth_udp_tunnel *udp_tunnel)
8470 {
8471         int ret = 0;
8472         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8473
8474         if (hw->mac.type != ixgbe_mac_X550 &&
8475             hw->mac.type != ixgbe_mac_X550EM_x &&
8476             hw->mac.type != ixgbe_mac_X550EM_a) {
8477                 return -ENOTSUP;
8478         }
8479
8480         if (udp_tunnel == NULL)
8481                 return -EINVAL;
8482
8483         switch (udp_tunnel->prot_type) {
8484         case RTE_TUNNEL_TYPE_VXLAN:
8485                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8486                 break;
8487         case RTE_TUNNEL_TYPE_GENEVE:
8488         case RTE_TUNNEL_TYPE_TEREDO:
8489                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8490                 ret = -EINVAL;
8491                 break;
8492         default:
8493                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8494                 ret = -EINVAL;
8495                 break;
8496         }
8497
8498         return ret;
8499 }
8500
8501 static int
8502 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8503 {
8504         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8505         int ret;
8506
8507         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8508         case IXGBE_SUCCESS:
8509                 ret = 0;
8510                 break;
8511         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8512                 ret = -ENOTSUP;
8513                 break;
8514         default:
8515                 ret = -EAGAIN;
8516                 break;
8517         }
8518
8519         return ret;
8520 }
8521
8522 static int
8523 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8524 {
8525         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8526         int ret;
8527
8528         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8529         case IXGBE_SUCCESS:
8530                 ret = 0;
8531                 break;
8532         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8533                 ret = -ENOTSUP;
8534                 break;
8535         default:
8536                 ret = -EAGAIN;
8537                 break;
8538         }
8539
8540         return ret;
8541 }
8542
8543 static int
8544 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8545 {
8546         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8547         int ret;
8548         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8549
8550         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8551         case IXGBE_SUCCESS:
8552                 ret = 0;
8553                 break;
8554         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8555                 ret = -ENOTSUP;
8556                 break;
8557         default:
8558                 ret = -EAGAIN;
8559                 break;
8560         }
8561
8562         return ret;
8563 }
8564
8565 static int
8566 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8567 {
8568         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8569         int ret;
8570
8571         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8572         case IXGBE_SUCCESS:
8573                 ret = 0;
8574                 break;
8575         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8576                 ret = -ENOTSUP;
8577                 break;
8578         default:
8579                 ret = -EAGAIN;
8580                 break;
8581         }
8582
8583         return ret;
8584 }
8585
8586 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8587 {
8588         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8589         u32 in_msg = 0;
8590
8591         /* peek the message first */
8592         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8593
8594         /* PF reset VF event */
8595         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8596                 /* dummy mbx read to ack pf */
8597                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8598                         return;
8599                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8600                                               NULL);
8601         }
8602 }
8603
8604 static int
8605 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8606 {
8607         uint32_t eicr;
8608         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8609         struct ixgbe_interrupt *intr =
8610                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8611         ixgbevf_intr_disable(dev);
8612
8613         /* read-on-clear nic registers here */
8614         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8615         intr->flags = 0;
8616
8617         /* only one misc vector supported - mailbox */
8618         eicr &= IXGBE_VTEICR_MASK;
8619         if (eicr == IXGBE_MISC_VEC_ID)
8620                 intr->flags |= IXGBE_FLAG_MAILBOX;
8621
8622         return 0;
8623 }
8624
8625 static int
8626 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8627 {
8628         struct ixgbe_interrupt *intr =
8629                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8630
8631         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8632                 ixgbevf_mbx_process(dev);
8633                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8634         }
8635
8636         ixgbevf_intr_enable(dev);
8637
8638         return 0;
8639 }
8640
8641 static void
8642 ixgbevf_dev_interrupt_handler(void *param)
8643 {
8644         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8645
8646         ixgbevf_dev_interrupt_get_status(dev);
8647         ixgbevf_dev_interrupt_action(dev);
8648 }
8649
8650 /**
8651  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8652  *  @hw: pointer to hardware structure
8653  *
8654  *  Stops the transmit data path and waits for the HW to internally empty
8655  *  the Tx security block
8656  **/
8657 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8658 {
8659 #define IXGBE_MAX_SECTX_POLL 40
8660
8661         int i;
8662         int sectxreg;
8663
8664         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8665         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8666         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8667         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8668                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8669                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8670                         break;
8671                 /* Use interrupt-safe sleep just in case */
8672                 usec_delay(1000);
8673         }
8674
8675         /* For informational purposes only */
8676         if (i >= IXGBE_MAX_SECTX_POLL)
8677                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8678                          "path fully disabled.  Continuing with init.");
8679
8680         return IXGBE_SUCCESS;
8681 }
8682
8683 /**
8684  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8685  *  @hw: pointer to hardware structure
8686  *
8687  *  Enables the transmit data path.
8688  **/
8689 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8690 {
8691         uint32_t sectxreg;
8692
8693         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8694         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8695         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8696         IXGBE_WRITE_FLUSH(hw);
8697
8698         return IXGBE_SUCCESS;
8699 }
8700
8701 /* restore n-tuple filter */
8702 static inline void
8703 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8704 {
8705         struct ixgbe_filter_info *filter_info =
8706                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8707         struct ixgbe_5tuple_filter *node;
8708
8709         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8710                 ixgbe_inject_5tuple_filter(dev, node);
8711         }
8712 }
8713
8714 /* restore ethernet type filter */
8715 static inline void
8716 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8717 {
8718         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8719         struct ixgbe_filter_info *filter_info =
8720                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8721         int i;
8722
8723         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8724                 if (filter_info->ethertype_mask & (1 << i)) {
8725                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8726                                         filter_info->ethertype_filters[i].etqf);
8727                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8728                                         filter_info->ethertype_filters[i].etqs);
8729                         IXGBE_WRITE_FLUSH(hw);
8730                 }
8731         }
8732 }
8733
8734 /* restore SYN filter */
8735 static inline void
8736 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8737 {
8738         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8739         struct ixgbe_filter_info *filter_info =
8740                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8741         uint32_t synqf;
8742
8743         synqf = filter_info->syn_info;
8744
8745         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8746                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8747                 IXGBE_WRITE_FLUSH(hw);
8748         }
8749 }
8750
8751 /* restore L2 tunnel filter */
8752 static inline void
8753 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8754 {
8755         struct ixgbe_l2_tn_info *l2_tn_info =
8756                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8757         struct ixgbe_l2_tn_filter *node;
8758         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8759
8760         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8761                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8762                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8763                 l2_tn_conf.pool           = node->pool;
8764                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8765         }
8766 }
8767
8768 /* restore rss filter */
8769 static inline void
8770 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8771 {
8772         struct ixgbe_filter_info *filter_info =
8773                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8774
8775         if (filter_info->rss_info.conf.queue_num)
8776                 ixgbe_config_rss_filter(dev,
8777                         &filter_info->rss_info, TRUE);
8778 }
8779
8780 static int
8781 ixgbe_filter_restore(struct rte_eth_dev *dev)
8782 {
8783         ixgbe_ntuple_filter_restore(dev);
8784         ixgbe_ethertype_filter_restore(dev);
8785         ixgbe_syn_filter_restore(dev);
8786         ixgbe_fdir_filter_restore(dev);
8787         ixgbe_l2_tn_filter_restore(dev);
8788         ixgbe_rss_filter_restore(dev);
8789
8790         return 0;
8791 }
8792
8793 static void
8794 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8795 {
8796         struct ixgbe_l2_tn_info *l2_tn_info =
8797                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8798         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8799
8800         if (l2_tn_info->e_tag_en)
8801                 (void)ixgbe_e_tag_enable(hw);
8802
8803         if (l2_tn_info->e_tag_fwd_en)
8804                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8805
8806         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8807 }
8808
8809 /* remove all the n-tuple filters */
8810 void
8811 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8812 {
8813         struct ixgbe_filter_info *filter_info =
8814                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8815         struct ixgbe_5tuple_filter *p_5tuple;
8816
8817         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8818                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8819 }
8820
8821 /* remove all the ether type filters */
8822 void
8823 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8824 {
8825         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8826         struct ixgbe_filter_info *filter_info =
8827                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8828         int i;
8829
8830         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8831                 if (filter_info->ethertype_mask & (1 << i) &&
8832                     !filter_info->ethertype_filters[i].conf) {
8833                         (void)ixgbe_ethertype_filter_remove(filter_info,
8834                                                             (uint8_t)i);
8835                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8836                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8837                         IXGBE_WRITE_FLUSH(hw);
8838                 }
8839         }
8840 }
8841
8842 /* remove the SYN filter */
8843 void
8844 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8845 {
8846         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8847         struct ixgbe_filter_info *filter_info =
8848                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8849
8850         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8851                 filter_info->syn_info = 0;
8852
8853                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8854                 IXGBE_WRITE_FLUSH(hw);
8855         }
8856 }
8857
8858 /* remove all the L2 tunnel filters */
8859 int
8860 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8861 {
8862         struct ixgbe_l2_tn_info *l2_tn_info =
8863                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8864         struct ixgbe_l2_tn_filter *l2_tn_filter;
8865         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8866         int ret = 0;
8867
8868         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8869                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8870                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8871                 l2_tn_conf.pool           = l2_tn_filter->pool;
8872                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8873                 if (ret < 0)
8874                         return ret;
8875         }
8876
8877         return 0;
8878 }
8879
8880 void
8881 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8882                                 struct ixgbe_macsec_setting *macsec_setting)
8883 {
8884         struct ixgbe_macsec_setting *macsec =
8885                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8886
8887         macsec->offload_en = macsec_setting->offload_en;
8888         macsec->encrypt_en = macsec_setting->encrypt_en;
8889         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8890 }
8891
8892 void
8893 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8894 {
8895         struct ixgbe_macsec_setting *macsec =
8896                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8897
8898         macsec->offload_en = 0;
8899         macsec->encrypt_en = 0;
8900         macsec->replayprotect_en = 0;
8901 }
8902
8903 void
8904 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8905                                 struct ixgbe_macsec_setting *macsec_setting)
8906 {
8907         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8908         uint32_t ctrl;
8909         uint8_t en = macsec_setting->encrypt_en;
8910         uint8_t rp = macsec_setting->replayprotect_en;
8911
8912         /**
8913          * Workaround:
8914          * As no ixgbe_disable_sec_rx_path equivalent is
8915          * implemented for tx in the base code, and we are
8916          * not allowed to modify the base code in DPDK, so
8917          * just call the hand-written one directly for now.
8918          * The hardware support has been checked by
8919          * ixgbe_disable_sec_rx_path().
8920          */
8921         ixgbe_disable_sec_tx_path_generic(hw);
8922
8923         /* Enable Ethernet CRC (required by MACsec offload) */
8924         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8925         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8926         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8927
8928         /* Enable the TX and RX crypto engines */
8929         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8930         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8931         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8932
8933         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8934         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8935         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8936
8937         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8938         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8939         ctrl |= 0x3;
8940         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8941
8942         /* Enable SA lookup */
8943         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8944         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8945         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8946                      IXGBE_LSECTXCTRL_AUTH;
8947         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8948         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8949         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8950         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8951
8952         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8953         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8954         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8955         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8956         if (rp)
8957                 ctrl |= IXGBE_LSECRXCTRL_RP;
8958         else
8959                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8960         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8961
8962         /* Start the data paths */
8963         ixgbe_enable_sec_rx_path(hw);
8964         /**
8965          * Workaround:
8966          * As no ixgbe_enable_sec_rx_path equivalent is
8967          * implemented for tx in the base code, and we are
8968          * not allowed to modify the base code in DPDK, so
8969          * just call the hand-written one directly for now.
8970          */
8971         ixgbe_enable_sec_tx_path_generic(hw);
8972 }
8973
8974 void
8975 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
8976 {
8977         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8978         uint32_t ctrl;
8979
8980         /**
8981          * Workaround:
8982          * As no ixgbe_disable_sec_rx_path equivalent is
8983          * implemented for tx in the base code, and we are
8984          * not allowed to modify the base code in DPDK, so
8985          * just call the hand-written one directly for now.
8986          * The hardware support has been checked by
8987          * ixgbe_disable_sec_rx_path().
8988          */
8989         ixgbe_disable_sec_tx_path_generic(hw);
8990
8991         /* Disable the TX and RX crypto engines */
8992         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8993         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8994         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8995
8996         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8997         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8998         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8999
9000         /* Disable SA lookup */
9001         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9002         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9003         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
9004         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9005
9006         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9007         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9008         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
9009         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9010
9011         /* Start the data paths */
9012         ixgbe_enable_sec_rx_path(hw);
9013         /**
9014          * Workaround:
9015          * As no ixgbe_enable_sec_rx_path equivalent is
9016          * implemented for tx in the base code, and we are
9017          * not allowed to modify the base code in DPDK, so
9018          * just call the hand-written one directly for now.
9019          */
9020         ixgbe_enable_sec_tx_path_generic(hw);
9021 }
9022
9023 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
9024 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
9025 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
9026 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
9027 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
9028 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
9029 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
9030                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
9031
9032 RTE_INIT(ixgbe_init_log)
9033 {
9034         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
9035         if (ixgbe_logtype_init >= 0)
9036                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
9037         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
9038         if (ixgbe_logtype_driver >= 0)
9039                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
9040 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
9041         ixgbe_logtype_rx = rte_log_register("pmd.net.ixgbe.rx");
9042         if (ixgbe_logtype_rx >= 0)
9043                 rte_log_set_level(ixgbe_logtype_rx, RTE_LOG_DEBUG);
9044 #endif
9045
9046 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
9047         ixgbe_logtype_tx = rte_log_register("pmd.net.ixgbe.tx");
9048         if (ixgbe_logtype_tx >= 0)
9049                 rte_log_set_level(ixgbe_logtype_tx, RTE_LOG_DEBUG);
9050 #endif
9051
9052 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
9053         ixgbe_logtype_tx_free = rte_log_register("pmd.net.ixgbe.tx_free");
9054         if (ixgbe_logtype_tx_free >= 0)
9055                 rte_log_set_level(ixgbe_logtype_tx_free, RTE_LOG_DEBUG);
9056 #endif
9057 }