drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define NSEC_PER_SEC             1000000000L
 130 #define IXGBE_INCVAL_10GB        0x66666666
 131 #define IXGBE_INCVAL_1GB         0x40000000
 132 #define IXGBE_INCVAL_100         0x50000000
 133 #define IXGBE_INCVAL_SHIFT_10GB  28
 134 #define IXGBE_INCVAL_SHIFT_1GB   24
 135 #define IXGBE_INCVAL_SHIFT_100   21
 136 #define IXGBE_INCVAL_SHIFT_82599 7
 137 #define IXGBE_INCPER_SHIFT_82599 24
 138
 139 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 143 #define DEFAULT_ETAG_ETYPE                     0x893f
 144 #define IXGBE_ETAG_ETYPE                       0x00005084
 145 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 146 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 147 #define IXGBE_RAH_ADTYPE                       0x40000000
 148 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 149 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 152 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 153
 154 enum ixgbevf_xcast_modes {
 155         IXGBEVF_XCAST_MODE_NONE = 0,
 156         IXGBEVF_XCAST_MODE_MULTI,
 157         IXGBEVF_XCAST_MODE_ALLMULTI,
 158 };
 159
 160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 162 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 163 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 164 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 165 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 166 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 167 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 168 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 169 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 171 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 172 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 173                                 int wait_to_complete);
 174 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 175                                 struct rte_eth_stats *stats);
 176 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 177                                 struct rte_eth_xstats *xstats, unsigned n);
 178 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 179                                   struct rte_eth_xstats *xstats, unsigned n);
 180 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 181 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 182 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 183                                              uint16_t queue_id,
 184                                              uint8_t stat_idx,
 185                                              uint8_t is_rx);
 186 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 187                                struct rte_eth_dev_info *dev_info);
 188 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 189 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 190                                  struct rte_eth_dev_info *dev_info);
 191 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 192
 193 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 194                 uint16_t vlan_id, int on);
 195 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 196                                enum rte_vlan_type vlan_type,
 197                                uint16_t tpid_id);
 198 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 199                 uint16_t queue, bool on);
 200 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 201                 int on);
 202 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 203 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 204 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 205 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 206 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 207
 208 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 209 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 210 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 211                                struct rte_eth_fc_conf *fc_conf);
 212 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 215                 struct rte_eth_pfc_conf *pfc_conf);
 216 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 217                         struct rte_eth_rss_reta_entry64 *reta_conf,
 218                         uint16_t reta_size);
 219 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 220                         struct rte_eth_rss_reta_entry64 *reta_conf,
 221                         uint16_t reta_size);
 222 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 223 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 224 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 226 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 227 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 228                 void *param);
 229 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 230 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 231                 uint32_t index, uint32_t pool);
 232 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 233 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 234                                            struct ether_addr *mac_addr);
 235 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 236
 237 /* For Virtual Function support */
 238 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 239 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 240 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 241 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 242 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 243 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 244 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 245 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 246 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 247                 struct rte_eth_stats *stats);
 248 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 249 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 250                 uint16_t vlan_id, int on);
 251 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 252                 uint16_t queue, int on);
 253 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 254 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 255 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 256                                             uint16_t queue_id);
 257 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 258                                              uint16_t queue_id);
 259 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 260                                  uint8_t queue, uint8_t msix_vector);
 261 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 262 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 263 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 264
 265 /* For Eth VMDQ APIs support */
 266 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 267                 ether_addr* mac_addr,uint8_t on);
 268 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 269 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 270                 uint16_t rx_mask, uint8_t on);
 271 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 272 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 273 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 274                 uint64_t pool_mask,uint8_t vlan_on);
 275 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 276                 struct rte_eth_mirror_conf *mirror_conf,
 277                 uint8_t rule_id, uint8_t on);
 278 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 279                 uint8_t rule_id);
 280 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 281                                           uint16_t queue_id);
 282 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 283                                            uint16_t queue_id);
 284 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 285                                uint8_t queue, uint8_t msix_vector);
 286 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 287
 288 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 289                 uint16_t queue_idx, uint16_t tx_rate);
 290 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 291                 uint16_t tx_rate, uint64_t q_msk);
 292
 293 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 294                                  struct ether_addr *mac_addr,
 295                                  uint32_t index, uint32_t pool);
 296 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 297 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 298                                              struct ether_addr *mac_addr);
 299 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 300                         struct rte_eth_syn_filter *filter,
 301                         bool add);
 302 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 303                         struct rte_eth_syn_filter *filter);
 304 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 305                         enum rte_filter_op filter_op,
 306                         void *arg);
 307 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 308                         struct ixgbe_5tuple_filter *filter);
 309 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 310                         struct ixgbe_5tuple_filter *filter);
 311 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 312                         struct rte_eth_ntuple_filter *filter,
 313                         bool add);
 314 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 315                                 enum rte_filter_op filter_op,
 316                                 void *arg);
 317 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 318                         struct rte_eth_ntuple_filter *filter);
 319 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 320                         struct rte_eth_ethertype_filter *filter,
 321                         bool add);
 322 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 323                                 enum rte_filter_op filter_op,
 324                                 void *arg);
 325 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 326                         struct rte_eth_ethertype_filter *filter);
 327 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 328                      enum rte_filter_type filter_type,
 329                      enum rte_filter_op filter_op,
 330                      void *arg);
 331 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 332
 333 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 334                                       struct ether_addr *mc_addr_set,
 335                                       uint32_t nb_mc_addr);
 336 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 337                                    struct rte_eth_dcb_info *dcb_info);
 338
 339 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 340 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 341                             struct rte_dev_reg_info *regs);
 342 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 343 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 344                                 struct rte_dev_eeprom_info *eeprom);
 345 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 346                                 struct rte_dev_eeprom_info *eeprom);
 347
 348 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 349 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 350                                 struct rte_dev_reg_info *regs);
 351
 352 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 354 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 355                                             struct timespec *timestamp,
 356                                             uint32_t flags);
 357 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 358                                             struct timespec *timestamp);
 359 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 360 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 361                                    struct timespec *timestamp);
 362 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 363                                    const struct timespec *timestamp);
 364
 365 static int ixgbe_dev_l2_tunnel_eth_type_conf
 366         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 367 static int ixgbe_dev_l2_tunnel_offload_set
 368         (struct rte_eth_dev *dev,
 369          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 370          uint32_t mask,
 371          uint8_t en);
 372 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 373                                              enum rte_filter_op filter_op,
 374                                              void *arg);
 375
 376 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 377                                          struct rte_eth_udp_tunnel *udp_tunnel);
 378 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 379                                          struct rte_eth_udp_tunnel *udp_tunnel);
 380
 381 /*
 382  * Define VF Stats MACRO for Non "cleared on read" register
 383  */
 384 #define UPDATE_VF_STAT(reg, last, cur)                          \
 385 {                                                               \
 386         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 387         cur += (latest - last) & UINT_MAX;                      \
 388         last = latest;                                          \
 389 }
 390
 391 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 392 {                                                                \
 393         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 394         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 395         u64 latest = ((new_msb << 32) | new_lsb);                \
 396         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 397         last = latest;                                           \
 398 }
 399
 400 #define IXGBE_SET_HWSTRIP(h, q) do{\
 401                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 402                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 403                 (h)->bitmap[idx] |= 1 << bit;\
 404         } while (0)
 405
 406 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 407                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 408                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 409                 (h)->bitmap[idx] &= ~(1 << bit);\
 410         } while (0)
 411
 412 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 413                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 414                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 415                 (r) = (h)->bitmap[idx] >> bit & 1;\
 416         } while (0)
 417
 418 /*
 419  * The set of PCI devices this driver supports
 420  */
 421 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 422
 423 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 424 #include "rte_pci_dev_ids.h"
 425
 426 { .vendor_id = 0, /* sentinel */ },
 427 };
 428
 429
 430 /*
 431  * The set of PCI devices this driver supports (for 82599 VF)
 432  */
 433 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 434
 435 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 436 #include "rte_pci_dev_ids.h"
 437 { .vendor_id = 0, /* sentinel */ },
 438
 439 };
 440
 441 static const struct rte_eth_desc_lim rx_desc_lim = {
 442         .nb_max = IXGBE_MAX_RING_DESC,
 443         .nb_min = IXGBE_MIN_RING_DESC,
 444         .nb_align = IXGBE_RXD_ALIGN,
 445 };
 446
 447 static const struct rte_eth_desc_lim tx_desc_lim = {
 448         .nb_max = IXGBE_MAX_RING_DESC,
 449         .nb_min = IXGBE_MIN_RING_DESC,
 450         .nb_align = IXGBE_TXD_ALIGN,
 451 };
 452
 453 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 454         .dev_configure        = ixgbe_dev_configure,
 455         .dev_start            = ixgbe_dev_start,
 456         .dev_stop             = ixgbe_dev_stop,
 457         .dev_set_link_up    = ixgbe_dev_set_link_up,
 458         .dev_set_link_down  = ixgbe_dev_set_link_down,
 459         .dev_close            = ixgbe_dev_close,
 460         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 461         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 462         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 463         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 464         .link_update          = ixgbe_dev_link_update,
 465         .stats_get            = ixgbe_dev_stats_get,
 466         .xstats_get           = ixgbe_dev_xstats_get,
 467         .stats_reset          = ixgbe_dev_stats_reset,
 468         .xstats_reset         = ixgbe_dev_xstats_reset,
 469         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 470         .dev_infos_get        = ixgbe_dev_info_get,
 471         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 472         .mtu_set              = ixgbe_dev_mtu_set,
 473         .vlan_filter_set      = ixgbe_vlan_filter_set,
 474         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 475         .vlan_offload_set     = ixgbe_vlan_offload_set,
 476         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 477         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 478         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 479         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 480         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 481         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 482         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 483         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 484         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 485         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 486         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 487         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 488         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 489         .dev_led_on           = ixgbe_dev_led_on,
 490         .dev_led_off          = ixgbe_dev_led_off,
 491         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 492         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 493         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 494         .mac_addr_add         = ixgbe_add_rar,
 495         .mac_addr_remove      = ixgbe_remove_rar,
 496         .mac_addr_set         = ixgbe_set_default_mac_addr,
 497         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 498         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 499         .mirror_rule_set      = ixgbe_mirror_rule_set,
 500         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 501         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 502         .set_vf_rx            = ixgbe_set_pool_rx,
 503         .set_vf_tx            = ixgbe_set_pool_tx,
 504         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 505         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 506         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 507         .reta_update          = ixgbe_dev_rss_reta_update,
 508         .reta_query           = ixgbe_dev_rss_reta_query,
 509 #ifdef RTE_NIC_BYPASS
 510         .bypass_init          = ixgbe_bypass_init,
 511         .bypass_state_set     = ixgbe_bypass_state_store,
 512         .bypass_state_show    = ixgbe_bypass_state_show,
 513         .bypass_event_set     = ixgbe_bypass_event_store,
 514         .bypass_event_show    = ixgbe_bypass_event_show,
 515         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 516         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 517         .bypass_ver_show      = ixgbe_bypass_ver_show,
 518         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 519 #endif /* RTE_NIC_BYPASS */
 520         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 521         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 522         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 523         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 524         .rxq_info_get         = ixgbe_rxq_info_get,
 525         .txq_info_get         = ixgbe_txq_info_get,
 526         .timesync_enable      = ixgbe_timesync_enable,
 527         .timesync_disable     = ixgbe_timesync_disable,
 528         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 529         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 530         .get_reg_length       = ixgbe_get_reg_length,
 531         .get_reg              = ixgbe_get_regs,
 532         .get_eeprom_length    = ixgbe_get_eeprom_length,
 533         .get_eeprom           = ixgbe_get_eeprom,
 534         .set_eeprom           = ixgbe_set_eeprom,
 535         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 536         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 537         .timesync_read_time   = ixgbe_timesync_read_time,
 538         .timesync_write_time  = ixgbe_timesync_write_time,
 539         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 540         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 541         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 542         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 543 };
 544
 545 /*
 546  * dev_ops for virtual function, bare necessities for basic vf
 547  * operation have been implemented
 548  */
 549 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 550         .dev_configure        = ixgbevf_dev_configure,
 551         .dev_start            = ixgbevf_dev_start,
 552         .dev_stop             = ixgbevf_dev_stop,
 553         .link_update          = ixgbe_dev_link_update,
 554         .stats_get            = ixgbevf_dev_stats_get,
 555         .xstats_get           = ixgbevf_dev_xstats_get,
 556         .stats_reset          = ixgbevf_dev_stats_reset,
 557         .xstats_reset         = ixgbevf_dev_stats_reset,
 558         .dev_close            = ixgbevf_dev_close,
 559         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 560         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 561         .dev_infos_get        = ixgbevf_dev_info_get,
 562         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 563         .mtu_set              = ixgbevf_dev_set_mtu,
 564         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 565         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 566         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 567         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 568         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 569         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 570         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 571         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 572         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 573         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 574         .mac_addr_add         = ixgbevf_add_mac_addr,
 575         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 576         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 577         .rxq_info_get         = ixgbe_rxq_info_get,
 578         .txq_info_get         = ixgbe_txq_info_get,
 579         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 580         .get_reg_length       = ixgbevf_get_reg_length,
 581         .get_reg              = ixgbevf_get_regs,
 582         .reta_update          = ixgbe_dev_rss_reta_update,
 583         .reta_query           = ixgbe_dev_rss_reta_query,
 584         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 585         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 586 };
 587
 588 /* store statistics names and its offset in stats structure */
 589 struct rte_ixgbe_xstats_name_off {
 590         char name[RTE_ETH_XSTATS_NAME_SIZE];
 591         unsigned offset;
 592 };
 593
 594 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 595         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 596         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 597         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 598         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 599         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 600         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 601         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 602         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 603         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 604         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 605         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 606         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 607         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 608         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 609         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 610                 prc1023)},
 611         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 612                 prc1522)},
 613         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 614         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 615         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 616         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 617         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 618         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 619         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 620         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 621         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 622         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 623         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 624         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 625         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 626         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 627         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 628         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 629         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 630                 ptc1023)},
 631         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 632                 ptc1522)},
 633         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 634         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 635         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 636         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 637
 638         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 639                 fdirustat_add)},
 640         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 641                 fdirustat_remove)},
 642         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 643                 fdirfstat_fadd)},
 644         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 645                 fdirfstat_fremove)},
 646         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 647                 fdirmatch)},
 648         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 649                 fdirmiss)},
 650
 651         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 652         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 653         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 654                 fclast)},
 655         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 656         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 657         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 658         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 659         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 660                 fcoe_noddp)},
 661         {"rx_fcoe_no_direct_data_placement_ext_buff",
 662                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 663
 664         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 665                 lxontxc)},
 666         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 667                 lxonrxc)},
 668         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 669                 lxofftxc)},
 670         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 671                 lxoffrxc)},
 672         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 673 };
 674
 675 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 676                            sizeof(rte_ixgbe_stats_strings[0]))
 677
 678 /* Per-queue statistics */
 679 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 680         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 681         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 682         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 683         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 684 };
 685
 686 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 687                            sizeof(rte_ixgbe_rxq_strings[0]))
 688
 689 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 690         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 691         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 692         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 693                 pxon2offc)},
 694 };
 695
 696 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 697                            sizeof(rte_ixgbe_txq_strings[0]))
 698
 699 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 700         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 701 };
 702
 703 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 704                 sizeof(rte_ixgbevf_stats_strings[0]))
 705
 706 /**
 707  * Atomically reads the link status information from global
 708  * structure rte_eth_dev.
 709  *
 710  * @param dev
 711  *   - Pointer to the structure rte_eth_dev to read from.
 712  *   - Pointer to the buffer to be saved with the link status.
 713  *
 714  * @return
 715  *   - On success, zero.
 716  *   - On failure, negative value.
 717  */
 718 static inline int
 719 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 720                                 struct rte_eth_link *link)
 721 {
 722         struct rte_eth_link *dst = link;
 723         struct rte_eth_link *src = &(dev->data->dev_link);
 724
 725         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 726                                         *(uint64_t *)src) == 0)
 727                 return -1;
 728
 729         return 0;
 730 }
 731
 732 /**
 733  * Atomically writes the link status information into global
 734  * structure rte_eth_dev.
 735  *
 736  * @param dev
 737  *   - Pointer to the structure rte_eth_dev to read from.
 738  *   - Pointer to the buffer to be saved with the link status.
 739  *
 740  * @return
 741  *   - On success, zero.
 742  *   - On failure, negative value.
 743  */
 744 static inline int
 745 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 746                                 struct rte_eth_link *link)
 747 {
 748         struct rte_eth_link *dst = &(dev->data->dev_link);
 749         struct rte_eth_link *src = link;
 750
 751         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 752                                         *(uint64_t *)src) == 0)
 753                 return -1;
 754
 755         return 0;
 756 }
 757
 758 /*
 759  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 760  */
 761 static inline int
 762 ixgbe_is_sfp(struct ixgbe_hw *hw)
 763 {
 764         switch (hw->phy.type) {
 765         case ixgbe_phy_sfp_avago:
 766         case ixgbe_phy_sfp_ftl:
 767         case ixgbe_phy_sfp_intel:
 768         case ixgbe_phy_sfp_unknown:
 769         case ixgbe_phy_sfp_passive_tyco:
 770         case ixgbe_phy_sfp_passive_unknown:
 771                 return 1;
 772         default:
 773                 return 0;
 774         }
 775 }
 776
 777 static inline int32_t
 778 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 779 {
 780         uint32_t ctrl_ext;
 781         int32_t status;
 782
 783         status = ixgbe_reset_hw(hw);
 784
 785         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 786         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 787         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 788         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 789         IXGBE_WRITE_FLUSH(hw);
 790
 791         return status;
 792 }
 793
 794 static inline void
 795 ixgbe_enable_intr(struct rte_eth_dev *dev)
 796 {
 797         struct ixgbe_interrupt *intr =
 798                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 799         struct ixgbe_hw *hw =
 800                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 801
 802         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 803         IXGBE_WRITE_FLUSH(hw);
 804 }
 805
 806 /*
 807  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 808  */
 809 static void
 810 ixgbe_disable_intr(struct ixgbe_hw *hw)
 811 {
 812         PMD_INIT_FUNC_TRACE();
 813
 814         if (hw->mac.type == ixgbe_mac_82598EB) {
 815                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 816         } else {
 817                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 818                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 819                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 820         }
 821         IXGBE_WRITE_FLUSH(hw);
 822 }
 823
 824 /*
 825  * This function resets queue statistics mapping registers.
 826  * From Niantic datasheet, Initialization of Statistics section:
 827  * "...if software requires the queue counters, the RQSMR and TQSM registers
 828  * must be re-programmed following a device reset.
 829  */
 830 static void
 831 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 832 {
 833         uint32_t i;
 834
 835         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 836                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 837                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 838         }
 839 }
 840
 841
 842 static int
 843 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 844                                   uint16_t queue_id,
 845                                   uint8_t stat_idx,
 846                                   uint8_t is_rx)
 847 {
 848 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 849 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 850 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 851
 852         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 853         struct ixgbe_stat_mapping_registers *stat_mappings =
 854                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 855         uint32_t qsmr_mask = 0;
 856         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 857         uint32_t q_map;
 858         uint8_t n, offset;
 859
 860         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 861                 (hw->mac.type != ixgbe_mac_X540) &&
 862                 (hw->mac.type != ixgbe_mac_X550) &&
 863                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 864                 (hw->mac.type != ixgbe_mac_X550EM_a))
 865                 return -ENOSYS;
 866
 867         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 868                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 869                      queue_id, stat_idx);
 870
 871         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 872         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 873                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 874                 return -EIO;
 875         }
 876         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 877
 878         /* Now clear any previous stat_idx set */
 879         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 880         if (!is_rx)
 881                 stat_mappings->tqsm[n] &= ~clearing_mask;
 882         else
 883                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 884
 885         q_map = (uint32_t)stat_idx;
 886         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 887         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 888         if (!is_rx)
 889                 stat_mappings->tqsm[n] |= qsmr_mask;
 890         else
 891                 stat_mappings->rqsmr[n] |= qsmr_mask;
 892
 893         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 894                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 895                      queue_id, stat_idx);
 896         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 897                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 898
 899         /* Now write the mapping in the appropriate register */
 900         if (is_rx) {
 901                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 902                              stat_mappings->rqsmr[n], n);
 903                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 904         }
 905         else {
 906                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 907                              stat_mappings->tqsm[n], n);
 908                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 909         }
 910         return 0;
 911 }
 912
 913 static void
 914 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 915 {
 916         struct ixgbe_stat_mapping_registers *stat_mappings =
 917                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 918         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 919         int i;
 920
 921         /* write whatever was in stat mapping table to the NIC */
 922         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 923                 /* rx */
 924                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 925
 926                 /* tx */
 927                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 928         }
 929 }
 930
 931 static void
 932 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 933 {
 934         uint8_t i;
 935         struct ixgbe_dcb_tc_config *tc;
 936         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 937
 938         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 939         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 940         for (i = 0; i < dcb_max_tc; i++) {
 941                 tc = &dcb_config->tc_config[i];
 942                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 943                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 944                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 945                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 946                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 947                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 948                 tc->pfc = ixgbe_dcb_pfc_disabled;
 949         }
 950
 951         /* Initialize default user to priority mapping, UPx->TC0 */
 952         tc = &dcb_config->tc_config[0];
 953         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 954         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 955         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 956                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 957                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 958         }
 959         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 960         dcb_config->pfc_mode_enable = false;
 961         dcb_config->vt_mode = true;
 962         dcb_config->round_robin_enable = false;
 963         /* support all DCB capabilities in 82599 */
 964         dcb_config->support.capabilities = 0xFF;
 965
 966         /*we only support 4 Tcs for X540, X550 */
 967         if (hw->mac.type == ixgbe_mac_X540 ||
 968                 hw->mac.type == ixgbe_mac_X550 ||
 969                 hw->mac.type == ixgbe_mac_X550EM_x ||
 970                 hw->mac.type == ixgbe_mac_X550EM_a) {
 971                 dcb_config->num_tcs.pg_tcs = 4;
 972                 dcb_config->num_tcs.pfc_tcs = 4;
 973         }
 974 }
 975
 976 /*
 977  * Ensure that all locks are released before first NVM or PHY access
 978  */
 979 static void
 980 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 981 {
 982         uint16_t mask;
 983
 984         /*
 985          * Phy lock should not fail in this early stage. If this is the case,
 986          * it is due to an improper exit of the application.
 987          * So force the release of the faulty lock. Release of common lock
 988          * is done automatically by swfw_sync function.
 989          */
 990         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 991         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 992                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 993         }
 994         ixgbe_release_swfw_semaphore(hw, mask);
 995
 996         /*
 997          * These ones are more tricky since they are common to all ports; but
 998          * swfw_sync retries last long enough (1s) to be almost sure that if
 999          * lock can not be taken it is due to an improper lock of the
1000          * semaphore.
1001          */
1002         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1003         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1004                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1005         }
1006         ixgbe_release_swfw_semaphore(hw, mask);
1007 }
1008
1009 /*
1010  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1011  * It returns 0 on success.
1012  */
1013 static int
1014 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1015 {
1016         struct rte_pci_device *pci_dev;
1017         struct ixgbe_hw *hw =
1018                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1019         struct ixgbe_vfta * shadow_vfta =
1020                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1021         struct ixgbe_hwstrip *hwstrip =
1022                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1023         struct ixgbe_dcb_config *dcb_config =
1024                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1025         struct ixgbe_filter_info *filter_info =
1026                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1027         uint32_t ctrl_ext;
1028         uint16_t csum;
1029         int diag, i;
1030
1031         PMD_INIT_FUNC_TRACE();
1032
1033         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1034         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1035         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1036
1037         /*
1038          * For secondary processes, we don't initialise any further as primary
1039          * has already done this work. Only check we don't need a different
1040          * RX and TX function.
1041          */
1042         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1043                 struct ixgbe_tx_queue *txq;
1044                 /* TX queue function in primary, set by last queue initialized
1045                  * Tx queue may not initialized by primary process */
1046                 if (eth_dev->data->tx_queues) {
1047                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1048                         ixgbe_set_tx_function(eth_dev, txq);
1049                 } else {
1050                         /* Use default TX function if we get here */
1051                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1052                                              "Using default TX function.");
1053                 }
1054
1055                 ixgbe_set_rx_function(eth_dev);
1056
1057                 return 0;
1058         }
1059         pci_dev = eth_dev->pci_dev;
1060
1061         rte_eth_copy_pci_info(eth_dev, pci_dev);
1062
1063         /* Vendor and Device ID need to be set before init of shared code */
1064         hw->device_id = pci_dev->id.device_id;
1065         hw->vendor_id = pci_dev->id.vendor_id;
1066         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1067         hw->allow_unsupported_sfp = 1;
1068
1069         /* Initialize the shared code (base driver) */
1070 #ifdef RTE_NIC_BYPASS
1071         diag = ixgbe_bypass_init_shared_code(hw);
1072 #else
1073         diag = ixgbe_init_shared_code(hw);
1074 #endif /* RTE_NIC_BYPASS */
1075
1076         if (diag != IXGBE_SUCCESS) {
1077                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1078                 return -EIO;
1079         }
1080
1081         /* pick up the PCI bus settings for reporting later */
1082         ixgbe_get_bus_info(hw);
1083
1084         /* Unlock any pending hardware semaphore */
1085         ixgbe_swfw_lock_reset(hw);
1086
1087         /* Initialize DCB configuration*/
1088         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1089         ixgbe_dcb_init(hw,dcb_config);
1090         /* Get Hardware Flow Control setting */
1091         hw->fc.requested_mode = ixgbe_fc_full;
1092         hw->fc.current_mode = ixgbe_fc_full;
1093         hw->fc.pause_time = IXGBE_FC_PAUSE;
1094         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1095                 hw->fc.low_water[i] = IXGBE_FC_LO;
1096                 hw->fc.high_water[i] = IXGBE_FC_HI;
1097         }
1098         hw->fc.send_xon = 1;
1099
1100         /* Make sure we have a good EEPROM before we read from it */
1101         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1102         if (diag != IXGBE_SUCCESS) {
1103                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1104                 return -EIO;
1105         }
1106
1107 #ifdef RTE_NIC_BYPASS
1108         diag = ixgbe_bypass_init_hw(hw);
1109 #else
1110         diag = ixgbe_init_hw(hw);
1111 #endif /* RTE_NIC_BYPASS */
1112
1113         /*
1114          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1115          * is called too soon after the kernel driver unbinding/binding occurs.
1116          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1117          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1118          * also called. See ixgbe_identify_phy_82599(). The reason for the
1119          * failure is not known, and only occuts when virtualisation features
1120          * are disabled in the bios. A delay of 100ms  was found to be enough by
1121          * trial-and-error, and is doubled to be safe.
1122          */
1123         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1124                 rte_delay_ms(200);
1125                 diag = ixgbe_init_hw(hw);
1126         }
1127
1128         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1129                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1130                     "LOM.  Please be aware there may be issues associated "
1131                     "with your hardware.");
1132                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1133                     "please contact your Intel or hardware representative "
1134                     "who provided you with this hardware.");
1135         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1136                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1137         if (diag) {
1138                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1139                 return -EIO;
1140         }
1141
1142         /* Reset the hw statistics */
1143         ixgbe_dev_stats_reset(eth_dev);
1144
1145         /* disable interrupt */
1146         ixgbe_disable_intr(hw);
1147
1148         /* reset mappings for queue statistics hw counters*/
1149         ixgbe_reset_qstat_mappings(hw);
1150
1151         /* Allocate memory for storing MAC addresses */
1152         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1153                         hw->mac.num_rar_entries, 0);
1154         if (eth_dev->data->mac_addrs == NULL) {
1155                 PMD_INIT_LOG(ERR,
1156                         "Failed to allocate %u bytes needed to store "
1157                         "MAC addresses",
1158                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1159                 return -ENOMEM;
1160         }
1161         /* Copy the permanent MAC address */
1162         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1163                         &eth_dev->data->mac_addrs[0]);
1164
1165         /* Allocate memory for storing hash filter MAC addresses */
1166         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1167                         IXGBE_VMDQ_NUM_UC_MAC, 0);
1168         if (eth_dev->data->hash_mac_addrs == NULL) {
1169                 PMD_INIT_LOG(ERR,
1170                         "Failed to allocate %d bytes needed to store MAC addresses",
1171                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1172                 return -ENOMEM;
1173         }
1174
1175         /* initialize the vfta */
1176         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1177
1178         /* initialize the hw strip bitmap*/
1179         memset(hwstrip, 0, sizeof(*hwstrip));
1180
1181         /* initialize PF if max_vfs not zero */
1182         ixgbe_pf_host_init(eth_dev);
1183
1184         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1185         /* let hardware know driver is loaded */
1186         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1187         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1188         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1189         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1190         IXGBE_WRITE_FLUSH(hw);
1191
1192         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1193                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1194                              (int) hw->mac.type, (int) hw->phy.type,
1195                              (int) hw->phy.sfp_type);
1196         else
1197                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1198                              (int) hw->mac.type, (int) hw->phy.type);
1199
1200         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1201                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1202                         pci_dev->id.device_id);
1203
1204         rte_intr_callback_register(&pci_dev->intr_handle,
1205                                    ixgbe_dev_interrupt_handler,
1206                                    (void *)eth_dev);
1207
1208         /* enable uio/vfio intr/eventfd mapping */
1209         rte_intr_enable(&pci_dev->intr_handle);
1210
1211         /* enable support intr */
1212         ixgbe_enable_intr(eth_dev);
1213
1214         /* initialize 5tuple filter list */
1215         TAILQ_INIT(&filter_info->fivetuple_list);
1216         memset(filter_info->fivetuple_mask, 0,
1217                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1218
1219         return 0;
1220 }
1221
1222 static int
1223 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1224 {
1225         struct rte_pci_device *pci_dev;
1226         struct ixgbe_hw *hw;
1227
1228         PMD_INIT_FUNC_TRACE();
1229
1230         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1231                 return -EPERM;
1232
1233         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1234         pci_dev = eth_dev->pci_dev;
1235
1236         if (hw->adapter_stopped == 0)
1237                 ixgbe_dev_close(eth_dev);
1238
1239         eth_dev->dev_ops = NULL;
1240         eth_dev->rx_pkt_burst = NULL;
1241         eth_dev->tx_pkt_burst = NULL;
1242
1243         /* Unlock any pending hardware semaphore */
1244         ixgbe_swfw_lock_reset(hw);
1245
1246         /* disable uio intr before callback unregister */
1247         rte_intr_disable(&(pci_dev->intr_handle));
1248         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1249                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1250
1251         /* uninitialize PF if max_vfs not zero */
1252         ixgbe_pf_host_uninit(eth_dev);
1253
1254         rte_free(eth_dev->data->mac_addrs);
1255         eth_dev->data->mac_addrs = NULL;
1256
1257         rte_free(eth_dev->data->hash_mac_addrs);
1258         eth_dev->data->hash_mac_addrs = NULL;
1259
1260         return 0;
1261 }
1262
1263 /*
1264  * Negotiate mailbox API version with the PF.
1265  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1266  * Then we try to negotiate starting with the most recent one.
1267  * If all negotiation attempts fail, then we will proceed with
1268  * the default one (ixgbe_mbox_api_10).
1269  */
1270 static void
1271 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1272 {
1273         int32_t i;
1274
1275         /* start with highest supported, proceed down */
1276         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1277                 ixgbe_mbox_api_12,
1278                 ixgbe_mbox_api_11,
1279                 ixgbe_mbox_api_10,
1280         };
1281
1282         for (i = 0;
1283                         i != RTE_DIM(sup_ver) &&
1284                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1285                         i++)
1286                 ;
1287 }
1288
1289 static void
1290 generate_random_mac_addr(struct ether_addr *mac_addr)
1291 {
1292         uint64_t random;
1293
1294         /* Set Organizationally Unique Identifier (OUI) prefix. */
1295         mac_addr->addr_bytes[0] = 0x00;
1296         mac_addr->addr_bytes[1] = 0x09;
1297         mac_addr->addr_bytes[2] = 0xC0;
1298         /* Force indication of locally assigned MAC address. */
1299         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1300         /* Generate the last 3 bytes of the MAC address with a random number. */
1301         random = rte_rand();
1302         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1303 }
1304
1305 /*
1306  * Virtual Function device init
1307  */
1308 static int
1309 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1310 {
1311         int diag;
1312         uint32_t tc, tcs;
1313         struct rte_pci_device *pci_dev;
1314         struct ixgbe_hw *hw =
1315                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1316         struct ixgbe_vfta * shadow_vfta =
1317                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1318         struct ixgbe_hwstrip *hwstrip =
1319                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1320         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1321
1322         PMD_INIT_FUNC_TRACE();
1323
1324         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1325         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1326         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1327
1328         /* for secondary processes, we don't initialise any further as primary
1329          * has already done this work. Only check we don't need a different
1330          * RX function */
1331         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1332                 struct ixgbe_tx_queue *txq;
1333                 /* TX queue function in primary, set by last queue initialized
1334                  * Tx queue may not initialized by primary process
1335                  */
1336                 if (eth_dev->data->tx_queues) {
1337                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1338                         ixgbe_set_tx_function(eth_dev, txq);
1339                 } else {
1340                         /* Use default TX function if we get here */
1341                         PMD_INIT_LOG(NOTICE,
1342                                 "No TX queues configured yet. Using default TX function.");
1343                 }
1344
1345                 ixgbe_set_rx_function(eth_dev);
1346
1347                 return 0;
1348         }
1349
1350         pci_dev = eth_dev->pci_dev;
1351
1352         rte_eth_copy_pci_info(eth_dev, pci_dev);
1353
1354         hw->device_id = pci_dev->id.device_id;
1355         hw->vendor_id = pci_dev->id.vendor_id;
1356         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1357
1358         /* initialize the vfta */
1359         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1360
1361         /* initialize the hw strip bitmap*/
1362         memset(hwstrip, 0, sizeof(*hwstrip));
1363
1364         /* Initialize the shared code (base driver) */
1365         diag = ixgbe_init_shared_code(hw);
1366         if (diag != IXGBE_SUCCESS) {
1367                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1368                 return -EIO;
1369         }
1370
1371         /* init_mailbox_params */
1372         hw->mbx.ops.init_params(hw);
1373
1374         /* Reset the hw statistics */
1375         ixgbevf_dev_stats_reset(eth_dev);
1376
1377         /* Disable the interrupts for VF */
1378         ixgbevf_intr_disable(hw);
1379
1380         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1381         diag = hw->mac.ops.reset_hw(hw);
1382
1383         /*
1384          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1385          * the underlying PF driver has not assigned a MAC address to the VF.
1386          * In this case, assign a random MAC address.
1387          */
1388         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1389                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1390                 return diag;
1391         }
1392
1393         /* negotiate mailbox API version to use with the PF. */
1394         ixgbevf_negotiate_api(hw);
1395
1396         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1397         ixgbevf_get_queues(hw, &tcs, &tc);
1398
1399         /* Allocate memory for storing MAC addresses */
1400         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1401                         hw->mac.num_rar_entries, 0);
1402         if (eth_dev->data->mac_addrs == NULL) {
1403                 PMD_INIT_LOG(ERR,
1404                         "Failed to allocate %u bytes needed to store "
1405                         "MAC addresses",
1406                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1407                 return -ENOMEM;
1408         }
1409
1410         /* Generate a random MAC address, if none was assigned by PF. */
1411         if (is_zero_ether_addr(perm_addr)) {
1412                 generate_random_mac_addr(perm_addr);
1413                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1414                 if (diag) {
1415                         rte_free(eth_dev->data->mac_addrs);
1416                         eth_dev->data->mac_addrs = NULL;
1417                         return diag;
1418                 }
1419                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1420                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1421                              "%02x:%02x:%02x:%02x:%02x:%02x",
1422                              perm_addr->addr_bytes[0],
1423                              perm_addr->addr_bytes[1],
1424                              perm_addr->addr_bytes[2],
1425                              perm_addr->addr_bytes[3],
1426                              perm_addr->addr_bytes[4],
1427                              perm_addr->addr_bytes[5]);
1428         }
1429
1430         /* Copy the permanent MAC address */
1431         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1432
1433         /* reset the hardware with the new settings */
1434         diag = hw->mac.ops.start_hw(hw);
1435         switch (diag) {
1436                 case  0:
1437                         break;
1438
1439                 default:
1440                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1441                         return -EIO;
1442         }
1443
1444         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1445                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1446                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1447
1448         return 0;
1449 }
1450
1451 /* Virtual Function device uninit */
1452
1453 static int
1454 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1455 {
1456         struct ixgbe_hw *hw;
1457
1458         PMD_INIT_FUNC_TRACE();
1459
1460         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1461                 return -EPERM;
1462
1463         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1464
1465         if (hw->adapter_stopped == 0)
1466                 ixgbevf_dev_close(eth_dev);
1467
1468         eth_dev->dev_ops = NULL;
1469         eth_dev->rx_pkt_burst = NULL;
1470         eth_dev->tx_pkt_burst = NULL;
1471
1472         /* Disable the interrupts for VF */
1473         ixgbevf_intr_disable(hw);
1474
1475         rte_free(eth_dev->data->mac_addrs);
1476         eth_dev->data->mac_addrs = NULL;
1477
1478         return 0;
1479 }
1480
1481 static struct eth_driver rte_ixgbe_pmd = {
1482         .pci_drv = {
1483                 .name = "rte_ixgbe_pmd",
1484                 .id_table = pci_id_ixgbe_map,
1485                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1486                         RTE_PCI_DRV_DETACHABLE,
1487         },
1488         .eth_dev_init = eth_ixgbe_dev_init,
1489         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1490         .dev_private_size = sizeof(struct ixgbe_adapter),
1491 };
1492
1493 /*
1494  * virtual function driver struct
1495  */
1496 static struct eth_driver rte_ixgbevf_pmd = {
1497         .pci_drv = {
1498                 .name = "rte_ixgbevf_pmd",
1499                 .id_table = pci_id_ixgbevf_map,
1500                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1501         },
1502         .eth_dev_init = eth_ixgbevf_dev_init,
1503         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1504         .dev_private_size = sizeof(struct ixgbe_adapter),
1505 };
1506
1507 /*
1508  * Driver initialization routine.
1509  * Invoked once at EAL init time.
1510  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1511  */
1512 static int
1513 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1514 {
1515         PMD_INIT_FUNC_TRACE();
1516
1517         rte_eth_driver_register(&rte_ixgbe_pmd);
1518         return 0;
1519 }
1520
1521 /*
1522  * VF Driver initialization routine.
1523  * Invoked one at EAL init time.
1524  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1525  */
1526 static int
1527 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1528 {
1529         PMD_INIT_FUNC_TRACE();
1530
1531         rte_eth_driver_register(&rte_ixgbevf_pmd);
1532         return 0;
1533 }
1534
1535 static int
1536 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1537 {
1538         struct ixgbe_hw *hw =
1539                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1540         struct ixgbe_vfta * shadow_vfta =
1541                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1542         uint32_t vfta;
1543         uint32_t vid_idx;
1544         uint32_t vid_bit;
1545
1546         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1547         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1548         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1549         if (on)
1550                 vfta |= vid_bit;
1551         else
1552                 vfta &= ~vid_bit;
1553         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1554
1555         /* update local VFTA copy */
1556         shadow_vfta->vfta[vid_idx] = vfta;
1557
1558         return 0;
1559 }
1560
1561 static void
1562 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1563 {
1564         if (on)
1565                 ixgbe_vlan_hw_strip_enable(dev, queue);
1566         else
1567                 ixgbe_vlan_hw_strip_disable(dev, queue);
1568 }
1569
1570 static int
1571 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1572                     enum rte_vlan_type vlan_type,
1573                     uint16_t tpid)
1574 {
1575         struct ixgbe_hw *hw =
1576                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1577         int ret = 0;
1578
1579         switch (vlan_type) {
1580         case ETH_VLAN_TYPE_INNER:
1581                 /* Only the high 16-bits is valid */
1582                 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1583                 break;
1584         default:
1585                 ret = -EINVAL;
1586                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
1587                 break;
1588         }
1589
1590         return ret;
1591 }
1592
1593 void
1594 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1595 {
1596         struct ixgbe_hw *hw =
1597                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1598         uint32_t vlnctrl;
1599
1600         PMD_INIT_FUNC_TRACE();
1601
1602         /* Filter Table Disable */
1603         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1604         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1605
1606         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1607 }
1608
1609 void
1610 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1611 {
1612         struct ixgbe_hw *hw =
1613                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1614         struct ixgbe_vfta * shadow_vfta =
1615                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1616         uint32_t vlnctrl;
1617         uint16_t i;
1618
1619         PMD_INIT_FUNC_TRACE();
1620
1621         /* Filter Table Enable */
1622         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1623         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1624         vlnctrl |= IXGBE_VLNCTRL_VFE;
1625
1626         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1627
1628         /* write whatever is in local vfta copy */
1629         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1630                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1631 }
1632
1633 static void
1634 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1635 {
1636         struct ixgbe_hwstrip *hwstrip =
1637                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1638
1639         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1640                 return;
1641
1642         if (on)
1643                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1644         else
1645                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1646 }
1647
1648 static void
1649 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1650 {
1651         struct ixgbe_hw *hw =
1652                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1653         uint32_t ctrl;
1654
1655         PMD_INIT_FUNC_TRACE();
1656
1657         if (hw->mac.type == ixgbe_mac_82598EB) {
1658                 /* No queue level support */
1659                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1660                 return;
1661         }
1662         else {
1663                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1664                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1665                 ctrl &= ~IXGBE_RXDCTL_VME;
1666                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1667         }
1668         /* record those setting for HW strip per queue */
1669         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1670 }
1671
1672 static void
1673 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1674 {
1675         struct ixgbe_hw *hw =
1676                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1677         uint32_t ctrl;
1678
1679         PMD_INIT_FUNC_TRACE();
1680
1681         if (hw->mac.type == ixgbe_mac_82598EB) {
1682                 /* No queue level supported */
1683                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1684                 return;
1685         }
1686         else {
1687                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1688                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1689                 ctrl |= IXGBE_RXDCTL_VME;
1690                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1691         }
1692         /* record those setting for HW strip per queue */
1693         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1694 }
1695
1696 void
1697 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1698 {
1699         struct ixgbe_hw *hw =
1700                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1701         uint32_t ctrl;
1702         uint16_t i;
1703
1704         PMD_INIT_FUNC_TRACE();
1705
1706         if (hw->mac.type == ixgbe_mac_82598EB) {
1707                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1708                 ctrl &= ~IXGBE_VLNCTRL_VME;
1709                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1710         }
1711         else {
1712                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1713                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1714                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1715                         ctrl &= ~IXGBE_RXDCTL_VME;
1716                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1717
1718                         /* record those setting for HW strip per queue */
1719                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1720                 }
1721         }
1722 }
1723
1724 void
1725 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1726 {
1727         struct ixgbe_hw *hw =
1728                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1729         uint32_t ctrl;
1730         uint16_t i;
1731
1732         PMD_INIT_FUNC_TRACE();
1733
1734         if (hw->mac.type == ixgbe_mac_82598EB) {
1735                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1736                 ctrl |= IXGBE_VLNCTRL_VME;
1737                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1738         }
1739         else {
1740                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1741                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1742                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1743                         ctrl |= IXGBE_RXDCTL_VME;
1744                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1745
1746                         /* record those setting for HW strip per queue */
1747                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1748                 }
1749         }
1750 }
1751
1752 static void
1753 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1754 {
1755         struct ixgbe_hw *hw =
1756                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1757         uint32_t ctrl;
1758
1759         PMD_INIT_FUNC_TRACE();
1760
1761         /* DMATXCTRL: Geric Double VLAN Disable */
1762         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1763         ctrl &= ~IXGBE_DMATXCTL_GDV;
1764         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1765
1766         /* CTRL_EXT: Global Double VLAN Disable */
1767         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1768         ctrl &= ~IXGBE_EXTENDED_VLAN;
1769         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1770
1771 }
1772
1773 static void
1774 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1775 {
1776         struct ixgbe_hw *hw =
1777                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1778         uint32_t ctrl;
1779
1780         PMD_INIT_FUNC_TRACE();
1781
1782         /* DMATXCTRL: Geric Double VLAN Enable */
1783         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1784         ctrl |= IXGBE_DMATXCTL_GDV;
1785         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1786
1787         /* CTRL_EXT: Global Double VLAN Enable */
1788         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1789         ctrl |= IXGBE_EXTENDED_VLAN;
1790         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1791
1792         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1793         if (hw->mac.type == ixgbe_mac_X550 ||
1794             hw->mac.type == ixgbe_mac_X550EM_x ||
1795             hw->mac.type == ixgbe_mac_X550EM_a) {
1796                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1797                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1798                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1799         }
1800
1801         /*
1802          * VET EXT field in the EXVET register = 0x8100 by default
1803          * So no need to change. Same to VT field of DMATXCTL register
1804          */
1805 }
1806
1807 static void
1808 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1809 {
1810         if (mask & ETH_VLAN_STRIP_MASK) {
1811                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1812                         ixgbe_vlan_hw_strip_enable_all(dev);
1813                 else
1814                         ixgbe_vlan_hw_strip_disable_all(dev);
1815         }
1816
1817         if (mask & ETH_VLAN_FILTER_MASK) {
1818                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1819                         ixgbe_vlan_hw_filter_enable(dev);
1820                 else
1821                         ixgbe_vlan_hw_filter_disable(dev);
1822         }
1823
1824         if (mask & ETH_VLAN_EXTEND_MASK) {
1825                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1826                         ixgbe_vlan_hw_extend_enable(dev);
1827                 else
1828                         ixgbe_vlan_hw_extend_disable(dev);
1829         }
1830 }
1831
1832 static void
1833 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1834 {
1835         struct ixgbe_hw *hw =
1836                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1837         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1838         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1839         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1840         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1841 }
1842
1843 static int
1844 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1845 {
1846         switch (nb_rx_q) {
1847         case 1:
1848         case 2:
1849                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1850                 break;
1851         case 4:
1852                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1853                 break;
1854         default:
1855                 return -EINVAL;
1856         }
1857
1858         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1859         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1860
1861         return 0;
1862 }
1863
1864 static int
1865 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1866 {
1867         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1868         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1869         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1870         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1871
1872         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1873                 /* check multi-queue mode */
1874                 switch (dev_conf->rxmode.mq_mode) {
1875                 case ETH_MQ_RX_VMDQ_DCB:
1876                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1877                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1878                         PMD_INIT_LOG(ERR, "SRIOV active,"
1879                                         " unsupported mq_mode rx %d.",
1880                                         dev_conf->rxmode.mq_mode);
1881                         return -EINVAL;
1882                 case ETH_MQ_RX_RSS:
1883                 case ETH_MQ_RX_VMDQ_RSS:
1884                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1885                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1886                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1887                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1888                                                 " invalid queue number"
1889                                                 " for VMDQ RSS, allowed"
1890                                                 " value are 1, 2 or 4.");
1891                                         return -EINVAL;
1892                                 }
1893                         break;
1894                 case ETH_MQ_RX_VMDQ_ONLY:
1895                 case ETH_MQ_RX_NONE:
1896                         /* if nothing mq mode configure, use default scheme */
1897                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1898                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1899                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1900                         break;
1901                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1902                         /* SRIOV only works in VMDq enable mode */
1903                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1904                                         " wrong mq_mode rx %d.",
1905                                         dev_conf->rxmode.mq_mode);
1906                         return -EINVAL;
1907                 }
1908
1909                 switch (dev_conf->txmode.mq_mode) {
1910                 case ETH_MQ_TX_VMDQ_DCB:
1911                         /* DCB VMDQ in SRIOV mode, not implement yet */
1912                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1913                                         " unsupported VMDQ mq_mode tx %d.",
1914                                         dev_conf->txmode.mq_mode);
1915                         return -EINVAL;
1916                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1917                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1918                         break;
1919                 }
1920
1921                 /* check valid queue number */
1922                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1923                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1924                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1925                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1926                                         " must be less than or equal to %d.",
1927                                         nb_rx_q, nb_tx_q,
1928                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1929                         return -EINVAL;
1930                 }
1931         } else {
1932                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1933                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1934                                           " not supported.");
1935                         return -EINVAL;
1936                 }
1937                 /* check configuration for vmdb+dcb mode */
1938                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1939                         const struct rte_eth_vmdq_dcb_conf *conf;
1940
1941                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1942                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1943                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1944                                 return -EINVAL;
1945                         }
1946                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1947                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1948                                conf->nb_queue_pools == ETH_32_POOLS)) {
1949                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1950                                                 " nb_queue_pools must be %d or %d.",
1951                                                 ETH_16_POOLS, ETH_32_POOLS);
1952                                 return -EINVAL;
1953                         }
1954                 }
1955                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1956                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1957
1958                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1959                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1960                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1961                                 return -EINVAL;
1962                         }
1963                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1964                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1965                                conf->nb_queue_pools == ETH_32_POOLS)) {
1966                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1967                                                 " nb_queue_pools != %d and"
1968                                                 " nb_queue_pools != %d.",
1969                                                 ETH_16_POOLS, ETH_32_POOLS);
1970                                 return -EINVAL;
1971                         }
1972                 }
1973
1974                 /* For DCB mode check our configuration before we go further */
1975                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1976                         const struct rte_eth_dcb_rx_conf *conf;
1977
1978                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1979                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1980                                                  IXGBE_DCB_NB_QUEUES);
1981                                 return -EINVAL;
1982                         }
1983                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1984                         if (!(conf->nb_tcs == ETH_4_TCS ||
1985                                conf->nb_tcs == ETH_8_TCS)) {
1986                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1987                                                 " and nb_tcs != %d.",
1988                                                 ETH_4_TCS, ETH_8_TCS);
1989                                 return -EINVAL;
1990                         }
1991                 }
1992
1993                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1994                         const struct rte_eth_dcb_tx_conf *conf;
1995
1996                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1997                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1998                                                  IXGBE_DCB_NB_QUEUES);
1999                                 return -EINVAL;
2000                         }
2001                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2002                         if (!(conf->nb_tcs == ETH_4_TCS ||
2003                                conf->nb_tcs == ETH_8_TCS)) {
2004                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2005                                                 " and nb_tcs != %d.",
2006                                                 ETH_4_TCS, ETH_8_TCS);
2007                                 return -EINVAL;
2008                         }
2009                 }
2010
2011                 /*
2012                  * When DCB/VT is off, maximum number of queues changes,
2013                  * except for 82598EB, which remains constant.
2014                  */
2015                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2016                                 hw->mac.type != ixgbe_mac_82598EB) {
2017                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2018                                 PMD_INIT_LOG(ERR,
2019                                              "Neither VT nor DCB are enabled, "
2020                                              "nb_tx_q > %d.",
2021                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2022                                 return -EINVAL;
2023                         }
2024                 }
2025         }
2026         return 0;
2027 }
2028
2029 static int
2030 ixgbe_dev_configure(struct rte_eth_dev *dev)
2031 {
2032         struct ixgbe_interrupt *intr =
2033                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2034         struct ixgbe_adapter *adapter =
2035                 (struct ixgbe_adapter *)dev->data->dev_private;
2036         int ret;
2037
2038         PMD_INIT_FUNC_TRACE();
2039         /* multipe queue mode checking */
2040         ret  = ixgbe_check_mq_mode(dev);
2041         if (ret != 0) {
2042                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2043                             ret);
2044                 return ret;
2045         }
2046
2047         /* set flag to update link status after init */
2048         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2049
2050         /*
2051          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2052          * allocation or vector Rx preconditions we will reset it.
2053          */
2054         adapter->rx_bulk_alloc_allowed = true;
2055         adapter->rx_vec_allowed = true;
2056
2057         return 0;
2058 }
2059
2060 static void
2061 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2062 {
2063         struct ixgbe_hw *hw =
2064                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2065         struct ixgbe_interrupt *intr =
2066                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2067         uint32_t gpie;
2068
2069         /* only set up it on X550EM_X */
2070         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2071                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2072                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2073                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2074                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2075                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2076         }
2077 }
2078
2079 /*
2080  * Configure device link speed and setup link.
2081  * It returns 0 on success.
2082  */
2083 static int
2084 ixgbe_dev_start(struct rte_eth_dev *dev)
2085 {
2086         struct ixgbe_hw *hw =
2087                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2088         struct ixgbe_vf_info *vfinfo =
2089                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2090         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2091         uint32_t intr_vector = 0;
2092         int err, link_up = 0, negotiate = 0;
2093         uint32_t speed = 0;
2094         int mask = 0;
2095         int status;
2096         uint16_t vf, idx;
2097         uint32_t *link_speeds;
2098
2099         PMD_INIT_FUNC_TRACE();
2100
2101         /* IXGBE devices don't support:
2102         *    - half duplex (checked afterwards for valid speeds)
2103         *    - fixed speed: TODO implement
2104         */
2105         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2106                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2107                              dev->data->port_id);
2108                 return -EINVAL;
2109         }
2110
2111         /* disable uio/vfio intr/eventfd mapping */
2112         rte_intr_disable(intr_handle);
2113
2114         /* stop adapter */
2115         hw->adapter_stopped = 0;
2116         ixgbe_stop_adapter(hw);
2117
2118         /* reinitialize adapter
2119          * this calls reset and start */
2120         status = ixgbe_pf_reset_hw(hw);
2121         if (status != 0)
2122                 return -1;
2123         hw->mac.ops.start_hw(hw);
2124         hw->mac.get_link_status = true;
2125
2126         /* configure PF module if SRIOV enabled */
2127         ixgbe_pf_host_configure(dev);
2128
2129         ixgbe_dev_phy_intr_setup(dev);
2130
2131         /* check and configure queue intr-vector mapping */
2132         if ((rte_intr_cap_multiple(intr_handle) ||
2133              !RTE_ETH_DEV_SRIOV(dev).active) &&
2134             dev->data->dev_conf.intr_conf.rxq != 0) {
2135                 intr_vector = dev->data->nb_rx_queues;
2136                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2137                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2138                                         IXGBE_MAX_INTR_QUEUE_NUM);
2139                         return -ENOTSUP;
2140                 }
2141                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2142                         return -1;
2143         }
2144
2145         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2146                 intr_handle->intr_vec =
2147                         rte_zmalloc("intr_vec",
2148                                     dev->data->nb_rx_queues * sizeof(int), 0);
2149                 if (intr_handle->intr_vec == NULL) {
2150                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2151                                      " intr_vec\n", dev->data->nb_rx_queues);
2152                         return -ENOMEM;
2153                 }
2154         }
2155
2156         /* confiugre msix for sleep until rx interrupt */
2157         ixgbe_configure_msix(dev);
2158
2159         /* initialize transmission unit */
2160         ixgbe_dev_tx_init(dev);
2161
2162         /* This can fail when allocating mbufs for descriptor rings */
2163         err = ixgbe_dev_rx_init(dev);
2164         if (err) {
2165                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2166                 goto error;
2167         }
2168
2169         err = ixgbe_dev_rxtx_start(dev);
2170         if (err < 0) {
2171                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2172                 goto error;
2173         }
2174
2175         /* Skip link setup if loopback mode is enabled for 82599. */
2176         if (hw->mac.type == ixgbe_mac_82599EB &&
2177                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2178                 goto skip_link_setup;
2179
2180         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2181                 err = hw->mac.ops.setup_sfp(hw);
2182                 if (err)
2183                         goto error;
2184         }
2185
2186         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2187                 /* Turn on the copper */
2188                 ixgbe_set_phy_power(hw, true);
2189         } else {
2190                 /* Turn on the laser */
2191                 ixgbe_enable_tx_laser(hw);
2192         }
2193
2194         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2195         if (err)
2196                 goto error;
2197         dev->data->dev_link.link_status = link_up;
2198
2199         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2200         if (err)
2201                 goto error;
2202
2203         link_speeds = &dev->data->dev_conf.link_speeds;
2204         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2205                         ETH_LINK_SPEED_10G)) {
2206                 PMD_INIT_LOG(ERR, "Invalid link setting");
2207                 goto error;
2208         }
2209
2210         speed = 0x0;
2211         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2212                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2213                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2214                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2215         } else {
2216                 if (*link_speeds & ETH_LINK_SPEED_10G)
2217                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2218                 if (*link_speeds & ETH_LINK_SPEED_1G)
2219                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2220                 if (*link_speeds & ETH_LINK_SPEED_100M)
2221                         speed |= IXGBE_LINK_SPEED_100_FULL;
2222         }
2223
2224         err = ixgbe_setup_link(hw, speed, link_up);
2225         if (err)
2226                 goto error;
2227
2228 skip_link_setup:
2229
2230         if (rte_intr_allow_others(intr_handle)) {
2231                 /* check if lsc interrupt is enabled */
2232                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2233                         ixgbe_dev_lsc_interrupt_setup(dev);
2234         } else {
2235                 rte_intr_callback_unregister(intr_handle,
2236                                              ixgbe_dev_interrupt_handler,
2237                                              (void *)dev);
2238                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2239                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2240                                      " no intr multiplex\n");
2241         }
2242
2243         /* check if rxq interrupt is enabled */
2244         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2245             rte_intr_dp_is_en(intr_handle))
2246                 ixgbe_dev_rxq_interrupt_setup(dev);
2247
2248         /* enable uio/vfio intr/eventfd mapping */
2249         rte_intr_enable(intr_handle);
2250
2251         /* resume enabled intr since hw reset */
2252         ixgbe_enable_intr(dev);
2253
2254         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2255                 ETH_VLAN_EXTEND_MASK;
2256         ixgbe_vlan_offload_set(dev, mask);
2257
2258         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2259                 /* Enable vlan filtering for VMDq */
2260                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2261         }
2262
2263         /* Configure DCB hw */
2264         ixgbe_configure_dcb(dev);
2265
2266         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2267                 err = ixgbe_fdir_configure(dev);
2268                 if (err)
2269                         goto error;
2270         }
2271
2272         /* Restore vf rate limit */
2273         if (vfinfo != NULL) {
2274                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2275                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2276                                 if (vfinfo[vf].tx_rate[idx] != 0)
2277                                         ixgbe_set_vf_rate_limit(dev, vf,
2278                                                 vfinfo[vf].tx_rate[idx],
2279                                                 1 << idx);
2280         }
2281
2282         ixgbe_restore_statistics_mapping(dev);
2283
2284         return 0;
2285
2286 error:
2287         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2288         ixgbe_dev_clear_queues(dev);
2289         return -EIO;
2290 }
2291
2292 /*
2293  * Stop device: disable rx and tx functions to allow for reconfiguring.
2294  */
2295 static void
2296 ixgbe_dev_stop(struct rte_eth_dev *dev)
2297 {
2298         struct rte_eth_link link;
2299         struct ixgbe_hw *hw =
2300                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2301         struct ixgbe_vf_info *vfinfo =
2302                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2303         struct ixgbe_filter_info *filter_info =
2304                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2305         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2306         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2307         int vf;
2308
2309         PMD_INIT_FUNC_TRACE();
2310
2311         /* disable interrupts */
2312         ixgbe_disable_intr(hw);
2313
2314         /* reset the NIC */
2315         ixgbe_pf_reset_hw(hw);
2316         hw->adapter_stopped = 0;
2317
2318         /* stop adapter */
2319         ixgbe_stop_adapter(hw);
2320
2321         for (vf = 0; vfinfo != NULL &&
2322                      vf < dev->pci_dev->max_vfs; vf++)
2323                 vfinfo[vf].clear_to_send = false;
2324
2325         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2326                 /* Turn off the copper */
2327                 ixgbe_set_phy_power(hw, false);
2328         } else {
2329                 /* Turn off the laser */
2330                 ixgbe_disable_tx_laser(hw);
2331         }
2332
2333         ixgbe_dev_clear_queues(dev);
2334
2335         /* Clear stored conf */
2336         dev->data->scattered_rx = 0;
2337         dev->data->lro = 0;
2338
2339         /* Clear recorded link status */
2340         memset(&link, 0, sizeof(link));
2341         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2342
2343         /* Remove all ntuple filters of the device */
2344         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2345              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2346                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2347                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2348                              p_5tuple, entries);
2349                 rte_free(p_5tuple);
2350         }
2351         memset(filter_info->fivetuple_mask, 0,
2352                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2353
2354         if (!rte_intr_allow_others(intr_handle))
2355                 /* resume to the default handler */
2356                 rte_intr_callback_register(intr_handle,
2357                                            ixgbe_dev_interrupt_handler,
2358                                            (void *)dev);
2359
2360         /* Clean datapath event and queue/vec mapping */
2361         rte_intr_efd_disable(intr_handle);
2362         if (intr_handle->intr_vec != NULL) {
2363                 rte_free(intr_handle->intr_vec);
2364                 intr_handle->intr_vec = NULL;
2365         }
2366 }
2367
2368 /*
2369  * Set device link up: enable tx.
2370  */
2371 static int
2372 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2373 {
2374         struct ixgbe_hw *hw =
2375                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2376         if (hw->mac.type == ixgbe_mac_82599EB) {
2377 #ifdef RTE_NIC_BYPASS
2378                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2379                         /* Not suported in bypass mode */
2380                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2381                                      "by device id 0x%x", hw->device_id);
2382                         return -ENOTSUP;
2383                 }
2384 #endif
2385         }
2386
2387         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2388                 /* Turn on the copper */
2389                 ixgbe_set_phy_power(hw, true);
2390         } else {
2391                 /* Turn on the laser */
2392                 ixgbe_enable_tx_laser(hw);
2393         }
2394
2395         return 0;
2396 }
2397
2398 /*
2399  * Set device link down: disable tx.
2400  */
2401 static int
2402 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2403 {
2404         struct ixgbe_hw *hw =
2405                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2406         if (hw->mac.type == ixgbe_mac_82599EB) {
2407 #ifdef RTE_NIC_BYPASS
2408                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2409                         /* Not suported in bypass mode */
2410                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2411                                      "by device id 0x%x", hw->device_id);
2412                         return -ENOTSUP;
2413                 }
2414 #endif
2415         }
2416
2417         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2418                 /* Turn off the copper */
2419                 ixgbe_set_phy_power(hw, false);
2420         } else {
2421                 /* Turn off the laser */
2422                 ixgbe_disable_tx_laser(hw);
2423         }
2424
2425         return 0;
2426 }
2427
2428 /*
2429  * Reest and stop device.
2430  */
2431 static void
2432 ixgbe_dev_close(struct rte_eth_dev *dev)
2433 {
2434         struct ixgbe_hw *hw =
2435                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2436
2437         PMD_INIT_FUNC_TRACE();
2438
2439         ixgbe_pf_reset_hw(hw);
2440
2441         ixgbe_dev_stop(dev);
2442         hw->adapter_stopped = 1;
2443
2444         ixgbe_dev_free_queues(dev);
2445
2446         ixgbe_disable_pcie_master(hw);
2447
2448         /* reprogram the RAR[0] in case user changed it. */
2449         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2450 }
2451
2452 static void
2453 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2454                            struct ixgbe_hw_stats *hw_stats,
2455                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2456                            uint64_t *total_qprc, uint64_t *total_qprdc)
2457 {
2458         uint32_t bprc, lxon, lxoff, total;
2459         uint32_t delta_gprc = 0;
2460         unsigned i;
2461         /* Workaround for RX byte count not including CRC bytes when CRC
2462 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2463          * is disabled.
2464 +        */
2465         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2466                         IXGBE_HLREG0_RXCRCSTRP);
2467
2468         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2469         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2470         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2471         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2472
2473         for (i = 0; i < 8; i++) {
2474                 uint32_t mp;
2475                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2476                 /* global total per queue */
2477                 hw_stats->mpc[i] += mp;
2478                 /* Running comprehensive total for stats display */
2479                 *total_missed_rx += hw_stats->mpc[i];
2480                 if (hw->mac.type == ixgbe_mac_82598EB) {
2481                         hw_stats->rnbc[i] +=
2482                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2483                         hw_stats->pxonrxc[i] +=
2484                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2485                         hw_stats->pxoffrxc[i] +=
2486                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2487                 } else {
2488                         hw_stats->pxonrxc[i] +=
2489                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2490                         hw_stats->pxoffrxc[i] +=
2491                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2492                         hw_stats->pxon2offc[i] +=
2493                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2494                 }
2495                 hw_stats->pxontxc[i] +=
2496                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2497                 hw_stats->pxofftxc[i] +=
2498                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2499         }
2500         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2501                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2502                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2503                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2504
2505                 delta_gprc += delta_qprc;
2506
2507                 hw_stats->qprc[i] += delta_qprc;
2508                 hw_stats->qptc[i] += delta_qptc;
2509
2510                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2511                 hw_stats->qbrc[i] +=
2512                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2513                 if (crc_strip == 0)
2514                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2515
2516                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2517                 hw_stats->qbtc[i] +=
2518                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2519
2520                 hw_stats->qprdc[i] += delta_qprdc;
2521                 *total_qprdc += hw_stats->qprdc[i];
2522
2523                 *total_qprc += hw_stats->qprc[i];
2524                 *total_qbrc += hw_stats->qbrc[i];
2525         }
2526         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2527         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2528         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2529
2530         /*
2531          * An errata states that gprc actually counts good + missed packets:
2532          * Workaround to set gprc to summated queue packet receives
2533          */
2534         hw_stats->gprc = *total_qprc;
2535
2536         if (hw->mac.type != ixgbe_mac_82598EB) {
2537                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2538                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2539                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2540                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2541                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2542                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2543                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2544                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2545         } else {
2546                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2547                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2548                 /* 82598 only has a counter in the high register */
2549                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2550                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2551                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2552         }
2553         uint64_t old_tpr = hw_stats->tpr;
2554
2555         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2556         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2557
2558         if (crc_strip == 0)
2559                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2560
2561         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2562         hw_stats->gptc += delta_gptc;
2563         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2564         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2565
2566         /*
2567          * Workaround: mprc hardware is incorrectly counting
2568          * broadcasts, so for now we subtract those.
2569          */
2570         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2571         hw_stats->bprc += bprc;
2572         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2573         if (hw->mac.type == ixgbe_mac_82598EB)
2574                 hw_stats->mprc -= bprc;
2575
2576         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2577         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2578         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2579         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2580         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2581         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2582
2583         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2584         hw_stats->lxontxc += lxon;
2585         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2586         hw_stats->lxofftxc += lxoff;
2587         total = lxon + lxoff;
2588
2589         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2590         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2591         hw_stats->gptc -= total;
2592         hw_stats->mptc -= total;
2593         hw_stats->ptc64 -= total;
2594         hw_stats->gotc -= total * ETHER_MIN_LEN;
2595
2596         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2597         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2598         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2599         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2600         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2601         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2602         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2603         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2604         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2605         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2606         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2607         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2608         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2609         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2610         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2611         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2612         /* Only read FCOE on 82599 */
2613         if (hw->mac.type != ixgbe_mac_82598EB) {
2614                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2615                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2616                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2617                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2618                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2619         }
2620
2621         /* Flow Director Stats registers */
2622         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2623         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2624 }
2625
2626 /*
2627  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2628  */
2629 static void
2630 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2631 {
2632         struct ixgbe_hw *hw =
2633                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2634         struct ixgbe_hw_stats *hw_stats =
2635                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2636         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2637         unsigned i;
2638
2639         total_missed_rx = 0;
2640         total_qbrc = 0;
2641         total_qprc = 0;
2642         total_qprdc = 0;
2643
2644         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2645                         &total_qprc, &total_qprdc);
2646
2647         if (stats == NULL)
2648                 return;
2649
2650         /* Fill out the rte_eth_stats statistics structure */
2651         stats->ipackets = total_qprc;
2652         stats->ibytes = total_qbrc;
2653         stats->opackets = hw_stats->gptc;
2654         stats->obytes = hw_stats->gotc;
2655
2656         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2657                 stats->q_ipackets[i] = hw_stats->qprc[i];
2658                 stats->q_opackets[i] = hw_stats->qptc[i];
2659                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2660                 stats->q_obytes[i] = hw_stats->qbtc[i];
2661                 stats->q_errors[i] = hw_stats->qprdc[i];
2662         }
2663
2664         /* Rx Errors */
2665         stats->imissed  = total_missed_rx;
2666         stats->ierrors  = hw_stats->crcerrs +
2667                           hw_stats->mspdc +
2668                           hw_stats->rlec +
2669                           hw_stats->ruc +
2670                           hw_stats->roc +
2671                           hw_stats->illerrc +
2672                           hw_stats->errbc +
2673                           hw_stats->rfc +
2674                           hw_stats->fccrc +
2675                           hw_stats->fclast;
2676
2677         /* Tx Errors */
2678         stats->oerrors  = 0;
2679 }
2680
2681 static void
2682 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2683 {
2684         struct ixgbe_hw_stats *stats =
2685                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2686
2687         /* HW registers are cleared on read */
2688         ixgbe_dev_stats_get(dev, NULL);
2689
2690         /* Reset software totals */
2691         memset(stats, 0, sizeof(*stats));
2692 }
2693
2694 /* This function calculates the number of xstats based on the current config */
2695 static unsigned
2696 ixgbe_xstats_calc_num(void) {
2697         return IXGBE_NB_HW_STATS + (IXGBE_NB_RXQ_PRIO_STATS * 8) +
2698                 (IXGBE_NB_TXQ_PRIO_STATS * 8);
2699 }
2700
2701 static int
2702 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2703                                          unsigned n)
2704 {
2705         struct ixgbe_hw *hw =
2706                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2707         struct ixgbe_hw_stats *hw_stats =
2708                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2709         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2710         unsigned i, stat, count = 0;
2711
2712         count = ixgbe_xstats_calc_num();
2713
2714         if (n < count)
2715                 return count;
2716
2717         total_missed_rx = 0;
2718         total_qbrc = 0;
2719         total_qprc = 0;
2720         total_qprdc = 0;
2721
2722         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2723                                    &total_qprc, &total_qprdc);
2724
2725         /* If this is a reset xstats is NULL, and we have cleared the
2726          * registers by reading them.
2727          */
2728         if (!xstats)
2729                 return 0;
2730
2731         /* Extended stats from ixgbe_hw_stats */
2732         count = 0;
2733         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2734                 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2735                          rte_ixgbe_stats_strings[i].name);
2736                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2737                                 rte_ixgbe_stats_strings[i].offset);
2738                 count++;
2739         }
2740
2741         /* RX Priority Stats */
2742         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2743                 for (i = 0; i < 8; i++) {
2744                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2745                                  "rx_priority%u_%s", i,
2746                                  rte_ixgbe_rxq_strings[stat].name);
2747                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2748                                         rte_ixgbe_rxq_strings[stat].offset +
2749                                         (sizeof(uint64_t) * i));
2750                         count++;
2751                 }
2752         }
2753
2754         /* TX Priority Stats */
2755         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2756                 for (i = 0; i < 8; i++) {
2757                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2758                                  "tx_priority%u_%s", i,
2759                                  rte_ixgbe_txq_strings[stat].name);
2760                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2761                                         rte_ixgbe_txq_strings[stat].offset +
2762                                         (sizeof(uint64_t) * i));
2763                         count++;
2764                 }
2765         }
2766
2767         return count;
2768 }
2769
2770 static void
2771 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2772 {
2773         struct ixgbe_hw_stats *stats =
2774                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2775
2776         unsigned count = ixgbe_xstats_calc_num();
2777
2778         /* HW registers are cleared on read */
2779         ixgbe_dev_xstats_get(dev, NULL, count);
2780
2781         /* Reset software totals */
2782         memset(stats, 0, sizeof(*stats));
2783 }
2784
2785 static void
2786 ixgbevf_update_stats(struct rte_eth_dev *dev)
2787 {
2788         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2789         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2790                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2791
2792         /* Good Rx packet, include VF loopback */
2793         UPDATE_VF_STAT(IXGBE_VFGPRC,
2794             hw_stats->last_vfgprc, hw_stats->vfgprc);
2795
2796         /* Good Rx octets, include VF loopback */
2797         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2798             hw_stats->last_vfgorc, hw_stats->vfgorc);
2799
2800         /* Good Tx packet, include VF loopback */
2801         UPDATE_VF_STAT(IXGBE_VFGPTC,
2802             hw_stats->last_vfgptc, hw_stats->vfgptc);
2803
2804         /* Good Tx octets, include VF loopback */
2805         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2806             hw_stats->last_vfgotc, hw_stats->vfgotc);
2807
2808         /* Rx Multicst Packet */
2809         UPDATE_VF_STAT(IXGBE_VFMPRC,
2810             hw_stats->last_vfmprc, hw_stats->vfmprc);
2811 }
2812
2813 static int
2814 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2815                        unsigned n)
2816 {
2817         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2818                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2819         unsigned i;
2820
2821         if (n < IXGBEVF_NB_XSTATS)
2822                 return IXGBEVF_NB_XSTATS;
2823
2824         ixgbevf_update_stats(dev);
2825
2826         if (!xstats)
2827                 return 0;
2828
2829         /* Extended stats */
2830         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2831                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2832                          "%s", rte_ixgbevf_stats_strings[i].name);
2833                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2834                         rte_ixgbevf_stats_strings[i].offset);
2835         }
2836
2837         return IXGBEVF_NB_XSTATS;
2838 }
2839
2840 static void
2841 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2842 {
2843         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2844                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2845
2846         ixgbevf_update_stats(dev);
2847
2848         if (stats == NULL)
2849                 return;
2850
2851         stats->ipackets = hw_stats->vfgprc;
2852         stats->ibytes = hw_stats->vfgorc;
2853         stats->opackets = hw_stats->vfgptc;
2854         stats->obytes = hw_stats->vfgotc;
2855 }
2856
2857 static void
2858 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2859 {
2860         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2861                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2862
2863         /* Sync HW register to the last stats */
2864         ixgbevf_dev_stats_get(dev, NULL);
2865
2866         /* reset HW current stats*/
2867         hw_stats->vfgprc = 0;
2868         hw_stats->vfgorc = 0;
2869         hw_stats->vfgptc = 0;
2870         hw_stats->vfgotc = 0;
2871 }
2872
2873 static void
2874 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2875 {
2876         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2877         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2878
2879         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2880         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2881         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
2882                 /*
2883                  * When DCB/VT is off, maximum number of queues changes,
2884                  * except for 82598EB, which remains constant.
2885                  */
2886                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2887                                 hw->mac.type != ixgbe_mac_82598EB)
2888                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
2889         }
2890         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2891         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2892         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2893         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2894         dev_info->max_vfs = dev->pci_dev->max_vfs;
2895         if (hw->mac.type == ixgbe_mac_82598EB)
2896                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2897         else
2898                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2899         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2900         dev_info->rx_offload_capa =
2901                 DEV_RX_OFFLOAD_VLAN_STRIP |
2902                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2903                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2904                 DEV_RX_OFFLOAD_TCP_CKSUM;
2905
2906         /*
2907          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2908          * mode.
2909          */
2910         if ((hw->mac.type == ixgbe_mac_82599EB ||
2911              hw->mac.type == ixgbe_mac_X540) &&
2912             !RTE_ETH_DEV_SRIOV(dev).active)
2913                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2914
2915         if (hw->mac.type == ixgbe_mac_X550 ||
2916             hw->mac.type == ixgbe_mac_X550EM_x ||
2917             hw->mac.type == ixgbe_mac_X550EM_a)
2918                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2919
2920         dev_info->tx_offload_capa =
2921                 DEV_TX_OFFLOAD_VLAN_INSERT |
2922                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2923                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2924                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2925                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2926                 DEV_TX_OFFLOAD_TCP_TSO;
2927
2928         if (hw->mac.type == ixgbe_mac_X550 ||
2929             hw->mac.type == ixgbe_mac_X550EM_x ||
2930             hw->mac.type == ixgbe_mac_X550EM_a)
2931                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2932
2933         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2934                 .rx_thresh = {
2935                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2936                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2937                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2938                 },
2939                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2940                 .rx_drop_en = 0,
2941         };
2942
2943         dev_info->default_txconf = (struct rte_eth_txconf) {
2944                 .tx_thresh = {
2945                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2946                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2947                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2948                 },
2949                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2950                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2951                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2952                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2953         };
2954
2955         dev_info->rx_desc_lim = rx_desc_lim;
2956         dev_info->tx_desc_lim = tx_desc_lim;
2957
2958         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2959         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2960         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2961
2962         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2963         if (hw->mac.type == ixgbe_mac_X540 ||
2964             hw->mac.type == ixgbe_mac_X540_vf ||
2965             hw->mac.type == ixgbe_mac_X550 ||
2966             hw->mac.type == ixgbe_mac_X550_vf) {
2967                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
2968         }
2969 }
2970
2971 static const uint32_t *
2972 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2973 {
2974         static const uint32_t ptypes[] = {
2975                 /* For non-vec functions,
2976                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
2977                  * for vec functions,
2978                  * refers to _recv_raw_pkts_vec().
2979                  */
2980                 RTE_PTYPE_L2_ETHER,
2981                 RTE_PTYPE_L3_IPV4,
2982                 RTE_PTYPE_L3_IPV4_EXT,
2983                 RTE_PTYPE_L3_IPV6,
2984                 RTE_PTYPE_L3_IPV6_EXT,
2985                 RTE_PTYPE_L4_SCTP,
2986                 RTE_PTYPE_L4_TCP,
2987                 RTE_PTYPE_L4_UDP,
2988                 RTE_PTYPE_TUNNEL_IP,
2989                 RTE_PTYPE_INNER_L3_IPV6,
2990                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2991                 RTE_PTYPE_INNER_L4_TCP,
2992                 RTE_PTYPE_INNER_L4_UDP,
2993                 RTE_PTYPE_UNKNOWN
2994         };
2995
2996         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
2997             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
2998             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
2999             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3000                 return ptypes;
3001         return NULL;
3002 }
3003
3004 static void
3005 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3006                      struct rte_eth_dev_info *dev_info)
3007 {
3008         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3009
3010         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3011         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3012         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3013         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3014         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3015         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3016         dev_info->max_vfs = dev->pci_dev->max_vfs;
3017         if (hw->mac.type == ixgbe_mac_82598EB)
3018                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3019         else
3020                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3021         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3022                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3023                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3024                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3025         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3026                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3027                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3028                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3029                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3030                                 DEV_TX_OFFLOAD_TCP_TSO;
3031
3032         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3033                 .rx_thresh = {
3034                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3035                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3036                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3037                 },
3038                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3039                 .rx_drop_en = 0,
3040         };
3041
3042         dev_info->default_txconf = (struct rte_eth_txconf) {
3043                 .tx_thresh = {
3044                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3045                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3046                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3047                 },
3048                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3049                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3050                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3051                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3052         };
3053
3054         dev_info->rx_desc_lim = rx_desc_lim;
3055         dev_info->tx_desc_lim = tx_desc_lim;
3056 }
3057
3058 /* return 0 means link status changed, -1 means not changed */
3059 static int
3060 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3061 {
3062         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3063         struct rte_eth_link link, old;
3064         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3065         int link_up;
3066         int diag;
3067
3068         link.link_status = ETH_LINK_DOWN;
3069         link.link_speed = 0;
3070         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3071         memset(&old, 0, sizeof(old));
3072         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3073
3074         hw->mac.get_link_status = true;
3075
3076         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3077         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3078                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3079         else
3080                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3081
3082         if (diag != 0) {
3083                 link.link_speed = ETH_SPEED_NUM_100M;
3084                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3085                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3086                 if (link.link_status == old.link_status)
3087                         return -1;
3088                 return 0;
3089         }
3090
3091         if (link_up == 0) {
3092                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3093                 if (link.link_status == old.link_status)
3094                         return -1;
3095                 return 0;
3096         }
3097         link.link_status = ETH_LINK_UP;
3098         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3099
3100         switch (link_speed) {
3101         default:
3102         case IXGBE_LINK_SPEED_UNKNOWN:
3103                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3104                 link.link_speed = ETH_SPEED_NUM_100M;
3105                 break;
3106
3107         case IXGBE_LINK_SPEED_100_FULL:
3108                 link.link_speed = ETH_SPEED_NUM_100M;
3109                 break;
3110
3111         case IXGBE_LINK_SPEED_1GB_FULL:
3112                 link.link_speed = ETH_SPEED_NUM_1G;
3113                 break;
3114
3115         case IXGBE_LINK_SPEED_10GB_FULL:
3116                 link.link_speed = ETH_SPEED_NUM_10G;
3117                 break;
3118         }
3119         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3120
3121         if (link.link_status == old.link_status)
3122                 return -1;
3123
3124         return 0;
3125 }
3126
3127 static void
3128 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3129 {
3130         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3131         uint32_t fctrl;
3132
3133         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3134         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3135         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3136 }
3137
3138 static void
3139 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3140 {
3141         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3142         uint32_t fctrl;
3143
3144         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3145         fctrl &= (~IXGBE_FCTRL_UPE);
3146         if (dev->data->all_multicast == 1)
3147                 fctrl |= IXGBE_FCTRL_MPE;
3148         else
3149                 fctrl &= (~IXGBE_FCTRL_MPE);
3150         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3151 }
3152
3153 static void
3154 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3155 {
3156         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3157         uint32_t fctrl;
3158
3159         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3160         fctrl |= IXGBE_FCTRL_MPE;
3161         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3162 }
3163
3164 static void
3165 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3166 {
3167         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3168         uint32_t fctrl;
3169
3170         if (dev->data->promiscuous == 1)
3171                 return; /* must remain in all_multicast mode */
3172
3173         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3174         fctrl &= (~IXGBE_FCTRL_MPE);
3175         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3176 }
3177
3178 /**
3179  * It clears the interrupt causes and enables the interrupt.
3180  * It will be called once only during nic initialized.
3181  *
3182  * @param dev
3183  *  Pointer to struct rte_eth_dev.
3184  *
3185  * @return
3186  *  - On success, zero.
3187  *  - On failure, a negative value.
3188  */
3189 static int
3190 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3191 {
3192         struct ixgbe_interrupt *intr =
3193                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3194
3195         ixgbe_dev_link_status_print(dev);
3196         intr->mask |= IXGBE_EICR_LSC;
3197
3198         return 0;
3199 }
3200
3201 /**
3202  * It clears the interrupt causes and enables the interrupt.
3203  * It will be called once only during nic initialized.
3204  *
3205  * @param dev
3206  *  Pointer to struct rte_eth_dev.
3207  *
3208  * @return
3209  *  - On success, zero.
3210  *  - On failure, a negative value.
3211  */
3212 static int
3213 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3214 {
3215         struct ixgbe_interrupt *intr =
3216                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3217
3218         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3219
3220         return 0;
3221 }
3222
3223 /*
3224  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3225  *
3226  * @param dev
3227  *  Pointer to struct rte_eth_dev.
3228  *
3229  * @return
3230  *  - On success, zero.
3231  *  - On failure, a negative value.
3232  */
3233 static int
3234 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3235 {
3236         uint32_t eicr;
3237         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3238         struct ixgbe_interrupt *intr =
3239                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3240
3241         /* clear all cause mask */
3242         ixgbe_disable_intr(hw);
3243
3244         /* read-on-clear nic registers here */
3245         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3246         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3247
3248         intr->flags = 0;
3249
3250         /* set flag for async link update */
3251         if (eicr & IXGBE_EICR_LSC)
3252                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3253
3254         if (eicr & IXGBE_EICR_MAILBOX)
3255                 intr->flags |= IXGBE_FLAG_MAILBOX;
3256
3257         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3258             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3259             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3260                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3261
3262         return 0;
3263 }
3264
3265 /**
3266  * It gets and then prints the link status.
3267  *
3268  * @param dev
3269  *  Pointer to struct rte_eth_dev.
3270  *
3271  * @return
3272  *  - On success, zero.
3273  *  - On failure, a negative value.
3274  */
3275 static void
3276 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3277 {
3278         struct rte_eth_link link;
3279
3280         memset(&link, 0, sizeof(link));
3281         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3282         if (link.link_status) {
3283                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3284                                         (int)(dev->data->port_id),
3285                                         (unsigned)link.link_speed,
3286                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3287                                         "full-duplex" : "half-duplex");
3288         } else {
3289                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3290                                 (int)(dev->data->port_id));
3291         }
3292         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3293                                 dev->pci_dev->addr.domain,
3294                                 dev->pci_dev->addr.bus,
3295                                 dev->pci_dev->addr.devid,
3296                                 dev->pci_dev->addr.function);
3297 }
3298
3299 /*
3300  * It executes link_update after knowing an interrupt occurred.
3301  *
3302  * @param dev
3303  *  Pointer to struct rte_eth_dev.
3304  *
3305  * @return
3306  *  - On success, zero.
3307  *  - On failure, a negative value.
3308  */
3309 static int
3310 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3311 {
3312         struct ixgbe_interrupt *intr =
3313                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3314         int64_t timeout;
3315         struct rte_eth_link link;
3316         int intr_enable_delay = false;
3317         struct ixgbe_hw *hw =
3318                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3319
3320         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3321
3322         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3323                 ixgbe_pf_mbx_process(dev);
3324                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3325         }
3326
3327         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3328                 ixgbe_handle_lasi(hw);
3329                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3330         }
3331
3332         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3333                 /* get the link status before link update, for predicting later */
3334                 memset(&link, 0, sizeof(link));
3335                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3336
3337                 ixgbe_dev_link_update(dev, 0);
3338
3339                 /* likely to up */
3340                 if (!link.link_status)
3341                         /* handle it 1 sec later, wait it being stable */
3342                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3343                 /* likely to down */
3344                 else
3345                         /* handle it 4 sec later, wait it being stable */
3346                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3347
3348                 ixgbe_dev_link_status_print(dev);
3349
3350                 intr_enable_delay = true;
3351         }
3352
3353         if (intr_enable_delay) {
3354                 if (rte_eal_alarm_set(timeout * 1000,
3355                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3356                         PMD_DRV_LOG(ERR, "Error setting alarm");
3357         } else {
3358                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3359                 ixgbe_enable_intr(dev);
3360                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3361         }
3362
3363
3364         return 0;
3365 }
3366
3367 /**
3368  * Interrupt handler which shall be registered for alarm callback for delayed
3369  * handling specific interrupt to wait for the stable nic state. As the
3370  * NIC interrupt state is not stable for ixgbe after link is just down,
3371  * it needs to wait 4 seconds to get the stable status.
3372  *
3373  * @param handle
3374  *  Pointer to interrupt handle.
3375  * @param param
3376  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3377  *
3378  * @return
3379  *  void
3380  */
3381 static void
3382 ixgbe_dev_interrupt_delayed_handler(void *param)
3383 {
3384         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3385         struct ixgbe_interrupt *intr =
3386                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3387         struct ixgbe_hw *hw =
3388                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3389         uint32_t eicr;
3390
3391         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3392         if (eicr & IXGBE_EICR_MAILBOX)
3393                 ixgbe_pf_mbx_process(dev);
3394
3395         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3396                 ixgbe_handle_lasi(hw);
3397                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3398         }
3399
3400         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3401                 ixgbe_dev_link_update(dev, 0);
3402                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3403                 ixgbe_dev_link_status_print(dev);
3404                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3405         }
3406
3407         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3408         ixgbe_enable_intr(dev);
3409         rte_intr_enable(&(dev->pci_dev->intr_handle));
3410 }
3411
3412 /**
3413  * Interrupt handler triggered by NIC  for handling
3414  * specific interrupt.
3415  *
3416  * @param handle
3417  *  Pointer to interrupt handle.
3418  * @param param
3419  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3420  *
3421  * @return
3422  *  void
3423  */
3424 static void
3425 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3426                             void *param)
3427 {
3428         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3429
3430         ixgbe_dev_interrupt_get_status(dev);
3431         ixgbe_dev_interrupt_action(dev);
3432 }
3433
3434 static int
3435 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3436 {
3437         struct ixgbe_hw *hw;
3438
3439         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3440         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3441 }
3442
3443 static int
3444 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3445 {
3446         struct ixgbe_hw *hw;
3447
3448         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3449         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3450 }
3451
3452 static int
3453 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3454 {
3455         struct ixgbe_hw *hw;
3456         uint32_t mflcn_reg;
3457         uint32_t fccfg_reg;
3458         int rx_pause;
3459         int tx_pause;
3460
3461         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3462
3463         fc_conf->pause_time = hw->fc.pause_time;
3464         fc_conf->high_water = hw->fc.high_water[0];
3465         fc_conf->low_water = hw->fc.low_water[0];
3466         fc_conf->send_xon = hw->fc.send_xon;
3467         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3468
3469         /*
3470          * Return rx_pause status according to actual setting of
3471          * MFLCN register.
3472          */
3473         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3474         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3475                 rx_pause = 1;
3476         else
3477                 rx_pause = 0;
3478
3479         /*
3480          * Return tx_pause status according to actual setting of
3481          * FCCFG register.
3482          */
3483         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3484         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3485                 tx_pause = 1;
3486         else
3487                 tx_pause = 0;
3488
3489         if (rx_pause && tx_pause)
3490                 fc_conf->mode = RTE_FC_FULL;
3491         else if (rx_pause)
3492                 fc_conf->mode = RTE_FC_RX_PAUSE;
3493         else if (tx_pause)
3494                 fc_conf->mode = RTE_FC_TX_PAUSE;
3495         else
3496                 fc_conf->mode = RTE_FC_NONE;
3497
3498         return 0;
3499 }
3500
3501 static int
3502 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3503 {
3504         struct ixgbe_hw *hw;
3505         int err;
3506         uint32_t rx_buf_size;
3507         uint32_t max_high_water;
3508         uint32_t mflcn;
3509         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3510                 ixgbe_fc_none,
3511                 ixgbe_fc_rx_pause,
3512                 ixgbe_fc_tx_pause,
3513                 ixgbe_fc_full
3514         };
3515
3516         PMD_INIT_FUNC_TRACE();
3517
3518         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3519         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3520         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3521
3522         /*
3523          * At least reserve one Ethernet frame for watermark
3524          * high_water/low_water in kilo bytes for ixgbe
3525          */
3526         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3527         if ((fc_conf->high_water > max_high_water) ||
3528                 (fc_conf->high_water < fc_conf->low_water)) {
3529                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3530                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3531                 return -EINVAL;
3532         }
3533
3534         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3535         hw->fc.pause_time     = fc_conf->pause_time;
3536         hw->fc.high_water[0]  = fc_conf->high_water;
3537         hw->fc.low_water[0]   = fc_conf->low_water;
3538         hw->fc.send_xon       = fc_conf->send_xon;
3539         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3540
3541         err = ixgbe_fc_enable(hw);
3542
3543         /* Not negotiated is not an error case */
3544         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3545
3546                 /* check if we want to forward MAC frames - driver doesn't have native
3547                  * capability to do that, so we'll write the registers ourselves */
3548
3549                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3550
3551                 /* set or clear MFLCN.PMCF bit depending on configuration */
3552                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3553                         mflcn |= IXGBE_MFLCN_PMCF;
3554                 else
3555                         mflcn &= ~IXGBE_MFLCN_PMCF;
3556
3557                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3558                 IXGBE_WRITE_FLUSH(hw);
3559
3560                 return 0;
3561         }
3562
3563         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3564         return -EIO;
3565 }
3566
3567 /**
3568  *  ixgbe_pfc_enable_generic - Enable flow control
3569  *  @hw: pointer to hardware structure
3570  *  @tc_num: traffic class number
3571  *  Enable flow control according to the current settings.
3572  */
3573 static int
3574 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3575 {
3576         int ret_val = 0;
3577         uint32_t mflcn_reg, fccfg_reg;
3578         uint32_t reg;
3579         uint32_t fcrtl, fcrth;
3580         uint8_t i;
3581         uint8_t nb_rx_en;
3582
3583         /* Validate the water mark configuration */
3584         if (!hw->fc.pause_time) {
3585                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3586                 goto out;
3587         }
3588
3589         /* Low water mark of zero causes XOFF floods */
3590         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3591                  /* High/Low water can not be 0 */
3592                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3593                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3594                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3595                         goto out;
3596                 }
3597
3598                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3599                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3600                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3601                         goto out;
3602                 }
3603         }
3604         /* Negotiate the fc mode to use */
3605         ixgbe_fc_autoneg(hw);
3606
3607         /* Disable any previous flow control settings */
3608         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3609         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3610
3611         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3612         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3613
3614         switch (hw->fc.current_mode) {
3615         case ixgbe_fc_none:
3616                 /*
3617                  * If the count of enabled RX Priority Flow control >1,
3618                  * and the TX pause can not be disabled
3619                  */
3620                 nb_rx_en = 0;
3621                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3622                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3623                         if (reg & IXGBE_FCRTH_FCEN)
3624                                 nb_rx_en++;
3625                 }
3626                 if (nb_rx_en > 1)
3627                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3628                 break;
3629         case ixgbe_fc_rx_pause:
3630                 /*
3631                  * Rx Flow control is enabled and Tx Flow control is
3632                  * disabled by software override. Since there really
3633                  * isn't a way to advertise that we are capable of RX
3634                  * Pause ONLY, we will advertise that we support both
3635                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3636                  * disable the adapter's ability to send PAUSE frames.
3637                  */
3638                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3639                 /*
3640                  * If the count of enabled RX Priority Flow control >1,
3641                  * and the TX pause can not be disabled
3642                  */
3643                 nb_rx_en = 0;
3644                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3645                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3646                         if (reg & IXGBE_FCRTH_FCEN)
3647                                 nb_rx_en++;
3648                 }
3649                 if (nb_rx_en > 1)
3650                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3651                 break;
3652         case ixgbe_fc_tx_pause:
3653                 /*
3654                  * Tx Flow control is enabled, and Rx Flow control is
3655                  * disabled by software override.
3656                  */
3657                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3658                 break;
3659         case ixgbe_fc_full:
3660                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3661                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3662                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3663                 break;
3664         default:
3665                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3666                 ret_val = IXGBE_ERR_CONFIG;
3667                 goto out;
3668                 break;
3669         }
3670
3671         /* Set 802.3x based flow control settings. */
3672         mflcn_reg |= IXGBE_MFLCN_DPF;
3673         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3674         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3675
3676         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3677         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3678                 hw->fc.high_water[tc_num]) {
3679                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3680                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3681                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3682         } else {
3683                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3684                 /*
3685                  * In order to prevent Tx hangs when the internal Tx
3686                  * switch is enabled we must set the high water mark
3687                  * to the maximum FCRTH value.  This allows the Tx
3688                  * switch to function even under heavy Rx workloads.
3689                  */
3690                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3691         }
3692         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3693
3694         /* Configure pause time (2 TCs per register) */
3695         reg = hw->fc.pause_time * 0x00010001;
3696         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3697                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3698
3699         /* Configure flow control refresh threshold value */
3700         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3701
3702 out:
3703         return ret_val;
3704 }
3705
3706 static int
3707 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3708 {
3709         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3710         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3711
3712         if (hw->mac.type != ixgbe_mac_82598EB) {
3713                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3714         }
3715         return ret_val;
3716 }
3717
3718 static int
3719 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3720 {
3721         int err;
3722         uint32_t rx_buf_size;
3723         uint32_t max_high_water;
3724         uint8_t tc_num;
3725         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3726         struct ixgbe_hw *hw =
3727                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3728         struct ixgbe_dcb_config *dcb_config =
3729                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3730
3731         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3732                 ixgbe_fc_none,
3733                 ixgbe_fc_rx_pause,
3734                 ixgbe_fc_tx_pause,
3735                 ixgbe_fc_full
3736         };
3737
3738         PMD_INIT_FUNC_TRACE();
3739
3740         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3741         tc_num = map[pfc_conf->priority];
3742         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3743         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3744         /*
3745          * At least reserve one Ethernet frame for watermark
3746          * high_water/low_water in kilo bytes for ixgbe
3747          */
3748         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3749         if ((pfc_conf->fc.high_water > max_high_water) ||
3750             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3751                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3752                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3753                 return -EINVAL;
3754         }
3755
3756         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3757         hw->fc.pause_time = pfc_conf->fc.pause_time;
3758         hw->fc.send_xon = pfc_conf->fc.send_xon;
3759         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3760         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3761
3762         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3763
3764         /* Not negotiated is not an error case */
3765         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3766                 return 0;
3767
3768         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3769         return -EIO;
3770 }
3771
3772 static int
3773 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3774                           struct rte_eth_rss_reta_entry64 *reta_conf,
3775                           uint16_t reta_size)
3776 {
3777         uint16_t i, sp_reta_size;
3778         uint8_t j, mask;
3779         uint32_t reta, r;
3780         uint16_t idx, shift;
3781         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3782         uint32_t reta_reg;
3783
3784         PMD_INIT_FUNC_TRACE();
3785
3786         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3787                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3788                         "NIC.");
3789                 return -ENOTSUP;
3790         }
3791
3792         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3793         if (reta_size != sp_reta_size) {
3794                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3795                         "(%d) doesn't match the number hardware can supported "
3796                         "(%d)\n", reta_size, sp_reta_size);
3797                 return -EINVAL;
3798         }
3799
3800         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3801                 idx = i / RTE_RETA_GROUP_SIZE;
3802                 shift = i % RTE_RETA_GROUP_SIZE;
3803                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3804                                                 IXGBE_4_BIT_MASK);
3805                 if (!mask)
3806                         continue;
3807                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3808                 if (mask == IXGBE_4_BIT_MASK)
3809                         r = 0;
3810                 else
3811                         r = IXGBE_READ_REG(hw, reta_reg);
3812                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3813                         if (mask & (0x1 << j))
3814                                 reta |= reta_conf[idx].reta[shift + j] <<
3815                                                         (CHAR_BIT * j);
3816                         else
3817                                 reta |= r & (IXGBE_8_BIT_MASK <<
3818                                                 (CHAR_BIT * j));
3819                 }
3820                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3821         }
3822
3823         return 0;
3824 }
3825
3826 static int
3827 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3828                          struct rte_eth_rss_reta_entry64 *reta_conf,
3829                          uint16_t reta_size)
3830 {
3831         uint16_t i, sp_reta_size;
3832         uint8_t j, mask;
3833         uint32_t reta;
3834         uint16_t idx, shift;
3835         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3836         uint32_t reta_reg;
3837
3838         PMD_INIT_FUNC_TRACE();
3839         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3840         if (reta_size != sp_reta_size) {
3841                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3842                         "(%d) doesn't match the number hardware can supported "
3843                         "(%d)\n", reta_size, sp_reta_size);
3844                 return -EINVAL;
3845         }
3846
3847         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3848                 idx = i / RTE_RETA_GROUP_SIZE;
3849                 shift = i % RTE_RETA_GROUP_SIZE;
3850                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3851                                                 IXGBE_4_BIT_MASK);
3852                 if (!mask)
3853                         continue;
3854
3855                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3856                 reta = IXGBE_READ_REG(hw, reta_reg);
3857                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3858                         if (mask & (0x1 << j))
3859                                 reta_conf[idx].reta[shift + j] =
3860                                         ((reta >> (CHAR_BIT * j)) &
3861                                                 IXGBE_8_BIT_MASK);
3862                 }
3863         }
3864
3865         return 0;
3866 }
3867
3868 static void
3869 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3870                                 uint32_t index, uint32_t pool)
3871 {
3872         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3873         uint32_t enable_addr = 1;
3874
3875         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3876 }
3877
3878 static void
3879 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3880 {
3881         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3882
3883         ixgbe_clear_rar(hw, index);
3884 }
3885
3886 static void
3887 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3888 {
3889         ixgbe_remove_rar(dev, 0);
3890
3891         ixgbe_add_rar(dev, addr, 0, 0);
3892 }
3893
3894 static int
3895 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3896 {
3897         uint32_t hlreg0;
3898         uint32_t maxfrs;
3899         struct ixgbe_hw *hw;
3900         struct rte_eth_dev_info dev_info;
3901         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3902
3903         ixgbe_dev_info_get(dev, &dev_info);
3904
3905         /* check that mtu is within the allowed range */
3906         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3907                 return -EINVAL;
3908
3909         /* refuse mtu that requires the support of scattered packets when this
3910          * feature has not been enabled before. */
3911         if (!dev->data->scattered_rx &&
3912             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3913              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3914                 return -EINVAL;
3915
3916         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3917         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3918
3919         /* switch to jumbo mode if needed */
3920         if (frame_size > ETHER_MAX_LEN) {
3921                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3922                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3923         } else {
3924                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3925                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3926         }
3927         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3928
3929         /* update max frame size */
3930         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3931
3932         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3933         maxfrs &= 0x0000FFFF;
3934         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3935         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3936
3937         return 0;
3938 }
3939
3940 /*
3941  * Virtual Function operations
3942  */
3943 static void
3944 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3945 {
3946         PMD_INIT_FUNC_TRACE();
3947
3948         /* Clear interrupt mask to stop from interrupts being generated */
3949         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3950
3951         IXGBE_WRITE_FLUSH(hw);
3952 }
3953
3954 static void
3955 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3956 {
3957         PMD_INIT_FUNC_TRACE();
3958
3959         /* VF enable interrupt autoclean */
3960         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3961         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3962         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3963
3964         IXGBE_WRITE_FLUSH(hw);
3965 }
3966
3967 static int
3968 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3969 {
3970         struct rte_eth_conf* conf = &dev->data->dev_conf;
3971         struct ixgbe_adapter *adapter =
3972                         (struct ixgbe_adapter *)dev->data->dev_private;
3973
3974         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3975                      dev->data->port_id);
3976
3977         /*
3978          * VF has no ability to enable/disable HW CRC
3979          * Keep the persistent behavior the same as Host PF
3980          */
3981 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3982         if (!conf->rxmode.hw_strip_crc) {
3983                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3984                 conf->rxmode.hw_strip_crc = 1;
3985         }
3986 #else
3987         if (conf->rxmode.hw_strip_crc) {
3988                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3989                 conf->rxmode.hw_strip_crc = 0;
3990         }
3991 #endif
3992
3993         /*
3994          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3995          * allocation or vector Rx preconditions we will reset it.
3996          */
3997         adapter->rx_bulk_alloc_allowed = true;
3998         adapter->rx_vec_allowed = true;
3999
4000         return 0;
4001 }
4002
4003 static int
4004 ixgbevf_dev_start(struct rte_eth_dev *dev)
4005 {
4006         struct ixgbe_hw *hw =
4007                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4008         uint32_t intr_vector = 0;
4009         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4010
4011         int err, mask = 0;
4012
4013         PMD_INIT_FUNC_TRACE();
4014
4015         hw->mac.ops.reset_hw(hw);
4016         hw->mac.get_link_status = true;
4017
4018         /* negotiate mailbox API version to use with the PF. */
4019         ixgbevf_negotiate_api(hw);
4020
4021         ixgbevf_dev_tx_init(dev);
4022
4023         /* This can fail when allocating mbufs for descriptor rings */
4024         err = ixgbevf_dev_rx_init(dev);
4025         if (err) {
4026                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4027                 ixgbe_dev_clear_queues(dev);
4028                 return err;
4029         }
4030
4031         /* Set vfta */
4032         ixgbevf_set_vfta_all(dev,1);
4033
4034         /* Set HW strip */
4035         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
4036                 ETH_VLAN_EXTEND_MASK;
4037         ixgbevf_vlan_offload_set(dev, mask);
4038
4039         ixgbevf_dev_rxtx_start(dev);
4040
4041         /* check and configure queue intr-vector mapping */
4042         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4043                 intr_vector = dev->data->nb_rx_queues;
4044                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4045                         return -1;
4046         }
4047
4048         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4049                 intr_handle->intr_vec =
4050                         rte_zmalloc("intr_vec",
4051                                     dev->data->nb_rx_queues * sizeof(int), 0);
4052                 if (intr_handle->intr_vec == NULL) {
4053                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4054                                      " intr_vec\n", dev->data->nb_rx_queues);
4055                         return -ENOMEM;
4056                 }
4057         }
4058         ixgbevf_configure_msix(dev);
4059
4060         rte_intr_enable(intr_handle);
4061
4062         /* Re-enable interrupt for VF */
4063         ixgbevf_intr_enable(hw);
4064
4065         return 0;
4066 }
4067
4068 static void
4069 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4070 {
4071         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4072         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4073
4074         PMD_INIT_FUNC_TRACE();
4075
4076         hw->adapter_stopped = 1;
4077         ixgbe_stop_adapter(hw);
4078
4079         /*
4080           * Clear what we set, but we still keep shadow_vfta to
4081           * restore after device starts
4082           */
4083         ixgbevf_set_vfta_all(dev,0);
4084
4085         /* Clear stored conf */
4086         dev->data->scattered_rx = 0;
4087
4088         ixgbe_dev_clear_queues(dev);
4089
4090         /* Clean datapath event and queue/vec mapping */
4091         rte_intr_efd_disable(intr_handle);
4092         if (intr_handle->intr_vec != NULL) {
4093                 rte_free(intr_handle->intr_vec);
4094                 intr_handle->intr_vec = NULL;
4095         }
4096 }
4097
4098 static void
4099 ixgbevf_dev_close(struct rte_eth_dev *dev)
4100 {
4101         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4102
4103         PMD_INIT_FUNC_TRACE();
4104
4105         ixgbe_reset_hw(hw);
4106
4107         ixgbevf_dev_stop(dev);
4108
4109         ixgbe_dev_free_queues(dev);
4110
4111         /**
4112          * Remove the VF MAC address ro ensure
4113          * that the VF traffic goes to the PF
4114          * after stop, close and detach of the VF
4115          **/
4116         ixgbevf_remove_mac_addr(dev, 0);
4117 }
4118
4119 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4120 {
4121         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4122         struct ixgbe_vfta * shadow_vfta =
4123                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4124         int i = 0, j = 0, vfta = 0, mask = 1;
4125
4126         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
4127                 vfta = shadow_vfta->vfta[i];
4128                 if (vfta) {
4129                         mask = 1;
4130                         for (j = 0; j < 32; j++){
4131                                 if (vfta & mask)
4132                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
4133                                 mask<<=1;
4134                         }
4135                 }
4136         }
4137
4138 }
4139
4140 static int
4141 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4142 {
4143         struct ixgbe_hw *hw =
4144                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4145         struct ixgbe_vfta * shadow_vfta =
4146                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4147         uint32_t vid_idx = 0;
4148         uint32_t vid_bit = 0;
4149         int ret = 0;
4150
4151         PMD_INIT_FUNC_TRACE();
4152
4153         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4154         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4155         if (ret) {
4156                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4157                 return ret;
4158         }
4159         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4160         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4161
4162         /* Save what we set and retore it after device reset */
4163         if (on)
4164                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4165         else
4166                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4167
4168         return 0;
4169 }
4170
4171 static void
4172 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4173 {
4174         struct ixgbe_hw *hw =
4175                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4176         uint32_t ctrl;
4177
4178         PMD_INIT_FUNC_TRACE();
4179
4180         if (queue >= hw->mac.max_rx_queues)
4181                 return;
4182
4183         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4184         if (on)
4185                 ctrl |= IXGBE_RXDCTL_VME;
4186         else
4187                 ctrl &= ~IXGBE_RXDCTL_VME;
4188         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4189
4190         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4191 }
4192
4193 static void
4194 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4195 {
4196         struct ixgbe_hw *hw =
4197                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4198         uint16_t i;
4199         int on = 0;
4200
4201         /* VF function only support hw strip feature, others are not support */
4202         if (mask & ETH_VLAN_STRIP_MASK) {
4203                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4204
4205                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4206                         ixgbevf_vlan_strip_queue_set(dev,i,on);
4207         }
4208 }
4209
4210 static int
4211 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4212 {
4213         uint32_t reg_val;
4214
4215         /* we only need to do this if VMDq is enabled */
4216         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4217         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4218                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4219                 return -1;
4220         }
4221
4222         return 0;
4223 }
4224
4225 static uint32_t
4226 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4227 {
4228         uint32_t vector = 0;
4229         switch (hw->mac.mc_filter_type) {
4230         case 0:   /* use bits [47:36] of the address */
4231                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4232                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4233                 break;
4234         case 1:   /* use bits [46:35] of the address */
4235                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4236                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4237                 break;
4238         case 2:   /* use bits [45:34] of the address */
4239                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4240                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4241                 break;
4242         case 3:   /* use bits [43:32] of the address */
4243                 vector = ((uc_addr->addr_bytes[4]) |
4244                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4245                 break;
4246         default:  /* Invalid mc_filter_type */
4247                 break;
4248         }
4249
4250         /* vector can only be 12-bits or boundary will be exceeded */
4251         vector &= 0xFFF;
4252         return vector;
4253 }
4254
4255 static int
4256 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4257                                uint8_t on)
4258 {
4259         uint32_t vector;
4260         uint32_t uta_idx;
4261         uint32_t reg_val;
4262         uint32_t uta_shift;
4263         uint32_t rc;
4264         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4265         const uint32_t ixgbe_uta_bit_shift = 5;
4266         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4267         const uint32_t bit1 = 0x1;
4268
4269         struct ixgbe_hw *hw =
4270                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4271         struct ixgbe_uta_info *uta_info =
4272                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4273
4274         /* The UTA table only exists on 82599 hardware and newer */
4275         if (hw->mac.type < ixgbe_mac_82599EB)
4276                 return -ENOTSUP;
4277
4278         vector = ixgbe_uta_vector(hw,mac_addr);
4279         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4280         uta_shift = vector & ixgbe_uta_bit_mask;
4281
4282         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4283         if (rc == on)
4284                 return 0;
4285
4286         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4287         if (on) {
4288                 uta_info->uta_in_use++;
4289                 reg_val |= (bit1 << uta_shift);
4290                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4291         } else {
4292                 uta_info->uta_in_use--;
4293                 reg_val &= ~(bit1 << uta_shift);
4294                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4295         }
4296
4297         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4298
4299         if (uta_info->uta_in_use > 0)
4300                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4301                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4302         else
4303                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4304
4305         return 0;
4306 }
4307
4308 static int
4309 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4310 {
4311         int i;
4312         struct ixgbe_hw *hw =
4313                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4314         struct ixgbe_uta_info *uta_info =
4315                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4316
4317         /* The UTA table only exists on 82599 hardware and newer */
4318         if (hw->mac.type < ixgbe_mac_82599EB)
4319                 return -ENOTSUP;
4320
4321         if (on) {
4322                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4323                         uta_info->uta_shadow[i] = ~0;
4324                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4325                 }
4326         } else {
4327                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4328                         uta_info->uta_shadow[i] = 0;
4329                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4330                 }
4331         }
4332         return 0;
4333
4334 }
4335
4336 uint32_t
4337 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4338 {
4339         uint32_t new_val = orig_val;
4340
4341         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4342                 new_val |= IXGBE_VMOLR_AUPE;
4343         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4344                 new_val |= IXGBE_VMOLR_ROMPE;
4345         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4346                 new_val |= IXGBE_VMOLR_ROPE;
4347         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4348                 new_val |= IXGBE_VMOLR_BAM;
4349         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4350                 new_val |= IXGBE_VMOLR_MPE;
4351
4352         return new_val;
4353 }
4354
4355 static int
4356 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4357                                uint16_t rx_mask, uint8_t on)
4358 {
4359         int val = 0;
4360
4361         struct ixgbe_hw *hw =
4362                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4363         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4364
4365         if (hw->mac.type == ixgbe_mac_82598EB) {
4366                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4367                              " on 82599 hardware and newer");
4368                 return -ENOTSUP;
4369         }
4370         if (ixgbe_vmdq_mode_check(hw) < 0)
4371                 return -ENOTSUP;
4372
4373         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4374
4375         if (on)
4376                 vmolr |= val;
4377         else
4378                 vmolr &= ~val;
4379
4380         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4381
4382         return 0;
4383 }
4384
4385 static int
4386 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4387 {
4388         uint32_t reg,addr;
4389         uint32_t val;
4390         const uint8_t bit1 = 0x1;
4391
4392         struct ixgbe_hw *hw =
4393                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4394
4395         if (ixgbe_vmdq_mode_check(hw) < 0)
4396                 return -ENOTSUP;
4397
4398         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4399         reg = IXGBE_READ_REG(hw, addr);
4400         val = bit1 << pool;
4401
4402         if (on)
4403                 reg |= val;
4404         else
4405                 reg &= ~val;
4406
4407         IXGBE_WRITE_REG(hw, addr,reg);
4408
4409         return 0;
4410 }
4411
4412 static int
4413 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4414 {
4415         uint32_t reg,addr;
4416         uint32_t val;
4417         const uint8_t bit1 = 0x1;
4418
4419         struct ixgbe_hw *hw =
4420                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4421
4422         if (ixgbe_vmdq_mode_check(hw) < 0)
4423                 return -ENOTSUP;
4424
4425         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4426         reg = IXGBE_READ_REG(hw, addr);
4427         val = bit1 << pool;
4428
4429         if (on)
4430                 reg |= val;
4431         else
4432                 reg &= ~val;
4433
4434         IXGBE_WRITE_REG(hw, addr,reg);
4435
4436         return 0;
4437 }
4438
4439 static int
4440 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4441                         uint64_t pool_mask, uint8_t vlan_on)
4442 {
4443         int ret = 0;
4444         uint16_t pool_idx;
4445         struct ixgbe_hw *hw =
4446                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4447
4448         if (ixgbe_vmdq_mode_check(hw) < 0)
4449                 return -ENOTSUP;
4450         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4451                 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4452                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4453                         if (ret < 0)
4454                                 return ret;
4455                 }
4456         }
4457
4458         return ret;
4459 }
4460
4461 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4462 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4463 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4464 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4465 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4466         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4467         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4468
4469 static int
4470 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4471                         struct rte_eth_mirror_conf *mirror_conf,
4472                         uint8_t rule_id, uint8_t on)
4473 {
4474         uint32_t mr_ctl,vlvf;
4475         uint32_t mp_lsb = 0;
4476         uint32_t mv_msb = 0;
4477         uint32_t mv_lsb = 0;
4478         uint32_t mp_msb = 0;
4479         uint8_t i = 0;
4480         int reg_index = 0;
4481         uint64_t vlan_mask = 0;
4482
4483         const uint8_t pool_mask_offset = 32;
4484         const uint8_t vlan_mask_offset = 32;
4485         const uint8_t dst_pool_offset = 8;
4486         const uint8_t rule_mr_offset  = 4;
4487         const uint8_t mirror_rule_mask= 0x0F;
4488
4489         struct ixgbe_mirror_info *mr_info =
4490                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4491         struct ixgbe_hw *hw =
4492                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4493         uint8_t mirror_type = 0;
4494
4495         if (ixgbe_vmdq_mode_check(hw) < 0)
4496                 return -ENOTSUP;
4497
4498         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4499                 return -EINVAL;
4500
4501         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4502                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4503                         mirror_conf->rule_type);
4504                 return -EINVAL;
4505         }
4506
4507         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4508                 mirror_type |= IXGBE_MRCTL_VLME;
4509                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4510                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4511                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4512                                 /* search vlan id related pool vlan filter index */
4513                                 reg_index = ixgbe_find_vlvf_slot(hw,
4514                                                 mirror_conf->vlan.vlan_id[i]);
4515                                 if (reg_index < 0)
4516                                         return -EINVAL;
4517                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4518                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4519                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4520                                       mirror_conf->vlan.vlan_id[i]))
4521                                         vlan_mask |= (1ULL << reg_index);
4522                                 else
4523                                         return -EINVAL;
4524                         }
4525                 }
4526
4527                 if (on) {
4528                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4529                         mv_msb = vlan_mask >> vlan_mask_offset;
4530
4531                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4532                                                 mirror_conf->vlan.vlan_mask;
4533                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4534                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4535                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4536                                                 mirror_conf->vlan.vlan_id[i];
4537                         }
4538                 } else {
4539                         mv_lsb = 0;
4540                         mv_msb = 0;
4541                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4542                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4543                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4544                 }
4545         }
4546
4547         /*
4548          * if enable pool mirror, write related pool mask register,if disable
4549          * pool mirror, clear PFMRVM register
4550          */
4551         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4552                 mirror_type |= IXGBE_MRCTL_VPME;
4553                 if (on) {
4554                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4555                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4556                         mr_info->mr_conf[rule_id].pool_mask =
4557                                         mirror_conf->pool_mask;
4558
4559                 } else {
4560                         mp_lsb = 0;
4561                         mp_msb = 0;
4562                         mr_info->mr_conf[rule_id].pool_mask = 0;
4563                 }
4564         }
4565         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4566                 mirror_type |= IXGBE_MRCTL_UPME;
4567         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4568                 mirror_type |= IXGBE_MRCTL_DPME;
4569
4570         /* read  mirror control register and recalculate it */
4571         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4572
4573         if (on) {
4574                 mr_ctl |= mirror_type;
4575                 mr_ctl &= mirror_rule_mask;
4576                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4577         } else
4578                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4579
4580         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4581         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4582
4583         /* write mirrror control  register */
4584         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4585
4586         /* write pool mirrror control  register */
4587         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4588                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4589                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4590                                 mp_msb);
4591         }
4592         /* write VLAN mirrror control  register */
4593         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4594                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4595                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4596                                 mv_msb);
4597         }
4598
4599         return 0;
4600 }
4601
4602 static int
4603 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4604 {
4605         int mr_ctl = 0;
4606         uint32_t lsb_val = 0;
4607         uint32_t msb_val = 0;
4608         const uint8_t rule_mr_offset = 4;
4609
4610         struct ixgbe_hw *hw =
4611                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4612         struct ixgbe_mirror_info *mr_info =
4613                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4614
4615         if (ixgbe_vmdq_mode_check(hw) < 0)
4616                 return -ENOTSUP;
4617
4618         memset(&mr_info->mr_conf[rule_id], 0,
4619                 sizeof(struct rte_eth_mirror_conf));
4620
4621         /* clear PFVMCTL register */
4622         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4623
4624         /* clear pool mask register */
4625         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4626         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4627
4628         /* clear vlan mask register */
4629         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4630         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4631
4632         return 0;
4633 }
4634
4635 static int
4636 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4637 {
4638         uint32_t mask;
4639         struct ixgbe_hw *hw =
4640                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4641
4642         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4643         mask |= (1 << IXGBE_MISC_VEC_ID);
4644         RTE_SET_USED(queue_id);
4645         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4646
4647         rte_intr_enable(&dev->pci_dev->intr_handle);
4648
4649         return 0;
4650 }
4651
4652 static int
4653 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4654 {
4655         uint32_t mask;
4656         struct ixgbe_hw *hw =
4657                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4658
4659         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4660         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4661         RTE_SET_USED(queue_id);
4662         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4663
4664         return 0;
4665 }
4666
4667 static int
4668 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4669 {
4670         uint32_t mask;
4671         struct ixgbe_hw *hw =
4672                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4673         struct ixgbe_interrupt *intr =
4674                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4675
4676         if (queue_id < 16) {
4677                 ixgbe_disable_intr(hw);
4678                 intr->mask |= (1 << queue_id);
4679                 ixgbe_enable_intr(dev);
4680         } else if (queue_id < 32) {
4681                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4682                 mask &= (1 << queue_id);
4683                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4684         } else if (queue_id < 64) {
4685                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4686                 mask &= (1 << (queue_id - 32));
4687                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4688         }
4689         rte_intr_enable(&dev->pci_dev->intr_handle);
4690
4691         return 0;
4692 }
4693
4694 static int
4695 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4696 {
4697         uint32_t mask;
4698         struct ixgbe_hw *hw =
4699                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4700         struct ixgbe_interrupt *intr =
4701                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4702
4703         if (queue_id < 16) {
4704                 ixgbe_disable_intr(hw);
4705                 intr->mask &= ~(1 << queue_id);
4706                 ixgbe_enable_intr(dev);
4707         } else if (queue_id < 32) {
4708                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4709                 mask &= ~(1 << queue_id);
4710                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4711         } else if (queue_id < 64) {
4712                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4713                 mask &= ~(1 << (queue_id - 32));
4714                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4715         }
4716
4717         return 0;
4718 }
4719
4720 static void
4721 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4722                      uint8_t queue, uint8_t msix_vector)
4723 {
4724         uint32_t tmp, idx;
4725
4726         if (direction == -1) {
4727                 /* other causes */
4728                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4729                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4730                 tmp &= ~0xFF;
4731                 tmp |= msix_vector;
4732                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4733         } else {
4734                 /* rx or tx cause */
4735                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4736                 idx = ((16 * (queue & 1)) + (8 * direction));
4737                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4738                 tmp &= ~(0xFF << idx);
4739                 tmp |= (msix_vector << idx);
4740                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4741         }
4742 }
4743
4744 /**
4745  * set the IVAR registers, mapping interrupt causes to vectors
4746  * @param hw
4747  *  pointer to ixgbe_hw struct
4748  * @direction
4749  *  0 for Rx, 1 for Tx, -1 for other causes
4750  * @queue
4751  *  queue to map the corresponding interrupt to
4752  * @msix_vector
4753  *  the vector to map to the corresponding queue
4754  */
4755 static void
4756 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4757                    uint8_t queue, uint8_t msix_vector)
4758 {
4759         uint32_t tmp, idx;
4760
4761         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4762         if (hw->mac.type == ixgbe_mac_82598EB) {
4763                 if (direction == -1)
4764                         direction = 0;
4765                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4766                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4767                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4768                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4769                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4770         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4771                         (hw->mac.type == ixgbe_mac_X540)) {
4772                 if (direction == -1) {
4773                         /* other causes */
4774                         idx = ((queue & 1) * 8);
4775                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4776                         tmp &= ~(0xFF << idx);
4777                         tmp |= (msix_vector << idx);
4778                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4779                 } else {
4780                         /* rx or tx causes */
4781                         idx = ((16 * (queue & 1)) + (8 * direction));
4782                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4783                         tmp &= ~(0xFF << idx);
4784                         tmp |= (msix_vector << idx);
4785                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4786                 }
4787         }
4788 }
4789
4790 static void
4791 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4792 {
4793         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4794         struct ixgbe_hw *hw =
4795                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4796         uint32_t q_idx;
4797         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4798
4799         /* won't configure msix register if no mapping is done
4800          * between intr vector and event fd.
4801          */
4802         if (!rte_intr_dp_is_en(intr_handle))
4803                 return;
4804
4805         /* Configure all RX queues of VF */
4806         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4807                 /* Force all queue use vector 0,
4808                  * as IXGBE_VF_MAXMSIVECOTR = 1
4809                  */
4810                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4811                 intr_handle->intr_vec[q_idx] = vector_idx;
4812         }
4813
4814         /* Configure VF other cause ivar */
4815         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4816 }
4817
4818 /**
4819  * Sets up the hardware to properly generate MSI-X interrupts
4820  * @hw
4821  *  board private structure
4822  */
4823 static void
4824 ixgbe_configure_msix(struct rte_eth_dev *dev)
4825 {
4826         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4827         struct ixgbe_hw *hw =
4828                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4829         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4830         uint32_t vec = IXGBE_MISC_VEC_ID;
4831         uint32_t mask;
4832         uint32_t gpie;
4833
4834         /* won't configure msix register if no mapping is done
4835          * between intr vector and event fd
4836          */
4837         if (!rte_intr_dp_is_en(intr_handle))
4838                 return;
4839
4840         if (rte_intr_allow_others(intr_handle))
4841                 vec = base = IXGBE_RX_VEC_START;
4842
4843         /* setup GPIE for MSI-x mode */
4844         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4845         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4846                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4847         /* auto clearing and auto setting corresponding bits in EIMS
4848          * when MSI-X interrupt is triggered
4849          */
4850         if (hw->mac.type == ixgbe_mac_82598EB) {
4851                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4852         } else {
4853                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4854                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4855         }
4856         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4857
4858         /* Populate the IVAR table and set the ITR values to the
4859          * corresponding register.
4860          */
4861         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4862              queue_id++) {
4863                 /* by default, 1:1 mapping */
4864                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4865                 intr_handle->intr_vec[queue_id] = vec;
4866                 if (vec < base + intr_handle->nb_efd - 1)
4867                         vec++;
4868         }
4869
4870         switch (hw->mac.type) {
4871         case ixgbe_mac_82598EB:
4872                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4873                                    IXGBE_MISC_VEC_ID);
4874                 break;
4875         case ixgbe_mac_82599EB:
4876         case ixgbe_mac_X540:
4877                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4878                 break;
4879         default:
4880                 break;
4881         }
4882         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4883                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4884
4885         /* set up to autoclear timer, and the vectors */
4886         mask = IXGBE_EIMS_ENABLE_MASK;
4887         mask &= ~(IXGBE_EIMS_OTHER |
4888                   IXGBE_EIMS_MAILBOX |
4889                   IXGBE_EIMS_LSC);
4890
4891         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4892 }
4893
4894 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4895         uint16_t queue_idx, uint16_t tx_rate)
4896 {
4897         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4898         uint32_t rf_dec, rf_int;
4899         uint32_t bcnrc_val;
4900         uint16_t link_speed = dev->data->dev_link.link_speed;
4901
4902         if (queue_idx >= hw->mac.max_tx_queues)
4903                 return -EINVAL;
4904
4905         if (tx_rate != 0) {
4906                 /* Calculate the rate factor values to set */
4907                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4908                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4909                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4910
4911                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4912                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4913                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4914                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4915         } else {
4916                 bcnrc_val = 0;
4917         }
4918
4919         /*
4920          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4921          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4922          * set as 0x4.
4923          */
4924         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4925                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4926                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4927                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4928                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4929         else
4930                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4931                         IXGBE_MMW_SIZE_DEFAULT);
4932
4933         /* Set RTTBCNRC of queue X */
4934         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4935         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4936         IXGBE_WRITE_FLUSH(hw);
4937
4938         return 0;
4939 }
4940
4941 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4942         uint16_t tx_rate, uint64_t q_msk)
4943 {
4944         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4945         struct ixgbe_vf_info *vfinfo =
4946                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4947         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4948         uint32_t queue_stride =
4949                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4950         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4951         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4952         uint16_t total_rate = 0;
4953
4954         if (queue_end >= hw->mac.max_tx_queues)
4955                 return -EINVAL;
4956
4957         if (vfinfo != NULL) {
4958                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4959                         if (vf_idx == vf)
4960                                 continue;
4961                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4962                                 idx++)
4963                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4964                 }
4965         } else
4966                 return -EINVAL;
4967
4968         /* Store tx_rate for this vf. */
4969         for (idx = 0; idx < nb_q_per_pool; idx++) {
4970                 if (((uint64_t)0x1 << idx) & q_msk) {
4971                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
4972                                 vfinfo[vf].tx_rate[idx] = tx_rate;
4973                         total_rate += tx_rate;
4974                 }
4975         }
4976
4977         if (total_rate > dev->data->dev_link.link_speed) {
4978                 /*
4979                  * Reset stored TX rate of the VF if it causes exceed
4980                  * link speed.
4981                  */
4982                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4983                 return -EINVAL;
4984         }
4985
4986         /* Set RTTBCNRC of each queue/pool for vf X  */
4987         for (; queue_idx <= queue_end; queue_idx++) {
4988                 if (0x1 & q_msk)
4989                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4990                 q_msk = q_msk >> 1;
4991         }
4992
4993         return 0;
4994 }
4995
4996 static void
4997 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4998                      __attribute__((unused)) uint32_t index,
4999                      __attribute__((unused)) uint32_t pool)
5000 {
5001         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5002         int diag;
5003
5004         /*
5005          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5006          * operation. Trap this case to avoid exhausting the [very limited]
5007          * set of PF resources used to store VF MAC addresses.
5008          */
5009         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5010                 return;
5011         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5012         if (diag == 0)
5013                 return;
5014         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5015 }
5016
5017 static void
5018 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5019 {
5020         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5021         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5022         struct ether_addr *mac_addr;
5023         uint32_t i;
5024         int diag;
5025
5026         /*
5027          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5028          * not support the deletion of a given MAC address.
5029          * Instead, it imposes to delete all MAC addresses, then to add again
5030          * all MAC addresses with the exception of the one to be deleted.
5031          */
5032         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5033
5034         /*
5035          * Add again all MAC addresses, with the exception of the deleted one
5036          * and of the permanent MAC address.
5037          */
5038         for (i = 0, mac_addr = dev->data->mac_addrs;
5039              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5040                 /* Skip the deleted MAC address */
5041                 if (i == index)
5042                         continue;
5043                 /* Skip NULL MAC addresses */
5044                 if (is_zero_ether_addr(mac_addr))
5045                         continue;
5046                 /* Skip the permanent MAC address */
5047                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5048                         continue;
5049                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5050                 if (diag != 0)
5051                         PMD_DRV_LOG(ERR,
5052                                     "Adding again MAC address "
5053                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5054                                     "diag=%d",
5055                                     mac_addr->addr_bytes[0],
5056                                     mac_addr->addr_bytes[1],
5057                                     mac_addr->addr_bytes[2],
5058                                     mac_addr->addr_bytes[3],
5059                                     mac_addr->addr_bytes[4],
5060                                     mac_addr->addr_bytes[5],
5061                                     diag);
5062         }
5063 }
5064
5065 static void
5066 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5067 {
5068         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5069
5070         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5071 }
5072
5073 #define MAC_TYPE_FILTER_SUP(type)    do {\
5074         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5075                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5076                 (type) != ixgbe_mac_X550EM_a)\
5077                 return -ENOTSUP;\
5078 } while (0)
5079
5080 static int
5081 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5082                         struct rte_eth_syn_filter *filter,
5083                         bool add)
5084 {
5085         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5086         uint32_t synqf;
5087
5088         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5089                 return -EINVAL;
5090
5091         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5092
5093         if (add) {
5094                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5095                         return -EINVAL;
5096                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5097                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5098
5099                 if (filter->hig_pri)
5100                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5101                 else
5102                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5103         } else {
5104                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5105                         return -ENOENT;
5106                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5107         }
5108         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5109         IXGBE_WRITE_FLUSH(hw);
5110         return 0;
5111 }
5112
5113 static int
5114 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5115                         struct rte_eth_syn_filter *filter)
5116 {
5117         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5118         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5119
5120         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5121                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5122                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5123                 return 0;
5124         }
5125         return -ENOENT;
5126 }
5127
5128 static int
5129 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5130                         enum rte_filter_op filter_op,
5131                         void *arg)
5132 {
5133         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5134         int ret;
5135
5136         MAC_TYPE_FILTER_SUP(hw->mac.type);
5137
5138         if (filter_op == RTE_ETH_FILTER_NOP)
5139                 return 0;
5140
5141         if (arg == NULL) {
5142                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5143                             filter_op);
5144                 return -EINVAL;
5145         }
5146
5147         switch (filter_op) {
5148         case RTE_ETH_FILTER_ADD:
5149                 ret = ixgbe_syn_filter_set(dev,
5150                                 (struct rte_eth_syn_filter *)arg,
5151                                 TRUE);
5152                 break;
5153         case RTE_ETH_FILTER_DELETE:
5154                 ret = ixgbe_syn_filter_set(dev,
5155                                 (struct rte_eth_syn_filter *)arg,
5156                                 FALSE);
5157                 break;
5158         case RTE_ETH_FILTER_GET:
5159                 ret = ixgbe_syn_filter_get(dev,
5160                                 (struct rte_eth_syn_filter *)arg);
5161                 break;
5162         default:
5163                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5164                 ret = -EINVAL;
5165                 break;
5166         }
5167
5168         return ret;
5169 }
5170
5171
5172 static inline enum ixgbe_5tuple_protocol
5173 convert_protocol_type(uint8_t protocol_value)
5174 {
5175         if (protocol_value == IPPROTO_TCP)
5176                 return IXGBE_FILTER_PROTOCOL_TCP;
5177         else if (protocol_value == IPPROTO_UDP)
5178                 return IXGBE_FILTER_PROTOCOL_UDP;
5179         else if (protocol_value == IPPROTO_SCTP)
5180                 return IXGBE_FILTER_PROTOCOL_SCTP;
5181         else
5182                 return IXGBE_FILTER_PROTOCOL_NONE;
5183 }
5184
5185 /*
5186  * add a 5tuple filter
5187  *
5188  * @param
5189  * dev: Pointer to struct rte_eth_dev.
5190  * index: the index the filter allocates.
5191  * filter: ponter to the filter that will be added.
5192  * rx_queue: the queue id the filter assigned to.
5193  *
5194  * @return
5195  *    - On success, zero.
5196  *    - On failure, a negative value.
5197  */
5198 static int
5199 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5200                         struct ixgbe_5tuple_filter *filter)
5201 {
5202         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5203         struct ixgbe_filter_info *filter_info =
5204                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5205         int i, idx, shift;
5206         uint32_t ftqf, sdpqf;
5207         uint32_t l34timir = 0;
5208         uint8_t mask = 0xff;
5209
5210         /*
5211          * look for an unused 5tuple filter index,
5212          * and insert the filter to list.
5213          */
5214         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5215                 idx = i / (sizeof(uint32_t) * NBBY);
5216                 shift = i % (sizeof(uint32_t) * NBBY);
5217                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5218                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5219                         filter->index = i;
5220                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5221                                           filter,
5222                                           entries);
5223                         break;
5224                 }
5225         }
5226         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5227                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5228                 return -ENOSYS;
5229         }
5230
5231         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5232                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5233         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5234
5235         ftqf = (uint32_t)(filter->filter_info.proto &
5236                 IXGBE_FTQF_PROTOCOL_MASK);
5237         ftqf |= (uint32_t)((filter->filter_info.priority &
5238                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5239         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5240                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5241         if (filter->filter_info.dst_ip_mask == 0)
5242                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5243         if (filter->filter_info.src_port_mask == 0)
5244                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5245         if (filter->filter_info.dst_port_mask == 0)
5246                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5247         if (filter->filter_info.proto_mask == 0)
5248                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5249         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5250         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5251         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5252
5253         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5254         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5255         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5256         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5257
5258         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5259         l34timir |= (uint32_t)(filter->queue <<
5260                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5261         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5262         return 0;
5263 }
5264
5265 /*
5266  * remove a 5tuple filter
5267  *
5268  * @param
5269  * dev: Pointer to struct rte_eth_dev.
5270  * filter: the pointer of the filter will be removed.
5271  */
5272 static void
5273 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5274                         struct ixgbe_5tuple_filter *filter)
5275 {
5276         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5277         struct ixgbe_filter_info *filter_info =
5278                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5279         uint16_t index = filter->index;
5280
5281         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5282                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5283         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5284         rte_free(filter);
5285
5286         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5287         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5288         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5289         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5290         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5291 }
5292
5293 static int
5294 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5295 {
5296         struct ixgbe_hw *hw;
5297         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5298
5299         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5300
5301         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5302                 return -EINVAL;
5303
5304         /* refuse mtu that requires the support of scattered packets when this
5305          * feature has not been enabled before. */
5306         if (!dev->data->scattered_rx &&
5307             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5308              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5309                 return -EINVAL;
5310
5311         /*
5312          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5313          * request of the version 2.0 of the mailbox API.
5314          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5315          * of the mailbox API.
5316          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5317          * prior to 3.11.33 which contains the following change:
5318          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5319          */
5320         ixgbevf_rlpml_set_vf(hw, max_frame);
5321
5322         /* update max frame size */
5323         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5324         return 0;
5325 }
5326
5327 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5328         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5329                 return -ENOTSUP;\
5330 } while (0)
5331
5332 static inline struct ixgbe_5tuple_filter *
5333 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5334                         struct ixgbe_5tuple_filter_info *key)
5335 {
5336         struct ixgbe_5tuple_filter *it;
5337
5338         TAILQ_FOREACH(it, filter_list, entries) {
5339                 if (memcmp(key, &it->filter_info,
5340                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5341                         return it;
5342                 }
5343         }
5344         return NULL;
5345 }
5346
5347 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5348 static inline int
5349 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5350                         struct ixgbe_5tuple_filter_info *filter_info)
5351 {
5352         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5353                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5354                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5355                 return -EINVAL;
5356
5357         switch (filter->dst_ip_mask) {
5358         case UINT32_MAX:
5359                 filter_info->dst_ip_mask = 0;
5360                 filter_info->dst_ip = filter->dst_ip;
5361                 break;
5362         case 0:
5363                 filter_info->dst_ip_mask = 1;
5364                 break;
5365         default:
5366                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5367                 return -EINVAL;
5368         }
5369
5370         switch (filter->src_ip_mask) {
5371         case UINT32_MAX:
5372                 filter_info->src_ip_mask = 0;
5373                 filter_info->src_ip = filter->src_ip;
5374                 break;
5375         case 0:
5376                 filter_info->src_ip_mask = 1;
5377                 break;
5378         default:
5379                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5380                 return -EINVAL;
5381         }
5382
5383         switch (filter->dst_port_mask) {
5384         case UINT16_MAX:
5385                 filter_info->dst_port_mask = 0;
5386                 filter_info->dst_port = filter->dst_port;
5387                 break;
5388         case 0:
5389                 filter_info->dst_port_mask = 1;
5390                 break;
5391         default:
5392                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5393                 return -EINVAL;
5394         }
5395
5396         switch (filter->src_port_mask) {
5397         case UINT16_MAX:
5398                 filter_info->src_port_mask = 0;
5399                 filter_info->src_port = filter->src_port;
5400                 break;
5401         case 0:
5402                 filter_info->src_port_mask = 1;
5403                 break;
5404         default:
5405                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5406                 return -EINVAL;
5407         }
5408
5409         switch (filter->proto_mask) {
5410         case UINT8_MAX:
5411                 filter_info->proto_mask = 0;
5412                 filter_info->proto =
5413                         convert_protocol_type(filter->proto);
5414                 break;
5415         case 0:
5416                 filter_info->proto_mask = 1;
5417                 break;
5418         default:
5419                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5420                 return -EINVAL;
5421         }
5422
5423         filter_info->priority = (uint8_t)filter->priority;
5424         return 0;
5425 }
5426
5427 /*
5428  * add or delete a ntuple filter
5429  *
5430  * @param
5431  * dev: Pointer to struct rte_eth_dev.
5432  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5433  * add: if true, add filter, if false, remove filter
5434  *
5435  * @return
5436  *    - On success, zero.
5437  *    - On failure, a negative value.
5438  */
5439 static int
5440 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5441                         struct rte_eth_ntuple_filter *ntuple_filter,
5442                         bool add)
5443 {
5444         struct ixgbe_filter_info *filter_info =
5445                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5446         struct ixgbe_5tuple_filter_info filter_5tuple;
5447         struct ixgbe_5tuple_filter *filter;
5448         int ret;
5449
5450         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5451                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5452                 return -EINVAL;
5453         }
5454
5455         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5456         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5457         if (ret < 0)
5458                 return ret;
5459
5460         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5461                                          &filter_5tuple);
5462         if (filter != NULL && add) {
5463                 PMD_DRV_LOG(ERR, "filter exists.");
5464                 return -EEXIST;
5465         }
5466         if (filter == NULL && !add) {
5467                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5468                 return -ENOENT;
5469         }
5470
5471         if (add) {
5472                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5473                                 sizeof(struct ixgbe_5tuple_filter), 0);
5474                 if (filter == NULL)
5475                         return -ENOMEM;
5476                 (void)rte_memcpy(&filter->filter_info,
5477                                  &filter_5tuple,
5478                                  sizeof(struct ixgbe_5tuple_filter_info));
5479                 filter->queue = ntuple_filter->queue;
5480                 ret = ixgbe_add_5tuple_filter(dev, filter);
5481                 if (ret < 0) {
5482                         rte_free(filter);
5483                         return ret;
5484                 }
5485         } else
5486                 ixgbe_remove_5tuple_filter(dev, filter);
5487
5488         return 0;
5489 }
5490
5491 /*
5492  * get a ntuple filter
5493  *
5494  * @param
5495  * dev: Pointer to struct rte_eth_dev.
5496  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5497  *
5498  * @return
5499  *    - On success, zero.
5500  *    - On failure, a negative value.
5501  */
5502 static int
5503 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5504                         struct rte_eth_ntuple_filter *ntuple_filter)
5505 {
5506         struct ixgbe_filter_info *filter_info =
5507                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5508         struct ixgbe_5tuple_filter_info filter_5tuple;
5509         struct ixgbe_5tuple_filter *filter;
5510         int ret;
5511
5512         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5513                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5514                 return -EINVAL;
5515         }
5516
5517         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5518         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5519         if (ret < 0)
5520                 return ret;
5521
5522         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5523                                          &filter_5tuple);
5524         if (filter == NULL) {
5525                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5526                 return -ENOENT;
5527         }
5528         ntuple_filter->queue = filter->queue;
5529         return 0;
5530 }
5531
5532 /*
5533  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5534  * @dev: pointer to rte_eth_dev structure
5535  * @filter_op:operation will be taken.
5536  * @arg: a pointer to specific structure corresponding to the filter_op
5537  *
5538  * @return
5539  *    - On success, zero.
5540  *    - On failure, a negative value.
5541  */
5542 static int
5543 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5544                                 enum rte_filter_op filter_op,
5545                                 void *arg)
5546 {
5547         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5548         int ret;
5549
5550         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5551
5552         if (filter_op == RTE_ETH_FILTER_NOP)
5553                 return 0;
5554
5555         if (arg == NULL) {
5556                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5557                             filter_op);
5558                 return -EINVAL;
5559         }
5560
5561         switch (filter_op) {
5562         case RTE_ETH_FILTER_ADD:
5563                 ret = ixgbe_add_del_ntuple_filter(dev,
5564                         (struct rte_eth_ntuple_filter *)arg,
5565                         TRUE);
5566                 break;
5567         case RTE_ETH_FILTER_DELETE:
5568                 ret = ixgbe_add_del_ntuple_filter(dev,
5569                         (struct rte_eth_ntuple_filter *)arg,
5570                         FALSE);
5571                 break;
5572         case RTE_ETH_FILTER_GET:
5573                 ret = ixgbe_get_ntuple_filter(dev,
5574                         (struct rte_eth_ntuple_filter *)arg);
5575                 break;
5576         default:
5577                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5578                 ret = -EINVAL;
5579                 break;
5580         }
5581         return ret;
5582 }
5583
5584 static inline int
5585 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5586                         uint16_t ethertype)
5587 {
5588         int i;
5589
5590         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5591                 if (filter_info->ethertype_filters[i] == ethertype &&
5592                     (filter_info->ethertype_mask & (1 << i)))
5593                         return i;
5594         }
5595         return -1;
5596 }
5597
5598 static inline int
5599 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5600                         uint16_t ethertype)
5601 {
5602         int i;
5603
5604         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5605                 if (!(filter_info->ethertype_mask & (1 << i))) {
5606                         filter_info->ethertype_mask |= 1 << i;
5607                         filter_info->ethertype_filters[i] = ethertype;
5608                         return i;
5609                 }
5610         }
5611         return -1;
5612 }
5613
5614 static inline int
5615 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5616                         uint8_t idx)
5617 {
5618         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5619                 return -1;
5620         filter_info->ethertype_mask &= ~(1 << idx);
5621         filter_info->ethertype_filters[idx] = 0;
5622         return idx;
5623 }
5624
5625 static int
5626 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5627                         struct rte_eth_ethertype_filter *filter,
5628                         bool add)
5629 {
5630         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5631         struct ixgbe_filter_info *filter_info =
5632                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5633         uint32_t etqf = 0;
5634         uint32_t etqs = 0;
5635         int ret;
5636
5637         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5638                 return -EINVAL;
5639
5640         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5641                 filter->ether_type == ETHER_TYPE_IPv6) {
5642                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5643                         " ethertype filter.", filter->ether_type);
5644                 return -EINVAL;
5645         }
5646
5647         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5648                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5649                 return -EINVAL;
5650         }
5651         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5652                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5653                 return -EINVAL;
5654         }
5655
5656         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5657         if (ret >= 0 && add) {
5658                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5659                             filter->ether_type);
5660                 return -EEXIST;
5661         }
5662         if (ret < 0 && !add) {
5663                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5664                             filter->ether_type);
5665                 return -ENOENT;
5666         }
5667
5668         if (add) {
5669                 ret = ixgbe_ethertype_filter_insert(filter_info,
5670                         filter->ether_type);
5671                 if (ret < 0) {
5672                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5673                         return -ENOSYS;
5674                 }
5675                 etqf = IXGBE_ETQF_FILTER_EN;
5676                 etqf |= (uint32_t)filter->ether_type;
5677                 etqs |= (uint32_t)((filter->queue <<
5678                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5679                                     IXGBE_ETQS_RX_QUEUE);
5680                 etqs |= IXGBE_ETQS_QUEUE_EN;
5681         } else {
5682                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5683                 if (ret < 0)
5684                         return -ENOSYS;
5685         }
5686         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5687         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5688         IXGBE_WRITE_FLUSH(hw);
5689
5690         return 0;
5691 }
5692
5693 static int
5694 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5695                         struct rte_eth_ethertype_filter *filter)
5696 {
5697         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5698         struct ixgbe_filter_info *filter_info =
5699                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5700         uint32_t etqf, etqs;
5701         int ret;
5702
5703         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5704         if (ret < 0) {
5705                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5706                             filter->ether_type);
5707                 return -ENOENT;
5708         }
5709
5710         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5711         if (etqf & IXGBE_ETQF_FILTER_EN) {
5712                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5713                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5714                 filter->flags = 0;
5715                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5716                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5717                 return 0;
5718         }
5719         return -ENOENT;
5720 }
5721
5722 /*
5723  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5724  * @dev: pointer to rte_eth_dev structure
5725  * @filter_op:operation will be taken.
5726  * @arg: a pointer to specific structure corresponding to the filter_op
5727  */
5728 static int
5729 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5730                                 enum rte_filter_op filter_op,
5731                                 void *arg)
5732 {
5733         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5734         int ret;
5735
5736         MAC_TYPE_FILTER_SUP(hw->mac.type);
5737
5738         if (filter_op == RTE_ETH_FILTER_NOP)
5739                 return 0;
5740
5741         if (arg == NULL) {
5742                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5743                             filter_op);
5744                 return -EINVAL;
5745         }
5746
5747         switch (filter_op) {
5748         case RTE_ETH_FILTER_ADD:
5749                 ret = ixgbe_add_del_ethertype_filter(dev,
5750                         (struct rte_eth_ethertype_filter *)arg,
5751                         TRUE);
5752                 break;
5753         case RTE_ETH_FILTER_DELETE:
5754                 ret = ixgbe_add_del_ethertype_filter(dev,
5755                         (struct rte_eth_ethertype_filter *)arg,
5756                         FALSE);
5757                 break;
5758         case RTE_ETH_FILTER_GET:
5759                 ret = ixgbe_get_ethertype_filter(dev,
5760                         (struct rte_eth_ethertype_filter *)arg);
5761                 break;
5762         default:
5763                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5764                 ret = -EINVAL;
5765                 break;
5766         }
5767         return ret;
5768 }
5769
5770 static int
5771 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5772                      enum rte_filter_type filter_type,
5773                      enum rte_filter_op filter_op,
5774                      void *arg)
5775 {
5776         int ret = -EINVAL;
5777
5778         switch (filter_type) {
5779         case RTE_ETH_FILTER_NTUPLE:
5780                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5781                 break;
5782         case RTE_ETH_FILTER_ETHERTYPE:
5783                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5784                 break;
5785         case RTE_ETH_FILTER_SYN:
5786                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5787                 break;
5788         case RTE_ETH_FILTER_FDIR:
5789                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5790                 break;
5791         case RTE_ETH_FILTER_L2_TUNNEL:
5792                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5793                 break;
5794         default:
5795                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5796                                                         filter_type);
5797                 break;
5798         }
5799
5800         return ret;
5801 }
5802
5803 static u8 *
5804 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5805                         u8 **mc_addr_ptr, u32 *vmdq)
5806 {
5807         u8 *mc_addr;
5808
5809         *vmdq = 0;
5810         mc_addr = *mc_addr_ptr;
5811         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5812         return mc_addr;
5813 }
5814
5815 static int
5816 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5817                           struct ether_addr *mc_addr_set,
5818                           uint32_t nb_mc_addr)
5819 {
5820         struct ixgbe_hw *hw;
5821         u8 *mc_addr_list;
5822
5823         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5824         mc_addr_list = (u8 *)mc_addr_set;
5825         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5826                                          ixgbe_dev_addr_list_itr, TRUE);
5827 }
5828
5829 static uint64_t
5830 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5831 {
5832         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5833         uint64_t systime_cycles;
5834
5835         switch (hw->mac.type) {
5836         case ixgbe_mac_X550:
5837         case ixgbe_mac_X550EM_x:
5838         case ixgbe_mac_X550EM_a:
5839                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5840                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5841                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5842                                 * NSEC_PER_SEC;
5843                 break;
5844         default:
5845                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5846                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5847                                 << 32;
5848         }
5849
5850         return systime_cycles;
5851 }
5852
5853 static uint64_t
5854 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5855 {
5856         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5857         uint64_t rx_tstamp_cycles;
5858
5859         switch (hw->mac.type) {
5860         case ixgbe_mac_X550:
5861         case ixgbe_mac_X550EM_x:
5862         case ixgbe_mac_X550EM_a:
5863                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5864                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5865                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5866                                 * NSEC_PER_SEC;
5867                 break;
5868         default:
5869                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5870                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5871                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5872                                 << 32;
5873         }
5874
5875         return rx_tstamp_cycles;
5876 }
5877
5878 static uint64_t
5879 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5880 {
5881         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5882         uint64_t tx_tstamp_cycles;
5883
5884         switch (hw->mac.type) {
5885         case ixgbe_mac_X550:
5886         case ixgbe_mac_X550EM_x:
5887         case ixgbe_mac_X550EM_a:
5888                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5889                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5890                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5891                                 * NSEC_PER_SEC;
5892                 break;
5893         default:
5894                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5895                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5896                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5897                                 << 32;
5898         }
5899
5900         return tx_tstamp_cycles;
5901 }
5902
5903 static void
5904 ixgbe_start_timecounters(struct rte_eth_dev *dev)
5905 {
5906         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5907         struct ixgbe_adapter *adapter =
5908                 (struct ixgbe_adapter *)dev->data->dev_private;
5909         struct rte_eth_link link;
5910         uint32_t incval = 0;
5911         uint32_t shift = 0;
5912
5913         /* Get current link speed. */
5914         memset(&link, 0, sizeof(link));
5915         ixgbe_dev_link_update(dev, 1);
5916         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
5917
5918         switch (link.link_speed) {
5919         case ETH_SPEED_NUM_100M:
5920                 incval = IXGBE_INCVAL_100;
5921                 shift = IXGBE_INCVAL_SHIFT_100;
5922                 break;
5923         case ETH_SPEED_NUM_1G:
5924                 incval = IXGBE_INCVAL_1GB;
5925                 shift = IXGBE_INCVAL_SHIFT_1GB;
5926                 break;
5927         case ETH_SPEED_NUM_10G:
5928         default:
5929                 incval = IXGBE_INCVAL_10GB;
5930                 shift = IXGBE_INCVAL_SHIFT_10GB;
5931                 break;
5932         }
5933
5934         switch (hw->mac.type) {
5935         case ixgbe_mac_X550:
5936         case ixgbe_mac_X550EM_x:
5937         case ixgbe_mac_X550EM_a:
5938                 /* Independent of link speed. */
5939                 incval = 1;
5940                 /* Cycles read will be interpreted as ns. */
5941                 shift = 0;
5942                 /* Fall-through */
5943         case ixgbe_mac_X540:
5944                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
5945                 break;
5946         case ixgbe_mac_82599EB:
5947                 incval >>= IXGBE_INCVAL_SHIFT_82599;
5948                 shift -= IXGBE_INCVAL_SHIFT_82599;
5949                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
5950                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
5951                 break;
5952         default:
5953                 /* Not supported. */
5954                 return;
5955         }
5956
5957         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5958         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5959         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5960
5961         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5962         adapter->systime_tc.cc_shift = shift;
5963         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5964
5965         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5966         adapter->rx_tstamp_tc.cc_shift = shift;
5967         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5968
5969         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5970         adapter->tx_tstamp_tc.cc_shift = shift;
5971         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5972 }
5973
5974 static int
5975 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5976 {
5977         struct ixgbe_adapter *adapter =
5978                         (struct ixgbe_adapter *)dev->data->dev_private;
5979
5980         adapter->systime_tc.nsec += delta;
5981         adapter->rx_tstamp_tc.nsec += delta;
5982         adapter->tx_tstamp_tc.nsec += delta;
5983
5984         return 0;
5985 }
5986
5987 static int
5988 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5989 {
5990         uint64_t ns;
5991         struct ixgbe_adapter *adapter =
5992                         (struct ixgbe_adapter *)dev->data->dev_private;
5993
5994         ns = rte_timespec_to_ns(ts);
5995         /* Set the timecounters to a new value. */
5996         adapter->systime_tc.nsec = ns;
5997         adapter->rx_tstamp_tc.nsec = ns;
5998         adapter->tx_tstamp_tc.nsec = ns;
5999
6000         return 0;
6001 }
6002
6003 static int
6004 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6005 {
6006         uint64_t ns, systime_cycles;
6007         struct ixgbe_adapter *adapter =
6008                         (struct ixgbe_adapter *)dev->data->dev_private;
6009
6010         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6011         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6012         *ts = rte_ns_to_timespec(ns);
6013
6014         return 0;
6015 }
6016
6017 static int
6018 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6019 {
6020         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6021         uint32_t tsync_ctl;
6022         uint32_t tsauxc;
6023
6024         /* Stop the timesync system time. */
6025         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6026         /* Reset the timesync system time value. */
6027         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6028         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6029
6030         /* Enable system time for platforms where it isn't on by default. */
6031         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6032         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6033         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6034
6035         ixgbe_start_timecounters(dev);
6036
6037         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6038         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6039                         (ETHER_TYPE_1588 |
6040                          IXGBE_ETQF_FILTER_EN |
6041                          IXGBE_ETQF_1588));
6042
6043         /* Enable timestamping of received PTP packets. */
6044         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6045         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6046         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6047
6048         /* Enable timestamping of transmitted PTP packets. */
6049         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6050         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6051         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6052
6053         IXGBE_WRITE_FLUSH(hw);
6054
6055         return 0;
6056 }
6057
6058 static int
6059 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6060 {
6061         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6062         uint32_t tsync_ctl;
6063
6064         /* Disable timestamping of transmitted PTP packets. */
6065         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6066         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6067         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6068
6069         /* Disable timestamping of received PTP packets. */
6070         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6071         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6072         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6073
6074         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6075         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6076
6077         /* Stop incrementating the System Time registers. */
6078         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6079
6080         return 0;
6081 }
6082
6083 static int
6084 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6085                                  struct timespec *timestamp,
6086                                  uint32_t flags __rte_unused)
6087 {
6088         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6089         struct ixgbe_adapter *adapter =
6090                 (struct ixgbe_adapter *)dev->data->dev_private;
6091         uint32_t tsync_rxctl;
6092         uint64_t rx_tstamp_cycles;
6093         uint64_t ns;
6094
6095         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6096         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6097                 return -EINVAL;
6098
6099         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6100         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6101         *timestamp = rte_ns_to_timespec(ns);
6102
6103         return  0;
6104 }
6105
6106 static int
6107 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6108                                  struct timespec *timestamp)
6109 {
6110         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6111         struct ixgbe_adapter *adapter =
6112                 (struct ixgbe_adapter *)dev->data->dev_private;
6113         uint32_t tsync_txctl;
6114         uint64_t tx_tstamp_cycles;
6115         uint64_t ns;
6116
6117         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6118         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6119                 return -EINVAL;
6120
6121         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6122         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6123         *timestamp = rte_ns_to_timespec(ns);
6124
6125         return 0;
6126 }
6127
6128 static int
6129 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6130 {
6131         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6132         int count = 0;
6133         int g_ind = 0;
6134         const struct reg_info *reg_group;
6135         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6136                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6137
6138         while ((reg_group = reg_set[g_ind++]))
6139                 count += ixgbe_regs_group_count(reg_group);
6140
6141         return count;
6142 }
6143
6144 static int
6145 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6146 {
6147         int count = 0;
6148         int g_ind = 0;
6149         const struct reg_info *reg_group;
6150
6151         while ((reg_group = ixgbevf_regs[g_ind++]))
6152                 count += ixgbe_regs_group_count(reg_group);
6153
6154         return count;
6155 }
6156
6157 static int
6158 ixgbe_get_regs(struct rte_eth_dev *dev,
6159               struct rte_dev_reg_info *regs)
6160 {
6161         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6162         uint32_t *data = regs->data;
6163         int g_ind = 0;
6164         int count = 0;
6165         const struct reg_info *reg_group;
6166         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6167                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6168
6169         /* Support only full register dump */
6170         if ((regs->length == 0) ||
6171             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6172                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6173                         hw->device_id;
6174                 while ((reg_group = reg_set[g_ind++]))
6175                         count += ixgbe_read_regs_group(dev, &data[count],
6176                                 reg_group);
6177                 return 0;
6178         }
6179
6180         return -ENOTSUP;
6181 }
6182
6183 static int
6184 ixgbevf_get_regs(struct rte_eth_dev *dev,
6185                 struct rte_dev_reg_info *regs)
6186 {
6187         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6188         uint32_t *data = regs->data;
6189         int g_ind = 0;
6190         int count = 0;
6191         const struct reg_info *reg_group;
6192
6193         /* Support only full register dump */
6194         if ((regs->length == 0) ||
6195             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6196                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6197                         hw->device_id;
6198                 while ((reg_group = ixgbevf_regs[g_ind++]))
6199                         count += ixgbe_read_regs_group(dev, &data[count],
6200                                                       reg_group);
6201                 return 0;
6202         }
6203
6204         return -ENOTSUP;
6205 }
6206
6207 static int
6208 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6209 {
6210         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6211
6212         /* Return unit is byte count */
6213         return hw->eeprom.word_size * 2;
6214 }
6215
6216 static int
6217 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6218                 struct rte_dev_eeprom_info *in_eeprom)
6219 {
6220         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6221         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6222         uint16_t *data = in_eeprom->data;
6223         int first, length;
6224
6225         first = in_eeprom->offset >> 1;
6226         length = in_eeprom->length >> 1;
6227         if ((first > hw->eeprom.word_size) ||
6228             ((first + length) > hw->eeprom.word_size))
6229                 return -EINVAL;
6230
6231         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6232
6233         return eeprom->ops.read_buffer(hw, first, length, data);
6234 }
6235
6236 static int
6237 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6238                 struct rte_dev_eeprom_info *in_eeprom)
6239 {
6240         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6241         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6242         uint16_t *data = in_eeprom->data;
6243         int first, length;
6244
6245         first = in_eeprom->offset >> 1;
6246         length = in_eeprom->length >> 1;
6247         if ((first > hw->eeprom.word_size) ||
6248             ((first + length) > hw->eeprom.word_size))
6249                 return -EINVAL;
6250
6251         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6252
6253         return eeprom->ops.write_buffer(hw,  first, length, data);
6254 }
6255
6256 uint16_t
6257 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6258         switch (mac_type) {
6259         case ixgbe_mac_X550:
6260         case ixgbe_mac_X550EM_x:
6261         case ixgbe_mac_X550EM_a:
6262                 return ETH_RSS_RETA_SIZE_512;
6263         case ixgbe_mac_X550_vf:
6264         case ixgbe_mac_X550EM_x_vf:
6265         case ixgbe_mac_X550EM_a_vf:
6266                 return ETH_RSS_RETA_SIZE_64;
6267         default:
6268                 return ETH_RSS_RETA_SIZE_128;
6269         }
6270 }
6271
6272 uint32_t
6273 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6274         switch (mac_type) {
6275         case ixgbe_mac_X550:
6276         case ixgbe_mac_X550EM_x:
6277         case ixgbe_mac_X550EM_a:
6278                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6279                         return IXGBE_RETA(reta_idx >> 2);
6280                 else
6281                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6282         case ixgbe_mac_X550_vf:
6283         case ixgbe_mac_X550EM_x_vf:
6284         case ixgbe_mac_X550EM_a_vf:
6285                 return IXGBE_VFRETA(reta_idx >> 2);
6286         default:
6287                 return IXGBE_RETA(reta_idx >> 2);
6288         }
6289 }
6290
6291 uint32_t
6292 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6293         switch (mac_type) {
6294         case ixgbe_mac_X550_vf:
6295         case ixgbe_mac_X550EM_x_vf:
6296         case ixgbe_mac_X550EM_a_vf:
6297                 return IXGBE_VFMRQC;
6298         default:
6299                 return IXGBE_MRQC;
6300         }
6301 }
6302
6303 uint32_t
6304 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6305         switch (mac_type) {
6306         case ixgbe_mac_X550_vf:
6307         case ixgbe_mac_X550EM_x_vf:
6308         case ixgbe_mac_X550EM_a_vf:
6309                 return IXGBE_VFRSSRK(i);
6310         default:
6311                 return IXGBE_RSSRK(i);
6312         }
6313 }
6314
6315 bool
6316 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6317         switch (mac_type) {
6318         case ixgbe_mac_82599_vf:
6319         case ixgbe_mac_X540_vf:
6320                 return 0;
6321         default:
6322                 return 1;
6323         }
6324 }
6325
6326 static int
6327 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6328                         struct rte_eth_dcb_info *dcb_info)
6329 {
6330         struct ixgbe_dcb_config *dcb_config =
6331                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6332         struct ixgbe_dcb_tc_config *tc;
6333         uint8_t i, j;
6334
6335         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6336                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6337         else
6338                 dcb_info->nb_tcs = 1;
6339
6340         if (dcb_config->vt_mode) { /* vt is enabled*/
6341                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6342                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6343                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6344                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6345                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6346                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6347                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6348                                                 i * dcb_info->nb_tcs + j;
6349                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6350                                 dcb_info->tc_queue.tc_txq[i][j].base =
6351                                                 i * dcb_info->nb_tcs + j;
6352                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6353                         }
6354                 }
6355         } else { /* vt is disabled*/
6356                 struct rte_eth_dcb_rx_conf *rx_conf =
6357                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6358                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6359                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6360                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6361                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6362                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6363                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6364                         }
6365                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6366                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6367                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6368                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6369                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6370                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6371                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6372                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6373                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6374                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6375                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6376                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6377                         }
6378                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6379                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6380                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6381                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6382                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6383                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6384                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6385                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6386                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6387                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6388                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6389                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6390                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6391                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6392                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6393                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6394                 }
6395         }
6396         for (i = 0; i < dcb_info->nb_tcs; i++) {
6397                 tc = &dcb_config->tc_config[i];
6398                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6399         }
6400         return 0;
6401 }
6402
6403 /* Update e-tag ether type */
6404 static int
6405 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6406                             uint16_t ether_type)
6407 {
6408         uint32_t etag_etype;
6409
6410         if (hw->mac.type != ixgbe_mac_X550 &&
6411             hw->mac.type != ixgbe_mac_X550EM_x &&
6412             hw->mac.type != ixgbe_mac_X550EM_a) {
6413                 return -ENOTSUP;
6414         }
6415
6416         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6417         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6418         etag_etype |= ether_type;
6419         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6420         IXGBE_WRITE_FLUSH(hw);
6421
6422         return 0;
6423 }
6424
6425 /* Config l2 tunnel ether type */
6426 static int
6427 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6428                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6429 {
6430         int ret = 0;
6431         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6432
6433         if (l2_tunnel == NULL)
6434                 return -EINVAL;
6435
6436         switch (l2_tunnel->l2_tunnel_type) {
6437         case RTE_L2_TUNNEL_TYPE_E_TAG:
6438                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6439                 break;
6440         default:
6441                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6442                 ret = -EINVAL;
6443                 break;
6444         }
6445
6446         return ret;
6447 }
6448
6449 /* Enable e-tag tunnel */
6450 static int
6451 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6452 {
6453         uint32_t etag_etype;
6454
6455         if (hw->mac.type != ixgbe_mac_X550 &&
6456             hw->mac.type != ixgbe_mac_X550EM_x &&
6457             hw->mac.type != ixgbe_mac_X550EM_a) {
6458                 return -ENOTSUP;
6459         }
6460
6461         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6462         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6463         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6464         IXGBE_WRITE_FLUSH(hw);
6465
6466         return 0;
6467 }
6468
6469 /* Enable l2 tunnel */
6470 static int
6471 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6472                            enum rte_eth_tunnel_type l2_tunnel_type)
6473 {
6474         int ret = 0;
6475         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6476
6477         switch (l2_tunnel_type) {
6478         case RTE_L2_TUNNEL_TYPE_E_TAG:
6479                 ret = ixgbe_e_tag_enable(hw);
6480                 break;
6481         default:
6482                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6483                 ret = -EINVAL;
6484                 break;
6485         }
6486
6487         return ret;
6488 }
6489
6490 /* Disable e-tag tunnel */
6491 static int
6492 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6493 {
6494         uint32_t etag_etype;
6495
6496         if (hw->mac.type != ixgbe_mac_X550 &&
6497             hw->mac.type != ixgbe_mac_X550EM_x &&
6498             hw->mac.type != ixgbe_mac_X550EM_a) {
6499                 return -ENOTSUP;
6500         }
6501
6502         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6503         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6504         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6505         IXGBE_WRITE_FLUSH(hw);
6506
6507         return 0;
6508 }
6509
6510 /* Disable l2 tunnel */
6511 static int
6512 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6513                             enum rte_eth_tunnel_type l2_tunnel_type)
6514 {
6515         int ret = 0;
6516         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6517
6518         switch (l2_tunnel_type) {
6519         case RTE_L2_TUNNEL_TYPE_E_TAG:
6520                 ret = ixgbe_e_tag_disable(hw);
6521                 break;
6522         default:
6523                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6524                 ret = -EINVAL;
6525                 break;
6526         }
6527
6528         return ret;
6529 }
6530
6531 static int
6532 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6533                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6534 {
6535         int ret = 0;
6536         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6537         uint32_t i, rar_entries;
6538         uint32_t rar_low, rar_high;
6539
6540         if (hw->mac.type != ixgbe_mac_X550 &&
6541             hw->mac.type != ixgbe_mac_X550EM_x &&
6542             hw->mac.type != ixgbe_mac_X550EM_a) {
6543                 return -ENOTSUP;
6544         }
6545
6546         rar_entries = ixgbe_get_num_rx_addrs(hw);
6547
6548         for (i = 1; i < rar_entries; i++) {
6549                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6550                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6551                 if ((rar_high & IXGBE_RAH_AV) &&
6552                     (rar_high & IXGBE_RAH_ADTYPE) &&
6553                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6554                      l2_tunnel->tunnel_id)) {
6555                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6556                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6557
6558                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6559
6560                         return ret;
6561                 }
6562         }
6563
6564         return ret;
6565 }
6566
6567 static int
6568 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6569                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6570 {
6571         int ret = 0;
6572         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6573         uint32_t i, rar_entries;
6574         uint32_t rar_low, rar_high;
6575
6576         if (hw->mac.type != ixgbe_mac_X550 &&
6577             hw->mac.type != ixgbe_mac_X550EM_x &&
6578             hw->mac.type != ixgbe_mac_X550EM_a) {
6579                 return -ENOTSUP;
6580         }
6581
6582         /* One entry for one tunnel. Try to remove potential existing entry. */
6583         ixgbe_e_tag_filter_del(dev, l2_tunnel);
6584
6585         rar_entries = ixgbe_get_num_rx_addrs(hw);
6586
6587         for (i = 1; i < rar_entries; i++) {
6588                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6589                 if (rar_high & IXGBE_RAH_AV) {
6590                         continue;
6591                 } else {
6592                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6593                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6594                         rar_low = l2_tunnel->tunnel_id;
6595
6596                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6597                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6598
6599                         return ret;
6600                 }
6601         }
6602
6603         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6604                      " Please remove a rule before adding a new one.");
6605         return -EINVAL;
6606 }
6607
6608 /* Add l2 tunnel filter */
6609 static int
6610 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6611                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6612 {
6613         int ret = 0;
6614
6615         switch (l2_tunnel->l2_tunnel_type) {
6616         case RTE_L2_TUNNEL_TYPE_E_TAG:
6617                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6618                 break;
6619         default:
6620                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6621                 ret = -EINVAL;
6622                 break;
6623         }
6624
6625         return ret;
6626 }
6627
6628 /* Delete l2 tunnel filter */
6629 static int
6630 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6631                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6632 {
6633         int ret = 0;
6634
6635         switch (l2_tunnel->l2_tunnel_type) {
6636         case RTE_L2_TUNNEL_TYPE_E_TAG:
6637                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6638                 break;
6639         default:
6640                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6641                 ret = -EINVAL;
6642                 break;
6643         }
6644
6645         return ret;
6646 }
6647
6648 /**
6649  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6650  * @dev: pointer to rte_eth_dev structure
6651  * @filter_op:operation will be taken.
6652  * @arg: a pointer to specific structure corresponding to the filter_op
6653  */
6654 static int
6655 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6656                                   enum rte_filter_op filter_op,
6657                                   void *arg)
6658 {
6659         int ret = 0;
6660
6661         if (filter_op == RTE_ETH_FILTER_NOP)
6662                 return 0;
6663
6664         if (arg == NULL) {
6665                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6666                             filter_op);
6667                 return -EINVAL;
6668         }
6669
6670         switch (filter_op) {
6671         case RTE_ETH_FILTER_ADD:
6672                 ret = ixgbe_dev_l2_tunnel_filter_add
6673                         (dev,
6674                          (struct rte_eth_l2_tunnel_conf *)arg);
6675                 break;
6676         case RTE_ETH_FILTER_DELETE:
6677                 ret = ixgbe_dev_l2_tunnel_filter_del
6678                         (dev,
6679                          (struct rte_eth_l2_tunnel_conf *)arg);
6680                 break;
6681         default:
6682                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6683                 ret = -EINVAL;
6684                 break;
6685         }
6686         return ret;
6687 }
6688
6689 static int
6690 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6691 {
6692         int ret = 0;
6693         uint32_t ctrl;
6694         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6695
6696         if (hw->mac.type != ixgbe_mac_X550 &&
6697             hw->mac.type != ixgbe_mac_X550EM_x &&
6698             hw->mac.type != ixgbe_mac_X550EM_a) {
6699                 return -ENOTSUP;
6700         }
6701
6702         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6703         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6704         if (en)
6705                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6706         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6707
6708         return ret;
6709 }
6710
6711 /* Enable l2 tunnel forwarding */
6712 static int
6713 ixgbe_dev_l2_tunnel_forwarding_enable
6714         (struct rte_eth_dev *dev,
6715          enum rte_eth_tunnel_type l2_tunnel_type)
6716 {
6717         int ret = 0;
6718
6719         switch (l2_tunnel_type) {
6720         case RTE_L2_TUNNEL_TYPE_E_TAG:
6721                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6722                 break;
6723         default:
6724                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6725                 ret = -EINVAL;
6726                 break;
6727         }
6728
6729         return ret;
6730 }
6731
6732 /* Disable l2 tunnel forwarding */
6733 static int
6734 ixgbe_dev_l2_tunnel_forwarding_disable
6735         (struct rte_eth_dev *dev,
6736          enum rte_eth_tunnel_type l2_tunnel_type)
6737 {
6738         int ret = 0;
6739
6740         switch (l2_tunnel_type) {
6741         case RTE_L2_TUNNEL_TYPE_E_TAG:
6742                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6743                 break;
6744         default:
6745                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6746                 ret = -EINVAL;
6747                 break;
6748         }
6749
6750         return ret;
6751 }
6752
6753 static int
6754 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6755                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
6756                              bool en)
6757 {
6758         int ret = 0;
6759         uint32_t vmtir, vmvir;
6760         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6761
6762         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6763                 PMD_DRV_LOG(ERR,
6764                             "VF id %u should be less than %u",
6765                             l2_tunnel->vf_id,
6766                             dev->pci_dev->max_vfs);
6767                 return -EINVAL;
6768         }
6769
6770         if (hw->mac.type != ixgbe_mac_X550 &&
6771             hw->mac.type != ixgbe_mac_X550EM_x &&
6772             hw->mac.type != ixgbe_mac_X550EM_a) {
6773                 return -ENOTSUP;
6774         }
6775
6776         if (en)
6777                 vmtir = l2_tunnel->tunnel_id;
6778         else
6779                 vmtir = 0;
6780
6781         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6782
6783         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6784         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6785         if (en)
6786                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6787         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6788
6789         return ret;
6790 }
6791
6792 /* Enable l2 tunnel tag insertion */
6793 static int
6794 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6795                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
6796 {
6797         int ret = 0;
6798
6799         switch (l2_tunnel->l2_tunnel_type) {
6800         case RTE_L2_TUNNEL_TYPE_E_TAG:
6801                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6802                 break;
6803         default:
6804                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6805                 ret = -EINVAL;
6806                 break;
6807         }
6808
6809         return ret;
6810 }
6811
6812 /* Disable l2 tunnel tag insertion */
6813 static int
6814 ixgbe_dev_l2_tunnel_insertion_disable
6815         (struct rte_eth_dev *dev,
6816          struct rte_eth_l2_tunnel_conf *l2_tunnel)
6817 {
6818         int ret = 0;
6819
6820         switch (l2_tunnel->l2_tunnel_type) {
6821         case RTE_L2_TUNNEL_TYPE_E_TAG:
6822                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6823                 break;
6824         default:
6825                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6826                 ret = -EINVAL;
6827                 break;
6828         }
6829
6830         return ret;
6831 }
6832
6833 static int
6834 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6835                              bool en)
6836 {
6837         int ret = 0;
6838         uint32_t qde;
6839         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6840
6841         if (hw->mac.type != ixgbe_mac_X550 &&
6842             hw->mac.type != ixgbe_mac_X550EM_x &&
6843             hw->mac.type != ixgbe_mac_X550EM_a) {
6844                 return -ENOTSUP;
6845         }
6846
6847         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
6848         if (en)
6849                 qde |= IXGBE_QDE_STRIP_TAG;
6850         else
6851                 qde &= ~IXGBE_QDE_STRIP_TAG;
6852         qde &= ~IXGBE_QDE_READ;
6853         qde |= IXGBE_QDE_WRITE;
6854         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
6855
6856         return ret;
6857 }
6858
6859 /* Enable l2 tunnel tag stripping */
6860 static int
6861 ixgbe_dev_l2_tunnel_stripping_enable
6862         (struct rte_eth_dev *dev,
6863          enum rte_eth_tunnel_type l2_tunnel_type)
6864 {
6865         int ret = 0;
6866
6867         switch (l2_tunnel_type) {
6868         case RTE_L2_TUNNEL_TYPE_E_TAG:
6869                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
6870                 break;
6871         default:
6872                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6873                 ret = -EINVAL;
6874                 break;
6875         }
6876
6877         return ret;
6878 }
6879
6880 /* Disable l2 tunnel tag stripping */
6881 static int
6882 ixgbe_dev_l2_tunnel_stripping_disable
6883         (struct rte_eth_dev *dev,
6884          enum rte_eth_tunnel_type l2_tunnel_type)
6885 {
6886         int ret = 0;
6887
6888         switch (l2_tunnel_type) {
6889         case RTE_L2_TUNNEL_TYPE_E_TAG:
6890                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
6891                 break;
6892         default:
6893                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6894                 ret = -EINVAL;
6895                 break;
6896         }
6897
6898         return ret;
6899 }
6900
6901 /* Enable/disable l2 tunnel offload functions */
6902 static int
6903 ixgbe_dev_l2_tunnel_offload_set
6904         (struct rte_eth_dev *dev,
6905          struct rte_eth_l2_tunnel_conf *l2_tunnel,
6906          uint32_t mask,
6907          uint8_t en)
6908 {
6909         int ret = 0;
6910
6911         if (l2_tunnel == NULL)
6912                 return -EINVAL;
6913
6914         ret = -EINVAL;
6915         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
6916                 if (en)
6917                         ret = ixgbe_dev_l2_tunnel_enable(
6918                                 dev,
6919                                 l2_tunnel->l2_tunnel_type);
6920                 else
6921                         ret = ixgbe_dev_l2_tunnel_disable(
6922                                 dev,
6923                                 l2_tunnel->l2_tunnel_type);
6924         }
6925
6926         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
6927                 if (en)
6928                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
6929                                 dev,
6930                                 l2_tunnel);
6931                 else
6932                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
6933                                 dev,
6934                                 l2_tunnel);
6935         }
6936
6937         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
6938                 if (en)
6939                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
6940                                 dev,
6941                                 l2_tunnel->l2_tunnel_type);
6942                 else
6943                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
6944                                 dev,
6945                                 l2_tunnel->l2_tunnel_type);
6946         }
6947
6948         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
6949                 if (en)
6950                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
6951                                 dev,
6952                                 l2_tunnel->l2_tunnel_type);
6953                 else
6954                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
6955                                 dev,
6956                                 l2_tunnel->l2_tunnel_type);
6957         }
6958
6959         return ret;
6960 }
6961
6962 static int
6963 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
6964                         uint16_t port)
6965 {
6966         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
6967         IXGBE_WRITE_FLUSH(hw);
6968
6969         return 0;
6970 }
6971
6972 /* There's only one register for VxLAN UDP port.
6973  * So, we cannot add several ports. Will update it.
6974  */
6975 static int
6976 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
6977                      uint16_t port)
6978 {
6979         if (port == 0) {
6980                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
6981                 return -EINVAL;
6982         }
6983
6984         return ixgbe_update_vxlan_port(hw, port);
6985 }
6986
6987 /* We cannot delete the VxLAN port. For there's a register for VxLAN
6988  * UDP port, it must have a value.
6989  * So, will reset it to the original value 0.
6990  */
6991 static int
6992 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
6993                      uint16_t port)
6994 {
6995         uint16_t cur_port;
6996
6997         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
6998
6999         if (cur_port != port) {
7000                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7001                 return -EINVAL;
7002         }
7003
7004         return ixgbe_update_vxlan_port(hw, 0);
7005 }
7006
7007 /* Add UDP tunneling port */
7008 static int
7009 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7010                               struct rte_eth_udp_tunnel *udp_tunnel)
7011 {
7012         int ret = 0;
7013         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7014
7015         if (hw->mac.type != ixgbe_mac_X550 &&
7016             hw->mac.type != ixgbe_mac_X550EM_x &&
7017             hw->mac.type != ixgbe_mac_X550EM_a) {
7018                 return -ENOTSUP;
7019         }
7020
7021         if (udp_tunnel == NULL)
7022                 return -EINVAL;
7023
7024         switch (udp_tunnel->prot_type) {
7025         case RTE_TUNNEL_TYPE_VXLAN:
7026                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7027                 break;
7028
7029         case RTE_TUNNEL_TYPE_GENEVE:
7030         case RTE_TUNNEL_TYPE_TEREDO:
7031                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7032                 ret = -EINVAL;
7033                 break;
7034
7035         default:
7036                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7037                 ret = -EINVAL;
7038                 break;
7039         }
7040
7041         return ret;
7042 }
7043
7044 /* Remove UDP tunneling port */
7045 static int
7046 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7047                               struct rte_eth_udp_tunnel *udp_tunnel)
7048 {
7049         int ret = 0;
7050         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7051
7052         if (hw->mac.type != ixgbe_mac_X550 &&
7053             hw->mac.type != ixgbe_mac_X550EM_x &&
7054             hw->mac.type != ixgbe_mac_X550EM_a) {
7055                 return -ENOTSUP;
7056         }
7057
7058         if (udp_tunnel == NULL)
7059                 return -EINVAL;
7060
7061         switch (udp_tunnel->prot_type) {
7062         case RTE_TUNNEL_TYPE_VXLAN:
7063                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7064                 break;
7065         case RTE_TUNNEL_TYPE_GENEVE:
7066         case RTE_TUNNEL_TYPE_TEREDO:
7067                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7068                 ret = -EINVAL;
7069                 break;
7070         default:
7071                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7072                 ret = -EINVAL;
7073                 break;
7074         }
7075
7076         return ret;
7077 }
7078
7079 /* ixgbevf_update_xcast_mode - Update Multicast mode
7080  * @hw: pointer to the HW structure
7081  * @netdev: pointer to net device structure
7082  * @xcast_mode: new multicast mode
7083  *
7084  * Updates the Multicast Mode of VF.
7085  */
7086 static int ixgbevf_update_xcast_mode(struct ixgbe_hw *hw,
7087                                      int xcast_mode)
7088 {
7089         struct ixgbe_mbx_info *mbx = &hw->mbx;
7090         u32 msgbuf[2];
7091         s32 err;
7092
7093         switch (hw->api_version) {
7094         case ixgbe_mbox_api_12:
7095                 break;
7096         default:
7097                 return -EOPNOTSUPP;
7098         }
7099
7100         msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
7101         msgbuf[1] = xcast_mode;
7102
7103         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
7104         if (err)
7105                 return err;
7106
7107         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
7108         if (err)
7109                 return err;
7110
7111         msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
7112         if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
7113                 return -EPERM;
7114
7115         return 0;
7116 }
7117
7118 static void
7119 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7120 {
7121         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7122
7123         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7124 }
7125
7126 static void
7127 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7128 {
7129         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7130
7131         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7132 }
7133
7134 static struct rte_driver rte_ixgbe_driver = {
7135         .type = PMD_PDEV,
7136         .init = rte_ixgbe_pmd_init,
7137 };
7138
7139 static struct rte_driver rte_ixgbevf_driver = {
7140         .type = PMD_PDEV,
7141         .init = rte_ixgbevf_pmd_init,
7142 };
7143
7144 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
7145 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);