drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_eal.h>
  26 #include <rte_alarm.h>
  27 #include <rte_ether.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_malloc.h>
  31 #include <rte_random.h>
  32 #include <rte_dev.h>
  33 #include <rte_hash_crc.h>
  34 #ifdef RTE_LIBRTE_SECURITY
  35 #include <rte_security_driver.h>
  36 #endif
  37
  38 #include "ixgbe_logs.h"
  39 #include "base/ixgbe_api.h"
  40 #include "base/ixgbe_vf.h"
  41 #include "base/ixgbe_common.h"
  42 #include "ixgbe_ethdev.h"
  43 #include "ixgbe_bypass.h"
  44 #include "ixgbe_rxtx.h"
  45 #include "base/ixgbe_type.h"
  46 #include "base/ixgbe_phy.h"
  47 #include "ixgbe_regs.h"
  48
  49 /*
  50  * High threshold controlling when to start sending XOFF frames. Must be at
  51  * least 8 bytes less than receive packet buffer size. This value is in units
  52  * of 1024 bytes.
  53  */
  54 #define IXGBE_FC_HI    0x80
  55
  56 /*
  57  * Low threshold controlling when to start sending XON frames. This value is
  58  * in units of 1024 bytes.
  59  */
  60 #define IXGBE_FC_LO    0x40
  61
  62 /* Timer value included in XOFF frames. */
  63 #define IXGBE_FC_PAUSE 0x680
  64
  65 /*Default value of Max Rx Queue*/
  66 #define IXGBE_MAX_RX_QUEUE_NUM 128
  67
  68 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  69 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  70 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  71
  72 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  73 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  74 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  75
  76 /*
  77  *  Default values for RX/TX configuration
  78  */
  79 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  80 #define IXGBE_DEFAULT_RX_PTHRESH      8
  81 #define IXGBE_DEFAULT_RX_HTHRESH      8
  82 #define IXGBE_DEFAULT_RX_WTHRESH      0
  83
  84 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  85 #define IXGBE_DEFAULT_TX_PTHRESH      32
  86 #define IXGBE_DEFAULT_TX_HTHRESH      0
  87 #define IXGBE_DEFAULT_TX_WTHRESH      0
  88 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  89
  90 /* Bit shift and mask */
  91 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  92 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  93 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  94 #define IXGBE_8_BIT_MASK   UINT8_MAX
  95
  96 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  97
  98 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
  99
 100 /* Additional timesync values. */
 101 #define NSEC_PER_SEC             1000000000L
 102 #define IXGBE_INCVAL_10GB        0x66666666
 103 #define IXGBE_INCVAL_1GB         0x40000000
 104 #define IXGBE_INCVAL_100         0x50000000
 105 #define IXGBE_INCVAL_SHIFT_10GB  28
 106 #define IXGBE_INCVAL_SHIFT_1GB   24
 107 #define IXGBE_INCVAL_SHIFT_100   21
 108 #define IXGBE_INCVAL_SHIFT_82599 7
 109 #define IXGBE_INCPER_SHIFT_82599 24
 110
 111 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 112
 113 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 114 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 115 #define IXGBE_ETAG_ETYPE                       0x00005084
 116 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 117 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 118 #define IXGBE_RAH_ADTYPE                       0x40000000
 119 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 120 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 121 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 122 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 123 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 124 #define IXGBE_VTEICR_MASK                      0x07
 125
 126 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 127 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 128
 129 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 130 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 131 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 132 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 133 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 134 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 135 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 136 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 137 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 139 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 142 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 143 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 146 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 148                                 int wait_to_complete);
 149 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 150                                 struct rte_eth_stats *stats);
 151 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 152                                 struct rte_eth_xstat *xstats, unsigned n);
 153 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 154                                   struct rte_eth_xstat *xstats, unsigned n);
 155 static int
 156 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 157                 uint64_t *values, unsigned int n);
 158 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 159 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 160 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 161         struct rte_eth_xstat_name *xstats_names,
 162         unsigned int size);
 163 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 164         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 165 static int ixgbe_dev_xstats_get_names_by_id(
 166         struct rte_eth_dev *dev,
 167         struct rte_eth_xstat_name *xstats_names,
 168         const uint64_t *ids,
 169         unsigned int limit);
 170 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 171                                              uint16_t queue_id,
 172                                              uint8_t stat_idx,
 173                                              uint8_t is_rx);
 174 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 175                                  size_t fw_size);
 176 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 177                                struct rte_eth_dev_info *dev_info);
 178 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 179 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 180                                  struct rte_eth_dev_info *dev_info);
 181 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 182
 183 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 184                 uint16_t vlan_id, int on);
 185 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 186                                enum rte_vlan_type vlan_type,
 187                                uint16_t tpid_id);
 188 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 189                 uint16_t queue, bool on);
 190 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 191                 int on);
 192 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 193 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 194 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 195 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 196 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 197
 198 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 199 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 200 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 201                                struct rte_eth_fc_conf *fc_conf);
 202 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 203                                struct rte_eth_fc_conf *fc_conf);
 204 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 205                 struct rte_eth_pfc_conf *pfc_conf);
 206 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 207                         struct rte_eth_rss_reta_entry64 *reta_conf,
 208                         uint16_t reta_size);
 209 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 210                         struct rte_eth_rss_reta_entry64 *reta_conf,
 211                         uint16_t reta_size);
 212 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 213 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 214 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 215 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 216 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 217 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 218                                       struct rte_intr_handle *handle);
 219 static void ixgbe_dev_interrupt_handler(void *param);
 220 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 221 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 222                          uint32_t index, uint32_t pool);
 223 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 224 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 225                                            struct ether_addr *mac_addr);
 226 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 227 static bool is_device_supported(struct rte_eth_dev *dev,
 228                                 struct rte_pci_driver *drv);
 229
 230 /* For Virtual Function support */
 231 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 232 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 233 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 234 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 235 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 236                                    int wait_to_complete);
 237 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 238 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 239 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 240 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 241 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 242 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 243                 struct rte_eth_stats *stats);
 244 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 245 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 246                 uint16_t vlan_id, int on);
 247 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 248                 uint16_t queue, int on);
 249 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 250 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 251 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 252                                             uint16_t queue_id);
 253 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 254                                              uint16_t queue_id);
 255 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 256                                  uint8_t queue, uint8_t msix_vector);
 257 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 258 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 259 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 260
 261 /* For Eth VMDQ APIs support */
 262 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 263                 ether_addr * mac_addr, uint8_t on);
 264 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 265 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 266                 struct rte_eth_mirror_conf *mirror_conf,
 267                 uint8_t rule_id, uint8_t on);
 268 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 269                 uint8_t rule_id);
 270 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 271                                           uint16_t queue_id);
 272 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 273                                            uint16_t queue_id);
 274 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 275                                uint8_t queue, uint8_t msix_vector);
 276 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 277
 278 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 279                                 struct ether_addr *mac_addr,
 280                                 uint32_t index, uint32_t pool);
 281 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 282 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 283                                              struct ether_addr *mac_addr);
 284 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 285                         struct rte_eth_syn_filter *filter);
 286 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 287                         enum rte_filter_op filter_op,
 288                         void *arg);
 289 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 290                         struct ixgbe_5tuple_filter *filter);
 291 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 292                         struct ixgbe_5tuple_filter *filter);
 293 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 294                                 enum rte_filter_op filter_op,
 295                                 void *arg);
 296 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 297                         struct rte_eth_ntuple_filter *filter);
 298 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 299                                 enum rte_filter_op filter_op,
 300                                 void *arg);
 301 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 302                         struct rte_eth_ethertype_filter *filter);
 303 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 304                      enum rte_filter_type filter_type,
 305                      enum rte_filter_op filter_op,
 306                      void *arg);
 307 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 308
 309 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 310                                       struct ether_addr *mc_addr_set,
 311                                       uint32_t nb_mc_addr);
 312 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 313                                    struct rte_eth_dcb_info *dcb_info);
 314
 315 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 316 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 317                             struct rte_dev_reg_info *regs);
 318 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 319 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 320                                 struct rte_dev_eeprom_info *eeprom);
 321 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 322                                 struct rte_dev_eeprom_info *eeprom);
 323
 324 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 325                                  struct rte_eth_dev_module_info *modinfo);
 326 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 327                                    struct rte_dev_eeprom_info *info);
 328
 329 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 330 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 331                                 struct rte_dev_reg_info *regs);
 332
 333 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 334 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 335 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 336                                             struct timespec *timestamp,
 337                                             uint32_t flags);
 338 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 339                                             struct timespec *timestamp);
 340 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 341 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 342                                    struct timespec *timestamp);
 343 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 344                                    const struct timespec *timestamp);
 345 static void ixgbevf_dev_interrupt_handler(void *param);
 346
 347 static int ixgbe_dev_l2_tunnel_eth_type_conf
 348         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 349 static int ixgbe_dev_l2_tunnel_offload_set
 350         (struct rte_eth_dev *dev,
 351          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 352          uint32_t mask,
 353          uint8_t en);
 354 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 355                                              enum rte_filter_op filter_op,
 356                                              void *arg);
 357
 358 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 359                                          struct rte_eth_udp_tunnel *udp_tunnel);
 360 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 361                                          struct rte_eth_udp_tunnel *udp_tunnel);
 362 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 363 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 364
 365 /*
 366  * Define VF Stats MACRO for Non "cleared on read" register
 367  */
 368 #define UPDATE_VF_STAT(reg, last, cur)                          \
 369 {                                                               \
 370         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 371         cur += (latest - last) & UINT_MAX;                      \
 372         last = latest;                                          \
 373 }
 374
 375 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 376 {                                                                \
 377         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 378         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 379         u64 latest = ((new_msb << 32) | new_lsb);                \
 380         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 381         last = latest;                                           \
 382 }
 383
 384 #define IXGBE_SET_HWSTRIP(h, q) do {\
 385                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 386                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 387                 (h)->bitmap[idx] |= 1 << bit;\
 388         } while (0)
 389
 390 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 391                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 392                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 393                 (h)->bitmap[idx] &= ~(1 << bit);\
 394         } while (0)
 395
 396 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 397                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 398                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 399                 (r) = (h)->bitmap[idx] >> bit & 1;\
 400         } while (0)
 401
 402 int ixgbe_logtype_init;
 403 int ixgbe_logtype_driver;
 404
 405 /*
 406  * The set of PCI devices this driver supports
 407  */
 408 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 409         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 410         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 411         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 457 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 459 #endif
 460         { .vendor_id = 0, /* sentinel */ },
 461 };
 462
 463 /*
 464  * The set of PCI devices this driver supports (for 82599 VF)
 465  */
 466 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 477         { .vendor_id = 0, /* sentinel */ },
 478 };
 479
 480 static const struct rte_eth_desc_lim rx_desc_lim = {
 481         .nb_max = IXGBE_MAX_RING_DESC,
 482         .nb_min = IXGBE_MIN_RING_DESC,
 483         .nb_align = IXGBE_RXD_ALIGN,
 484 };
 485
 486 static const struct rte_eth_desc_lim tx_desc_lim = {
 487         .nb_max = IXGBE_MAX_RING_DESC,
 488         .nb_min = IXGBE_MIN_RING_DESC,
 489         .nb_align = IXGBE_TXD_ALIGN,
 490         .nb_seg_max = IXGBE_TX_MAX_SEG,
 491         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 492 };
 493
 494 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 495         .dev_configure        = ixgbe_dev_configure,
 496         .dev_start            = ixgbe_dev_start,
 497         .dev_stop             = ixgbe_dev_stop,
 498         .dev_set_link_up    = ixgbe_dev_set_link_up,
 499         .dev_set_link_down  = ixgbe_dev_set_link_down,
 500         .dev_close            = ixgbe_dev_close,
 501         .dev_reset            = ixgbe_dev_reset,
 502         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 503         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 504         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 505         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 506         .link_update          = ixgbe_dev_link_update,
 507         .stats_get            = ixgbe_dev_stats_get,
 508         .xstats_get           = ixgbe_dev_xstats_get,
 509         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 510         .stats_reset          = ixgbe_dev_stats_reset,
 511         .xstats_reset         = ixgbe_dev_xstats_reset,
 512         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 513         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 514         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 515         .fw_version_get       = ixgbe_fw_version_get,
 516         .dev_infos_get        = ixgbe_dev_info_get,
 517         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 518         .mtu_set              = ixgbe_dev_mtu_set,
 519         .vlan_filter_set      = ixgbe_vlan_filter_set,
 520         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 521         .vlan_offload_set     = ixgbe_vlan_offload_set,
 522         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 523         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 524         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 525         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 526         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 527         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 528         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 529         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 530         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 531         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 532         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 533         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 534         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 535         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 536         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 537         .dev_led_on           = ixgbe_dev_led_on,
 538         .dev_led_off          = ixgbe_dev_led_off,
 539         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 540         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 541         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 542         .mac_addr_add         = ixgbe_add_rar,
 543         .mac_addr_remove      = ixgbe_remove_rar,
 544         .mac_addr_set         = ixgbe_set_default_mac_addr,
 545         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 546         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 547         .mirror_rule_set      = ixgbe_mirror_rule_set,
 548         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 549         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 550         .reta_update          = ixgbe_dev_rss_reta_update,
 551         .reta_query           = ixgbe_dev_rss_reta_query,
 552         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 553         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 554         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 555         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 556         .rxq_info_get         = ixgbe_rxq_info_get,
 557         .txq_info_get         = ixgbe_txq_info_get,
 558         .timesync_enable      = ixgbe_timesync_enable,
 559         .timesync_disable     = ixgbe_timesync_disable,
 560         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 561         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 562         .get_reg              = ixgbe_get_regs,
 563         .get_eeprom_length    = ixgbe_get_eeprom_length,
 564         .get_eeprom           = ixgbe_get_eeprom,
 565         .set_eeprom           = ixgbe_set_eeprom,
 566         .get_module_info      = ixgbe_get_module_info,
 567         .get_module_eeprom    = ixgbe_get_module_eeprom,
 568         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 569         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 570         .timesync_read_time   = ixgbe_timesync_read_time,
 571         .timesync_write_time  = ixgbe_timesync_write_time,
 572         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 573         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 574         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 575         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 576         .tm_ops_get           = ixgbe_tm_ops_get,
 577 };
 578
 579 /*
 580  * dev_ops for virtual function, bare necessities for basic vf
 581  * operation have been implemented
 582  */
 583 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 584         .dev_configure        = ixgbevf_dev_configure,
 585         .dev_start            = ixgbevf_dev_start,
 586         .dev_stop             = ixgbevf_dev_stop,
 587         .link_update          = ixgbevf_dev_link_update,
 588         .stats_get            = ixgbevf_dev_stats_get,
 589         .xstats_get           = ixgbevf_dev_xstats_get,
 590         .stats_reset          = ixgbevf_dev_stats_reset,
 591         .xstats_reset         = ixgbevf_dev_stats_reset,
 592         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 593         .dev_close            = ixgbevf_dev_close,
 594         .dev_reset            = ixgbevf_dev_reset,
 595         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 596         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 597         .dev_infos_get        = ixgbevf_dev_info_get,
 598         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 599         .mtu_set              = ixgbevf_dev_set_mtu,
 600         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 601         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 602         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 603         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 604         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 605         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 606         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 607         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 608         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 609         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 610         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 611         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 612         .mac_addr_add         = ixgbevf_add_mac_addr,
 613         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 614         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 615         .rxq_info_get         = ixgbe_rxq_info_get,
 616         .txq_info_get         = ixgbe_txq_info_get,
 617         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 618         .get_reg              = ixgbevf_get_regs,
 619         .reta_update          = ixgbe_dev_rss_reta_update,
 620         .reta_query           = ixgbe_dev_rss_reta_query,
 621         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 622         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 623 };
 624
 625 /* store statistics names and its offset in stats structure */
 626 struct rte_ixgbe_xstats_name_off {
 627         char name[RTE_ETH_XSTATS_NAME_SIZE];
 628         unsigned offset;
 629 };
 630
 631 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 632         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 633         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 634         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 635         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 636         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 637         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 638         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 639         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 640         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 641         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 642         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 643         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 644         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 645         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 646         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 647                 prc1023)},
 648         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 649                 prc1522)},
 650         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 651         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 652         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 653         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 654         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 655         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 656         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 657         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 658         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 659         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 660         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 661         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 662         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 663         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 664         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 665         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 666         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 667                 ptc1023)},
 668         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 669                 ptc1522)},
 670         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 671         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 672         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 673         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 674
 675         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 676                 fdirustat_add)},
 677         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 678                 fdirustat_remove)},
 679         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 680                 fdirfstat_fadd)},
 681         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 682                 fdirfstat_fremove)},
 683         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 684                 fdirmatch)},
 685         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 686                 fdirmiss)},
 687
 688         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 689         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 690         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 691                 fclast)},
 692         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 693         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 694         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 695         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 696         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 697                 fcoe_noddp)},
 698         {"rx_fcoe_no_direct_data_placement_ext_buff",
 699                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 700
 701         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 702                 lxontxc)},
 703         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 704                 lxonrxc)},
 705         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 706                 lxofftxc)},
 707         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 708                 lxoffrxc)},
 709         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 710 };
 711
 712 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 713                            sizeof(rte_ixgbe_stats_strings[0]))
 714
 715 /* MACsec statistics */
 716 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 717         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 718                 out_pkts_untagged)},
 719         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 720                 out_pkts_encrypted)},
 721         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 722                 out_pkts_protected)},
 723         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 724                 out_octets_encrypted)},
 725         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 726                 out_octets_protected)},
 727         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 728                 in_pkts_untagged)},
 729         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 730                 in_pkts_badtag)},
 731         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 732                 in_pkts_nosci)},
 733         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 734                 in_pkts_unknownsci)},
 735         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 736                 in_octets_decrypted)},
 737         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 738                 in_octets_validated)},
 739         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 740                 in_pkts_unchecked)},
 741         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 742                 in_pkts_delayed)},
 743         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 744                 in_pkts_late)},
 745         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 746                 in_pkts_ok)},
 747         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_invalid)},
 749         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 750                 in_pkts_notvalid)},
 751         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 752                 in_pkts_unusedsa)},
 753         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_notusingsa)},
 755 };
 756
 757 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 758                            sizeof(rte_ixgbe_macsec_strings[0]))
 759
 760 /* Per-queue statistics */
 761 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 762         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 763         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 764         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 765         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 766 };
 767
 768 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 769                            sizeof(rte_ixgbe_rxq_strings[0]))
 770 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 771
 772 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 773         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 774         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 775         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 776                 pxon2offc)},
 777 };
 778
 779 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 780                            sizeof(rte_ixgbe_txq_strings[0]))
 781 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 782
 783 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 784         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 785 };
 786
 787 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 788                 sizeof(rte_ixgbevf_stats_strings[0]))
 789
 790 /*
 791  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 792  */
 793 static inline int
 794 ixgbe_is_sfp(struct ixgbe_hw *hw)
 795 {
 796         switch (hw->phy.type) {
 797         case ixgbe_phy_sfp_avago:
 798         case ixgbe_phy_sfp_ftl:
 799         case ixgbe_phy_sfp_intel:
 800         case ixgbe_phy_sfp_unknown:
 801         case ixgbe_phy_sfp_passive_tyco:
 802         case ixgbe_phy_sfp_passive_unknown:
 803                 return 1;
 804         default:
 805                 return 0;
 806         }
 807 }
 808
 809 static inline int32_t
 810 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 811 {
 812         uint32_t ctrl_ext;
 813         int32_t status;
 814
 815         status = ixgbe_reset_hw(hw);
 816
 817         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 818         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 819         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 820         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 821         IXGBE_WRITE_FLUSH(hw);
 822
 823         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 824                 status = IXGBE_SUCCESS;
 825         return status;
 826 }
 827
 828 static inline void
 829 ixgbe_enable_intr(struct rte_eth_dev *dev)
 830 {
 831         struct ixgbe_interrupt *intr =
 832                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 833         struct ixgbe_hw *hw =
 834                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 835
 836         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 837         IXGBE_WRITE_FLUSH(hw);
 838 }
 839
 840 /*
 841  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 842  */
 843 static void
 844 ixgbe_disable_intr(struct ixgbe_hw *hw)
 845 {
 846         PMD_INIT_FUNC_TRACE();
 847
 848         if (hw->mac.type == ixgbe_mac_82598EB) {
 849                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 850         } else {
 851                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 852                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 853                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 854         }
 855         IXGBE_WRITE_FLUSH(hw);
 856 }
 857
 858 /*
 859  * This function resets queue statistics mapping registers.
 860  * From Niantic datasheet, Initialization of Statistics section:
 861  * "...if software requires the queue counters, the RQSMR and TQSM registers
 862  * must be re-programmed following a device reset.
 863  */
 864 static void
 865 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 866 {
 867         uint32_t i;
 868
 869         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 870                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 871                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 872         }
 873 }
 874
 875
 876 static int
 877 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 878                                   uint16_t queue_id,
 879                                   uint8_t stat_idx,
 880                                   uint8_t is_rx)
 881 {
 882 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 883 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 884 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 885
 886         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 887         struct ixgbe_stat_mapping_registers *stat_mappings =
 888                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 889         uint32_t qsmr_mask = 0;
 890         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 891         uint32_t q_map;
 892         uint8_t n, offset;
 893
 894         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 895                 (hw->mac.type != ixgbe_mac_X540) &&
 896                 (hw->mac.type != ixgbe_mac_X550) &&
 897                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 898                 (hw->mac.type != ixgbe_mac_X550EM_a))
 899                 return -ENOSYS;
 900
 901         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 902                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 903                      queue_id, stat_idx);
 904
 905         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 906         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 907                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 908                 return -EIO;
 909         }
 910         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 911
 912         /* Now clear any previous stat_idx set */
 913         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 914         if (!is_rx)
 915                 stat_mappings->tqsm[n] &= ~clearing_mask;
 916         else
 917                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 918
 919         q_map = (uint32_t)stat_idx;
 920         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 921         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 922         if (!is_rx)
 923                 stat_mappings->tqsm[n] |= qsmr_mask;
 924         else
 925                 stat_mappings->rqsmr[n] |= qsmr_mask;
 926
 927         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 928                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 929                      queue_id, stat_idx);
 930         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 931                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 932
 933         /* Now write the mapping in the appropriate register */
 934         if (is_rx) {
 935                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 936                              stat_mappings->rqsmr[n], n);
 937                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 938         } else {
 939                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 940                              stat_mappings->tqsm[n], n);
 941                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 942         }
 943         return 0;
 944 }
 945
 946 static void
 947 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 948 {
 949         struct ixgbe_stat_mapping_registers *stat_mappings =
 950                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 951         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 952         int i;
 953
 954         /* write whatever was in stat mapping table to the NIC */
 955         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 956                 /* rx */
 957                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 958
 959                 /* tx */
 960                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 961         }
 962 }
 963
 964 static void
 965 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 966 {
 967         uint8_t i;
 968         struct ixgbe_dcb_tc_config *tc;
 969         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 970
 971         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 972         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 973         for (i = 0; i < dcb_max_tc; i++) {
 974                 tc = &dcb_config->tc_config[i];
 975                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 976                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 977                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 978                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 979                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 980                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 981                 tc->pfc = ixgbe_dcb_pfc_disabled;
 982         }
 983
 984         /* Initialize default user to priority mapping, UPx->TC0 */
 985         tc = &dcb_config->tc_config[0];
 986         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 987         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 988         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 989                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 990                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 991         }
 992         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 993         dcb_config->pfc_mode_enable = false;
 994         dcb_config->vt_mode = true;
 995         dcb_config->round_robin_enable = false;
 996         /* support all DCB capabilities in 82599 */
 997         dcb_config->support.capabilities = 0xFF;
 998
 999         /*we only support 4 Tcs for X540, X550 */
1000         if (hw->mac.type == ixgbe_mac_X540 ||
1001                 hw->mac.type == ixgbe_mac_X550 ||
1002                 hw->mac.type == ixgbe_mac_X550EM_x ||
1003                 hw->mac.type == ixgbe_mac_X550EM_a) {
1004                 dcb_config->num_tcs.pg_tcs = 4;
1005                 dcb_config->num_tcs.pfc_tcs = 4;
1006         }
1007 }
1008
1009 /*
1010  * Ensure that all locks are released before first NVM or PHY access
1011  */
1012 static void
1013 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1014 {
1015         uint16_t mask;
1016
1017         /*
1018          * Phy lock should not fail in this early stage. If this is the case,
1019          * it is due to an improper exit of the application.
1020          * So force the release of the faulty lock. Release of common lock
1021          * is done automatically by swfw_sync function.
1022          */
1023         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1024         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1025                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1026         }
1027         ixgbe_release_swfw_semaphore(hw, mask);
1028
1029         /*
1030          * These ones are more tricky since they are common to all ports; but
1031          * swfw_sync retries last long enough (1s) to be almost sure that if
1032          * lock can not be taken it is due to an improper lock of the
1033          * semaphore.
1034          */
1035         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1036         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1037                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1038         }
1039         ixgbe_release_swfw_semaphore(hw, mask);
1040 }
1041
1042 /*
1043  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1044  * It returns 0 on success.
1045  */
1046 static int
1047 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1048 {
1049         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1050         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1051         struct ixgbe_hw *hw =
1052                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1053         struct ixgbe_vfta *shadow_vfta =
1054                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1055         struct ixgbe_hwstrip *hwstrip =
1056                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1057         struct ixgbe_dcb_config *dcb_config =
1058                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1059         struct ixgbe_filter_info *filter_info =
1060                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1061         struct ixgbe_bw_conf *bw_conf =
1062                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1063         uint32_t ctrl_ext;
1064         uint16_t csum;
1065         int diag, i;
1066
1067         PMD_INIT_FUNC_TRACE();
1068
1069         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1070         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1071         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1072         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1073
1074         /*
1075          * For secondary processes, we don't initialise any further as primary
1076          * has already done this work. Only check we don't need a different
1077          * RX and TX function.
1078          */
1079         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1080                 struct ixgbe_tx_queue *txq;
1081                 /* TX queue function in primary, set by last queue initialized
1082                  * Tx queue may not initialized by primary process
1083                  */
1084                 if (eth_dev->data->tx_queues) {
1085                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1086                         ixgbe_set_tx_function(eth_dev, txq);
1087                 } else {
1088                         /* Use default TX function if we get here */
1089                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1090                                      "Using default TX function.");
1091                 }
1092
1093                 ixgbe_set_rx_function(eth_dev);
1094
1095                 return 0;
1096         }
1097
1098         rte_eth_copy_pci_info(eth_dev, pci_dev);
1099
1100         /* Vendor and Device ID need to be set before init of shared code */
1101         hw->device_id = pci_dev->id.device_id;
1102         hw->vendor_id = pci_dev->id.vendor_id;
1103         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1104         hw->allow_unsupported_sfp = 1;
1105
1106         /* Initialize the shared code (base driver) */
1107 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1108         diag = ixgbe_bypass_init_shared_code(hw);
1109 #else
1110         diag = ixgbe_init_shared_code(hw);
1111 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1112
1113         if (diag != IXGBE_SUCCESS) {
1114                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1115                 return -EIO;
1116         }
1117
1118         /* pick up the PCI bus settings for reporting later */
1119         ixgbe_get_bus_info(hw);
1120
1121         /* Unlock any pending hardware semaphore */
1122         ixgbe_swfw_lock_reset(hw);
1123
1124 #ifdef RTE_LIBRTE_SECURITY
1125         /* Initialize security_ctx only for primary process*/
1126         if (ixgbe_ipsec_ctx_create(eth_dev))
1127                 return -ENOMEM;
1128 #endif
1129
1130         /* Initialize DCB configuration*/
1131         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1132         ixgbe_dcb_init(hw, dcb_config);
1133         /* Get Hardware Flow Control setting */
1134         hw->fc.requested_mode = ixgbe_fc_full;
1135         hw->fc.current_mode = ixgbe_fc_full;
1136         hw->fc.pause_time = IXGBE_FC_PAUSE;
1137         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1138                 hw->fc.low_water[i] = IXGBE_FC_LO;
1139                 hw->fc.high_water[i] = IXGBE_FC_HI;
1140         }
1141         hw->fc.send_xon = 1;
1142
1143         /* Make sure we have a good EEPROM before we read from it */
1144         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1145         if (diag != IXGBE_SUCCESS) {
1146                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1147                 return -EIO;
1148         }
1149
1150 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1151         diag = ixgbe_bypass_init_hw(hw);
1152 #else
1153         diag = ixgbe_init_hw(hw);
1154 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1155
1156         /*
1157          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1158          * is called too soon after the kernel driver unbinding/binding occurs.
1159          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1160          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1161          * also called. See ixgbe_identify_phy_82599(). The reason for the
1162          * failure is not known, and only occuts when virtualisation features
1163          * are disabled in the bios. A delay of 100ms  was found to be enough by
1164          * trial-and-error, and is doubled to be safe.
1165          */
1166         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1167                 rte_delay_ms(200);
1168                 diag = ixgbe_init_hw(hw);
1169         }
1170
1171         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1172                 diag = IXGBE_SUCCESS;
1173
1174         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1175                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1176                              "LOM.  Please be aware there may be issues associated "
1177                              "with your hardware.");
1178                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1179                              "please contact your Intel or hardware representative "
1180                              "who provided you with this hardware.");
1181         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1182                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1183         if (diag) {
1184                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1185                 return -EIO;
1186         }
1187
1188         /* Reset the hw statistics */
1189         ixgbe_dev_stats_reset(eth_dev);
1190
1191         /* disable interrupt */
1192         ixgbe_disable_intr(hw);
1193
1194         /* reset mappings for queue statistics hw counters*/
1195         ixgbe_reset_qstat_mappings(hw);
1196
1197         /* Allocate memory for storing MAC addresses */
1198         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1199                                                hw->mac.num_rar_entries, 0);
1200         if (eth_dev->data->mac_addrs == NULL) {
1201                 PMD_INIT_LOG(ERR,
1202                              "Failed to allocate %u bytes needed to store "
1203                              "MAC addresses",
1204                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1205                 return -ENOMEM;
1206         }
1207         /* Copy the permanent MAC address */
1208         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1209                         &eth_dev->data->mac_addrs[0]);
1210
1211         /* Allocate memory for storing hash filter MAC addresses */
1212         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1213                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1214         if (eth_dev->data->hash_mac_addrs == NULL) {
1215                 PMD_INIT_LOG(ERR,
1216                              "Failed to allocate %d bytes needed to store MAC addresses",
1217                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1218                 return -ENOMEM;
1219         }
1220
1221         /* initialize the vfta */
1222         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1223
1224         /* initialize the hw strip bitmap*/
1225         memset(hwstrip, 0, sizeof(*hwstrip));
1226
1227         /* initialize PF if max_vfs not zero */
1228         ixgbe_pf_host_init(eth_dev);
1229
1230         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1231         /* let hardware know driver is loaded */
1232         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1233         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1234         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1235         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1236         IXGBE_WRITE_FLUSH(hw);
1237
1238         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1239                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1240                              (int) hw->mac.type, (int) hw->phy.type,
1241                              (int) hw->phy.sfp_type);
1242         else
1243                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1244                              (int) hw->mac.type, (int) hw->phy.type);
1245
1246         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1247                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1248                      pci_dev->id.device_id);
1249
1250         rte_intr_callback_register(intr_handle,
1251                                    ixgbe_dev_interrupt_handler, eth_dev);
1252
1253         /* enable uio/vfio intr/eventfd mapping */
1254         rte_intr_enable(intr_handle);
1255
1256         /* enable support intr */
1257         ixgbe_enable_intr(eth_dev);
1258
1259         /* initialize filter info */
1260         memset(filter_info, 0,
1261                sizeof(struct ixgbe_filter_info));
1262
1263         /* initialize 5tuple filter list */
1264         TAILQ_INIT(&filter_info->fivetuple_list);
1265
1266         /* initialize flow director filter list & hash */
1267         ixgbe_fdir_filter_init(eth_dev);
1268
1269         /* initialize l2 tunnel filter list & hash */
1270         ixgbe_l2_tn_filter_init(eth_dev);
1271
1272         /* initialize flow filter lists */
1273         ixgbe_filterlist_init();
1274
1275         /* initialize bandwidth configuration info */
1276         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1277
1278         /* initialize Traffic Manager configuration */
1279         ixgbe_tm_conf_init(eth_dev);
1280
1281         return 0;
1282 }
1283
1284 static int
1285 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1286 {
1287         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1288         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1289         struct ixgbe_hw *hw;
1290         int retries = 0;
1291         int ret;
1292
1293         PMD_INIT_FUNC_TRACE();
1294
1295         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1296                 return -EPERM;
1297
1298         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1299
1300         if (hw->adapter_stopped == 0)
1301                 ixgbe_dev_close(eth_dev);
1302
1303         eth_dev->dev_ops = NULL;
1304         eth_dev->rx_pkt_burst = NULL;
1305         eth_dev->tx_pkt_burst = NULL;
1306
1307         /* Unlock any pending hardware semaphore */
1308         ixgbe_swfw_lock_reset(hw);
1309
1310         /* disable uio intr before callback unregister */
1311         rte_intr_disable(intr_handle);
1312
1313         do {
1314                 ret = rte_intr_callback_unregister(intr_handle,
1315                                 ixgbe_dev_interrupt_handler, eth_dev);
1316                 if (ret >= 0) {
1317                         break;
1318                 } else if (ret != -EAGAIN) {
1319                         PMD_INIT_LOG(ERR,
1320                                 "intr callback unregister failed: %d",
1321                                 ret);
1322                         return ret;
1323                 }
1324                 rte_delay_ms(100);
1325         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1326
1327         /* uninitialize PF if max_vfs not zero */
1328         ixgbe_pf_host_uninit(eth_dev);
1329
1330         rte_free(eth_dev->data->mac_addrs);
1331         eth_dev->data->mac_addrs = NULL;
1332
1333         rte_free(eth_dev->data->hash_mac_addrs);
1334         eth_dev->data->hash_mac_addrs = NULL;
1335
1336         /* remove all the fdir filters & hash */
1337         ixgbe_fdir_filter_uninit(eth_dev);
1338
1339         /* remove all the L2 tunnel filters & hash */
1340         ixgbe_l2_tn_filter_uninit(eth_dev);
1341
1342         /* Remove all ntuple filters of the device */
1343         ixgbe_ntuple_filter_uninit(eth_dev);
1344
1345         /* clear all the filters list */
1346         ixgbe_filterlist_flush();
1347
1348         /* Remove all Traffic Manager configuration */
1349         ixgbe_tm_conf_uninit(eth_dev);
1350
1351 #ifdef RTE_LIBRTE_SECURITY
1352         rte_free(eth_dev->security_ctx);
1353 #endif
1354
1355         return 0;
1356 }
1357
1358 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1359 {
1360         struct ixgbe_filter_info *filter_info =
1361                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1362         struct ixgbe_5tuple_filter *p_5tuple;
1363
1364         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1365                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1366                              p_5tuple,
1367                              entries);
1368                 rte_free(p_5tuple);
1369         }
1370         memset(filter_info->fivetuple_mask, 0,
1371                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1372
1373         return 0;
1374 }
1375
1376 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1377 {
1378         struct ixgbe_hw_fdir_info *fdir_info =
1379                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1380         struct ixgbe_fdir_filter *fdir_filter;
1381
1382                 if (fdir_info->hash_map)
1383                 rte_free(fdir_info->hash_map);
1384         if (fdir_info->hash_handle)
1385                 rte_hash_free(fdir_info->hash_handle);
1386
1387         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1388                 TAILQ_REMOVE(&fdir_info->fdir_list,
1389                              fdir_filter,
1390                              entries);
1391                 rte_free(fdir_filter);
1392         }
1393
1394         return 0;
1395 }
1396
1397 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1398 {
1399         struct ixgbe_l2_tn_info *l2_tn_info =
1400                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1401         struct ixgbe_l2_tn_filter *l2_tn_filter;
1402
1403         if (l2_tn_info->hash_map)
1404                 rte_free(l2_tn_info->hash_map);
1405         if (l2_tn_info->hash_handle)
1406                 rte_hash_free(l2_tn_info->hash_handle);
1407
1408         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1409                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1410                              l2_tn_filter,
1411                              entries);
1412                 rte_free(l2_tn_filter);
1413         }
1414
1415         return 0;
1416 }
1417
1418 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1419 {
1420         struct ixgbe_hw_fdir_info *fdir_info =
1421                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1422         char fdir_hash_name[RTE_HASH_NAMESIZE];
1423         struct rte_hash_parameters fdir_hash_params = {
1424                 .name = fdir_hash_name,
1425                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1426                 .key_len = sizeof(union ixgbe_atr_input),
1427                 .hash_func = rte_hash_crc,
1428                 .hash_func_init_val = 0,
1429                 .socket_id = rte_socket_id(),
1430         };
1431
1432         TAILQ_INIT(&fdir_info->fdir_list);
1433         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1434                  "fdir_%s", eth_dev->device->name);
1435         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1436         if (!fdir_info->hash_handle) {
1437                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1438                 return -EINVAL;
1439         }
1440         fdir_info->hash_map = rte_zmalloc("ixgbe",
1441                                           sizeof(struct ixgbe_fdir_filter *) *
1442                                           IXGBE_MAX_FDIR_FILTER_NUM,
1443                                           0);
1444         if (!fdir_info->hash_map) {
1445                 PMD_INIT_LOG(ERR,
1446                              "Failed to allocate memory for fdir hash map!");
1447                 return -ENOMEM;
1448         }
1449         fdir_info->mask_added = FALSE;
1450
1451         return 0;
1452 }
1453
1454 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1455 {
1456         struct ixgbe_l2_tn_info *l2_tn_info =
1457                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1458         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1459         struct rte_hash_parameters l2_tn_hash_params = {
1460                 .name = l2_tn_hash_name,
1461                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1462                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1463                 .hash_func = rte_hash_crc,
1464                 .hash_func_init_val = 0,
1465                 .socket_id = rte_socket_id(),
1466         };
1467
1468         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1469         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1470                  "l2_tn_%s", eth_dev->device->name);
1471         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1472         if (!l2_tn_info->hash_handle) {
1473                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1474                 return -EINVAL;
1475         }
1476         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1477                                    sizeof(struct ixgbe_l2_tn_filter *) *
1478                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1479                                    0);
1480         if (!l2_tn_info->hash_map) {
1481                 PMD_INIT_LOG(ERR,
1482                         "Failed to allocate memory for L2 TN hash map!");
1483                 return -ENOMEM;
1484         }
1485         l2_tn_info->e_tag_en = FALSE;
1486         l2_tn_info->e_tag_fwd_en = FALSE;
1487         l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG;
1488
1489         return 0;
1490 }
1491 /*
1492  * Negotiate mailbox API version with the PF.
1493  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1494  * Then we try to negotiate starting with the most recent one.
1495  * If all negotiation attempts fail, then we will proceed with
1496  * the default one (ixgbe_mbox_api_10).
1497  */
1498 static void
1499 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1500 {
1501         int32_t i;
1502
1503         /* start with highest supported, proceed down */
1504         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1505                 ixgbe_mbox_api_12,
1506                 ixgbe_mbox_api_11,
1507                 ixgbe_mbox_api_10,
1508         };
1509
1510         for (i = 0;
1511                         i != RTE_DIM(sup_ver) &&
1512                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1513                         i++)
1514                 ;
1515 }
1516
1517 static void
1518 generate_random_mac_addr(struct ether_addr *mac_addr)
1519 {
1520         uint64_t random;
1521
1522         /* Set Organizationally Unique Identifier (OUI) prefix. */
1523         mac_addr->addr_bytes[0] = 0x00;
1524         mac_addr->addr_bytes[1] = 0x09;
1525         mac_addr->addr_bytes[2] = 0xC0;
1526         /* Force indication of locally assigned MAC address. */
1527         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1528         /* Generate the last 3 bytes of the MAC address with a random number. */
1529         random = rte_rand();
1530         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1531 }
1532
1533 /*
1534  * Virtual Function device init
1535  */
1536 static int
1537 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1538 {
1539         int diag;
1540         uint32_t tc, tcs;
1541         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1542         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1543         struct ixgbe_hw *hw =
1544                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1545         struct ixgbe_vfta *shadow_vfta =
1546                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1547         struct ixgbe_hwstrip *hwstrip =
1548                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1549         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1550
1551         PMD_INIT_FUNC_TRACE();
1552
1553         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1554         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1555         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1556
1557         /* for secondary processes, we don't initialise any further as primary
1558          * has already done this work. Only check we don't need a different
1559          * RX function
1560          */
1561         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1562                 struct ixgbe_tx_queue *txq;
1563                 /* TX queue function in primary, set by last queue initialized
1564                  * Tx queue may not initialized by primary process
1565                  */
1566                 if (eth_dev->data->tx_queues) {
1567                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1568                         ixgbe_set_tx_function(eth_dev, txq);
1569                 } else {
1570                         /* Use default TX function if we get here */
1571                         PMD_INIT_LOG(NOTICE,
1572                                      "No TX queues configured yet. Using default TX function.");
1573                 }
1574
1575                 ixgbe_set_rx_function(eth_dev);
1576
1577                 return 0;
1578         }
1579
1580         rte_eth_copy_pci_info(eth_dev, pci_dev);
1581
1582         hw->device_id = pci_dev->id.device_id;
1583         hw->vendor_id = pci_dev->id.vendor_id;
1584         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1585
1586         /* initialize the vfta */
1587         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1588
1589         /* initialize the hw strip bitmap*/
1590         memset(hwstrip, 0, sizeof(*hwstrip));
1591
1592         /* Initialize the shared code (base driver) */
1593         diag = ixgbe_init_shared_code(hw);
1594         if (diag != IXGBE_SUCCESS) {
1595                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1596                 return -EIO;
1597         }
1598
1599         /* init_mailbox_params */
1600         hw->mbx.ops.init_params(hw);
1601
1602         /* Reset the hw statistics */
1603         ixgbevf_dev_stats_reset(eth_dev);
1604
1605         /* Disable the interrupts for VF */
1606         ixgbevf_intr_disable(eth_dev);
1607
1608         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1609         diag = hw->mac.ops.reset_hw(hw);
1610
1611         /*
1612          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1613          * the underlying PF driver has not assigned a MAC address to the VF.
1614          * In this case, assign a random MAC address.
1615          */
1616         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1617                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1618                 return diag;
1619         }
1620
1621         /* negotiate mailbox API version to use with the PF. */
1622         ixgbevf_negotiate_api(hw);
1623
1624         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1625         ixgbevf_get_queues(hw, &tcs, &tc);
1626
1627         /* Allocate memory for storing MAC addresses */
1628         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1629                                                hw->mac.num_rar_entries, 0);
1630         if (eth_dev->data->mac_addrs == NULL) {
1631                 PMD_INIT_LOG(ERR,
1632                              "Failed to allocate %u bytes needed to store "
1633                              "MAC addresses",
1634                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1635                 return -ENOMEM;
1636         }
1637
1638         /* Generate a random MAC address, if none was assigned by PF. */
1639         if (is_zero_ether_addr(perm_addr)) {
1640                 generate_random_mac_addr(perm_addr);
1641                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1642                 if (diag) {
1643                         rte_free(eth_dev->data->mac_addrs);
1644                         eth_dev->data->mac_addrs = NULL;
1645                         return diag;
1646                 }
1647                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1648                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1649                              "%02x:%02x:%02x:%02x:%02x:%02x",
1650                              perm_addr->addr_bytes[0],
1651                              perm_addr->addr_bytes[1],
1652                              perm_addr->addr_bytes[2],
1653                              perm_addr->addr_bytes[3],
1654                              perm_addr->addr_bytes[4],
1655                              perm_addr->addr_bytes[5]);
1656         }
1657
1658         /* Copy the permanent MAC address */
1659         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1660
1661         /* reset the hardware with the new settings */
1662         diag = hw->mac.ops.start_hw(hw);
1663         switch (diag) {
1664         case  0:
1665                 break;
1666
1667         default:
1668                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1669                 return -EIO;
1670         }
1671
1672         rte_intr_callback_register(intr_handle,
1673                                    ixgbevf_dev_interrupt_handler, eth_dev);
1674         rte_intr_enable(intr_handle);
1675         ixgbevf_intr_enable(eth_dev);
1676
1677         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1678                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1679                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1680
1681         return 0;
1682 }
1683
1684 /* Virtual Function device uninit */
1685
1686 static int
1687 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1688 {
1689         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1690         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1691         struct ixgbe_hw *hw;
1692
1693         PMD_INIT_FUNC_TRACE();
1694
1695         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1696                 return -EPERM;
1697
1698         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1699
1700         if (hw->adapter_stopped == 0)
1701                 ixgbevf_dev_close(eth_dev);
1702
1703         eth_dev->dev_ops = NULL;
1704         eth_dev->rx_pkt_burst = NULL;
1705         eth_dev->tx_pkt_burst = NULL;
1706
1707         /* Disable the interrupts for VF */
1708         ixgbevf_intr_disable(eth_dev);
1709
1710         rte_free(eth_dev->data->mac_addrs);
1711         eth_dev->data->mac_addrs = NULL;
1712
1713         rte_intr_disable(intr_handle);
1714         rte_intr_callback_unregister(intr_handle,
1715                                      ixgbevf_dev_interrupt_handler, eth_dev);
1716
1717         return 0;
1718 }
1719
1720 static int
1721 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1722                 struct rte_pci_device *pci_dev)
1723 {
1724         char name[RTE_ETH_NAME_MAX_LEN];
1725         struct rte_eth_dev *pf_ethdev;
1726         struct rte_eth_devargs eth_da;
1727         int i, retval;
1728
1729         if (pci_dev->device.devargs) {
1730                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1731                                 &eth_da);
1732                 if (retval)
1733                         return retval;
1734         } else
1735                 memset(&eth_da, 0, sizeof(eth_da));
1736
1737         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1738                 sizeof(struct ixgbe_adapter),
1739                 eth_dev_pci_specific_init, pci_dev,
1740                 eth_ixgbe_dev_init, NULL);
1741
1742         if (retval || eth_da.nb_representor_ports < 1)
1743                 return retval;
1744
1745         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1746         if (pf_ethdev == NULL)
1747                 return -ENODEV;
1748
1749         /* probe VF representor ports */
1750         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1751                 struct ixgbe_vf_info *vfinfo;
1752                 struct ixgbe_vf_representor representor;
1753
1754                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1755                         pf_ethdev->data->dev_private);
1756                 if (vfinfo == NULL) {
1757                         PMD_DRV_LOG(ERR,
1758                                 "no virtual functions supported by PF");
1759                         break;
1760                 }
1761
1762                 representor.vf_id = eth_da.representor_ports[i];
1763                 representor.switch_domain_id = vfinfo->switch_domain_id;
1764                 representor.pf_ethdev = pf_ethdev;
1765
1766                 /* representor port net_bdf_port */
1767                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1768                         pci_dev->device.name,
1769                         eth_da.representor_ports[i]);
1770
1771                 retval = rte_eth_dev_create(&pci_dev->device, name,
1772                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1773                         ixgbe_vf_representor_init, &representor);
1774
1775                 if (retval)
1776                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1777                                 "representor %s.", name);
1778         }
1779
1780         return 0;
1781 }
1782
1783 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1784 {
1785         struct rte_eth_dev *ethdev;
1786
1787         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1788         if (!ethdev)
1789                 return -ENODEV;
1790
1791         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1792                 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1793         else
1794                 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1795 }
1796
1797 static struct rte_pci_driver rte_ixgbe_pmd = {
1798         .id_table = pci_id_ixgbe_map,
1799         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1800                      RTE_PCI_DRV_IOVA_AS_VA,
1801         .probe = eth_ixgbe_pci_probe,
1802         .remove = eth_ixgbe_pci_remove,
1803 };
1804
1805 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1806         struct rte_pci_device *pci_dev)
1807 {
1808         return rte_eth_dev_pci_generic_probe(pci_dev,
1809                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1810 }
1811
1812 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1813 {
1814         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1815 }
1816
1817 /*
1818  * virtual function driver struct
1819  */
1820 static struct rte_pci_driver rte_ixgbevf_pmd = {
1821         .id_table = pci_id_ixgbevf_map,
1822         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1823         .probe = eth_ixgbevf_pci_probe,
1824         .remove = eth_ixgbevf_pci_remove,
1825 };
1826
1827 static int
1828 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1829 {
1830         struct ixgbe_hw *hw =
1831                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1832         struct ixgbe_vfta *shadow_vfta =
1833                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1834         uint32_t vfta;
1835         uint32_t vid_idx;
1836         uint32_t vid_bit;
1837
1838         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1839         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1840         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1841         if (on)
1842                 vfta |= vid_bit;
1843         else
1844                 vfta &= ~vid_bit;
1845         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1846
1847         /* update local VFTA copy */
1848         shadow_vfta->vfta[vid_idx] = vfta;
1849
1850         return 0;
1851 }
1852
1853 static void
1854 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1855 {
1856         if (on)
1857                 ixgbe_vlan_hw_strip_enable(dev, queue);
1858         else
1859                 ixgbe_vlan_hw_strip_disable(dev, queue);
1860 }
1861
1862 static int
1863 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1864                     enum rte_vlan_type vlan_type,
1865                     uint16_t tpid)
1866 {
1867         struct ixgbe_hw *hw =
1868                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1869         int ret = 0;
1870         uint32_t reg;
1871         uint32_t qinq;
1872
1873         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1874         qinq &= IXGBE_DMATXCTL_GDV;
1875
1876         switch (vlan_type) {
1877         case ETH_VLAN_TYPE_INNER:
1878                 if (qinq) {
1879                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1880                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1881                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1882                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1883                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1884                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1885                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1886                 } else {
1887                         ret = -ENOTSUP;
1888                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1889                                     " by single VLAN");
1890                 }
1891                 break;
1892         case ETH_VLAN_TYPE_OUTER:
1893                 if (qinq) {
1894                         /* Only the high 16-bits is valid */
1895                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1896                                         IXGBE_EXVET_VET_EXT_SHIFT);
1897                 } else {
1898                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1899                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1900                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1901                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1902                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1903                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1904                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1905                 }
1906
1907                 break;
1908         default:
1909                 ret = -EINVAL;
1910                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1911                 break;
1912         }
1913
1914         return ret;
1915 }
1916
1917 void
1918 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1919 {
1920         struct ixgbe_hw *hw =
1921                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         uint32_t vlnctrl;
1923
1924         PMD_INIT_FUNC_TRACE();
1925
1926         /* Filter Table Disable */
1927         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1928         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1929
1930         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1931 }
1932
1933 void
1934 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1935 {
1936         struct ixgbe_hw *hw =
1937                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938         struct ixgbe_vfta *shadow_vfta =
1939                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1940         uint32_t vlnctrl;
1941         uint16_t i;
1942
1943         PMD_INIT_FUNC_TRACE();
1944
1945         /* Filter Table Enable */
1946         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1947         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1948         vlnctrl |= IXGBE_VLNCTRL_VFE;
1949
1950         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1951
1952         /* write whatever is in local vfta copy */
1953         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1954                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1955 }
1956
1957 static void
1958 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1959 {
1960         struct ixgbe_hwstrip *hwstrip =
1961                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1962         struct ixgbe_rx_queue *rxq;
1963
1964         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1965                 return;
1966
1967         if (on)
1968                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1969         else
1970                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1971
1972         if (queue >= dev->data->nb_rx_queues)
1973                 return;
1974
1975         rxq = dev->data->rx_queues[queue];
1976
1977         if (on)
1978                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1979         else
1980                 rxq->vlan_flags = PKT_RX_VLAN;
1981 }
1982
1983 static void
1984 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1985 {
1986         struct ixgbe_hw *hw =
1987                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1988         uint32_t ctrl;
1989
1990         PMD_INIT_FUNC_TRACE();
1991
1992         if (hw->mac.type == ixgbe_mac_82598EB) {
1993                 /* No queue level support */
1994                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1995                 return;
1996         }
1997
1998         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1999         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2000         ctrl &= ~IXGBE_RXDCTL_VME;
2001         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2002
2003         /* record those setting for HW strip per queue */
2004         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2005 }
2006
2007 static void
2008 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2009 {
2010         struct ixgbe_hw *hw =
2011                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2012         uint32_t ctrl;
2013
2014         PMD_INIT_FUNC_TRACE();
2015
2016         if (hw->mac.type == ixgbe_mac_82598EB) {
2017                 /* No queue level supported */
2018                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2019                 return;
2020         }
2021
2022         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2023         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2024         ctrl |= IXGBE_RXDCTL_VME;
2025         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2026
2027         /* record those setting for HW strip per queue */
2028         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2029 }
2030
2031 static void
2032 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2033 {
2034         struct ixgbe_hw *hw =
2035                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2036         uint32_t ctrl;
2037
2038         PMD_INIT_FUNC_TRACE();
2039
2040         /* DMATXCTRL: Geric Double VLAN Disable */
2041         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2042         ctrl &= ~IXGBE_DMATXCTL_GDV;
2043         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2044
2045         /* CTRL_EXT: Global Double VLAN Disable */
2046         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2047         ctrl &= ~IXGBE_EXTENDED_VLAN;
2048         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2049
2050 }
2051
2052 static void
2053 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2054 {
2055         struct ixgbe_hw *hw =
2056                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2057         uint32_t ctrl;
2058
2059         PMD_INIT_FUNC_TRACE();
2060
2061         /* DMATXCTRL: Geric Double VLAN Enable */
2062         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2063         ctrl |= IXGBE_DMATXCTL_GDV;
2064         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2065
2066         /* CTRL_EXT: Global Double VLAN Enable */
2067         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2068         ctrl |= IXGBE_EXTENDED_VLAN;
2069         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2070
2071         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2072         if (hw->mac.type == ixgbe_mac_X550 ||
2073             hw->mac.type == ixgbe_mac_X550EM_x ||
2074             hw->mac.type == ixgbe_mac_X550EM_a) {
2075                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2076                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2077                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2078         }
2079
2080         /*
2081          * VET EXT field in the EXVET register = 0x8100 by default
2082          * So no need to change. Same to VT field of DMATXCTL register
2083          */
2084 }
2085
2086 void
2087 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2088 {
2089         struct ixgbe_hw *hw =
2090                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2091         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2092         uint32_t ctrl;
2093         uint16_t i;
2094         struct ixgbe_rx_queue *rxq;
2095         bool on;
2096
2097         PMD_INIT_FUNC_TRACE();
2098
2099         if (hw->mac.type == ixgbe_mac_82598EB) {
2100                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2101                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2102                         ctrl |= IXGBE_VLNCTRL_VME;
2103                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2104                 } else {
2105                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2106                         ctrl &= ~IXGBE_VLNCTRL_VME;
2107                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2108                 }
2109         } else {
2110                 /*
2111                  * Other 10G NIC, the VLAN strip can be setup
2112                  * per queue in RXDCTL
2113                  */
2114                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2115                         rxq = dev->data->rx_queues[i];
2116                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2117                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2118                                 ctrl |= IXGBE_RXDCTL_VME;
2119                                 on = TRUE;
2120                         } else {
2121                                 ctrl &= ~IXGBE_RXDCTL_VME;
2122                                 on = FALSE;
2123                         }
2124                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2125
2126                         /* record those setting for HW strip per queue */
2127                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2128                 }
2129         }
2130 }
2131
2132 static int
2133 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2134 {
2135         struct rte_eth_rxmode *rxmode;
2136         rxmode = &dev->data->dev_conf.rxmode;
2137
2138         if (mask & ETH_VLAN_STRIP_MASK) {
2139                 ixgbe_vlan_hw_strip_config(dev);
2140         }
2141
2142         if (mask & ETH_VLAN_FILTER_MASK) {
2143                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2144                         ixgbe_vlan_hw_filter_enable(dev);
2145                 else
2146                         ixgbe_vlan_hw_filter_disable(dev);
2147         }
2148
2149         if (mask & ETH_VLAN_EXTEND_MASK) {
2150                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2151                         ixgbe_vlan_hw_extend_enable(dev);
2152                 else
2153                         ixgbe_vlan_hw_extend_disable(dev);
2154         }
2155
2156         return 0;
2157 }
2158
2159 static void
2160 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2161 {
2162         struct ixgbe_hw *hw =
2163                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2164         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2165         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2166
2167         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2168         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2169 }
2170
2171 static int
2172 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2173 {
2174         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2175
2176         switch (nb_rx_q) {
2177         case 1:
2178         case 2:
2179                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2180                 break;
2181         case 4:
2182                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2183                 break;
2184         default:
2185                 return -EINVAL;
2186         }
2187
2188         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2189                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2190         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2191                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2192         return 0;
2193 }
2194
2195 static int
2196 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2197 {
2198         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2199         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2200         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2201         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2202
2203         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2204                 /* check multi-queue mode */
2205                 switch (dev_conf->rxmode.mq_mode) {
2206                 case ETH_MQ_RX_VMDQ_DCB:
2207                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2208                         break;
2209                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2210                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2211                         PMD_INIT_LOG(ERR, "SRIOV active,"
2212                                         " unsupported mq_mode rx %d.",
2213                                         dev_conf->rxmode.mq_mode);
2214                         return -EINVAL;
2215                 case ETH_MQ_RX_RSS:
2216                 case ETH_MQ_RX_VMDQ_RSS:
2217                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2218                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2219                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2220                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2221                                                 " invalid queue number"
2222                                                 " for VMDQ RSS, allowed"
2223                                                 " value are 1, 2 or 4.");
2224                                         return -EINVAL;
2225                                 }
2226                         break;
2227                 case ETH_MQ_RX_VMDQ_ONLY:
2228                 case ETH_MQ_RX_NONE:
2229                         /* if nothing mq mode configure, use default scheme */
2230                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2231                         break;
2232                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2233                         /* SRIOV only works in VMDq enable mode */
2234                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2235                                         " wrong mq_mode rx %d.",
2236                                         dev_conf->rxmode.mq_mode);
2237                         return -EINVAL;
2238                 }
2239
2240                 switch (dev_conf->txmode.mq_mode) {
2241                 case ETH_MQ_TX_VMDQ_DCB:
2242                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2243                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2244                         break;
2245                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2246                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2247                         break;
2248                 }
2249
2250                 /* check valid queue number */
2251                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2252                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2253                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2254                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2255                                         " must be less than or equal to %d.",
2256                                         nb_rx_q, nb_tx_q,
2257                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2258                         return -EINVAL;
2259                 }
2260         } else {
2261                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2262                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2263                                           " not supported.");
2264                         return -EINVAL;
2265                 }
2266                 /* check configuration for vmdb+dcb mode */
2267                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2268                         const struct rte_eth_vmdq_dcb_conf *conf;
2269
2270                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2271                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2272                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2273                                 return -EINVAL;
2274                         }
2275                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2276                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2277                                conf->nb_queue_pools == ETH_32_POOLS)) {
2278                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2279                                                 " nb_queue_pools must be %d or %d.",
2280                                                 ETH_16_POOLS, ETH_32_POOLS);
2281                                 return -EINVAL;
2282                         }
2283                 }
2284                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2285                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2286
2287                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2288                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2289                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2290                                 return -EINVAL;
2291                         }
2292                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2293                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2294                                conf->nb_queue_pools == ETH_32_POOLS)) {
2295                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2296                                                 " nb_queue_pools != %d and"
2297                                                 " nb_queue_pools != %d.",
2298                                                 ETH_16_POOLS, ETH_32_POOLS);
2299                                 return -EINVAL;
2300                         }
2301                 }
2302
2303                 /* For DCB mode check our configuration before we go further */
2304                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2305                         const struct rte_eth_dcb_rx_conf *conf;
2306
2307                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2308                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2309                                                  IXGBE_DCB_NB_QUEUES);
2310                                 return -EINVAL;
2311                         }
2312                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2313                         if (!(conf->nb_tcs == ETH_4_TCS ||
2314                                conf->nb_tcs == ETH_8_TCS)) {
2315                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2316                                                 " and nb_tcs != %d.",
2317                                                 ETH_4_TCS, ETH_8_TCS);
2318                                 return -EINVAL;
2319                         }
2320                 }
2321
2322                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2323                         const struct rte_eth_dcb_tx_conf *conf;
2324
2325                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2326                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2327                                                  IXGBE_DCB_NB_QUEUES);
2328                                 return -EINVAL;
2329                         }
2330                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2331                         if (!(conf->nb_tcs == ETH_4_TCS ||
2332                                conf->nb_tcs == ETH_8_TCS)) {
2333                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2334                                                 " and nb_tcs != %d.",
2335                                                 ETH_4_TCS, ETH_8_TCS);
2336                                 return -EINVAL;
2337                         }
2338                 }
2339
2340                 /*
2341                  * When DCB/VT is off, maximum number of queues changes,
2342                  * except for 82598EB, which remains constant.
2343                  */
2344                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2345                                 hw->mac.type != ixgbe_mac_82598EB) {
2346                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2347                                 PMD_INIT_LOG(ERR,
2348                                              "Neither VT nor DCB are enabled, "
2349                                              "nb_tx_q > %d.",
2350                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2351                                 return -EINVAL;
2352                         }
2353                 }
2354         }
2355         return 0;
2356 }
2357
2358 static int
2359 ixgbe_dev_configure(struct rte_eth_dev *dev)
2360 {
2361         struct ixgbe_interrupt *intr =
2362                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2363         struct ixgbe_adapter *adapter =
2364                 (struct ixgbe_adapter *)dev->data->dev_private;
2365         int ret;
2366
2367         PMD_INIT_FUNC_TRACE();
2368         /* multipe queue mode checking */
2369         ret  = ixgbe_check_mq_mode(dev);
2370         if (ret != 0) {
2371                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2372                             ret);
2373                 return ret;
2374         }
2375
2376         /* set flag to update link status after init */
2377         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2378
2379         /*
2380          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2381          * allocation or vector Rx preconditions we will reset it.
2382          */
2383         adapter->rx_bulk_alloc_allowed = true;
2384         adapter->rx_vec_allowed = true;
2385
2386         return 0;
2387 }
2388
2389 static void
2390 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2391 {
2392         struct ixgbe_hw *hw =
2393                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2394         struct ixgbe_interrupt *intr =
2395                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2396         uint32_t gpie;
2397
2398         /* only set up it on X550EM_X */
2399         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2400                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2401                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2402                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2403                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2404                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2405         }
2406 }
2407
2408 int
2409 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2410                         uint16_t tx_rate, uint64_t q_msk)
2411 {
2412         struct ixgbe_hw *hw;
2413         struct ixgbe_vf_info *vfinfo;
2414         struct rte_eth_link link;
2415         uint8_t  nb_q_per_pool;
2416         uint32_t queue_stride;
2417         uint32_t queue_idx, idx = 0, vf_idx;
2418         uint32_t queue_end;
2419         uint16_t total_rate = 0;
2420         struct rte_pci_device *pci_dev;
2421
2422         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2423         rte_eth_link_get_nowait(dev->data->port_id, &link);
2424
2425         if (vf >= pci_dev->max_vfs)
2426                 return -EINVAL;
2427
2428         if (tx_rate > link.link_speed)
2429                 return -EINVAL;
2430
2431         if (q_msk == 0)
2432                 return 0;
2433
2434         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2435         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2436         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2437         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2438         queue_idx = vf * queue_stride;
2439         queue_end = queue_idx + nb_q_per_pool - 1;
2440         if (queue_end >= hw->mac.max_tx_queues)
2441                 return -EINVAL;
2442
2443         if (vfinfo) {
2444                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2445                         if (vf_idx == vf)
2446                                 continue;
2447                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2448                                 idx++)
2449                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2450                 }
2451         } else {
2452                 return -EINVAL;
2453         }
2454
2455         /* Store tx_rate for this vf. */
2456         for (idx = 0; idx < nb_q_per_pool; idx++) {
2457                 if (((uint64_t)0x1 << idx) & q_msk) {
2458                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2459                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2460                         total_rate += tx_rate;
2461                 }
2462         }
2463
2464         if (total_rate > dev->data->dev_link.link_speed) {
2465                 /* Reset stored TX rate of the VF if it causes exceed
2466                  * link speed.
2467                  */
2468                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2469                 return -EINVAL;
2470         }
2471
2472         /* Set RTTBCNRC of each queue/pool for vf X  */
2473         for (; queue_idx <= queue_end; queue_idx++) {
2474                 if (0x1 & q_msk)
2475                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2476                 q_msk = q_msk >> 1;
2477         }
2478
2479         return 0;
2480 }
2481
2482 /*
2483  * Configure device link speed and setup link.
2484  * It returns 0 on success.
2485  */
2486 static int
2487 ixgbe_dev_start(struct rte_eth_dev *dev)
2488 {
2489         struct ixgbe_hw *hw =
2490                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2491         struct ixgbe_vf_info *vfinfo =
2492                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2493         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2494         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2495         uint32_t intr_vector = 0;
2496         int err, link_up = 0, negotiate = 0;
2497         uint32_t speed = 0;
2498         uint32_t allowed_speeds = 0;
2499         int mask = 0;
2500         int status;
2501         uint16_t vf, idx;
2502         uint32_t *link_speeds;
2503         struct ixgbe_tm_conf *tm_conf =
2504                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2505
2506         PMD_INIT_FUNC_TRACE();
2507
2508         /* IXGBE devices don't support:
2509         *    - half duplex (checked afterwards for valid speeds)
2510         *    - fixed speed: TODO implement
2511         */
2512         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2513                 PMD_INIT_LOG(ERR,
2514                 "Invalid link_speeds for port %u, fix speed not supported",
2515                                 dev->data->port_id);
2516                 return -EINVAL;
2517         }
2518
2519         /* disable uio/vfio intr/eventfd mapping */
2520         rte_intr_disable(intr_handle);
2521
2522         /* stop adapter */
2523         hw->adapter_stopped = 0;
2524         ixgbe_stop_adapter(hw);
2525
2526         /* reinitialize adapter
2527          * this calls reset and start
2528          */
2529         status = ixgbe_pf_reset_hw(hw);
2530         if (status != 0)
2531                 return -1;
2532         hw->mac.ops.start_hw(hw);
2533         hw->mac.get_link_status = true;
2534
2535         /* configure PF module if SRIOV enabled */
2536         ixgbe_pf_host_configure(dev);
2537
2538         ixgbe_dev_phy_intr_setup(dev);
2539
2540         /* check and configure queue intr-vector mapping */
2541         if ((rte_intr_cap_multiple(intr_handle) ||
2542              !RTE_ETH_DEV_SRIOV(dev).active) &&
2543             dev->data->dev_conf.intr_conf.rxq != 0) {
2544                 intr_vector = dev->data->nb_rx_queues;
2545                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2546                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2547                                         IXGBE_MAX_INTR_QUEUE_NUM);
2548                         return -ENOTSUP;
2549                 }
2550                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2551                         return -1;
2552         }
2553
2554         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2555                 intr_handle->intr_vec =
2556                         rte_zmalloc("intr_vec",
2557                                     dev->data->nb_rx_queues * sizeof(int), 0);
2558                 if (intr_handle->intr_vec == NULL) {
2559                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2560                                      " intr_vec", dev->data->nb_rx_queues);
2561                         return -ENOMEM;
2562                 }
2563         }
2564
2565         /* confiugre msix for sleep until rx interrupt */
2566         ixgbe_configure_msix(dev);
2567
2568         /* initialize transmission unit */
2569         ixgbe_dev_tx_init(dev);
2570
2571         /* This can fail when allocating mbufs for descriptor rings */
2572         err = ixgbe_dev_rx_init(dev);
2573         if (err) {
2574                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2575                 goto error;
2576         }
2577
2578         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2579                 ETH_VLAN_EXTEND_MASK;
2580         err = ixgbe_vlan_offload_set(dev, mask);
2581         if (err) {
2582                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2583                 goto error;
2584         }
2585
2586         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2587                 /* Enable vlan filtering for VMDq */
2588                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2589         }
2590
2591         /* Configure DCB hw */
2592         ixgbe_configure_dcb(dev);
2593
2594         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2595                 err = ixgbe_fdir_configure(dev);
2596                 if (err)
2597                         goto error;
2598         }
2599
2600         /* Restore vf rate limit */
2601         if (vfinfo != NULL) {
2602                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2603                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2604                                 if (vfinfo[vf].tx_rate[idx] != 0)
2605                                         ixgbe_set_vf_rate_limit(
2606                                                 dev, vf,
2607                                                 vfinfo[vf].tx_rate[idx],
2608                                                 1 << idx);
2609         }
2610
2611         ixgbe_restore_statistics_mapping(dev);
2612
2613         err = ixgbe_dev_rxtx_start(dev);
2614         if (err < 0) {
2615                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2616                 goto error;
2617         }
2618
2619         /* Skip link setup if loopback mode is enabled for 82599. */
2620         if (hw->mac.type == ixgbe_mac_82599EB &&
2621                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2622                 goto skip_link_setup;
2623
2624         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2625                 err = hw->mac.ops.setup_sfp(hw);
2626                 if (err)
2627                         goto error;
2628         }
2629
2630         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2631                 /* Turn on the copper */
2632                 ixgbe_set_phy_power(hw, true);
2633         } else {
2634                 /* Turn on the laser */
2635                 ixgbe_enable_tx_laser(hw);
2636         }
2637
2638         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2639         if (err)
2640                 goto error;
2641         dev->data->dev_link.link_status = link_up;
2642
2643         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2644         if (err)
2645                 goto error;
2646
2647         switch (hw->mac.type) {
2648         case ixgbe_mac_X550:
2649         case ixgbe_mac_X550EM_x:
2650         case ixgbe_mac_X550EM_a:
2651                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2652                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2653                         ETH_LINK_SPEED_10G;
2654                 break;
2655         default:
2656                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2657                         ETH_LINK_SPEED_10G;
2658         }
2659
2660         link_speeds = &dev->data->dev_conf.link_speeds;
2661         if (*link_speeds & ~allowed_speeds) {
2662                 PMD_INIT_LOG(ERR, "Invalid link setting");
2663                 goto error;
2664         }
2665
2666         speed = 0x0;
2667         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2668                 switch (hw->mac.type) {
2669                 case ixgbe_mac_82598EB:
2670                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2671                         break;
2672                 case ixgbe_mac_82599EB:
2673                 case ixgbe_mac_X540:
2674                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2675                         break;
2676                 case ixgbe_mac_X550:
2677                 case ixgbe_mac_X550EM_x:
2678                 case ixgbe_mac_X550EM_a:
2679                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2680                         break;
2681                 default:
2682                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2683                 }
2684         } else {
2685                 if (*link_speeds & ETH_LINK_SPEED_10G)
2686                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2687                 if (*link_speeds & ETH_LINK_SPEED_5G)
2688                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2689                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2690                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2691                 if (*link_speeds & ETH_LINK_SPEED_1G)
2692                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2693                 if (*link_speeds & ETH_LINK_SPEED_100M)
2694                         speed |= IXGBE_LINK_SPEED_100_FULL;
2695         }
2696
2697         err = ixgbe_setup_link(hw, speed, link_up);
2698         if (err)
2699                 goto error;
2700
2701         ixgbe_dev_link_update(dev, 0);
2702
2703 skip_link_setup:
2704
2705         if (rte_intr_allow_others(intr_handle)) {
2706                 /* check if lsc interrupt is enabled */
2707                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2708                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2709                 else
2710                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2711                 ixgbe_dev_macsec_interrupt_setup(dev);
2712         } else {
2713                 rte_intr_callback_unregister(intr_handle,
2714                                              ixgbe_dev_interrupt_handler, dev);
2715                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2716                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2717                                      " no intr multiplex");
2718         }
2719
2720         /* check if rxq interrupt is enabled */
2721         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2722             rte_intr_dp_is_en(intr_handle))
2723                 ixgbe_dev_rxq_interrupt_setup(dev);
2724
2725         /* enable uio/vfio intr/eventfd mapping */
2726         rte_intr_enable(intr_handle);
2727
2728         /* resume enabled intr since hw reset */
2729         ixgbe_enable_intr(dev);
2730         ixgbe_l2_tunnel_conf(dev);
2731         ixgbe_filter_restore(dev);
2732
2733         if (tm_conf->root && !tm_conf->committed)
2734                 PMD_DRV_LOG(WARNING,
2735                             "please call hierarchy_commit() "
2736                             "before starting the port");
2737
2738         return 0;
2739
2740 error:
2741         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2742         ixgbe_dev_clear_queues(dev);
2743         return -EIO;
2744 }
2745
2746 /*
2747  * Stop device: disable rx and tx functions to allow for reconfiguring.
2748  */
2749 static void
2750 ixgbe_dev_stop(struct rte_eth_dev *dev)
2751 {
2752         struct rte_eth_link link;
2753         struct ixgbe_hw *hw =
2754                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2755         struct ixgbe_vf_info *vfinfo =
2756                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2757         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2758         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2759         int vf;
2760         struct ixgbe_tm_conf *tm_conf =
2761                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2762
2763         PMD_INIT_FUNC_TRACE();
2764
2765         /* disable interrupts */
2766         ixgbe_disable_intr(hw);
2767
2768         /* reset the NIC */
2769         ixgbe_pf_reset_hw(hw);
2770         hw->adapter_stopped = 0;
2771
2772         /* stop adapter */
2773         ixgbe_stop_adapter(hw);
2774
2775         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2776                 vfinfo[vf].clear_to_send = false;
2777
2778         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2779                 /* Turn off the copper */
2780                 ixgbe_set_phy_power(hw, false);
2781         } else {
2782                 /* Turn off the laser */
2783                 ixgbe_disable_tx_laser(hw);
2784         }
2785
2786         ixgbe_dev_clear_queues(dev);
2787
2788         /* Clear stored conf */
2789         dev->data->scattered_rx = 0;
2790         dev->data->lro = 0;
2791
2792         /* Clear recorded link status */
2793         memset(&link, 0, sizeof(link));
2794         rte_eth_linkstatus_set(dev, &link);
2795
2796         if (!rte_intr_allow_others(intr_handle))
2797                 /* resume to the default handler */
2798                 rte_intr_callback_register(intr_handle,
2799                                            ixgbe_dev_interrupt_handler,
2800                                            (void *)dev);
2801
2802         /* Clean datapath event and queue/vec mapping */
2803         rte_intr_efd_disable(intr_handle);
2804         if (intr_handle->intr_vec != NULL) {
2805                 rte_free(intr_handle->intr_vec);
2806                 intr_handle->intr_vec = NULL;
2807         }
2808
2809         /* reset hierarchy commit */
2810         tm_conf->committed = false;
2811 }
2812
2813 /*
2814  * Set device link up: enable tx.
2815  */
2816 static int
2817 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2818 {
2819         struct ixgbe_hw *hw =
2820                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2821         if (hw->mac.type == ixgbe_mac_82599EB) {
2822 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2823                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2824                         /* Not suported in bypass mode */
2825                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2826                                      "by device id 0x%x", hw->device_id);
2827                         return -ENOTSUP;
2828                 }
2829 #endif
2830         }
2831
2832         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2833                 /* Turn on the copper */
2834                 ixgbe_set_phy_power(hw, true);
2835         } else {
2836                 /* Turn on the laser */
2837                 ixgbe_enable_tx_laser(hw);
2838         }
2839
2840         return 0;
2841 }
2842
2843 /*
2844  * Set device link down: disable tx.
2845  */
2846 static int
2847 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2848 {
2849         struct ixgbe_hw *hw =
2850                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2851         if (hw->mac.type == ixgbe_mac_82599EB) {
2852 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2853                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2854                         /* Not suported in bypass mode */
2855                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2856                                      "by device id 0x%x", hw->device_id);
2857                         return -ENOTSUP;
2858                 }
2859 #endif
2860         }
2861
2862         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2863                 /* Turn off the copper */
2864                 ixgbe_set_phy_power(hw, false);
2865         } else {
2866                 /* Turn off the laser */
2867                 ixgbe_disable_tx_laser(hw);
2868         }
2869
2870         return 0;
2871 }
2872
2873 /*
2874  * Reset and stop device.
2875  */
2876 static void
2877 ixgbe_dev_close(struct rte_eth_dev *dev)
2878 {
2879         struct ixgbe_hw *hw =
2880                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2881
2882         PMD_INIT_FUNC_TRACE();
2883
2884         ixgbe_pf_reset_hw(hw);
2885
2886         ixgbe_dev_stop(dev);
2887         hw->adapter_stopped = 1;
2888
2889         ixgbe_dev_free_queues(dev);
2890
2891         ixgbe_disable_pcie_master(hw);
2892
2893         /* reprogram the RAR[0] in case user changed it. */
2894         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2895 }
2896
2897 /*
2898  * Reset PF device.
2899  */
2900 static int
2901 ixgbe_dev_reset(struct rte_eth_dev *dev)
2902 {
2903         int ret;
2904
2905         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2906          * its VF to make them align with it. The detailed notification
2907          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2908          * To avoid unexpected behavior in VF, currently reset of PF with
2909          * SR-IOV activation is not supported. It might be supported later.
2910          */
2911         if (dev->data->sriov.active)
2912                 return -ENOTSUP;
2913
2914         ret = eth_ixgbe_dev_uninit(dev);
2915         if (ret)
2916                 return ret;
2917
2918         ret = eth_ixgbe_dev_init(dev, NULL);
2919
2920         return ret;
2921 }
2922
2923 static void
2924 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2925                            struct ixgbe_hw_stats *hw_stats,
2926                            struct ixgbe_macsec_stats *macsec_stats,
2927                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2928                            uint64_t *total_qprc, uint64_t *total_qprdc)
2929 {
2930         uint32_t bprc, lxon, lxoff, total;
2931         uint32_t delta_gprc = 0;
2932         unsigned i;
2933         /* Workaround for RX byte count not including CRC bytes when CRC
2934          * strip is enabled. CRC bytes are removed from counters when crc_strip
2935          * is disabled.
2936          */
2937         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2938                         IXGBE_HLREG0_RXCRCSTRP);
2939
2940         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2941         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2942         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2943         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2944
2945         for (i = 0; i < 8; i++) {
2946                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2947
2948                 /* global total per queue */
2949                 hw_stats->mpc[i] += mp;
2950                 /* Running comprehensive total for stats display */
2951                 *total_missed_rx += hw_stats->mpc[i];
2952                 if (hw->mac.type == ixgbe_mac_82598EB) {
2953                         hw_stats->rnbc[i] +=
2954                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2955                         hw_stats->pxonrxc[i] +=
2956                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2957                         hw_stats->pxoffrxc[i] +=
2958                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2959                 } else {
2960                         hw_stats->pxonrxc[i] +=
2961                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2962                         hw_stats->pxoffrxc[i] +=
2963                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2964                         hw_stats->pxon2offc[i] +=
2965                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2966                 }
2967                 hw_stats->pxontxc[i] +=
2968                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2969                 hw_stats->pxofftxc[i] +=
2970                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2971         }
2972         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2973                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2974                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2975                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2976
2977                 delta_gprc += delta_qprc;
2978
2979                 hw_stats->qprc[i] += delta_qprc;
2980                 hw_stats->qptc[i] += delta_qptc;
2981
2982                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2983                 hw_stats->qbrc[i] +=
2984                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2985                 if (crc_strip == 0)
2986                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2987
2988                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2989                 hw_stats->qbtc[i] +=
2990                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2991
2992                 hw_stats->qprdc[i] += delta_qprdc;
2993                 *total_qprdc += hw_stats->qprdc[i];
2994
2995                 *total_qprc += hw_stats->qprc[i];
2996                 *total_qbrc += hw_stats->qbrc[i];
2997         }
2998         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2999         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3000         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3001
3002         /*
3003          * An errata states that gprc actually counts good + missed packets:
3004          * Workaround to set gprc to summated queue packet receives
3005          */
3006         hw_stats->gprc = *total_qprc;
3007
3008         if (hw->mac.type != ixgbe_mac_82598EB) {
3009                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3010                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3011                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3012                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3013                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3014                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3015                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3016                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3017         } else {
3018                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3019                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3020                 /* 82598 only has a counter in the high register */
3021                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3022                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3023                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3024         }
3025         uint64_t old_tpr = hw_stats->tpr;
3026
3027         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3028         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3029
3030         if (crc_strip == 0)
3031                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3032
3033         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3034         hw_stats->gptc += delta_gptc;
3035         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3036         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3037
3038         /*
3039          * Workaround: mprc hardware is incorrectly counting
3040          * broadcasts, so for now we subtract those.
3041          */
3042         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3043         hw_stats->bprc += bprc;
3044         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3045         if (hw->mac.type == ixgbe_mac_82598EB)
3046                 hw_stats->mprc -= bprc;
3047
3048         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3049         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3050         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3051         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3052         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3053         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3054
3055         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3056         hw_stats->lxontxc += lxon;
3057         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3058         hw_stats->lxofftxc += lxoff;
3059         total = lxon + lxoff;
3060
3061         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3062         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3063         hw_stats->gptc -= total;
3064         hw_stats->mptc -= total;
3065         hw_stats->ptc64 -= total;
3066         hw_stats->gotc -= total * ETHER_MIN_LEN;
3067
3068         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3069         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3070         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3071         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3072         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3073         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3074         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3075         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3076         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3077         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3078         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3079         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3080         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3081         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3082         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3083         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3084         /* Only read FCOE on 82599 */
3085         if (hw->mac.type != ixgbe_mac_82598EB) {
3086                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3087                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3088                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3089                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3090                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3091         }
3092
3093         /* Flow Director Stats registers */
3094         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3095         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3096
3097         /* MACsec Stats registers */
3098         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3099         macsec_stats->out_pkts_encrypted +=
3100                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3101         macsec_stats->out_pkts_protected +=
3102                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3103         macsec_stats->out_octets_encrypted +=
3104                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3105         macsec_stats->out_octets_protected +=
3106                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3107         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3108         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3109         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3110         macsec_stats->in_pkts_unknownsci +=
3111                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3112         macsec_stats->in_octets_decrypted +=
3113                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3114         macsec_stats->in_octets_validated +=
3115                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3116         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3117         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3118         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3119         for (i = 0; i < 2; i++) {
3120                 macsec_stats->in_pkts_ok +=
3121                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3122                 macsec_stats->in_pkts_invalid +=
3123                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3124                 macsec_stats->in_pkts_notvalid +=
3125                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3126         }
3127         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3128         macsec_stats->in_pkts_notusingsa +=
3129                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3130 }
3131
3132 /*
3133  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3134  */
3135 static int
3136 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3137 {
3138         struct ixgbe_hw *hw =
3139                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3140         struct ixgbe_hw_stats *hw_stats =
3141                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3142         struct ixgbe_macsec_stats *macsec_stats =
3143                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3144                                 dev->data->dev_private);
3145         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3146         unsigned i;
3147
3148         total_missed_rx = 0;
3149         total_qbrc = 0;
3150         total_qprc = 0;
3151         total_qprdc = 0;
3152
3153         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3154                         &total_qbrc, &total_qprc, &total_qprdc);
3155
3156         if (stats == NULL)
3157                 return -EINVAL;
3158
3159         /* Fill out the rte_eth_stats statistics structure */
3160         stats->ipackets = total_qprc;
3161         stats->ibytes = total_qbrc;
3162         stats->opackets = hw_stats->gptc;
3163         stats->obytes = hw_stats->gotc;
3164
3165         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3166                 stats->q_ipackets[i] = hw_stats->qprc[i];
3167                 stats->q_opackets[i] = hw_stats->qptc[i];
3168                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3169                 stats->q_obytes[i] = hw_stats->qbtc[i];
3170                 stats->q_errors[i] = hw_stats->qprdc[i];
3171         }
3172
3173         /* Rx Errors */
3174         stats->imissed  = total_missed_rx;
3175         stats->ierrors  = hw_stats->crcerrs +
3176                           hw_stats->mspdc +
3177                           hw_stats->rlec +
3178                           hw_stats->ruc +
3179                           hw_stats->roc +
3180                           hw_stats->illerrc +
3181                           hw_stats->errbc +
3182                           hw_stats->rfc +
3183                           hw_stats->fccrc +
3184                           hw_stats->fclast;
3185
3186         /* Tx Errors */
3187         stats->oerrors  = 0;
3188         return 0;
3189 }
3190
3191 static void
3192 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3193 {
3194         struct ixgbe_hw_stats *stats =
3195                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3196
3197         /* HW registers are cleared on read */
3198         ixgbe_dev_stats_get(dev, NULL);
3199
3200         /* Reset software totals */
3201         memset(stats, 0, sizeof(*stats));
3202 }
3203
3204 /* This function calculates the number of xstats based on the current config */
3205 static unsigned
3206 ixgbe_xstats_calc_num(void) {
3207         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3208                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3209                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3210 }
3211
3212 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3213         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3214 {
3215         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3216         unsigned stat, i, count;
3217
3218         if (xstats_names != NULL) {
3219                 count = 0;
3220
3221                 /* Note: limit >= cnt_stats checked upstream
3222                  * in rte_eth_xstats_names()
3223                  */
3224
3225                 /* Extended stats from ixgbe_hw_stats */
3226                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3227                         snprintf(xstats_names[count].name,
3228                                 sizeof(xstats_names[count].name),
3229                                 "%s",
3230                                 rte_ixgbe_stats_strings[i].name);
3231                         count++;
3232                 }
3233
3234                 /* MACsec Stats */
3235                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3236                         snprintf(xstats_names[count].name,
3237                                 sizeof(xstats_names[count].name),
3238                                 "%s",
3239                                 rte_ixgbe_macsec_strings[i].name);
3240                         count++;
3241                 }
3242
3243                 /* RX Priority Stats */
3244                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3245                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3246                                 snprintf(xstats_names[count].name,
3247                                         sizeof(xstats_names[count].name),
3248                                         "rx_priority%u_%s", i,
3249                                         rte_ixgbe_rxq_strings[stat].name);
3250                                 count++;
3251                         }
3252                 }
3253
3254                 /* TX Priority Stats */
3255                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3256                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3257                                 snprintf(xstats_names[count].name,
3258                                         sizeof(xstats_names[count].name),
3259                                         "tx_priority%u_%s", i,
3260                                         rte_ixgbe_txq_strings[stat].name);
3261                                 count++;
3262                         }
3263                 }
3264         }
3265         return cnt_stats;
3266 }
3267
3268 static int ixgbe_dev_xstats_get_names_by_id(
3269         struct rte_eth_dev *dev,
3270         struct rte_eth_xstat_name *xstats_names,
3271         const uint64_t *ids,
3272         unsigned int limit)
3273 {
3274         if (!ids) {
3275                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3276                 unsigned int stat, i, count;
3277
3278                 if (xstats_names != NULL) {
3279                         count = 0;
3280
3281                         /* Note: limit >= cnt_stats checked upstream
3282                          * in rte_eth_xstats_names()
3283                          */
3284
3285                         /* Extended stats from ixgbe_hw_stats */
3286                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3287                                 snprintf(xstats_names[count].name,
3288                                         sizeof(xstats_names[count].name),
3289                                         "%s",
3290                                         rte_ixgbe_stats_strings[i].name);
3291                                 count++;
3292                         }
3293
3294                         /* MACsec Stats */
3295                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3296                                 snprintf(xstats_names[count].name,
3297                                         sizeof(xstats_names[count].name),
3298                                         "%s",
3299                                         rte_ixgbe_macsec_strings[i].name);
3300                                 count++;
3301                         }
3302
3303                         /* RX Priority Stats */
3304                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3305                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3306                                         snprintf(xstats_names[count].name,
3307                                             sizeof(xstats_names[count].name),
3308                                             "rx_priority%u_%s", i,
3309                                             rte_ixgbe_rxq_strings[stat].name);
3310                                         count++;
3311                                 }
3312                         }
3313
3314                         /* TX Priority Stats */
3315                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3316                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3317                                         snprintf(xstats_names[count].name,
3318                                             sizeof(xstats_names[count].name),
3319                                             "tx_priority%u_%s", i,
3320                                             rte_ixgbe_txq_strings[stat].name);
3321                                         count++;
3322                                 }
3323                         }
3324                 }
3325                 return cnt_stats;
3326         }
3327
3328         uint16_t i;
3329         uint16_t size = ixgbe_xstats_calc_num();
3330         struct rte_eth_xstat_name xstats_names_copy[size];
3331
3332         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3333                         size);
3334
3335         for (i = 0; i < limit; i++) {
3336                 if (ids[i] >= size) {
3337                         PMD_INIT_LOG(ERR, "id value isn't valid");
3338                         return -1;
3339                 }
3340                 strcpy(xstats_names[i].name,
3341                                 xstats_names_copy[ids[i]].name);
3342         }
3343         return limit;
3344 }
3345
3346 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3347         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3348 {
3349         unsigned i;
3350
3351         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3352                 return -ENOMEM;
3353
3354         if (xstats_names != NULL)
3355                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3356                         snprintf(xstats_names[i].name,
3357                                 sizeof(xstats_names[i].name),
3358                                 "%s", rte_ixgbevf_stats_strings[i].name);
3359         return IXGBEVF_NB_XSTATS;
3360 }
3361
3362 static int
3363 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3364                                          unsigned n)
3365 {
3366         struct ixgbe_hw *hw =
3367                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3368         struct ixgbe_hw_stats *hw_stats =
3369                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3370         struct ixgbe_macsec_stats *macsec_stats =
3371                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3372                                 dev->data->dev_private);
3373         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3374         unsigned i, stat, count = 0;
3375
3376         count = ixgbe_xstats_calc_num();
3377
3378         if (n < count)
3379                 return count;
3380
3381         total_missed_rx = 0;
3382         total_qbrc = 0;
3383         total_qprc = 0;
3384         total_qprdc = 0;
3385
3386         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3387                         &total_qbrc, &total_qprc, &total_qprdc);
3388
3389         /* If this is a reset xstats is NULL, and we have cleared the
3390          * registers by reading them.
3391          */
3392         if (!xstats)
3393                 return 0;
3394
3395         /* Extended stats from ixgbe_hw_stats */
3396         count = 0;
3397         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3398                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3399                                 rte_ixgbe_stats_strings[i].offset);
3400                 xstats[count].id = count;
3401                 count++;
3402         }
3403
3404         /* MACsec Stats */
3405         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3406                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3407                                 rte_ixgbe_macsec_strings[i].offset);
3408                 xstats[count].id = count;
3409                 count++;
3410         }
3411
3412         /* RX Priority Stats */
3413         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3414                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3415                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3416                                         rte_ixgbe_rxq_strings[stat].offset +
3417                                         (sizeof(uint64_t) * i));
3418                         xstats[count].id = count;
3419                         count++;
3420                 }
3421         }
3422
3423         /* TX Priority Stats */
3424         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3425                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3426                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3427                                         rte_ixgbe_txq_strings[stat].offset +
3428                                         (sizeof(uint64_t) * i));
3429                         xstats[count].id = count;
3430                         count++;
3431                 }
3432         }
3433         return count;
3434 }
3435
3436 static int
3437 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3438                 uint64_t *values, unsigned int n)
3439 {
3440         if (!ids) {
3441                 struct ixgbe_hw *hw =
3442                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3443                 struct ixgbe_hw_stats *hw_stats =
3444                                 IXGBE_DEV_PRIVATE_TO_STATS(
3445                                                 dev->data->dev_private);
3446                 struct ixgbe_macsec_stats *macsec_stats =
3447                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3448                                         dev->data->dev_private);
3449                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3450                 unsigned int i, stat, count = 0;
3451
3452                 count = ixgbe_xstats_calc_num();
3453
3454                 if (!ids && n < count)
3455                         return count;
3456
3457                 total_missed_rx = 0;
3458                 total_qbrc = 0;
3459                 total_qprc = 0;
3460                 total_qprdc = 0;
3461
3462                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3463                                 &total_missed_rx, &total_qbrc, &total_qprc,
3464                                 &total_qprdc);
3465
3466                 /* If this is a reset xstats is NULL, and we have cleared the
3467                  * registers by reading them.
3468                  */
3469                 if (!ids && !values)
3470                         return 0;
3471
3472                 /* Extended stats from ixgbe_hw_stats */
3473                 count = 0;
3474                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3475                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3476                                         rte_ixgbe_stats_strings[i].offset);
3477                         count++;
3478                 }
3479
3480                 /* MACsec Stats */
3481                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3482                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3483                                         rte_ixgbe_macsec_strings[i].offset);
3484                         count++;
3485                 }
3486
3487                 /* RX Priority Stats */
3488                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3489                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3490                                 values[count] =
3491                                         *(uint64_t *)(((char *)hw_stats) +
3492                                         rte_ixgbe_rxq_strings[stat].offset +
3493                                         (sizeof(uint64_t) * i));
3494                                 count++;
3495                         }
3496                 }
3497
3498                 /* TX Priority Stats */
3499                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3500                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3501                                 values[count] =
3502                                         *(uint64_t *)(((char *)hw_stats) +
3503                                         rte_ixgbe_txq_strings[stat].offset +
3504                                         (sizeof(uint64_t) * i));
3505                                 count++;
3506                         }
3507                 }
3508                 return count;
3509         }
3510
3511         uint16_t i;
3512         uint16_t size = ixgbe_xstats_calc_num();
3513         uint64_t values_copy[size];
3514
3515         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3516
3517         for (i = 0; i < n; i++) {
3518                 if (ids[i] >= size) {
3519                         PMD_INIT_LOG(ERR, "id value isn't valid");
3520                         return -1;
3521                 }
3522                 values[i] = values_copy[ids[i]];
3523         }
3524         return n;
3525 }
3526
3527 static void
3528 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3529 {
3530         struct ixgbe_hw_stats *stats =
3531                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3532         struct ixgbe_macsec_stats *macsec_stats =
3533                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3534                                 dev->data->dev_private);
3535
3536         unsigned count = ixgbe_xstats_calc_num();
3537
3538         /* HW registers are cleared on read */
3539         ixgbe_dev_xstats_get(dev, NULL, count);
3540
3541         /* Reset software totals */
3542         memset(stats, 0, sizeof(*stats));
3543         memset(macsec_stats, 0, sizeof(*macsec_stats));
3544 }
3545
3546 static void
3547 ixgbevf_update_stats(struct rte_eth_dev *dev)
3548 {
3549         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3550         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3551                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3552
3553         /* Good Rx packet, include VF loopback */
3554         UPDATE_VF_STAT(IXGBE_VFGPRC,
3555             hw_stats->last_vfgprc, hw_stats->vfgprc);
3556
3557         /* Good Rx octets, include VF loopback */
3558         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3559             hw_stats->last_vfgorc, hw_stats->vfgorc);
3560
3561         /* Good Tx packet, include VF loopback */
3562         UPDATE_VF_STAT(IXGBE_VFGPTC,
3563             hw_stats->last_vfgptc, hw_stats->vfgptc);
3564
3565         /* Good Tx octets, include VF loopback */
3566         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3567             hw_stats->last_vfgotc, hw_stats->vfgotc);
3568
3569         /* Rx Multicst Packet */
3570         UPDATE_VF_STAT(IXGBE_VFMPRC,
3571             hw_stats->last_vfmprc, hw_stats->vfmprc);
3572 }
3573
3574 static int
3575 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3576                        unsigned n)
3577 {
3578         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3579                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3580         unsigned i;
3581
3582         if (n < IXGBEVF_NB_XSTATS)
3583                 return IXGBEVF_NB_XSTATS;
3584
3585         ixgbevf_update_stats(dev);
3586
3587         if (!xstats)
3588                 return 0;
3589
3590         /* Extended stats */
3591         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3592                 xstats[i].id = i;
3593                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3594                         rte_ixgbevf_stats_strings[i].offset);
3595         }
3596
3597         return IXGBEVF_NB_XSTATS;
3598 }
3599
3600 static int
3601 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3602 {
3603         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3604                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3605
3606         ixgbevf_update_stats(dev);
3607
3608         if (stats == NULL)
3609                 return -EINVAL;
3610
3611         stats->ipackets = hw_stats->vfgprc;
3612         stats->ibytes = hw_stats->vfgorc;
3613         stats->opackets = hw_stats->vfgptc;
3614         stats->obytes = hw_stats->vfgotc;
3615         return 0;
3616 }
3617
3618 static void
3619 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3620 {
3621         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3622                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3623
3624         /* Sync HW register to the last stats */
3625         ixgbevf_dev_stats_get(dev, NULL);
3626
3627         /* reset HW current stats*/
3628         hw_stats->vfgprc = 0;
3629         hw_stats->vfgorc = 0;
3630         hw_stats->vfgptc = 0;
3631         hw_stats->vfgotc = 0;
3632 }
3633
3634 static int
3635 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3636 {
3637         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3638         u16 eeprom_verh, eeprom_verl;
3639         u32 etrack_id;
3640         int ret;
3641
3642         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3643         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3644
3645         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3646         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3647
3648         ret += 1; /* add the size of '\0' */
3649         if (fw_size < (u32)ret)
3650                 return ret;
3651         else
3652                 return 0;
3653 }
3654
3655 static void
3656 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3657 {
3658         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3659         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3660         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3661
3662         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3663         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3664         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3665                 /*
3666                  * When DCB/VT is off, maximum number of queues changes,
3667                  * except for 82598EB, which remains constant.
3668                  */
3669                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3670                                 hw->mac.type != ixgbe_mac_82598EB)
3671                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3672         }
3673         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3674         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3675         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3676         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3677         dev_info->max_vfs = pci_dev->max_vfs;
3678         if (hw->mac.type == ixgbe_mac_82598EB)
3679                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3680         else
3681                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3682         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3683         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3684         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3685                                      dev_info->rx_queue_offload_capa);
3686         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3687         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3688
3689         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3690                 .rx_thresh = {
3691                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3692                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3693                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3694                 },
3695                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3696                 .rx_drop_en = 0,
3697                 .offloads = 0,
3698         };
3699
3700         dev_info->default_txconf = (struct rte_eth_txconf) {
3701                 .tx_thresh = {
3702                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3703                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3704                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3705                 },
3706                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3707                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3708                 .offloads = 0,
3709         };
3710
3711         dev_info->rx_desc_lim = rx_desc_lim;
3712         dev_info->tx_desc_lim = tx_desc_lim;
3713
3714         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3715         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3716         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3717
3718         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3719         if (hw->mac.type == ixgbe_mac_X540 ||
3720             hw->mac.type == ixgbe_mac_X540_vf ||
3721             hw->mac.type == ixgbe_mac_X550 ||
3722             hw->mac.type == ixgbe_mac_X550_vf) {
3723                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3724         }
3725         if (hw->mac.type == ixgbe_mac_X550) {
3726                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3727                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3728         }
3729 }
3730
3731 static const uint32_t *
3732 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3733 {
3734         static const uint32_t ptypes[] = {
3735                 /* For non-vec functions,
3736                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3737                  * for vec functions,
3738                  * refers to _recv_raw_pkts_vec().
3739                  */
3740                 RTE_PTYPE_L2_ETHER,
3741                 RTE_PTYPE_L3_IPV4,
3742                 RTE_PTYPE_L3_IPV4_EXT,
3743                 RTE_PTYPE_L3_IPV6,
3744                 RTE_PTYPE_L3_IPV6_EXT,
3745                 RTE_PTYPE_L4_SCTP,
3746                 RTE_PTYPE_L4_TCP,
3747                 RTE_PTYPE_L4_UDP,
3748                 RTE_PTYPE_TUNNEL_IP,
3749                 RTE_PTYPE_INNER_L3_IPV6,
3750                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3751                 RTE_PTYPE_INNER_L4_TCP,
3752                 RTE_PTYPE_INNER_L4_UDP,
3753                 RTE_PTYPE_UNKNOWN
3754         };
3755
3756         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3757             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3758             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3759             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3760                 return ptypes;
3761
3762 #if defined(RTE_ARCH_X86)
3763         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3764             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3765                 return ptypes;
3766 #endif
3767         return NULL;
3768 }
3769
3770 static void
3771 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3772                      struct rte_eth_dev_info *dev_info)
3773 {
3774         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3775         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3776
3777         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3778         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3779         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3780         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3781         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3782         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3783         dev_info->max_vfs = pci_dev->max_vfs;
3784         if (hw->mac.type == ixgbe_mac_82598EB)
3785                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3786         else
3787                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3788         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3789         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3790                                      dev_info->rx_queue_offload_capa);
3791         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3792         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3793
3794         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3795                 .rx_thresh = {
3796                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3797                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3798                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3799                 },
3800                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3801                 .rx_drop_en = 0,
3802                 .offloads = 0,
3803         };
3804
3805         dev_info->default_txconf = (struct rte_eth_txconf) {
3806                 .tx_thresh = {
3807                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3808                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3809                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3810                 },
3811                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3812                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3813                 .offloads = 0,
3814         };
3815
3816         dev_info->rx_desc_lim = rx_desc_lim;
3817         dev_info->tx_desc_lim = tx_desc_lim;
3818 }
3819
3820 static int
3821 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3822                    int *link_up, int wait_to_complete)
3823 {
3824         /**
3825          * for a quick link status checking, wait_to_compelet == 0,
3826          * skip PF link status checking
3827          */
3828         bool no_pflink_check = wait_to_complete == 0;
3829         struct ixgbe_mbx_info *mbx = &hw->mbx;
3830         struct ixgbe_mac_info *mac = &hw->mac;
3831         uint32_t links_reg, in_msg;
3832         int ret_val = 0;
3833
3834         /* If we were hit with a reset drop the link */
3835         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3836                 mac->get_link_status = true;
3837
3838         if (!mac->get_link_status)
3839                 goto out;
3840
3841         /* if link status is down no point in checking to see if pf is up */
3842         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3843         if (!(links_reg & IXGBE_LINKS_UP))
3844                 goto out;
3845
3846         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3847          * before the link status is correct
3848          */
3849         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3850                 int i;
3851
3852                 for (i = 0; i < 5; i++) {
3853                         rte_delay_us(100);
3854                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3855
3856                         if (!(links_reg & IXGBE_LINKS_UP))
3857                                 goto out;
3858                 }
3859         }
3860
3861         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3862         case IXGBE_LINKS_SPEED_10G_82599:
3863                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3864                 if (hw->mac.type >= ixgbe_mac_X550) {
3865                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3866                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3867                 }
3868                 break;
3869         case IXGBE_LINKS_SPEED_1G_82599:
3870                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3871                 break;
3872         case IXGBE_LINKS_SPEED_100_82599:
3873                 *speed = IXGBE_LINK_SPEED_100_FULL;
3874                 if (hw->mac.type == ixgbe_mac_X550) {
3875                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3876                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3877                 }
3878                 break;
3879         case IXGBE_LINKS_SPEED_10_X550EM_A:
3880                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3881                 /* Since Reserved in older MAC's */
3882                 if (hw->mac.type >= ixgbe_mac_X550)
3883                         *speed = IXGBE_LINK_SPEED_10_FULL;
3884                 break;
3885         default:
3886                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3887         }
3888
3889         if (no_pflink_check) {
3890                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3891                         mac->get_link_status = true;
3892                 else
3893                         mac->get_link_status = false;
3894
3895                 goto out;
3896         }
3897         /* if the read failed it could just be a mailbox collision, best wait
3898          * until we are called again and don't report an error
3899          */
3900         if (mbx->ops.read(hw, &in_msg, 1, 0))
3901                 goto out;
3902
3903         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3904                 /* msg is not CTS and is NACK we must have lost CTS status */
3905                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3906                         ret_val = -1;
3907                 goto out;
3908         }
3909
3910         /* the pf is talking, if we timed out in the past we reinit */
3911         if (!mbx->timeout) {
3912                 ret_val = -1;
3913                 goto out;
3914         }
3915
3916         /* if we passed all the tests above then the link is up and we no
3917          * longer need to check for link
3918          */
3919         mac->get_link_status = false;
3920
3921 out:
3922         *link_up = !mac->get_link_status;
3923         return ret_val;
3924 }
3925
3926 /* return 0 means link status changed, -1 means not changed */
3927 int
3928 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3929                             int wait_to_complete, int vf)
3930 {
3931         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3932         struct rte_eth_link link;
3933         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3934         struct ixgbe_interrupt *intr =
3935                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3936         int link_up;
3937         int diag;
3938         u32 speed = 0;
3939         int wait = 1;
3940         bool autoneg = false;
3941
3942         memset(&link, 0, sizeof(link));
3943         link.link_status = ETH_LINK_DOWN;
3944         link.link_speed = ETH_SPEED_NUM_NONE;
3945         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3946         link.link_autoneg = ETH_LINK_AUTONEG;
3947
3948         hw->mac.get_link_status = true;
3949
3950         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3951                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3952                 speed = hw->phy.autoneg_advertised;
3953                 if (!speed)
3954                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3955                 ixgbe_setup_link(hw, speed, true);
3956         }
3957
3958         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3959         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3960                 wait = 0;
3961
3962         if (vf)
3963                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3964         else
3965                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3966
3967         if (diag != 0) {
3968                 link.link_speed = ETH_SPEED_NUM_100M;
3969                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3970                 return rte_eth_linkstatus_set(dev, &link);
3971         }
3972
3973         if (link_up == 0) {
3974                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3975                 return rte_eth_linkstatus_set(dev, &link);
3976         }
3977
3978         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3979         link.link_status = ETH_LINK_UP;
3980         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3981
3982         switch (link_speed) {
3983         default:
3984         case IXGBE_LINK_SPEED_UNKNOWN:
3985                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3986                 link.link_speed = ETH_SPEED_NUM_100M;
3987                 break;
3988
3989         case IXGBE_LINK_SPEED_100_FULL:
3990                 link.link_speed = ETH_SPEED_NUM_100M;
3991                 break;
3992
3993         case IXGBE_LINK_SPEED_1GB_FULL:
3994                 link.link_speed = ETH_SPEED_NUM_1G;
3995                 break;
3996
3997         case IXGBE_LINK_SPEED_2_5GB_FULL:
3998                 link.link_speed = ETH_SPEED_NUM_2_5G;
3999                 break;
4000
4001         case IXGBE_LINK_SPEED_5GB_FULL:
4002                 link.link_speed = ETH_SPEED_NUM_5G;
4003                 break;
4004
4005         case IXGBE_LINK_SPEED_10GB_FULL:
4006                 link.link_speed = ETH_SPEED_NUM_10G;
4007                 break;
4008         }
4009
4010         return rte_eth_linkstatus_set(dev, &link);
4011 }
4012
4013 static int
4014 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4015 {
4016         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4017 }
4018
4019 static int
4020 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4021 {
4022         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4023 }
4024
4025 static void
4026 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4027 {
4028         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4029         uint32_t fctrl;
4030
4031         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4032         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4033         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4034 }
4035
4036 static void
4037 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4038 {
4039         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4040         uint32_t fctrl;
4041
4042         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4043         fctrl &= (~IXGBE_FCTRL_UPE);
4044         if (dev->data->all_multicast == 1)
4045                 fctrl |= IXGBE_FCTRL_MPE;
4046         else
4047                 fctrl &= (~IXGBE_FCTRL_MPE);
4048         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4049 }
4050
4051 static void
4052 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4053 {
4054         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4055         uint32_t fctrl;
4056
4057         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4058         fctrl |= IXGBE_FCTRL_MPE;
4059         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4060 }
4061
4062 static void
4063 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4064 {
4065         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4066         uint32_t fctrl;
4067
4068         if (dev->data->promiscuous == 1)
4069                 return; /* must remain in all_multicast mode */
4070
4071         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4072         fctrl &= (~IXGBE_FCTRL_MPE);
4073         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4074 }
4075
4076 /**
4077  * It clears the interrupt causes and enables the interrupt.
4078  * It will be called once only during nic initialized.
4079  *
4080  * @param dev
4081  *  Pointer to struct rte_eth_dev.
4082  * @param on
4083  *  Enable or Disable.
4084  *
4085  * @return
4086  *  - On success, zero.
4087  *  - On failure, a negative value.
4088  */
4089 static int
4090 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4091 {
4092         struct ixgbe_interrupt *intr =
4093                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4094
4095         ixgbe_dev_link_status_print(dev);
4096         if (on)
4097                 intr->mask |= IXGBE_EICR_LSC;
4098         else
4099                 intr->mask &= ~IXGBE_EICR_LSC;
4100
4101         return 0;
4102 }
4103
4104 /**
4105  * It clears the interrupt causes and enables the interrupt.
4106  * It will be called once only during nic initialized.
4107  *
4108  * @param dev
4109  *  Pointer to struct rte_eth_dev.
4110  *
4111  * @return
4112  *  - On success, zero.
4113  *  - On failure, a negative value.
4114  */
4115 static int
4116 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4117 {
4118         struct ixgbe_interrupt *intr =
4119                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4120
4121         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4122
4123         return 0;
4124 }
4125
4126 /**
4127  * It clears the interrupt causes and enables the interrupt.
4128  * It will be called once only during nic initialized.
4129  *
4130  * @param dev
4131  *  Pointer to struct rte_eth_dev.
4132  *
4133  * @return
4134  *  - On success, zero.
4135  *  - On failure, a negative value.
4136  */
4137 static int
4138 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4139 {
4140         struct ixgbe_interrupt *intr =
4141                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4142
4143         intr->mask |= IXGBE_EICR_LINKSEC;
4144
4145         return 0;
4146 }
4147
4148 /*
4149  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4150  *
4151  * @param dev
4152  *  Pointer to struct rte_eth_dev.
4153  *
4154  * @return
4155  *  - On success, zero.
4156  *  - On failure, a negative value.
4157  */
4158 static int
4159 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4160 {
4161         uint32_t eicr;
4162         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4163         struct ixgbe_interrupt *intr =
4164                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4165
4166         /* clear all cause mask */
4167         ixgbe_disable_intr(hw);
4168
4169         /* read-on-clear nic registers here */
4170         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4171         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4172
4173         intr->flags = 0;
4174
4175         /* set flag for async link update */
4176         if (eicr & IXGBE_EICR_LSC)
4177                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4178
4179         if (eicr & IXGBE_EICR_MAILBOX)
4180                 intr->flags |= IXGBE_FLAG_MAILBOX;
4181
4182         if (eicr & IXGBE_EICR_LINKSEC)
4183                 intr->flags |= IXGBE_FLAG_MACSEC;
4184
4185         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4186             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4187             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4188                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4189
4190         return 0;
4191 }
4192
4193 /**
4194  * It gets and then prints the link status.
4195  *
4196  * @param dev
4197  *  Pointer to struct rte_eth_dev.
4198  *
4199  * @return
4200  *  - On success, zero.
4201  *  - On failure, a negative value.
4202  */
4203 static void
4204 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4205 {
4206         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4207         struct rte_eth_link link;
4208
4209         rte_eth_linkstatus_get(dev, &link);
4210
4211         if (link.link_status) {
4212                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4213                                         (int)(dev->data->port_id),
4214                                         (unsigned)link.link_speed,
4215                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4216                                         "full-duplex" : "half-duplex");
4217         } else {
4218                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4219                                 (int)(dev->data->port_id));
4220         }
4221         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4222                                 pci_dev->addr.domain,
4223                                 pci_dev->addr.bus,
4224                                 pci_dev->addr.devid,
4225                                 pci_dev->addr.function);
4226 }
4227
4228 /*
4229  * It executes link_update after knowing an interrupt occurred.
4230  *
4231  * @param dev
4232  *  Pointer to struct rte_eth_dev.
4233  *
4234  * @return
4235  *  - On success, zero.
4236  *  - On failure, a negative value.
4237  */
4238 static int
4239 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4240                            struct rte_intr_handle *intr_handle)
4241 {
4242         struct ixgbe_interrupt *intr =
4243                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4244         int64_t timeout;
4245         struct ixgbe_hw *hw =
4246                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4247
4248         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4249
4250         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4251                 ixgbe_pf_mbx_process(dev);
4252                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4253         }
4254
4255         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4256                 ixgbe_handle_lasi(hw);
4257                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4258         }
4259
4260         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4261                 struct rte_eth_link link;
4262
4263                 /* get the link status before link update, for predicting later */
4264                 rte_eth_linkstatus_get(dev, &link);
4265
4266                 ixgbe_dev_link_update(dev, 0);
4267
4268                 /* likely to up */
4269                 if (!link.link_status)
4270                         /* handle it 1 sec later, wait it being stable */
4271                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4272                 /* likely to down */
4273                 else
4274                         /* handle it 4 sec later, wait it being stable */
4275                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4276
4277                 ixgbe_dev_link_status_print(dev);
4278                 if (rte_eal_alarm_set(timeout * 1000,
4279                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4280                         PMD_DRV_LOG(ERR, "Error setting alarm");
4281                 else {
4282                         /* remember original mask */
4283                         intr->mask_original = intr->mask;
4284                         /* only disable lsc interrupt */
4285                         intr->mask &= ~IXGBE_EIMS_LSC;
4286                 }
4287         }
4288
4289         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4290         ixgbe_enable_intr(dev);
4291         rte_intr_enable(intr_handle);
4292
4293         return 0;
4294 }
4295
4296 /**
4297  * Interrupt handler which shall be registered for alarm callback for delayed
4298  * handling specific interrupt to wait for the stable nic state. As the
4299  * NIC interrupt state is not stable for ixgbe after link is just down,
4300  * it needs to wait 4 seconds to get the stable status.
4301  *
4302  * @param handle
4303  *  Pointer to interrupt handle.
4304  * @param param
4305  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4306  *
4307  * @return
4308  *  void
4309  */
4310 static void
4311 ixgbe_dev_interrupt_delayed_handler(void *param)
4312 {
4313         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4314         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4315         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4316         struct ixgbe_interrupt *intr =
4317                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4318         struct ixgbe_hw *hw =
4319                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4320         uint32_t eicr;
4321
4322         ixgbe_disable_intr(hw);
4323
4324         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4325         if (eicr & IXGBE_EICR_MAILBOX)
4326                 ixgbe_pf_mbx_process(dev);
4327
4328         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4329                 ixgbe_handle_lasi(hw);
4330                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4331         }
4332
4333         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4334                 ixgbe_dev_link_update(dev, 0);
4335                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4336                 ixgbe_dev_link_status_print(dev);
4337                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4338                                               NULL);
4339         }
4340
4341         if (intr->flags & IXGBE_FLAG_MACSEC) {
4342                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4343                                               NULL);
4344                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4345         }
4346
4347         /* restore original mask */
4348         intr->mask = intr->mask_original;
4349         intr->mask_original = 0;
4350
4351         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4352         ixgbe_enable_intr(dev);
4353         rte_intr_enable(intr_handle);
4354 }
4355
4356 /**
4357  * Interrupt handler triggered by NIC  for handling
4358  * specific interrupt.
4359  *
4360  * @param handle
4361  *  Pointer to interrupt handle.
4362  * @param param
4363  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4364  *
4365  * @return
4366  *  void
4367  */
4368 static void
4369 ixgbe_dev_interrupt_handler(void *param)
4370 {
4371         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4372
4373         ixgbe_dev_interrupt_get_status(dev);
4374         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4375 }
4376
4377 static int
4378 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4379 {
4380         struct ixgbe_hw *hw;
4381
4382         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4383         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4384 }
4385
4386 static int
4387 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4388 {
4389         struct ixgbe_hw *hw;
4390
4391         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4392         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4393 }
4394
4395 static int
4396 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4397 {
4398         struct ixgbe_hw *hw;
4399         uint32_t mflcn_reg;
4400         uint32_t fccfg_reg;
4401         int rx_pause;
4402         int tx_pause;
4403
4404         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4405
4406         fc_conf->pause_time = hw->fc.pause_time;
4407         fc_conf->high_water = hw->fc.high_water[0];
4408         fc_conf->low_water = hw->fc.low_water[0];
4409         fc_conf->send_xon = hw->fc.send_xon;
4410         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4411
4412         /*
4413          * Return rx_pause status according to actual setting of
4414          * MFLCN register.
4415          */
4416         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4417         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4418                 rx_pause = 1;
4419         else
4420                 rx_pause = 0;
4421
4422         /*
4423          * Return tx_pause status according to actual setting of
4424          * FCCFG register.
4425          */
4426         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4427         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4428                 tx_pause = 1;
4429         else
4430                 tx_pause = 0;
4431
4432         if (rx_pause && tx_pause)
4433                 fc_conf->mode = RTE_FC_FULL;
4434         else if (rx_pause)
4435                 fc_conf->mode = RTE_FC_RX_PAUSE;
4436         else if (tx_pause)
4437                 fc_conf->mode = RTE_FC_TX_PAUSE;
4438         else
4439                 fc_conf->mode = RTE_FC_NONE;
4440
4441         return 0;
4442 }
4443
4444 static int
4445 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4446 {
4447         struct ixgbe_hw *hw;
4448         int err;
4449         uint32_t rx_buf_size;
4450         uint32_t max_high_water;
4451         uint32_t mflcn;
4452         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4453                 ixgbe_fc_none,
4454                 ixgbe_fc_rx_pause,
4455                 ixgbe_fc_tx_pause,
4456                 ixgbe_fc_full
4457         };
4458
4459         PMD_INIT_FUNC_TRACE();
4460
4461         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4462         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4463         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4464
4465         /*
4466          * At least reserve one Ethernet frame for watermark
4467          * high_water/low_water in kilo bytes for ixgbe
4468          */
4469         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4470         if ((fc_conf->high_water > max_high_water) ||
4471                 (fc_conf->high_water < fc_conf->low_water)) {
4472                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4473                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4474                 return -EINVAL;
4475         }
4476
4477         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4478         hw->fc.pause_time     = fc_conf->pause_time;
4479         hw->fc.high_water[0]  = fc_conf->high_water;
4480         hw->fc.low_water[0]   = fc_conf->low_water;
4481         hw->fc.send_xon       = fc_conf->send_xon;
4482         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4483
4484         err = ixgbe_fc_enable(hw);
4485
4486         /* Not negotiated is not an error case */
4487         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4488
4489                 /* check if we want to forward MAC frames - driver doesn't have native
4490                  * capability to do that, so we'll write the registers ourselves */
4491
4492                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4493
4494                 /* set or clear MFLCN.PMCF bit depending on configuration */
4495                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4496                         mflcn |= IXGBE_MFLCN_PMCF;
4497                 else
4498                         mflcn &= ~IXGBE_MFLCN_PMCF;
4499
4500                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4501                 IXGBE_WRITE_FLUSH(hw);
4502
4503                 return 0;
4504         }
4505
4506         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4507         return -EIO;
4508 }
4509
4510 /**
4511  *  ixgbe_pfc_enable_generic - Enable flow control
4512  *  @hw: pointer to hardware structure
4513  *  @tc_num: traffic class number
4514  *  Enable flow control according to the current settings.
4515  */
4516 static int
4517 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4518 {
4519         int ret_val = 0;
4520         uint32_t mflcn_reg, fccfg_reg;
4521         uint32_t reg;
4522         uint32_t fcrtl, fcrth;
4523         uint8_t i;
4524         uint8_t nb_rx_en;
4525
4526         /* Validate the water mark configuration */
4527         if (!hw->fc.pause_time) {
4528                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4529                 goto out;
4530         }
4531
4532         /* Low water mark of zero causes XOFF floods */
4533         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4534                  /* High/Low water can not be 0 */
4535                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4536                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4537                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4538                         goto out;
4539                 }
4540
4541                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4542                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4543                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4544                         goto out;
4545                 }
4546         }
4547         /* Negotiate the fc mode to use */
4548         ixgbe_fc_autoneg(hw);
4549
4550         /* Disable any previous flow control settings */
4551         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4552         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4553
4554         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4555         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4556
4557         switch (hw->fc.current_mode) {
4558         case ixgbe_fc_none:
4559                 /*
4560                  * If the count of enabled RX Priority Flow control >1,
4561                  * and the TX pause can not be disabled
4562                  */
4563                 nb_rx_en = 0;
4564                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4565                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4566                         if (reg & IXGBE_FCRTH_FCEN)
4567                                 nb_rx_en++;
4568                 }
4569                 if (nb_rx_en > 1)
4570                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4571                 break;
4572         case ixgbe_fc_rx_pause:
4573                 /*
4574                  * Rx Flow control is enabled and Tx Flow control is
4575                  * disabled by software override. Since there really
4576                  * isn't a way to advertise that we are capable of RX
4577                  * Pause ONLY, we will advertise that we support both
4578                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4579                  * disable the adapter's ability to send PAUSE frames.
4580                  */
4581                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4582                 /*
4583                  * If the count of enabled RX Priority Flow control >1,
4584                  * and the TX pause can not be disabled
4585                  */
4586                 nb_rx_en = 0;
4587                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4588                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4589                         if (reg & IXGBE_FCRTH_FCEN)
4590                                 nb_rx_en++;
4591                 }
4592                 if (nb_rx_en > 1)
4593                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4594                 break;
4595         case ixgbe_fc_tx_pause:
4596                 /*
4597                  * Tx Flow control is enabled, and Rx Flow control is
4598                  * disabled by software override.
4599                  */
4600                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4601                 break;
4602         case ixgbe_fc_full:
4603                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4604                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4605                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4606                 break;
4607         default:
4608                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4609                 ret_val = IXGBE_ERR_CONFIG;
4610                 goto out;
4611         }
4612
4613         /* Set 802.3x based flow control settings. */
4614         mflcn_reg |= IXGBE_MFLCN_DPF;
4615         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4616         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4617
4618         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4619         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4620                 hw->fc.high_water[tc_num]) {
4621                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4622                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4623                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4624         } else {
4625                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4626                 /*
4627                  * In order to prevent Tx hangs when the internal Tx
4628                  * switch is enabled we must set the high water mark
4629                  * to the maximum FCRTH value.  This allows the Tx
4630                  * switch to function even under heavy Rx workloads.
4631                  */
4632                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4633         }
4634         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4635
4636         /* Configure pause time (2 TCs per register) */
4637         reg = hw->fc.pause_time * 0x00010001;
4638         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4639                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4640
4641         /* Configure flow control refresh threshold value */
4642         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4643
4644 out:
4645         return ret_val;
4646 }
4647
4648 static int
4649 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4650 {
4651         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4652         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4653
4654         if (hw->mac.type != ixgbe_mac_82598EB) {
4655                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4656         }
4657         return ret_val;
4658 }
4659
4660 static int
4661 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4662 {
4663         int err;
4664         uint32_t rx_buf_size;
4665         uint32_t max_high_water;
4666         uint8_t tc_num;
4667         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4668         struct ixgbe_hw *hw =
4669                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4670         struct ixgbe_dcb_config *dcb_config =
4671                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4672
4673         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4674                 ixgbe_fc_none,
4675                 ixgbe_fc_rx_pause,
4676                 ixgbe_fc_tx_pause,
4677                 ixgbe_fc_full
4678         };
4679
4680         PMD_INIT_FUNC_TRACE();
4681
4682         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4683         tc_num = map[pfc_conf->priority];
4684         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4685         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4686         /*
4687          * At least reserve one Ethernet frame for watermark
4688          * high_water/low_water in kilo bytes for ixgbe
4689          */
4690         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4691         if ((pfc_conf->fc.high_water > max_high_water) ||
4692             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4693                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4694                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4695                 return -EINVAL;
4696         }
4697
4698         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4699         hw->fc.pause_time = pfc_conf->fc.pause_time;
4700         hw->fc.send_xon = pfc_conf->fc.send_xon;
4701         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4702         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4703
4704         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4705
4706         /* Not negotiated is not an error case */
4707         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4708                 return 0;
4709
4710         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4711         return -EIO;
4712 }
4713
4714 static int
4715 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4716                           struct rte_eth_rss_reta_entry64 *reta_conf,
4717                           uint16_t reta_size)
4718 {
4719         uint16_t i, sp_reta_size;
4720         uint8_t j, mask;
4721         uint32_t reta, r;
4722         uint16_t idx, shift;
4723         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4724         uint32_t reta_reg;
4725
4726         PMD_INIT_FUNC_TRACE();
4727
4728         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4729                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4730                         "NIC.");
4731                 return -ENOTSUP;
4732         }
4733
4734         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4735         if (reta_size != sp_reta_size) {
4736                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4737                         "(%d) doesn't match the number hardware can supported "
4738                         "(%d)", reta_size, sp_reta_size);
4739                 return -EINVAL;
4740         }
4741
4742         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4743                 idx = i / RTE_RETA_GROUP_SIZE;
4744                 shift = i % RTE_RETA_GROUP_SIZE;
4745                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4746                                                 IXGBE_4_BIT_MASK);
4747                 if (!mask)
4748                         continue;
4749                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4750                 if (mask == IXGBE_4_BIT_MASK)
4751                         r = 0;
4752                 else
4753                         r = IXGBE_READ_REG(hw, reta_reg);
4754                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4755                         if (mask & (0x1 << j))
4756                                 reta |= reta_conf[idx].reta[shift + j] <<
4757                                                         (CHAR_BIT * j);
4758                         else
4759                                 reta |= r & (IXGBE_8_BIT_MASK <<
4760                                                 (CHAR_BIT * j));
4761                 }
4762                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4763         }
4764
4765         return 0;
4766 }
4767
4768 static int
4769 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4770                          struct rte_eth_rss_reta_entry64 *reta_conf,
4771                          uint16_t reta_size)
4772 {
4773         uint16_t i, sp_reta_size;
4774         uint8_t j, mask;
4775         uint32_t reta;
4776         uint16_t idx, shift;
4777         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4778         uint32_t reta_reg;
4779
4780         PMD_INIT_FUNC_TRACE();
4781         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4782         if (reta_size != sp_reta_size) {
4783                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4784                         "(%d) doesn't match the number hardware can supported "
4785                         "(%d)", reta_size, sp_reta_size);
4786                 return -EINVAL;
4787         }
4788
4789         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4790                 idx = i / RTE_RETA_GROUP_SIZE;
4791                 shift = i % RTE_RETA_GROUP_SIZE;
4792                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4793                                                 IXGBE_4_BIT_MASK);
4794                 if (!mask)
4795                         continue;
4796
4797                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4798                 reta = IXGBE_READ_REG(hw, reta_reg);
4799                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4800                         if (mask & (0x1 << j))
4801                                 reta_conf[idx].reta[shift + j] =
4802                                         ((reta >> (CHAR_BIT * j)) &
4803                                                 IXGBE_8_BIT_MASK);
4804                 }
4805         }
4806
4807         return 0;
4808 }
4809
4810 static int
4811 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4812                                 uint32_t index, uint32_t pool)
4813 {
4814         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4815         uint32_t enable_addr = 1;
4816
4817         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4818                              pool, enable_addr);
4819 }
4820
4821 static void
4822 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4823 {
4824         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4825
4826         ixgbe_clear_rar(hw, index);
4827 }
4828
4829 static int
4830 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4831 {
4832         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4833
4834         ixgbe_remove_rar(dev, 0);
4835         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4836
4837         return 0;
4838 }
4839
4840 static bool
4841 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4842 {
4843         if (strcmp(dev->device->driver->name, drv->driver.name))
4844                 return false;
4845
4846         return true;
4847 }
4848
4849 bool
4850 is_ixgbe_supported(struct rte_eth_dev *dev)
4851 {
4852         return is_device_supported(dev, &rte_ixgbe_pmd);
4853 }
4854
4855 static int
4856 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4857 {
4858         uint32_t hlreg0;
4859         uint32_t maxfrs;
4860         struct ixgbe_hw *hw;
4861         struct rte_eth_dev_info dev_info;
4862         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4863         struct rte_eth_dev_data *dev_data = dev->data;
4864
4865         ixgbe_dev_info_get(dev, &dev_info);
4866
4867         /* check that mtu is within the allowed range */
4868         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4869                 return -EINVAL;
4870
4871         /* If device is started, refuse mtu that requires the support of
4872          * scattered packets when this feature has not been enabled before.
4873          */
4874         if (dev_data->dev_started && !dev_data->scattered_rx &&
4875             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4876              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4877                 PMD_INIT_LOG(ERR, "Stop port first.");
4878                 return -EINVAL;
4879         }
4880
4881         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4882         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4883
4884         /* switch to jumbo mode if needed */
4885         if (frame_size > ETHER_MAX_LEN) {
4886                 dev->data->dev_conf.rxmode.offloads |=
4887                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4888                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4889         } else {
4890                 dev->data->dev_conf.rxmode.offloads &=
4891                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4892                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4893         }
4894         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4895
4896         /* update max frame size */
4897         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4898
4899         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4900         maxfrs &= 0x0000FFFF;
4901         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4902         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4903
4904         return 0;
4905 }
4906
4907 /*
4908  * Virtual Function operations
4909  */
4910 static void
4911 ixgbevf_intr_disable(struct rte_eth_dev *dev)
4912 {
4913         struct ixgbe_interrupt *intr =
4914                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4915         struct ixgbe_hw *hw =
4916                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4917
4918         PMD_INIT_FUNC_TRACE();
4919
4920         /* Clear interrupt mask to stop from interrupts being generated */
4921         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4922
4923         IXGBE_WRITE_FLUSH(hw);
4924
4925         /* Clear mask value. */
4926         intr->mask = 0;
4927 }
4928
4929 static void
4930 ixgbevf_intr_enable(struct rte_eth_dev *dev)
4931 {
4932         struct ixgbe_interrupt *intr =
4933                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4934         struct ixgbe_hw *hw =
4935                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4936
4937         PMD_INIT_FUNC_TRACE();
4938
4939         /* VF enable interrupt autoclean */
4940         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4941         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4942         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4943
4944         IXGBE_WRITE_FLUSH(hw);
4945
4946         /* Save IXGBE_VTEIMS value to mask. */
4947         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
4948 }
4949
4950 static int
4951 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4952 {
4953         struct rte_eth_conf *conf = &dev->data->dev_conf;
4954         struct ixgbe_adapter *adapter =
4955                         (struct ixgbe_adapter *)dev->data->dev_private;
4956
4957         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4958                      dev->data->port_id);
4959
4960         /*
4961          * VF has no ability to enable/disable HW CRC
4962          * Keep the persistent behavior the same as Host PF
4963          */
4964 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4965         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
4966                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4967                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
4968         }
4969 #else
4970         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
4971                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4972                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_CRC_STRIP;
4973         }
4974 #endif
4975
4976         /*
4977          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4978          * allocation or vector Rx preconditions we will reset it.
4979          */
4980         adapter->rx_bulk_alloc_allowed = true;
4981         adapter->rx_vec_allowed = true;
4982
4983         return 0;
4984 }
4985
4986 static int
4987 ixgbevf_dev_start(struct rte_eth_dev *dev)
4988 {
4989         struct ixgbe_hw *hw =
4990                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4991         uint32_t intr_vector = 0;
4992         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4993         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4994
4995         int err, mask = 0;
4996
4997         PMD_INIT_FUNC_TRACE();
4998
4999         err = hw->mac.ops.reset_hw(hw);
5000         if (err) {
5001                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5002                 return err;
5003         }
5004         hw->mac.get_link_status = true;
5005
5006         /* negotiate mailbox API version to use with the PF. */
5007         ixgbevf_negotiate_api(hw);
5008
5009         ixgbevf_dev_tx_init(dev);
5010
5011         /* This can fail when allocating mbufs for descriptor rings */
5012         err = ixgbevf_dev_rx_init(dev);
5013         if (err) {
5014                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5015                 ixgbe_dev_clear_queues(dev);
5016                 return err;
5017         }
5018
5019         /* Set vfta */
5020         ixgbevf_set_vfta_all(dev, 1);
5021
5022         /* Set HW strip */
5023         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5024                 ETH_VLAN_EXTEND_MASK;
5025         err = ixgbevf_vlan_offload_set(dev, mask);
5026         if (err) {
5027                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5028                 ixgbe_dev_clear_queues(dev);
5029                 return err;
5030         }
5031
5032         ixgbevf_dev_rxtx_start(dev);
5033
5034         ixgbevf_dev_link_update(dev, 0);
5035
5036         /* check and configure queue intr-vector mapping */
5037         if (rte_intr_cap_multiple(intr_handle) &&
5038             dev->data->dev_conf.intr_conf.rxq) {
5039                 /* According to datasheet, only vector 0/1/2 can be used,
5040                  * now only one vector is used for Rx queue
5041                  */
5042                 intr_vector = 1;
5043                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5044                         return -1;
5045         }
5046
5047         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5048                 intr_handle->intr_vec =
5049                         rte_zmalloc("intr_vec",
5050                                     dev->data->nb_rx_queues * sizeof(int), 0);
5051                 if (intr_handle->intr_vec == NULL) {
5052                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5053                                      " intr_vec", dev->data->nb_rx_queues);
5054                         return -ENOMEM;
5055                 }
5056         }
5057         ixgbevf_configure_msix(dev);
5058
5059         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5060          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5061          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5062          * is not cleared, it will fail when following rte_intr_enable( ) tries
5063          * to map Rx queue interrupt to other VFIO vectors.
5064          * So clear uio/vfio intr/evevnfd first to avoid failure.
5065          */
5066         rte_intr_disable(intr_handle);
5067
5068         rte_intr_enable(intr_handle);
5069
5070         /* Re-enable interrupt for VF */
5071         ixgbevf_intr_enable(dev);
5072
5073         return 0;
5074 }
5075
5076 static void
5077 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5078 {
5079         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5080         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5081         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5082
5083         PMD_INIT_FUNC_TRACE();
5084
5085         ixgbevf_intr_disable(dev);
5086
5087         hw->adapter_stopped = 1;
5088         ixgbe_stop_adapter(hw);
5089
5090         /*
5091           * Clear what we set, but we still keep shadow_vfta to
5092           * restore after device starts
5093           */
5094         ixgbevf_set_vfta_all(dev, 0);
5095
5096         /* Clear stored conf */
5097         dev->data->scattered_rx = 0;
5098
5099         ixgbe_dev_clear_queues(dev);
5100
5101         /* Clean datapath event and queue/vec mapping */
5102         rte_intr_efd_disable(intr_handle);
5103         if (intr_handle->intr_vec != NULL) {
5104                 rte_free(intr_handle->intr_vec);
5105                 intr_handle->intr_vec = NULL;
5106         }
5107 }
5108
5109 static void
5110 ixgbevf_dev_close(struct rte_eth_dev *dev)
5111 {
5112         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5113
5114         PMD_INIT_FUNC_TRACE();
5115
5116         ixgbe_reset_hw(hw);
5117
5118         ixgbevf_dev_stop(dev);
5119
5120         ixgbe_dev_free_queues(dev);
5121
5122         /**
5123          * Remove the VF MAC address ro ensure
5124          * that the VF traffic goes to the PF
5125          * after stop, close and detach of the VF
5126          **/
5127         ixgbevf_remove_mac_addr(dev, 0);
5128 }
5129
5130 /*
5131  * Reset VF device
5132  */
5133 static int
5134 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5135 {
5136         int ret;
5137
5138         ret = eth_ixgbevf_dev_uninit(dev);
5139         if (ret)
5140                 return ret;
5141
5142         ret = eth_ixgbevf_dev_init(dev);
5143
5144         return ret;
5145 }
5146
5147 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5148 {
5149         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5150         struct ixgbe_vfta *shadow_vfta =
5151                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5152         int i = 0, j = 0, vfta = 0, mask = 1;
5153
5154         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5155                 vfta = shadow_vfta->vfta[i];
5156                 if (vfta) {
5157                         mask = 1;
5158                         for (j = 0; j < 32; j++) {
5159                                 if (vfta & mask)
5160                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5161                                                        on, false);
5162                                 mask <<= 1;
5163                         }
5164                 }
5165         }
5166
5167 }
5168
5169 static int
5170 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5171 {
5172         struct ixgbe_hw *hw =
5173                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5174         struct ixgbe_vfta *shadow_vfta =
5175                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5176         uint32_t vid_idx = 0;
5177         uint32_t vid_bit = 0;
5178         int ret = 0;
5179
5180         PMD_INIT_FUNC_TRACE();
5181
5182         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5183         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5184         if (ret) {
5185                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5186                 return ret;
5187         }
5188         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5189         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5190
5191         /* Save what we set and retore it after device reset */
5192         if (on)
5193                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5194         else
5195                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5196
5197         return 0;
5198 }
5199
5200 static void
5201 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5202 {
5203         struct ixgbe_hw *hw =
5204                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5205         uint32_t ctrl;
5206
5207         PMD_INIT_FUNC_TRACE();
5208
5209         if (queue >= hw->mac.max_rx_queues)
5210                 return;
5211
5212         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5213         if (on)
5214                 ctrl |= IXGBE_RXDCTL_VME;
5215         else
5216                 ctrl &= ~IXGBE_RXDCTL_VME;
5217         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5218
5219         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5220 }
5221
5222 static int
5223 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5224 {
5225         struct ixgbe_rx_queue *rxq;
5226         uint16_t i;
5227         int on = 0;
5228
5229         /* VF function only support hw strip feature, others are not support */
5230         if (mask & ETH_VLAN_STRIP_MASK) {
5231                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5232                         rxq = dev->data->rx_queues[i];
5233                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5234                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5235                 }
5236         }
5237
5238         return 0;
5239 }
5240
5241 int
5242 ixgbe_vt_check(struct ixgbe_hw *hw)
5243 {
5244         uint32_t reg_val;
5245
5246         /* if Virtualization Technology is enabled */
5247         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5248         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5249                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5250                 return -1;
5251         }
5252
5253         return 0;
5254 }
5255
5256 static uint32_t
5257 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5258 {
5259         uint32_t vector = 0;
5260
5261         switch (hw->mac.mc_filter_type) {
5262         case 0:   /* use bits [47:36] of the address */
5263                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5264                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5265                 break;
5266         case 1:   /* use bits [46:35] of the address */
5267                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5268                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5269                 break;
5270         case 2:   /* use bits [45:34] of the address */
5271                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5272                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5273                 break;
5274         case 3:   /* use bits [43:32] of the address */
5275                 vector = ((uc_addr->addr_bytes[4]) |
5276                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5277                 break;
5278         default:  /* Invalid mc_filter_type */
5279                 break;
5280         }
5281
5282         /* vector can only be 12-bits or boundary will be exceeded */
5283         vector &= 0xFFF;
5284         return vector;
5285 }
5286
5287 static int
5288 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5289                         uint8_t on)
5290 {
5291         uint32_t vector;
5292         uint32_t uta_idx;
5293         uint32_t reg_val;
5294         uint32_t uta_shift;
5295         uint32_t rc;
5296         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5297         const uint32_t ixgbe_uta_bit_shift = 5;
5298         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5299         const uint32_t bit1 = 0x1;
5300
5301         struct ixgbe_hw *hw =
5302                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5303         struct ixgbe_uta_info *uta_info =
5304                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5305
5306         /* The UTA table only exists on 82599 hardware and newer */
5307         if (hw->mac.type < ixgbe_mac_82599EB)
5308                 return -ENOTSUP;
5309
5310         vector = ixgbe_uta_vector(hw, mac_addr);
5311         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5312         uta_shift = vector & ixgbe_uta_bit_mask;
5313
5314         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5315         if (rc == on)
5316                 return 0;
5317
5318         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5319         if (on) {
5320                 uta_info->uta_in_use++;
5321                 reg_val |= (bit1 << uta_shift);
5322                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5323         } else {
5324                 uta_info->uta_in_use--;
5325                 reg_val &= ~(bit1 << uta_shift);
5326                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5327         }
5328
5329         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5330
5331         if (uta_info->uta_in_use > 0)
5332                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5333                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5334         else
5335                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5336
5337         return 0;
5338 }
5339
5340 static int
5341 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5342 {
5343         int i;
5344         struct ixgbe_hw *hw =
5345                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5346         struct ixgbe_uta_info *uta_info =
5347                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5348
5349         /* The UTA table only exists on 82599 hardware and newer */
5350         if (hw->mac.type < ixgbe_mac_82599EB)
5351                 return -ENOTSUP;
5352
5353         if (on) {
5354                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5355                         uta_info->uta_shadow[i] = ~0;
5356                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5357                 }
5358         } else {
5359                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5360                         uta_info->uta_shadow[i] = 0;
5361                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5362                 }
5363         }
5364         return 0;
5365
5366 }
5367
5368 uint32_t
5369 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5370 {
5371         uint32_t new_val = orig_val;
5372
5373         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5374                 new_val |= IXGBE_VMOLR_AUPE;
5375         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5376                 new_val |= IXGBE_VMOLR_ROMPE;
5377         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5378                 new_val |= IXGBE_VMOLR_ROPE;
5379         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5380                 new_val |= IXGBE_VMOLR_BAM;
5381         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5382                 new_val |= IXGBE_VMOLR_MPE;
5383
5384         return new_val;
5385 }
5386
5387 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5388 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5389 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5390 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5391 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5392         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5393         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5394
5395 static int
5396 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5397                       struct rte_eth_mirror_conf *mirror_conf,
5398                       uint8_t rule_id, uint8_t on)
5399 {
5400         uint32_t mr_ctl, vlvf;
5401         uint32_t mp_lsb = 0;
5402         uint32_t mv_msb = 0;
5403         uint32_t mv_lsb = 0;
5404         uint32_t mp_msb = 0;
5405         uint8_t i = 0;
5406         int reg_index = 0;
5407         uint64_t vlan_mask = 0;
5408
5409         const uint8_t pool_mask_offset = 32;
5410         const uint8_t vlan_mask_offset = 32;
5411         const uint8_t dst_pool_offset = 8;
5412         const uint8_t rule_mr_offset  = 4;
5413         const uint8_t mirror_rule_mask = 0x0F;
5414
5415         struct ixgbe_mirror_info *mr_info =
5416                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5417         struct ixgbe_hw *hw =
5418                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5419         uint8_t mirror_type = 0;
5420
5421         if (ixgbe_vt_check(hw) < 0)
5422                 return -ENOTSUP;
5423
5424         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5425                 return -EINVAL;
5426
5427         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5428                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5429                             mirror_conf->rule_type);
5430                 return -EINVAL;
5431         }
5432
5433         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5434                 mirror_type |= IXGBE_MRCTL_VLME;
5435                 /* Check if vlan id is valid and find conresponding VLAN ID
5436                  * index in VLVF
5437                  */
5438                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5439                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5440                                 /* search vlan id related pool vlan filter
5441                                  * index
5442                                  */
5443                                 reg_index = ixgbe_find_vlvf_slot(
5444                                                 hw,
5445                                                 mirror_conf->vlan.vlan_id[i],
5446                                                 false);
5447                                 if (reg_index < 0)
5448                                         return -EINVAL;
5449                                 vlvf = IXGBE_READ_REG(hw,
5450                                                       IXGBE_VLVF(reg_index));
5451                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5452                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5453                                       mirror_conf->vlan.vlan_id[i]))
5454                                         vlan_mask |= (1ULL << reg_index);
5455                                 else
5456                                         return -EINVAL;
5457                         }
5458                 }
5459
5460                 if (on) {
5461                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5462                         mv_msb = vlan_mask >> vlan_mask_offset;
5463
5464                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5465                                                 mirror_conf->vlan.vlan_mask;
5466                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5467                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5468                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5469                                                 mirror_conf->vlan.vlan_id[i];
5470                         }
5471                 } else {
5472                         mv_lsb = 0;
5473                         mv_msb = 0;
5474                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5475                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5476                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5477                 }
5478         }
5479
5480         /**
5481          * if enable pool mirror, write related pool mask register,if disable
5482          * pool mirror, clear PFMRVM register
5483          */
5484         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5485                 mirror_type |= IXGBE_MRCTL_VPME;
5486                 if (on) {
5487                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5488                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5489                         mr_info->mr_conf[rule_id].pool_mask =
5490                                         mirror_conf->pool_mask;
5491
5492                 } else {
5493                         mp_lsb = 0;
5494                         mp_msb = 0;
5495                         mr_info->mr_conf[rule_id].pool_mask = 0;
5496                 }
5497         }
5498         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5499                 mirror_type |= IXGBE_MRCTL_UPME;
5500         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5501                 mirror_type |= IXGBE_MRCTL_DPME;
5502
5503         /* read  mirror control register and recalculate it */
5504         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5505
5506         if (on) {
5507                 mr_ctl |= mirror_type;
5508                 mr_ctl &= mirror_rule_mask;
5509                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5510         } else {
5511                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5512         }
5513
5514         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5515         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5516
5517         /* write mirrror control  register */
5518         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5519
5520         /* write pool mirrror control  register */
5521         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5522                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5523                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5524                                 mp_msb);
5525         }
5526         /* write VLAN mirrror control  register */
5527         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5528                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5529                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5530                                 mv_msb);
5531         }
5532
5533         return 0;
5534 }
5535
5536 static int
5537 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5538 {
5539         int mr_ctl = 0;
5540         uint32_t lsb_val = 0;
5541         uint32_t msb_val = 0;
5542         const uint8_t rule_mr_offset = 4;
5543
5544         struct ixgbe_hw *hw =
5545                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5546         struct ixgbe_mirror_info *mr_info =
5547                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5548
5549         if (ixgbe_vt_check(hw) < 0)
5550                 return -ENOTSUP;
5551
5552         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5553                 return -EINVAL;
5554
5555         memset(&mr_info->mr_conf[rule_id], 0,
5556                sizeof(struct rte_eth_mirror_conf));
5557
5558         /* clear PFVMCTL register */
5559         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5560
5561         /* clear pool mask register */
5562         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5563         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5564
5565         /* clear vlan mask register */
5566         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5567         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5568
5569         return 0;
5570 }
5571
5572 static int
5573 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5574 {
5575         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5576         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5577         struct ixgbe_interrupt *intr =
5578                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5579         struct ixgbe_hw *hw =
5580                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5581         uint32_t vec = IXGBE_MISC_VEC_ID;
5582
5583         if (rte_intr_allow_others(intr_handle))
5584                 vec = IXGBE_RX_VEC_START;
5585         intr->mask |= (1 << vec);
5586         RTE_SET_USED(queue_id);
5587         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5588
5589         rte_intr_enable(intr_handle);
5590
5591         return 0;
5592 }
5593
5594 static int
5595 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5596 {
5597         struct ixgbe_interrupt *intr =
5598                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5599         struct ixgbe_hw *hw =
5600                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5601         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5602         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5603         uint32_t vec = IXGBE_MISC_VEC_ID;
5604
5605         if (rte_intr_allow_others(intr_handle))
5606                 vec = IXGBE_RX_VEC_START;
5607         intr->mask &= ~(1 << vec);
5608         RTE_SET_USED(queue_id);
5609         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5610
5611         return 0;
5612 }
5613
5614 static int
5615 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5616 {
5617         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5618         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5619         uint32_t mask;
5620         struct ixgbe_hw *hw =
5621                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5622         struct ixgbe_interrupt *intr =
5623                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5624
5625         if (queue_id < 16) {
5626                 ixgbe_disable_intr(hw);
5627                 intr->mask |= (1 << queue_id);
5628                 ixgbe_enable_intr(dev);
5629         } else if (queue_id < 32) {
5630                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5631                 mask &= (1 << queue_id);
5632                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5633         } else if (queue_id < 64) {
5634                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5635                 mask &= (1 << (queue_id - 32));
5636                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5637         }
5638         rte_intr_enable(intr_handle);
5639
5640         return 0;
5641 }
5642
5643 static int
5644 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5645 {
5646         uint32_t mask;
5647         struct ixgbe_hw *hw =
5648                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5649         struct ixgbe_interrupt *intr =
5650                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5651
5652         if (queue_id < 16) {
5653                 ixgbe_disable_intr(hw);
5654                 intr->mask &= ~(1 << queue_id);
5655                 ixgbe_enable_intr(dev);
5656         } else if (queue_id < 32) {
5657                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5658                 mask &= ~(1 << queue_id);
5659                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5660         } else if (queue_id < 64) {
5661                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5662                 mask &= ~(1 << (queue_id - 32));
5663                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5664         }
5665
5666         return 0;
5667 }
5668
5669 static void
5670 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5671                      uint8_t queue, uint8_t msix_vector)
5672 {
5673         uint32_t tmp, idx;
5674
5675         if (direction == -1) {
5676                 /* other causes */
5677                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5678                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5679                 tmp &= ~0xFF;
5680                 tmp |= msix_vector;
5681                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5682         } else {
5683                 /* rx or tx cause */
5684                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5685                 idx = ((16 * (queue & 1)) + (8 * direction));
5686                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5687                 tmp &= ~(0xFF << idx);
5688                 tmp |= (msix_vector << idx);
5689                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5690         }
5691 }
5692
5693 /**
5694  * set the IVAR registers, mapping interrupt causes to vectors
5695  * @param hw
5696  *  pointer to ixgbe_hw struct
5697  * @direction
5698  *  0 for Rx, 1 for Tx, -1 for other causes
5699  * @queue
5700  *  queue to map the corresponding interrupt to
5701  * @msix_vector
5702  *  the vector to map to the corresponding queue
5703  */
5704 static void
5705 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5706                    uint8_t queue, uint8_t msix_vector)
5707 {
5708         uint32_t tmp, idx;
5709
5710         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5711         if (hw->mac.type == ixgbe_mac_82598EB) {
5712                 if (direction == -1)
5713                         direction = 0;
5714                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5715                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5716                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5717                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5718                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5719         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5720                         (hw->mac.type == ixgbe_mac_X540) ||
5721                         (hw->mac.type == ixgbe_mac_X550)) {
5722                 if (direction == -1) {
5723                         /* other causes */
5724                         idx = ((queue & 1) * 8);
5725                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5726                         tmp &= ~(0xFF << idx);
5727                         tmp |= (msix_vector << idx);
5728                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5729                 } else {
5730                         /* rx or tx causes */
5731                         idx = ((16 * (queue & 1)) + (8 * direction));
5732                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5733                         tmp &= ~(0xFF << idx);
5734                         tmp |= (msix_vector << idx);
5735                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5736                 }
5737         }
5738 }
5739
5740 static void
5741 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5742 {
5743         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5744         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5745         struct ixgbe_hw *hw =
5746                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5747         uint32_t q_idx;
5748         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5749         uint32_t base = IXGBE_MISC_VEC_ID;
5750
5751         /* Configure VF other cause ivar */
5752         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5753
5754         /* won't configure msix register if no mapping is done
5755          * between intr vector and event fd.
5756          */
5757         if (!rte_intr_dp_is_en(intr_handle))
5758                 return;
5759
5760         if (rte_intr_allow_others(intr_handle)) {
5761                 base = IXGBE_RX_VEC_START;
5762                 vector_idx = IXGBE_RX_VEC_START;
5763         }
5764
5765         /* Configure all RX queues of VF */
5766         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5767                 /* Force all queue use vector 0,
5768                  * as IXGBE_VF_MAXMSIVECOTR = 1
5769                  */
5770                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5771                 intr_handle->intr_vec[q_idx] = vector_idx;
5772                 if (vector_idx < base + intr_handle->nb_efd - 1)
5773                         vector_idx++;
5774         }
5775
5776         /* As RX queue setting above show, all queues use the vector 0.
5777          * Set only the ITR value of IXGBE_MISC_VEC_ID.
5778          */
5779         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5780                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5781                         | IXGBE_EITR_CNT_WDIS);
5782 }
5783
5784 /**
5785  * Sets up the hardware to properly generate MSI-X interrupts
5786  * @hw
5787  *  board private structure
5788  */
5789 static void
5790 ixgbe_configure_msix(struct rte_eth_dev *dev)
5791 {
5792         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5793         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5794         struct ixgbe_hw *hw =
5795                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5796         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5797         uint32_t vec = IXGBE_MISC_VEC_ID;
5798         uint32_t mask;
5799         uint32_t gpie;
5800
5801         /* won't configure msix register if no mapping is done
5802          * between intr vector and event fd
5803          */
5804         if (!rte_intr_dp_is_en(intr_handle))
5805                 return;
5806
5807         if (rte_intr_allow_others(intr_handle))
5808                 vec = base = IXGBE_RX_VEC_START;
5809
5810         /* setup GPIE for MSI-x mode */
5811         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5812         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5813                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5814         /* auto clearing and auto setting corresponding bits in EIMS
5815          * when MSI-X interrupt is triggered
5816          */
5817         if (hw->mac.type == ixgbe_mac_82598EB) {
5818                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5819         } else {
5820                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5821                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5822         }
5823         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5824
5825         /* Populate the IVAR table and set the ITR values to the
5826          * corresponding register.
5827          */
5828         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5829              queue_id++) {
5830                 /* by default, 1:1 mapping */
5831                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5832                 intr_handle->intr_vec[queue_id] = vec;
5833                 if (vec < base + intr_handle->nb_efd - 1)
5834                         vec++;
5835         }
5836
5837         switch (hw->mac.type) {
5838         case ixgbe_mac_82598EB:
5839                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5840                                    IXGBE_MISC_VEC_ID);
5841                 break;
5842         case ixgbe_mac_82599EB:
5843         case ixgbe_mac_X540:
5844         case ixgbe_mac_X550:
5845                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5846                 break;
5847         default:
5848                 break;
5849         }
5850         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5851                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5852                         | IXGBE_EITR_CNT_WDIS);
5853
5854         /* set up to autoclear timer, and the vectors */
5855         mask = IXGBE_EIMS_ENABLE_MASK;
5856         mask &= ~(IXGBE_EIMS_OTHER |
5857                   IXGBE_EIMS_MAILBOX |
5858                   IXGBE_EIMS_LSC);
5859
5860         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5861 }
5862
5863 int
5864 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5865                            uint16_t queue_idx, uint16_t tx_rate)
5866 {
5867         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5868         struct rte_eth_rxmode *rxmode;
5869         uint32_t rf_dec, rf_int;
5870         uint32_t bcnrc_val;
5871         uint16_t link_speed = dev->data->dev_link.link_speed;
5872
5873         if (queue_idx >= hw->mac.max_tx_queues)
5874                 return -EINVAL;
5875
5876         if (tx_rate != 0) {
5877                 /* Calculate the rate factor values to set */
5878                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5879                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5880                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5881
5882                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5883                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5884                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5885                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5886         } else {
5887                 bcnrc_val = 0;
5888         }
5889
5890         rxmode = &dev->data->dev_conf.rxmode;
5891         /*
5892          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5893          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5894          * set as 0x4.
5895          */
5896         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
5897             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
5898                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5899                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5900         else
5901                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5902                         IXGBE_MMW_SIZE_DEFAULT);
5903
5904         /* Set RTTBCNRC of queue X */
5905         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5906         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5907         IXGBE_WRITE_FLUSH(hw);
5908
5909         return 0;
5910 }
5911
5912 static int
5913 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5914                      __attribute__((unused)) uint32_t index,
5915                      __attribute__((unused)) uint32_t pool)
5916 {
5917         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5918         int diag;
5919
5920         /*
5921          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5922          * operation. Trap this case to avoid exhausting the [very limited]
5923          * set of PF resources used to store VF MAC addresses.
5924          */
5925         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5926                 return -1;
5927         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5928         if (diag != 0)
5929                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5930                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5931                             mac_addr->addr_bytes[0],
5932                             mac_addr->addr_bytes[1],
5933                             mac_addr->addr_bytes[2],
5934                             mac_addr->addr_bytes[3],
5935                             mac_addr->addr_bytes[4],
5936                             mac_addr->addr_bytes[5],
5937                             diag);
5938         return diag;
5939 }
5940
5941 static void
5942 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5943 {
5944         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5945         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5946         struct ether_addr *mac_addr;
5947         uint32_t i;
5948         int diag;
5949
5950         /*
5951          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5952          * not support the deletion of a given MAC address.
5953          * Instead, it imposes to delete all MAC addresses, then to add again
5954          * all MAC addresses with the exception of the one to be deleted.
5955          */
5956         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5957
5958         /*
5959          * Add again all MAC addresses, with the exception of the deleted one
5960          * and of the permanent MAC address.
5961          */
5962         for (i = 0, mac_addr = dev->data->mac_addrs;
5963              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5964                 /* Skip the deleted MAC address */
5965                 if (i == index)
5966                         continue;
5967                 /* Skip NULL MAC addresses */
5968                 if (is_zero_ether_addr(mac_addr))
5969                         continue;
5970                 /* Skip the permanent MAC address */
5971                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5972                         continue;
5973                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5974                 if (diag != 0)
5975                         PMD_DRV_LOG(ERR,
5976                                     "Adding again MAC address "
5977                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5978                                     "diag=%d",
5979                                     mac_addr->addr_bytes[0],
5980                                     mac_addr->addr_bytes[1],
5981                                     mac_addr->addr_bytes[2],
5982                                     mac_addr->addr_bytes[3],
5983                                     mac_addr->addr_bytes[4],
5984                                     mac_addr->addr_bytes[5],
5985                                     diag);
5986         }
5987 }
5988
5989 static int
5990 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5991 {
5992         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5993
5994         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5995
5996         return 0;
5997 }
5998
5999 int
6000 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6001                         struct rte_eth_syn_filter *filter,
6002                         bool add)
6003 {
6004         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6005         struct ixgbe_filter_info *filter_info =
6006                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6007         uint32_t syn_info;
6008         uint32_t synqf;
6009
6010         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6011                 return -EINVAL;
6012
6013         syn_info = filter_info->syn_info;
6014
6015         if (add) {
6016                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6017                         return -EINVAL;
6018                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6019                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6020
6021                 if (filter->hig_pri)
6022                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6023                 else
6024                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6025         } else {
6026                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6027                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6028                         return -ENOENT;
6029                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6030         }
6031
6032         filter_info->syn_info = synqf;
6033         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6034         IXGBE_WRITE_FLUSH(hw);
6035         return 0;
6036 }
6037
6038 static int
6039 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6040                         struct rte_eth_syn_filter *filter)
6041 {
6042         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6043         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6044
6045         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6046                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6047                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6048                 return 0;
6049         }
6050         return -ENOENT;
6051 }
6052
6053 static int
6054 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6055                         enum rte_filter_op filter_op,
6056                         void *arg)
6057 {
6058         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6059         int ret;
6060
6061         MAC_TYPE_FILTER_SUP(hw->mac.type);
6062
6063         if (filter_op == RTE_ETH_FILTER_NOP)
6064                 return 0;
6065
6066         if (arg == NULL) {
6067                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6068                             filter_op);
6069                 return -EINVAL;
6070         }
6071
6072         switch (filter_op) {
6073         case RTE_ETH_FILTER_ADD:
6074                 ret = ixgbe_syn_filter_set(dev,
6075                                 (struct rte_eth_syn_filter *)arg,
6076                                 TRUE);
6077                 break;
6078         case RTE_ETH_FILTER_DELETE:
6079                 ret = ixgbe_syn_filter_set(dev,
6080                                 (struct rte_eth_syn_filter *)arg,
6081                                 FALSE);
6082                 break;
6083         case RTE_ETH_FILTER_GET:
6084                 ret = ixgbe_syn_filter_get(dev,
6085                                 (struct rte_eth_syn_filter *)arg);
6086                 break;
6087         default:
6088                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6089                 ret = -EINVAL;
6090                 break;
6091         }
6092
6093         return ret;
6094 }
6095
6096
6097 static inline enum ixgbe_5tuple_protocol
6098 convert_protocol_type(uint8_t protocol_value)
6099 {
6100         if (protocol_value == IPPROTO_TCP)
6101                 return IXGBE_FILTER_PROTOCOL_TCP;
6102         else if (protocol_value == IPPROTO_UDP)
6103                 return IXGBE_FILTER_PROTOCOL_UDP;
6104         else if (protocol_value == IPPROTO_SCTP)
6105                 return IXGBE_FILTER_PROTOCOL_SCTP;
6106         else
6107                 return IXGBE_FILTER_PROTOCOL_NONE;
6108 }
6109
6110 /* inject a 5-tuple filter to HW */
6111 static inline void
6112 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6113                            struct ixgbe_5tuple_filter *filter)
6114 {
6115         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6116         int i;
6117         uint32_t ftqf, sdpqf;
6118         uint32_t l34timir = 0;
6119         uint8_t mask = 0xff;
6120
6121         i = filter->index;
6122
6123         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6124                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6125         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6126
6127         ftqf = (uint32_t)(filter->filter_info.proto &
6128                 IXGBE_FTQF_PROTOCOL_MASK);
6129         ftqf |= (uint32_t)((filter->filter_info.priority &
6130                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6131         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6132                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6133         if (filter->filter_info.dst_ip_mask == 0)
6134                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6135         if (filter->filter_info.src_port_mask == 0)
6136                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6137         if (filter->filter_info.dst_port_mask == 0)
6138                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6139         if (filter->filter_info.proto_mask == 0)
6140                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6141         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6142         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6143         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6144
6145         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6146         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6147         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6148         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6149
6150         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6151         l34timir |= (uint32_t)(filter->queue <<
6152                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6153         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6154 }
6155
6156 /*
6157  * add a 5tuple filter
6158  *
6159  * @param
6160  * dev: Pointer to struct rte_eth_dev.
6161  * index: the index the filter allocates.
6162  * filter: ponter to the filter that will be added.
6163  * rx_queue: the queue id the filter assigned to.
6164  *
6165  * @return
6166  *    - On success, zero.
6167  *    - On failure, a negative value.
6168  */
6169 static int
6170 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6171                         struct ixgbe_5tuple_filter *filter)
6172 {
6173         struct ixgbe_filter_info *filter_info =
6174                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6175         int i, idx, shift;
6176
6177         /*
6178          * look for an unused 5tuple filter index,
6179          * and insert the filter to list.
6180          */
6181         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6182                 idx = i / (sizeof(uint32_t) * NBBY);
6183                 shift = i % (sizeof(uint32_t) * NBBY);
6184                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6185                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6186                         filter->index = i;
6187                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6188                                           filter,
6189                                           entries);
6190                         break;
6191                 }
6192         }
6193         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6194                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6195                 return -ENOSYS;
6196         }
6197
6198         ixgbe_inject_5tuple_filter(dev, filter);
6199
6200         return 0;
6201 }
6202
6203 /*
6204  * remove a 5tuple filter
6205  *
6206  * @param
6207  * dev: Pointer to struct rte_eth_dev.
6208  * filter: the pointer of the filter will be removed.
6209  */
6210 static void
6211 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6212                         struct ixgbe_5tuple_filter *filter)
6213 {
6214         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6215         struct ixgbe_filter_info *filter_info =
6216                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6217         uint16_t index = filter->index;
6218
6219         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6220                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6221         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6222         rte_free(filter);
6223
6224         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6225         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6226         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6227         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6228         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6229 }
6230
6231 static int
6232 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6233 {
6234         struct ixgbe_hw *hw;
6235         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6236         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6237
6238         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6239
6240         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6241                 return -EINVAL;
6242
6243         /* refuse mtu that requires the support of scattered packets when this
6244          * feature has not been enabled before.
6245          */
6246         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6247             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6248              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6249                 return -EINVAL;
6250
6251         /*
6252          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6253          * request of the version 2.0 of the mailbox API.
6254          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6255          * of the mailbox API.
6256          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6257          * prior to 3.11.33 which contains the following change:
6258          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6259          */
6260         ixgbevf_rlpml_set_vf(hw, max_frame);
6261
6262         /* update max frame size */
6263         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6264         return 0;
6265 }
6266
6267 static inline struct ixgbe_5tuple_filter *
6268 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6269                         struct ixgbe_5tuple_filter_info *key)
6270 {
6271         struct ixgbe_5tuple_filter *it;
6272
6273         TAILQ_FOREACH(it, filter_list, entries) {
6274                 if (memcmp(key, &it->filter_info,
6275                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6276                         return it;
6277                 }
6278         }
6279         return NULL;
6280 }
6281
6282 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6283 static inline int
6284 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6285                         struct ixgbe_5tuple_filter_info *filter_info)
6286 {
6287         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6288                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6289                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6290                 return -EINVAL;
6291
6292         switch (filter->dst_ip_mask) {
6293         case UINT32_MAX:
6294                 filter_info->dst_ip_mask = 0;
6295                 filter_info->dst_ip = filter->dst_ip;
6296                 break;
6297         case 0:
6298                 filter_info->dst_ip_mask = 1;
6299                 break;
6300         default:
6301                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6302                 return -EINVAL;
6303         }
6304
6305         switch (filter->src_ip_mask) {
6306         case UINT32_MAX:
6307                 filter_info->src_ip_mask = 0;
6308                 filter_info->src_ip = filter->src_ip;
6309                 break;
6310         case 0:
6311                 filter_info->src_ip_mask = 1;
6312                 break;
6313         default:
6314                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6315                 return -EINVAL;
6316         }
6317
6318         switch (filter->dst_port_mask) {
6319         case UINT16_MAX:
6320                 filter_info->dst_port_mask = 0;
6321                 filter_info->dst_port = filter->dst_port;
6322                 break;
6323         case 0:
6324                 filter_info->dst_port_mask = 1;
6325                 break;
6326         default:
6327                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6328                 return -EINVAL;
6329         }
6330
6331         switch (filter->src_port_mask) {
6332         case UINT16_MAX:
6333                 filter_info->src_port_mask = 0;
6334                 filter_info->src_port = filter->src_port;
6335                 break;
6336         case 0:
6337                 filter_info->src_port_mask = 1;
6338                 break;
6339         default:
6340                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6341                 return -EINVAL;
6342         }
6343
6344         switch (filter->proto_mask) {
6345         case UINT8_MAX:
6346                 filter_info->proto_mask = 0;
6347                 filter_info->proto =
6348                         convert_protocol_type(filter->proto);
6349                 break;
6350         case 0:
6351                 filter_info->proto_mask = 1;
6352                 break;
6353         default:
6354                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6355                 return -EINVAL;
6356         }
6357
6358         filter_info->priority = (uint8_t)filter->priority;
6359         return 0;
6360 }
6361
6362 /*
6363  * add or delete a ntuple filter
6364  *
6365  * @param
6366  * dev: Pointer to struct rte_eth_dev.
6367  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6368  * add: if true, add filter, if false, remove filter
6369  *
6370  * @return
6371  *    - On success, zero.
6372  *    - On failure, a negative value.
6373  */
6374 int
6375 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6376                         struct rte_eth_ntuple_filter *ntuple_filter,
6377                         bool add)
6378 {
6379         struct ixgbe_filter_info *filter_info =
6380                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6381         struct ixgbe_5tuple_filter_info filter_5tuple;
6382         struct ixgbe_5tuple_filter *filter;
6383         int ret;
6384
6385         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6386                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6387                 return -EINVAL;
6388         }
6389
6390         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6391         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6392         if (ret < 0)
6393                 return ret;
6394
6395         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6396                                          &filter_5tuple);
6397         if (filter != NULL && add) {
6398                 PMD_DRV_LOG(ERR, "filter exists.");
6399                 return -EEXIST;
6400         }
6401         if (filter == NULL && !add) {
6402                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6403                 return -ENOENT;
6404         }
6405
6406         if (add) {
6407                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6408                                 sizeof(struct ixgbe_5tuple_filter), 0);
6409                 if (filter == NULL)
6410                         return -ENOMEM;
6411                 rte_memcpy(&filter->filter_info,
6412                                  &filter_5tuple,
6413                                  sizeof(struct ixgbe_5tuple_filter_info));
6414                 filter->queue = ntuple_filter->queue;
6415                 ret = ixgbe_add_5tuple_filter(dev, filter);
6416                 if (ret < 0) {
6417                         rte_free(filter);
6418                         return ret;
6419                 }
6420         } else
6421                 ixgbe_remove_5tuple_filter(dev, filter);
6422
6423         return 0;
6424 }
6425
6426 /*
6427  * get a ntuple filter
6428  *
6429  * @param
6430  * dev: Pointer to struct rte_eth_dev.
6431  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6432  *
6433  * @return
6434  *    - On success, zero.
6435  *    - On failure, a negative value.
6436  */
6437 static int
6438 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6439                         struct rte_eth_ntuple_filter *ntuple_filter)
6440 {
6441         struct ixgbe_filter_info *filter_info =
6442                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6443         struct ixgbe_5tuple_filter_info filter_5tuple;
6444         struct ixgbe_5tuple_filter *filter;
6445         int ret;
6446
6447         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6448                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6449                 return -EINVAL;
6450         }
6451
6452         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6453         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6454         if (ret < 0)
6455                 return ret;
6456
6457         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6458                                          &filter_5tuple);
6459         if (filter == NULL) {
6460                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6461                 return -ENOENT;
6462         }
6463         ntuple_filter->queue = filter->queue;
6464         return 0;
6465 }
6466
6467 /*
6468  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6469  * @dev: pointer to rte_eth_dev structure
6470  * @filter_op:operation will be taken.
6471  * @arg: a pointer to specific structure corresponding to the filter_op
6472  *
6473  * @return
6474  *    - On success, zero.
6475  *    - On failure, a negative value.
6476  */
6477 static int
6478 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6479                                 enum rte_filter_op filter_op,
6480                                 void *arg)
6481 {
6482         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6483         int ret;
6484
6485         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6486
6487         if (filter_op == RTE_ETH_FILTER_NOP)
6488                 return 0;
6489
6490         if (arg == NULL) {
6491                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6492                             filter_op);
6493                 return -EINVAL;
6494         }
6495
6496         switch (filter_op) {
6497         case RTE_ETH_FILTER_ADD:
6498                 ret = ixgbe_add_del_ntuple_filter(dev,
6499                         (struct rte_eth_ntuple_filter *)arg,
6500                         TRUE);
6501                 break;
6502         case RTE_ETH_FILTER_DELETE:
6503                 ret = ixgbe_add_del_ntuple_filter(dev,
6504                         (struct rte_eth_ntuple_filter *)arg,
6505                         FALSE);
6506                 break;
6507         case RTE_ETH_FILTER_GET:
6508                 ret = ixgbe_get_ntuple_filter(dev,
6509                         (struct rte_eth_ntuple_filter *)arg);
6510                 break;
6511         default:
6512                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6513                 ret = -EINVAL;
6514                 break;
6515         }
6516         return ret;
6517 }
6518
6519 int
6520 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6521                         struct rte_eth_ethertype_filter *filter,
6522                         bool add)
6523 {
6524         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6525         struct ixgbe_filter_info *filter_info =
6526                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6527         uint32_t etqf = 0;
6528         uint32_t etqs = 0;
6529         int ret;
6530         struct ixgbe_ethertype_filter ethertype_filter;
6531
6532         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6533                 return -EINVAL;
6534
6535         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6536                 filter->ether_type == ETHER_TYPE_IPv6) {
6537                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6538                         " ethertype filter.", filter->ether_type);
6539                 return -EINVAL;
6540         }
6541
6542         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6543                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6544                 return -EINVAL;
6545         }
6546         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6547                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6548                 return -EINVAL;
6549         }
6550
6551         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6552         if (ret >= 0 && add) {
6553                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6554                             filter->ether_type);
6555                 return -EEXIST;
6556         }
6557         if (ret < 0 && !add) {
6558                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6559                             filter->ether_type);
6560                 return -ENOENT;
6561         }
6562
6563         if (add) {
6564                 etqf = IXGBE_ETQF_FILTER_EN;
6565                 etqf |= (uint32_t)filter->ether_type;
6566                 etqs |= (uint32_t)((filter->queue <<
6567                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6568                                     IXGBE_ETQS_RX_QUEUE);
6569                 etqs |= IXGBE_ETQS_QUEUE_EN;
6570
6571                 ethertype_filter.ethertype = filter->ether_type;
6572                 ethertype_filter.etqf = etqf;
6573                 ethertype_filter.etqs = etqs;
6574                 ethertype_filter.conf = FALSE;
6575                 ret = ixgbe_ethertype_filter_insert(filter_info,
6576                                                     &ethertype_filter);
6577                 if (ret < 0) {
6578                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6579                         return -ENOSPC;
6580                 }
6581         } else {
6582                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6583                 if (ret < 0)
6584                         return -ENOSYS;
6585         }
6586         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6587         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6588         IXGBE_WRITE_FLUSH(hw);
6589
6590         return 0;
6591 }
6592
6593 static int
6594 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6595                         struct rte_eth_ethertype_filter *filter)
6596 {
6597         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6598         struct ixgbe_filter_info *filter_info =
6599                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6600         uint32_t etqf, etqs;
6601         int ret;
6602
6603         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6604         if (ret < 0) {
6605                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6606                             filter->ether_type);
6607                 return -ENOENT;
6608         }
6609
6610         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6611         if (etqf & IXGBE_ETQF_FILTER_EN) {
6612                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6613                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6614                 filter->flags = 0;
6615                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6616                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6617                 return 0;
6618         }
6619         return -ENOENT;
6620 }
6621
6622 /*
6623  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6624  * @dev: pointer to rte_eth_dev structure
6625  * @filter_op:operation will be taken.
6626  * @arg: a pointer to specific structure corresponding to the filter_op
6627  */
6628 static int
6629 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6630                                 enum rte_filter_op filter_op,
6631                                 void *arg)
6632 {
6633         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6634         int ret;
6635
6636         MAC_TYPE_FILTER_SUP(hw->mac.type);
6637
6638         if (filter_op == RTE_ETH_FILTER_NOP)
6639                 return 0;
6640
6641         if (arg == NULL) {
6642                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6643                             filter_op);
6644                 return -EINVAL;
6645         }
6646
6647         switch (filter_op) {
6648         case RTE_ETH_FILTER_ADD:
6649                 ret = ixgbe_add_del_ethertype_filter(dev,
6650                         (struct rte_eth_ethertype_filter *)arg,
6651                         TRUE);
6652                 break;
6653         case RTE_ETH_FILTER_DELETE:
6654                 ret = ixgbe_add_del_ethertype_filter(dev,
6655                         (struct rte_eth_ethertype_filter *)arg,
6656                         FALSE);
6657                 break;
6658         case RTE_ETH_FILTER_GET:
6659                 ret = ixgbe_get_ethertype_filter(dev,
6660                         (struct rte_eth_ethertype_filter *)arg);
6661                 break;
6662         default:
6663                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6664                 ret = -EINVAL;
6665                 break;
6666         }
6667         return ret;
6668 }
6669
6670 static int
6671 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6672                      enum rte_filter_type filter_type,
6673                      enum rte_filter_op filter_op,
6674                      void *arg)
6675 {
6676         int ret = 0;
6677
6678         switch (filter_type) {
6679         case RTE_ETH_FILTER_NTUPLE:
6680                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6681                 break;
6682         case RTE_ETH_FILTER_ETHERTYPE:
6683                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6684                 break;
6685         case RTE_ETH_FILTER_SYN:
6686                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6687                 break;
6688         case RTE_ETH_FILTER_FDIR:
6689                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6690                 break;
6691         case RTE_ETH_FILTER_L2_TUNNEL:
6692                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6693                 break;
6694         case RTE_ETH_FILTER_GENERIC:
6695                 if (filter_op != RTE_ETH_FILTER_GET)
6696                         return -EINVAL;
6697                 *(const void **)arg = &ixgbe_flow_ops;
6698                 break;
6699         default:
6700                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6701                                                         filter_type);
6702                 ret = -EINVAL;
6703                 break;
6704         }
6705
6706         return ret;
6707 }
6708
6709 static u8 *
6710 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6711                         u8 **mc_addr_ptr, u32 *vmdq)
6712 {
6713         u8 *mc_addr;
6714
6715         *vmdq = 0;
6716         mc_addr = *mc_addr_ptr;
6717         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6718         return mc_addr;
6719 }
6720
6721 static int
6722 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6723                           struct ether_addr *mc_addr_set,
6724                           uint32_t nb_mc_addr)
6725 {
6726         struct ixgbe_hw *hw;
6727         u8 *mc_addr_list;
6728
6729         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6730         mc_addr_list = (u8 *)mc_addr_set;
6731         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6732                                          ixgbe_dev_addr_list_itr, TRUE);
6733 }
6734
6735 static uint64_t
6736 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6737 {
6738         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6739         uint64_t systime_cycles;
6740
6741         switch (hw->mac.type) {
6742         case ixgbe_mac_X550:
6743         case ixgbe_mac_X550EM_x:
6744         case ixgbe_mac_X550EM_a:
6745                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6746                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6747                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6748                                 * NSEC_PER_SEC;
6749                 break;
6750         default:
6751                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6752                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6753                                 << 32;
6754         }
6755
6756         return systime_cycles;
6757 }
6758
6759 static uint64_t
6760 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6761 {
6762         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6763         uint64_t rx_tstamp_cycles;
6764
6765         switch (hw->mac.type) {
6766         case ixgbe_mac_X550:
6767         case ixgbe_mac_X550EM_x:
6768         case ixgbe_mac_X550EM_a:
6769                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6770                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6771                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6772                                 * NSEC_PER_SEC;
6773                 break;
6774         default:
6775                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6776                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6777                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6778                                 << 32;
6779         }
6780
6781         return rx_tstamp_cycles;
6782 }
6783
6784 static uint64_t
6785 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6786 {
6787         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6788         uint64_t tx_tstamp_cycles;
6789
6790         switch (hw->mac.type) {
6791         case ixgbe_mac_X550:
6792         case ixgbe_mac_X550EM_x:
6793         case ixgbe_mac_X550EM_a:
6794                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6795                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6796                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6797                                 * NSEC_PER_SEC;
6798                 break;
6799         default:
6800                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6801                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6802                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6803                                 << 32;
6804         }
6805
6806         return tx_tstamp_cycles;
6807 }
6808
6809 static void
6810 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6811 {
6812         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6813         struct ixgbe_adapter *adapter =
6814                 (struct ixgbe_adapter *)dev->data->dev_private;
6815         struct rte_eth_link link;
6816         uint32_t incval = 0;
6817         uint32_t shift = 0;
6818
6819         /* Get current link speed. */
6820         ixgbe_dev_link_update(dev, 1);
6821         rte_eth_linkstatus_get(dev, &link);
6822
6823         switch (link.link_speed) {
6824         case ETH_SPEED_NUM_100M:
6825                 incval = IXGBE_INCVAL_100;
6826                 shift = IXGBE_INCVAL_SHIFT_100;
6827                 break;
6828         case ETH_SPEED_NUM_1G:
6829                 incval = IXGBE_INCVAL_1GB;
6830                 shift = IXGBE_INCVAL_SHIFT_1GB;
6831                 break;
6832         case ETH_SPEED_NUM_10G:
6833         default:
6834                 incval = IXGBE_INCVAL_10GB;
6835                 shift = IXGBE_INCVAL_SHIFT_10GB;
6836                 break;
6837         }
6838
6839         switch (hw->mac.type) {
6840         case ixgbe_mac_X550:
6841         case ixgbe_mac_X550EM_x:
6842         case ixgbe_mac_X550EM_a:
6843                 /* Independent of link speed. */
6844                 incval = 1;
6845                 /* Cycles read will be interpreted as ns. */
6846                 shift = 0;
6847                 /* Fall-through */
6848         case ixgbe_mac_X540:
6849                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6850                 break;
6851         case ixgbe_mac_82599EB:
6852                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6853                 shift -= IXGBE_INCVAL_SHIFT_82599;
6854                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6855                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6856                 break;
6857         default:
6858                 /* Not supported. */
6859                 return;
6860         }
6861
6862         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6863         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6864         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6865
6866         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6867         adapter->systime_tc.cc_shift = shift;
6868         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6869
6870         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6871         adapter->rx_tstamp_tc.cc_shift = shift;
6872         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6873
6874         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6875         adapter->tx_tstamp_tc.cc_shift = shift;
6876         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6877 }
6878
6879 static int
6880 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6881 {
6882         struct ixgbe_adapter *adapter =
6883                         (struct ixgbe_adapter *)dev->data->dev_private;
6884
6885         adapter->systime_tc.nsec += delta;
6886         adapter->rx_tstamp_tc.nsec += delta;
6887         adapter->tx_tstamp_tc.nsec += delta;
6888
6889         return 0;
6890 }
6891
6892 static int
6893 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6894 {
6895         uint64_t ns;
6896         struct ixgbe_adapter *adapter =
6897                         (struct ixgbe_adapter *)dev->data->dev_private;
6898
6899         ns = rte_timespec_to_ns(ts);
6900         /* Set the timecounters to a new value. */
6901         adapter->systime_tc.nsec = ns;
6902         adapter->rx_tstamp_tc.nsec = ns;
6903         adapter->tx_tstamp_tc.nsec = ns;
6904
6905         return 0;
6906 }
6907
6908 static int
6909 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6910 {
6911         uint64_t ns, systime_cycles;
6912         struct ixgbe_adapter *adapter =
6913                         (struct ixgbe_adapter *)dev->data->dev_private;
6914
6915         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6916         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6917         *ts = rte_ns_to_timespec(ns);
6918
6919         return 0;
6920 }
6921
6922 static int
6923 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6924 {
6925         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6926         uint32_t tsync_ctl;
6927         uint32_t tsauxc;
6928
6929         /* Stop the timesync system time. */
6930         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6931         /* Reset the timesync system time value. */
6932         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6933         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6934
6935         /* Enable system time for platforms where it isn't on by default. */
6936         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6937         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6938         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6939
6940         ixgbe_start_timecounters(dev);
6941
6942         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6943         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6944                         (ETHER_TYPE_1588 |
6945                          IXGBE_ETQF_FILTER_EN |
6946                          IXGBE_ETQF_1588));
6947
6948         /* Enable timestamping of received PTP packets. */
6949         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6950         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6951         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6952
6953         /* Enable timestamping of transmitted PTP packets. */
6954         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6955         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6956         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6957
6958         IXGBE_WRITE_FLUSH(hw);
6959
6960         return 0;
6961 }
6962
6963 static int
6964 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6965 {
6966         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6967         uint32_t tsync_ctl;
6968
6969         /* Disable timestamping of transmitted PTP packets. */
6970         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6971         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6972         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6973
6974         /* Disable timestamping of received PTP packets. */
6975         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6976         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6977         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6978
6979         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6980         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6981
6982         /* Stop incrementating the System Time registers. */
6983         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6984
6985         return 0;
6986 }
6987
6988 static int
6989 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6990                                  struct timespec *timestamp,
6991                                  uint32_t flags __rte_unused)
6992 {
6993         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6994         struct ixgbe_adapter *adapter =
6995                 (struct ixgbe_adapter *)dev->data->dev_private;
6996         uint32_t tsync_rxctl;
6997         uint64_t rx_tstamp_cycles;
6998         uint64_t ns;
6999
7000         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7001         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7002                 return -EINVAL;
7003
7004         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7005         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7006         *timestamp = rte_ns_to_timespec(ns);
7007
7008         return  0;
7009 }
7010
7011 static int
7012 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7013                                  struct timespec *timestamp)
7014 {
7015         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7016         struct ixgbe_adapter *adapter =
7017                 (struct ixgbe_adapter *)dev->data->dev_private;
7018         uint32_t tsync_txctl;
7019         uint64_t tx_tstamp_cycles;
7020         uint64_t ns;
7021
7022         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7023         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7024                 return -EINVAL;
7025
7026         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7027         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7028         *timestamp = rte_ns_to_timespec(ns);
7029
7030         return 0;
7031 }
7032
7033 static int
7034 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7035 {
7036         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7037         int count = 0;
7038         int g_ind = 0;
7039         const struct reg_info *reg_group;
7040         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7041                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7042
7043         while ((reg_group = reg_set[g_ind++]))
7044                 count += ixgbe_regs_group_count(reg_group);
7045
7046         return count;
7047 }
7048
7049 static int
7050 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7051 {
7052         int count = 0;
7053         int g_ind = 0;
7054         const struct reg_info *reg_group;
7055
7056         while ((reg_group = ixgbevf_regs[g_ind++]))
7057                 count += ixgbe_regs_group_count(reg_group);
7058
7059         return count;
7060 }
7061
7062 static int
7063 ixgbe_get_regs(struct rte_eth_dev *dev,
7064               struct rte_dev_reg_info *regs)
7065 {
7066         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7067         uint32_t *data = regs->data;
7068         int g_ind = 0;
7069         int count = 0;
7070         const struct reg_info *reg_group;
7071         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7072                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7073
7074         if (data == NULL) {
7075                 regs->length = ixgbe_get_reg_length(dev);
7076                 regs->width = sizeof(uint32_t);
7077                 return 0;
7078         }
7079
7080         /* Support only full register dump */
7081         if ((regs->length == 0) ||
7082             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7083                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7084                         hw->device_id;
7085                 while ((reg_group = reg_set[g_ind++]))
7086                         count += ixgbe_read_regs_group(dev, &data[count],
7087                                 reg_group);
7088                 return 0;
7089         }
7090
7091         return -ENOTSUP;
7092 }
7093
7094 static int
7095 ixgbevf_get_regs(struct rte_eth_dev *dev,
7096                 struct rte_dev_reg_info *regs)
7097 {
7098         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7099         uint32_t *data = regs->data;
7100         int g_ind = 0;
7101         int count = 0;
7102         const struct reg_info *reg_group;
7103
7104         if (data == NULL) {
7105                 regs->length = ixgbevf_get_reg_length(dev);
7106                 regs->width = sizeof(uint32_t);
7107                 return 0;
7108         }
7109
7110         /* Support only full register dump */
7111         if ((regs->length == 0) ||
7112             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7113                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7114                         hw->device_id;
7115                 while ((reg_group = ixgbevf_regs[g_ind++]))
7116                         count += ixgbe_read_regs_group(dev, &data[count],
7117                                                       reg_group);
7118                 return 0;
7119         }
7120
7121         return -ENOTSUP;
7122 }
7123
7124 static int
7125 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7126 {
7127         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7128
7129         /* Return unit is byte count */
7130         return hw->eeprom.word_size * 2;
7131 }
7132
7133 static int
7134 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7135                 struct rte_dev_eeprom_info *in_eeprom)
7136 {
7137         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7138         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7139         uint16_t *data = in_eeprom->data;
7140         int first, length;
7141
7142         first = in_eeprom->offset >> 1;
7143         length = in_eeprom->length >> 1;
7144         if ((first > hw->eeprom.word_size) ||
7145             ((first + length) > hw->eeprom.word_size))
7146                 return -EINVAL;
7147
7148         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7149
7150         return eeprom->ops.read_buffer(hw, first, length, data);
7151 }
7152
7153 static int
7154 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7155                 struct rte_dev_eeprom_info *in_eeprom)
7156 {
7157         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7158         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7159         uint16_t *data = in_eeprom->data;
7160         int first, length;
7161
7162         first = in_eeprom->offset >> 1;
7163         length = in_eeprom->length >> 1;
7164         if ((first > hw->eeprom.word_size) ||
7165             ((first + length) > hw->eeprom.word_size))
7166                 return -EINVAL;
7167
7168         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7169
7170         return eeprom->ops.write_buffer(hw,  first, length, data);
7171 }
7172
7173 static int
7174 ixgbe_get_module_info(struct rte_eth_dev *dev,
7175                       struct rte_eth_dev_module_info *modinfo)
7176 {
7177         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7178         uint32_t status;
7179         uint8_t sff8472_rev, addr_mode;
7180         bool page_swap = false;
7181
7182         /* Check whether we support SFF-8472 or not */
7183         status = hw->phy.ops.read_i2c_eeprom(hw,
7184                                              IXGBE_SFF_SFF_8472_COMP,
7185                                              &sff8472_rev);
7186         if (status != 0)
7187                 return -EIO;
7188
7189         /* addressing mode is not supported */
7190         status = hw->phy.ops.read_i2c_eeprom(hw,
7191                                              IXGBE_SFF_SFF_8472_SWAP,
7192                                              &addr_mode);
7193         if (status != 0)
7194                 return -EIO;
7195
7196         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7197                 PMD_DRV_LOG(ERR,
7198                             "Address change required to access page 0xA2, "
7199                             "but not supported. Please report the module "
7200                             "type to the driver maintainers.");
7201                 page_swap = true;
7202         }
7203
7204         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7205                 /* We have a SFP, but it does not support SFF-8472 */
7206                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7207                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7208         } else {
7209                 /* We have a SFP which supports a revision of SFF-8472. */
7210                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7211                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7212         }
7213
7214         return 0;
7215 }
7216
7217 static int
7218 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7219                         struct rte_dev_eeprom_info *info)
7220 {
7221         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7222         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7223         uint8_t databyte = 0xFF;
7224         uint8_t *data = info->data;
7225         uint32_t i = 0;
7226
7227         if (info->length == 0)
7228                 return -EINVAL;
7229
7230         for (i = info->offset; i < info->offset + info->length; i++) {
7231                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7232                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7233                 else
7234                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7235
7236                 if (status != 0)
7237                         return -EIO;
7238
7239                 data[i - info->offset] = databyte;
7240         }
7241
7242         return 0;
7243 }
7244
7245 uint16_t
7246 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7247         switch (mac_type) {
7248         case ixgbe_mac_X550:
7249         case ixgbe_mac_X550EM_x:
7250         case ixgbe_mac_X550EM_a:
7251                 return ETH_RSS_RETA_SIZE_512;
7252         case ixgbe_mac_X550_vf:
7253         case ixgbe_mac_X550EM_x_vf:
7254         case ixgbe_mac_X550EM_a_vf:
7255                 return ETH_RSS_RETA_SIZE_64;
7256         default:
7257                 return ETH_RSS_RETA_SIZE_128;
7258         }
7259 }
7260
7261 uint32_t
7262 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7263         switch (mac_type) {
7264         case ixgbe_mac_X550:
7265         case ixgbe_mac_X550EM_x:
7266         case ixgbe_mac_X550EM_a:
7267                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7268                         return IXGBE_RETA(reta_idx >> 2);
7269                 else
7270                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7271         case ixgbe_mac_X550_vf:
7272         case ixgbe_mac_X550EM_x_vf:
7273         case ixgbe_mac_X550EM_a_vf:
7274                 return IXGBE_VFRETA(reta_idx >> 2);
7275         default:
7276                 return IXGBE_RETA(reta_idx >> 2);
7277         }
7278 }
7279
7280 uint32_t
7281 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7282         switch (mac_type) {
7283         case ixgbe_mac_X550_vf:
7284         case ixgbe_mac_X550EM_x_vf:
7285         case ixgbe_mac_X550EM_a_vf:
7286                 return IXGBE_VFMRQC;
7287         default:
7288                 return IXGBE_MRQC;
7289         }
7290 }
7291
7292 uint32_t
7293 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7294         switch (mac_type) {
7295         case ixgbe_mac_X550_vf:
7296         case ixgbe_mac_X550EM_x_vf:
7297         case ixgbe_mac_X550EM_a_vf:
7298                 return IXGBE_VFRSSRK(i);
7299         default:
7300                 return IXGBE_RSSRK(i);
7301         }
7302 }
7303
7304 bool
7305 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7306         switch (mac_type) {
7307         case ixgbe_mac_82599_vf:
7308         case ixgbe_mac_X540_vf:
7309                 return 0;
7310         default:
7311                 return 1;
7312         }
7313 }
7314
7315 static int
7316 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7317                         struct rte_eth_dcb_info *dcb_info)
7318 {
7319         struct ixgbe_dcb_config *dcb_config =
7320                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7321         struct ixgbe_dcb_tc_config *tc;
7322         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7323         uint8_t nb_tcs;
7324         uint8_t i, j;
7325
7326         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7327                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7328         else
7329                 dcb_info->nb_tcs = 1;
7330
7331         tc_queue = &dcb_info->tc_queue;
7332         nb_tcs = dcb_info->nb_tcs;
7333
7334         if (dcb_config->vt_mode) { /* vt is enabled*/
7335                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7336                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7337                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7338                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7339                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7340                         for (j = 0; j < nb_tcs; j++) {
7341                                 tc_queue->tc_rxq[0][j].base = j;
7342                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7343                                 tc_queue->tc_txq[0][j].base = j;
7344                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7345                         }
7346                 } else {
7347                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7348                                 for (j = 0; j < nb_tcs; j++) {
7349                                         tc_queue->tc_rxq[i][j].base =
7350                                                 i * nb_tcs + j;
7351                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7352                                         tc_queue->tc_txq[i][j].base =
7353                                                 i * nb_tcs + j;
7354                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7355                                 }
7356                         }
7357                 }
7358         } else { /* vt is disabled*/
7359                 struct rte_eth_dcb_rx_conf *rx_conf =
7360                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7361                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7362                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7363                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7364                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7365                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7366                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7367                         }
7368                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7369                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7370                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7371                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7372                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7373                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7374                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7375                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7376                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7377                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7378                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7379                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7380                         }
7381                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7382                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7383                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7384                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7385                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7386                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7387                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7388                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7389                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7390                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7391                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7392                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7393                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7394                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7395                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7396                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7397                 }
7398         }
7399         for (i = 0; i < dcb_info->nb_tcs; i++) {
7400                 tc = &dcb_config->tc_config[i];
7401                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7402         }
7403         return 0;
7404 }
7405
7406 /* Update e-tag ether type */
7407 static int
7408 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7409                             uint16_t ether_type)
7410 {
7411         uint32_t etag_etype;
7412
7413         if (hw->mac.type != ixgbe_mac_X550 &&
7414             hw->mac.type != ixgbe_mac_X550EM_x &&
7415             hw->mac.type != ixgbe_mac_X550EM_a) {
7416                 return -ENOTSUP;
7417         }
7418
7419         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7420         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7421         etag_etype |= ether_type;
7422         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7423         IXGBE_WRITE_FLUSH(hw);
7424
7425         return 0;
7426 }
7427
7428 /* Config l2 tunnel ether type */
7429 static int
7430 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7431                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7432 {
7433         int ret = 0;
7434         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7435         struct ixgbe_l2_tn_info *l2_tn_info =
7436                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7437
7438         if (l2_tunnel == NULL)
7439                 return -EINVAL;
7440
7441         switch (l2_tunnel->l2_tunnel_type) {
7442         case RTE_L2_TUNNEL_TYPE_E_TAG:
7443                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7444                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7445                 break;
7446         default:
7447                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7448                 ret = -EINVAL;
7449                 break;
7450         }
7451
7452         return ret;
7453 }
7454
7455 /* Enable e-tag tunnel */
7456 static int
7457 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7458 {
7459         uint32_t etag_etype;
7460
7461         if (hw->mac.type != ixgbe_mac_X550 &&
7462             hw->mac.type != ixgbe_mac_X550EM_x &&
7463             hw->mac.type != ixgbe_mac_X550EM_a) {
7464                 return -ENOTSUP;
7465         }
7466
7467         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7468         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7469         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7470         IXGBE_WRITE_FLUSH(hw);
7471
7472         return 0;
7473 }
7474
7475 /* Enable l2 tunnel */
7476 static int
7477 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7478                            enum rte_eth_tunnel_type l2_tunnel_type)
7479 {
7480         int ret = 0;
7481         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7482         struct ixgbe_l2_tn_info *l2_tn_info =
7483                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7484
7485         switch (l2_tunnel_type) {
7486         case RTE_L2_TUNNEL_TYPE_E_TAG:
7487                 l2_tn_info->e_tag_en = TRUE;
7488                 ret = ixgbe_e_tag_enable(hw);
7489                 break;
7490         default:
7491                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7492                 ret = -EINVAL;
7493                 break;
7494         }
7495
7496         return ret;
7497 }
7498
7499 /* Disable e-tag tunnel */
7500 static int
7501 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7502 {
7503         uint32_t etag_etype;
7504
7505         if (hw->mac.type != ixgbe_mac_X550 &&
7506             hw->mac.type != ixgbe_mac_X550EM_x &&
7507             hw->mac.type != ixgbe_mac_X550EM_a) {
7508                 return -ENOTSUP;
7509         }
7510
7511         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7512         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7513         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7514         IXGBE_WRITE_FLUSH(hw);
7515
7516         return 0;
7517 }
7518
7519 /* Disable l2 tunnel */
7520 static int
7521 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7522                             enum rte_eth_tunnel_type l2_tunnel_type)
7523 {
7524         int ret = 0;
7525         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7526         struct ixgbe_l2_tn_info *l2_tn_info =
7527                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7528
7529         switch (l2_tunnel_type) {
7530         case RTE_L2_TUNNEL_TYPE_E_TAG:
7531                 l2_tn_info->e_tag_en = FALSE;
7532                 ret = ixgbe_e_tag_disable(hw);
7533                 break;
7534         default:
7535                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7536                 ret = -EINVAL;
7537                 break;
7538         }
7539
7540         return ret;
7541 }
7542
7543 static int
7544 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7545                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7546 {
7547         int ret = 0;
7548         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7549         uint32_t i, rar_entries;
7550         uint32_t rar_low, rar_high;
7551
7552         if (hw->mac.type != ixgbe_mac_X550 &&
7553             hw->mac.type != ixgbe_mac_X550EM_x &&
7554             hw->mac.type != ixgbe_mac_X550EM_a) {
7555                 return -ENOTSUP;
7556         }
7557
7558         rar_entries = ixgbe_get_num_rx_addrs(hw);
7559
7560         for (i = 1; i < rar_entries; i++) {
7561                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7562                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7563                 if ((rar_high & IXGBE_RAH_AV) &&
7564                     (rar_high & IXGBE_RAH_ADTYPE) &&
7565                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7566                      l2_tunnel->tunnel_id)) {
7567                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7568                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7569
7570                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7571
7572                         return ret;
7573                 }
7574         }
7575
7576         return ret;
7577 }
7578
7579 static int
7580 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7581                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7582 {
7583         int ret = 0;
7584         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7585         uint32_t i, rar_entries;
7586         uint32_t rar_low, rar_high;
7587
7588         if (hw->mac.type != ixgbe_mac_X550 &&
7589             hw->mac.type != ixgbe_mac_X550EM_x &&
7590             hw->mac.type != ixgbe_mac_X550EM_a) {
7591                 return -ENOTSUP;
7592         }
7593
7594         /* One entry for one tunnel. Try to remove potential existing entry. */
7595         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7596
7597         rar_entries = ixgbe_get_num_rx_addrs(hw);
7598
7599         for (i = 1; i < rar_entries; i++) {
7600                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7601                 if (rar_high & IXGBE_RAH_AV) {
7602                         continue;
7603                 } else {
7604                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7605                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7606                         rar_low = l2_tunnel->tunnel_id;
7607
7608                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7609                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7610
7611                         return ret;
7612                 }
7613         }
7614
7615         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7616                      " Please remove a rule before adding a new one.");
7617         return -EINVAL;
7618 }
7619
7620 static inline struct ixgbe_l2_tn_filter *
7621 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7622                           struct ixgbe_l2_tn_key *key)
7623 {
7624         int ret;
7625
7626         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7627         if (ret < 0)
7628                 return NULL;
7629
7630         return l2_tn_info->hash_map[ret];
7631 }
7632
7633 static inline int
7634 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7635                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7636 {
7637         int ret;
7638
7639         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7640                                &l2_tn_filter->key);
7641
7642         if (ret < 0) {
7643                 PMD_DRV_LOG(ERR,
7644                             "Failed to insert L2 tunnel filter"
7645                             " to hash table %d!",
7646                             ret);
7647                 return ret;
7648         }
7649
7650         l2_tn_info->hash_map[ret] = l2_tn_filter;
7651
7652         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7653
7654         return 0;
7655 }
7656
7657 static inline int
7658 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7659                           struct ixgbe_l2_tn_key *key)
7660 {
7661         int ret;
7662         struct ixgbe_l2_tn_filter *l2_tn_filter;
7663
7664         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7665
7666         if (ret < 0) {
7667                 PMD_DRV_LOG(ERR,
7668                             "No such L2 tunnel filter to delete %d!",
7669                             ret);
7670                 return ret;
7671         }
7672
7673         l2_tn_filter = l2_tn_info->hash_map[ret];
7674         l2_tn_info->hash_map[ret] = NULL;
7675
7676         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7677         rte_free(l2_tn_filter);
7678
7679         return 0;
7680 }
7681
7682 /* Add l2 tunnel filter */
7683 int
7684 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7685                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7686                                bool restore)
7687 {
7688         int ret;
7689         struct ixgbe_l2_tn_info *l2_tn_info =
7690                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7691         struct ixgbe_l2_tn_key key;
7692         struct ixgbe_l2_tn_filter *node;
7693
7694         if (!restore) {
7695                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7696                 key.tn_id = l2_tunnel->tunnel_id;
7697
7698                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7699
7700                 if (node) {
7701                         PMD_DRV_LOG(ERR,
7702                                     "The L2 tunnel filter already exists!");
7703                         return -EINVAL;
7704                 }
7705
7706                 node = rte_zmalloc("ixgbe_l2_tn",
7707                                    sizeof(struct ixgbe_l2_tn_filter),
7708                                    0);
7709                 if (!node)
7710                         return -ENOMEM;
7711
7712                 rte_memcpy(&node->key,
7713                                  &key,
7714                                  sizeof(struct ixgbe_l2_tn_key));
7715                 node->pool = l2_tunnel->pool;
7716                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7717                 if (ret < 0) {
7718                         rte_free(node);
7719                         return ret;
7720                 }
7721         }
7722
7723         switch (l2_tunnel->l2_tunnel_type) {
7724         case RTE_L2_TUNNEL_TYPE_E_TAG:
7725                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7726                 break;
7727         default:
7728                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7729                 ret = -EINVAL;
7730                 break;
7731         }
7732
7733         if ((!restore) && (ret < 0))
7734                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7735
7736         return ret;
7737 }
7738
7739 /* Delete l2 tunnel filter */
7740 int
7741 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7742                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7743 {
7744         int ret;
7745         struct ixgbe_l2_tn_info *l2_tn_info =
7746                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7747         struct ixgbe_l2_tn_key key;
7748
7749         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7750         key.tn_id = l2_tunnel->tunnel_id;
7751         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7752         if (ret < 0)
7753                 return ret;
7754
7755         switch (l2_tunnel->l2_tunnel_type) {
7756         case RTE_L2_TUNNEL_TYPE_E_TAG:
7757                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7758                 break;
7759         default:
7760                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7761                 ret = -EINVAL;
7762                 break;
7763         }
7764
7765         return ret;
7766 }
7767
7768 /**
7769  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7770  * @dev: pointer to rte_eth_dev structure
7771  * @filter_op:operation will be taken.
7772  * @arg: a pointer to specific structure corresponding to the filter_op
7773  */
7774 static int
7775 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7776                                   enum rte_filter_op filter_op,
7777                                   void *arg)
7778 {
7779         int ret;
7780
7781         if (filter_op == RTE_ETH_FILTER_NOP)
7782                 return 0;
7783
7784         if (arg == NULL) {
7785                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7786                             filter_op);
7787                 return -EINVAL;
7788         }
7789
7790         switch (filter_op) {
7791         case RTE_ETH_FILTER_ADD:
7792                 ret = ixgbe_dev_l2_tunnel_filter_add
7793                         (dev,
7794                          (struct rte_eth_l2_tunnel_conf *)arg,
7795                          FALSE);
7796                 break;
7797         case RTE_ETH_FILTER_DELETE:
7798                 ret = ixgbe_dev_l2_tunnel_filter_del
7799                         (dev,
7800                          (struct rte_eth_l2_tunnel_conf *)arg);
7801                 break;
7802         default:
7803                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7804                 ret = -EINVAL;
7805                 break;
7806         }
7807         return ret;
7808 }
7809
7810 static int
7811 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7812 {
7813         int ret = 0;
7814         uint32_t ctrl;
7815         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7816
7817         if (hw->mac.type != ixgbe_mac_X550 &&
7818             hw->mac.type != ixgbe_mac_X550EM_x &&
7819             hw->mac.type != ixgbe_mac_X550EM_a) {
7820                 return -ENOTSUP;
7821         }
7822
7823         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7824         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7825         if (en)
7826                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7827         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7828
7829         return ret;
7830 }
7831
7832 /* Enable l2 tunnel forwarding */
7833 static int
7834 ixgbe_dev_l2_tunnel_forwarding_enable
7835         (struct rte_eth_dev *dev,
7836          enum rte_eth_tunnel_type l2_tunnel_type)
7837 {
7838         struct ixgbe_l2_tn_info *l2_tn_info =
7839                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7840         int ret = 0;
7841
7842         switch (l2_tunnel_type) {
7843         case RTE_L2_TUNNEL_TYPE_E_TAG:
7844                 l2_tn_info->e_tag_fwd_en = TRUE;
7845                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7846                 break;
7847         default:
7848                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7849                 ret = -EINVAL;
7850                 break;
7851         }
7852
7853         return ret;
7854 }
7855
7856 /* Disable l2 tunnel forwarding */
7857 static int
7858 ixgbe_dev_l2_tunnel_forwarding_disable
7859         (struct rte_eth_dev *dev,
7860          enum rte_eth_tunnel_type l2_tunnel_type)
7861 {
7862         struct ixgbe_l2_tn_info *l2_tn_info =
7863                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7864         int ret = 0;
7865
7866         switch (l2_tunnel_type) {
7867         case RTE_L2_TUNNEL_TYPE_E_TAG:
7868                 l2_tn_info->e_tag_fwd_en = FALSE;
7869                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7870                 break;
7871         default:
7872                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7873                 ret = -EINVAL;
7874                 break;
7875         }
7876
7877         return ret;
7878 }
7879
7880 static int
7881 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7882                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7883                              bool en)
7884 {
7885         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7886         int ret = 0;
7887         uint32_t vmtir, vmvir;
7888         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7889
7890         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7891                 PMD_DRV_LOG(ERR,
7892                             "VF id %u should be less than %u",
7893                             l2_tunnel->vf_id,
7894                             pci_dev->max_vfs);
7895                 return -EINVAL;
7896         }
7897
7898         if (hw->mac.type != ixgbe_mac_X550 &&
7899             hw->mac.type != ixgbe_mac_X550EM_x &&
7900             hw->mac.type != ixgbe_mac_X550EM_a) {
7901                 return -ENOTSUP;
7902         }
7903
7904         if (en)
7905                 vmtir = l2_tunnel->tunnel_id;
7906         else
7907                 vmtir = 0;
7908
7909         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7910
7911         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7912         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7913         if (en)
7914                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7915         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7916
7917         return ret;
7918 }
7919
7920 /* Enable l2 tunnel tag insertion */
7921 static int
7922 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7923                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7924 {
7925         int ret = 0;
7926
7927         switch (l2_tunnel->l2_tunnel_type) {
7928         case RTE_L2_TUNNEL_TYPE_E_TAG:
7929                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7930                 break;
7931         default:
7932                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7933                 ret = -EINVAL;
7934                 break;
7935         }
7936
7937         return ret;
7938 }
7939
7940 /* Disable l2 tunnel tag insertion */
7941 static int
7942 ixgbe_dev_l2_tunnel_insertion_disable
7943         (struct rte_eth_dev *dev,
7944          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7945 {
7946         int ret = 0;
7947
7948         switch (l2_tunnel->l2_tunnel_type) {
7949         case RTE_L2_TUNNEL_TYPE_E_TAG:
7950                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7951                 break;
7952         default:
7953                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7954                 ret = -EINVAL;
7955                 break;
7956         }
7957
7958         return ret;
7959 }
7960
7961 static int
7962 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7963                              bool en)
7964 {
7965         int ret = 0;
7966         uint32_t qde;
7967         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7968
7969         if (hw->mac.type != ixgbe_mac_X550 &&
7970             hw->mac.type != ixgbe_mac_X550EM_x &&
7971             hw->mac.type != ixgbe_mac_X550EM_a) {
7972                 return -ENOTSUP;
7973         }
7974
7975         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7976         if (en)
7977                 qde |= IXGBE_QDE_STRIP_TAG;
7978         else
7979                 qde &= ~IXGBE_QDE_STRIP_TAG;
7980         qde &= ~IXGBE_QDE_READ;
7981         qde |= IXGBE_QDE_WRITE;
7982         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7983
7984         return ret;
7985 }
7986
7987 /* Enable l2 tunnel tag stripping */
7988 static int
7989 ixgbe_dev_l2_tunnel_stripping_enable
7990         (struct rte_eth_dev *dev,
7991          enum rte_eth_tunnel_type l2_tunnel_type)
7992 {
7993         int ret = 0;
7994
7995         switch (l2_tunnel_type) {
7996         case RTE_L2_TUNNEL_TYPE_E_TAG:
7997                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7998                 break;
7999         default:
8000                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8001                 ret = -EINVAL;
8002                 break;
8003         }
8004
8005         return ret;
8006 }
8007
8008 /* Disable l2 tunnel tag stripping */
8009 static int
8010 ixgbe_dev_l2_tunnel_stripping_disable
8011         (struct rte_eth_dev *dev,
8012          enum rte_eth_tunnel_type l2_tunnel_type)
8013 {
8014         int ret = 0;
8015
8016         switch (l2_tunnel_type) {
8017         case RTE_L2_TUNNEL_TYPE_E_TAG:
8018                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8019                 break;
8020         default:
8021                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8022                 ret = -EINVAL;
8023                 break;
8024         }
8025
8026         return ret;
8027 }
8028
8029 /* Enable/disable l2 tunnel offload functions */
8030 static int
8031 ixgbe_dev_l2_tunnel_offload_set
8032         (struct rte_eth_dev *dev,
8033          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8034          uint32_t mask,
8035          uint8_t en)
8036 {
8037         int ret = 0;
8038
8039         if (l2_tunnel == NULL)
8040                 return -EINVAL;
8041
8042         ret = -EINVAL;
8043         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8044                 if (en)
8045                         ret = ixgbe_dev_l2_tunnel_enable(
8046                                 dev,
8047                                 l2_tunnel->l2_tunnel_type);
8048                 else
8049                         ret = ixgbe_dev_l2_tunnel_disable(
8050                                 dev,
8051                                 l2_tunnel->l2_tunnel_type);
8052         }
8053
8054         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8055                 if (en)
8056                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8057                                 dev,
8058                                 l2_tunnel);
8059                 else
8060                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8061                                 dev,
8062                                 l2_tunnel);
8063         }
8064
8065         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8066                 if (en)
8067                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8068                                 dev,
8069                                 l2_tunnel->l2_tunnel_type);
8070                 else
8071                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8072                                 dev,
8073                                 l2_tunnel->l2_tunnel_type);
8074         }
8075
8076         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8077                 if (en)
8078                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8079                                 dev,
8080                                 l2_tunnel->l2_tunnel_type);
8081                 else
8082                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8083                                 dev,
8084                                 l2_tunnel->l2_tunnel_type);
8085         }
8086
8087         return ret;
8088 }
8089
8090 static int
8091 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8092                         uint16_t port)
8093 {
8094         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8095         IXGBE_WRITE_FLUSH(hw);
8096
8097         return 0;
8098 }
8099
8100 /* There's only one register for VxLAN UDP port.
8101  * So, we cannot add several ports. Will update it.
8102  */
8103 static int
8104 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8105                      uint16_t port)
8106 {
8107         if (port == 0) {
8108                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8109                 return -EINVAL;
8110         }
8111
8112         return ixgbe_update_vxlan_port(hw, port);
8113 }
8114
8115 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8116  * UDP port, it must have a value.
8117  * So, will reset it to the original value 0.
8118  */
8119 static int
8120 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8121                      uint16_t port)
8122 {
8123         uint16_t cur_port;
8124
8125         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8126
8127         if (cur_port != port) {
8128                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8129                 return -EINVAL;
8130         }
8131
8132         return ixgbe_update_vxlan_port(hw, 0);
8133 }
8134
8135 /* Add UDP tunneling port */
8136 static int
8137 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8138                               struct rte_eth_udp_tunnel *udp_tunnel)
8139 {
8140         int ret = 0;
8141         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8142
8143         if (hw->mac.type != ixgbe_mac_X550 &&
8144             hw->mac.type != ixgbe_mac_X550EM_x &&
8145             hw->mac.type != ixgbe_mac_X550EM_a) {
8146                 return -ENOTSUP;
8147         }
8148
8149         if (udp_tunnel == NULL)
8150                 return -EINVAL;
8151
8152         switch (udp_tunnel->prot_type) {
8153         case RTE_TUNNEL_TYPE_VXLAN:
8154                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8155                 break;
8156
8157         case RTE_TUNNEL_TYPE_GENEVE:
8158         case RTE_TUNNEL_TYPE_TEREDO:
8159                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8160                 ret = -EINVAL;
8161                 break;
8162
8163         default:
8164                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8165                 ret = -EINVAL;
8166                 break;
8167         }
8168
8169         return ret;
8170 }
8171
8172 /* Remove UDP tunneling port */
8173 static int
8174 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8175                               struct rte_eth_udp_tunnel *udp_tunnel)
8176 {
8177         int ret = 0;
8178         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8179
8180         if (hw->mac.type != ixgbe_mac_X550 &&
8181             hw->mac.type != ixgbe_mac_X550EM_x &&
8182             hw->mac.type != ixgbe_mac_X550EM_a) {
8183                 return -ENOTSUP;
8184         }
8185
8186         if (udp_tunnel == NULL)
8187                 return -EINVAL;
8188
8189         switch (udp_tunnel->prot_type) {
8190         case RTE_TUNNEL_TYPE_VXLAN:
8191                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8192                 break;
8193         case RTE_TUNNEL_TYPE_GENEVE:
8194         case RTE_TUNNEL_TYPE_TEREDO:
8195                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8196                 ret = -EINVAL;
8197                 break;
8198         default:
8199                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8200                 ret = -EINVAL;
8201                 break;
8202         }
8203
8204         return ret;
8205 }
8206
8207 static void
8208 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8209 {
8210         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8211
8212         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8213 }
8214
8215 static void
8216 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8217 {
8218         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8219
8220         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8221 }
8222
8223 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8224 {
8225         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8226         u32 in_msg = 0;
8227
8228         /* peek the message first */
8229         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8230
8231         /* PF reset VF event */
8232         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8233                 /* dummy mbx read to ack pf */
8234                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8235                         return;
8236                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8237                                               NULL);
8238         }
8239 }
8240
8241 static int
8242 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8243 {
8244         uint32_t eicr;
8245         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8246         struct ixgbe_interrupt *intr =
8247                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8248         ixgbevf_intr_disable(dev);
8249
8250         /* read-on-clear nic registers here */
8251         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8252         intr->flags = 0;
8253
8254         /* only one misc vector supported - mailbox */
8255         eicr &= IXGBE_VTEICR_MASK;
8256         if (eicr == IXGBE_MISC_VEC_ID)
8257                 intr->flags |= IXGBE_FLAG_MAILBOX;
8258
8259         return 0;
8260 }
8261
8262 static int
8263 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8264 {
8265         struct ixgbe_interrupt *intr =
8266                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8267
8268         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8269                 ixgbevf_mbx_process(dev);
8270                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8271         }
8272
8273         ixgbevf_intr_enable(dev);
8274
8275         return 0;
8276 }
8277
8278 static void
8279 ixgbevf_dev_interrupt_handler(void *param)
8280 {
8281         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8282
8283         ixgbevf_dev_interrupt_get_status(dev);
8284         ixgbevf_dev_interrupt_action(dev);
8285 }
8286
8287 /**
8288  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8289  *  @hw: pointer to hardware structure
8290  *
8291  *  Stops the transmit data path and waits for the HW to internally empty
8292  *  the Tx security block
8293  **/
8294 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8295 {
8296 #define IXGBE_MAX_SECTX_POLL 40
8297
8298         int i;
8299         int sectxreg;
8300
8301         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8302         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8303         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8304         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8305                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8306                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8307                         break;
8308                 /* Use interrupt-safe sleep just in case */
8309                 usec_delay(1000);
8310         }
8311
8312         /* For informational purposes only */
8313         if (i >= IXGBE_MAX_SECTX_POLL)
8314                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8315                          "path fully disabled.  Continuing with init.");
8316
8317         return IXGBE_SUCCESS;
8318 }
8319
8320 /**
8321  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8322  *  @hw: pointer to hardware structure
8323  *
8324  *  Enables the transmit data path.
8325  **/
8326 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8327 {
8328         uint32_t sectxreg;
8329
8330         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8331         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8332         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8333         IXGBE_WRITE_FLUSH(hw);
8334
8335         return IXGBE_SUCCESS;
8336 }
8337
8338 /* restore n-tuple filter */
8339 static inline void
8340 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8341 {
8342         struct ixgbe_filter_info *filter_info =
8343                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8344         struct ixgbe_5tuple_filter *node;
8345
8346         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8347                 ixgbe_inject_5tuple_filter(dev, node);
8348         }
8349 }
8350
8351 /* restore ethernet type filter */
8352 static inline void
8353 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8354 {
8355         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8356         struct ixgbe_filter_info *filter_info =
8357                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8358         int i;
8359
8360         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8361                 if (filter_info->ethertype_mask & (1 << i)) {
8362                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8363                                         filter_info->ethertype_filters[i].etqf);
8364                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8365                                         filter_info->ethertype_filters[i].etqs);
8366                         IXGBE_WRITE_FLUSH(hw);
8367                 }
8368         }
8369 }
8370
8371 /* restore SYN filter */
8372 static inline void
8373 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8374 {
8375         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8376         struct ixgbe_filter_info *filter_info =
8377                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8378         uint32_t synqf;
8379
8380         synqf = filter_info->syn_info;
8381
8382         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8383                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8384                 IXGBE_WRITE_FLUSH(hw);
8385         }
8386 }
8387
8388 /* restore L2 tunnel filter */
8389 static inline void
8390 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8391 {
8392         struct ixgbe_l2_tn_info *l2_tn_info =
8393                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8394         struct ixgbe_l2_tn_filter *node;
8395         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8396
8397         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8398                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8399                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8400                 l2_tn_conf.pool           = node->pool;
8401                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8402         }
8403 }
8404
8405 /* restore rss filter */
8406 static inline void
8407 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8408 {
8409         struct ixgbe_filter_info *filter_info =
8410                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8411
8412         if (filter_info->rss_info.conf.queue_num)
8413                 ixgbe_config_rss_filter(dev,
8414                         &filter_info->rss_info, TRUE);
8415 }
8416
8417 static int
8418 ixgbe_filter_restore(struct rte_eth_dev *dev)
8419 {
8420         ixgbe_ntuple_filter_restore(dev);
8421         ixgbe_ethertype_filter_restore(dev);
8422         ixgbe_syn_filter_restore(dev);
8423         ixgbe_fdir_filter_restore(dev);
8424         ixgbe_l2_tn_filter_restore(dev);
8425         ixgbe_rss_filter_restore(dev);
8426
8427         return 0;
8428 }
8429
8430 static void
8431 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8432 {
8433         struct ixgbe_l2_tn_info *l2_tn_info =
8434                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8435         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8436
8437         if (l2_tn_info->e_tag_en)
8438                 (void)ixgbe_e_tag_enable(hw);
8439
8440         if (l2_tn_info->e_tag_fwd_en)
8441                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8442
8443         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8444 }
8445
8446 /* remove all the n-tuple filters */
8447 void
8448 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8449 {
8450         struct ixgbe_filter_info *filter_info =
8451                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8452         struct ixgbe_5tuple_filter *p_5tuple;
8453
8454         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8455                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8456 }
8457
8458 /* remove all the ether type filters */
8459 void
8460 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8461 {
8462         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8463         struct ixgbe_filter_info *filter_info =
8464                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8465         int i;
8466
8467         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8468                 if (filter_info->ethertype_mask & (1 << i) &&
8469                     !filter_info->ethertype_filters[i].conf) {
8470                         (void)ixgbe_ethertype_filter_remove(filter_info,
8471                                                             (uint8_t)i);
8472                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8473                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8474                         IXGBE_WRITE_FLUSH(hw);
8475                 }
8476         }
8477 }
8478
8479 /* remove the SYN filter */
8480 void
8481 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8482 {
8483         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8484         struct ixgbe_filter_info *filter_info =
8485                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8486
8487         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8488                 filter_info->syn_info = 0;
8489
8490                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8491                 IXGBE_WRITE_FLUSH(hw);
8492         }
8493 }
8494
8495 /* remove all the L2 tunnel filters */
8496 int
8497 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8498 {
8499         struct ixgbe_l2_tn_info *l2_tn_info =
8500                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8501         struct ixgbe_l2_tn_filter *l2_tn_filter;
8502         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8503         int ret = 0;
8504
8505         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8506                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8507                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8508                 l2_tn_conf.pool           = l2_tn_filter->pool;
8509                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8510                 if (ret < 0)
8511                         return ret;
8512         }
8513
8514         return 0;
8515 }
8516
8517 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8518 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8519 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8520 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8521 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8522 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8523
8524 RTE_INIT(ixgbe_init_log);
8525 static void
8526 ixgbe_init_log(void)
8527 {
8528         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8529         if (ixgbe_logtype_init >= 0)
8530                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8531         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8532         if (ixgbe_logtype_driver >= 0)
8533                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8534 }