1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
13 #include <netinet/in.h>
14 #include <rte_byteorder.h>
15 #include <rte_common.h>
16 #include <rte_cycles.h>
18 #include <rte_interrupts.h>
20 #include <rte_debug.h>
22 #include <rte_bus_pci.h>
23 #include <rte_atomic.h>
24 #include <rte_branch_prediction.h>
25 #include <rte_memory.h>
27 #include <rte_alarm.h>
28 #include <rte_ether.h>
29 #include <rte_ethdev.h>
30 #include <rte_ethdev_pci.h>
31 #include <rte_malloc.h>
32 #include <rte_random.h>
34 #include <rte_hash_crc.h>
35 #ifdef RTE_LIBRTE_SECURITY
36 #include <rte_security_driver.h>
39 #include "ixgbe_logs.h"
40 #include "base/ixgbe_api.h"
41 #include "base/ixgbe_vf.h"
42 #include "base/ixgbe_common.h"
43 #include "ixgbe_ethdev.h"
44 #include "ixgbe_bypass.h"
45 #include "ixgbe_rxtx.h"
46 #include "base/ixgbe_type.h"
47 #include "base/ixgbe_phy.h"
48 #include "ixgbe_regs.h"
51 * High threshold controlling when to start sending XOFF frames. Must be at
52 * least 8 bytes less than receive packet buffer size. This value is in units
55 #define IXGBE_FC_HI 0x80
58 * Low threshold controlling when to start sending XON frames. This value is
59 * in units of 1024 bytes.
61 #define IXGBE_FC_LO 0x40
63 /* Default minimum inter-interrupt interval for EITR configuration */
64 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
66 /* Timer value included in XOFF frames. */
67 #define IXGBE_FC_PAUSE 0x680
69 /*Default value of Max Rx Queue*/
70 #define IXGBE_MAX_RX_QUEUE_NUM 128
72 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
73 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
74 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
76 #define IXGBE_MMW_SIZE_DEFAULT 0x4
77 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
78 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
81 * Default values for RX/TX configuration
83 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
84 #define IXGBE_DEFAULT_RX_PTHRESH 8
85 #define IXGBE_DEFAULT_RX_HTHRESH 8
86 #define IXGBE_DEFAULT_RX_WTHRESH 0
88 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
89 #define IXGBE_DEFAULT_TX_PTHRESH 32
90 #define IXGBE_DEFAULT_TX_HTHRESH 0
91 #define IXGBE_DEFAULT_TX_WTHRESH 0
92 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
94 /* Bit shift and mask */
95 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
96 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
97 #define IXGBE_8_BIT_WIDTH CHAR_BIT
98 #define IXGBE_8_BIT_MASK UINT8_MAX
100 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
102 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
104 #define IXGBE_HKEY_MAX_INDEX 10
106 /* Additional timesync values. */
107 #define NSEC_PER_SEC 1000000000L
108 #define IXGBE_INCVAL_10GB 0x66666666
109 #define IXGBE_INCVAL_1GB 0x40000000
110 #define IXGBE_INCVAL_100 0x50000000
111 #define IXGBE_INCVAL_SHIFT_10GB 28
112 #define IXGBE_INCVAL_SHIFT_1GB 24
113 #define IXGBE_INCVAL_SHIFT_100 21
114 #define IXGBE_INCVAL_SHIFT_82599 7
115 #define IXGBE_INCPER_SHIFT_82599 24
117 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
119 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
120 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
121 #define DEFAULT_ETAG_ETYPE 0x893f
122 #define IXGBE_ETAG_ETYPE 0x00005084
123 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
124 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
125 #define IXGBE_RAH_ADTYPE 0x40000000
126 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
127 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
128 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
129 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
130 #define IXGBE_QDE_STRIP_TAG 0x00000004
131 #define IXGBE_VTEICR_MASK 0x07
133 #define IXGBE_EXVET_VET_EXT_SHIFT 16
134 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
136 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
137 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
138 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
139 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
140 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
141 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
142 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
143 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
144 static int ixgbe_dev_start(struct rte_eth_dev *dev);
145 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
146 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
147 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
148 static void ixgbe_dev_close(struct rte_eth_dev *dev);
149 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
150 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
151 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
152 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
153 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
154 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
155 int wait_to_complete);
156 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
157 struct rte_eth_stats *stats);
158 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
159 struct rte_eth_xstat *xstats, unsigned n);
160 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
161 struct rte_eth_xstat *xstats, unsigned n);
163 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
164 uint64_t *values, unsigned int n);
165 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
166 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
167 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
168 struct rte_eth_xstat_name *xstats_names,
170 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
171 struct rte_eth_xstat_name *xstats_names, unsigned limit);
172 static int ixgbe_dev_xstats_get_names_by_id(
173 struct rte_eth_dev *dev,
174 struct rte_eth_xstat_name *xstats_names,
177 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
181 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
183 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
184 struct rte_eth_dev_info *dev_info);
185 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
186 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
187 struct rte_eth_dev_info *dev_info);
188 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
190 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
191 uint16_t vlan_id, int on);
192 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
193 enum rte_vlan_type vlan_type,
195 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
196 uint16_t queue, bool on);
197 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
199 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
200 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
201 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
202 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
203 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
205 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
206 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
207 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
208 struct rte_eth_fc_conf *fc_conf);
209 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
210 struct rte_eth_fc_conf *fc_conf);
211 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
212 struct rte_eth_pfc_conf *pfc_conf);
213 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
214 struct rte_eth_rss_reta_entry64 *reta_conf,
216 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
217 struct rte_eth_rss_reta_entry64 *reta_conf,
219 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
220 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
221 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
222 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
223 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
224 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
225 struct rte_intr_handle *handle);
226 static void ixgbe_dev_interrupt_handler(void *param);
227 static void ixgbe_dev_interrupt_delayed_handler(void *param);
228 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
229 uint32_t index, uint32_t pool);
230 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
231 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
232 struct ether_addr *mac_addr);
233 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
234 static bool is_device_supported(struct rte_eth_dev *dev,
235 struct rte_pci_driver *drv);
237 /* For Virtual Function support */
238 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
239 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
240 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
241 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
242 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
243 int wait_to_complete);
244 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
245 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
246 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
247 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
248 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
249 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
250 struct rte_eth_stats *stats);
251 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
252 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
253 uint16_t vlan_id, int on);
254 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
255 uint16_t queue, int on);
256 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
257 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
258 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
260 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
262 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
263 uint8_t queue, uint8_t msix_vector);
264 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
265 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
266 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
268 /* For Eth VMDQ APIs support */
269 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
270 ether_addr * mac_addr, uint8_t on);
271 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
272 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
273 struct rte_eth_mirror_conf *mirror_conf,
274 uint8_t rule_id, uint8_t on);
275 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
277 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
279 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
281 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
282 uint8_t queue, uint8_t msix_vector);
283 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
285 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
286 struct ether_addr *mac_addr,
287 uint32_t index, uint32_t pool);
288 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
289 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
290 struct ether_addr *mac_addr);
291 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
292 struct rte_eth_syn_filter *filter);
293 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
294 enum rte_filter_op filter_op,
296 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
297 struct ixgbe_5tuple_filter *filter);
298 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
299 struct ixgbe_5tuple_filter *filter);
300 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
301 enum rte_filter_op filter_op,
303 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
304 struct rte_eth_ntuple_filter *filter);
305 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
306 enum rte_filter_op filter_op,
308 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
309 struct rte_eth_ethertype_filter *filter);
310 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
311 enum rte_filter_type filter_type,
312 enum rte_filter_op filter_op,
314 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
316 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
317 struct ether_addr *mc_addr_set,
318 uint32_t nb_mc_addr);
319 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
320 struct rte_eth_dcb_info *dcb_info);
322 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
323 static int ixgbe_get_regs(struct rte_eth_dev *dev,
324 struct rte_dev_reg_info *regs);
325 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
326 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
327 struct rte_dev_eeprom_info *eeprom);
328 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
329 struct rte_dev_eeprom_info *eeprom);
331 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
332 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
333 struct rte_dev_reg_info *regs);
335 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
336 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
337 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
338 struct timespec *timestamp,
340 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
341 struct timespec *timestamp);
342 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
343 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
344 struct timespec *timestamp);
345 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
346 const struct timespec *timestamp);
347 static void ixgbevf_dev_interrupt_handler(void *param);
349 static int ixgbe_dev_l2_tunnel_eth_type_conf
350 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
351 static int ixgbe_dev_l2_tunnel_offload_set
352 (struct rte_eth_dev *dev,
353 struct rte_eth_l2_tunnel_conf *l2_tunnel,
356 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
357 enum rte_filter_op filter_op,
360 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
361 struct rte_eth_udp_tunnel *udp_tunnel);
362 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
363 struct rte_eth_udp_tunnel *udp_tunnel);
364 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
365 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
368 * Define VF Stats MACRO for Non "cleared on read" register
370 #define UPDATE_VF_STAT(reg, last, cur) \
372 uint32_t latest = IXGBE_READ_REG(hw, reg); \
373 cur += (latest - last) & UINT_MAX; \
377 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
379 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
380 u64 new_msb = IXGBE_READ_REG(hw, msb); \
381 u64 latest = ((new_msb << 32) | new_lsb); \
382 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
386 #define IXGBE_SET_HWSTRIP(h, q) do {\
387 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
388 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
389 (h)->bitmap[idx] |= 1 << bit;\
392 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
393 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
394 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
395 (h)->bitmap[idx] &= ~(1 << bit);\
398 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
399 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
400 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
401 (r) = (h)->bitmap[idx] >> bit & 1;\
404 int ixgbe_logtype_init;
405 int ixgbe_logtype_driver;
408 * The set of PCI devices this driver supports
410 static const struct rte_pci_id pci_id_ixgbe_map[] = {
411 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
412 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
413 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
414 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
415 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
416 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
417 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
418 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
419 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
420 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
421 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
422 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
423 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
424 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
425 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
459 #ifdef RTE_LIBRTE_IXGBE_BYPASS
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
462 { .vendor_id = 0, /* sentinel */ },
466 * The set of PCI devices this driver supports (for 82599 VF)
468 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
479 { .vendor_id = 0, /* sentinel */ },
482 static const struct rte_eth_desc_lim rx_desc_lim = {
483 .nb_max = IXGBE_MAX_RING_DESC,
484 .nb_min = IXGBE_MIN_RING_DESC,
485 .nb_align = IXGBE_RXD_ALIGN,
488 static const struct rte_eth_desc_lim tx_desc_lim = {
489 .nb_max = IXGBE_MAX_RING_DESC,
490 .nb_min = IXGBE_MIN_RING_DESC,
491 .nb_align = IXGBE_TXD_ALIGN,
492 .nb_seg_max = IXGBE_TX_MAX_SEG,
493 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
496 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
497 .dev_configure = ixgbe_dev_configure,
498 .dev_start = ixgbe_dev_start,
499 .dev_stop = ixgbe_dev_stop,
500 .dev_set_link_up = ixgbe_dev_set_link_up,
501 .dev_set_link_down = ixgbe_dev_set_link_down,
502 .dev_close = ixgbe_dev_close,
503 .dev_reset = ixgbe_dev_reset,
504 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
505 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
506 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
507 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
508 .link_update = ixgbe_dev_link_update,
509 .stats_get = ixgbe_dev_stats_get,
510 .xstats_get = ixgbe_dev_xstats_get,
511 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
512 .stats_reset = ixgbe_dev_stats_reset,
513 .xstats_reset = ixgbe_dev_xstats_reset,
514 .xstats_get_names = ixgbe_dev_xstats_get_names,
515 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
516 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
517 .fw_version_get = ixgbe_fw_version_get,
518 .dev_infos_get = ixgbe_dev_info_get,
519 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
520 .mtu_set = ixgbe_dev_mtu_set,
521 .vlan_filter_set = ixgbe_vlan_filter_set,
522 .vlan_tpid_set = ixgbe_vlan_tpid_set,
523 .vlan_offload_set = ixgbe_vlan_offload_set,
524 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
525 .rx_queue_start = ixgbe_dev_rx_queue_start,
526 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
527 .tx_queue_start = ixgbe_dev_tx_queue_start,
528 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
529 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
530 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
531 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
532 .rx_queue_release = ixgbe_dev_rx_queue_release,
533 .rx_queue_count = ixgbe_dev_rx_queue_count,
534 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
535 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
536 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
537 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
538 .tx_queue_release = ixgbe_dev_tx_queue_release,
539 .dev_led_on = ixgbe_dev_led_on,
540 .dev_led_off = ixgbe_dev_led_off,
541 .flow_ctrl_get = ixgbe_flow_ctrl_get,
542 .flow_ctrl_set = ixgbe_flow_ctrl_set,
543 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
544 .mac_addr_add = ixgbe_add_rar,
545 .mac_addr_remove = ixgbe_remove_rar,
546 .mac_addr_set = ixgbe_set_default_mac_addr,
547 .uc_hash_table_set = ixgbe_uc_hash_table_set,
548 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
549 .mirror_rule_set = ixgbe_mirror_rule_set,
550 .mirror_rule_reset = ixgbe_mirror_rule_reset,
551 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
552 .reta_update = ixgbe_dev_rss_reta_update,
553 .reta_query = ixgbe_dev_rss_reta_query,
554 .rss_hash_update = ixgbe_dev_rss_hash_update,
555 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
556 .filter_ctrl = ixgbe_dev_filter_ctrl,
557 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
558 .rxq_info_get = ixgbe_rxq_info_get,
559 .txq_info_get = ixgbe_txq_info_get,
560 .timesync_enable = ixgbe_timesync_enable,
561 .timesync_disable = ixgbe_timesync_disable,
562 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
563 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
564 .get_reg = ixgbe_get_regs,
565 .get_eeprom_length = ixgbe_get_eeprom_length,
566 .get_eeprom = ixgbe_get_eeprom,
567 .set_eeprom = ixgbe_set_eeprom,
568 .get_dcb_info = ixgbe_dev_get_dcb_info,
569 .timesync_adjust_time = ixgbe_timesync_adjust_time,
570 .timesync_read_time = ixgbe_timesync_read_time,
571 .timesync_write_time = ixgbe_timesync_write_time,
572 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
573 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
574 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
575 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
576 .tm_ops_get = ixgbe_tm_ops_get,
580 * dev_ops for virtual function, bare necessities for basic vf
581 * operation have been implemented
583 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
584 .dev_configure = ixgbevf_dev_configure,
585 .dev_start = ixgbevf_dev_start,
586 .dev_stop = ixgbevf_dev_stop,
587 .link_update = ixgbevf_dev_link_update,
588 .stats_get = ixgbevf_dev_stats_get,
589 .xstats_get = ixgbevf_dev_xstats_get,
590 .stats_reset = ixgbevf_dev_stats_reset,
591 .xstats_reset = ixgbevf_dev_stats_reset,
592 .xstats_get_names = ixgbevf_dev_xstats_get_names,
593 .dev_close = ixgbevf_dev_close,
594 .dev_reset = ixgbevf_dev_reset,
595 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
596 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
597 .dev_infos_get = ixgbevf_dev_info_get,
598 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
599 .mtu_set = ixgbevf_dev_set_mtu,
600 .vlan_filter_set = ixgbevf_vlan_filter_set,
601 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
602 .vlan_offload_set = ixgbevf_vlan_offload_set,
603 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
604 .rx_queue_release = ixgbe_dev_rx_queue_release,
605 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
606 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
607 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
608 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
609 .tx_queue_release = ixgbe_dev_tx_queue_release,
610 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
611 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
612 .mac_addr_add = ixgbevf_add_mac_addr,
613 .mac_addr_remove = ixgbevf_remove_mac_addr,
614 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
615 .rxq_info_get = ixgbe_rxq_info_get,
616 .txq_info_get = ixgbe_txq_info_get,
617 .mac_addr_set = ixgbevf_set_default_mac_addr,
618 .get_reg = ixgbevf_get_regs,
619 .reta_update = ixgbe_dev_rss_reta_update,
620 .reta_query = ixgbe_dev_rss_reta_query,
621 .rss_hash_update = ixgbe_dev_rss_hash_update,
622 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
625 /* store statistics names and its offset in stats structure */
626 struct rte_ixgbe_xstats_name_off {
627 char name[RTE_ETH_XSTATS_NAME_SIZE];
631 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
632 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
633 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
634 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
635 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
636 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
637 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
638 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
639 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
640 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
641 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
642 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
643 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
644 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
645 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
646 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
648 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
650 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
651 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
652 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
653 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
654 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
655 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
656 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
657 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
658 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
659 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
660 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
661 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
662 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
663 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
664 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
665 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
666 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
668 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
670 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
671 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
672 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
673 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
675 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
677 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
679 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
681 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
683 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
685 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
688 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
689 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
690 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
692 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
693 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
694 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
695 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
696 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
698 {"rx_fcoe_no_direct_data_placement_ext_buff",
699 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
701 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
703 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
705 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
707 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
709 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
712 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
713 sizeof(rte_ixgbe_stats_strings[0]))
715 /* MACsec statistics */
716 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
717 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
719 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
720 out_pkts_encrypted)},
721 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
722 out_pkts_protected)},
723 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
724 out_octets_encrypted)},
725 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
726 out_octets_protected)},
727 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
729 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
731 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
733 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
734 in_pkts_unknownsci)},
735 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
736 in_octets_decrypted)},
737 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
738 in_octets_validated)},
739 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
741 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
743 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
745 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
747 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
749 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
751 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
753 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
754 in_pkts_notusingsa)},
757 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
758 sizeof(rte_ixgbe_macsec_strings[0]))
760 /* Per-queue statistics */
761 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
762 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
763 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
764 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
765 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
768 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
769 sizeof(rte_ixgbe_rxq_strings[0]))
770 #define IXGBE_NB_RXQ_PRIO_VALUES 8
772 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
773 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
774 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
775 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
779 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
780 sizeof(rte_ixgbe_txq_strings[0]))
781 #define IXGBE_NB_TXQ_PRIO_VALUES 8
783 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
784 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
787 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
788 sizeof(rte_ixgbevf_stats_strings[0]))
791 * Atomically reads the link status information from global
792 * structure rte_eth_dev.
795 * - Pointer to the structure rte_eth_dev to read from.
796 * - Pointer to the buffer to be saved with the link status.
799 * - On success, zero.
800 * - On failure, negative value.
803 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
804 struct rte_eth_link *link)
806 struct rte_eth_link *dst = link;
807 struct rte_eth_link *src = &(dev->data->dev_link);
809 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
810 *(uint64_t *)src) == 0)
817 * Atomically writes the link status information into global
818 * structure rte_eth_dev.
821 * - Pointer to the structure rte_eth_dev to read from.
822 * - Pointer to the buffer to be saved with the link status.
825 * - On success, zero.
826 * - On failure, negative value.
829 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
830 struct rte_eth_link *link)
832 struct rte_eth_link *dst = &(dev->data->dev_link);
833 struct rte_eth_link *src = link;
835 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
836 *(uint64_t *)src) == 0)
843 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
846 ixgbe_is_sfp(struct ixgbe_hw *hw)
848 switch (hw->phy.type) {
849 case ixgbe_phy_sfp_avago:
850 case ixgbe_phy_sfp_ftl:
851 case ixgbe_phy_sfp_intel:
852 case ixgbe_phy_sfp_unknown:
853 case ixgbe_phy_sfp_passive_tyco:
854 case ixgbe_phy_sfp_passive_unknown:
861 static inline int32_t
862 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
867 status = ixgbe_reset_hw(hw);
869 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
870 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
871 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
872 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
873 IXGBE_WRITE_FLUSH(hw);
875 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
876 status = IXGBE_SUCCESS;
881 ixgbe_enable_intr(struct rte_eth_dev *dev)
883 struct ixgbe_interrupt *intr =
884 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
885 struct ixgbe_hw *hw =
886 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
888 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
889 IXGBE_WRITE_FLUSH(hw);
893 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
896 ixgbe_disable_intr(struct ixgbe_hw *hw)
898 PMD_INIT_FUNC_TRACE();
900 if (hw->mac.type == ixgbe_mac_82598EB) {
901 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
903 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
904 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
905 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
907 IXGBE_WRITE_FLUSH(hw);
911 * This function resets queue statistics mapping registers.
912 * From Niantic datasheet, Initialization of Statistics section:
913 * "...if software requires the queue counters, the RQSMR and TQSM registers
914 * must be re-programmed following a device reset.
917 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
921 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
922 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
923 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
929 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
934 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
935 #define NB_QMAP_FIELDS_PER_QSM_REG 4
936 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
938 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
939 struct ixgbe_stat_mapping_registers *stat_mappings =
940 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
941 uint32_t qsmr_mask = 0;
942 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
946 if ((hw->mac.type != ixgbe_mac_82599EB) &&
947 (hw->mac.type != ixgbe_mac_X540) &&
948 (hw->mac.type != ixgbe_mac_X550) &&
949 (hw->mac.type != ixgbe_mac_X550EM_x) &&
950 (hw->mac.type != ixgbe_mac_X550EM_a))
953 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
954 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
957 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
958 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
959 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
962 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
964 /* Now clear any previous stat_idx set */
965 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
967 stat_mappings->tqsm[n] &= ~clearing_mask;
969 stat_mappings->rqsmr[n] &= ~clearing_mask;
971 q_map = (uint32_t)stat_idx;
972 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
973 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
975 stat_mappings->tqsm[n] |= qsmr_mask;
977 stat_mappings->rqsmr[n] |= qsmr_mask;
979 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
980 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
982 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
983 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
985 /* Now write the mapping in the appropriate register */
987 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
988 stat_mappings->rqsmr[n], n);
989 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
991 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
992 stat_mappings->tqsm[n], n);
993 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
999 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1001 struct ixgbe_stat_mapping_registers *stat_mappings =
1002 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1003 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1006 /* write whatever was in stat mapping table to the NIC */
1007 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1009 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1012 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1017 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1020 struct ixgbe_dcb_tc_config *tc;
1021 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1023 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1024 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1025 for (i = 0; i < dcb_max_tc; i++) {
1026 tc = &dcb_config->tc_config[i];
1027 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1028 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1029 (uint8_t)(100/dcb_max_tc + (i & 1));
1030 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1031 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1032 (uint8_t)(100/dcb_max_tc + (i & 1));
1033 tc->pfc = ixgbe_dcb_pfc_disabled;
1036 /* Initialize default user to priority mapping, UPx->TC0 */
1037 tc = &dcb_config->tc_config[0];
1038 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1039 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1040 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1041 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1042 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1044 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1045 dcb_config->pfc_mode_enable = false;
1046 dcb_config->vt_mode = true;
1047 dcb_config->round_robin_enable = false;
1048 /* support all DCB capabilities in 82599 */
1049 dcb_config->support.capabilities = 0xFF;
1051 /*we only support 4 Tcs for X540, X550 */
1052 if (hw->mac.type == ixgbe_mac_X540 ||
1053 hw->mac.type == ixgbe_mac_X550 ||
1054 hw->mac.type == ixgbe_mac_X550EM_x ||
1055 hw->mac.type == ixgbe_mac_X550EM_a) {
1056 dcb_config->num_tcs.pg_tcs = 4;
1057 dcb_config->num_tcs.pfc_tcs = 4;
1062 * Ensure that all locks are released before first NVM or PHY access
1065 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1070 * Phy lock should not fail in this early stage. If this is the case,
1071 * it is due to an improper exit of the application.
1072 * So force the release of the faulty lock. Release of common lock
1073 * is done automatically by swfw_sync function.
1075 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1076 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1077 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1079 ixgbe_release_swfw_semaphore(hw, mask);
1082 * These ones are more tricky since they are common to all ports; but
1083 * swfw_sync retries last long enough (1s) to be almost sure that if
1084 * lock can not be taken it is due to an improper lock of the
1087 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1088 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1089 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1091 ixgbe_release_swfw_semaphore(hw, mask);
1095 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1096 * It returns 0 on success.
1099 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1101 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1102 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1103 struct ixgbe_hw *hw =
1104 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1105 struct ixgbe_vfta *shadow_vfta =
1106 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1107 struct ixgbe_hwstrip *hwstrip =
1108 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1109 struct ixgbe_dcb_config *dcb_config =
1110 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1111 struct ixgbe_filter_info *filter_info =
1112 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1113 struct ixgbe_bw_conf *bw_conf =
1114 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1119 PMD_INIT_FUNC_TRACE();
1121 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1122 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1123 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1124 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1127 * For secondary processes, we don't initialise any further as primary
1128 * has already done this work. Only check we don't need a different
1129 * RX and TX function.
1131 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1132 struct ixgbe_tx_queue *txq;
1133 /* TX queue function in primary, set by last queue initialized
1134 * Tx queue may not initialized by primary process
1136 if (eth_dev->data->tx_queues) {
1137 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1138 ixgbe_set_tx_function(eth_dev, txq);
1140 /* Use default TX function if we get here */
1141 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1142 "Using default TX function.");
1145 ixgbe_set_rx_function(eth_dev);
1150 #ifdef RTE_LIBRTE_SECURITY
1151 /* Initialize security_ctx only for primary process*/
1152 eth_dev->security_ctx = ixgbe_ipsec_ctx_create(eth_dev);
1153 if (eth_dev->security_ctx == NULL)
1157 rte_eth_copy_pci_info(eth_dev, pci_dev);
1159 /* Vendor and Device ID need to be set before init of shared code */
1160 hw->device_id = pci_dev->id.device_id;
1161 hw->vendor_id = pci_dev->id.vendor_id;
1162 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1163 hw->allow_unsupported_sfp = 1;
1165 /* Initialize the shared code (base driver) */
1166 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1167 diag = ixgbe_bypass_init_shared_code(hw);
1169 diag = ixgbe_init_shared_code(hw);
1170 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1172 if (diag != IXGBE_SUCCESS) {
1173 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1177 /* pick up the PCI bus settings for reporting later */
1178 ixgbe_get_bus_info(hw);
1180 /* Unlock any pending hardware semaphore */
1181 ixgbe_swfw_lock_reset(hw);
1183 /* Initialize DCB configuration*/
1184 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1185 ixgbe_dcb_init(hw, dcb_config);
1186 /* Get Hardware Flow Control setting */
1187 hw->fc.requested_mode = ixgbe_fc_full;
1188 hw->fc.current_mode = ixgbe_fc_full;
1189 hw->fc.pause_time = IXGBE_FC_PAUSE;
1190 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1191 hw->fc.low_water[i] = IXGBE_FC_LO;
1192 hw->fc.high_water[i] = IXGBE_FC_HI;
1194 hw->fc.send_xon = 1;
1196 /* Make sure we have a good EEPROM before we read from it */
1197 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1198 if (diag != IXGBE_SUCCESS) {
1199 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1203 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1204 diag = ixgbe_bypass_init_hw(hw);
1206 diag = ixgbe_init_hw(hw);
1207 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1210 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1211 * is called too soon after the kernel driver unbinding/binding occurs.
1212 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1213 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1214 * also called. See ixgbe_identify_phy_82599(). The reason for the
1215 * failure is not known, and only occuts when virtualisation features
1216 * are disabled in the bios. A delay of 100ms was found to be enough by
1217 * trial-and-error, and is doubled to be safe.
1219 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1221 diag = ixgbe_init_hw(hw);
1224 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1225 diag = IXGBE_SUCCESS;
1227 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1228 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1229 "LOM. Please be aware there may be issues associated "
1230 "with your hardware.");
1231 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1232 "please contact your Intel or hardware representative "
1233 "who provided you with this hardware.");
1234 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1235 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1237 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1241 /* Reset the hw statistics */
1242 ixgbe_dev_stats_reset(eth_dev);
1244 /* disable interrupt */
1245 ixgbe_disable_intr(hw);
1247 /* reset mappings for queue statistics hw counters*/
1248 ixgbe_reset_qstat_mappings(hw);
1250 /* Allocate memory for storing MAC addresses */
1251 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1252 hw->mac.num_rar_entries, 0);
1253 if (eth_dev->data->mac_addrs == NULL) {
1255 "Failed to allocate %u bytes needed to store "
1257 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1260 /* Copy the permanent MAC address */
1261 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1262 ð_dev->data->mac_addrs[0]);
1264 /* Allocate memory for storing hash filter MAC addresses */
1265 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1266 IXGBE_VMDQ_NUM_UC_MAC, 0);
1267 if (eth_dev->data->hash_mac_addrs == NULL) {
1269 "Failed to allocate %d bytes needed to store MAC addresses",
1270 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1274 /* initialize the vfta */
1275 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1277 /* initialize the hw strip bitmap*/
1278 memset(hwstrip, 0, sizeof(*hwstrip));
1280 /* initialize PF if max_vfs not zero */
1281 ixgbe_pf_host_init(eth_dev);
1283 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1284 /* let hardware know driver is loaded */
1285 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1286 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1287 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1288 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1289 IXGBE_WRITE_FLUSH(hw);
1291 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1292 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1293 (int) hw->mac.type, (int) hw->phy.type,
1294 (int) hw->phy.sfp_type);
1296 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1297 (int) hw->mac.type, (int) hw->phy.type);
1299 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1300 eth_dev->data->port_id, pci_dev->id.vendor_id,
1301 pci_dev->id.device_id);
1303 rte_intr_callback_register(intr_handle,
1304 ixgbe_dev_interrupt_handler, eth_dev);
1306 /* enable uio/vfio intr/eventfd mapping */
1307 rte_intr_enable(intr_handle);
1309 /* enable support intr */
1310 ixgbe_enable_intr(eth_dev);
1312 /* initialize filter info */
1313 memset(filter_info, 0,
1314 sizeof(struct ixgbe_filter_info));
1316 /* initialize 5tuple filter list */
1317 TAILQ_INIT(&filter_info->fivetuple_list);
1319 /* initialize flow director filter list & hash */
1320 ixgbe_fdir_filter_init(eth_dev);
1322 /* initialize l2 tunnel filter list & hash */
1323 ixgbe_l2_tn_filter_init(eth_dev);
1325 /* initialize flow filter lists */
1326 ixgbe_filterlist_init();
1328 /* initialize bandwidth configuration info */
1329 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1331 /* initialize Traffic Manager configuration */
1332 ixgbe_tm_conf_init(eth_dev);
1338 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1340 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1341 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1342 struct ixgbe_hw *hw;
1344 PMD_INIT_FUNC_TRACE();
1346 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1349 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1351 if (hw->adapter_stopped == 0)
1352 ixgbe_dev_close(eth_dev);
1354 eth_dev->dev_ops = NULL;
1355 eth_dev->rx_pkt_burst = NULL;
1356 eth_dev->tx_pkt_burst = NULL;
1358 /* Unlock any pending hardware semaphore */
1359 ixgbe_swfw_lock_reset(hw);
1361 /* disable uio intr before callback unregister */
1362 rte_intr_disable(intr_handle);
1363 rte_intr_callback_unregister(intr_handle,
1364 ixgbe_dev_interrupt_handler, eth_dev);
1366 /* uninitialize PF if max_vfs not zero */
1367 ixgbe_pf_host_uninit(eth_dev);
1369 rte_free(eth_dev->data->mac_addrs);
1370 eth_dev->data->mac_addrs = NULL;
1372 rte_free(eth_dev->data->hash_mac_addrs);
1373 eth_dev->data->hash_mac_addrs = NULL;
1375 /* remove all the fdir filters & hash */
1376 ixgbe_fdir_filter_uninit(eth_dev);
1378 /* remove all the L2 tunnel filters & hash */
1379 ixgbe_l2_tn_filter_uninit(eth_dev);
1381 /* Remove all ntuple filters of the device */
1382 ixgbe_ntuple_filter_uninit(eth_dev);
1384 /* clear all the filters list */
1385 ixgbe_filterlist_flush();
1387 /* Remove all Traffic Manager configuration */
1388 ixgbe_tm_conf_uninit(eth_dev);
1390 #ifdef RTE_LIBRTE_SECURITY
1391 rte_free(eth_dev->security_ctx);
1397 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1399 struct ixgbe_filter_info *filter_info =
1400 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1401 struct ixgbe_5tuple_filter *p_5tuple;
1403 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1404 TAILQ_REMOVE(&filter_info->fivetuple_list,
1409 memset(filter_info->fivetuple_mask, 0,
1410 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1415 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1417 struct ixgbe_hw_fdir_info *fdir_info =
1418 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1419 struct ixgbe_fdir_filter *fdir_filter;
1421 if (fdir_info->hash_map)
1422 rte_free(fdir_info->hash_map);
1423 if (fdir_info->hash_handle)
1424 rte_hash_free(fdir_info->hash_handle);
1426 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1427 TAILQ_REMOVE(&fdir_info->fdir_list,
1430 rte_free(fdir_filter);
1436 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1438 struct ixgbe_l2_tn_info *l2_tn_info =
1439 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1440 struct ixgbe_l2_tn_filter *l2_tn_filter;
1442 if (l2_tn_info->hash_map)
1443 rte_free(l2_tn_info->hash_map);
1444 if (l2_tn_info->hash_handle)
1445 rte_hash_free(l2_tn_info->hash_handle);
1447 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1448 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1451 rte_free(l2_tn_filter);
1457 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1459 struct ixgbe_hw_fdir_info *fdir_info =
1460 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1461 char fdir_hash_name[RTE_HASH_NAMESIZE];
1462 struct rte_hash_parameters fdir_hash_params = {
1463 .name = fdir_hash_name,
1464 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1465 .key_len = sizeof(union ixgbe_atr_input),
1466 .hash_func = rte_hash_crc,
1467 .hash_func_init_val = 0,
1468 .socket_id = rte_socket_id(),
1471 TAILQ_INIT(&fdir_info->fdir_list);
1472 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1473 "fdir_%s", eth_dev->device->name);
1474 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1475 if (!fdir_info->hash_handle) {
1476 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1479 fdir_info->hash_map = rte_zmalloc("ixgbe",
1480 sizeof(struct ixgbe_fdir_filter *) *
1481 IXGBE_MAX_FDIR_FILTER_NUM,
1483 if (!fdir_info->hash_map) {
1485 "Failed to allocate memory for fdir hash map!");
1488 fdir_info->mask_added = FALSE;
1493 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1495 struct ixgbe_l2_tn_info *l2_tn_info =
1496 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1497 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1498 struct rte_hash_parameters l2_tn_hash_params = {
1499 .name = l2_tn_hash_name,
1500 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1501 .key_len = sizeof(struct ixgbe_l2_tn_key),
1502 .hash_func = rte_hash_crc,
1503 .hash_func_init_val = 0,
1504 .socket_id = rte_socket_id(),
1507 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1508 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1509 "l2_tn_%s", eth_dev->device->name);
1510 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1511 if (!l2_tn_info->hash_handle) {
1512 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1515 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1516 sizeof(struct ixgbe_l2_tn_filter *) *
1517 IXGBE_MAX_L2_TN_FILTER_NUM,
1519 if (!l2_tn_info->hash_map) {
1521 "Failed to allocate memory for L2 TN hash map!");
1524 l2_tn_info->e_tag_en = FALSE;
1525 l2_tn_info->e_tag_fwd_en = FALSE;
1526 l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1531 * Negotiate mailbox API version with the PF.
1532 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1533 * Then we try to negotiate starting with the most recent one.
1534 * If all negotiation attempts fail, then we will proceed with
1535 * the default one (ixgbe_mbox_api_10).
1538 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1542 /* start with highest supported, proceed down */
1543 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1550 i != RTE_DIM(sup_ver) &&
1551 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1557 generate_random_mac_addr(struct ether_addr *mac_addr)
1561 /* Set Organizationally Unique Identifier (OUI) prefix. */
1562 mac_addr->addr_bytes[0] = 0x00;
1563 mac_addr->addr_bytes[1] = 0x09;
1564 mac_addr->addr_bytes[2] = 0xC0;
1565 /* Force indication of locally assigned MAC address. */
1566 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1567 /* Generate the last 3 bytes of the MAC address with a random number. */
1568 random = rte_rand();
1569 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1573 * Virtual Function device init
1576 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1580 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1581 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1582 struct ixgbe_hw *hw =
1583 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1584 struct ixgbe_vfta *shadow_vfta =
1585 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1586 struct ixgbe_hwstrip *hwstrip =
1587 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1588 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1590 PMD_INIT_FUNC_TRACE();
1592 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1593 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1594 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1596 /* for secondary processes, we don't initialise any further as primary
1597 * has already done this work. Only check we don't need a different
1600 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1601 struct ixgbe_tx_queue *txq;
1602 /* TX queue function in primary, set by last queue initialized
1603 * Tx queue may not initialized by primary process
1605 if (eth_dev->data->tx_queues) {
1606 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1607 ixgbe_set_tx_function(eth_dev, txq);
1609 /* Use default TX function if we get here */
1610 PMD_INIT_LOG(NOTICE,
1611 "No TX queues configured yet. Using default TX function.");
1614 ixgbe_set_rx_function(eth_dev);
1619 rte_eth_copy_pci_info(eth_dev, pci_dev);
1621 hw->device_id = pci_dev->id.device_id;
1622 hw->vendor_id = pci_dev->id.vendor_id;
1623 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1625 /* initialize the vfta */
1626 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1628 /* initialize the hw strip bitmap*/
1629 memset(hwstrip, 0, sizeof(*hwstrip));
1631 /* Initialize the shared code (base driver) */
1632 diag = ixgbe_init_shared_code(hw);
1633 if (diag != IXGBE_SUCCESS) {
1634 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1638 /* init_mailbox_params */
1639 hw->mbx.ops.init_params(hw);
1641 /* Reset the hw statistics */
1642 ixgbevf_dev_stats_reset(eth_dev);
1644 /* Disable the interrupts for VF */
1645 ixgbevf_intr_disable(hw);
1647 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1648 diag = hw->mac.ops.reset_hw(hw);
1651 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1652 * the underlying PF driver has not assigned a MAC address to the VF.
1653 * In this case, assign a random MAC address.
1655 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1656 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1660 /* negotiate mailbox API version to use with the PF. */
1661 ixgbevf_negotiate_api(hw);
1663 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1664 ixgbevf_get_queues(hw, &tcs, &tc);
1666 /* Allocate memory for storing MAC addresses */
1667 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1668 hw->mac.num_rar_entries, 0);
1669 if (eth_dev->data->mac_addrs == NULL) {
1671 "Failed to allocate %u bytes needed to store "
1673 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1677 /* Generate a random MAC address, if none was assigned by PF. */
1678 if (is_zero_ether_addr(perm_addr)) {
1679 generate_random_mac_addr(perm_addr);
1680 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1682 rte_free(eth_dev->data->mac_addrs);
1683 eth_dev->data->mac_addrs = NULL;
1686 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1687 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1688 "%02x:%02x:%02x:%02x:%02x:%02x",
1689 perm_addr->addr_bytes[0],
1690 perm_addr->addr_bytes[1],
1691 perm_addr->addr_bytes[2],
1692 perm_addr->addr_bytes[3],
1693 perm_addr->addr_bytes[4],
1694 perm_addr->addr_bytes[5]);
1697 /* Copy the permanent MAC address */
1698 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1700 /* reset the hardware with the new settings */
1701 diag = hw->mac.ops.start_hw(hw);
1707 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1711 rte_intr_callback_register(intr_handle,
1712 ixgbevf_dev_interrupt_handler, eth_dev);
1713 rte_intr_enable(intr_handle);
1714 ixgbevf_intr_enable(hw);
1716 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1717 eth_dev->data->port_id, pci_dev->id.vendor_id,
1718 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1723 /* Virtual Function device uninit */
1726 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1728 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1729 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1730 struct ixgbe_hw *hw;
1732 PMD_INIT_FUNC_TRACE();
1734 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1737 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1739 if (hw->adapter_stopped == 0)
1740 ixgbevf_dev_close(eth_dev);
1742 eth_dev->dev_ops = NULL;
1743 eth_dev->rx_pkt_burst = NULL;
1744 eth_dev->tx_pkt_burst = NULL;
1746 /* Disable the interrupts for VF */
1747 ixgbevf_intr_disable(hw);
1749 rte_free(eth_dev->data->mac_addrs);
1750 eth_dev->data->mac_addrs = NULL;
1752 rte_intr_disable(intr_handle);
1753 rte_intr_callback_unregister(intr_handle,
1754 ixgbevf_dev_interrupt_handler, eth_dev);
1759 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1760 struct rte_pci_device *pci_dev)
1762 return rte_eth_dev_pci_generic_probe(pci_dev,
1763 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1766 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1768 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1771 static struct rte_pci_driver rte_ixgbe_pmd = {
1772 .id_table = pci_id_ixgbe_map,
1773 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1774 RTE_PCI_DRV_IOVA_AS_VA,
1775 .probe = eth_ixgbe_pci_probe,
1776 .remove = eth_ixgbe_pci_remove,
1779 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1780 struct rte_pci_device *pci_dev)
1782 return rte_eth_dev_pci_generic_probe(pci_dev,
1783 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1786 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1788 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1792 * virtual function driver struct
1794 static struct rte_pci_driver rte_ixgbevf_pmd = {
1795 .id_table = pci_id_ixgbevf_map,
1796 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1797 .probe = eth_ixgbevf_pci_probe,
1798 .remove = eth_ixgbevf_pci_remove,
1802 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1804 struct ixgbe_hw *hw =
1805 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1806 struct ixgbe_vfta *shadow_vfta =
1807 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1812 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1813 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1814 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1819 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1821 /* update local VFTA copy */
1822 shadow_vfta->vfta[vid_idx] = vfta;
1828 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1831 ixgbe_vlan_hw_strip_enable(dev, queue);
1833 ixgbe_vlan_hw_strip_disable(dev, queue);
1837 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1838 enum rte_vlan_type vlan_type,
1841 struct ixgbe_hw *hw =
1842 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1847 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1848 qinq &= IXGBE_DMATXCTL_GDV;
1850 switch (vlan_type) {
1851 case ETH_VLAN_TYPE_INNER:
1853 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1854 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1855 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1856 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1857 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1858 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1859 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1862 PMD_DRV_LOG(ERR, "Inner type is not supported"
1866 case ETH_VLAN_TYPE_OUTER:
1868 /* Only the high 16-bits is valid */
1869 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1870 IXGBE_EXVET_VET_EXT_SHIFT);
1872 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1873 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1874 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1875 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1876 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1877 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1878 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1884 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1892 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1894 struct ixgbe_hw *hw =
1895 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1898 PMD_INIT_FUNC_TRACE();
1900 /* Filter Table Disable */
1901 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1902 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1904 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1908 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1910 struct ixgbe_hw *hw =
1911 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1912 struct ixgbe_vfta *shadow_vfta =
1913 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1917 PMD_INIT_FUNC_TRACE();
1919 /* Filter Table Enable */
1920 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1921 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1922 vlnctrl |= IXGBE_VLNCTRL_VFE;
1924 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1926 /* write whatever is in local vfta copy */
1927 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1928 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1932 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1934 struct ixgbe_hwstrip *hwstrip =
1935 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1936 struct ixgbe_rx_queue *rxq;
1938 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1942 IXGBE_SET_HWSTRIP(hwstrip, queue);
1944 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1946 if (queue >= dev->data->nb_rx_queues)
1949 rxq = dev->data->rx_queues[queue];
1952 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1954 rxq->vlan_flags = PKT_RX_VLAN;
1958 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1960 struct ixgbe_hw *hw =
1961 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1964 PMD_INIT_FUNC_TRACE();
1966 if (hw->mac.type == ixgbe_mac_82598EB) {
1967 /* No queue level support */
1968 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1972 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1973 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1974 ctrl &= ~IXGBE_RXDCTL_VME;
1975 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1977 /* record those setting for HW strip per queue */
1978 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1982 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1984 struct ixgbe_hw *hw =
1985 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1988 PMD_INIT_FUNC_TRACE();
1990 if (hw->mac.type == ixgbe_mac_82598EB) {
1991 /* No queue level supported */
1992 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1996 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1997 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1998 ctrl |= IXGBE_RXDCTL_VME;
1999 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2001 /* record those setting for HW strip per queue */
2002 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2006 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2008 struct ixgbe_hw *hw =
2009 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2012 struct ixgbe_rx_queue *rxq;
2014 PMD_INIT_FUNC_TRACE();
2016 if (hw->mac.type == ixgbe_mac_82598EB) {
2017 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2018 ctrl &= ~IXGBE_VLNCTRL_VME;
2019 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2021 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2022 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2023 rxq = dev->data->rx_queues[i];
2024 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2025 ctrl &= ~IXGBE_RXDCTL_VME;
2026 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2028 /* record those setting for HW strip per queue */
2029 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2035 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2037 struct ixgbe_hw *hw =
2038 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2041 struct ixgbe_rx_queue *rxq;
2043 PMD_INIT_FUNC_TRACE();
2045 if (hw->mac.type == ixgbe_mac_82598EB) {
2046 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2047 ctrl |= IXGBE_VLNCTRL_VME;
2048 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2050 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2051 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2052 rxq = dev->data->rx_queues[i];
2053 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2054 ctrl |= IXGBE_RXDCTL_VME;
2055 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2057 /* record those setting for HW strip per queue */
2058 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2064 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2066 struct ixgbe_hw *hw =
2067 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2070 PMD_INIT_FUNC_TRACE();
2072 /* DMATXCTRL: Geric Double VLAN Disable */
2073 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2074 ctrl &= ~IXGBE_DMATXCTL_GDV;
2075 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2077 /* CTRL_EXT: Global Double VLAN Disable */
2078 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2079 ctrl &= ~IXGBE_EXTENDED_VLAN;
2080 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2085 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2087 struct ixgbe_hw *hw =
2088 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2091 PMD_INIT_FUNC_TRACE();
2093 /* DMATXCTRL: Geric Double VLAN Enable */
2094 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2095 ctrl |= IXGBE_DMATXCTL_GDV;
2096 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2098 /* CTRL_EXT: Global Double VLAN Enable */
2099 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2100 ctrl |= IXGBE_EXTENDED_VLAN;
2101 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2103 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2104 if (hw->mac.type == ixgbe_mac_X550 ||
2105 hw->mac.type == ixgbe_mac_X550EM_x ||
2106 hw->mac.type == ixgbe_mac_X550EM_a) {
2107 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2108 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2109 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2113 * VET EXT field in the EXVET register = 0x8100 by default
2114 * So no need to change. Same to VT field of DMATXCTL register
2119 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2121 if (mask & ETH_VLAN_STRIP_MASK) {
2122 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2123 ixgbe_vlan_hw_strip_enable_all(dev);
2125 ixgbe_vlan_hw_strip_disable_all(dev);
2128 if (mask & ETH_VLAN_FILTER_MASK) {
2129 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2130 ixgbe_vlan_hw_filter_enable(dev);
2132 ixgbe_vlan_hw_filter_disable(dev);
2135 if (mask & ETH_VLAN_EXTEND_MASK) {
2136 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2137 ixgbe_vlan_hw_extend_enable(dev);
2139 ixgbe_vlan_hw_extend_disable(dev);
2146 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2148 struct ixgbe_hw *hw =
2149 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2151 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2153 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2154 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2158 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2160 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2165 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2168 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2174 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2175 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2176 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2177 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2182 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2184 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2185 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2186 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2187 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2189 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2190 /* check multi-queue mode */
2191 switch (dev_conf->rxmode.mq_mode) {
2192 case ETH_MQ_RX_VMDQ_DCB:
2193 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2195 case ETH_MQ_RX_VMDQ_DCB_RSS:
2196 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2197 PMD_INIT_LOG(ERR, "SRIOV active,"
2198 " unsupported mq_mode rx %d.",
2199 dev_conf->rxmode.mq_mode);
2202 case ETH_MQ_RX_VMDQ_RSS:
2203 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2204 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2205 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2206 PMD_INIT_LOG(ERR, "SRIOV is active,"
2207 " invalid queue number"
2208 " for VMDQ RSS, allowed"
2209 " value are 1, 2 or 4.");
2213 case ETH_MQ_RX_VMDQ_ONLY:
2214 case ETH_MQ_RX_NONE:
2215 /* if nothing mq mode configure, use default scheme */
2216 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2218 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2219 /* SRIOV only works in VMDq enable mode */
2220 PMD_INIT_LOG(ERR, "SRIOV is active,"
2221 " wrong mq_mode rx %d.",
2222 dev_conf->rxmode.mq_mode);
2226 switch (dev_conf->txmode.mq_mode) {
2227 case ETH_MQ_TX_VMDQ_DCB:
2228 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2229 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2231 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2232 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2236 /* check valid queue number */
2237 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2238 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2239 PMD_INIT_LOG(ERR, "SRIOV is active,"
2240 " nb_rx_q=%d nb_tx_q=%d queue number"
2241 " must be less than or equal to %d.",
2243 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2247 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2248 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2252 /* check configuration for vmdb+dcb mode */
2253 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2254 const struct rte_eth_vmdq_dcb_conf *conf;
2256 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2257 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2258 IXGBE_VMDQ_DCB_NB_QUEUES);
2261 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2262 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2263 conf->nb_queue_pools == ETH_32_POOLS)) {
2264 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2265 " nb_queue_pools must be %d or %d.",
2266 ETH_16_POOLS, ETH_32_POOLS);
2270 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2271 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2273 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2274 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2275 IXGBE_VMDQ_DCB_NB_QUEUES);
2278 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2279 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2280 conf->nb_queue_pools == ETH_32_POOLS)) {
2281 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2282 " nb_queue_pools != %d and"
2283 " nb_queue_pools != %d.",
2284 ETH_16_POOLS, ETH_32_POOLS);
2289 /* For DCB mode check our configuration before we go further */
2290 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2291 const struct rte_eth_dcb_rx_conf *conf;
2293 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2294 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2295 IXGBE_DCB_NB_QUEUES);
2298 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2299 if (!(conf->nb_tcs == ETH_4_TCS ||
2300 conf->nb_tcs == ETH_8_TCS)) {
2301 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2302 " and nb_tcs != %d.",
2303 ETH_4_TCS, ETH_8_TCS);
2308 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2309 const struct rte_eth_dcb_tx_conf *conf;
2311 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2312 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2313 IXGBE_DCB_NB_QUEUES);
2316 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2317 if (!(conf->nb_tcs == ETH_4_TCS ||
2318 conf->nb_tcs == ETH_8_TCS)) {
2319 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2320 " and nb_tcs != %d.",
2321 ETH_4_TCS, ETH_8_TCS);
2327 * When DCB/VT is off, maximum number of queues changes,
2328 * except for 82598EB, which remains constant.
2330 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2331 hw->mac.type != ixgbe_mac_82598EB) {
2332 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2334 "Neither VT nor DCB are enabled, "
2336 IXGBE_NONE_MODE_TX_NB_QUEUES);
2345 ixgbe_dev_configure(struct rte_eth_dev *dev)
2347 struct ixgbe_interrupt *intr =
2348 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2349 struct ixgbe_adapter *adapter =
2350 (struct ixgbe_adapter *)dev->data->dev_private;
2353 PMD_INIT_FUNC_TRACE();
2354 /* multipe queue mode checking */
2355 ret = ixgbe_check_mq_mode(dev);
2357 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2362 /* set flag to update link status after init */
2363 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2366 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2367 * allocation or vector Rx preconditions we will reset it.
2369 adapter->rx_bulk_alloc_allowed = true;
2370 adapter->rx_vec_allowed = true;
2376 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2378 struct ixgbe_hw *hw =
2379 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2380 struct ixgbe_interrupt *intr =
2381 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2384 /* only set up it on X550EM_X */
2385 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2386 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2387 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2388 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2389 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2390 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2395 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2396 uint16_t tx_rate, uint64_t q_msk)
2398 struct ixgbe_hw *hw;
2399 struct ixgbe_vf_info *vfinfo;
2400 struct rte_eth_link link;
2401 uint8_t nb_q_per_pool;
2402 uint32_t queue_stride;
2403 uint32_t queue_idx, idx = 0, vf_idx;
2405 uint16_t total_rate = 0;
2406 struct rte_pci_device *pci_dev;
2408 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2409 rte_eth_link_get_nowait(dev->data->port_id, &link);
2411 if (vf >= pci_dev->max_vfs)
2414 if (tx_rate > link.link_speed)
2420 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2421 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2422 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2423 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2424 queue_idx = vf * queue_stride;
2425 queue_end = queue_idx + nb_q_per_pool - 1;
2426 if (queue_end >= hw->mac.max_tx_queues)
2430 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2433 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2435 total_rate += vfinfo[vf_idx].tx_rate[idx];
2441 /* Store tx_rate for this vf. */
2442 for (idx = 0; idx < nb_q_per_pool; idx++) {
2443 if (((uint64_t)0x1 << idx) & q_msk) {
2444 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2445 vfinfo[vf].tx_rate[idx] = tx_rate;
2446 total_rate += tx_rate;
2450 if (total_rate > dev->data->dev_link.link_speed) {
2451 /* Reset stored TX rate of the VF if it causes exceed
2454 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2458 /* Set RTTBCNRC of each queue/pool for vf X */
2459 for (; queue_idx <= queue_end; queue_idx++) {
2461 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2469 * Configure device link speed and setup link.
2470 * It returns 0 on success.
2473 ixgbe_dev_start(struct rte_eth_dev *dev)
2475 struct ixgbe_hw *hw =
2476 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2477 struct ixgbe_vf_info *vfinfo =
2478 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2479 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2480 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2481 uint32_t intr_vector = 0;
2482 int err, link_up = 0, negotiate = 0;
2487 uint32_t *link_speeds;
2488 struct ixgbe_tm_conf *tm_conf =
2489 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2491 PMD_INIT_FUNC_TRACE();
2493 /* IXGBE devices don't support:
2494 * - half duplex (checked afterwards for valid speeds)
2495 * - fixed speed: TODO implement
2497 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2499 "Invalid link_speeds for port %u, fix speed not supported",
2500 dev->data->port_id);
2504 /* disable uio/vfio intr/eventfd mapping */
2505 rte_intr_disable(intr_handle);
2508 hw->adapter_stopped = 0;
2509 ixgbe_stop_adapter(hw);
2511 /* reinitialize adapter
2512 * this calls reset and start
2514 status = ixgbe_pf_reset_hw(hw);
2517 hw->mac.ops.start_hw(hw);
2518 hw->mac.get_link_status = true;
2520 /* configure PF module if SRIOV enabled */
2521 ixgbe_pf_host_configure(dev);
2523 ixgbe_dev_phy_intr_setup(dev);
2525 /* check and configure queue intr-vector mapping */
2526 if ((rte_intr_cap_multiple(intr_handle) ||
2527 !RTE_ETH_DEV_SRIOV(dev).active) &&
2528 dev->data->dev_conf.intr_conf.rxq != 0) {
2529 intr_vector = dev->data->nb_rx_queues;
2530 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2531 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2532 IXGBE_MAX_INTR_QUEUE_NUM);
2535 if (rte_intr_efd_enable(intr_handle, intr_vector))
2539 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2540 intr_handle->intr_vec =
2541 rte_zmalloc("intr_vec",
2542 dev->data->nb_rx_queues * sizeof(int), 0);
2543 if (intr_handle->intr_vec == NULL) {
2544 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2545 " intr_vec", dev->data->nb_rx_queues);
2550 /* confiugre msix for sleep until rx interrupt */
2551 ixgbe_configure_msix(dev);
2553 /* initialize transmission unit */
2554 ixgbe_dev_tx_init(dev);
2556 /* This can fail when allocating mbufs for descriptor rings */
2557 err = ixgbe_dev_rx_init(dev);
2559 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2563 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2564 ETH_VLAN_EXTEND_MASK;
2565 err = ixgbe_vlan_offload_set(dev, mask);
2567 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2571 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2572 /* Enable vlan filtering for VMDq */
2573 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2576 /* Configure DCB hw */
2577 ixgbe_configure_dcb(dev);
2579 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2580 err = ixgbe_fdir_configure(dev);
2585 /* Restore vf rate limit */
2586 if (vfinfo != NULL) {
2587 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2588 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2589 if (vfinfo[vf].tx_rate[idx] != 0)
2590 ixgbe_set_vf_rate_limit(
2592 vfinfo[vf].tx_rate[idx],
2596 ixgbe_restore_statistics_mapping(dev);
2598 err = ixgbe_dev_rxtx_start(dev);
2600 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2604 /* Skip link setup if loopback mode is enabled for 82599. */
2605 if (hw->mac.type == ixgbe_mac_82599EB &&
2606 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2607 goto skip_link_setup;
2609 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2610 err = hw->mac.ops.setup_sfp(hw);
2615 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2616 /* Turn on the copper */
2617 ixgbe_set_phy_power(hw, true);
2619 /* Turn on the laser */
2620 ixgbe_enable_tx_laser(hw);
2623 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2626 dev->data->dev_link.link_status = link_up;
2628 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2632 link_speeds = &dev->data->dev_conf.link_speeds;
2633 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2634 ETH_LINK_SPEED_10G)) {
2635 PMD_INIT_LOG(ERR, "Invalid link setting");
2640 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2641 switch (hw->mac.type) {
2642 case ixgbe_mac_82598EB:
2643 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2645 case ixgbe_mac_82599EB:
2646 case ixgbe_mac_X540:
2647 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2649 case ixgbe_mac_X550:
2650 case ixgbe_mac_X550EM_x:
2651 case ixgbe_mac_X550EM_a:
2652 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2655 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2658 if (*link_speeds & ETH_LINK_SPEED_10G)
2659 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2660 if (*link_speeds & ETH_LINK_SPEED_1G)
2661 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2662 if (*link_speeds & ETH_LINK_SPEED_100M)
2663 speed |= IXGBE_LINK_SPEED_100_FULL;
2666 err = ixgbe_setup_link(hw, speed, link_up);
2672 if (rte_intr_allow_others(intr_handle)) {
2673 /* check if lsc interrupt is enabled */
2674 if (dev->data->dev_conf.intr_conf.lsc != 0)
2675 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2677 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2678 ixgbe_dev_macsec_interrupt_setup(dev);
2680 rte_intr_callback_unregister(intr_handle,
2681 ixgbe_dev_interrupt_handler, dev);
2682 if (dev->data->dev_conf.intr_conf.lsc != 0)
2683 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2684 " no intr multiplex");
2687 /* check if rxq interrupt is enabled */
2688 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2689 rte_intr_dp_is_en(intr_handle))
2690 ixgbe_dev_rxq_interrupt_setup(dev);
2692 /* enable uio/vfio intr/eventfd mapping */
2693 rte_intr_enable(intr_handle);
2695 /* resume enabled intr since hw reset */
2696 ixgbe_enable_intr(dev);
2697 ixgbe_l2_tunnel_conf(dev);
2698 ixgbe_filter_restore(dev);
2700 if (tm_conf->root && !tm_conf->committed)
2701 PMD_DRV_LOG(WARNING,
2702 "please call hierarchy_commit() "
2703 "before starting the port");
2708 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2709 ixgbe_dev_clear_queues(dev);
2714 * Stop device: disable rx and tx functions to allow for reconfiguring.
2717 ixgbe_dev_stop(struct rte_eth_dev *dev)
2719 struct rte_eth_link link;
2720 struct ixgbe_hw *hw =
2721 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2722 struct ixgbe_vf_info *vfinfo =
2723 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2724 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2725 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2727 struct ixgbe_tm_conf *tm_conf =
2728 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2730 PMD_INIT_FUNC_TRACE();
2732 /* disable interrupts */
2733 ixgbe_disable_intr(hw);
2736 ixgbe_pf_reset_hw(hw);
2737 hw->adapter_stopped = 0;
2740 ixgbe_stop_adapter(hw);
2742 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2743 vfinfo[vf].clear_to_send = false;
2745 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2746 /* Turn off the copper */
2747 ixgbe_set_phy_power(hw, false);
2749 /* Turn off the laser */
2750 ixgbe_disable_tx_laser(hw);
2753 ixgbe_dev_clear_queues(dev);
2755 /* Clear stored conf */
2756 dev->data->scattered_rx = 0;
2759 /* Clear recorded link status */
2760 memset(&link, 0, sizeof(link));
2761 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2763 if (!rte_intr_allow_others(intr_handle))
2764 /* resume to the default handler */
2765 rte_intr_callback_register(intr_handle,
2766 ixgbe_dev_interrupt_handler,
2769 /* Clean datapath event and queue/vec mapping */
2770 rte_intr_efd_disable(intr_handle);
2771 if (intr_handle->intr_vec != NULL) {
2772 rte_free(intr_handle->intr_vec);
2773 intr_handle->intr_vec = NULL;
2776 /* reset hierarchy commit */
2777 tm_conf->committed = false;
2781 * Set device link up: enable tx.
2784 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2786 struct ixgbe_hw *hw =
2787 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2788 if (hw->mac.type == ixgbe_mac_82599EB) {
2789 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2790 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2791 /* Not suported in bypass mode */
2792 PMD_INIT_LOG(ERR, "Set link up is not supported "
2793 "by device id 0x%x", hw->device_id);
2799 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2800 /* Turn on the copper */
2801 ixgbe_set_phy_power(hw, true);
2803 /* Turn on the laser */
2804 ixgbe_enable_tx_laser(hw);
2811 * Set device link down: disable tx.
2814 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2816 struct ixgbe_hw *hw =
2817 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2818 if (hw->mac.type == ixgbe_mac_82599EB) {
2819 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2820 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2821 /* Not suported in bypass mode */
2822 PMD_INIT_LOG(ERR, "Set link down is not supported "
2823 "by device id 0x%x", hw->device_id);
2829 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2830 /* Turn off the copper */
2831 ixgbe_set_phy_power(hw, false);
2833 /* Turn off the laser */
2834 ixgbe_disable_tx_laser(hw);
2841 * Reset and stop device.
2844 ixgbe_dev_close(struct rte_eth_dev *dev)
2846 struct ixgbe_hw *hw =
2847 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2849 PMD_INIT_FUNC_TRACE();
2851 ixgbe_pf_reset_hw(hw);
2853 ixgbe_dev_stop(dev);
2854 hw->adapter_stopped = 1;
2856 ixgbe_dev_free_queues(dev);
2858 ixgbe_disable_pcie_master(hw);
2860 /* reprogram the RAR[0] in case user changed it. */
2861 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2868 ixgbe_dev_reset(struct rte_eth_dev *dev)
2872 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2873 * its VF to make them align with it. The detailed notification
2874 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2875 * To avoid unexpected behavior in VF, currently reset of PF with
2876 * SR-IOV activation is not supported. It might be supported later.
2878 if (dev->data->sriov.active)
2881 ret = eth_ixgbe_dev_uninit(dev);
2885 ret = eth_ixgbe_dev_init(dev);
2891 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2892 struct ixgbe_hw_stats *hw_stats,
2893 struct ixgbe_macsec_stats *macsec_stats,
2894 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2895 uint64_t *total_qprc, uint64_t *total_qprdc)
2897 uint32_t bprc, lxon, lxoff, total;
2898 uint32_t delta_gprc = 0;
2900 /* Workaround for RX byte count not including CRC bytes when CRC
2901 * strip is enabled. CRC bytes are removed from counters when crc_strip
2904 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2905 IXGBE_HLREG0_RXCRCSTRP);
2907 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2908 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2909 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2910 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2912 for (i = 0; i < 8; i++) {
2913 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2915 /* global total per queue */
2916 hw_stats->mpc[i] += mp;
2917 /* Running comprehensive total for stats display */
2918 *total_missed_rx += hw_stats->mpc[i];
2919 if (hw->mac.type == ixgbe_mac_82598EB) {
2920 hw_stats->rnbc[i] +=
2921 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2922 hw_stats->pxonrxc[i] +=
2923 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2924 hw_stats->pxoffrxc[i] +=
2925 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2927 hw_stats->pxonrxc[i] +=
2928 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2929 hw_stats->pxoffrxc[i] +=
2930 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2931 hw_stats->pxon2offc[i] +=
2932 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2934 hw_stats->pxontxc[i] +=
2935 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2936 hw_stats->pxofftxc[i] +=
2937 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2939 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2940 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2941 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2942 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2944 delta_gprc += delta_qprc;
2946 hw_stats->qprc[i] += delta_qprc;
2947 hw_stats->qptc[i] += delta_qptc;
2949 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2950 hw_stats->qbrc[i] +=
2951 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2953 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2955 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2956 hw_stats->qbtc[i] +=
2957 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2959 hw_stats->qprdc[i] += delta_qprdc;
2960 *total_qprdc += hw_stats->qprdc[i];
2962 *total_qprc += hw_stats->qprc[i];
2963 *total_qbrc += hw_stats->qbrc[i];
2965 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2966 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2967 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2970 * An errata states that gprc actually counts good + missed packets:
2971 * Workaround to set gprc to summated queue packet receives
2973 hw_stats->gprc = *total_qprc;
2975 if (hw->mac.type != ixgbe_mac_82598EB) {
2976 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2977 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2978 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2979 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2980 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2981 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2982 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2983 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2985 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2986 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2987 /* 82598 only has a counter in the high register */
2988 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2989 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2990 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2992 uint64_t old_tpr = hw_stats->tpr;
2994 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2995 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2998 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3000 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3001 hw_stats->gptc += delta_gptc;
3002 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3003 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3006 * Workaround: mprc hardware is incorrectly counting
3007 * broadcasts, so for now we subtract those.
3009 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3010 hw_stats->bprc += bprc;
3011 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3012 if (hw->mac.type == ixgbe_mac_82598EB)
3013 hw_stats->mprc -= bprc;
3015 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3016 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3017 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3018 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3019 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3020 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3022 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3023 hw_stats->lxontxc += lxon;
3024 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3025 hw_stats->lxofftxc += lxoff;
3026 total = lxon + lxoff;
3028 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3029 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3030 hw_stats->gptc -= total;
3031 hw_stats->mptc -= total;
3032 hw_stats->ptc64 -= total;
3033 hw_stats->gotc -= total * ETHER_MIN_LEN;
3035 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3036 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3037 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3038 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3039 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3040 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3041 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3042 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3043 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3044 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3045 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3046 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3047 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3048 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3049 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3050 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3051 /* Only read FCOE on 82599 */
3052 if (hw->mac.type != ixgbe_mac_82598EB) {
3053 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3054 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3055 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3056 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3057 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3060 /* Flow Director Stats registers */
3061 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3062 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3064 /* MACsec Stats registers */
3065 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3066 macsec_stats->out_pkts_encrypted +=
3067 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3068 macsec_stats->out_pkts_protected +=
3069 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3070 macsec_stats->out_octets_encrypted +=
3071 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3072 macsec_stats->out_octets_protected +=
3073 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3074 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3075 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3076 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3077 macsec_stats->in_pkts_unknownsci +=
3078 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3079 macsec_stats->in_octets_decrypted +=
3080 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3081 macsec_stats->in_octets_validated +=
3082 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3083 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3084 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3085 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3086 for (i = 0; i < 2; i++) {
3087 macsec_stats->in_pkts_ok +=
3088 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3089 macsec_stats->in_pkts_invalid +=
3090 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3091 macsec_stats->in_pkts_notvalid +=
3092 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3094 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3095 macsec_stats->in_pkts_notusingsa +=
3096 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3100 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3103 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3105 struct ixgbe_hw *hw =
3106 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3107 struct ixgbe_hw_stats *hw_stats =
3108 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3109 struct ixgbe_macsec_stats *macsec_stats =
3110 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3111 dev->data->dev_private);
3112 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3115 total_missed_rx = 0;
3120 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3121 &total_qbrc, &total_qprc, &total_qprdc);
3126 /* Fill out the rte_eth_stats statistics structure */
3127 stats->ipackets = total_qprc;
3128 stats->ibytes = total_qbrc;
3129 stats->opackets = hw_stats->gptc;
3130 stats->obytes = hw_stats->gotc;
3132 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3133 stats->q_ipackets[i] = hw_stats->qprc[i];
3134 stats->q_opackets[i] = hw_stats->qptc[i];
3135 stats->q_ibytes[i] = hw_stats->qbrc[i];
3136 stats->q_obytes[i] = hw_stats->qbtc[i];
3137 stats->q_errors[i] = hw_stats->qprdc[i];
3141 stats->imissed = total_missed_rx;
3142 stats->ierrors = hw_stats->crcerrs +
3159 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3161 struct ixgbe_hw_stats *stats =
3162 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3164 /* HW registers are cleared on read */
3165 ixgbe_dev_stats_get(dev, NULL);
3167 /* Reset software totals */
3168 memset(stats, 0, sizeof(*stats));
3171 /* This function calculates the number of xstats based on the current config */
3173 ixgbe_xstats_calc_num(void) {
3174 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3175 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3176 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3179 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3180 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3182 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3183 unsigned stat, i, count;
3185 if (xstats_names != NULL) {
3188 /* Note: limit >= cnt_stats checked upstream
3189 * in rte_eth_xstats_names()
3192 /* Extended stats from ixgbe_hw_stats */
3193 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3194 snprintf(xstats_names[count].name,
3195 sizeof(xstats_names[count].name),
3197 rte_ixgbe_stats_strings[i].name);
3202 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3203 snprintf(xstats_names[count].name,
3204 sizeof(xstats_names[count].name),
3206 rte_ixgbe_macsec_strings[i].name);
3210 /* RX Priority Stats */
3211 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3212 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3213 snprintf(xstats_names[count].name,
3214 sizeof(xstats_names[count].name),
3215 "rx_priority%u_%s", i,
3216 rte_ixgbe_rxq_strings[stat].name);
3221 /* TX Priority Stats */
3222 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3223 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3224 snprintf(xstats_names[count].name,
3225 sizeof(xstats_names[count].name),
3226 "tx_priority%u_%s", i,
3227 rte_ixgbe_txq_strings[stat].name);
3235 static int ixgbe_dev_xstats_get_names_by_id(
3236 struct rte_eth_dev *dev,
3237 struct rte_eth_xstat_name *xstats_names,
3238 const uint64_t *ids,
3242 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3243 unsigned int stat, i, count;
3245 if (xstats_names != NULL) {
3248 /* Note: limit >= cnt_stats checked upstream
3249 * in rte_eth_xstats_names()
3252 /* Extended stats from ixgbe_hw_stats */
3253 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3254 snprintf(xstats_names[count].name,
3255 sizeof(xstats_names[count].name),
3257 rte_ixgbe_stats_strings[i].name);
3262 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3263 snprintf(xstats_names[count].name,
3264 sizeof(xstats_names[count].name),
3266 rte_ixgbe_macsec_strings[i].name);
3270 /* RX Priority Stats */
3271 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3272 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3273 snprintf(xstats_names[count].name,
3274 sizeof(xstats_names[count].name),
3275 "rx_priority%u_%s", i,
3276 rte_ixgbe_rxq_strings[stat].name);
3281 /* TX Priority Stats */
3282 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3283 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3284 snprintf(xstats_names[count].name,
3285 sizeof(xstats_names[count].name),
3286 "tx_priority%u_%s", i,
3287 rte_ixgbe_txq_strings[stat].name);
3296 uint16_t size = ixgbe_xstats_calc_num();
3297 struct rte_eth_xstat_name xstats_names_copy[size];
3299 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3302 for (i = 0; i < limit; i++) {
3303 if (ids[i] >= size) {
3304 PMD_INIT_LOG(ERR, "id value isn't valid");
3307 strcpy(xstats_names[i].name,
3308 xstats_names_copy[ids[i]].name);
3313 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3314 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3318 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3321 if (xstats_names != NULL)
3322 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3323 snprintf(xstats_names[i].name,
3324 sizeof(xstats_names[i].name),
3325 "%s", rte_ixgbevf_stats_strings[i].name);
3326 return IXGBEVF_NB_XSTATS;
3330 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3333 struct ixgbe_hw *hw =
3334 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3335 struct ixgbe_hw_stats *hw_stats =
3336 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3337 struct ixgbe_macsec_stats *macsec_stats =
3338 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3339 dev->data->dev_private);
3340 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3341 unsigned i, stat, count = 0;
3343 count = ixgbe_xstats_calc_num();
3348 total_missed_rx = 0;
3353 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3354 &total_qbrc, &total_qprc, &total_qprdc);
3356 /* If this is a reset xstats is NULL, and we have cleared the
3357 * registers by reading them.
3362 /* Extended stats from ixgbe_hw_stats */
3364 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3365 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3366 rte_ixgbe_stats_strings[i].offset);
3367 xstats[count].id = count;
3372 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3373 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3374 rte_ixgbe_macsec_strings[i].offset);
3375 xstats[count].id = count;
3379 /* RX Priority Stats */
3380 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3381 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3382 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3383 rte_ixgbe_rxq_strings[stat].offset +
3384 (sizeof(uint64_t) * i));
3385 xstats[count].id = count;
3390 /* TX Priority Stats */
3391 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3392 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3393 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3394 rte_ixgbe_txq_strings[stat].offset +
3395 (sizeof(uint64_t) * i));
3396 xstats[count].id = count;
3404 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3405 uint64_t *values, unsigned int n)
3408 struct ixgbe_hw *hw =
3409 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3410 struct ixgbe_hw_stats *hw_stats =
3411 IXGBE_DEV_PRIVATE_TO_STATS(
3412 dev->data->dev_private);
3413 struct ixgbe_macsec_stats *macsec_stats =
3414 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3415 dev->data->dev_private);
3416 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3417 unsigned int i, stat, count = 0;
3419 count = ixgbe_xstats_calc_num();
3421 if (!ids && n < count)
3424 total_missed_rx = 0;
3429 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3430 &total_missed_rx, &total_qbrc, &total_qprc,
3433 /* If this is a reset xstats is NULL, and we have cleared the
3434 * registers by reading them.
3436 if (!ids && !values)
3439 /* Extended stats from ixgbe_hw_stats */
3441 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3442 values[count] = *(uint64_t *)(((char *)hw_stats) +
3443 rte_ixgbe_stats_strings[i].offset);
3448 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3449 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3450 rte_ixgbe_macsec_strings[i].offset);
3454 /* RX Priority Stats */
3455 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3456 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3458 *(uint64_t *)(((char *)hw_stats) +
3459 rte_ixgbe_rxq_strings[stat].offset +
3460 (sizeof(uint64_t) * i));
3465 /* TX Priority Stats */
3466 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3467 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3469 *(uint64_t *)(((char *)hw_stats) +
3470 rte_ixgbe_txq_strings[stat].offset +
3471 (sizeof(uint64_t) * i));
3479 uint16_t size = ixgbe_xstats_calc_num();
3480 uint64_t values_copy[size];
3482 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3484 for (i = 0; i < n; i++) {
3485 if (ids[i] >= size) {
3486 PMD_INIT_LOG(ERR, "id value isn't valid");
3489 values[i] = values_copy[ids[i]];
3495 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3497 struct ixgbe_hw_stats *stats =
3498 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3499 struct ixgbe_macsec_stats *macsec_stats =
3500 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3501 dev->data->dev_private);
3503 unsigned count = ixgbe_xstats_calc_num();
3505 /* HW registers are cleared on read */
3506 ixgbe_dev_xstats_get(dev, NULL, count);
3508 /* Reset software totals */
3509 memset(stats, 0, sizeof(*stats));
3510 memset(macsec_stats, 0, sizeof(*macsec_stats));
3514 ixgbevf_update_stats(struct rte_eth_dev *dev)
3516 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3517 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3518 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3520 /* Good Rx packet, include VF loopback */
3521 UPDATE_VF_STAT(IXGBE_VFGPRC,
3522 hw_stats->last_vfgprc, hw_stats->vfgprc);
3524 /* Good Rx octets, include VF loopback */
3525 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3526 hw_stats->last_vfgorc, hw_stats->vfgorc);
3528 /* Good Tx packet, include VF loopback */
3529 UPDATE_VF_STAT(IXGBE_VFGPTC,
3530 hw_stats->last_vfgptc, hw_stats->vfgptc);
3532 /* Good Tx octets, include VF loopback */
3533 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3534 hw_stats->last_vfgotc, hw_stats->vfgotc);
3536 /* Rx Multicst Packet */
3537 UPDATE_VF_STAT(IXGBE_VFMPRC,
3538 hw_stats->last_vfmprc, hw_stats->vfmprc);
3542 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3545 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3546 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3549 if (n < IXGBEVF_NB_XSTATS)
3550 return IXGBEVF_NB_XSTATS;
3552 ixgbevf_update_stats(dev);
3557 /* Extended stats */
3558 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3560 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3561 rte_ixgbevf_stats_strings[i].offset);
3564 return IXGBEVF_NB_XSTATS;
3568 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3570 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3571 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3573 ixgbevf_update_stats(dev);
3578 stats->ipackets = hw_stats->vfgprc;
3579 stats->ibytes = hw_stats->vfgorc;
3580 stats->opackets = hw_stats->vfgptc;
3581 stats->obytes = hw_stats->vfgotc;
3586 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3588 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3589 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3591 /* Sync HW register to the last stats */
3592 ixgbevf_dev_stats_get(dev, NULL);
3594 /* reset HW current stats*/
3595 hw_stats->vfgprc = 0;
3596 hw_stats->vfgorc = 0;
3597 hw_stats->vfgptc = 0;
3598 hw_stats->vfgotc = 0;
3602 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3604 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3605 u16 eeprom_verh, eeprom_verl;
3609 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3610 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3612 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3613 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3615 ret += 1; /* add the size of '\0' */
3616 if (fw_size < (u32)ret)
3623 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3625 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3626 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3627 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3629 dev_info->pci_dev = pci_dev;
3630 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3631 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3632 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3634 * When DCB/VT is off, maximum number of queues changes,
3635 * except for 82598EB, which remains constant.
3637 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3638 hw->mac.type != ixgbe_mac_82598EB)
3639 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3641 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3642 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3643 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3644 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3645 dev_info->max_vfs = pci_dev->max_vfs;
3646 if (hw->mac.type == ixgbe_mac_82598EB)
3647 dev_info->max_vmdq_pools = ETH_16_POOLS;
3649 dev_info->max_vmdq_pools = ETH_64_POOLS;
3650 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3651 dev_info->rx_offload_capa =
3652 DEV_RX_OFFLOAD_VLAN_STRIP |
3653 DEV_RX_OFFLOAD_IPV4_CKSUM |
3654 DEV_RX_OFFLOAD_UDP_CKSUM |
3655 DEV_RX_OFFLOAD_TCP_CKSUM;
3658 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3661 if ((hw->mac.type == ixgbe_mac_82599EB ||
3662 hw->mac.type == ixgbe_mac_X540) &&
3663 !RTE_ETH_DEV_SRIOV(dev).active)
3664 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3666 if (hw->mac.type == ixgbe_mac_82599EB ||
3667 hw->mac.type == ixgbe_mac_X540)
3668 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3670 if (hw->mac.type == ixgbe_mac_X550 ||
3671 hw->mac.type == ixgbe_mac_X550EM_x ||
3672 hw->mac.type == ixgbe_mac_X550EM_a)
3673 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3675 dev_info->tx_offload_capa =
3676 DEV_TX_OFFLOAD_VLAN_INSERT |
3677 DEV_TX_OFFLOAD_IPV4_CKSUM |
3678 DEV_TX_OFFLOAD_UDP_CKSUM |
3679 DEV_TX_OFFLOAD_TCP_CKSUM |
3680 DEV_TX_OFFLOAD_SCTP_CKSUM |
3681 DEV_TX_OFFLOAD_TCP_TSO;
3683 if (hw->mac.type == ixgbe_mac_82599EB ||
3684 hw->mac.type == ixgbe_mac_X540)
3685 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3687 if (hw->mac.type == ixgbe_mac_X550 ||
3688 hw->mac.type == ixgbe_mac_X550EM_x ||
3689 hw->mac.type == ixgbe_mac_X550EM_a)
3690 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3692 #ifdef RTE_LIBRTE_SECURITY
3693 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_SECURITY;
3694 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
3697 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3699 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3700 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3701 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3703 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3707 dev_info->default_txconf = (struct rte_eth_txconf) {
3709 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3710 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3711 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3713 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3714 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3715 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3716 ETH_TXQ_FLAGS_NOOFFLOADS,
3719 dev_info->rx_desc_lim = rx_desc_lim;
3720 dev_info->tx_desc_lim = tx_desc_lim;
3722 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3723 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3724 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3726 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3727 if (hw->mac.type == ixgbe_mac_X540 ||
3728 hw->mac.type == ixgbe_mac_X540_vf ||
3729 hw->mac.type == ixgbe_mac_X550 ||
3730 hw->mac.type == ixgbe_mac_X550_vf) {
3731 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3733 if (hw->mac.type == ixgbe_mac_X550) {
3734 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3735 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3739 static const uint32_t *
3740 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3742 static const uint32_t ptypes[] = {
3743 /* For non-vec functions,
3744 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3745 * for vec functions,
3746 * refers to _recv_raw_pkts_vec().
3750 RTE_PTYPE_L3_IPV4_EXT,
3752 RTE_PTYPE_L3_IPV6_EXT,
3756 RTE_PTYPE_TUNNEL_IP,
3757 RTE_PTYPE_INNER_L3_IPV6,
3758 RTE_PTYPE_INNER_L3_IPV6_EXT,
3759 RTE_PTYPE_INNER_L4_TCP,
3760 RTE_PTYPE_INNER_L4_UDP,
3764 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3765 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3766 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3767 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3770 #if defined(RTE_ARCH_X86)
3771 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3772 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3779 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3780 struct rte_eth_dev_info *dev_info)
3782 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3783 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3785 dev_info->pci_dev = pci_dev;
3786 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3787 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3788 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3789 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3790 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3791 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3792 dev_info->max_vfs = pci_dev->max_vfs;
3793 if (hw->mac.type == ixgbe_mac_82598EB)
3794 dev_info->max_vmdq_pools = ETH_16_POOLS;
3796 dev_info->max_vmdq_pools = ETH_64_POOLS;
3797 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3798 DEV_RX_OFFLOAD_IPV4_CKSUM |
3799 DEV_RX_OFFLOAD_UDP_CKSUM |
3800 DEV_RX_OFFLOAD_TCP_CKSUM;
3801 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3802 DEV_TX_OFFLOAD_IPV4_CKSUM |
3803 DEV_TX_OFFLOAD_UDP_CKSUM |
3804 DEV_TX_OFFLOAD_TCP_CKSUM |
3805 DEV_TX_OFFLOAD_SCTP_CKSUM |
3806 DEV_TX_OFFLOAD_TCP_TSO;
3808 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3810 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3811 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3812 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3814 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3818 dev_info->default_txconf = (struct rte_eth_txconf) {
3820 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3821 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3822 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3824 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3825 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3826 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3827 ETH_TXQ_FLAGS_NOOFFLOADS,
3830 dev_info->rx_desc_lim = rx_desc_lim;
3831 dev_info->tx_desc_lim = tx_desc_lim;
3835 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3836 int *link_up, int wait_to_complete)
3839 * for a quick link status checking, wait_to_compelet == 0,
3840 * skip PF link status checking
3842 bool no_pflink_check = wait_to_complete == 0;
3843 struct ixgbe_mbx_info *mbx = &hw->mbx;
3844 struct ixgbe_mac_info *mac = &hw->mac;
3845 uint32_t links_reg, in_msg;
3848 /* If we were hit with a reset drop the link */
3849 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3850 mac->get_link_status = true;
3852 if (!mac->get_link_status)
3855 /* if link status is down no point in checking to see if pf is up */
3856 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3857 if (!(links_reg & IXGBE_LINKS_UP))
3860 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3861 * before the link status is correct
3863 if (mac->type == ixgbe_mac_82599_vf) {
3866 for (i = 0; i < 5; i++) {
3868 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3870 if (!(links_reg & IXGBE_LINKS_UP))
3875 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3876 case IXGBE_LINKS_SPEED_10G_82599:
3877 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3878 if (hw->mac.type >= ixgbe_mac_X550) {
3879 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3880 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3883 case IXGBE_LINKS_SPEED_1G_82599:
3884 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3886 case IXGBE_LINKS_SPEED_100_82599:
3887 *speed = IXGBE_LINK_SPEED_100_FULL;
3888 if (hw->mac.type == ixgbe_mac_X550) {
3889 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3890 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3893 case IXGBE_LINKS_SPEED_10_X550EM_A:
3894 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3895 /* Since Reserved in older MAC's */
3896 if (hw->mac.type >= ixgbe_mac_X550)
3897 *speed = IXGBE_LINK_SPEED_10_FULL;
3900 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3903 if (no_pflink_check) {
3904 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3905 mac->get_link_status = true;
3907 mac->get_link_status = false;
3911 /* if the read failed it could just be a mailbox collision, best wait
3912 * until we are called again and don't report an error
3914 if (mbx->ops.read(hw, &in_msg, 1, 0))
3917 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3918 /* msg is not CTS and is NACK we must have lost CTS status */
3919 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3924 /* the pf is talking, if we timed out in the past we reinit */
3925 if (!mbx->timeout) {
3930 /* if we passed all the tests above then the link is up and we no
3931 * longer need to check for link
3933 mac->get_link_status = false;
3936 *link_up = !mac->get_link_status;
3940 /* return 0 means link status changed, -1 means not changed */
3942 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3943 int wait_to_complete, int vf)
3945 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3946 struct rte_eth_link link, old;
3947 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3948 struct ixgbe_interrupt *intr =
3949 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3954 bool autoneg = false;
3956 link.link_status = ETH_LINK_DOWN;
3957 link.link_speed = 0;
3958 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3959 link.link_autoneg = ETH_LINK_AUTONEG;
3960 memset(&old, 0, sizeof(old));
3961 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3963 hw->mac.get_link_status = true;
3965 if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3966 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3967 speed = hw->phy.autoneg_advertised;
3969 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3970 ixgbe_setup_link(hw, speed, true);
3973 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3974 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3978 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3980 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3983 link.link_speed = ETH_SPEED_NUM_100M;
3984 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3985 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3986 if (link.link_status == old.link_status)
3992 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3993 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3994 if (link.link_status == old.link_status)
3998 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3999 link.link_status = ETH_LINK_UP;
4000 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4002 switch (link_speed) {
4004 case IXGBE_LINK_SPEED_UNKNOWN:
4005 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4006 link.link_speed = ETH_SPEED_NUM_100M;
4009 case IXGBE_LINK_SPEED_100_FULL:
4010 link.link_speed = ETH_SPEED_NUM_100M;
4013 case IXGBE_LINK_SPEED_1GB_FULL:
4014 link.link_speed = ETH_SPEED_NUM_1G;
4017 case IXGBE_LINK_SPEED_2_5GB_FULL:
4018 link.link_speed = ETH_SPEED_NUM_2_5G;
4021 case IXGBE_LINK_SPEED_5GB_FULL:
4022 link.link_speed = ETH_SPEED_NUM_5G;
4025 case IXGBE_LINK_SPEED_10GB_FULL:
4026 link.link_speed = ETH_SPEED_NUM_10G;
4029 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4031 if (link.link_status == old.link_status)
4038 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4040 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4044 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4046 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4050 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4052 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4055 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4056 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4057 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4061 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4063 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4066 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4067 fctrl &= (~IXGBE_FCTRL_UPE);
4068 if (dev->data->all_multicast == 1)
4069 fctrl |= IXGBE_FCTRL_MPE;
4071 fctrl &= (~IXGBE_FCTRL_MPE);
4072 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4076 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4078 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4081 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4082 fctrl |= IXGBE_FCTRL_MPE;
4083 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4087 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4089 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4092 if (dev->data->promiscuous == 1)
4093 return; /* must remain in all_multicast mode */
4095 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4096 fctrl &= (~IXGBE_FCTRL_MPE);
4097 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4101 * It clears the interrupt causes and enables the interrupt.
4102 * It will be called once only during nic initialized.
4105 * Pointer to struct rte_eth_dev.
4107 * Enable or Disable.
4110 * - On success, zero.
4111 * - On failure, a negative value.
4114 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4116 struct ixgbe_interrupt *intr =
4117 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4119 ixgbe_dev_link_status_print(dev);
4121 intr->mask |= IXGBE_EICR_LSC;
4123 intr->mask &= ~IXGBE_EICR_LSC;
4129 * It clears the interrupt causes and enables the interrupt.
4130 * It will be called once only during nic initialized.
4133 * Pointer to struct rte_eth_dev.
4136 * - On success, zero.
4137 * - On failure, a negative value.
4140 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4142 struct ixgbe_interrupt *intr =
4143 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4145 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4151 * It clears the interrupt causes and enables the interrupt.
4152 * It will be called once only during nic initialized.
4155 * Pointer to struct rte_eth_dev.
4158 * - On success, zero.
4159 * - On failure, a negative value.
4162 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4164 struct ixgbe_interrupt *intr =
4165 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4167 intr->mask |= IXGBE_EICR_LINKSEC;
4173 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4176 * Pointer to struct rte_eth_dev.
4179 * - On success, zero.
4180 * - On failure, a negative value.
4183 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4186 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4187 struct ixgbe_interrupt *intr =
4188 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4190 /* clear all cause mask */
4191 ixgbe_disable_intr(hw);
4193 /* read-on-clear nic registers here */
4194 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4195 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4199 /* set flag for async link update */
4200 if (eicr & IXGBE_EICR_LSC)
4201 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4203 if (eicr & IXGBE_EICR_MAILBOX)
4204 intr->flags |= IXGBE_FLAG_MAILBOX;
4206 if (eicr & IXGBE_EICR_LINKSEC)
4207 intr->flags |= IXGBE_FLAG_MACSEC;
4209 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4210 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4211 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4212 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4218 * It gets and then prints the link status.
4221 * Pointer to struct rte_eth_dev.
4224 * - On success, zero.
4225 * - On failure, a negative value.
4228 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4230 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4231 struct rte_eth_link link;
4233 memset(&link, 0, sizeof(link));
4234 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4235 if (link.link_status) {
4236 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4237 (int)(dev->data->port_id),
4238 (unsigned)link.link_speed,
4239 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4240 "full-duplex" : "half-duplex");
4242 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4243 (int)(dev->data->port_id));
4245 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4246 pci_dev->addr.domain,
4248 pci_dev->addr.devid,
4249 pci_dev->addr.function);
4253 * It executes link_update after knowing an interrupt occurred.
4256 * Pointer to struct rte_eth_dev.
4259 * - On success, zero.
4260 * - On failure, a negative value.
4263 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4264 struct rte_intr_handle *intr_handle)
4266 struct ixgbe_interrupt *intr =
4267 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4269 struct rte_eth_link link;
4270 struct ixgbe_hw *hw =
4271 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4273 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4275 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4276 ixgbe_pf_mbx_process(dev);
4277 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4280 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4281 ixgbe_handle_lasi(hw);
4282 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4285 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4286 /* get the link status before link update, for predicting later */
4287 memset(&link, 0, sizeof(link));
4288 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4290 ixgbe_dev_link_update(dev, 0);
4293 if (!link.link_status)
4294 /* handle it 1 sec later, wait it being stable */
4295 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4296 /* likely to down */
4298 /* handle it 4 sec later, wait it being stable */
4299 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4301 ixgbe_dev_link_status_print(dev);
4302 if (rte_eal_alarm_set(timeout * 1000,
4303 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4304 PMD_DRV_LOG(ERR, "Error setting alarm");
4306 /* remember original mask */
4307 intr->mask_original = intr->mask;
4308 /* only disable lsc interrupt */
4309 intr->mask &= ~IXGBE_EIMS_LSC;
4313 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4314 ixgbe_enable_intr(dev);
4315 rte_intr_enable(intr_handle);
4321 * Interrupt handler which shall be registered for alarm callback for delayed
4322 * handling specific interrupt to wait for the stable nic state. As the
4323 * NIC interrupt state is not stable for ixgbe after link is just down,
4324 * it needs to wait 4 seconds to get the stable status.
4327 * Pointer to interrupt handle.
4329 * The address of parameter (struct rte_eth_dev *) regsitered before.
4335 ixgbe_dev_interrupt_delayed_handler(void *param)
4337 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4338 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4339 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4340 struct ixgbe_interrupt *intr =
4341 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4342 struct ixgbe_hw *hw =
4343 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4346 ixgbe_disable_intr(hw);
4348 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4349 if (eicr & IXGBE_EICR_MAILBOX)
4350 ixgbe_pf_mbx_process(dev);
4352 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4353 ixgbe_handle_lasi(hw);
4354 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4357 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4358 ixgbe_dev_link_update(dev, 0);
4359 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4360 ixgbe_dev_link_status_print(dev);
4361 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4365 if (intr->flags & IXGBE_FLAG_MACSEC) {
4366 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4368 intr->flags &= ~IXGBE_FLAG_MACSEC;
4371 /* restore original mask */
4372 intr->mask = intr->mask_original;
4373 intr->mask_original = 0;
4375 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4376 ixgbe_enable_intr(dev);
4377 rte_intr_enable(intr_handle);
4381 * Interrupt handler triggered by NIC for handling
4382 * specific interrupt.
4385 * Pointer to interrupt handle.
4387 * The address of parameter (struct rte_eth_dev *) regsitered before.
4393 ixgbe_dev_interrupt_handler(void *param)
4395 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4397 ixgbe_dev_interrupt_get_status(dev);
4398 ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4402 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4404 struct ixgbe_hw *hw;
4406 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4407 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4411 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4413 struct ixgbe_hw *hw;
4415 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4416 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4420 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4422 struct ixgbe_hw *hw;
4428 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4430 fc_conf->pause_time = hw->fc.pause_time;
4431 fc_conf->high_water = hw->fc.high_water[0];
4432 fc_conf->low_water = hw->fc.low_water[0];
4433 fc_conf->send_xon = hw->fc.send_xon;
4434 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4437 * Return rx_pause status according to actual setting of
4440 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4441 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4447 * Return tx_pause status according to actual setting of
4450 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4451 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4456 if (rx_pause && tx_pause)
4457 fc_conf->mode = RTE_FC_FULL;
4459 fc_conf->mode = RTE_FC_RX_PAUSE;
4461 fc_conf->mode = RTE_FC_TX_PAUSE;
4463 fc_conf->mode = RTE_FC_NONE;
4469 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4471 struct ixgbe_hw *hw;
4473 uint32_t rx_buf_size;
4474 uint32_t max_high_water;
4476 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4483 PMD_INIT_FUNC_TRACE();
4485 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4486 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4487 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4490 * At least reserve one Ethernet frame for watermark
4491 * high_water/low_water in kilo bytes for ixgbe
4493 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4494 if ((fc_conf->high_water > max_high_water) ||
4495 (fc_conf->high_water < fc_conf->low_water)) {
4496 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4497 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4501 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4502 hw->fc.pause_time = fc_conf->pause_time;
4503 hw->fc.high_water[0] = fc_conf->high_water;
4504 hw->fc.low_water[0] = fc_conf->low_water;
4505 hw->fc.send_xon = fc_conf->send_xon;
4506 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4508 err = ixgbe_fc_enable(hw);
4510 /* Not negotiated is not an error case */
4511 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4513 /* check if we want to forward MAC frames - driver doesn't have native
4514 * capability to do that, so we'll write the registers ourselves */
4516 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4518 /* set or clear MFLCN.PMCF bit depending on configuration */
4519 if (fc_conf->mac_ctrl_frame_fwd != 0)
4520 mflcn |= IXGBE_MFLCN_PMCF;
4522 mflcn &= ~IXGBE_MFLCN_PMCF;
4524 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4525 IXGBE_WRITE_FLUSH(hw);
4530 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4535 * ixgbe_pfc_enable_generic - Enable flow control
4536 * @hw: pointer to hardware structure
4537 * @tc_num: traffic class number
4538 * Enable flow control according to the current settings.
4541 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4544 uint32_t mflcn_reg, fccfg_reg;
4546 uint32_t fcrtl, fcrth;
4550 /* Validate the water mark configuration */
4551 if (!hw->fc.pause_time) {
4552 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4556 /* Low water mark of zero causes XOFF floods */
4557 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4558 /* High/Low water can not be 0 */
4559 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4560 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4561 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4565 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4566 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4567 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4571 /* Negotiate the fc mode to use */
4572 ixgbe_fc_autoneg(hw);
4574 /* Disable any previous flow control settings */
4575 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4576 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4578 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4579 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4581 switch (hw->fc.current_mode) {
4584 * If the count of enabled RX Priority Flow control >1,
4585 * and the TX pause can not be disabled
4588 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4589 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4590 if (reg & IXGBE_FCRTH_FCEN)
4594 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4596 case ixgbe_fc_rx_pause:
4598 * Rx Flow control is enabled and Tx Flow control is
4599 * disabled by software override. Since there really
4600 * isn't a way to advertise that we are capable of RX
4601 * Pause ONLY, we will advertise that we support both
4602 * symmetric and asymmetric Rx PAUSE. Later, we will
4603 * disable the adapter's ability to send PAUSE frames.
4605 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4607 * If the count of enabled RX Priority Flow control >1,
4608 * and the TX pause can not be disabled
4611 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4612 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4613 if (reg & IXGBE_FCRTH_FCEN)
4617 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4619 case ixgbe_fc_tx_pause:
4621 * Tx Flow control is enabled, and Rx Flow control is
4622 * disabled by software override.
4624 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4627 /* Flow control (both Rx and Tx) is enabled by SW override. */
4628 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4629 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4632 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4633 ret_val = IXGBE_ERR_CONFIG;
4637 /* Set 802.3x based flow control settings. */
4638 mflcn_reg |= IXGBE_MFLCN_DPF;
4639 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4640 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4642 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4643 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4644 hw->fc.high_water[tc_num]) {
4645 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4646 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4647 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4649 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4651 * In order to prevent Tx hangs when the internal Tx
4652 * switch is enabled we must set the high water mark
4653 * to the maximum FCRTH value. This allows the Tx
4654 * switch to function even under heavy Rx workloads.
4656 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4658 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4660 /* Configure pause time (2 TCs per register) */
4661 reg = hw->fc.pause_time * 0x00010001;
4662 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4663 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4665 /* Configure flow control refresh threshold value */
4666 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4673 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4675 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4676 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4678 if (hw->mac.type != ixgbe_mac_82598EB) {
4679 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4685 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4688 uint32_t rx_buf_size;
4689 uint32_t max_high_water;
4691 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4692 struct ixgbe_hw *hw =
4693 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4694 struct ixgbe_dcb_config *dcb_config =
4695 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4697 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4704 PMD_INIT_FUNC_TRACE();
4706 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4707 tc_num = map[pfc_conf->priority];
4708 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4709 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4711 * At least reserve one Ethernet frame for watermark
4712 * high_water/low_water in kilo bytes for ixgbe
4714 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4715 if ((pfc_conf->fc.high_water > max_high_water) ||
4716 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4717 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4718 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4722 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4723 hw->fc.pause_time = pfc_conf->fc.pause_time;
4724 hw->fc.send_xon = pfc_conf->fc.send_xon;
4725 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4726 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4728 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4730 /* Not negotiated is not an error case */
4731 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4734 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4739 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4740 struct rte_eth_rss_reta_entry64 *reta_conf,
4743 uint16_t i, sp_reta_size;
4746 uint16_t idx, shift;
4747 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4750 PMD_INIT_FUNC_TRACE();
4752 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4753 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4758 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4759 if (reta_size != sp_reta_size) {
4760 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4761 "(%d) doesn't match the number hardware can supported "
4762 "(%d)", reta_size, sp_reta_size);
4766 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4767 idx = i / RTE_RETA_GROUP_SIZE;
4768 shift = i % RTE_RETA_GROUP_SIZE;
4769 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4773 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4774 if (mask == IXGBE_4_BIT_MASK)
4777 r = IXGBE_READ_REG(hw, reta_reg);
4778 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4779 if (mask & (0x1 << j))
4780 reta |= reta_conf[idx].reta[shift + j] <<
4783 reta |= r & (IXGBE_8_BIT_MASK <<
4786 IXGBE_WRITE_REG(hw, reta_reg, reta);
4793 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4794 struct rte_eth_rss_reta_entry64 *reta_conf,
4797 uint16_t i, sp_reta_size;
4800 uint16_t idx, shift;
4801 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4804 PMD_INIT_FUNC_TRACE();
4805 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4806 if (reta_size != sp_reta_size) {
4807 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4808 "(%d) doesn't match the number hardware can supported "
4809 "(%d)", reta_size, sp_reta_size);
4813 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4814 idx = i / RTE_RETA_GROUP_SIZE;
4815 shift = i % RTE_RETA_GROUP_SIZE;
4816 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4821 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4822 reta = IXGBE_READ_REG(hw, reta_reg);
4823 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4824 if (mask & (0x1 << j))
4825 reta_conf[idx].reta[shift + j] =
4826 ((reta >> (CHAR_BIT * j)) &
4835 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4836 uint32_t index, uint32_t pool)
4838 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4839 uint32_t enable_addr = 1;
4841 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4846 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4848 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4850 ixgbe_clear_rar(hw, index);
4854 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4856 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4858 ixgbe_remove_rar(dev, 0);
4860 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4864 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4866 if (strcmp(dev->device->driver->name, drv->driver.name))
4873 is_ixgbe_supported(struct rte_eth_dev *dev)
4875 return is_device_supported(dev, &rte_ixgbe_pmd);
4879 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4883 struct ixgbe_hw *hw;
4884 struct rte_eth_dev_info dev_info;
4885 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4886 struct rte_eth_dev_data *dev_data = dev->data;
4888 ixgbe_dev_info_get(dev, &dev_info);
4890 /* check that mtu is within the allowed range */
4891 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4894 /* If device is started, refuse mtu that requires the support of
4895 * scattered packets when this feature has not been enabled before.
4897 if (dev_data->dev_started && !dev_data->scattered_rx &&
4898 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4899 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4900 PMD_INIT_LOG(ERR, "Stop port first.");
4904 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4905 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4907 /* switch to jumbo mode if needed */
4908 if (frame_size > ETHER_MAX_LEN) {
4909 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4910 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4912 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4913 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4915 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4917 /* update max frame size */
4918 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4920 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4921 maxfrs &= 0x0000FFFF;
4922 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4923 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4929 * Virtual Function operations
4932 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4934 PMD_INIT_FUNC_TRACE();
4936 /* Clear interrupt mask to stop from interrupts being generated */
4937 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4939 IXGBE_WRITE_FLUSH(hw);
4943 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4945 PMD_INIT_FUNC_TRACE();
4947 /* VF enable interrupt autoclean */
4948 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4949 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4950 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4952 IXGBE_WRITE_FLUSH(hw);
4956 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4958 struct rte_eth_conf *conf = &dev->data->dev_conf;
4959 struct ixgbe_adapter *adapter =
4960 (struct ixgbe_adapter *)dev->data->dev_private;
4962 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4963 dev->data->port_id);
4966 * VF has no ability to enable/disable HW CRC
4967 * Keep the persistent behavior the same as Host PF
4969 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4970 if (!conf->rxmode.hw_strip_crc) {
4971 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4972 conf->rxmode.hw_strip_crc = 1;
4975 if (conf->rxmode.hw_strip_crc) {
4976 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4977 conf->rxmode.hw_strip_crc = 0;
4982 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4983 * allocation or vector Rx preconditions we will reset it.
4985 adapter->rx_bulk_alloc_allowed = true;
4986 adapter->rx_vec_allowed = true;
4992 ixgbevf_dev_start(struct rte_eth_dev *dev)
4994 struct ixgbe_hw *hw =
4995 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4996 uint32_t intr_vector = 0;
4997 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4998 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5002 PMD_INIT_FUNC_TRACE();
5004 hw->mac.ops.reset_hw(hw);
5005 hw->mac.get_link_status = true;
5007 /* negotiate mailbox API version to use with the PF. */
5008 ixgbevf_negotiate_api(hw);
5010 ixgbevf_dev_tx_init(dev);
5012 /* This can fail when allocating mbufs for descriptor rings */
5013 err = ixgbevf_dev_rx_init(dev);
5015 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5016 ixgbe_dev_clear_queues(dev);
5021 ixgbevf_set_vfta_all(dev, 1);
5024 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5025 ETH_VLAN_EXTEND_MASK;
5026 err = ixgbevf_vlan_offload_set(dev, mask);
5028 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5029 ixgbe_dev_clear_queues(dev);
5033 ixgbevf_dev_rxtx_start(dev);
5035 /* check and configure queue intr-vector mapping */
5036 if (dev->data->dev_conf.intr_conf.rxq != 0) {
5037 /* According to datasheet, only vector 0/1/2 can be used,
5038 * now only one vector is used for Rx queue
5041 if (rte_intr_efd_enable(intr_handle, intr_vector))
5045 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5046 intr_handle->intr_vec =
5047 rte_zmalloc("intr_vec",
5048 dev->data->nb_rx_queues * sizeof(int), 0);
5049 if (intr_handle->intr_vec == NULL) {
5050 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5051 " intr_vec", dev->data->nb_rx_queues);
5055 ixgbevf_configure_msix(dev);
5057 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5058 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5059 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5060 * is not cleared, it will fail when following rte_intr_enable( ) tries
5061 * to map Rx queue interrupt to other VFIO vectors.
5062 * So clear uio/vfio intr/evevnfd first to avoid failure.
5064 rte_intr_disable(intr_handle);
5066 rte_intr_enable(intr_handle);
5068 /* Re-enable interrupt for VF */
5069 ixgbevf_intr_enable(hw);
5075 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5077 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5078 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5079 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5081 PMD_INIT_FUNC_TRACE();
5083 ixgbevf_intr_disable(hw);
5085 hw->adapter_stopped = 1;
5086 ixgbe_stop_adapter(hw);
5089 * Clear what we set, but we still keep shadow_vfta to
5090 * restore after device starts
5092 ixgbevf_set_vfta_all(dev, 0);
5094 /* Clear stored conf */
5095 dev->data->scattered_rx = 0;
5097 ixgbe_dev_clear_queues(dev);
5099 /* Clean datapath event and queue/vec mapping */
5100 rte_intr_efd_disable(intr_handle);
5101 if (intr_handle->intr_vec != NULL) {
5102 rte_free(intr_handle->intr_vec);
5103 intr_handle->intr_vec = NULL;
5108 ixgbevf_dev_close(struct rte_eth_dev *dev)
5110 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5112 PMD_INIT_FUNC_TRACE();
5116 ixgbevf_dev_stop(dev);
5118 ixgbe_dev_free_queues(dev);
5121 * Remove the VF MAC address ro ensure
5122 * that the VF traffic goes to the PF
5123 * after stop, close and detach of the VF
5125 ixgbevf_remove_mac_addr(dev, 0);
5132 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5136 ret = eth_ixgbevf_dev_uninit(dev);
5140 ret = eth_ixgbevf_dev_init(dev);
5145 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5147 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5148 struct ixgbe_vfta *shadow_vfta =
5149 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5150 int i = 0, j = 0, vfta = 0, mask = 1;
5152 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5153 vfta = shadow_vfta->vfta[i];
5156 for (j = 0; j < 32; j++) {
5158 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5168 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5170 struct ixgbe_hw *hw =
5171 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5172 struct ixgbe_vfta *shadow_vfta =
5173 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5174 uint32_t vid_idx = 0;
5175 uint32_t vid_bit = 0;
5178 PMD_INIT_FUNC_TRACE();
5180 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5181 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5183 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5186 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5187 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5189 /* Save what we set and retore it after device reset */
5191 shadow_vfta->vfta[vid_idx] |= vid_bit;
5193 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5199 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5201 struct ixgbe_hw *hw =
5202 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5205 PMD_INIT_FUNC_TRACE();
5207 if (queue >= hw->mac.max_rx_queues)
5210 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5212 ctrl |= IXGBE_RXDCTL_VME;
5214 ctrl &= ~IXGBE_RXDCTL_VME;
5215 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5217 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5221 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5223 struct ixgbe_hw *hw =
5224 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5228 /* VF function only support hw strip feature, others are not support */
5229 if (mask & ETH_VLAN_STRIP_MASK) {
5230 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5232 for (i = 0; i < hw->mac.max_rx_queues; i++)
5233 ixgbevf_vlan_strip_queue_set(dev, i, on);
5240 ixgbe_vt_check(struct ixgbe_hw *hw)
5244 /* if Virtualization Technology is enabled */
5245 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5246 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5247 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5255 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5257 uint32_t vector = 0;
5259 switch (hw->mac.mc_filter_type) {
5260 case 0: /* use bits [47:36] of the address */
5261 vector = ((uc_addr->addr_bytes[4] >> 4) |
5262 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5264 case 1: /* use bits [46:35] of the address */
5265 vector = ((uc_addr->addr_bytes[4] >> 3) |
5266 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5268 case 2: /* use bits [45:34] of the address */
5269 vector = ((uc_addr->addr_bytes[4] >> 2) |
5270 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5272 case 3: /* use bits [43:32] of the address */
5273 vector = ((uc_addr->addr_bytes[4]) |
5274 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5276 default: /* Invalid mc_filter_type */
5280 /* vector can only be 12-bits or boundary will be exceeded */
5286 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5294 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5295 const uint32_t ixgbe_uta_bit_shift = 5;
5296 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5297 const uint32_t bit1 = 0x1;
5299 struct ixgbe_hw *hw =
5300 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5301 struct ixgbe_uta_info *uta_info =
5302 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5304 /* The UTA table only exists on 82599 hardware and newer */
5305 if (hw->mac.type < ixgbe_mac_82599EB)
5308 vector = ixgbe_uta_vector(hw, mac_addr);
5309 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5310 uta_shift = vector & ixgbe_uta_bit_mask;
5312 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5316 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5318 uta_info->uta_in_use++;
5319 reg_val |= (bit1 << uta_shift);
5320 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5322 uta_info->uta_in_use--;
5323 reg_val &= ~(bit1 << uta_shift);
5324 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5327 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5329 if (uta_info->uta_in_use > 0)
5330 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5331 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5333 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5339 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5342 struct ixgbe_hw *hw =
5343 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5344 struct ixgbe_uta_info *uta_info =
5345 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5347 /* The UTA table only exists on 82599 hardware and newer */
5348 if (hw->mac.type < ixgbe_mac_82599EB)
5352 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5353 uta_info->uta_shadow[i] = ~0;
5354 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5357 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5358 uta_info->uta_shadow[i] = 0;
5359 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5367 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5369 uint32_t new_val = orig_val;
5371 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5372 new_val |= IXGBE_VMOLR_AUPE;
5373 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5374 new_val |= IXGBE_VMOLR_ROMPE;
5375 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5376 new_val |= IXGBE_VMOLR_ROPE;
5377 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5378 new_val |= IXGBE_VMOLR_BAM;
5379 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5380 new_val |= IXGBE_VMOLR_MPE;
5385 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5386 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5387 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5388 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5389 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5390 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5391 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5394 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5395 struct rte_eth_mirror_conf *mirror_conf,
5396 uint8_t rule_id, uint8_t on)
5398 uint32_t mr_ctl, vlvf;
5399 uint32_t mp_lsb = 0;
5400 uint32_t mv_msb = 0;
5401 uint32_t mv_lsb = 0;
5402 uint32_t mp_msb = 0;
5405 uint64_t vlan_mask = 0;
5407 const uint8_t pool_mask_offset = 32;
5408 const uint8_t vlan_mask_offset = 32;
5409 const uint8_t dst_pool_offset = 8;
5410 const uint8_t rule_mr_offset = 4;
5411 const uint8_t mirror_rule_mask = 0x0F;
5413 struct ixgbe_mirror_info *mr_info =
5414 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5415 struct ixgbe_hw *hw =
5416 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5417 uint8_t mirror_type = 0;
5419 if (ixgbe_vt_check(hw) < 0)
5422 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5425 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5426 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5427 mirror_conf->rule_type);
5431 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5432 mirror_type |= IXGBE_MRCTL_VLME;
5433 /* Check if vlan id is valid and find conresponding VLAN ID
5436 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5437 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5438 /* search vlan id related pool vlan filter
5441 reg_index = ixgbe_find_vlvf_slot(
5443 mirror_conf->vlan.vlan_id[i],
5447 vlvf = IXGBE_READ_REG(hw,
5448 IXGBE_VLVF(reg_index));
5449 if ((vlvf & IXGBE_VLVF_VIEN) &&
5450 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5451 mirror_conf->vlan.vlan_id[i]))
5452 vlan_mask |= (1ULL << reg_index);
5459 mv_lsb = vlan_mask & 0xFFFFFFFF;
5460 mv_msb = vlan_mask >> vlan_mask_offset;
5462 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5463 mirror_conf->vlan.vlan_mask;
5464 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5465 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5466 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5467 mirror_conf->vlan.vlan_id[i];
5472 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5473 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5474 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5479 * if enable pool mirror, write related pool mask register,if disable
5480 * pool mirror, clear PFMRVM register
5482 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5483 mirror_type |= IXGBE_MRCTL_VPME;
5485 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5486 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5487 mr_info->mr_conf[rule_id].pool_mask =
5488 mirror_conf->pool_mask;
5493 mr_info->mr_conf[rule_id].pool_mask = 0;
5496 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5497 mirror_type |= IXGBE_MRCTL_UPME;
5498 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5499 mirror_type |= IXGBE_MRCTL_DPME;
5501 /* read mirror control register and recalculate it */
5502 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5505 mr_ctl |= mirror_type;
5506 mr_ctl &= mirror_rule_mask;
5507 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5509 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5512 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5513 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5515 /* write mirrror control register */
5516 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5518 /* write pool mirrror control register */
5519 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5520 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5521 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5524 /* write VLAN mirrror control register */
5525 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5526 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5527 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5535 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5538 uint32_t lsb_val = 0;
5539 uint32_t msb_val = 0;
5540 const uint8_t rule_mr_offset = 4;
5542 struct ixgbe_hw *hw =
5543 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5544 struct ixgbe_mirror_info *mr_info =
5545 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5547 if (ixgbe_vt_check(hw) < 0)
5550 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5553 memset(&mr_info->mr_conf[rule_id], 0,
5554 sizeof(struct rte_eth_mirror_conf));
5556 /* clear PFVMCTL register */
5557 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5559 /* clear pool mask register */
5560 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5561 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5563 /* clear vlan mask register */
5564 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5565 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5571 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5573 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5574 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5576 struct ixgbe_hw *hw =
5577 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5578 uint32_t vec = IXGBE_MISC_VEC_ID;
5580 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5581 if (rte_intr_allow_others(intr_handle))
5582 vec = IXGBE_RX_VEC_START;
5584 RTE_SET_USED(queue_id);
5585 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5587 rte_intr_enable(intr_handle);
5593 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5596 struct ixgbe_hw *hw =
5597 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5598 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5599 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5600 uint32_t vec = IXGBE_MISC_VEC_ID;
5602 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5603 if (rte_intr_allow_others(intr_handle))
5604 vec = IXGBE_RX_VEC_START;
5605 mask &= ~(1 << vec);
5606 RTE_SET_USED(queue_id);
5607 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5613 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5615 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5616 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5618 struct ixgbe_hw *hw =
5619 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5620 struct ixgbe_interrupt *intr =
5621 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5623 if (queue_id < 16) {
5624 ixgbe_disable_intr(hw);
5625 intr->mask |= (1 << queue_id);
5626 ixgbe_enable_intr(dev);
5627 } else if (queue_id < 32) {
5628 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5629 mask &= (1 << queue_id);
5630 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5631 } else if (queue_id < 64) {
5632 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5633 mask &= (1 << (queue_id - 32));
5634 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5636 rte_intr_enable(intr_handle);
5642 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5645 struct ixgbe_hw *hw =
5646 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5647 struct ixgbe_interrupt *intr =
5648 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5650 if (queue_id < 16) {
5651 ixgbe_disable_intr(hw);
5652 intr->mask &= ~(1 << queue_id);
5653 ixgbe_enable_intr(dev);
5654 } else if (queue_id < 32) {
5655 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5656 mask &= ~(1 << queue_id);
5657 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5658 } else if (queue_id < 64) {
5659 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5660 mask &= ~(1 << (queue_id - 32));
5661 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5668 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5669 uint8_t queue, uint8_t msix_vector)
5673 if (direction == -1) {
5675 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5676 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5679 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5681 /* rx or tx cause */
5682 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5683 idx = ((16 * (queue & 1)) + (8 * direction));
5684 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5685 tmp &= ~(0xFF << idx);
5686 tmp |= (msix_vector << idx);
5687 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5692 * set the IVAR registers, mapping interrupt causes to vectors
5694 * pointer to ixgbe_hw struct
5696 * 0 for Rx, 1 for Tx, -1 for other causes
5698 * queue to map the corresponding interrupt to
5700 * the vector to map to the corresponding queue
5703 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5704 uint8_t queue, uint8_t msix_vector)
5708 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5709 if (hw->mac.type == ixgbe_mac_82598EB) {
5710 if (direction == -1)
5712 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5713 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5714 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5715 tmp |= (msix_vector << (8 * (queue & 0x3)));
5716 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5717 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5718 (hw->mac.type == ixgbe_mac_X540) ||
5719 (hw->mac.type == ixgbe_mac_X550)) {
5720 if (direction == -1) {
5722 idx = ((queue & 1) * 8);
5723 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5724 tmp &= ~(0xFF << idx);
5725 tmp |= (msix_vector << idx);
5726 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5728 /* rx or tx causes */
5729 idx = ((16 * (queue & 1)) + (8 * direction));
5730 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5731 tmp &= ~(0xFF << idx);
5732 tmp |= (msix_vector << idx);
5733 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5739 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5741 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5742 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5743 struct ixgbe_hw *hw =
5744 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5746 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5747 uint32_t base = IXGBE_MISC_VEC_ID;
5749 /* Configure VF other cause ivar */
5750 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5752 /* won't configure msix register if no mapping is done
5753 * between intr vector and event fd.
5755 if (!rte_intr_dp_is_en(intr_handle))
5758 if (rte_intr_allow_others(intr_handle)) {
5759 base = IXGBE_RX_VEC_START;
5760 vector_idx = IXGBE_RX_VEC_START;
5763 /* Configure all RX queues of VF */
5764 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5765 /* Force all queue use vector 0,
5766 * as IXGBE_VF_MAXMSIVECOTR = 1
5768 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5769 intr_handle->intr_vec[q_idx] = vector_idx;
5770 if (vector_idx < base + intr_handle->nb_efd - 1)
5776 * Sets up the hardware to properly generate MSI-X interrupts
5778 * board private structure
5781 ixgbe_configure_msix(struct rte_eth_dev *dev)
5783 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5784 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5785 struct ixgbe_hw *hw =
5786 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5787 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5788 uint32_t vec = IXGBE_MISC_VEC_ID;
5792 /* won't configure msix register if no mapping is done
5793 * between intr vector and event fd
5795 if (!rte_intr_dp_is_en(intr_handle))
5798 if (rte_intr_allow_others(intr_handle))
5799 vec = base = IXGBE_RX_VEC_START;
5801 /* setup GPIE for MSI-x mode */
5802 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5803 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5804 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5805 /* auto clearing and auto setting corresponding bits in EIMS
5806 * when MSI-X interrupt is triggered
5808 if (hw->mac.type == ixgbe_mac_82598EB) {
5809 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5811 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5812 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5814 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5816 /* Populate the IVAR table and set the ITR values to the
5817 * corresponding register.
5819 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5821 /* by default, 1:1 mapping */
5822 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5823 intr_handle->intr_vec[queue_id] = vec;
5824 if (vec < base + intr_handle->nb_efd - 1)
5828 switch (hw->mac.type) {
5829 case ixgbe_mac_82598EB:
5830 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5833 case ixgbe_mac_82599EB:
5834 case ixgbe_mac_X540:
5835 case ixgbe_mac_X550:
5836 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5841 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5842 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5844 /* set up to autoclear timer, and the vectors */
5845 mask = IXGBE_EIMS_ENABLE_MASK;
5846 mask &= ~(IXGBE_EIMS_OTHER |
5847 IXGBE_EIMS_MAILBOX |
5850 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5854 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5855 uint16_t queue_idx, uint16_t tx_rate)
5857 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5858 uint32_t rf_dec, rf_int;
5860 uint16_t link_speed = dev->data->dev_link.link_speed;
5862 if (queue_idx >= hw->mac.max_tx_queues)
5866 /* Calculate the rate factor values to set */
5867 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5868 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5869 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5871 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5872 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5873 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5874 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5880 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5881 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5884 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5885 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5886 IXGBE_MAX_JUMBO_FRAME_SIZE))
5887 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5888 IXGBE_MMW_SIZE_JUMBO_FRAME);
5890 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5891 IXGBE_MMW_SIZE_DEFAULT);
5893 /* Set RTTBCNRC of queue X */
5894 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5895 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5896 IXGBE_WRITE_FLUSH(hw);
5902 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5903 __attribute__((unused)) uint32_t index,
5904 __attribute__((unused)) uint32_t pool)
5906 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5910 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5911 * operation. Trap this case to avoid exhausting the [very limited]
5912 * set of PF resources used to store VF MAC addresses.
5914 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5916 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5918 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5919 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5920 mac_addr->addr_bytes[0],
5921 mac_addr->addr_bytes[1],
5922 mac_addr->addr_bytes[2],
5923 mac_addr->addr_bytes[3],
5924 mac_addr->addr_bytes[4],
5925 mac_addr->addr_bytes[5],
5931 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5933 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5934 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5935 struct ether_addr *mac_addr;
5940 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5941 * not support the deletion of a given MAC address.
5942 * Instead, it imposes to delete all MAC addresses, then to add again
5943 * all MAC addresses with the exception of the one to be deleted.
5945 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5948 * Add again all MAC addresses, with the exception of the deleted one
5949 * and of the permanent MAC address.
5951 for (i = 0, mac_addr = dev->data->mac_addrs;
5952 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5953 /* Skip the deleted MAC address */
5956 /* Skip NULL MAC addresses */
5957 if (is_zero_ether_addr(mac_addr))
5959 /* Skip the permanent MAC address */
5960 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5962 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5965 "Adding again MAC address "
5966 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5968 mac_addr->addr_bytes[0],
5969 mac_addr->addr_bytes[1],
5970 mac_addr->addr_bytes[2],
5971 mac_addr->addr_bytes[3],
5972 mac_addr->addr_bytes[4],
5973 mac_addr->addr_bytes[5],
5979 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5981 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5983 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5987 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5988 struct rte_eth_syn_filter *filter,
5991 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5992 struct ixgbe_filter_info *filter_info =
5993 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5997 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6000 syn_info = filter_info->syn_info;
6003 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6005 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6006 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6008 if (filter->hig_pri)
6009 synqf |= IXGBE_SYN_FILTER_SYNQFP;
6011 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6013 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6014 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6016 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6019 filter_info->syn_info = synqf;
6020 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6021 IXGBE_WRITE_FLUSH(hw);
6026 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6027 struct rte_eth_syn_filter *filter)
6029 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6030 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6032 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6033 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6034 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6041 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6042 enum rte_filter_op filter_op,
6045 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6048 MAC_TYPE_FILTER_SUP(hw->mac.type);
6050 if (filter_op == RTE_ETH_FILTER_NOP)
6054 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6059 switch (filter_op) {
6060 case RTE_ETH_FILTER_ADD:
6061 ret = ixgbe_syn_filter_set(dev,
6062 (struct rte_eth_syn_filter *)arg,
6065 case RTE_ETH_FILTER_DELETE:
6066 ret = ixgbe_syn_filter_set(dev,
6067 (struct rte_eth_syn_filter *)arg,
6070 case RTE_ETH_FILTER_GET:
6071 ret = ixgbe_syn_filter_get(dev,
6072 (struct rte_eth_syn_filter *)arg);
6075 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6084 static inline enum ixgbe_5tuple_protocol
6085 convert_protocol_type(uint8_t protocol_value)
6087 if (protocol_value == IPPROTO_TCP)
6088 return IXGBE_FILTER_PROTOCOL_TCP;
6089 else if (protocol_value == IPPROTO_UDP)
6090 return IXGBE_FILTER_PROTOCOL_UDP;
6091 else if (protocol_value == IPPROTO_SCTP)
6092 return IXGBE_FILTER_PROTOCOL_SCTP;
6094 return IXGBE_FILTER_PROTOCOL_NONE;
6097 /* inject a 5-tuple filter to HW */
6099 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6100 struct ixgbe_5tuple_filter *filter)
6102 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6104 uint32_t ftqf, sdpqf;
6105 uint32_t l34timir = 0;
6106 uint8_t mask = 0xff;
6110 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6111 IXGBE_SDPQF_DSTPORT_SHIFT);
6112 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6114 ftqf = (uint32_t)(filter->filter_info.proto &
6115 IXGBE_FTQF_PROTOCOL_MASK);
6116 ftqf |= (uint32_t)((filter->filter_info.priority &
6117 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6118 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6119 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6120 if (filter->filter_info.dst_ip_mask == 0)
6121 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6122 if (filter->filter_info.src_port_mask == 0)
6123 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6124 if (filter->filter_info.dst_port_mask == 0)
6125 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6126 if (filter->filter_info.proto_mask == 0)
6127 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6128 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6129 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6130 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6132 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6133 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6134 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6135 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6137 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6138 l34timir |= (uint32_t)(filter->queue <<
6139 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6140 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6144 * add a 5tuple filter
6147 * dev: Pointer to struct rte_eth_dev.
6148 * index: the index the filter allocates.
6149 * filter: ponter to the filter that will be added.
6150 * rx_queue: the queue id the filter assigned to.
6153 * - On success, zero.
6154 * - On failure, a negative value.
6157 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6158 struct ixgbe_5tuple_filter *filter)
6160 struct ixgbe_filter_info *filter_info =
6161 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6165 * look for an unused 5tuple filter index,
6166 * and insert the filter to list.
6168 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6169 idx = i / (sizeof(uint32_t) * NBBY);
6170 shift = i % (sizeof(uint32_t) * NBBY);
6171 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6172 filter_info->fivetuple_mask[idx] |= 1 << shift;
6174 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6180 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6181 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6185 ixgbe_inject_5tuple_filter(dev, filter);
6191 * remove a 5tuple filter
6194 * dev: Pointer to struct rte_eth_dev.
6195 * filter: the pointer of the filter will be removed.
6198 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6199 struct ixgbe_5tuple_filter *filter)
6201 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6202 struct ixgbe_filter_info *filter_info =
6203 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6204 uint16_t index = filter->index;
6206 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6207 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6208 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6211 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6212 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6213 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6214 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6215 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6219 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6221 struct ixgbe_hw *hw;
6222 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6223 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6225 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6227 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6230 /* refuse mtu that requires the support of scattered packets when this
6231 * feature has not been enabled before.
6233 if (!rx_conf->enable_scatter &&
6234 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6235 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6239 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6240 * request of the version 2.0 of the mailbox API.
6241 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6242 * of the mailbox API.
6243 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6244 * prior to 3.11.33 which contains the following change:
6245 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6247 ixgbevf_rlpml_set_vf(hw, max_frame);
6249 /* update max frame size */
6250 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6254 static inline struct ixgbe_5tuple_filter *
6255 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6256 struct ixgbe_5tuple_filter_info *key)
6258 struct ixgbe_5tuple_filter *it;
6260 TAILQ_FOREACH(it, filter_list, entries) {
6261 if (memcmp(key, &it->filter_info,
6262 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6269 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6271 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6272 struct ixgbe_5tuple_filter_info *filter_info)
6274 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6275 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6276 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6279 switch (filter->dst_ip_mask) {
6281 filter_info->dst_ip_mask = 0;
6282 filter_info->dst_ip = filter->dst_ip;
6285 filter_info->dst_ip_mask = 1;
6288 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6292 switch (filter->src_ip_mask) {
6294 filter_info->src_ip_mask = 0;
6295 filter_info->src_ip = filter->src_ip;
6298 filter_info->src_ip_mask = 1;
6301 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6305 switch (filter->dst_port_mask) {
6307 filter_info->dst_port_mask = 0;
6308 filter_info->dst_port = filter->dst_port;
6311 filter_info->dst_port_mask = 1;
6314 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6318 switch (filter->src_port_mask) {
6320 filter_info->src_port_mask = 0;
6321 filter_info->src_port = filter->src_port;
6324 filter_info->src_port_mask = 1;
6327 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6331 switch (filter->proto_mask) {
6333 filter_info->proto_mask = 0;
6334 filter_info->proto =
6335 convert_protocol_type(filter->proto);
6338 filter_info->proto_mask = 1;
6341 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6345 filter_info->priority = (uint8_t)filter->priority;
6350 * add or delete a ntuple filter
6353 * dev: Pointer to struct rte_eth_dev.
6354 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6355 * add: if true, add filter, if false, remove filter
6358 * - On success, zero.
6359 * - On failure, a negative value.
6362 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6363 struct rte_eth_ntuple_filter *ntuple_filter,
6366 struct ixgbe_filter_info *filter_info =
6367 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6368 struct ixgbe_5tuple_filter_info filter_5tuple;
6369 struct ixgbe_5tuple_filter *filter;
6372 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6373 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6377 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6378 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6382 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6384 if (filter != NULL && add) {
6385 PMD_DRV_LOG(ERR, "filter exists.");
6388 if (filter == NULL && !add) {
6389 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6394 filter = rte_zmalloc("ixgbe_5tuple_filter",
6395 sizeof(struct ixgbe_5tuple_filter), 0);
6398 rte_memcpy(&filter->filter_info,
6400 sizeof(struct ixgbe_5tuple_filter_info));
6401 filter->queue = ntuple_filter->queue;
6402 ret = ixgbe_add_5tuple_filter(dev, filter);
6408 ixgbe_remove_5tuple_filter(dev, filter);
6414 * get a ntuple filter
6417 * dev: Pointer to struct rte_eth_dev.
6418 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6421 * - On success, zero.
6422 * - On failure, a negative value.
6425 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6426 struct rte_eth_ntuple_filter *ntuple_filter)
6428 struct ixgbe_filter_info *filter_info =
6429 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6430 struct ixgbe_5tuple_filter_info filter_5tuple;
6431 struct ixgbe_5tuple_filter *filter;
6434 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6435 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6439 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6440 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6444 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6446 if (filter == NULL) {
6447 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6450 ntuple_filter->queue = filter->queue;
6455 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6456 * @dev: pointer to rte_eth_dev structure
6457 * @filter_op:operation will be taken.
6458 * @arg: a pointer to specific structure corresponding to the filter_op
6461 * - On success, zero.
6462 * - On failure, a negative value.
6465 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6466 enum rte_filter_op filter_op,
6469 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6472 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6474 if (filter_op == RTE_ETH_FILTER_NOP)
6478 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6483 switch (filter_op) {
6484 case RTE_ETH_FILTER_ADD:
6485 ret = ixgbe_add_del_ntuple_filter(dev,
6486 (struct rte_eth_ntuple_filter *)arg,
6489 case RTE_ETH_FILTER_DELETE:
6490 ret = ixgbe_add_del_ntuple_filter(dev,
6491 (struct rte_eth_ntuple_filter *)arg,
6494 case RTE_ETH_FILTER_GET:
6495 ret = ixgbe_get_ntuple_filter(dev,
6496 (struct rte_eth_ntuple_filter *)arg);
6499 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6507 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6508 struct rte_eth_ethertype_filter *filter,
6511 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6512 struct ixgbe_filter_info *filter_info =
6513 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6517 struct ixgbe_ethertype_filter ethertype_filter;
6519 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6522 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6523 filter->ether_type == ETHER_TYPE_IPv6) {
6524 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6525 " ethertype filter.", filter->ether_type);
6529 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6530 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6533 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6534 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6538 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6539 if (ret >= 0 && add) {
6540 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6541 filter->ether_type);
6544 if (ret < 0 && !add) {
6545 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6546 filter->ether_type);
6551 etqf = IXGBE_ETQF_FILTER_EN;
6552 etqf |= (uint32_t)filter->ether_type;
6553 etqs |= (uint32_t)((filter->queue <<
6554 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6555 IXGBE_ETQS_RX_QUEUE);
6556 etqs |= IXGBE_ETQS_QUEUE_EN;
6558 ethertype_filter.ethertype = filter->ether_type;
6559 ethertype_filter.etqf = etqf;
6560 ethertype_filter.etqs = etqs;
6561 ethertype_filter.conf = FALSE;
6562 ret = ixgbe_ethertype_filter_insert(filter_info,
6565 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6569 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6573 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6574 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6575 IXGBE_WRITE_FLUSH(hw);
6581 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6582 struct rte_eth_ethertype_filter *filter)
6584 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6585 struct ixgbe_filter_info *filter_info =
6586 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6587 uint32_t etqf, etqs;
6590 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6592 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6593 filter->ether_type);
6597 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6598 if (etqf & IXGBE_ETQF_FILTER_EN) {
6599 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6600 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6602 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6603 IXGBE_ETQS_RX_QUEUE_SHIFT;
6610 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6611 * @dev: pointer to rte_eth_dev structure
6612 * @filter_op:operation will be taken.
6613 * @arg: a pointer to specific structure corresponding to the filter_op
6616 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6617 enum rte_filter_op filter_op,
6620 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6623 MAC_TYPE_FILTER_SUP(hw->mac.type);
6625 if (filter_op == RTE_ETH_FILTER_NOP)
6629 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6634 switch (filter_op) {
6635 case RTE_ETH_FILTER_ADD:
6636 ret = ixgbe_add_del_ethertype_filter(dev,
6637 (struct rte_eth_ethertype_filter *)arg,
6640 case RTE_ETH_FILTER_DELETE:
6641 ret = ixgbe_add_del_ethertype_filter(dev,
6642 (struct rte_eth_ethertype_filter *)arg,
6645 case RTE_ETH_FILTER_GET:
6646 ret = ixgbe_get_ethertype_filter(dev,
6647 (struct rte_eth_ethertype_filter *)arg);
6650 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6658 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6659 enum rte_filter_type filter_type,
6660 enum rte_filter_op filter_op,
6665 switch (filter_type) {
6666 case RTE_ETH_FILTER_NTUPLE:
6667 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6669 case RTE_ETH_FILTER_ETHERTYPE:
6670 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6672 case RTE_ETH_FILTER_SYN:
6673 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6675 case RTE_ETH_FILTER_FDIR:
6676 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6678 case RTE_ETH_FILTER_L2_TUNNEL:
6679 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6681 case RTE_ETH_FILTER_GENERIC:
6682 if (filter_op != RTE_ETH_FILTER_GET)
6684 *(const void **)arg = &ixgbe_flow_ops;
6687 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6697 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6698 u8 **mc_addr_ptr, u32 *vmdq)
6703 mc_addr = *mc_addr_ptr;
6704 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6709 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6710 struct ether_addr *mc_addr_set,
6711 uint32_t nb_mc_addr)
6713 struct ixgbe_hw *hw;
6716 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6717 mc_addr_list = (u8 *)mc_addr_set;
6718 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6719 ixgbe_dev_addr_list_itr, TRUE);
6723 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6725 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6726 uint64_t systime_cycles;
6728 switch (hw->mac.type) {
6729 case ixgbe_mac_X550:
6730 case ixgbe_mac_X550EM_x:
6731 case ixgbe_mac_X550EM_a:
6732 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6733 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6734 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6738 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6739 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6743 return systime_cycles;
6747 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6749 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6750 uint64_t rx_tstamp_cycles;
6752 switch (hw->mac.type) {
6753 case ixgbe_mac_X550:
6754 case ixgbe_mac_X550EM_x:
6755 case ixgbe_mac_X550EM_a:
6756 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6757 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6758 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6762 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6763 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6764 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6768 return rx_tstamp_cycles;
6772 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6774 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6775 uint64_t tx_tstamp_cycles;
6777 switch (hw->mac.type) {
6778 case ixgbe_mac_X550:
6779 case ixgbe_mac_X550EM_x:
6780 case ixgbe_mac_X550EM_a:
6781 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6782 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6783 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6787 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6788 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6789 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6793 return tx_tstamp_cycles;
6797 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6799 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6800 struct ixgbe_adapter *adapter =
6801 (struct ixgbe_adapter *)dev->data->dev_private;
6802 struct rte_eth_link link;
6803 uint32_t incval = 0;
6806 /* Get current link speed. */
6807 memset(&link, 0, sizeof(link));
6808 ixgbe_dev_link_update(dev, 1);
6809 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6811 switch (link.link_speed) {
6812 case ETH_SPEED_NUM_100M:
6813 incval = IXGBE_INCVAL_100;
6814 shift = IXGBE_INCVAL_SHIFT_100;
6816 case ETH_SPEED_NUM_1G:
6817 incval = IXGBE_INCVAL_1GB;
6818 shift = IXGBE_INCVAL_SHIFT_1GB;
6820 case ETH_SPEED_NUM_10G:
6822 incval = IXGBE_INCVAL_10GB;
6823 shift = IXGBE_INCVAL_SHIFT_10GB;
6827 switch (hw->mac.type) {
6828 case ixgbe_mac_X550:
6829 case ixgbe_mac_X550EM_x:
6830 case ixgbe_mac_X550EM_a:
6831 /* Independent of link speed. */
6833 /* Cycles read will be interpreted as ns. */
6836 case ixgbe_mac_X540:
6837 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6839 case ixgbe_mac_82599EB:
6840 incval >>= IXGBE_INCVAL_SHIFT_82599;
6841 shift -= IXGBE_INCVAL_SHIFT_82599;
6842 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6843 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6846 /* Not supported. */
6850 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6851 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6852 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6854 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6855 adapter->systime_tc.cc_shift = shift;
6856 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6858 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6859 adapter->rx_tstamp_tc.cc_shift = shift;
6860 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6862 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6863 adapter->tx_tstamp_tc.cc_shift = shift;
6864 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6868 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6870 struct ixgbe_adapter *adapter =
6871 (struct ixgbe_adapter *)dev->data->dev_private;
6873 adapter->systime_tc.nsec += delta;
6874 adapter->rx_tstamp_tc.nsec += delta;
6875 adapter->tx_tstamp_tc.nsec += delta;
6881 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6884 struct ixgbe_adapter *adapter =
6885 (struct ixgbe_adapter *)dev->data->dev_private;
6887 ns = rte_timespec_to_ns(ts);
6888 /* Set the timecounters to a new value. */
6889 adapter->systime_tc.nsec = ns;
6890 adapter->rx_tstamp_tc.nsec = ns;
6891 adapter->tx_tstamp_tc.nsec = ns;
6897 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6899 uint64_t ns, systime_cycles;
6900 struct ixgbe_adapter *adapter =
6901 (struct ixgbe_adapter *)dev->data->dev_private;
6903 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6904 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6905 *ts = rte_ns_to_timespec(ns);
6911 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6913 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6917 /* Stop the timesync system time. */
6918 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6919 /* Reset the timesync system time value. */
6920 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6921 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6923 /* Enable system time for platforms where it isn't on by default. */
6924 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6925 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6926 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6928 ixgbe_start_timecounters(dev);
6930 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6931 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6933 IXGBE_ETQF_FILTER_EN |
6936 /* Enable timestamping of received PTP packets. */
6937 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6938 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6939 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6941 /* Enable timestamping of transmitted PTP packets. */
6942 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6943 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6944 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6946 IXGBE_WRITE_FLUSH(hw);
6952 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6954 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6957 /* Disable timestamping of transmitted PTP packets. */
6958 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6959 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6960 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6962 /* Disable timestamping of received PTP packets. */
6963 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6964 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6965 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6967 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6968 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6970 /* Stop incrementating the System Time registers. */
6971 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6977 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6978 struct timespec *timestamp,
6979 uint32_t flags __rte_unused)
6981 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6982 struct ixgbe_adapter *adapter =
6983 (struct ixgbe_adapter *)dev->data->dev_private;
6984 uint32_t tsync_rxctl;
6985 uint64_t rx_tstamp_cycles;
6988 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6989 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6992 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6993 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6994 *timestamp = rte_ns_to_timespec(ns);
7000 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7001 struct timespec *timestamp)
7003 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7004 struct ixgbe_adapter *adapter =
7005 (struct ixgbe_adapter *)dev->data->dev_private;
7006 uint32_t tsync_txctl;
7007 uint64_t tx_tstamp_cycles;
7010 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7011 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7014 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7015 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7016 *timestamp = rte_ns_to_timespec(ns);
7022 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7024 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7027 const struct reg_info *reg_group;
7028 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7029 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7031 while ((reg_group = reg_set[g_ind++]))
7032 count += ixgbe_regs_group_count(reg_group);
7038 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7042 const struct reg_info *reg_group;
7044 while ((reg_group = ixgbevf_regs[g_ind++]))
7045 count += ixgbe_regs_group_count(reg_group);
7051 ixgbe_get_regs(struct rte_eth_dev *dev,
7052 struct rte_dev_reg_info *regs)
7054 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7055 uint32_t *data = regs->data;
7058 const struct reg_info *reg_group;
7059 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7060 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7063 regs->length = ixgbe_get_reg_length(dev);
7064 regs->width = sizeof(uint32_t);
7068 /* Support only full register dump */
7069 if ((regs->length == 0) ||
7070 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7071 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7073 while ((reg_group = reg_set[g_ind++]))
7074 count += ixgbe_read_regs_group(dev, &data[count],
7083 ixgbevf_get_regs(struct rte_eth_dev *dev,
7084 struct rte_dev_reg_info *regs)
7086 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7087 uint32_t *data = regs->data;
7090 const struct reg_info *reg_group;
7093 regs->length = ixgbevf_get_reg_length(dev);
7094 regs->width = sizeof(uint32_t);
7098 /* Support only full register dump */
7099 if ((regs->length == 0) ||
7100 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7101 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7103 while ((reg_group = ixgbevf_regs[g_ind++]))
7104 count += ixgbe_read_regs_group(dev, &data[count],
7113 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7115 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7117 /* Return unit is byte count */
7118 return hw->eeprom.word_size * 2;
7122 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7123 struct rte_dev_eeprom_info *in_eeprom)
7125 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7126 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7127 uint16_t *data = in_eeprom->data;
7130 first = in_eeprom->offset >> 1;
7131 length = in_eeprom->length >> 1;
7132 if ((first > hw->eeprom.word_size) ||
7133 ((first + length) > hw->eeprom.word_size))
7136 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7138 return eeprom->ops.read_buffer(hw, first, length, data);
7142 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7143 struct rte_dev_eeprom_info *in_eeprom)
7145 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7146 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7147 uint16_t *data = in_eeprom->data;
7150 first = in_eeprom->offset >> 1;
7151 length = in_eeprom->length >> 1;
7152 if ((first > hw->eeprom.word_size) ||
7153 ((first + length) > hw->eeprom.word_size))
7156 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7158 return eeprom->ops.write_buffer(hw, first, length, data);
7162 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7164 case ixgbe_mac_X550:
7165 case ixgbe_mac_X550EM_x:
7166 case ixgbe_mac_X550EM_a:
7167 return ETH_RSS_RETA_SIZE_512;
7168 case ixgbe_mac_X550_vf:
7169 case ixgbe_mac_X550EM_x_vf:
7170 case ixgbe_mac_X550EM_a_vf:
7171 return ETH_RSS_RETA_SIZE_64;
7173 return ETH_RSS_RETA_SIZE_128;
7178 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7180 case ixgbe_mac_X550:
7181 case ixgbe_mac_X550EM_x:
7182 case ixgbe_mac_X550EM_a:
7183 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7184 return IXGBE_RETA(reta_idx >> 2);
7186 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7187 case ixgbe_mac_X550_vf:
7188 case ixgbe_mac_X550EM_x_vf:
7189 case ixgbe_mac_X550EM_a_vf:
7190 return IXGBE_VFRETA(reta_idx >> 2);
7192 return IXGBE_RETA(reta_idx >> 2);
7197 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7199 case ixgbe_mac_X550_vf:
7200 case ixgbe_mac_X550EM_x_vf:
7201 case ixgbe_mac_X550EM_a_vf:
7202 return IXGBE_VFMRQC;
7209 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7211 case ixgbe_mac_X550_vf:
7212 case ixgbe_mac_X550EM_x_vf:
7213 case ixgbe_mac_X550EM_a_vf:
7214 return IXGBE_VFRSSRK(i);
7216 return IXGBE_RSSRK(i);
7221 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7223 case ixgbe_mac_82599_vf:
7224 case ixgbe_mac_X540_vf:
7232 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7233 struct rte_eth_dcb_info *dcb_info)
7235 struct ixgbe_dcb_config *dcb_config =
7236 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7237 struct ixgbe_dcb_tc_config *tc;
7238 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7242 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7243 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7245 dcb_info->nb_tcs = 1;
7247 tc_queue = &dcb_info->tc_queue;
7248 nb_tcs = dcb_info->nb_tcs;
7250 if (dcb_config->vt_mode) { /* vt is enabled*/
7251 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7252 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7253 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7254 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7255 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7256 for (j = 0; j < nb_tcs; j++) {
7257 tc_queue->tc_rxq[0][j].base = j;
7258 tc_queue->tc_rxq[0][j].nb_queue = 1;
7259 tc_queue->tc_txq[0][j].base = j;
7260 tc_queue->tc_txq[0][j].nb_queue = 1;
7263 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7264 for (j = 0; j < nb_tcs; j++) {
7265 tc_queue->tc_rxq[i][j].base =
7267 tc_queue->tc_rxq[i][j].nb_queue = 1;
7268 tc_queue->tc_txq[i][j].base =
7270 tc_queue->tc_txq[i][j].nb_queue = 1;
7274 } else { /* vt is disabled*/
7275 struct rte_eth_dcb_rx_conf *rx_conf =
7276 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7277 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7278 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7279 if (dcb_info->nb_tcs == ETH_4_TCS) {
7280 for (i = 0; i < dcb_info->nb_tcs; i++) {
7281 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7282 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7284 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7285 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7286 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7287 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7288 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7289 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7290 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7291 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7292 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7293 for (i = 0; i < dcb_info->nb_tcs; i++) {
7294 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7295 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7297 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7298 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7299 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7300 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7301 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7302 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7303 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7304 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7305 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7306 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7307 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7308 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7309 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7310 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7311 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7312 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7315 for (i = 0; i < dcb_info->nb_tcs; i++) {
7316 tc = &dcb_config->tc_config[i];
7317 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7322 /* Update e-tag ether type */
7324 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7325 uint16_t ether_type)
7327 uint32_t etag_etype;
7329 if (hw->mac.type != ixgbe_mac_X550 &&
7330 hw->mac.type != ixgbe_mac_X550EM_x &&
7331 hw->mac.type != ixgbe_mac_X550EM_a) {
7335 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7336 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7337 etag_etype |= ether_type;
7338 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7339 IXGBE_WRITE_FLUSH(hw);
7344 /* Config l2 tunnel ether type */
7346 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7347 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7350 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7351 struct ixgbe_l2_tn_info *l2_tn_info =
7352 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7354 if (l2_tunnel == NULL)
7357 switch (l2_tunnel->l2_tunnel_type) {
7358 case RTE_L2_TUNNEL_TYPE_E_TAG:
7359 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7360 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7363 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7371 /* Enable e-tag tunnel */
7373 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7375 uint32_t etag_etype;
7377 if (hw->mac.type != ixgbe_mac_X550 &&
7378 hw->mac.type != ixgbe_mac_X550EM_x &&
7379 hw->mac.type != ixgbe_mac_X550EM_a) {
7383 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7384 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7385 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7386 IXGBE_WRITE_FLUSH(hw);
7391 /* Enable l2 tunnel */
7393 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7394 enum rte_eth_tunnel_type l2_tunnel_type)
7397 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7398 struct ixgbe_l2_tn_info *l2_tn_info =
7399 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7401 switch (l2_tunnel_type) {
7402 case RTE_L2_TUNNEL_TYPE_E_TAG:
7403 l2_tn_info->e_tag_en = TRUE;
7404 ret = ixgbe_e_tag_enable(hw);
7407 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7415 /* Disable e-tag tunnel */
7417 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7419 uint32_t etag_etype;
7421 if (hw->mac.type != ixgbe_mac_X550 &&
7422 hw->mac.type != ixgbe_mac_X550EM_x &&
7423 hw->mac.type != ixgbe_mac_X550EM_a) {
7427 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7428 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7429 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7430 IXGBE_WRITE_FLUSH(hw);
7435 /* Disable l2 tunnel */
7437 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7438 enum rte_eth_tunnel_type l2_tunnel_type)
7441 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7442 struct ixgbe_l2_tn_info *l2_tn_info =
7443 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7445 switch (l2_tunnel_type) {
7446 case RTE_L2_TUNNEL_TYPE_E_TAG:
7447 l2_tn_info->e_tag_en = FALSE;
7448 ret = ixgbe_e_tag_disable(hw);
7451 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7460 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7461 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7464 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7465 uint32_t i, rar_entries;
7466 uint32_t rar_low, rar_high;
7468 if (hw->mac.type != ixgbe_mac_X550 &&
7469 hw->mac.type != ixgbe_mac_X550EM_x &&
7470 hw->mac.type != ixgbe_mac_X550EM_a) {
7474 rar_entries = ixgbe_get_num_rx_addrs(hw);
7476 for (i = 1; i < rar_entries; i++) {
7477 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7478 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7479 if ((rar_high & IXGBE_RAH_AV) &&
7480 (rar_high & IXGBE_RAH_ADTYPE) &&
7481 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7482 l2_tunnel->tunnel_id)) {
7483 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7484 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7486 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7496 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7497 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7500 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7501 uint32_t i, rar_entries;
7502 uint32_t rar_low, rar_high;
7504 if (hw->mac.type != ixgbe_mac_X550 &&
7505 hw->mac.type != ixgbe_mac_X550EM_x &&
7506 hw->mac.type != ixgbe_mac_X550EM_a) {
7510 /* One entry for one tunnel. Try to remove potential existing entry. */
7511 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7513 rar_entries = ixgbe_get_num_rx_addrs(hw);
7515 for (i = 1; i < rar_entries; i++) {
7516 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7517 if (rar_high & IXGBE_RAH_AV) {
7520 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7521 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7522 rar_low = l2_tunnel->tunnel_id;
7524 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7525 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7531 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7532 " Please remove a rule before adding a new one.");
7536 static inline struct ixgbe_l2_tn_filter *
7537 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7538 struct ixgbe_l2_tn_key *key)
7542 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7546 return l2_tn_info->hash_map[ret];
7550 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7551 struct ixgbe_l2_tn_filter *l2_tn_filter)
7555 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7556 &l2_tn_filter->key);
7560 "Failed to insert L2 tunnel filter"
7561 " to hash table %d!",
7566 l2_tn_info->hash_map[ret] = l2_tn_filter;
7568 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7574 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7575 struct ixgbe_l2_tn_key *key)
7578 struct ixgbe_l2_tn_filter *l2_tn_filter;
7580 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7584 "No such L2 tunnel filter to delete %d!",
7589 l2_tn_filter = l2_tn_info->hash_map[ret];
7590 l2_tn_info->hash_map[ret] = NULL;
7592 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7593 rte_free(l2_tn_filter);
7598 /* Add l2 tunnel filter */
7600 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7601 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7605 struct ixgbe_l2_tn_info *l2_tn_info =
7606 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7607 struct ixgbe_l2_tn_key key;
7608 struct ixgbe_l2_tn_filter *node;
7611 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7612 key.tn_id = l2_tunnel->tunnel_id;
7614 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7618 "The L2 tunnel filter already exists!");
7622 node = rte_zmalloc("ixgbe_l2_tn",
7623 sizeof(struct ixgbe_l2_tn_filter),
7628 rte_memcpy(&node->key,
7630 sizeof(struct ixgbe_l2_tn_key));
7631 node->pool = l2_tunnel->pool;
7632 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7639 switch (l2_tunnel->l2_tunnel_type) {
7640 case RTE_L2_TUNNEL_TYPE_E_TAG:
7641 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7644 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7649 if ((!restore) && (ret < 0))
7650 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7655 /* Delete l2 tunnel filter */
7657 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7658 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7661 struct ixgbe_l2_tn_info *l2_tn_info =
7662 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7663 struct ixgbe_l2_tn_key key;
7665 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7666 key.tn_id = l2_tunnel->tunnel_id;
7667 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7671 switch (l2_tunnel->l2_tunnel_type) {
7672 case RTE_L2_TUNNEL_TYPE_E_TAG:
7673 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7676 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7685 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7686 * @dev: pointer to rte_eth_dev structure
7687 * @filter_op:operation will be taken.
7688 * @arg: a pointer to specific structure corresponding to the filter_op
7691 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7692 enum rte_filter_op filter_op,
7697 if (filter_op == RTE_ETH_FILTER_NOP)
7701 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7706 switch (filter_op) {
7707 case RTE_ETH_FILTER_ADD:
7708 ret = ixgbe_dev_l2_tunnel_filter_add
7710 (struct rte_eth_l2_tunnel_conf *)arg,
7713 case RTE_ETH_FILTER_DELETE:
7714 ret = ixgbe_dev_l2_tunnel_filter_del
7716 (struct rte_eth_l2_tunnel_conf *)arg);
7719 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7727 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7731 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7733 if (hw->mac.type != ixgbe_mac_X550 &&
7734 hw->mac.type != ixgbe_mac_X550EM_x &&
7735 hw->mac.type != ixgbe_mac_X550EM_a) {
7739 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7740 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7742 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7743 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7748 /* Enable l2 tunnel forwarding */
7750 ixgbe_dev_l2_tunnel_forwarding_enable
7751 (struct rte_eth_dev *dev,
7752 enum rte_eth_tunnel_type l2_tunnel_type)
7754 struct ixgbe_l2_tn_info *l2_tn_info =
7755 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7758 switch (l2_tunnel_type) {
7759 case RTE_L2_TUNNEL_TYPE_E_TAG:
7760 l2_tn_info->e_tag_fwd_en = TRUE;
7761 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7764 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7772 /* Disable l2 tunnel forwarding */
7774 ixgbe_dev_l2_tunnel_forwarding_disable
7775 (struct rte_eth_dev *dev,
7776 enum rte_eth_tunnel_type l2_tunnel_type)
7778 struct ixgbe_l2_tn_info *l2_tn_info =
7779 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7782 switch (l2_tunnel_type) {
7783 case RTE_L2_TUNNEL_TYPE_E_TAG:
7784 l2_tn_info->e_tag_fwd_en = FALSE;
7785 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7788 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7797 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7798 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7801 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7803 uint32_t vmtir, vmvir;
7804 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7806 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7808 "VF id %u should be less than %u",
7814 if (hw->mac.type != ixgbe_mac_X550 &&
7815 hw->mac.type != ixgbe_mac_X550EM_x &&
7816 hw->mac.type != ixgbe_mac_X550EM_a) {
7821 vmtir = l2_tunnel->tunnel_id;
7825 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7827 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7828 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7830 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7831 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7836 /* Enable l2 tunnel tag insertion */
7838 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7839 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7843 switch (l2_tunnel->l2_tunnel_type) {
7844 case RTE_L2_TUNNEL_TYPE_E_TAG:
7845 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7848 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7856 /* Disable l2 tunnel tag insertion */
7858 ixgbe_dev_l2_tunnel_insertion_disable
7859 (struct rte_eth_dev *dev,
7860 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7864 switch (l2_tunnel->l2_tunnel_type) {
7865 case RTE_L2_TUNNEL_TYPE_E_TAG:
7866 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7869 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7878 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7883 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7885 if (hw->mac.type != ixgbe_mac_X550 &&
7886 hw->mac.type != ixgbe_mac_X550EM_x &&
7887 hw->mac.type != ixgbe_mac_X550EM_a) {
7891 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7893 qde |= IXGBE_QDE_STRIP_TAG;
7895 qde &= ~IXGBE_QDE_STRIP_TAG;
7896 qde &= ~IXGBE_QDE_READ;
7897 qde |= IXGBE_QDE_WRITE;
7898 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7903 /* Enable l2 tunnel tag stripping */
7905 ixgbe_dev_l2_tunnel_stripping_enable
7906 (struct rte_eth_dev *dev,
7907 enum rte_eth_tunnel_type l2_tunnel_type)
7911 switch (l2_tunnel_type) {
7912 case RTE_L2_TUNNEL_TYPE_E_TAG:
7913 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7916 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7924 /* Disable l2 tunnel tag stripping */
7926 ixgbe_dev_l2_tunnel_stripping_disable
7927 (struct rte_eth_dev *dev,
7928 enum rte_eth_tunnel_type l2_tunnel_type)
7932 switch (l2_tunnel_type) {
7933 case RTE_L2_TUNNEL_TYPE_E_TAG:
7934 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7937 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7945 /* Enable/disable l2 tunnel offload functions */
7947 ixgbe_dev_l2_tunnel_offload_set
7948 (struct rte_eth_dev *dev,
7949 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7955 if (l2_tunnel == NULL)
7959 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7961 ret = ixgbe_dev_l2_tunnel_enable(
7963 l2_tunnel->l2_tunnel_type);
7965 ret = ixgbe_dev_l2_tunnel_disable(
7967 l2_tunnel->l2_tunnel_type);
7970 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7972 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7976 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7981 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7983 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7985 l2_tunnel->l2_tunnel_type);
7987 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7989 l2_tunnel->l2_tunnel_type);
7992 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7994 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7996 l2_tunnel->l2_tunnel_type);
7998 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8000 l2_tunnel->l2_tunnel_type);
8007 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8010 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8011 IXGBE_WRITE_FLUSH(hw);
8016 /* There's only one register for VxLAN UDP port.
8017 * So, we cannot add several ports. Will update it.
8020 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8024 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8028 return ixgbe_update_vxlan_port(hw, port);
8031 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8032 * UDP port, it must have a value.
8033 * So, will reset it to the original value 0.
8036 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8041 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8043 if (cur_port != port) {
8044 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8048 return ixgbe_update_vxlan_port(hw, 0);
8051 /* Add UDP tunneling port */
8053 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8054 struct rte_eth_udp_tunnel *udp_tunnel)
8057 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8059 if (hw->mac.type != ixgbe_mac_X550 &&
8060 hw->mac.type != ixgbe_mac_X550EM_x &&
8061 hw->mac.type != ixgbe_mac_X550EM_a) {
8065 if (udp_tunnel == NULL)
8068 switch (udp_tunnel->prot_type) {
8069 case RTE_TUNNEL_TYPE_VXLAN:
8070 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8073 case RTE_TUNNEL_TYPE_GENEVE:
8074 case RTE_TUNNEL_TYPE_TEREDO:
8075 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8080 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8088 /* Remove UDP tunneling port */
8090 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8091 struct rte_eth_udp_tunnel *udp_tunnel)
8094 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8096 if (hw->mac.type != ixgbe_mac_X550 &&
8097 hw->mac.type != ixgbe_mac_X550EM_x &&
8098 hw->mac.type != ixgbe_mac_X550EM_a) {
8102 if (udp_tunnel == NULL)
8105 switch (udp_tunnel->prot_type) {
8106 case RTE_TUNNEL_TYPE_VXLAN:
8107 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8109 case RTE_TUNNEL_TYPE_GENEVE:
8110 case RTE_TUNNEL_TYPE_TEREDO:
8111 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8115 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8124 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8126 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8128 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8132 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8134 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8136 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8139 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8141 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8144 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8147 /* PF reset VF event */
8148 if (in_msg == IXGBE_PF_CONTROL_MSG)
8149 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8154 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8157 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8158 struct ixgbe_interrupt *intr =
8159 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8160 ixgbevf_intr_disable(hw);
8162 /* read-on-clear nic registers here */
8163 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8166 /* only one misc vector supported - mailbox */
8167 eicr &= IXGBE_VTEICR_MASK;
8168 if (eicr == IXGBE_MISC_VEC_ID)
8169 intr->flags |= IXGBE_FLAG_MAILBOX;
8175 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8177 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8178 struct ixgbe_interrupt *intr =
8179 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8181 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8182 ixgbevf_mbx_process(dev);
8183 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8186 ixgbevf_intr_enable(hw);
8192 ixgbevf_dev_interrupt_handler(void *param)
8194 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8196 ixgbevf_dev_interrupt_get_status(dev);
8197 ixgbevf_dev_interrupt_action(dev);
8201 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8202 * @hw: pointer to hardware structure
8204 * Stops the transmit data path and waits for the HW to internally empty
8205 * the Tx security block
8207 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8209 #define IXGBE_MAX_SECTX_POLL 40
8214 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8215 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8216 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8217 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8218 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8219 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8221 /* Use interrupt-safe sleep just in case */
8225 /* For informational purposes only */
8226 if (i >= IXGBE_MAX_SECTX_POLL)
8227 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8228 "path fully disabled. Continuing with init.");
8230 return IXGBE_SUCCESS;
8234 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8235 * @hw: pointer to hardware structure
8237 * Enables the transmit data path.
8239 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8243 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8244 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8245 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8246 IXGBE_WRITE_FLUSH(hw);
8248 return IXGBE_SUCCESS;
8251 /* restore n-tuple filter */
8253 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8255 struct ixgbe_filter_info *filter_info =
8256 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8257 struct ixgbe_5tuple_filter *node;
8259 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8260 ixgbe_inject_5tuple_filter(dev, node);
8264 /* restore ethernet type filter */
8266 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8268 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8269 struct ixgbe_filter_info *filter_info =
8270 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8273 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8274 if (filter_info->ethertype_mask & (1 << i)) {
8275 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8276 filter_info->ethertype_filters[i].etqf);
8277 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8278 filter_info->ethertype_filters[i].etqs);
8279 IXGBE_WRITE_FLUSH(hw);
8284 /* restore SYN filter */
8286 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8288 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8289 struct ixgbe_filter_info *filter_info =
8290 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8293 synqf = filter_info->syn_info;
8295 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8296 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8297 IXGBE_WRITE_FLUSH(hw);
8301 /* restore L2 tunnel filter */
8303 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8305 struct ixgbe_l2_tn_info *l2_tn_info =
8306 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8307 struct ixgbe_l2_tn_filter *node;
8308 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8310 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8311 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8312 l2_tn_conf.tunnel_id = node->key.tn_id;
8313 l2_tn_conf.pool = node->pool;
8314 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8318 /* restore rss filter */
8320 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8322 struct ixgbe_filter_info *filter_info =
8323 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8325 if (filter_info->rss_info.num)
8326 ixgbe_config_rss_filter(dev,
8327 &filter_info->rss_info, TRUE);
8331 ixgbe_filter_restore(struct rte_eth_dev *dev)
8333 ixgbe_ntuple_filter_restore(dev);
8334 ixgbe_ethertype_filter_restore(dev);
8335 ixgbe_syn_filter_restore(dev);
8336 ixgbe_fdir_filter_restore(dev);
8337 ixgbe_l2_tn_filter_restore(dev);
8338 ixgbe_rss_filter_restore(dev);
8344 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8346 struct ixgbe_l2_tn_info *l2_tn_info =
8347 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8348 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8350 if (l2_tn_info->e_tag_en)
8351 (void)ixgbe_e_tag_enable(hw);
8353 if (l2_tn_info->e_tag_fwd_en)
8354 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8356 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8359 /* remove all the n-tuple filters */
8361 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8363 struct ixgbe_filter_info *filter_info =
8364 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8365 struct ixgbe_5tuple_filter *p_5tuple;
8367 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8368 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8371 /* remove all the ether type filters */
8373 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8375 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8376 struct ixgbe_filter_info *filter_info =
8377 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8380 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8381 if (filter_info->ethertype_mask & (1 << i) &&
8382 !filter_info->ethertype_filters[i].conf) {
8383 (void)ixgbe_ethertype_filter_remove(filter_info,
8385 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8386 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8387 IXGBE_WRITE_FLUSH(hw);
8392 /* remove the SYN filter */
8394 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8396 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8397 struct ixgbe_filter_info *filter_info =
8398 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8400 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8401 filter_info->syn_info = 0;
8403 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8404 IXGBE_WRITE_FLUSH(hw);
8408 /* remove all the L2 tunnel filters */
8410 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8412 struct ixgbe_l2_tn_info *l2_tn_info =
8413 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8414 struct ixgbe_l2_tn_filter *l2_tn_filter;
8415 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8418 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8419 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8420 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8421 l2_tn_conf.pool = l2_tn_filter->pool;
8422 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8430 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8431 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8432 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8433 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8434 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8435 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8437 RTE_INIT(ixgbe_init_log);
8439 ixgbe_init_log(void)
8441 ixgbe_logtype_init = rte_log_register("pmd.ixgbe.init");
8442 if (ixgbe_logtype_init >= 0)
8443 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8444 ixgbe_logtype_driver = rte_log_register("pmd.ixgbe.driver");
8445 if (ixgbe_logtype_driver >= 0)
8446 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);