drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_ethdev_pci.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63 #include <rte_hash_crc.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "base/ixgbe_api.h"
  67 #include "base/ixgbe_vf.h"
  68 #include "base/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71 #include "ixgbe_rxtx.h"
  72 #include "base/ixgbe_type.h"
  73 #include "base/ixgbe_phy.h"
  74 #include "ixgbe_regs.h"
  75
  76 /*
  77  * High threshold controlling when to start sending XOFF frames. Must be at
  78  * least 8 bytes less than receive packet buffer size. This value is in units
  79  * of 1024 bytes.
  80  */
  81 #define IXGBE_FC_HI    0x80
  82
  83 /*
  84  * Low threshold controlling when to start sending XON frames. This value is
  85  * in units of 1024 bytes.
  86  */
  87 #define IXGBE_FC_LO    0x40
  88
  89 /* Default minimum inter-interrupt interval for EITR configuration */
  90 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  91
  92 /* Timer value included in XOFF frames. */
  93 #define IXGBE_FC_PAUSE 0x680
  94
  95 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  96 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  97 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  98
  99 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 100 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 101 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 102
 103 /*
 104  *  Default values for RX/TX configuration
 105  */
 106 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 107 #define IXGBE_DEFAULT_RX_PTHRESH      8
 108 #define IXGBE_DEFAULT_RX_HTHRESH      8
 109 #define IXGBE_DEFAULT_RX_WTHRESH      0
 110
 111 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 112 #define IXGBE_DEFAULT_TX_PTHRESH      32
 113 #define IXGBE_DEFAULT_TX_HTHRESH      0
 114 #define IXGBE_DEFAULT_TX_WTHRESH      0
 115 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 116
 117 /* Bit shift and mask */
 118 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 119 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 120 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 121 #define IXGBE_8_BIT_MASK   UINT8_MAX
 122
 123 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 124
 125 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 126
 127 #define IXGBE_HKEY_MAX_INDEX 10
 128
 129 /* Additional timesync values. */
 130 #define NSEC_PER_SEC             1000000000L
 131 #define IXGBE_INCVAL_10GB        0x66666666
 132 #define IXGBE_INCVAL_1GB         0x40000000
 133 #define IXGBE_INCVAL_100         0x50000000
 134 #define IXGBE_INCVAL_SHIFT_10GB  28
 135 #define IXGBE_INCVAL_SHIFT_1GB   24
 136 #define IXGBE_INCVAL_SHIFT_100   21
 137 #define IXGBE_INCVAL_SHIFT_82599 7
 138 #define IXGBE_INCPER_SHIFT_82599 24
 139
 140 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 141
 142 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 143 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 144 #define DEFAULT_ETAG_ETYPE                     0x893f
 145 #define IXGBE_ETAG_ETYPE                       0x00005084
 146 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 147 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 148 #define IXGBE_RAH_ADTYPE                       0x40000000
 149 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 150 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 151 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 152 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 153 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 154 #define IXGBE_VTEICR_MASK                      0x07
 155
 156 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 157 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 158
 159 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 160 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 161 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 162 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 163 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 164 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 165 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 166 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 167 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 168 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 169 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 170 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 171 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 172 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 177 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 178                                 int wait_to_complete);
 179 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 180                                 struct rte_eth_stats *stats);
 181 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 182                                 struct rte_eth_xstat *xstats, unsigned n);
 183 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 184                                   struct rte_eth_xstat *xstats, unsigned n);
 185 static int
 186 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 187                 uint64_t *values, unsigned int n);
 188 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 189 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 190 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 191         struct rte_eth_xstat_name *xstats_names,
 192         unsigned int size);
 193 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 194         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 195 static int ixgbe_dev_xstats_get_names_by_id(
 196         struct rte_eth_dev *dev,
 197         struct rte_eth_xstat_name *xstats_names,
 198         const uint64_t *ids,
 199         unsigned int limit);
 200 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 201                                              uint16_t queue_id,
 202                                              uint8_t stat_idx,
 203                                              uint8_t is_rx);
 204 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 205                                  size_t fw_size);
 206 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 207                                struct rte_eth_dev_info *dev_info);
 208 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 209 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 210                                  struct rte_eth_dev_info *dev_info);
 211 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 212
 213 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 214                 uint16_t vlan_id, int on);
 215 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 216                                enum rte_vlan_type vlan_type,
 217                                uint16_t tpid_id);
 218 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 219                 uint16_t queue, bool on);
 220 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 221                 int on);
 222 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 223 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 224 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 225 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 226 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 227
 228 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 230 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 231                                struct rte_eth_fc_conf *fc_conf);
 232 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 233                                struct rte_eth_fc_conf *fc_conf);
 234 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 235                 struct rte_eth_pfc_conf *pfc_conf);
 236 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 237                         struct rte_eth_rss_reta_entry64 *reta_conf,
 238                         uint16_t reta_size);
 239 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 240                         struct rte_eth_rss_reta_entry64 *reta_conf,
 241                         uint16_t reta_size);
 242 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 243 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 244 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 245 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 246 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 247 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 248                                       struct rte_intr_handle *handle);
 249 static void ixgbe_dev_interrupt_handler(void *param);
 250 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 251 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 252                          uint32_t index, uint32_t pool);
 253 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 254 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 255                                            struct ether_addr *mac_addr);
 256 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 257 static bool is_device_supported(struct rte_eth_dev *dev,
 258                                 struct rte_pci_driver *drv);
 259
 260 /* For Virtual Function support */
 261 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 262 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 263 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 264 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 265 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 266                                    int wait_to_complete);
 267 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 268 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 269 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 270 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 271 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 272 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 273                 struct rte_eth_stats *stats);
 274 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 275 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 276                 uint16_t vlan_id, int on);
 277 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 278                 uint16_t queue, int on);
 279 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 280 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 281 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 282                                             uint16_t queue_id);
 283 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 284                                              uint16_t queue_id);
 285 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 286                                  uint8_t queue, uint8_t msix_vector);
 287 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 288 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 289 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 290
 291 /* For Eth VMDQ APIs support */
 292 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 293                 ether_addr * mac_addr, uint8_t on);
 294 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 295 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 296                 struct rte_eth_mirror_conf *mirror_conf,
 297                 uint8_t rule_id, uint8_t on);
 298 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 299                 uint8_t rule_id);
 300 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 301                                           uint16_t queue_id);
 302 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 303                                            uint16_t queue_id);
 304 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 305                                uint8_t queue, uint8_t msix_vector);
 306 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 307
 308 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 309                                 struct ether_addr *mac_addr,
 310                                 uint32_t index, uint32_t pool);
 311 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 312 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 313                                              struct ether_addr *mac_addr);
 314 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 315                         struct rte_eth_syn_filter *filter);
 316 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 317                         enum rte_filter_op filter_op,
 318                         void *arg);
 319 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 320                         struct ixgbe_5tuple_filter *filter);
 321 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 322                         struct ixgbe_5tuple_filter *filter);
 323 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 327                         struct rte_eth_ntuple_filter *filter);
 328 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 329                                 enum rte_filter_op filter_op,
 330                                 void *arg);
 331 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 332                         struct rte_eth_ethertype_filter *filter);
 333 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 334                      enum rte_filter_type filter_type,
 335                      enum rte_filter_op filter_op,
 336                      void *arg);
 337 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 338
 339 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 340                                       struct ether_addr *mc_addr_set,
 341                                       uint32_t nb_mc_addr);
 342 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 343                                    struct rte_eth_dcb_info *dcb_info);
 344
 345 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 346 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 347                             struct rte_dev_reg_info *regs);
 348 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 349 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 350                                 struct rte_dev_eeprom_info *eeprom);
 351 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 352                                 struct rte_dev_eeprom_info *eeprom);
 353
 354 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 355 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 356                                 struct rte_dev_reg_info *regs);
 357
 358 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 359 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 360 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 361                                             struct timespec *timestamp,
 362                                             uint32_t flags);
 363 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 364                                             struct timespec *timestamp);
 365 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 366 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 367                                    struct timespec *timestamp);
 368 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 369                                    const struct timespec *timestamp);
 370 static void ixgbevf_dev_interrupt_handler(void *param);
 371
 372 static int ixgbe_dev_l2_tunnel_eth_type_conf
 373         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 374 static int ixgbe_dev_l2_tunnel_offload_set
 375         (struct rte_eth_dev *dev,
 376          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 377          uint32_t mask,
 378          uint8_t en);
 379 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 380                                              enum rte_filter_op filter_op,
 381                                              void *arg);
 382
 383 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 384                                          struct rte_eth_udp_tunnel *udp_tunnel);
 385 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 386                                          struct rte_eth_udp_tunnel *udp_tunnel);
 387 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 388 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 389
 390 /*
 391  * Define VF Stats MACRO for Non "cleared on read" register
 392  */
 393 #define UPDATE_VF_STAT(reg, last, cur)                          \
 394 {                                                               \
 395         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 396         cur += (latest - last) & UINT_MAX;                      \
 397         last = latest;                                          \
 398 }
 399
 400 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 401 {                                                                \
 402         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 403         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 404         u64 latest = ((new_msb << 32) | new_lsb);                \
 405         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 406         last = latest;                                           \
 407 }
 408
 409 #define IXGBE_SET_HWSTRIP(h, q) do {\
 410                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 411                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 412                 (h)->bitmap[idx] |= 1 << bit;\
 413         } while (0)
 414
 415 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 416                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 417                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 418                 (h)->bitmap[idx] &= ~(1 << bit);\
 419         } while (0)
 420
 421 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 422                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 423                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 424                 (r) = (h)->bitmap[idx] >> bit & 1;\
 425         } while (0)
 426
 427 /*
 428  * The set of PCI devices this driver supports
 429  */
 430 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 479 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 481 #endif
 482         { .vendor_id = 0, /* sentinel */ },
 483 };
 484
 485 /*
 486  * The set of PCI devices this driver supports (for 82599 VF)
 487  */
 488 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 492         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 499         { .vendor_id = 0, /* sentinel */ },
 500 };
 501
 502 static const struct rte_eth_desc_lim rx_desc_lim = {
 503         .nb_max = IXGBE_MAX_RING_DESC,
 504         .nb_min = IXGBE_MIN_RING_DESC,
 505         .nb_align = IXGBE_RXD_ALIGN,
 506 };
 507
 508 static const struct rte_eth_desc_lim tx_desc_lim = {
 509         .nb_max = IXGBE_MAX_RING_DESC,
 510         .nb_min = IXGBE_MIN_RING_DESC,
 511         .nb_align = IXGBE_TXD_ALIGN,
 512         .nb_seg_max = IXGBE_TX_MAX_SEG,
 513         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 514 };
 515
 516 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 517         .dev_configure        = ixgbe_dev_configure,
 518         .dev_start            = ixgbe_dev_start,
 519         .dev_stop             = ixgbe_dev_stop,
 520         .dev_set_link_up    = ixgbe_dev_set_link_up,
 521         .dev_set_link_down  = ixgbe_dev_set_link_down,
 522         .dev_close            = ixgbe_dev_close,
 523         .dev_reset            = ixgbe_dev_reset,
 524         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 525         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 526         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 527         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 528         .link_update          = ixgbe_dev_link_update,
 529         .stats_get            = ixgbe_dev_stats_get,
 530         .xstats_get           = ixgbe_dev_xstats_get,
 531         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 532         .stats_reset          = ixgbe_dev_stats_reset,
 533         .xstats_reset         = ixgbe_dev_xstats_reset,
 534         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 535         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 536         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 537         .fw_version_get       = ixgbe_fw_version_get,
 538         .dev_infos_get        = ixgbe_dev_info_get,
 539         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 540         .mtu_set              = ixgbe_dev_mtu_set,
 541         .vlan_filter_set      = ixgbe_vlan_filter_set,
 542         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 543         .vlan_offload_set     = ixgbe_vlan_offload_set,
 544         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 545         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 546         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 547         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 548         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 549         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 550         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 551         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 552         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 553         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 554         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 555         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 556         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 557         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 558         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 559         .dev_led_on           = ixgbe_dev_led_on,
 560         .dev_led_off          = ixgbe_dev_led_off,
 561         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 562         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 563         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 564         .mac_addr_add         = ixgbe_add_rar,
 565         .mac_addr_remove      = ixgbe_remove_rar,
 566         .mac_addr_set         = ixgbe_set_default_mac_addr,
 567         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 568         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 569         .mirror_rule_set      = ixgbe_mirror_rule_set,
 570         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 571         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 572         .reta_update          = ixgbe_dev_rss_reta_update,
 573         .reta_query           = ixgbe_dev_rss_reta_query,
 574         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 575         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 576         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 577         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 578         .rxq_info_get         = ixgbe_rxq_info_get,
 579         .txq_info_get         = ixgbe_txq_info_get,
 580         .timesync_enable      = ixgbe_timesync_enable,
 581         .timesync_disable     = ixgbe_timesync_disable,
 582         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 583         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 584         .get_reg              = ixgbe_get_regs,
 585         .get_eeprom_length    = ixgbe_get_eeprom_length,
 586         .get_eeprom           = ixgbe_get_eeprom,
 587         .set_eeprom           = ixgbe_set_eeprom,
 588         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 589         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 590         .timesync_read_time   = ixgbe_timesync_read_time,
 591         .timesync_write_time  = ixgbe_timesync_write_time,
 592         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 593         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 594         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 595         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 596         .tm_ops_get           = ixgbe_tm_ops_get,
 597 };
 598
 599 /*
 600  * dev_ops for virtual function, bare necessities for basic vf
 601  * operation have been implemented
 602  */
 603 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 604         .dev_configure        = ixgbevf_dev_configure,
 605         .dev_start            = ixgbevf_dev_start,
 606         .dev_stop             = ixgbevf_dev_stop,
 607         .link_update          = ixgbevf_dev_link_update,
 608         .stats_get            = ixgbevf_dev_stats_get,
 609         .xstats_get           = ixgbevf_dev_xstats_get,
 610         .stats_reset          = ixgbevf_dev_stats_reset,
 611         .xstats_reset         = ixgbevf_dev_stats_reset,
 612         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 613         .dev_close            = ixgbevf_dev_close,
 614         .dev_reset            = ixgbevf_dev_reset,
 615         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 616         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 617         .dev_infos_get        = ixgbevf_dev_info_get,
 618         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 619         .mtu_set              = ixgbevf_dev_set_mtu,
 620         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 621         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 622         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 623         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 624         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 625         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 626         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 627         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 628         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 629         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 630         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 631         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 632         .mac_addr_add         = ixgbevf_add_mac_addr,
 633         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 634         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 635         .rxq_info_get         = ixgbe_rxq_info_get,
 636         .txq_info_get         = ixgbe_txq_info_get,
 637         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 638         .get_reg              = ixgbevf_get_regs,
 639         .reta_update          = ixgbe_dev_rss_reta_update,
 640         .reta_query           = ixgbe_dev_rss_reta_query,
 641         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 642         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 643 };
 644
 645 /* store statistics names and its offset in stats structure */
 646 struct rte_ixgbe_xstats_name_off {
 647         char name[RTE_ETH_XSTATS_NAME_SIZE];
 648         unsigned offset;
 649 };
 650
 651 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 652         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 653         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 654         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 655         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 656         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 657         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 658         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 659         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 660         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 661         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 662         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 663         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 664         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 665         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 666         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 667                 prc1023)},
 668         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 669                 prc1522)},
 670         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 671         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 672         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 673         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 674         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 675         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 676         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 677         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 678         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 679         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 680         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 681         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 682         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 683         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 684         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 685         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 686         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 687                 ptc1023)},
 688         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 689                 ptc1522)},
 690         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 691         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 692         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 693         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 694
 695         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 696                 fdirustat_add)},
 697         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 698                 fdirustat_remove)},
 699         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 700                 fdirfstat_fadd)},
 701         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 702                 fdirfstat_fremove)},
 703         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 704                 fdirmatch)},
 705         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 706                 fdirmiss)},
 707
 708         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 709         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 710         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 711                 fclast)},
 712         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 713         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 714         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 715         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 716         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 717                 fcoe_noddp)},
 718         {"rx_fcoe_no_direct_data_placement_ext_buff",
 719                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 720
 721         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 722                 lxontxc)},
 723         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 724                 lxonrxc)},
 725         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 726                 lxofftxc)},
 727         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 728                 lxoffrxc)},
 729         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 730 };
 731
 732 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 733                            sizeof(rte_ixgbe_stats_strings[0]))
 734
 735 /* MACsec statistics */
 736 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 737         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 738                 out_pkts_untagged)},
 739         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 740                 out_pkts_encrypted)},
 741         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 742                 out_pkts_protected)},
 743         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 744                 out_octets_encrypted)},
 745         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 746                 out_octets_protected)},
 747         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_untagged)},
 749         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 750                 in_pkts_badtag)},
 751         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 752                 in_pkts_nosci)},
 753         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_unknownsci)},
 755         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 756                 in_octets_decrypted)},
 757         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 758                 in_octets_validated)},
 759         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 760                 in_pkts_unchecked)},
 761         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 762                 in_pkts_delayed)},
 763         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 764                 in_pkts_late)},
 765         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 766                 in_pkts_ok)},
 767         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 768                 in_pkts_invalid)},
 769         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 770                 in_pkts_notvalid)},
 771         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 772                 in_pkts_unusedsa)},
 773         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 774                 in_pkts_notusingsa)},
 775 };
 776
 777 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 778                            sizeof(rte_ixgbe_macsec_strings[0]))
 779
 780 /* Per-queue statistics */
 781 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 782         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 783         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 784         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 785         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 786 };
 787
 788 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 789                            sizeof(rte_ixgbe_rxq_strings[0]))
 790 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 791
 792 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 793         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 794         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 795         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 796                 pxon2offc)},
 797 };
 798
 799 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 800                            sizeof(rte_ixgbe_txq_strings[0]))
 801 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 802
 803 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 804         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 805 };
 806
 807 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 808                 sizeof(rte_ixgbevf_stats_strings[0]))
 809
 810 /**
 811  * Atomically reads the link status information from global
 812  * structure rte_eth_dev.
 813  *
 814  * @param dev
 815  *   - Pointer to the structure rte_eth_dev to read from.
 816  *   - Pointer to the buffer to be saved with the link status.
 817  *
 818  * @return
 819  *   - On success, zero.
 820  *   - On failure, negative value.
 821  */
 822 static inline int
 823 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 824                                 struct rte_eth_link *link)
 825 {
 826         struct rte_eth_link *dst = link;
 827         struct rte_eth_link *src = &(dev->data->dev_link);
 828
 829         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 830                                         *(uint64_t *)src) == 0)
 831                 return -1;
 832
 833         return 0;
 834 }
 835
 836 /**
 837  * Atomically writes the link status information into global
 838  * structure rte_eth_dev.
 839  *
 840  * @param dev
 841  *   - Pointer to the structure rte_eth_dev to read from.
 842  *   - Pointer to the buffer to be saved with the link status.
 843  *
 844  * @return
 845  *   - On success, zero.
 846  *   - On failure, negative value.
 847  */
 848 static inline int
 849 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 850                                 struct rte_eth_link *link)
 851 {
 852         struct rte_eth_link *dst = &(dev->data->dev_link);
 853         struct rte_eth_link *src = link;
 854
 855         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 856                                         *(uint64_t *)src) == 0)
 857                 return -1;
 858
 859         return 0;
 860 }
 861
 862 /*
 863  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 864  */
 865 static inline int
 866 ixgbe_is_sfp(struct ixgbe_hw *hw)
 867 {
 868         switch (hw->phy.type) {
 869         case ixgbe_phy_sfp_avago:
 870         case ixgbe_phy_sfp_ftl:
 871         case ixgbe_phy_sfp_intel:
 872         case ixgbe_phy_sfp_unknown:
 873         case ixgbe_phy_sfp_passive_tyco:
 874         case ixgbe_phy_sfp_passive_unknown:
 875                 return 1;
 876         default:
 877                 return 0;
 878         }
 879 }
 880
 881 static inline int32_t
 882 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 883 {
 884         uint32_t ctrl_ext;
 885         int32_t status;
 886
 887         status = ixgbe_reset_hw(hw);
 888
 889         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 890         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 891         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 892         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 893         IXGBE_WRITE_FLUSH(hw);
 894
 895         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 896                 status = IXGBE_SUCCESS;
 897         return status;
 898 }
 899
 900 static inline void
 901 ixgbe_enable_intr(struct rte_eth_dev *dev)
 902 {
 903         struct ixgbe_interrupt *intr =
 904                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 905         struct ixgbe_hw *hw =
 906                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 907
 908         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 909         IXGBE_WRITE_FLUSH(hw);
 910 }
 911
 912 /*
 913  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 914  */
 915 static void
 916 ixgbe_disable_intr(struct ixgbe_hw *hw)
 917 {
 918         PMD_INIT_FUNC_TRACE();
 919
 920         if (hw->mac.type == ixgbe_mac_82598EB) {
 921                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 922         } else {
 923                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 924                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 925                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 926         }
 927         IXGBE_WRITE_FLUSH(hw);
 928 }
 929
 930 /*
 931  * This function resets queue statistics mapping registers.
 932  * From Niantic datasheet, Initialization of Statistics section:
 933  * "...if software requires the queue counters, the RQSMR and TQSM registers
 934  * must be re-programmed following a device reset.
 935  */
 936 static void
 937 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 938 {
 939         uint32_t i;
 940
 941         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 942                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 943                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 944         }
 945 }
 946
 947
 948 static int
 949 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 950                                   uint16_t queue_id,
 951                                   uint8_t stat_idx,
 952                                   uint8_t is_rx)
 953 {
 954 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 955 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 956 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 957
 958         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 959         struct ixgbe_stat_mapping_registers *stat_mappings =
 960                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 961         uint32_t qsmr_mask = 0;
 962         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 963         uint32_t q_map;
 964         uint8_t n, offset;
 965
 966         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 967                 (hw->mac.type != ixgbe_mac_X540) &&
 968                 (hw->mac.type != ixgbe_mac_X550) &&
 969                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 970                 (hw->mac.type != ixgbe_mac_X550EM_a))
 971                 return -ENOSYS;
 972
 973         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 974                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 975                      queue_id, stat_idx);
 976
 977         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 978         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 979                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 980                 return -EIO;
 981         }
 982         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 983
 984         /* Now clear any previous stat_idx set */
 985         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 986         if (!is_rx)
 987                 stat_mappings->tqsm[n] &= ~clearing_mask;
 988         else
 989                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 990
 991         q_map = (uint32_t)stat_idx;
 992         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 993         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 994         if (!is_rx)
 995                 stat_mappings->tqsm[n] |= qsmr_mask;
 996         else
 997                 stat_mappings->rqsmr[n] |= qsmr_mask;
 998
 999         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1000                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1001                      queue_id, stat_idx);
1002         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1003                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1004
1005         /* Now write the mapping in the appropriate register */
1006         if (is_rx) {
1007                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1008                              stat_mappings->rqsmr[n], n);
1009                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1010         } else {
1011                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1012                              stat_mappings->tqsm[n], n);
1013                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1014         }
1015         return 0;
1016 }
1017
1018 static void
1019 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1020 {
1021         struct ixgbe_stat_mapping_registers *stat_mappings =
1022                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1023         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1024         int i;
1025
1026         /* write whatever was in stat mapping table to the NIC */
1027         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1028                 /* rx */
1029                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1030
1031                 /* tx */
1032                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1033         }
1034 }
1035
1036 static void
1037 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1038 {
1039         uint8_t i;
1040         struct ixgbe_dcb_tc_config *tc;
1041         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1042
1043         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1044         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1045         for (i = 0; i < dcb_max_tc; i++) {
1046                 tc = &dcb_config->tc_config[i];
1047                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1048                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1049                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1050                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1051                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1052                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1053                 tc->pfc = ixgbe_dcb_pfc_disabled;
1054         }
1055
1056         /* Initialize default user to priority mapping, UPx->TC0 */
1057         tc = &dcb_config->tc_config[0];
1058         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1059         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1060         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1061                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1062                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1063         }
1064         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1065         dcb_config->pfc_mode_enable = false;
1066         dcb_config->vt_mode = true;
1067         dcb_config->round_robin_enable = false;
1068         /* support all DCB capabilities in 82599 */
1069         dcb_config->support.capabilities = 0xFF;
1070
1071         /*we only support 4 Tcs for X540, X550 */
1072         if (hw->mac.type == ixgbe_mac_X540 ||
1073                 hw->mac.type == ixgbe_mac_X550 ||
1074                 hw->mac.type == ixgbe_mac_X550EM_x ||
1075                 hw->mac.type == ixgbe_mac_X550EM_a) {
1076                 dcb_config->num_tcs.pg_tcs = 4;
1077                 dcb_config->num_tcs.pfc_tcs = 4;
1078         }
1079 }
1080
1081 /*
1082  * Ensure that all locks are released before first NVM or PHY access
1083  */
1084 static void
1085 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1086 {
1087         uint16_t mask;
1088
1089         /*
1090          * Phy lock should not fail in this early stage. If this is the case,
1091          * it is due to an improper exit of the application.
1092          * So force the release of the faulty lock. Release of common lock
1093          * is done automatically by swfw_sync function.
1094          */
1095         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1096         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1097                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1098         }
1099         ixgbe_release_swfw_semaphore(hw, mask);
1100
1101         /*
1102          * These ones are more tricky since they are common to all ports; but
1103          * swfw_sync retries last long enough (1s) to be almost sure that if
1104          * lock can not be taken it is due to an improper lock of the
1105          * semaphore.
1106          */
1107         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1108         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1109                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1110         }
1111         ixgbe_release_swfw_semaphore(hw, mask);
1112 }
1113
1114 /*
1115  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1116  * It returns 0 on success.
1117  */
1118 static int
1119 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1120 {
1121         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1122         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1123         struct ixgbe_hw *hw =
1124                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1125         struct ixgbe_vfta *shadow_vfta =
1126                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1127         struct ixgbe_hwstrip *hwstrip =
1128                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1129         struct ixgbe_dcb_config *dcb_config =
1130                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1131         struct ixgbe_filter_info *filter_info =
1132                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1133         struct ixgbe_bw_conf *bw_conf =
1134                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1135         uint32_t ctrl_ext;
1136         uint16_t csum;
1137         int diag, i;
1138
1139         PMD_INIT_FUNC_TRACE();
1140
1141         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1142         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1143         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1144         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1145
1146         /*
1147          * For secondary processes, we don't initialise any further as primary
1148          * has already done this work. Only check we don't need a different
1149          * RX and TX function.
1150          */
1151         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1152                 struct ixgbe_tx_queue *txq;
1153                 /* TX queue function in primary, set by last queue initialized
1154                  * Tx queue may not initialized by primary process
1155                  */
1156                 if (eth_dev->data->tx_queues) {
1157                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1158                         ixgbe_set_tx_function(eth_dev, txq);
1159                 } else {
1160                         /* Use default TX function if we get here */
1161                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1162                                      "Using default TX function.");
1163                 }
1164
1165                 ixgbe_set_rx_function(eth_dev);
1166
1167                 return 0;
1168         }
1169
1170         rte_eth_copy_pci_info(eth_dev, pci_dev);
1171         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1172
1173         /* Vendor and Device ID need to be set before init of shared code */
1174         hw->device_id = pci_dev->id.device_id;
1175         hw->vendor_id = pci_dev->id.vendor_id;
1176         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1177         hw->allow_unsupported_sfp = 1;
1178
1179         /* Initialize the shared code (base driver) */
1180 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1181         diag = ixgbe_bypass_init_shared_code(hw);
1182 #else
1183         diag = ixgbe_init_shared_code(hw);
1184 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1185
1186         if (diag != IXGBE_SUCCESS) {
1187                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1188                 return -EIO;
1189         }
1190
1191         /* pick up the PCI bus settings for reporting later */
1192         ixgbe_get_bus_info(hw);
1193
1194         /* Unlock any pending hardware semaphore */
1195         ixgbe_swfw_lock_reset(hw);
1196
1197         /* Initialize DCB configuration*/
1198         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1199         ixgbe_dcb_init(hw, dcb_config);
1200         /* Get Hardware Flow Control setting */
1201         hw->fc.requested_mode = ixgbe_fc_full;
1202         hw->fc.current_mode = ixgbe_fc_full;
1203         hw->fc.pause_time = IXGBE_FC_PAUSE;
1204         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1205                 hw->fc.low_water[i] = IXGBE_FC_LO;
1206                 hw->fc.high_water[i] = IXGBE_FC_HI;
1207         }
1208         hw->fc.send_xon = 1;
1209
1210         /* Make sure we have a good EEPROM before we read from it */
1211         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1212         if (diag != IXGBE_SUCCESS) {
1213                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1214                 return -EIO;
1215         }
1216
1217 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1218         diag = ixgbe_bypass_init_hw(hw);
1219 #else
1220         diag = ixgbe_init_hw(hw);
1221 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1222
1223         /*
1224          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1225          * is called too soon after the kernel driver unbinding/binding occurs.
1226          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1227          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1228          * also called. See ixgbe_identify_phy_82599(). The reason for the
1229          * failure is not known, and only occuts when virtualisation features
1230          * are disabled in the bios. A delay of 100ms  was found to be enough by
1231          * trial-and-error, and is doubled to be safe.
1232          */
1233         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1234                 rte_delay_ms(200);
1235                 diag = ixgbe_init_hw(hw);
1236         }
1237
1238         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1239                 diag = IXGBE_SUCCESS;
1240
1241         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1242                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1243                              "LOM.  Please be aware there may be issues associated "
1244                              "with your hardware.");
1245                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1246                              "please contact your Intel or hardware representative "
1247                              "who provided you with this hardware.");
1248         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1249                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1250         if (diag) {
1251                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1252                 return -EIO;
1253         }
1254
1255         /* Reset the hw statistics */
1256         ixgbe_dev_stats_reset(eth_dev);
1257
1258         /* disable interrupt */
1259         ixgbe_disable_intr(hw);
1260
1261         /* reset mappings for queue statistics hw counters*/
1262         ixgbe_reset_qstat_mappings(hw);
1263
1264         /* Allocate memory for storing MAC addresses */
1265         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1266                                                hw->mac.num_rar_entries, 0);
1267         if (eth_dev->data->mac_addrs == NULL) {
1268                 PMD_INIT_LOG(ERR,
1269                              "Failed to allocate %u bytes needed to store "
1270                              "MAC addresses",
1271                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1272                 return -ENOMEM;
1273         }
1274         /* Copy the permanent MAC address */
1275         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1276                         &eth_dev->data->mac_addrs[0]);
1277
1278         /* Allocate memory for storing hash filter MAC addresses */
1279         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1280                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1281         if (eth_dev->data->hash_mac_addrs == NULL) {
1282                 PMD_INIT_LOG(ERR,
1283                              "Failed to allocate %d bytes needed to store MAC addresses",
1284                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1285                 return -ENOMEM;
1286         }
1287
1288         /* initialize the vfta */
1289         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1290
1291         /* initialize the hw strip bitmap*/
1292         memset(hwstrip, 0, sizeof(*hwstrip));
1293
1294         /* initialize PF if max_vfs not zero */
1295         ixgbe_pf_host_init(eth_dev);
1296
1297         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1298         /* let hardware know driver is loaded */
1299         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1300         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1301         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1302         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1303         IXGBE_WRITE_FLUSH(hw);
1304
1305         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1306                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1307                              (int) hw->mac.type, (int) hw->phy.type,
1308                              (int) hw->phy.sfp_type);
1309         else
1310                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1311                              (int) hw->mac.type, (int) hw->phy.type);
1312
1313         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1314                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1315                      pci_dev->id.device_id);
1316
1317         rte_intr_callback_register(intr_handle,
1318                                    ixgbe_dev_interrupt_handler, eth_dev);
1319
1320         /* enable uio/vfio intr/eventfd mapping */
1321         rte_intr_enable(intr_handle);
1322
1323         /* enable support intr */
1324         ixgbe_enable_intr(eth_dev);
1325
1326         /* initialize filter info */
1327         memset(filter_info, 0,
1328                sizeof(struct ixgbe_filter_info));
1329
1330         /* initialize 5tuple filter list */
1331         TAILQ_INIT(&filter_info->fivetuple_list);
1332
1333         /* initialize flow director filter list & hash */
1334         ixgbe_fdir_filter_init(eth_dev);
1335
1336         /* initialize l2 tunnel filter list & hash */
1337         ixgbe_l2_tn_filter_init(eth_dev);
1338
1339         /* initialize flow filter lists */
1340         ixgbe_filterlist_init();
1341
1342         /* initialize bandwidth configuration info */
1343         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1344
1345         /* initialize Traffic Manager configuration */
1346         ixgbe_tm_conf_init(eth_dev);
1347
1348         return 0;
1349 }
1350
1351 static int
1352 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1353 {
1354         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1355         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1356         struct ixgbe_hw *hw;
1357
1358         PMD_INIT_FUNC_TRACE();
1359
1360         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1361                 return -EPERM;
1362
1363         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1364
1365         if (hw->adapter_stopped == 0)
1366                 ixgbe_dev_close(eth_dev);
1367
1368         eth_dev->dev_ops = NULL;
1369         eth_dev->rx_pkt_burst = NULL;
1370         eth_dev->tx_pkt_burst = NULL;
1371
1372         /* Unlock any pending hardware semaphore */
1373         ixgbe_swfw_lock_reset(hw);
1374
1375         /* disable uio intr before callback unregister */
1376         rte_intr_disable(intr_handle);
1377         rte_intr_callback_unregister(intr_handle,
1378                                      ixgbe_dev_interrupt_handler, eth_dev);
1379
1380         /* uninitialize PF if max_vfs not zero */
1381         ixgbe_pf_host_uninit(eth_dev);
1382
1383         rte_free(eth_dev->data->mac_addrs);
1384         eth_dev->data->mac_addrs = NULL;
1385
1386         rte_free(eth_dev->data->hash_mac_addrs);
1387         eth_dev->data->hash_mac_addrs = NULL;
1388
1389         /* remove all the fdir filters & hash */
1390         ixgbe_fdir_filter_uninit(eth_dev);
1391
1392         /* remove all the L2 tunnel filters & hash */
1393         ixgbe_l2_tn_filter_uninit(eth_dev);
1394
1395         /* Remove all ntuple filters of the device */
1396         ixgbe_ntuple_filter_uninit(eth_dev);
1397
1398         /* clear all the filters list */
1399         ixgbe_filterlist_flush();
1400
1401         /* Remove all Traffic Manager configuration */
1402         ixgbe_tm_conf_uninit(eth_dev);
1403
1404         return 0;
1405 }
1406
1407 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1408 {
1409         struct ixgbe_filter_info *filter_info =
1410                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1411         struct ixgbe_5tuple_filter *p_5tuple;
1412
1413         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1414                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1415                              p_5tuple,
1416                              entries);
1417                 rte_free(p_5tuple);
1418         }
1419         memset(filter_info->fivetuple_mask, 0,
1420                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1421
1422         return 0;
1423 }
1424
1425 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1426 {
1427         struct ixgbe_hw_fdir_info *fdir_info =
1428                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1429         struct ixgbe_fdir_filter *fdir_filter;
1430
1431                 if (fdir_info->hash_map)
1432                 rte_free(fdir_info->hash_map);
1433         if (fdir_info->hash_handle)
1434                 rte_hash_free(fdir_info->hash_handle);
1435
1436         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1437                 TAILQ_REMOVE(&fdir_info->fdir_list,
1438                              fdir_filter,
1439                              entries);
1440                 rte_free(fdir_filter);
1441         }
1442
1443         return 0;
1444 }
1445
1446 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1447 {
1448         struct ixgbe_l2_tn_info *l2_tn_info =
1449                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1450         struct ixgbe_l2_tn_filter *l2_tn_filter;
1451
1452         if (l2_tn_info->hash_map)
1453                 rte_free(l2_tn_info->hash_map);
1454         if (l2_tn_info->hash_handle)
1455                 rte_hash_free(l2_tn_info->hash_handle);
1456
1457         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1458                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1459                              l2_tn_filter,
1460                              entries);
1461                 rte_free(l2_tn_filter);
1462         }
1463
1464         return 0;
1465 }
1466
1467 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1468 {
1469         struct ixgbe_hw_fdir_info *fdir_info =
1470                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1471         char fdir_hash_name[RTE_HASH_NAMESIZE];
1472         struct rte_hash_parameters fdir_hash_params = {
1473                 .name = fdir_hash_name,
1474                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1475                 .key_len = sizeof(union ixgbe_atr_input),
1476                 .hash_func = rte_hash_crc,
1477                 .hash_func_init_val = 0,
1478                 .socket_id = rte_socket_id(),
1479         };
1480
1481         TAILQ_INIT(&fdir_info->fdir_list);
1482         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1483                  "fdir_%s", eth_dev->device->name);
1484         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1485         if (!fdir_info->hash_handle) {
1486                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1487                 return -EINVAL;
1488         }
1489         fdir_info->hash_map = rte_zmalloc("ixgbe",
1490                                           sizeof(struct ixgbe_fdir_filter *) *
1491                                           IXGBE_MAX_FDIR_FILTER_NUM,
1492                                           0);
1493         if (!fdir_info->hash_map) {
1494                 PMD_INIT_LOG(ERR,
1495                              "Failed to allocate memory for fdir hash map!");
1496                 return -ENOMEM;
1497         }
1498         fdir_info->mask_added = FALSE;
1499
1500         return 0;
1501 }
1502
1503 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1504 {
1505         struct ixgbe_l2_tn_info *l2_tn_info =
1506                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1507         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1508         struct rte_hash_parameters l2_tn_hash_params = {
1509                 .name = l2_tn_hash_name,
1510                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1511                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1512                 .hash_func = rte_hash_crc,
1513                 .hash_func_init_val = 0,
1514                 .socket_id = rte_socket_id(),
1515         };
1516
1517         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1518         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1519                  "l2_tn_%s", eth_dev->device->name);
1520         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1521         if (!l2_tn_info->hash_handle) {
1522                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1523                 return -EINVAL;
1524         }
1525         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1526                                    sizeof(struct ixgbe_l2_tn_filter *) *
1527                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1528                                    0);
1529         if (!l2_tn_info->hash_map) {
1530                 PMD_INIT_LOG(ERR,
1531                         "Failed to allocate memory for L2 TN hash map!");
1532                 return -ENOMEM;
1533         }
1534         l2_tn_info->e_tag_en = FALSE;
1535         l2_tn_info->e_tag_fwd_en = FALSE;
1536         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1537
1538         return 0;
1539 }
1540 /*
1541  * Negotiate mailbox API version with the PF.
1542  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1543  * Then we try to negotiate starting with the most recent one.
1544  * If all negotiation attempts fail, then we will proceed with
1545  * the default one (ixgbe_mbox_api_10).
1546  */
1547 static void
1548 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1549 {
1550         int32_t i;
1551
1552         /* start with highest supported, proceed down */
1553         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1554                 ixgbe_mbox_api_12,
1555                 ixgbe_mbox_api_11,
1556                 ixgbe_mbox_api_10,
1557         };
1558
1559         for (i = 0;
1560                         i != RTE_DIM(sup_ver) &&
1561                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1562                         i++)
1563                 ;
1564 }
1565
1566 static void
1567 generate_random_mac_addr(struct ether_addr *mac_addr)
1568 {
1569         uint64_t random;
1570
1571         /* Set Organizationally Unique Identifier (OUI) prefix. */
1572         mac_addr->addr_bytes[0] = 0x00;
1573         mac_addr->addr_bytes[1] = 0x09;
1574         mac_addr->addr_bytes[2] = 0xC0;
1575         /* Force indication of locally assigned MAC address. */
1576         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1577         /* Generate the last 3 bytes of the MAC address with a random number. */
1578         random = rte_rand();
1579         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1580 }
1581
1582 /*
1583  * Virtual Function device init
1584  */
1585 static int
1586 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1587 {
1588         int diag;
1589         uint32_t tc, tcs;
1590         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1591         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1592         struct ixgbe_hw *hw =
1593                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1594         struct ixgbe_vfta *shadow_vfta =
1595                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1596         struct ixgbe_hwstrip *hwstrip =
1597                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1598         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1599
1600         PMD_INIT_FUNC_TRACE();
1601
1602         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1603         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1604         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1605
1606         /* for secondary processes, we don't initialise any further as primary
1607          * has already done this work. Only check we don't need a different
1608          * RX function
1609          */
1610         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1611                 struct ixgbe_tx_queue *txq;
1612                 /* TX queue function in primary, set by last queue initialized
1613                  * Tx queue may not initialized by primary process
1614                  */
1615                 if (eth_dev->data->tx_queues) {
1616                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1617                         ixgbe_set_tx_function(eth_dev, txq);
1618                 } else {
1619                         /* Use default TX function if we get here */
1620                         PMD_INIT_LOG(NOTICE,
1621                                      "No TX queues configured yet. Using default TX function.");
1622                 }
1623
1624                 ixgbe_set_rx_function(eth_dev);
1625
1626                 return 0;
1627         }
1628
1629         rte_eth_copy_pci_info(eth_dev, pci_dev);
1630         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1631
1632         hw->device_id = pci_dev->id.device_id;
1633         hw->vendor_id = pci_dev->id.vendor_id;
1634         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1635
1636         /* initialize the vfta */
1637         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1638
1639         /* initialize the hw strip bitmap*/
1640         memset(hwstrip, 0, sizeof(*hwstrip));
1641
1642         /* Initialize the shared code (base driver) */
1643         diag = ixgbe_init_shared_code(hw);
1644         if (diag != IXGBE_SUCCESS) {
1645                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1646                 return -EIO;
1647         }
1648
1649         /* init_mailbox_params */
1650         hw->mbx.ops.init_params(hw);
1651
1652         /* Reset the hw statistics */
1653         ixgbevf_dev_stats_reset(eth_dev);
1654
1655         /* Disable the interrupts for VF */
1656         ixgbevf_intr_disable(hw);
1657
1658         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1659         diag = hw->mac.ops.reset_hw(hw);
1660
1661         /*
1662          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1663          * the underlying PF driver has not assigned a MAC address to the VF.
1664          * In this case, assign a random MAC address.
1665          */
1666         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1667                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1668                 return diag;
1669         }
1670
1671         /* negotiate mailbox API version to use with the PF. */
1672         ixgbevf_negotiate_api(hw);
1673
1674         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1675         ixgbevf_get_queues(hw, &tcs, &tc);
1676
1677         /* Allocate memory for storing MAC addresses */
1678         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1679                                                hw->mac.num_rar_entries, 0);
1680         if (eth_dev->data->mac_addrs == NULL) {
1681                 PMD_INIT_LOG(ERR,
1682                              "Failed to allocate %u bytes needed to store "
1683                              "MAC addresses",
1684                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1685                 return -ENOMEM;
1686         }
1687
1688         /* Generate a random MAC address, if none was assigned by PF. */
1689         if (is_zero_ether_addr(perm_addr)) {
1690                 generate_random_mac_addr(perm_addr);
1691                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1692                 if (diag) {
1693                         rte_free(eth_dev->data->mac_addrs);
1694                         eth_dev->data->mac_addrs = NULL;
1695                         return diag;
1696                 }
1697                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1698                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1699                              "%02x:%02x:%02x:%02x:%02x:%02x",
1700                              perm_addr->addr_bytes[0],
1701                              perm_addr->addr_bytes[1],
1702                              perm_addr->addr_bytes[2],
1703                              perm_addr->addr_bytes[3],
1704                              perm_addr->addr_bytes[4],
1705                              perm_addr->addr_bytes[5]);
1706         }
1707
1708         /* Copy the permanent MAC address */
1709         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1710
1711         /* reset the hardware with the new settings */
1712         diag = hw->mac.ops.start_hw(hw);
1713         switch (diag) {
1714         case  0:
1715                 break;
1716
1717         default:
1718                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1719                 return -EIO;
1720         }
1721
1722         rte_intr_callback_register(intr_handle,
1723                                    ixgbevf_dev_interrupt_handler, eth_dev);
1724         rte_intr_enable(intr_handle);
1725         ixgbevf_intr_enable(hw);
1726
1727         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1728                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1729                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1730
1731         return 0;
1732 }
1733
1734 /* Virtual Function device uninit */
1735
1736 static int
1737 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1738 {
1739         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1740         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1741         struct ixgbe_hw *hw;
1742
1743         PMD_INIT_FUNC_TRACE();
1744
1745         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1746                 return -EPERM;
1747
1748         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1749
1750         if (hw->adapter_stopped == 0)
1751                 ixgbevf_dev_close(eth_dev);
1752
1753         eth_dev->dev_ops = NULL;
1754         eth_dev->rx_pkt_burst = NULL;
1755         eth_dev->tx_pkt_burst = NULL;
1756
1757         /* Disable the interrupts for VF */
1758         ixgbevf_intr_disable(hw);
1759
1760         rte_free(eth_dev->data->mac_addrs);
1761         eth_dev->data->mac_addrs = NULL;
1762
1763         rte_intr_disable(intr_handle);
1764         rte_intr_callback_unregister(intr_handle,
1765                                      ixgbevf_dev_interrupt_handler, eth_dev);
1766
1767         return 0;
1768 }
1769
1770 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1771         struct rte_pci_device *pci_dev)
1772 {
1773         return rte_eth_dev_pci_generic_probe(pci_dev,
1774                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1775 }
1776
1777 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1778 {
1779         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1780 }
1781
1782 static struct rte_pci_driver rte_ixgbe_pmd = {
1783         .id_table = pci_id_ixgbe_map,
1784         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1785         .probe = eth_ixgbe_pci_probe,
1786         .remove = eth_ixgbe_pci_remove,
1787 };
1788
1789 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1790         struct rte_pci_device *pci_dev)
1791 {
1792         return rte_eth_dev_pci_generic_probe(pci_dev,
1793                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1794 }
1795
1796 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1797 {
1798         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1799 }
1800
1801 /*
1802  * virtual function driver struct
1803  */
1804 static struct rte_pci_driver rte_ixgbevf_pmd = {
1805         .id_table = pci_id_ixgbevf_map,
1806         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1807         .probe = eth_ixgbevf_pci_probe,
1808         .remove = eth_ixgbevf_pci_remove,
1809 };
1810
1811 static int
1812 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1813 {
1814         struct ixgbe_hw *hw =
1815                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1816         struct ixgbe_vfta *shadow_vfta =
1817                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1818         uint32_t vfta;
1819         uint32_t vid_idx;
1820         uint32_t vid_bit;
1821
1822         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1823         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1824         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1825         if (on)
1826                 vfta |= vid_bit;
1827         else
1828                 vfta &= ~vid_bit;
1829         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1830
1831         /* update local VFTA copy */
1832         shadow_vfta->vfta[vid_idx] = vfta;
1833
1834         return 0;
1835 }
1836
1837 static void
1838 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1839 {
1840         if (on)
1841                 ixgbe_vlan_hw_strip_enable(dev, queue);
1842         else
1843                 ixgbe_vlan_hw_strip_disable(dev, queue);
1844 }
1845
1846 static int
1847 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1848                     enum rte_vlan_type vlan_type,
1849                     uint16_t tpid)
1850 {
1851         struct ixgbe_hw *hw =
1852                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1853         int ret = 0;
1854         uint32_t reg;
1855         uint32_t qinq;
1856
1857         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1858         qinq &= IXGBE_DMATXCTL_GDV;
1859
1860         switch (vlan_type) {
1861         case ETH_VLAN_TYPE_INNER:
1862                 if (qinq) {
1863                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1864                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1865                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1866                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1867                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1868                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1869                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1870                 } else {
1871                         ret = -ENOTSUP;
1872                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1873                                     " by single VLAN");
1874                 }
1875                 break;
1876         case ETH_VLAN_TYPE_OUTER:
1877                 if (qinq) {
1878                         /* Only the high 16-bits is valid */
1879                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1880                                         IXGBE_EXVET_VET_EXT_SHIFT);
1881                 } else {
1882                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1883                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1884                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1885                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1886                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1887                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1888                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1889                 }
1890
1891                 break;
1892         default:
1893                 ret = -EINVAL;
1894                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1895                 break;
1896         }
1897
1898         return ret;
1899 }
1900
1901 void
1902 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1903 {
1904         struct ixgbe_hw *hw =
1905                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1906         uint32_t vlnctrl;
1907
1908         PMD_INIT_FUNC_TRACE();
1909
1910         /* Filter Table Disable */
1911         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1912         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1913
1914         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1915 }
1916
1917 void
1918 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1919 {
1920         struct ixgbe_hw *hw =
1921                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         struct ixgbe_vfta *shadow_vfta =
1923                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1924         uint32_t vlnctrl;
1925         uint16_t i;
1926
1927         PMD_INIT_FUNC_TRACE();
1928
1929         /* Filter Table Enable */
1930         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1931         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1932         vlnctrl |= IXGBE_VLNCTRL_VFE;
1933
1934         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1935
1936         /* write whatever is in local vfta copy */
1937         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1938                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1939 }
1940
1941 static void
1942 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1943 {
1944         struct ixgbe_hwstrip *hwstrip =
1945                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1946         struct ixgbe_rx_queue *rxq;
1947
1948         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1949                 return;
1950
1951         if (on)
1952                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1953         else
1954                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1955
1956         if (queue >= dev->data->nb_rx_queues)
1957                 return;
1958
1959         rxq = dev->data->rx_queues[queue];
1960
1961         if (on)
1962                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1963         else
1964                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1965 }
1966
1967 static void
1968 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1969 {
1970         struct ixgbe_hw *hw =
1971                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1972         uint32_t ctrl;
1973
1974         PMD_INIT_FUNC_TRACE();
1975
1976         if (hw->mac.type == ixgbe_mac_82598EB) {
1977                 /* No queue level support */
1978                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1979                 return;
1980         }
1981
1982         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1983         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1984         ctrl &= ~IXGBE_RXDCTL_VME;
1985         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1986
1987         /* record those setting for HW strip per queue */
1988         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1989 }
1990
1991 static void
1992 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1993 {
1994         struct ixgbe_hw *hw =
1995                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1996         uint32_t ctrl;
1997
1998         PMD_INIT_FUNC_TRACE();
1999
2000         if (hw->mac.type == ixgbe_mac_82598EB) {
2001                 /* No queue level supported */
2002                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2003                 return;
2004         }
2005
2006         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2007         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2008         ctrl |= IXGBE_RXDCTL_VME;
2009         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2010
2011         /* record those setting for HW strip per queue */
2012         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2013 }
2014
2015 void
2016 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2017 {
2018         struct ixgbe_hw *hw =
2019                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2020         uint32_t ctrl;
2021         uint16_t i;
2022         struct ixgbe_rx_queue *rxq;
2023
2024         PMD_INIT_FUNC_TRACE();
2025
2026         if (hw->mac.type == ixgbe_mac_82598EB) {
2027                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2028                 ctrl &= ~IXGBE_VLNCTRL_VME;
2029                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2030         } else {
2031                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2032                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2033                         rxq = dev->data->rx_queues[i];
2034                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2035                         ctrl &= ~IXGBE_RXDCTL_VME;
2036                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2037
2038                         /* record those setting for HW strip per queue */
2039                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2040                 }
2041         }
2042 }
2043
2044 void
2045 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2046 {
2047         struct ixgbe_hw *hw =
2048                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2049         uint32_t ctrl;
2050         uint16_t i;
2051         struct ixgbe_rx_queue *rxq;
2052
2053         PMD_INIT_FUNC_TRACE();
2054
2055         if (hw->mac.type == ixgbe_mac_82598EB) {
2056                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2057                 ctrl |= IXGBE_VLNCTRL_VME;
2058                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2059         } else {
2060                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2061                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2062                         rxq = dev->data->rx_queues[i];
2063                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2064                         ctrl |= IXGBE_RXDCTL_VME;
2065                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2066
2067                         /* record those setting for HW strip per queue */
2068                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2069                 }
2070         }
2071 }
2072
2073 static void
2074 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2075 {
2076         struct ixgbe_hw *hw =
2077                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2078         uint32_t ctrl;
2079
2080         PMD_INIT_FUNC_TRACE();
2081
2082         /* DMATXCTRL: Geric Double VLAN Disable */
2083         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2084         ctrl &= ~IXGBE_DMATXCTL_GDV;
2085         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2086
2087         /* CTRL_EXT: Global Double VLAN Disable */
2088         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2089         ctrl &= ~IXGBE_EXTENDED_VLAN;
2090         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2091
2092 }
2093
2094 static void
2095 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2096 {
2097         struct ixgbe_hw *hw =
2098                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2099         uint32_t ctrl;
2100
2101         PMD_INIT_FUNC_TRACE();
2102
2103         /* DMATXCTRL: Geric Double VLAN Enable */
2104         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2105         ctrl |= IXGBE_DMATXCTL_GDV;
2106         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2107
2108         /* CTRL_EXT: Global Double VLAN Enable */
2109         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2110         ctrl |= IXGBE_EXTENDED_VLAN;
2111         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2112
2113         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2114         if (hw->mac.type == ixgbe_mac_X550 ||
2115             hw->mac.type == ixgbe_mac_X550EM_x ||
2116             hw->mac.type == ixgbe_mac_X550EM_a) {
2117                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2118                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2119                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2120         }
2121
2122         /*
2123          * VET EXT field in the EXVET register = 0x8100 by default
2124          * So no need to change. Same to VT field of DMATXCTL register
2125          */
2126 }
2127
2128 static void
2129 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2130 {
2131         if (mask & ETH_VLAN_STRIP_MASK) {
2132                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2133                         ixgbe_vlan_hw_strip_enable_all(dev);
2134                 else
2135                         ixgbe_vlan_hw_strip_disable_all(dev);
2136         }
2137
2138         if (mask & ETH_VLAN_FILTER_MASK) {
2139                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2140                         ixgbe_vlan_hw_filter_enable(dev);
2141                 else
2142                         ixgbe_vlan_hw_filter_disable(dev);
2143         }
2144
2145         if (mask & ETH_VLAN_EXTEND_MASK) {
2146                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2147                         ixgbe_vlan_hw_extend_enable(dev);
2148                 else
2149                         ixgbe_vlan_hw_extend_disable(dev);
2150         }
2151 }
2152
2153 static void
2154 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2155 {
2156         struct ixgbe_hw *hw =
2157                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2158         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2159         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2160
2161         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2162         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2163 }
2164
2165 static int
2166 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2167 {
2168         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2169
2170         switch (nb_rx_q) {
2171         case 1:
2172         case 2:
2173                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2174                 break;
2175         case 4:
2176                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2177                 break;
2178         default:
2179                 return -EINVAL;
2180         }
2181
2182         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2183         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2184
2185         return 0;
2186 }
2187
2188 static int
2189 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2190 {
2191         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2192         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2193         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2194         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2195
2196         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2197                 /* check multi-queue mode */
2198                 switch (dev_conf->rxmode.mq_mode) {
2199                 case ETH_MQ_RX_VMDQ_DCB:
2200                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2201                         break;
2202                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2203                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2204                         PMD_INIT_LOG(ERR, "SRIOV active,"
2205                                         " unsupported mq_mode rx %d.",
2206                                         dev_conf->rxmode.mq_mode);
2207                         return -EINVAL;
2208                 case ETH_MQ_RX_RSS:
2209                 case ETH_MQ_RX_VMDQ_RSS:
2210                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2211                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2212                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2213                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2214                                                 " invalid queue number"
2215                                                 " for VMDQ RSS, allowed"
2216                                                 " value are 1, 2 or 4.");
2217                                         return -EINVAL;
2218                                 }
2219                         break;
2220                 case ETH_MQ_RX_VMDQ_ONLY:
2221                 case ETH_MQ_RX_NONE:
2222                         /* if nothing mq mode configure, use default scheme */
2223                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2224                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2225                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2226                         break;
2227                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2228                         /* SRIOV only works in VMDq enable mode */
2229                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2230                                         " wrong mq_mode rx %d.",
2231                                         dev_conf->rxmode.mq_mode);
2232                         return -EINVAL;
2233                 }
2234
2235                 switch (dev_conf->txmode.mq_mode) {
2236                 case ETH_MQ_TX_VMDQ_DCB:
2237                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2238                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2239                         break;
2240                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2241                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2242                         break;
2243                 }
2244
2245                 /* check valid queue number */
2246                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2247                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2248                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2249                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2250                                         " must be less than or equal to %d.",
2251                                         nb_rx_q, nb_tx_q,
2252                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2253                         return -EINVAL;
2254                 }
2255         } else {
2256                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2257                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2258                                           " not supported.");
2259                         return -EINVAL;
2260                 }
2261                 /* check configuration for vmdb+dcb mode */
2262                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2263                         const struct rte_eth_vmdq_dcb_conf *conf;
2264
2265                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2266                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2267                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2268                                 return -EINVAL;
2269                         }
2270                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2271                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2272                                conf->nb_queue_pools == ETH_32_POOLS)) {
2273                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2274                                                 " nb_queue_pools must be %d or %d.",
2275                                                 ETH_16_POOLS, ETH_32_POOLS);
2276                                 return -EINVAL;
2277                         }
2278                 }
2279                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2280                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2281
2282                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2283                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2284                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2285                                 return -EINVAL;
2286                         }
2287                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2288                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2289                                conf->nb_queue_pools == ETH_32_POOLS)) {
2290                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2291                                                 " nb_queue_pools != %d and"
2292                                                 " nb_queue_pools != %d.",
2293                                                 ETH_16_POOLS, ETH_32_POOLS);
2294                                 return -EINVAL;
2295                         }
2296                 }
2297
2298                 /* For DCB mode check our configuration before we go further */
2299                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2300                         const struct rte_eth_dcb_rx_conf *conf;
2301
2302                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2303                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2304                                                  IXGBE_DCB_NB_QUEUES);
2305                                 return -EINVAL;
2306                         }
2307                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2308                         if (!(conf->nb_tcs == ETH_4_TCS ||
2309                                conf->nb_tcs == ETH_8_TCS)) {
2310                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2311                                                 " and nb_tcs != %d.",
2312                                                 ETH_4_TCS, ETH_8_TCS);
2313                                 return -EINVAL;
2314                         }
2315                 }
2316
2317                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2318                         const struct rte_eth_dcb_tx_conf *conf;
2319
2320                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2321                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2322                                                  IXGBE_DCB_NB_QUEUES);
2323                                 return -EINVAL;
2324                         }
2325                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2326                         if (!(conf->nb_tcs == ETH_4_TCS ||
2327                                conf->nb_tcs == ETH_8_TCS)) {
2328                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2329                                                 " and nb_tcs != %d.",
2330                                                 ETH_4_TCS, ETH_8_TCS);
2331                                 return -EINVAL;
2332                         }
2333                 }
2334
2335                 /*
2336                  * When DCB/VT is off, maximum number of queues changes,
2337                  * except for 82598EB, which remains constant.
2338                  */
2339                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2340                                 hw->mac.type != ixgbe_mac_82598EB) {
2341                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2342                                 PMD_INIT_LOG(ERR,
2343                                              "Neither VT nor DCB are enabled, "
2344                                              "nb_tx_q > %d.",
2345                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2346                                 return -EINVAL;
2347                         }
2348                 }
2349         }
2350         return 0;
2351 }
2352
2353 static int
2354 ixgbe_dev_configure(struct rte_eth_dev *dev)
2355 {
2356         struct ixgbe_interrupt *intr =
2357                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2358         struct ixgbe_adapter *adapter =
2359                 (struct ixgbe_adapter *)dev->data->dev_private;
2360         int ret;
2361
2362         PMD_INIT_FUNC_TRACE();
2363         /* multipe queue mode checking */
2364         ret  = ixgbe_check_mq_mode(dev);
2365         if (ret != 0) {
2366                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2367                             ret);
2368                 return ret;
2369         }
2370
2371         /* set flag to update link status after init */
2372         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2373
2374         /*
2375          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2376          * allocation or vector Rx preconditions we will reset it.
2377          */
2378         adapter->rx_bulk_alloc_allowed = true;
2379         adapter->rx_vec_allowed = true;
2380
2381         return 0;
2382 }
2383
2384 static void
2385 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2386 {
2387         struct ixgbe_hw *hw =
2388                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2389         struct ixgbe_interrupt *intr =
2390                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2391         uint32_t gpie;
2392
2393         /* only set up it on X550EM_X */
2394         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2395                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2396                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2397                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2398                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2399                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2400         }
2401 }
2402
2403 int
2404 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2405                         uint16_t tx_rate, uint64_t q_msk)
2406 {
2407         struct ixgbe_hw *hw;
2408         struct ixgbe_vf_info *vfinfo;
2409         struct rte_eth_link link;
2410         uint8_t  nb_q_per_pool;
2411         uint32_t queue_stride;
2412         uint32_t queue_idx, idx = 0, vf_idx;
2413         uint32_t queue_end;
2414         uint16_t total_rate = 0;
2415         struct rte_pci_device *pci_dev;
2416
2417         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2418         rte_eth_link_get_nowait(dev->data->port_id, &link);
2419
2420         if (vf >= pci_dev->max_vfs)
2421                 return -EINVAL;
2422
2423         if (tx_rate > link.link_speed)
2424                 return -EINVAL;
2425
2426         if (q_msk == 0)
2427                 return 0;
2428
2429         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2430         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2431         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2432         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2433         queue_idx = vf * queue_stride;
2434         queue_end = queue_idx + nb_q_per_pool - 1;
2435         if (queue_end >= hw->mac.max_tx_queues)
2436                 return -EINVAL;
2437
2438         if (vfinfo) {
2439                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2440                         if (vf_idx == vf)
2441                                 continue;
2442                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2443                                 idx++)
2444                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2445                 }
2446         } else {
2447                 return -EINVAL;
2448         }
2449
2450         /* Store tx_rate for this vf. */
2451         for (idx = 0; idx < nb_q_per_pool; idx++) {
2452                 if (((uint64_t)0x1 << idx) & q_msk) {
2453                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2454                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2455                         total_rate += tx_rate;
2456                 }
2457         }
2458
2459         if (total_rate > dev->data->dev_link.link_speed) {
2460                 /* Reset stored TX rate of the VF if it causes exceed
2461                  * link speed.
2462                  */
2463                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2464                 return -EINVAL;
2465         }
2466
2467         /* Set RTTBCNRC of each queue/pool for vf X  */
2468         for (; queue_idx <= queue_end; queue_idx++) {
2469                 if (0x1 & q_msk)
2470                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2471                 q_msk = q_msk >> 1;
2472         }
2473
2474         return 0;
2475 }
2476
2477 /*
2478  * Configure device link speed and setup link.
2479  * It returns 0 on success.
2480  */
2481 static int
2482 ixgbe_dev_start(struct rte_eth_dev *dev)
2483 {
2484         struct ixgbe_hw *hw =
2485                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2486         struct ixgbe_vf_info *vfinfo =
2487                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2488         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2489         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2490         uint32_t intr_vector = 0;
2491         int err, link_up = 0, negotiate = 0;
2492         uint32_t speed = 0;
2493         int mask = 0;
2494         int status;
2495         uint16_t vf, idx;
2496         uint32_t *link_speeds;
2497         struct ixgbe_tm_conf *tm_conf =
2498                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2499
2500         PMD_INIT_FUNC_TRACE();
2501
2502         /* IXGBE devices don't support:
2503         *    - half duplex (checked afterwards for valid speeds)
2504         *    - fixed speed: TODO implement
2505         */
2506         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2507                 PMD_INIT_LOG(ERR,
2508                 "Invalid link_speeds for port %u, fix speed not supported",
2509                                 dev->data->port_id);
2510                 return -EINVAL;
2511         }
2512
2513         /* disable uio/vfio intr/eventfd mapping */
2514         rte_intr_disable(intr_handle);
2515
2516         /* stop adapter */
2517         hw->adapter_stopped = 0;
2518         ixgbe_stop_adapter(hw);
2519
2520         /* reinitialize adapter
2521          * this calls reset and start
2522          */
2523         status = ixgbe_pf_reset_hw(hw);
2524         if (status != 0)
2525                 return -1;
2526         hw->mac.ops.start_hw(hw);
2527         hw->mac.get_link_status = true;
2528
2529         /* configure PF module if SRIOV enabled */
2530         ixgbe_pf_host_configure(dev);
2531
2532         ixgbe_dev_phy_intr_setup(dev);
2533
2534         /* check and configure queue intr-vector mapping */
2535         if ((rte_intr_cap_multiple(intr_handle) ||
2536              !RTE_ETH_DEV_SRIOV(dev).active) &&
2537             dev->data->dev_conf.intr_conf.rxq != 0) {
2538                 intr_vector = dev->data->nb_rx_queues;
2539                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2540                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2541                                         IXGBE_MAX_INTR_QUEUE_NUM);
2542                         return -ENOTSUP;
2543                 }
2544                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2545                         return -1;
2546         }
2547
2548         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2549                 intr_handle->intr_vec =
2550                         rte_zmalloc("intr_vec",
2551                                     dev->data->nb_rx_queues * sizeof(int), 0);
2552                 if (intr_handle->intr_vec == NULL) {
2553                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2554                                      " intr_vec", dev->data->nb_rx_queues);
2555                         return -ENOMEM;
2556                 }
2557         }
2558
2559         /* confiugre msix for sleep until rx interrupt */
2560         ixgbe_configure_msix(dev);
2561
2562         /* initialize transmission unit */
2563         ixgbe_dev_tx_init(dev);
2564
2565         /* This can fail when allocating mbufs for descriptor rings */
2566         err = ixgbe_dev_rx_init(dev);
2567         if (err) {
2568                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2569                 goto error;
2570         }
2571
2572     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2573                 ETH_VLAN_EXTEND_MASK;
2574         ixgbe_vlan_offload_set(dev, mask);
2575
2576         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2577                 /* Enable vlan filtering for VMDq */
2578                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2579         }
2580
2581         /* Configure DCB hw */
2582         ixgbe_configure_dcb(dev);
2583
2584         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2585                 err = ixgbe_fdir_configure(dev);
2586                 if (err)
2587                         goto error;
2588         }
2589
2590         /* Restore vf rate limit */
2591         if (vfinfo != NULL) {
2592                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2593                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2594                                 if (vfinfo[vf].tx_rate[idx] != 0)
2595                                         ixgbe_set_vf_rate_limit(
2596                                                 dev, vf,
2597                                                 vfinfo[vf].tx_rate[idx],
2598                                                 1 << idx);
2599         }
2600
2601         ixgbe_restore_statistics_mapping(dev);
2602
2603         err = ixgbe_dev_rxtx_start(dev);
2604         if (err < 0) {
2605                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2606                 goto error;
2607         }
2608
2609         /* Skip link setup if loopback mode is enabled for 82599. */
2610         if (hw->mac.type == ixgbe_mac_82599EB &&
2611                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2612                 goto skip_link_setup;
2613
2614         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2615                 err = hw->mac.ops.setup_sfp(hw);
2616                 if (err)
2617                         goto error;
2618         }
2619
2620         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2621                 /* Turn on the copper */
2622                 ixgbe_set_phy_power(hw, true);
2623         } else {
2624                 /* Turn on the laser */
2625                 ixgbe_enable_tx_laser(hw);
2626         }
2627
2628         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2629         if (err)
2630                 goto error;
2631         dev->data->dev_link.link_status = link_up;
2632
2633         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2634         if (err)
2635                 goto error;
2636
2637         link_speeds = &dev->data->dev_conf.link_speeds;
2638         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2639                         ETH_LINK_SPEED_10G)) {
2640                 PMD_INIT_LOG(ERR, "Invalid link setting");
2641                 goto error;
2642         }
2643
2644         speed = 0x0;
2645         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2646                 switch (hw->mac.type) {
2647                 case ixgbe_mac_82598EB:
2648                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2649                         break;
2650                 case ixgbe_mac_82599EB:
2651                 case ixgbe_mac_X540:
2652                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2653                         break;
2654                 case ixgbe_mac_X550:
2655                 case ixgbe_mac_X550EM_x:
2656                 case ixgbe_mac_X550EM_a:
2657                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2658                         break;
2659                 default:
2660                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2661                 }
2662         } else {
2663                 if (*link_speeds & ETH_LINK_SPEED_10G)
2664                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2665                 if (*link_speeds & ETH_LINK_SPEED_1G)
2666                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2667                 if (*link_speeds & ETH_LINK_SPEED_100M)
2668                         speed |= IXGBE_LINK_SPEED_100_FULL;
2669         }
2670
2671         err = ixgbe_setup_link(hw, speed, link_up);
2672         if (err)
2673                 goto error;
2674
2675 skip_link_setup:
2676
2677         if (rte_intr_allow_others(intr_handle)) {
2678                 /* check if lsc interrupt is enabled */
2679                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2680                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2681                 else
2682                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2683                 ixgbe_dev_macsec_interrupt_setup(dev);
2684         } else {
2685                 rte_intr_callback_unregister(intr_handle,
2686                                              ixgbe_dev_interrupt_handler, dev);
2687                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2688                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2689                                      " no intr multiplex");
2690         }
2691
2692         /* check if rxq interrupt is enabled */
2693         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2694             rte_intr_dp_is_en(intr_handle))
2695                 ixgbe_dev_rxq_interrupt_setup(dev);
2696
2697         /* enable uio/vfio intr/eventfd mapping */
2698         rte_intr_enable(intr_handle);
2699
2700         /* resume enabled intr since hw reset */
2701         ixgbe_enable_intr(dev);
2702         ixgbe_l2_tunnel_conf(dev);
2703         ixgbe_filter_restore(dev);
2704
2705         if (tm_conf->root && !tm_conf->committed)
2706                 PMD_DRV_LOG(WARNING,
2707                             "please call hierarchy_commit() "
2708                             "before starting the port");
2709
2710         return 0;
2711
2712 error:
2713         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2714         ixgbe_dev_clear_queues(dev);
2715         return -EIO;
2716 }
2717
2718 /*
2719  * Stop device: disable rx and tx functions to allow for reconfiguring.
2720  */
2721 static void
2722 ixgbe_dev_stop(struct rte_eth_dev *dev)
2723 {
2724         struct rte_eth_link link;
2725         struct ixgbe_hw *hw =
2726                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2727         struct ixgbe_vf_info *vfinfo =
2728                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2729         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2730         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2731         int vf;
2732         struct ixgbe_tm_conf *tm_conf =
2733                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2734
2735         PMD_INIT_FUNC_TRACE();
2736
2737         /* disable interrupts */
2738         ixgbe_disable_intr(hw);
2739
2740         /* reset the NIC */
2741         ixgbe_pf_reset_hw(hw);
2742         hw->adapter_stopped = 0;
2743
2744         /* stop adapter */
2745         ixgbe_stop_adapter(hw);
2746
2747         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2748                 vfinfo[vf].clear_to_send = false;
2749
2750         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2751                 /* Turn off the copper */
2752                 ixgbe_set_phy_power(hw, false);
2753         } else {
2754                 /* Turn off the laser */
2755                 ixgbe_disable_tx_laser(hw);
2756         }
2757
2758         ixgbe_dev_clear_queues(dev);
2759
2760         /* Clear stored conf */
2761         dev->data->scattered_rx = 0;
2762         dev->data->lro = 0;
2763
2764         /* Clear recorded link status */
2765         memset(&link, 0, sizeof(link));
2766         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2767
2768         if (!rte_intr_allow_others(intr_handle))
2769                 /* resume to the default handler */
2770                 rte_intr_callback_register(intr_handle,
2771                                            ixgbe_dev_interrupt_handler,
2772                                            (void *)dev);
2773
2774         /* Clean datapath event and queue/vec mapping */
2775         rte_intr_efd_disable(intr_handle);
2776         if (intr_handle->intr_vec != NULL) {
2777                 rte_free(intr_handle->intr_vec);
2778                 intr_handle->intr_vec = NULL;
2779         }
2780
2781         /* reset hierarchy commit */
2782         tm_conf->committed = false;
2783 }
2784
2785 /*
2786  * Set device link up: enable tx.
2787  */
2788 static int
2789 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2790 {
2791         struct ixgbe_hw *hw =
2792                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2793         if (hw->mac.type == ixgbe_mac_82599EB) {
2794 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2795                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2796                         /* Not suported in bypass mode */
2797                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2798                                      "by device id 0x%x", hw->device_id);
2799                         return -ENOTSUP;
2800                 }
2801 #endif
2802         }
2803
2804         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2805                 /* Turn on the copper */
2806                 ixgbe_set_phy_power(hw, true);
2807         } else {
2808                 /* Turn on the laser */
2809                 ixgbe_enable_tx_laser(hw);
2810         }
2811
2812         return 0;
2813 }
2814
2815 /*
2816  * Set device link down: disable tx.
2817  */
2818 static int
2819 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2820 {
2821         struct ixgbe_hw *hw =
2822                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2823         if (hw->mac.type == ixgbe_mac_82599EB) {
2824 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2825                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2826                         /* Not suported in bypass mode */
2827                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2828                                      "by device id 0x%x", hw->device_id);
2829                         return -ENOTSUP;
2830                 }
2831 #endif
2832         }
2833
2834         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2835                 /* Turn off the copper */
2836                 ixgbe_set_phy_power(hw, false);
2837         } else {
2838                 /* Turn off the laser */
2839                 ixgbe_disable_tx_laser(hw);
2840         }
2841
2842         return 0;
2843 }
2844
2845 /*
2846  * Reset and stop device.
2847  */
2848 static void
2849 ixgbe_dev_close(struct rte_eth_dev *dev)
2850 {
2851         struct ixgbe_hw *hw =
2852                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2853
2854         PMD_INIT_FUNC_TRACE();
2855
2856         ixgbe_pf_reset_hw(hw);
2857
2858         ixgbe_dev_stop(dev);
2859         hw->adapter_stopped = 1;
2860
2861         ixgbe_dev_free_queues(dev);
2862
2863         ixgbe_disable_pcie_master(hw);
2864
2865         /* reprogram the RAR[0] in case user changed it. */
2866         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2867 }
2868
2869 /*
2870  * Reset PF device.
2871  */
2872 static int
2873 ixgbe_dev_reset(struct rte_eth_dev *dev)
2874 {
2875         int ret;
2876
2877         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2878          * its VF to make them align with it. The detailed notification
2879          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2880          * To avoid unexpected behavior in VF, currently reset of PF with
2881          * SR-IOV activation is not supported. It might be supported later.
2882          */
2883         if (dev->data->sriov.active)
2884                 return -ENOTSUP;
2885
2886         ret = eth_ixgbe_dev_uninit(dev);
2887         if (ret)
2888                 return ret;
2889
2890         ret = eth_ixgbe_dev_init(dev);
2891
2892         return ret;
2893 }
2894
2895 static void
2896 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2897                            struct ixgbe_hw_stats *hw_stats,
2898                            struct ixgbe_macsec_stats *macsec_stats,
2899                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2900                            uint64_t *total_qprc, uint64_t *total_qprdc)
2901 {
2902         uint32_t bprc, lxon, lxoff, total;
2903         uint32_t delta_gprc = 0;
2904         unsigned i;
2905         /* Workaround for RX byte count not including CRC bytes when CRC
2906          * strip is enabled. CRC bytes are removed from counters when crc_strip
2907          * is disabled.
2908          */
2909         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2910                         IXGBE_HLREG0_RXCRCSTRP);
2911
2912         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2913         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2914         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2915         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2916
2917         for (i = 0; i < 8; i++) {
2918                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2919
2920                 /* global total per queue */
2921                 hw_stats->mpc[i] += mp;
2922                 /* Running comprehensive total for stats display */
2923                 *total_missed_rx += hw_stats->mpc[i];
2924                 if (hw->mac.type == ixgbe_mac_82598EB) {
2925                         hw_stats->rnbc[i] +=
2926                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2927                         hw_stats->pxonrxc[i] +=
2928                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2929                         hw_stats->pxoffrxc[i] +=
2930                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2931                 } else {
2932                         hw_stats->pxonrxc[i] +=
2933                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2934                         hw_stats->pxoffrxc[i] +=
2935                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2936                         hw_stats->pxon2offc[i] +=
2937                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2938                 }
2939                 hw_stats->pxontxc[i] +=
2940                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2941                 hw_stats->pxofftxc[i] +=
2942                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2943         }
2944         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2945                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2946                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2947                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2948
2949                 delta_gprc += delta_qprc;
2950
2951                 hw_stats->qprc[i] += delta_qprc;
2952                 hw_stats->qptc[i] += delta_qptc;
2953
2954                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2955                 hw_stats->qbrc[i] +=
2956                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2957                 if (crc_strip == 0)
2958                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2959
2960                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2961                 hw_stats->qbtc[i] +=
2962                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2963
2964                 hw_stats->qprdc[i] += delta_qprdc;
2965                 *total_qprdc += hw_stats->qprdc[i];
2966
2967                 *total_qprc += hw_stats->qprc[i];
2968                 *total_qbrc += hw_stats->qbrc[i];
2969         }
2970         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2971         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2972         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2973
2974         /*
2975          * An errata states that gprc actually counts good + missed packets:
2976          * Workaround to set gprc to summated queue packet receives
2977          */
2978         hw_stats->gprc = *total_qprc;
2979
2980         if (hw->mac.type != ixgbe_mac_82598EB) {
2981                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2982                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2983                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2984                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2985                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2986                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2987                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2988                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2989         } else {
2990                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2991                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2992                 /* 82598 only has a counter in the high register */
2993                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2994                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2995                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2996         }
2997         uint64_t old_tpr = hw_stats->tpr;
2998
2999         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3000         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3001
3002         if (crc_strip == 0)
3003                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3004
3005         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3006         hw_stats->gptc += delta_gptc;
3007         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3008         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3009
3010         /*
3011          * Workaround: mprc hardware is incorrectly counting
3012          * broadcasts, so for now we subtract those.
3013          */
3014         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3015         hw_stats->bprc += bprc;
3016         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3017         if (hw->mac.type == ixgbe_mac_82598EB)
3018                 hw_stats->mprc -= bprc;
3019
3020         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3021         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3022         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3023         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3024         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3025         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3026
3027         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3028         hw_stats->lxontxc += lxon;
3029         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3030         hw_stats->lxofftxc += lxoff;
3031         total = lxon + lxoff;
3032
3033         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3034         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3035         hw_stats->gptc -= total;
3036         hw_stats->mptc -= total;
3037         hw_stats->ptc64 -= total;
3038         hw_stats->gotc -= total * ETHER_MIN_LEN;
3039
3040         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3041         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3042         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3043         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3044         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3045         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3046         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3047         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3048         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3049         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3050         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3051         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3052         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3053         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3054         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3055         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3056         /* Only read FCOE on 82599 */
3057         if (hw->mac.type != ixgbe_mac_82598EB) {
3058                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3059                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3060                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3061                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3062                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3063         }
3064
3065         /* Flow Director Stats registers */
3066         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3067         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3068
3069         /* MACsec Stats registers */
3070         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3071         macsec_stats->out_pkts_encrypted +=
3072                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3073         macsec_stats->out_pkts_protected +=
3074                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3075         macsec_stats->out_octets_encrypted +=
3076                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3077         macsec_stats->out_octets_protected +=
3078                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3079         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3080         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3081         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3082         macsec_stats->in_pkts_unknownsci +=
3083                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3084         macsec_stats->in_octets_decrypted +=
3085                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3086         macsec_stats->in_octets_validated +=
3087                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3088         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3089         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3090         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3091         for (i = 0; i < 2; i++) {
3092                 macsec_stats->in_pkts_ok +=
3093                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3094                 macsec_stats->in_pkts_invalid +=
3095                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3096                 macsec_stats->in_pkts_notvalid +=
3097                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3098         }
3099         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3100         macsec_stats->in_pkts_notusingsa +=
3101                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3102 }
3103
3104 /*
3105  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3106  */
3107 static int
3108 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3109 {
3110         struct ixgbe_hw *hw =
3111                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3112         struct ixgbe_hw_stats *hw_stats =
3113                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3114         struct ixgbe_macsec_stats *macsec_stats =
3115                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3116                                 dev->data->dev_private);
3117         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3118         unsigned i;
3119
3120         total_missed_rx = 0;
3121         total_qbrc = 0;
3122         total_qprc = 0;
3123         total_qprdc = 0;
3124
3125         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3126                         &total_qbrc, &total_qprc, &total_qprdc);
3127
3128         if (stats == NULL)
3129                 return -EINVAL;
3130
3131         /* Fill out the rte_eth_stats statistics structure */
3132         stats->ipackets = total_qprc;
3133         stats->ibytes = total_qbrc;
3134         stats->opackets = hw_stats->gptc;
3135         stats->obytes = hw_stats->gotc;
3136
3137         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3138                 stats->q_ipackets[i] = hw_stats->qprc[i];
3139                 stats->q_opackets[i] = hw_stats->qptc[i];
3140                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3141                 stats->q_obytes[i] = hw_stats->qbtc[i];
3142                 stats->q_errors[i] = hw_stats->qprdc[i];
3143         }
3144
3145         /* Rx Errors */
3146         stats->imissed  = total_missed_rx;
3147         stats->ierrors  = hw_stats->crcerrs +
3148                           hw_stats->mspdc +
3149                           hw_stats->rlec +
3150                           hw_stats->ruc +
3151                           hw_stats->roc +
3152                           hw_stats->illerrc +
3153                           hw_stats->errbc +
3154                           hw_stats->rfc +
3155                           hw_stats->fccrc +
3156                           hw_stats->fclast;
3157
3158         /* Tx Errors */
3159         stats->oerrors  = 0;
3160         return 0;
3161 }
3162
3163 static void
3164 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3165 {
3166         struct ixgbe_hw_stats *stats =
3167                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3168
3169         /* HW registers are cleared on read */
3170         ixgbe_dev_stats_get(dev, NULL);
3171
3172         /* Reset software totals */
3173         memset(stats, 0, sizeof(*stats));
3174 }
3175
3176 /* This function calculates the number of xstats based on the current config */
3177 static unsigned
3178 ixgbe_xstats_calc_num(void) {
3179         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3180                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3181                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3182 }
3183
3184 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3185         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3186 {
3187         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3188         unsigned stat, i, count;
3189
3190         if (xstats_names != NULL) {
3191                 count = 0;
3192
3193                 /* Note: limit >= cnt_stats checked upstream
3194                  * in rte_eth_xstats_names()
3195                  */
3196
3197                 /* Extended stats from ixgbe_hw_stats */
3198                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3199                         snprintf(xstats_names[count].name,
3200                                 sizeof(xstats_names[count].name),
3201                                 "%s",
3202                                 rte_ixgbe_stats_strings[i].name);
3203                         count++;
3204                 }
3205
3206                 /* MACsec Stats */
3207                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3208                         snprintf(xstats_names[count].name,
3209                                 sizeof(xstats_names[count].name),
3210                                 "%s",
3211                                 rte_ixgbe_macsec_strings[i].name);
3212                         count++;
3213                 }
3214
3215                 /* RX Priority Stats */
3216                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3217                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3218                                 snprintf(xstats_names[count].name,
3219                                         sizeof(xstats_names[count].name),
3220                                         "rx_priority%u_%s", i,
3221                                         rte_ixgbe_rxq_strings[stat].name);
3222                                 count++;
3223                         }
3224                 }
3225
3226                 /* TX Priority Stats */
3227                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3228                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3229                                 snprintf(xstats_names[count].name,
3230                                         sizeof(xstats_names[count].name),
3231                                         "tx_priority%u_%s", i,
3232                                         rte_ixgbe_txq_strings[stat].name);
3233                                 count++;
3234                         }
3235                 }
3236         }
3237         return cnt_stats;
3238 }
3239
3240 static int ixgbe_dev_xstats_get_names_by_id(
3241         struct rte_eth_dev *dev,
3242         struct rte_eth_xstat_name *xstats_names,
3243         const uint64_t *ids,
3244         unsigned int limit)
3245 {
3246         if (!ids) {
3247                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3248                 unsigned int stat, i, count;
3249
3250                 if (xstats_names != NULL) {
3251                         count = 0;
3252
3253                         /* Note: limit >= cnt_stats checked upstream
3254                          * in rte_eth_xstats_names()
3255                          */
3256
3257                         /* Extended stats from ixgbe_hw_stats */
3258                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3259                                 snprintf(xstats_names[count].name,
3260                                         sizeof(xstats_names[count].name),
3261                                         "%s",
3262                                         rte_ixgbe_stats_strings[i].name);
3263                                 count++;
3264                         }
3265
3266                         /* MACsec Stats */
3267                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3268                                 snprintf(xstats_names[count].name,
3269                                         sizeof(xstats_names[count].name),
3270                                         "%s",
3271                                         rte_ixgbe_macsec_strings[i].name);
3272                                 count++;
3273                         }
3274
3275                         /* RX Priority Stats */
3276                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3277                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3278                                         snprintf(xstats_names[count].name,
3279                                             sizeof(xstats_names[count].name),
3280                                             "rx_priority%u_%s", i,
3281                                             rte_ixgbe_rxq_strings[stat].name);
3282                                         count++;
3283                                 }
3284                         }
3285
3286                         /* TX Priority Stats */
3287                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3288                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3289                                         snprintf(xstats_names[count].name,
3290                                             sizeof(xstats_names[count].name),
3291                                             "tx_priority%u_%s", i,
3292                                             rte_ixgbe_txq_strings[stat].name);
3293                                         count++;
3294                                 }
3295                         }
3296                 }
3297                 return cnt_stats;
3298         }
3299
3300         uint16_t i;
3301         uint16_t size = ixgbe_xstats_calc_num();
3302         struct rte_eth_xstat_name xstats_names_copy[size];
3303
3304         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3305                         size);
3306
3307         for (i = 0; i < limit; i++) {
3308                 if (ids[i] >= size) {
3309                         PMD_INIT_LOG(ERR, "id value isn't valid");
3310                         return -1;
3311                 }
3312                 strcpy(xstats_names[i].name,
3313                                 xstats_names_copy[ids[i]].name);
3314         }
3315         return limit;
3316 }
3317
3318 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3319         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3320 {
3321         unsigned i;
3322
3323         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3324                 return -ENOMEM;
3325
3326         if (xstats_names != NULL)
3327                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3328                         snprintf(xstats_names[i].name,
3329                                 sizeof(xstats_names[i].name),
3330                                 "%s", rte_ixgbevf_stats_strings[i].name);
3331         return IXGBEVF_NB_XSTATS;
3332 }
3333
3334 static int
3335 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3336                                          unsigned n)
3337 {
3338         struct ixgbe_hw *hw =
3339                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3340         struct ixgbe_hw_stats *hw_stats =
3341                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3342         struct ixgbe_macsec_stats *macsec_stats =
3343                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3344                                 dev->data->dev_private);
3345         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3346         unsigned i, stat, count = 0;
3347
3348         count = ixgbe_xstats_calc_num();
3349
3350         if (n < count)
3351                 return count;
3352
3353         total_missed_rx = 0;
3354         total_qbrc = 0;
3355         total_qprc = 0;
3356         total_qprdc = 0;
3357
3358         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3359                         &total_qbrc, &total_qprc, &total_qprdc);
3360
3361         /* If this is a reset xstats is NULL, and we have cleared the
3362          * registers by reading them.
3363          */
3364         if (!xstats)
3365                 return 0;
3366
3367         /* Extended stats from ixgbe_hw_stats */
3368         count = 0;
3369         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3370                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3371                                 rte_ixgbe_stats_strings[i].offset);
3372                 xstats[count].id = count;
3373                 count++;
3374         }
3375
3376         /* MACsec Stats */
3377         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3378                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3379                                 rte_ixgbe_macsec_strings[i].offset);
3380                 xstats[count].id = count;
3381                 count++;
3382         }
3383
3384         /* RX Priority Stats */
3385         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3386                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3387                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3388                                         rte_ixgbe_rxq_strings[stat].offset +
3389                                         (sizeof(uint64_t) * i));
3390                         xstats[count].id = count;
3391                         count++;
3392                 }
3393         }
3394
3395         /* TX Priority Stats */
3396         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3397                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3398                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3399                                         rte_ixgbe_txq_strings[stat].offset +
3400                                         (sizeof(uint64_t) * i));
3401                         xstats[count].id = count;
3402                         count++;
3403                 }
3404         }
3405         return count;
3406 }
3407
3408 static int
3409 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3410                 uint64_t *values, unsigned int n)
3411 {
3412         if (!ids) {
3413                 struct ixgbe_hw *hw =
3414                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3415                 struct ixgbe_hw_stats *hw_stats =
3416                                 IXGBE_DEV_PRIVATE_TO_STATS(
3417                                                 dev->data->dev_private);
3418                 struct ixgbe_macsec_stats *macsec_stats =
3419                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3420                                         dev->data->dev_private);
3421                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3422                 unsigned int i, stat, count = 0;
3423
3424                 count = ixgbe_xstats_calc_num();
3425
3426                 if (!ids && n < count)
3427                         return count;
3428
3429                 total_missed_rx = 0;
3430                 total_qbrc = 0;
3431                 total_qprc = 0;
3432                 total_qprdc = 0;
3433
3434                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3435                                 &total_missed_rx, &total_qbrc, &total_qprc,
3436                                 &total_qprdc);
3437
3438                 /* If this is a reset xstats is NULL, and we have cleared the
3439                  * registers by reading them.
3440                  */
3441                 if (!ids && !values)
3442                         return 0;
3443
3444                 /* Extended stats from ixgbe_hw_stats */
3445                 count = 0;
3446                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3447                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3448                                         rte_ixgbe_stats_strings[i].offset);
3449                         count++;
3450                 }
3451
3452                 /* MACsec Stats */
3453                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3454                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3455                                         rte_ixgbe_macsec_strings[i].offset);
3456                         count++;
3457                 }
3458
3459                 /* RX Priority Stats */
3460                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3461                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3462                                 values[count] =
3463                                         *(uint64_t *)(((char *)hw_stats) +
3464                                         rte_ixgbe_rxq_strings[stat].offset +
3465                                         (sizeof(uint64_t) * i));
3466                                 count++;
3467                         }
3468                 }
3469
3470                 /* TX Priority Stats */
3471                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3472                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3473                                 values[count] =
3474                                         *(uint64_t *)(((char *)hw_stats) +
3475                                         rte_ixgbe_txq_strings[stat].offset +
3476                                         (sizeof(uint64_t) * i));
3477                                 count++;
3478                         }
3479                 }
3480                 return count;
3481         }
3482
3483         uint16_t i;
3484         uint16_t size = ixgbe_xstats_calc_num();
3485         uint64_t values_copy[size];
3486
3487         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3488
3489         for (i = 0; i < n; i++) {
3490                 if (ids[i] >= size) {
3491                         PMD_INIT_LOG(ERR, "id value isn't valid");
3492                         return -1;
3493                 }
3494                 values[i] = values_copy[ids[i]];
3495         }
3496         return n;
3497 }
3498
3499 static void
3500 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3501 {
3502         struct ixgbe_hw_stats *stats =
3503                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3504         struct ixgbe_macsec_stats *macsec_stats =
3505                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3506                                 dev->data->dev_private);
3507
3508         unsigned count = ixgbe_xstats_calc_num();
3509
3510         /* HW registers are cleared on read */
3511         ixgbe_dev_xstats_get(dev, NULL, count);
3512
3513         /* Reset software totals */
3514         memset(stats, 0, sizeof(*stats));
3515         memset(macsec_stats, 0, sizeof(*macsec_stats));
3516 }
3517
3518 static void
3519 ixgbevf_update_stats(struct rte_eth_dev *dev)
3520 {
3521         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3522         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3523                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3524
3525         /* Good Rx packet, include VF loopback */
3526         UPDATE_VF_STAT(IXGBE_VFGPRC,
3527             hw_stats->last_vfgprc, hw_stats->vfgprc);
3528
3529         /* Good Rx octets, include VF loopback */
3530         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3531             hw_stats->last_vfgorc, hw_stats->vfgorc);
3532
3533         /* Good Tx packet, include VF loopback */
3534         UPDATE_VF_STAT(IXGBE_VFGPTC,
3535             hw_stats->last_vfgptc, hw_stats->vfgptc);
3536
3537         /* Good Tx octets, include VF loopback */
3538         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3539             hw_stats->last_vfgotc, hw_stats->vfgotc);
3540
3541         /* Rx Multicst Packet */
3542         UPDATE_VF_STAT(IXGBE_VFMPRC,
3543             hw_stats->last_vfmprc, hw_stats->vfmprc);
3544 }
3545
3546 static int
3547 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3548                        unsigned n)
3549 {
3550         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3551                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3552         unsigned i;
3553
3554         if (n < IXGBEVF_NB_XSTATS)
3555                 return IXGBEVF_NB_XSTATS;
3556
3557         ixgbevf_update_stats(dev);
3558
3559         if (!xstats)
3560                 return 0;
3561
3562         /* Extended stats */
3563         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3564                 xstats[i].id = i;
3565                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3566                         rte_ixgbevf_stats_strings[i].offset);
3567         }
3568
3569         return IXGBEVF_NB_XSTATS;
3570 }
3571
3572 static int
3573 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3574 {
3575         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3576                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3577
3578         ixgbevf_update_stats(dev);
3579
3580         if (stats == NULL)
3581                 return -EINVAL;
3582
3583         stats->ipackets = hw_stats->vfgprc;
3584         stats->ibytes = hw_stats->vfgorc;
3585         stats->opackets = hw_stats->vfgptc;
3586         stats->obytes = hw_stats->vfgotc;
3587         return 0;
3588 }
3589
3590 static void
3591 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3592 {
3593         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3594                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3595
3596         /* Sync HW register to the last stats */
3597         ixgbevf_dev_stats_get(dev, NULL);
3598
3599         /* reset HW current stats*/
3600         hw_stats->vfgprc = 0;
3601         hw_stats->vfgorc = 0;
3602         hw_stats->vfgptc = 0;
3603         hw_stats->vfgotc = 0;
3604 }
3605
3606 static int
3607 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3608 {
3609         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3610         u16 eeprom_verh, eeprom_verl;
3611         u32 etrack_id;
3612         int ret;
3613
3614         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3615         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3616
3617         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3618         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3619
3620         ret += 1; /* add the size of '\0' */
3621         if (fw_size < (u32)ret)
3622                 return ret;
3623         else
3624                 return 0;
3625 }
3626
3627 static void
3628 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3629 {
3630         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3631         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3632         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3633
3634         dev_info->pci_dev = pci_dev;
3635         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3636         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3637         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3638                 /*
3639                  * When DCB/VT is off, maximum number of queues changes,
3640                  * except for 82598EB, which remains constant.
3641                  */
3642                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3643                                 hw->mac.type != ixgbe_mac_82598EB)
3644                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3645         }
3646         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3647         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3648         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3649         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3650         dev_info->max_vfs = pci_dev->max_vfs;
3651         if (hw->mac.type == ixgbe_mac_82598EB)
3652                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3653         else
3654                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3655         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3656         dev_info->rx_offload_capa =
3657                 DEV_RX_OFFLOAD_VLAN_STRIP |
3658                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3659                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3660                 DEV_RX_OFFLOAD_TCP_CKSUM;
3661
3662         /*
3663          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3664          * mode.
3665          */
3666         if ((hw->mac.type == ixgbe_mac_82599EB ||
3667              hw->mac.type == ixgbe_mac_X540) &&
3668             !RTE_ETH_DEV_SRIOV(dev).active)
3669                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3670
3671         if (hw->mac.type == ixgbe_mac_82599EB ||
3672             hw->mac.type == ixgbe_mac_X540)
3673                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3674
3675         if (hw->mac.type == ixgbe_mac_X550 ||
3676             hw->mac.type == ixgbe_mac_X550EM_x ||
3677             hw->mac.type == ixgbe_mac_X550EM_a)
3678                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3679
3680         dev_info->tx_offload_capa =
3681                 DEV_TX_OFFLOAD_VLAN_INSERT |
3682                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3683                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3684                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3685                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3686                 DEV_TX_OFFLOAD_TCP_TSO;
3687
3688         if (hw->mac.type == ixgbe_mac_82599EB ||
3689             hw->mac.type == ixgbe_mac_X540)
3690                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3691
3692         if (hw->mac.type == ixgbe_mac_X550 ||
3693             hw->mac.type == ixgbe_mac_X550EM_x ||
3694             hw->mac.type == ixgbe_mac_X550EM_a)
3695                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3696
3697         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3698                 .rx_thresh = {
3699                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3700                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3701                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3702                 },
3703                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3704                 .rx_drop_en = 0,
3705         };
3706
3707         dev_info->default_txconf = (struct rte_eth_txconf) {
3708                 .tx_thresh = {
3709                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3710                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3711                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3712                 },
3713                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3714                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3715                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3716                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3717         };
3718
3719         dev_info->rx_desc_lim = rx_desc_lim;
3720         dev_info->tx_desc_lim = tx_desc_lim;
3721
3722         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3723         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3724         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3725
3726         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3727         if (hw->mac.type == ixgbe_mac_X540 ||
3728             hw->mac.type == ixgbe_mac_X540_vf ||
3729             hw->mac.type == ixgbe_mac_X550 ||
3730             hw->mac.type == ixgbe_mac_X550_vf) {
3731                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3732         }
3733         if (hw->mac.type == ixgbe_mac_X550) {
3734                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3735                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3736         }
3737 }
3738
3739 static const uint32_t *
3740 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3741 {
3742         static const uint32_t ptypes[] = {
3743                 /* For non-vec functions,
3744                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3745                  * for vec functions,
3746                  * refers to _recv_raw_pkts_vec().
3747                  */
3748                 RTE_PTYPE_L2_ETHER,
3749                 RTE_PTYPE_L3_IPV4,
3750                 RTE_PTYPE_L3_IPV4_EXT,
3751                 RTE_PTYPE_L3_IPV6,
3752                 RTE_PTYPE_L3_IPV6_EXT,
3753                 RTE_PTYPE_L4_SCTP,
3754                 RTE_PTYPE_L4_TCP,
3755                 RTE_PTYPE_L4_UDP,
3756                 RTE_PTYPE_TUNNEL_IP,
3757                 RTE_PTYPE_INNER_L3_IPV6,
3758                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3759                 RTE_PTYPE_INNER_L4_TCP,
3760                 RTE_PTYPE_INNER_L4_UDP,
3761                 RTE_PTYPE_UNKNOWN
3762         };
3763
3764         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3765             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3766             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3767             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3768                 return ptypes;
3769
3770 #if defined(RTE_ARCH_X86)
3771         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3772             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3773                 return ptypes;
3774 #endif
3775         return NULL;
3776 }
3777
3778 static void
3779 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3780                      struct rte_eth_dev_info *dev_info)
3781 {
3782         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3783         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3784
3785         dev_info->pci_dev = pci_dev;
3786         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3787         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3788         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3789         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3790         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3791         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3792         dev_info->max_vfs = pci_dev->max_vfs;
3793         if (hw->mac.type == ixgbe_mac_82598EB)
3794                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3795         else
3796                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3797         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3798                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3799                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3800                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3801         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3802                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3803                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3804                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3805                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3806                                 DEV_TX_OFFLOAD_TCP_TSO;
3807
3808         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3809                 .rx_thresh = {
3810                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3811                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3812                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3813                 },
3814                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3815                 .rx_drop_en = 0,
3816         };
3817
3818         dev_info->default_txconf = (struct rte_eth_txconf) {
3819                 .tx_thresh = {
3820                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3821                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3822                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3823                 },
3824                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3825                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3826                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3827                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3828         };
3829
3830         dev_info->rx_desc_lim = rx_desc_lim;
3831         dev_info->tx_desc_lim = tx_desc_lim;
3832 }
3833
3834 static int
3835 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3836                    int *link_up, int wait_to_complete)
3837 {
3838         /**
3839          * for a quick link status checking, wait_to_compelet == 0,
3840          * skip PF link status checking
3841          */
3842         bool no_pflink_check = wait_to_complete == 0;
3843         struct ixgbe_mbx_info *mbx = &hw->mbx;
3844         struct ixgbe_mac_info *mac = &hw->mac;
3845         uint32_t links_reg, in_msg;
3846         int ret_val = 0;
3847
3848         /* If we were hit with a reset drop the link */
3849         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3850                 mac->get_link_status = true;
3851
3852         if (!mac->get_link_status)
3853                 goto out;
3854
3855         /* if link status is down no point in checking to see if pf is up */
3856         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3857         if (!(links_reg & IXGBE_LINKS_UP))
3858                 goto out;
3859
3860         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3861          * before the link status is correct
3862          */
3863         if (mac->type == ixgbe_mac_82599_vf) {
3864                 int i;
3865
3866                 for (i = 0; i < 5; i++) {
3867                         rte_delay_us(100);
3868                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3869
3870                         if (!(links_reg & IXGBE_LINKS_UP))
3871                                 goto out;
3872                 }
3873         }
3874
3875         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3876         case IXGBE_LINKS_SPEED_10G_82599:
3877                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3878                 if (hw->mac.type >= ixgbe_mac_X550) {
3879                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3880                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3881                 }
3882                 break;
3883         case IXGBE_LINKS_SPEED_1G_82599:
3884                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3885                 break;
3886         case IXGBE_LINKS_SPEED_100_82599:
3887                 *speed = IXGBE_LINK_SPEED_100_FULL;
3888                 if (hw->mac.type == ixgbe_mac_X550) {
3889                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3890                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3891                 }
3892                 break;
3893         case IXGBE_LINKS_SPEED_10_X550EM_A:
3894                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3895                 /* Since Reserved in older MAC's */
3896                 if (hw->mac.type >= ixgbe_mac_X550)
3897                         *speed = IXGBE_LINK_SPEED_10_FULL;
3898                 break;
3899         default:
3900                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3901         }
3902
3903         if (no_pflink_check) {
3904                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3905                         mac->get_link_status = true;
3906                 else
3907                         mac->get_link_status = false;
3908
3909                 goto out;
3910         }
3911         /* if the read failed it could just be a mailbox collision, best wait
3912          * until we are called again and don't report an error
3913          */
3914         if (mbx->ops.read(hw, &in_msg, 1, 0))
3915                 goto out;
3916
3917         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3918                 /* msg is not CTS and is NACK we must have lost CTS status */
3919                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3920                         ret_val = -1;
3921                 goto out;
3922         }
3923
3924         /* the pf is talking, if we timed out in the past we reinit */
3925         if (!mbx->timeout) {
3926                 ret_val = -1;
3927                 goto out;
3928         }
3929
3930         /* if we passed all the tests above then the link is up and we no
3931          * longer need to check for link
3932          */
3933         mac->get_link_status = false;
3934
3935 out:
3936         *link_up = !mac->get_link_status;
3937         return ret_val;
3938 }
3939
3940 /* return 0 means link status changed, -1 means not changed */
3941 static int
3942 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3943                             int wait_to_complete, int vf)
3944 {
3945         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3946         struct rte_eth_link link, old;
3947         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3948         struct ixgbe_interrupt *intr =
3949                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3950         int link_up;
3951         int diag;
3952         u32 speed = 0;
3953         int wait = 1;
3954         bool autoneg = false;
3955
3956         link.link_status = ETH_LINK_DOWN;
3957         link.link_speed = 0;
3958         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3959         memset(&old, 0, sizeof(old));
3960         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3961
3962         hw->mac.get_link_status = true;
3963
3964         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3965                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3966                 speed = hw->phy.autoneg_advertised;
3967                 if (!speed)
3968                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3969                 ixgbe_setup_link(hw, speed, true);
3970         }
3971
3972         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3973         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3974                 wait = 0;
3975
3976         if (vf)
3977                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3978         else
3979                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3980
3981         if (diag != 0) {
3982                 link.link_speed = ETH_SPEED_NUM_100M;
3983                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3984                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3985                 if (link.link_status == old.link_status)
3986                         return -1;
3987                 return 0;
3988         }
3989
3990         if (link_up == 0) {
3991                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3992                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3993                 if (link.link_status == old.link_status)
3994                         return -1;
3995                 return 0;
3996         }
3997         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3998         link.link_status = ETH_LINK_UP;
3999         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4000
4001         switch (link_speed) {
4002         default:
4003         case IXGBE_LINK_SPEED_UNKNOWN:
4004                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4005                 link.link_speed = ETH_SPEED_NUM_100M;
4006                 break;
4007
4008         case IXGBE_LINK_SPEED_100_FULL:
4009                 link.link_speed = ETH_SPEED_NUM_100M;
4010                 break;
4011
4012         case IXGBE_LINK_SPEED_1GB_FULL:
4013                 link.link_speed = ETH_SPEED_NUM_1G;
4014                 break;
4015
4016         case IXGBE_LINK_SPEED_2_5GB_FULL:
4017                 link.link_speed = ETH_SPEED_NUM_2_5G;
4018                 break;
4019
4020         case IXGBE_LINK_SPEED_5GB_FULL:
4021                 link.link_speed = ETH_SPEED_NUM_5G;
4022                 break;
4023
4024         case IXGBE_LINK_SPEED_10GB_FULL:
4025                 link.link_speed = ETH_SPEED_NUM_10G;
4026                 break;
4027         }
4028         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4029
4030         if (link.link_status == old.link_status)
4031                 return -1;
4032
4033         return 0;
4034 }
4035
4036 static int
4037 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4038 {
4039         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4040 }
4041
4042 static int
4043 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4044 {
4045         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4046 }
4047
4048 static void
4049 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4050 {
4051         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4052         uint32_t fctrl;
4053
4054         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4055         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4056         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4057 }
4058
4059 static void
4060 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4061 {
4062         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4063         uint32_t fctrl;
4064
4065         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4066         fctrl &= (~IXGBE_FCTRL_UPE);
4067         if (dev->data->all_multicast == 1)
4068                 fctrl |= IXGBE_FCTRL_MPE;
4069         else
4070                 fctrl &= (~IXGBE_FCTRL_MPE);
4071         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4072 }
4073
4074 static void
4075 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4076 {
4077         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4078         uint32_t fctrl;
4079
4080         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4081         fctrl |= IXGBE_FCTRL_MPE;
4082         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4083 }
4084
4085 static void
4086 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4087 {
4088         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4089         uint32_t fctrl;
4090
4091         if (dev->data->promiscuous == 1)
4092                 return; /* must remain in all_multicast mode */
4093
4094         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4095         fctrl &= (~IXGBE_FCTRL_MPE);
4096         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4097 }
4098
4099 /**
4100  * It clears the interrupt causes and enables the interrupt.
4101  * It will be called once only during nic initialized.
4102  *
4103  * @param dev
4104  *  Pointer to struct rte_eth_dev.
4105  * @param on
4106  *  Enable or Disable.
4107  *
4108  * @return
4109  *  - On success, zero.
4110  *  - On failure, a negative value.
4111  */
4112 static int
4113 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4114 {
4115         struct ixgbe_interrupt *intr =
4116                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4117
4118         ixgbe_dev_link_status_print(dev);
4119         if (on)
4120                 intr->mask |= IXGBE_EICR_LSC;
4121         else
4122                 intr->mask &= ~IXGBE_EICR_LSC;
4123
4124         return 0;
4125 }
4126
4127 /**
4128  * It clears the interrupt causes and enables the interrupt.
4129  * It will be called once only during nic initialized.
4130  *
4131  * @param dev
4132  *  Pointer to struct rte_eth_dev.
4133  *
4134  * @return
4135  *  - On success, zero.
4136  *  - On failure, a negative value.
4137  */
4138 static int
4139 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4140 {
4141         struct ixgbe_interrupt *intr =
4142                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4143
4144         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4145
4146         return 0;
4147 }
4148
4149 /**
4150  * It clears the interrupt causes and enables the interrupt.
4151  * It will be called once only during nic initialized.
4152  *
4153  * @param dev
4154  *  Pointer to struct rte_eth_dev.
4155  *
4156  * @return
4157  *  - On success, zero.
4158  *  - On failure, a negative value.
4159  */
4160 static int
4161 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4162 {
4163         struct ixgbe_interrupt *intr =
4164                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4165
4166         intr->mask |= IXGBE_EICR_LINKSEC;
4167
4168         return 0;
4169 }
4170
4171 /*
4172  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4173  *
4174  * @param dev
4175  *  Pointer to struct rte_eth_dev.
4176  *
4177  * @return
4178  *  - On success, zero.
4179  *  - On failure, a negative value.
4180  */
4181 static int
4182 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4183 {
4184         uint32_t eicr;
4185         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4186         struct ixgbe_interrupt *intr =
4187                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4188
4189         /* clear all cause mask */
4190         ixgbe_disable_intr(hw);
4191
4192         /* read-on-clear nic registers here */
4193         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4194         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4195
4196         intr->flags = 0;
4197
4198         /* set flag for async link update */
4199         if (eicr & IXGBE_EICR_LSC)
4200                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4201
4202         if (eicr & IXGBE_EICR_MAILBOX)
4203                 intr->flags |= IXGBE_FLAG_MAILBOX;
4204
4205         if (eicr & IXGBE_EICR_LINKSEC)
4206                 intr->flags |= IXGBE_FLAG_MACSEC;
4207
4208         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4209             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4210             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4211                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4212
4213         return 0;
4214 }
4215
4216 /**
4217  * It gets and then prints the link status.
4218  *
4219  * @param dev
4220  *  Pointer to struct rte_eth_dev.
4221  *
4222  * @return
4223  *  - On success, zero.
4224  *  - On failure, a negative value.
4225  */
4226 static void
4227 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4228 {
4229         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4230         struct rte_eth_link link;
4231
4232         memset(&link, 0, sizeof(link));
4233         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4234         if (link.link_status) {
4235                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4236                                         (int)(dev->data->port_id),
4237                                         (unsigned)link.link_speed,
4238                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4239                                         "full-duplex" : "half-duplex");
4240         } else {
4241                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4242                                 (int)(dev->data->port_id));
4243         }
4244         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4245                                 pci_dev->addr.domain,
4246                                 pci_dev->addr.bus,
4247                                 pci_dev->addr.devid,
4248                                 pci_dev->addr.function);
4249 }
4250
4251 /*
4252  * It executes link_update after knowing an interrupt occurred.
4253  *
4254  * @param dev
4255  *  Pointer to struct rte_eth_dev.
4256  *
4257  * @return
4258  *  - On success, zero.
4259  *  - On failure, a negative value.
4260  */
4261 static int
4262 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4263                            struct rte_intr_handle *intr_handle)
4264 {
4265         struct ixgbe_interrupt *intr =
4266                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4267         int64_t timeout;
4268         struct rte_eth_link link;
4269         struct ixgbe_hw *hw =
4270                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4271
4272         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4273
4274         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4275                 ixgbe_pf_mbx_process(dev);
4276                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4277         }
4278
4279         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4280                 ixgbe_handle_lasi(hw);
4281                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4282         }
4283
4284         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4285                 /* get the link status before link update, for predicting later */
4286                 memset(&link, 0, sizeof(link));
4287                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4288
4289                 ixgbe_dev_link_update(dev, 0);
4290
4291                 /* likely to up */
4292                 if (!link.link_status)
4293                         /* handle it 1 sec later, wait it being stable */
4294                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4295                 /* likely to down */
4296                 else
4297                         /* handle it 4 sec later, wait it being stable */
4298                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4299
4300                 ixgbe_dev_link_status_print(dev);
4301                 if (rte_eal_alarm_set(timeout * 1000,
4302                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4303                         PMD_DRV_LOG(ERR, "Error setting alarm");
4304                 else {
4305                         /* remember original mask */
4306                         intr->mask_original = intr->mask;
4307                         /* only disable lsc interrupt */
4308                         intr->mask &= ~IXGBE_EIMS_LSC;
4309                 }
4310         }
4311
4312         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4313         ixgbe_enable_intr(dev);
4314         rte_intr_enable(intr_handle);
4315
4316         return 0;
4317 }
4318
4319 /**
4320  * Interrupt handler which shall be registered for alarm callback for delayed
4321  * handling specific interrupt to wait for the stable nic state. As the
4322  * NIC interrupt state is not stable for ixgbe after link is just down,
4323  * it needs to wait 4 seconds to get the stable status.
4324  *
4325  * @param handle
4326  *  Pointer to interrupt handle.
4327  * @param param
4328  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4329  *
4330  * @return
4331  *  void
4332  */
4333 static void
4334 ixgbe_dev_interrupt_delayed_handler(void *param)
4335 {
4336         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4337         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4338         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4339         struct ixgbe_interrupt *intr =
4340                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4341         struct ixgbe_hw *hw =
4342                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4343         uint32_t eicr;
4344
4345         ixgbe_disable_intr(hw);
4346
4347         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4348         if (eicr & IXGBE_EICR_MAILBOX)
4349                 ixgbe_pf_mbx_process(dev);
4350
4351         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4352                 ixgbe_handle_lasi(hw);
4353                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4354         }
4355
4356         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4357                 ixgbe_dev_link_update(dev, 0);
4358                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4359                 ixgbe_dev_link_status_print(dev);
4360                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4361                                               NULL, NULL);
4362         }
4363
4364         if (intr->flags & IXGBE_FLAG_MACSEC) {
4365                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4366                                               NULL, NULL);
4367                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4368         }
4369
4370         /* restore original mask */
4371         intr->mask = intr->mask_original;
4372         intr->mask_original = 0;
4373
4374         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4375         ixgbe_enable_intr(dev);
4376         rte_intr_enable(intr_handle);
4377 }
4378
4379 /**
4380  * Interrupt handler triggered by NIC  for handling
4381  * specific interrupt.
4382  *
4383  * @param handle
4384  *  Pointer to interrupt handle.
4385  * @param param
4386  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4387  *
4388  * @return
4389  *  void
4390  */
4391 static void
4392 ixgbe_dev_interrupt_handler(void *param)
4393 {
4394         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4395
4396         ixgbe_dev_interrupt_get_status(dev);
4397         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4398 }
4399
4400 static int
4401 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4402 {
4403         struct ixgbe_hw *hw;
4404
4405         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4406         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4407 }
4408
4409 static int
4410 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4411 {
4412         struct ixgbe_hw *hw;
4413
4414         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4415         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4416 }
4417
4418 static int
4419 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4420 {
4421         struct ixgbe_hw *hw;
4422         uint32_t mflcn_reg;
4423         uint32_t fccfg_reg;
4424         int rx_pause;
4425         int tx_pause;
4426
4427         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4428
4429         fc_conf->pause_time = hw->fc.pause_time;
4430         fc_conf->high_water = hw->fc.high_water[0];
4431         fc_conf->low_water = hw->fc.low_water[0];
4432         fc_conf->send_xon = hw->fc.send_xon;
4433         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4434
4435         /*
4436          * Return rx_pause status according to actual setting of
4437          * MFLCN register.
4438          */
4439         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4440         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4441                 rx_pause = 1;
4442         else
4443                 rx_pause = 0;
4444
4445         /*
4446          * Return tx_pause status according to actual setting of
4447          * FCCFG register.
4448          */
4449         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4450         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4451                 tx_pause = 1;
4452         else
4453                 tx_pause = 0;
4454
4455         if (rx_pause && tx_pause)
4456                 fc_conf->mode = RTE_FC_FULL;
4457         else if (rx_pause)
4458                 fc_conf->mode = RTE_FC_RX_PAUSE;
4459         else if (tx_pause)
4460                 fc_conf->mode = RTE_FC_TX_PAUSE;
4461         else
4462                 fc_conf->mode = RTE_FC_NONE;
4463
4464         return 0;
4465 }
4466
4467 static int
4468 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4469 {
4470         struct ixgbe_hw *hw;
4471         int err;
4472         uint32_t rx_buf_size;
4473         uint32_t max_high_water;
4474         uint32_t mflcn;
4475         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4476                 ixgbe_fc_none,
4477                 ixgbe_fc_rx_pause,
4478                 ixgbe_fc_tx_pause,
4479                 ixgbe_fc_full
4480         };
4481
4482         PMD_INIT_FUNC_TRACE();
4483
4484         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4485         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4486         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4487
4488         /*
4489          * At least reserve one Ethernet frame for watermark
4490          * high_water/low_water in kilo bytes for ixgbe
4491          */
4492         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4493         if ((fc_conf->high_water > max_high_water) ||
4494                 (fc_conf->high_water < fc_conf->low_water)) {
4495                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4496                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4497                 return -EINVAL;
4498         }
4499
4500         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4501         hw->fc.pause_time     = fc_conf->pause_time;
4502         hw->fc.high_water[0]  = fc_conf->high_water;
4503         hw->fc.low_water[0]   = fc_conf->low_water;
4504         hw->fc.send_xon       = fc_conf->send_xon;
4505         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4506
4507         err = ixgbe_fc_enable(hw);
4508
4509         /* Not negotiated is not an error case */
4510         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4511
4512                 /* check if we want to forward MAC frames - driver doesn't have native
4513                  * capability to do that, so we'll write the registers ourselves */
4514
4515                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4516
4517                 /* set or clear MFLCN.PMCF bit depending on configuration */
4518                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4519                         mflcn |= IXGBE_MFLCN_PMCF;
4520                 else
4521                         mflcn &= ~IXGBE_MFLCN_PMCF;
4522
4523                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4524                 IXGBE_WRITE_FLUSH(hw);
4525
4526                 return 0;
4527         }
4528
4529         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4530         return -EIO;
4531 }
4532
4533 /**
4534  *  ixgbe_pfc_enable_generic - Enable flow control
4535  *  @hw: pointer to hardware structure
4536  *  @tc_num: traffic class number
4537  *  Enable flow control according to the current settings.
4538  */
4539 static int
4540 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4541 {
4542         int ret_val = 0;
4543         uint32_t mflcn_reg, fccfg_reg;
4544         uint32_t reg;
4545         uint32_t fcrtl, fcrth;
4546         uint8_t i;
4547         uint8_t nb_rx_en;
4548
4549         /* Validate the water mark configuration */
4550         if (!hw->fc.pause_time) {
4551                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4552                 goto out;
4553         }
4554
4555         /* Low water mark of zero causes XOFF floods */
4556         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4557                  /* High/Low water can not be 0 */
4558                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4559                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4560                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4561                         goto out;
4562                 }
4563
4564                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4565                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4566                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4567                         goto out;
4568                 }
4569         }
4570         /* Negotiate the fc mode to use */
4571         ixgbe_fc_autoneg(hw);
4572
4573         /* Disable any previous flow control settings */
4574         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4575         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4576
4577         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4578         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4579
4580         switch (hw->fc.current_mode) {
4581         case ixgbe_fc_none:
4582                 /*
4583                  * If the count of enabled RX Priority Flow control >1,
4584                  * and the TX pause can not be disabled
4585                  */
4586                 nb_rx_en = 0;
4587                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4588                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4589                         if (reg & IXGBE_FCRTH_FCEN)
4590                                 nb_rx_en++;
4591                 }
4592                 if (nb_rx_en > 1)
4593                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4594                 break;
4595         case ixgbe_fc_rx_pause:
4596                 /*
4597                  * Rx Flow control is enabled and Tx Flow control is
4598                  * disabled by software override. Since there really
4599                  * isn't a way to advertise that we are capable of RX
4600                  * Pause ONLY, we will advertise that we support both
4601                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4602                  * disable the adapter's ability to send PAUSE frames.
4603                  */
4604                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4605                 /*
4606                  * If the count of enabled RX Priority Flow control >1,
4607                  * and the TX pause can not be disabled
4608                  */
4609                 nb_rx_en = 0;
4610                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4611                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4612                         if (reg & IXGBE_FCRTH_FCEN)
4613                                 nb_rx_en++;
4614                 }
4615                 if (nb_rx_en > 1)
4616                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4617                 break;
4618         case ixgbe_fc_tx_pause:
4619                 /*
4620                  * Tx Flow control is enabled, and Rx Flow control is
4621                  * disabled by software override.
4622                  */
4623                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4624                 break;
4625         case ixgbe_fc_full:
4626                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4627                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4628                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4629                 break;
4630         default:
4631                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4632                 ret_val = IXGBE_ERR_CONFIG;
4633                 goto out;
4634         }
4635
4636         /* Set 802.3x based flow control settings. */
4637         mflcn_reg |= IXGBE_MFLCN_DPF;
4638         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4639         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4640
4641         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4642         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4643                 hw->fc.high_water[tc_num]) {
4644                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4645                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4646                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4647         } else {
4648                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4649                 /*
4650                  * In order to prevent Tx hangs when the internal Tx
4651                  * switch is enabled we must set the high water mark
4652                  * to the maximum FCRTH value.  This allows the Tx
4653                  * switch to function even under heavy Rx workloads.
4654                  */
4655                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4656         }
4657         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4658
4659         /* Configure pause time (2 TCs per register) */
4660         reg = hw->fc.pause_time * 0x00010001;
4661         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4662                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4663
4664         /* Configure flow control refresh threshold value */
4665         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4666
4667 out:
4668         return ret_val;
4669 }
4670
4671 static int
4672 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4673 {
4674         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4675         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4676
4677         if (hw->mac.type != ixgbe_mac_82598EB) {
4678                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4679         }
4680         return ret_val;
4681 }
4682
4683 static int
4684 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4685 {
4686         int err;
4687         uint32_t rx_buf_size;
4688         uint32_t max_high_water;
4689         uint8_t tc_num;
4690         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4691         struct ixgbe_hw *hw =
4692                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4693         struct ixgbe_dcb_config *dcb_config =
4694                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4695
4696         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4697                 ixgbe_fc_none,
4698                 ixgbe_fc_rx_pause,
4699                 ixgbe_fc_tx_pause,
4700                 ixgbe_fc_full
4701         };
4702
4703         PMD_INIT_FUNC_TRACE();
4704
4705         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4706         tc_num = map[pfc_conf->priority];
4707         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4708         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4709         /*
4710          * At least reserve one Ethernet frame for watermark
4711          * high_water/low_water in kilo bytes for ixgbe
4712          */
4713         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4714         if ((pfc_conf->fc.high_water > max_high_water) ||
4715             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4716                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4717                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4718                 return -EINVAL;
4719         }
4720
4721         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4722         hw->fc.pause_time = pfc_conf->fc.pause_time;
4723         hw->fc.send_xon = pfc_conf->fc.send_xon;
4724         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4725         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4726
4727         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4728
4729         /* Not negotiated is not an error case */
4730         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4731                 return 0;
4732
4733         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4734         return -EIO;
4735 }
4736
4737 static int
4738 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4739                           struct rte_eth_rss_reta_entry64 *reta_conf,
4740                           uint16_t reta_size)
4741 {
4742         uint16_t i, sp_reta_size;
4743         uint8_t j, mask;
4744         uint32_t reta, r;
4745         uint16_t idx, shift;
4746         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4747         uint32_t reta_reg;
4748
4749         PMD_INIT_FUNC_TRACE();
4750
4751         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4752                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4753                         "NIC.");
4754                 return -ENOTSUP;
4755         }
4756
4757         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4758         if (reta_size != sp_reta_size) {
4759                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4760                         "(%d) doesn't match the number hardware can supported "
4761                         "(%d)", reta_size, sp_reta_size);
4762                 return -EINVAL;
4763         }
4764
4765         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4766                 idx = i / RTE_RETA_GROUP_SIZE;
4767                 shift = i % RTE_RETA_GROUP_SIZE;
4768                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4769                                                 IXGBE_4_BIT_MASK);
4770                 if (!mask)
4771                         continue;
4772                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4773                 if (mask == IXGBE_4_BIT_MASK)
4774                         r = 0;
4775                 else
4776                         r = IXGBE_READ_REG(hw, reta_reg);
4777                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4778                         if (mask & (0x1 << j))
4779                                 reta |= reta_conf[idx].reta[shift + j] <<
4780                                                         (CHAR_BIT * j);
4781                         else
4782                                 reta |= r & (IXGBE_8_BIT_MASK <<
4783                                                 (CHAR_BIT * j));
4784                 }
4785                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4786         }
4787
4788         return 0;
4789 }
4790
4791 static int
4792 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4793                          struct rte_eth_rss_reta_entry64 *reta_conf,
4794                          uint16_t reta_size)
4795 {
4796         uint16_t i, sp_reta_size;
4797         uint8_t j, mask;
4798         uint32_t reta;
4799         uint16_t idx, shift;
4800         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4801         uint32_t reta_reg;
4802
4803         PMD_INIT_FUNC_TRACE();
4804         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4805         if (reta_size != sp_reta_size) {
4806                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4807                         "(%d) doesn't match the number hardware can supported "
4808                         "(%d)", reta_size, sp_reta_size);
4809                 return -EINVAL;
4810         }
4811
4812         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4813                 idx = i / RTE_RETA_GROUP_SIZE;
4814                 shift = i % RTE_RETA_GROUP_SIZE;
4815                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4816                                                 IXGBE_4_BIT_MASK);
4817                 if (!mask)
4818                         continue;
4819
4820                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4821                 reta = IXGBE_READ_REG(hw, reta_reg);
4822                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4823                         if (mask & (0x1 << j))
4824                                 reta_conf[idx].reta[shift + j] =
4825                                         ((reta >> (CHAR_BIT * j)) &
4826                                                 IXGBE_8_BIT_MASK);
4827                 }
4828         }
4829
4830         return 0;
4831 }
4832
4833 static int
4834 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4835                                 uint32_t index, uint32_t pool)
4836 {
4837         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4838         uint32_t enable_addr = 1;
4839
4840         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4841                              pool, enable_addr);
4842 }
4843
4844 static void
4845 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4846 {
4847         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4848
4849         ixgbe_clear_rar(hw, index);
4850 }
4851
4852 static void
4853 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4854 {
4855         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4856
4857         ixgbe_remove_rar(dev, 0);
4858
4859         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4860 }
4861
4862 static bool
4863 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4864 {
4865         if (strcmp(dev->device->driver->name, drv->driver.name))
4866                 return false;
4867
4868         return true;
4869 }
4870
4871 bool
4872 is_ixgbe_supported(struct rte_eth_dev *dev)
4873 {
4874         return is_device_supported(dev, &rte_ixgbe_pmd);
4875 }
4876
4877 static int
4878 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4879 {
4880         uint32_t hlreg0;
4881         uint32_t maxfrs;
4882         struct ixgbe_hw *hw;
4883         struct rte_eth_dev_info dev_info;
4884         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4885         struct rte_eth_dev_data *dev_data = dev->data;
4886
4887         ixgbe_dev_info_get(dev, &dev_info);
4888
4889         /* check that mtu is within the allowed range */
4890         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4891                 return -EINVAL;
4892
4893         /* If device is started, refuse mtu that requires the support of
4894          * scattered packets when this feature has not been enabled before.
4895          */
4896         if (dev_data->dev_started && !dev_data->scattered_rx &&
4897             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4898              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4899                 PMD_INIT_LOG(ERR, "Stop port first.");
4900                 return -EINVAL;
4901         }
4902
4903         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4904         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4905
4906         /* switch to jumbo mode if needed */
4907         if (frame_size > ETHER_MAX_LEN) {
4908                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4909                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4910         } else {
4911                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4912                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4913         }
4914         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4915
4916         /* update max frame size */
4917         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4918
4919         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4920         maxfrs &= 0x0000FFFF;
4921         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4922         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4923
4924         return 0;
4925 }
4926
4927 /*
4928  * Virtual Function operations
4929  */
4930 static void
4931 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4932 {
4933         PMD_INIT_FUNC_TRACE();
4934
4935         /* Clear interrupt mask to stop from interrupts being generated */
4936         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4937
4938         IXGBE_WRITE_FLUSH(hw);
4939 }
4940
4941 static void
4942 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4943 {
4944         PMD_INIT_FUNC_TRACE();
4945
4946         /* VF enable interrupt autoclean */
4947         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4948         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4949         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4950
4951         IXGBE_WRITE_FLUSH(hw);
4952 }
4953
4954 static int
4955 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4956 {
4957         struct rte_eth_conf *conf = &dev->data->dev_conf;
4958         struct ixgbe_adapter *adapter =
4959                         (struct ixgbe_adapter *)dev->data->dev_private;
4960
4961         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4962                      dev->data->port_id);
4963
4964         /*
4965          * VF has no ability to enable/disable HW CRC
4966          * Keep the persistent behavior the same as Host PF
4967          */
4968 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4969         if (!conf->rxmode.hw_strip_crc) {
4970                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4971                 conf->rxmode.hw_strip_crc = 1;
4972         }
4973 #else
4974         if (conf->rxmode.hw_strip_crc) {
4975                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4976                 conf->rxmode.hw_strip_crc = 0;
4977         }
4978 #endif
4979
4980         /*
4981          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4982          * allocation or vector Rx preconditions we will reset it.
4983          */
4984         adapter->rx_bulk_alloc_allowed = true;
4985         adapter->rx_vec_allowed = true;
4986
4987         return 0;
4988 }
4989
4990 static int
4991 ixgbevf_dev_start(struct rte_eth_dev *dev)
4992 {
4993         struct ixgbe_hw *hw =
4994                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4995         uint32_t intr_vector = 0;
4996         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4997         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4998
4999         int err, mask = 0;
5000
5001         PMD_INIT_FUNC_TRACE();
5002
5003         hw->mac.ops.reset_hw(hw);
5004         hw->mac.get_link_status = true;
5005
5006         /* negotiate mailbox API version to use with the PF. */
5007         ixgbevf_negotiate_api(hw);
5008
5009         ixgbevf_dev_tx_init(dev);
5010
5011         /* This can fail when allocating mbufs for descriptor rings */
5012         err = ixgbevf_dev_rx_init(dev);
5013         if (err) {
5014                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5015                 ixgbe_dev_clear_queues(dev);
5016                 return err;
5017         }
5018
5019         /* Set vfta */
5020         ixgbevf_set_vfta_all(dev, 1);
5021
5022         /* Set HW strip */
5023         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5024                 ETH_VLAN_EXTEND_MASK;
5025         ixgbevf_vlan_offload_set(dev, mask);
5026
5027         ixgbevf_dev_rxtx_start(dev);
5028
5029         /* check and configure queue intr-vector mapping */
5030         if (dev->data->dev_conf.intr_conf.rxq != 0) {
5031                 /* According to datasheet, only vector 0/1/2 can be used,
5032                  * now only one vector is used for Rx queue
5033                  */
5034                 intr_vector = 1;
5035                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5036                         return -1;
5037         }
5038
5039         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5040                 intr_handle->intr_vec =
5041                         rte_zmalloc("intr_vec",
5042                                     dev->data->nb_rx_queues * sizeof(int), 0);
5043                 if (intr_handle->intr_vec == NULL) {
5044                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5045                                      " intr_vec", dev->data->nb_rx_queues);
5046                         return -ENOMEM;
5047                 }
5048         }
5049         ixgbevf_configure_msix(dev);
5050
5051         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5052          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5053          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5054          * is not cleared, it will fail when following rte_intr_enable( ) tries
5055          * to map Rx queue interrupt to other VFIO vectors.
5056          * So clear uio/vfio intr/evevnfd first to avoid failure.
5057          */
5058         rte_intr_disable(intr_handle);
5059
5060         rte_intr_enable(intr_handle);
5061
5062         /* Re-enable interrupt for VF */
5063         ixgbevf_intr_enable(hw);
5064
5065         return 0;
5066 }
5067
5068 static void
5069 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5070 {
5071         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5072         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5073         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5074
5075         PMD_INIT_FUNC_TRACE();
5076
5077         ixgbevf_intr_disable(hw);
5078
5079         hw->adapter_stopped = 1;
5080         ixgbe_stop_adapter(hw);
5081
5082         /*
5083           * Clear what we set, but we still keep shadow_vfta to
5084           * restore after device starts
5085           */
5086         ixgbevf_set_vfta_all(dev, 0);
5087
5088         /* Clear stored conf */
5089         dev->data->scattered_rx = 0;
5090
5091         ixgbe_dev_clear_queues(dev);
5092
5093         /* Clean datapath event and queue/vec mapping */
5094         rte_intr_efd_disable(intr_handle);
5095         if (intr_handle->intr_vec != NULL) {
5096                 rte_free(intr_handle->intr_vec);
5097                 intr_handle->intr_vec = NULL;
5098         }
5099 }
5100
5101 static void
5102 ixgbevf_dev_close(struct rte_eth_dev *dev)
5103 {
5104         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5105
5106         PMD_INIT_FUNC_TRACE();
5107
5108         ixgbe_reset_hw(hw);
5109
5110         ixgbevf_dev_stop(dev);
5111
5112         ixgbe_dev_free_queues(dev);
5113
5114         /**
5115          * Remove the VF MAC address ro ensure
5116          * that the VF traffic goes to the PF
5117          * after stop, close and detach of the VF
5118          **/
5119         ixgbevf_remove_mac_addr(dev, 0);
5120 }
5121
5122 /*
5123  * Reset VF device
5124  */
5125 static int
5126 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5127 {
5128         int ret;
5129
5130         ret = eth_ixgbevf_dev_uninit(dev);
5131         if (ret)
5132                 return ret;
5133
5134         ret = eth_ixgbevf_dev_init(dev);
5135
5136         return ret;
5137 }
5138
5139 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5140 {
5141         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5142         struct ixgbe_vfta *shadow_vfta =
5143                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5144         int i = 0, j = 0, vfta = 0, mask = 1;
5145
5146         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5147                 vfta = shadow_vfta->vfta[i];
5148                 if (vfta) {
5149                         mask = 1;
5150                         for (j = 0; j < 32; j++) {
5151                                 if (vfta & mask)
5152                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5153                                                        on, false);
5154                                 mask <<= 1;
5155                         }
5156                 }
5157         }
5158
5159 }
5160
5161 static int
5162 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5163 {
5164         struct ixgbe_hw *hw =
5165                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5166         struct ixgbe_vfta *shadow_vfta =
5167                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5168         uint32_t vid_idx = 0;
5169         uint32_t vid_bit = 0;
5170         int ret = 0;
5171
5172         PMD_INIT_FUNC_TRACE();
5173
5174         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5175         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5176         if (ret) {
5177                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5178                 return ret;
5179         }
5180         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5181         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5182
5183         /* Save what we set and retore it after device reset */
5184         if (on)
5185                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5186         else
5187                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5188
5189         return 0;
5190 }
5191
5192 static void
5193 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5194 {
5195         struct ixgbe_hw *hw =
5196                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5197         uint32_t ctrl;
5198
5199         PMD_INIT_FUNC_TRACE();
5200
5201         if (queue >= hw->mac.max_rx_queues)
5202                 return;
5203
5204         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5205         if (on)
5206                 ctrl |= IXGBE_RXDCTL_VME;
5207         else
5208                 ctrl &= ~IXGBE_RXDCTL_VME;
5209         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5210
5211         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5212 }
5213
5214 static void
5215 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5216 {
5217         struct ixgbe_hw *hw =
5218                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5219         uint16_t i;
5220         int on = 0;
5221
5222         /* VF function only support hw strip feature, others are not support */
5223         if (mask & ETH_VLAN_STRIP_MASK) {
5224                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5225
5226                 for (i = 0; i < hw->mac.max_rx_queues; i++)
5227                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5228         }
5229 }
5230
5231 int
5232 ixgbe_vt_check(struct ixgbe_hw *hw)
5233 {
5234         uint32_t reg_val;
5235
5236         /* if Virtualization Technology is enabled */
5237         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5238         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5239                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5240                 return -1;
5241         }
5242
5243         return 0;
5244 }
5245
5246 static uint32_t
5247 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5248 {
5249         uint32_t vector = 0;
5250
5251         switch (hw->mac.mc_filter_type) {
5252         case 0:   /* use bits [47:36] of the address */
5253                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5254                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5255                 break;
5256         case 1:   /* use bits [46:35] of the address */
5257                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5258                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5259                 break;
5260         case 2:   /* use bits [45:34] of the address */
5261                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5262                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5263                 break;
5264         case 3:   /* use bits [43:32] of the address */
5265                 vector = ((uc_addr->addr_bytes[4]) |
5266                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5267                 break;
5268         default:  /* Invalid mc_filter_type */
5269                 break;
5270         }
5271
5272         /* vector can only be 12-bits or boundary will be exceeded */
5273         vector &= 0xFFF;
5274         return vector;
5275 }
5276
5277 static int
5278 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5279                         uint8_t on)
5280 {
5281         uint32_t vector;
5282         uint32_t uta_idx;
5283         uint32_t reg_val;
5284         uint32_t uta_shift;
5285         uint32_t rc;
5286         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5287         const uint32_t ixgbe_uta_bit_shift = 5;
5288         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5289         const uint32_t bit1 = 0x1;
5290
5291         struct ixgbe_hw *hw =
5292                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5293         struct ixgbe_uta_info *uta_info =
5294                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5295
5296         /* The UTA table only exists on 82599 hardware and newer */
5297         if (hw->mac.type < ixgbe_mac_82599EB)
5298                 return -ENOTSUP;
5299
5300         vector = ixgbe_uta_vector(hw, mac_addr);
5301         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5302         uta_shift = vector & ixgbe_uta_bit_mask;
5303
5304         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5305         if (rc == on)
5306                 return 0;
5307
5308         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5309         if (on) {
5310                 uta_info->uta_in_use++;
5311                 reg_val |= (bit1 << uta_shift);
5312                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5313         } else {
5314                 uta_info->uta_in_use--;
5315                 reg_val &= ~(bit1 << uta_shift);
5316                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5317         }
5318
5319         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5320
5321         if (uta_info->uta_in_use > 0)
5322                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5323                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5324         else
5325                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5326
5327         return 0;
5328 }
5329
5330 static int
5331 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5332 {
5333         int i;
5334         struct ixgbe_hw *hw =
5335                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5336         struct ixgbe_uta_info *uta_info =
5337                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5338
5339         /* The UTA table only exists on 82599 hardware and newer */
5340         if (hw->mac.type < ixgbe_mac_82599EB)
5341                 return -ENOTSUP;
5342
5343         if (on) {
5344                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5345                         uta_info->uta_shadow[i] = ~0;
5346                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5347                 }
5348         } else {
5349                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5350                         uta_info->uta_shadow[i] = 0;
5351                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5352                 }
5353         }
5354         return 0;
5355
5356 }
5357
5358 uint32_t
5359 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5360 {
5361         uint32_t new_val = orig_val;
5362
5363         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5364                 new_val |= IXGBE_VMOLR_AUPE;
5365         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5366                 new_val |= IXGBE_VMOLR_ROMPE;
5367         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5368                 new_val |= IXGBE_VMOLR_ROPE;
5369         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5370                 new_val |= IXGBE_VMOLR_BAM;
5371         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5372                 new_val |= IXGBE_VMOLR_MPE;
5373
5374         return new_val;
5375 }
5376
5377 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5378 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5379 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5380 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5381 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5382         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5383         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5384
5385 static int
5386 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5387                       struct rte_eth_mirror_conf *mirror_conf,
5388                       uint8_t rule_id, uint8_t on)
5389 {
5390         uint32_t mr_ctl, vlvf;
5391         uint32_t mp_lsb = 0;
5392         uint32_t mv_msb = 0;
5393         uint32_t mv_lsb = 0;
5394         uint32_t mp_msb = 0;
5395         uint8_t i = 0;
5396         int reg_index = 0;
5397         uint64_t vlan_mask = 0;
5398
5399         const uint8_t pool_mask_offset = 32;
5400         const uint8_t vlan_mask_offset = 32;
5401         const uint8_t dst_pool_offset = 8;
5402         const uint8_t rule_mr_offset  = 4;
5403         const uint8_t mirror_rule_mask = 0x0F;
5404
5405         struct ixgbe_mirror_info *mr_info =
5406                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5407         struct ixgbe_hw *hw =
5408                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5409         uint8_t mirror_type = 0;
5410
5411         if (ixgbe_vt_check(hw) < 0)
5412                 return -ENOTSUP;
5413
5414         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5415                 return -EINVAL;
5416
5417         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5418                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5419                             mirror_conf->rule_type);
5420                 return -EINVAL;
5421         }
5422
5423         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5424                 mirror_type |= IXGBE_MRCTL_VLME;
5425                 /* Check if vlan id is valid and find conresponding VLAN ID
5426                  * index in VLVF
5427                  */
5428                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5429                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5430                                 /* search vlan id related pool vlan filter
5431                                  * index
5432                                  */
5433                                 reg_index = ixgbe_find_vlvf_slot(
5434                                                 hw,
5435                                                 mirror_conf->vlan.vlan_id[i],
5436                                                 false);
5437                                 if (reg_index < 0)
5438                                         return -EINVAL;
5439                                 vlvf = IXGBE_READ_REG(hw,
5440                                                       IXGBE_VLVF(reg_index));
5441                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5442                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5443                                       mirror_conf->vlan.vlan_id[i]))
5444                                         vlan_mask |= (1ULL << reg_index);
5445                                 else
5446                                         return -EINVAL;
5447                         }
5448                 }
5449
5450                 if (on) {
5451                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5452                         mv_msb = vlan_mask >> vlan_mask_offset;
5453
5454                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5455                                                 mirror_conf->vlan.vlan_mask;
5456                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5457                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5458                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5459                                                 mirror_conf->vlan.vlan_id[i];
5460                         }
5461                 } else {
5462                         mv_lsb = 0;
5463                         mv_msb = 0;
5464                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5465                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5466                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5467                 }
5468         }
5469
5470         /**
5471          * if enable pool mirror, write related pool mask register,if disable
5472          * pool mirror, clear PFMRVM register
5473          */
5474         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5475                 mirror_type |= IXGBE_MRCTL_VPME;
5476                 if (on) {
5477                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5478                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5479                         mr_info->mr_conf[rule_id].pool_mask =
5480                                         mirror_conf->pool_mask;
5481
5482                 } else {
5483                         mp_lsb = 0;
5484                         mp_msb = 0;
5485                         mr_info->mr_conf[rule_id].pool_mask = 0;
5486                 }
5487         }
5488         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5489                 mirror_type |= IXGBE_MRCTL_UPME;
5490         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5491                 mirror_type |= IXGBE_MRCTL_DPME;
5492
5493         /* read  mirror control register and recalculate it */
5494         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5495
5496         if (on) {
5497                 mr_ctl |= mirror_type;
5498                 mr_ctl &= mirror_rule_mask;
5499                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5500         } else {
5501                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5502         }
5503
5504         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5505         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5506
5507         /* write mirrror control  register */
5508         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5509
5510         /* write pool mirrror control  register */
5511         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5512                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5513                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5514                                 mp_msb);
5515         }
5516         /* write VLAN mirrror control  register */
5517         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5518                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5519                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5520                                 mv_msb);
5521         }
5522
5523         return 0;
5524 }
5525
5526 static int
5527 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5528 {
5529         int mr_ctl = 0;
5530         uint32_t lsb_val = 0;
5531         uint32_t msb_val = 0;
5532         const uint8_t rule_mr_offset = 4;
5533
5534         struct ixgbe_hw *hw =
5535                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5536         struct ixgbe_mirror_info *mr_info =
5537                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5538
5539         if (ixgbe_vt_check(hw) < 0)
5540                 return -ENOTSUP;
5541
5542         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5543                 return -EINVAL;
5544
5545         memset(&mr_info->mr_conf[rule_id], 0,
5546                sizeof(struct rte_eth_mirror_conf));
5547
5548         /* clear PFVMCTL register */
5549         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5550
5551         /* clear pool mask register */
5552         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5553         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5554
5555         /* clear vlan mask register */
5556         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5557         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5558
5559         return 0;
5560 }
5561
5562 static int
5563 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5564 {
5565         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5566         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5567         uint32_t mask;
5568         struct ixgbe_hw *hw =
5569                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5570         uint32_t vec = IXGBE_MISC_VEC_ID;
5571
5572         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5573         if (rte_intr_allow_others(intr_handle))
5574                 vec = IXGBE_RX_VEC_START;
5575         mask |= (1 << vec);
5576         RTE_SET_USED(queue_id);
5577         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5578
5579         rte_intr_enable(intr_handle);
5580
5581         return 0;
5582 }
5583
5584 static int
5585 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5586 {
5587         uint32_t mask;
5588         struct ixgbe_hw *hw =
5589                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5590         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5591         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5592         uint32_t vec = IXGBE_MISC_VEC_ID;
5593
5594         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5595         if (rte_intr_allow_others(intr_handle))
5596                 vec = IXGBE_RX_VEC_START;
5597         mask &= ~(1 << vec);
5598         RTE_SET_USED(queue_id);
5599         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5600
5601         return 0;
5602 }
5603
5604 static int
5605 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5606 {
5607         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5608         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5609         uint32_t mask;
5610         struct ixgbe_hw *hw =
5611                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5612         struct ixgbe_interrupt *intr =
5613                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5614
5615         if (queue_id < 16) {
5616                 ixgbe_disable_intr(hw);
5617                 intr->mask |= (1 << queue_id);
5618                 ixgbe_enable_intr(dev);
5619         } else if (queue_id < 32) {
5620                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5621                 mask &= (1 << queue_id);
5622                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5623         } else if (queue_id < 64) {
5624                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5625                 mask &= (1 << (queue_id - 32));
5626                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5627         }
5628         rte_intr_enable(intr_handle);
5629
5630         return 0;
5631 }
5632
5633 static int
5634 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5635 {
5636         uint32_t mask;
5637         struct ixgbe_hw *hw =
5638                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5639         struct ixgbe_interrupt *intr =
5640                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5641
5642         if (queue_id < 16) {
5643                 ixgbe_disable_intr(hw);
5644                 intr->mask &= ~(1 << queue_id);
5645                 ixgbe_enable_intr(dev);
5646         } else if (queue_id < 32) {
5647                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5648                 mask &= ~(1 << queue_id);
5649                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5650         } else if (queue_id < 64) {
5651                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5652                 mask &= ~(1 << (queue_id - 32));
5653                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5654         }
5655
5656         return 0;
5657 }
5658
5659 static void
5660 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5661                      uint8_t queue, uint8_t msix_vector)
5662 {
5663         uint32_t tmp, idx;
5664
5665         if (direction == -1) {
5666                 /* other causes */
5667                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5668                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5669                 tmp &= ~0xFF;
5670                 tmp |= msix_vector;
5671                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5672         } else {
5673                 /* rx or tx cause */
5674                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5675                 idx = ((16 * (queue & 1)) + (8 * direction));
5676                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5677                 tmp &= ~(0xFF << idx);
5678                 tmp |= (msix_vector << idx);
5679                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5680         }
5681 }
5682
5683 /**
5684  * set the IVAR registers, mapping interrupt causes to vectors
5685  * @param hw
5686  *  pointer to ixgbe_hw struct
5687  * @direction
5688  *  0 for Rx, 1 for Tx, -1 for other causes
5689  * @queue
5690  *  queue to map the corresponding interrupt to
5691  * @msix_vector
5692  *  the vector to map to the corresponding queue
5693  */
5694 static void
5695 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5696                    uint8_t queue, uint8_t msix_vector)
5697 {
5698         uint32_t tmp, idx;
5699
5700         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5701         if (hw->mac.type == ixgbe_mac_82598EB) {
5702                 if (direction == -1)
5703                         direction = 0;
5704                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5705                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5706                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5707                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5708                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5709         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5710                         (hw->mac.type == ixgbe_mac_X540) ||
5711                         (hw->mac.type == ixgbe_mac_X550)) {
5712                 if (direction == -1) {
5713                         /* other causes */
5714                         idx = ((queue & 1) * 8);
5715                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5716                         tmp &= ~(0xFF << idx);
5717                         tmp |= (msix_vector << idx);
5718                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5719                 } else {
5720                         /* rx or tx causes */
5721                         idx = ((16 * (queue & 1)) + (8 * direction));
5722                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5723                         tmp &= ~(0xFF << idx);
5724                         tmp |= (msix_vector << idx);
5725                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5726                 }
5727         }
5728 }
5729
5730 static void
5731 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5732 {
5733         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5734         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5735         struct ixgbe_hw *hw =
5736                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5737         uint32_t q_idx;
5738         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5739         uint32_t base = IXGBE_MISC_VEC_ID;
5740
5741         /* Configure VF other cause ivar */
5742         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5743
5744         /* won't configure msix register if no mapping is done
5745          * between intr vector and event fd.
5746          */
5747         if (!rte_intr_dp_is_en(intr_handle))
5748                 return;
5749
5750         if (rte_intr_allow_others(intr_handle)) {
5751                 base = IXGBE_RX_VEC_START;
5752                 vector_idx = IXGBE_RX_VEC_START;
5753         }
5754
5755         /* Configure all RX queues of VF */
5756         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5757                 /* Force all queue use vector 0,
5758                  * as IXGBE_VF_MAXMSIVECOTR = 1
5759                  */
5760                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5761                 intr_handle->intr_vec[q_idx] = vector_idx;
5762                 if (vector_idx < base + intr_handle->nb_efd - 1)
5763                         vector_idx++;
5764         }
5765 }
5766
5767 /**
5768  * Sets up the hardware to properly generate MSI-X interrupts
5769  * @hw
5770  *  board private structure
5771  */
5772 static void
5773 ixgbe_configure_msix(struct rte_eth_dev *dev)
5774 {
5775         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5776         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5777         struct ixgbe_hw *hw =
5778                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5779         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5780         uint32_t vec = IXGBE_MISC_VEC_ID;
5781         uint32_t mask;
5782         uint32_t gpie;
5783
5784         /* won't configure msix register if no mapping is done
5785          * between intr vector and event fd
5786          */
5787         if (!rte_intr_dp_is_en(intr_handle))
5788                 return;
5789
5790         if (rte_intr_allow_others(intr_handle))
5791                 vec = base = IXGBE_RX_VEC_START;
5792
5793         /* setup GPIE for MSI-x mode */
5794         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5795         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5796                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5797         /* auto clearing and auto setting corresponding bits in EIMS
5798          * when MSI-X interrupt is triggered
5799          */
5800         if (hw->mac.type == ixgbe_mac_82598EB) {
5801                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5802         } else {
5803                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5804                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5805         }
5806         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5807
5808         /* Populate the IVAR table and set the ITR values to the
5809          * corresponding register.
5810          */
5811         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5812              queue_id++) {
5813                 /* by default, 1:1 mapping */
5814                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5815                 intr_handle->intr_vec[queue_id] = vec;
5816                 if (vec < base + intr_handle->nb_efd - 1)
5817                         vec++;
5818         }
5819
5820         switch (hw->mac.type) {
5821         case ixgbe_mac_82598EB:
5822                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5823                                    IXGBE_MISC_VEC_ID);
5824                 break;
5825         case ixgbe_mac_82599EB:
5826         case ixgbe_mac_X540:
5827         case ixgbe_mac_X550:
5828                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5829                 break;
5830         default:
5831                 break;
5832         }
5833         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5834                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5835
5836         /* set up to autoclear timer, and the vectors */
5837         mask = IXGBE_EIMS_ENABLE_MASK;
5838         mask &= ~(IXGBE_EIMS_OTHER |
5839                   IXGBE_EIMS_MAILBOX |
5840                   IXGBE_EIMS_LSC);
5841
5842         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5843 }
5844
5845 int
5846 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5847                            uint16_t queue_idx, uint16_t tx_rate)
5848 {
5849         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5850         uint32_t rf_dec, rf_int;
5851         uint32_t bcnrc_val;
5852         uint16_t link_speed = dev->data->dev_link.link_speed;
5853
5854         if (queue_idx >= hw->mac.max_tx_queues)
5855                 return -EINVAL;
5856
5857         if (tx_rate != 0) {
5858                 /* Calculate the rate factor values to set */
5859                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5860                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5861                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5862
5863                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5864                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5865                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5866                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5867         } else {
5868                 bcnrc_val = 0;
5869         }
5870
5871         /*
5872          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5873          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5874          * set as 0x4.
5875          */
5876         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5877                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5878                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5879                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5880                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5881         else
5882                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5883                         IXGBE_MMW_SIZE_DEFAULT);
5884
5885         /* Set RTTBCNRC of queue X */
5886         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5887         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5888         IXGBE_WRITE_FLUSH(hw);
5889
5890         return 0;
5891 }
5892
5893 static int
5894 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5895                      __attribute__((unused)) uint32_t index,
5896                      __attribute__((unused)) uint32_t pool)
5897 {
5898         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5899         int diag;
5900
5901         /*
5902          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5903          * operation. Trap this case to avoid exhausting the [very limited]
5904          * set of PF resources used to store VF MAC addresses.
5905          */
5906         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5907                 return -1;
5908         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5909         if (diag != 0)
5910                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5911                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5912                             mac_addr->addr_bytes[0],
5913                             mac_addr->addr_bytes[1],
5914                             mac_addr->addr_bytes[2],
5915                             mac_addr->addr_bytes[3],
5916                             mac_addr->addr_bytes[4],
5917                             mac_addr->addr_bytes[5],
5918                             diag);
5919         return diag;
5920 }
5921
5922 static void
5923 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5924 {
5925         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5926         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5927         struct ether_addr *mac_addr;
5928         uint32_t i;
5929         int diag;
5930
5931         /*
5932          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5933          * not support the deletion of a given MAC address.
5934          * Instead, it imposes to delete all MAC addresses, then to add again
5935          * all MAC addresses with the exception of the one to be deleted.
5936          */
5937         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5938
5939         /*
5940          * Add again all MAC addresses, with the exception of the deleted one
5941          * and of the permanent MAC address.
5942          */
5943         for (i = 0, mac_addr = dev->data->mac_addrs;
5944              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5945                 /* Skip the deleted MAC address */
5946                 if (i == index)
5947                         continue;
5948                 /* Skip NULL MAC addresses */
5949                 if (is_zero_ether_addr(mac_addr))
5950                         continue;
5951                 /* Skip the permanent MAC address */
5952                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5953                         continue;
5954                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5955                 if (diag != 0)
5956                         PMD_DRV_LOG(ERR,
5957                                     "Adding again MAC address "
5958                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5959                                     "diag=%d",
5960                                     mac_addr->addr_bytes[0],
5961                                     mac_addr->addr_bytes[1],
5962                                     mac_addr->addr_bytes[2],
5963                                     mac_addr->addr_bytes[3],
5964                                     mac_addr->addr_bytes[4],
5965                                     mac_addr->addr_bytes[5],
5966                                     diag);
5967         }
5968 }
5969
5970 static void
5971 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5972 {
5973         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5974
5975         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5976 }
5977
5978 int
5979 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5980                         struct rte_eth_syn_filter *filter,
5981                         bool add)
5982 {
5983         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5984         struct ixgbe_filter_info *filter_info =
5985                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5986         uint32_t syn_info;
5987         uint32_t synqf;
5988
5989         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5990                 return -EINVAL;
5991
5992         syn_info = filter_info->syn_info;
5993
5994         if (add) {
5995                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5996                         return -EINVAL;
5997                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5998                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5999
6000                 if (filter->hig_pri)
6001                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6002                 else
6003                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6004         } else {
6005                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6006                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6007                         return -ENOENT;
6008                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6009         }
6010
6011         filter_info->syn_info = synqf;
6012         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6013         IXGBE_WRITE_FLUSH(hw);
6014         return 0;
6015 }
6016
6017 static int
6018 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6019                         struct rte_eth_syn_filter *filter)
6020 {
6021         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6022         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6023
6024         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6025                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6026                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6027                 return 0;
6028         }
6029         return -ENOENT;
6030 }
6031
6032 static int
6033 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6034                         enum rte_filter_op filter_op,
6035                         void *arg)
6036 {
6037         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6038         int ret;
6039
6040         MAC_TYPE_FILTER_SUP(hw->mac.type);
6041
6042         if (filter_op == RTE_ETH_FILTER_NOP)
6043                 return 0;
6044
6045         if (arg == NULL) {
6046                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6047                             filter_op);
6048                 return -EINVAL;
6049         }
6050
6051         switch (filter_op) {
6052         case RTE_ETH_FILTER_ADD:
6053                 ret = ixgbe_syn_filter_set(dev,
6054                                 (struct rte_eth_syn_filter *)arg,
6055                                 TRUE);
6056                 break;
6057         case RTE_ETH_FILTER_DELETE:
6058                 ret = ixgbe_syn_filter_set(dev,
6059                                 (struct rte_eth_syn_filter *)arg,
6060                                 FALSE);
6061                 break;
6062         case RTE_ETH_FILTER_GET:
6063                 ret = ixgbe_syn_filter_get(dev,
6064                                 (struct rte_eth_syn_filter *)arg);
6065                 break;
6066         default:
6067                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6068                 ret = -EINVAL;
6069                 break;
6070         }
6071
6072         return ret;
6073 }
6074
6075
6076 static inline enum ixgbe_5tuple_protocol
6077 convert_protocol_type(uint8_t protocol_value)
6078 {
6079         if (protocol_value == IPPROTO_TCP)
6080                 return IXGBE_FILTER_PROTOCOL_TCP;
6081         else if (protocol_value == IPPROTO_UDP)
6082                 return IXGBE_FILTER_PROTOCOL_UDP;
6083         else if (protocol_value == IPPROTO_SCTP)
6084                 return IXGBE_FILTER_PROTOCOL_SCTP;
6085         else
6086                 return IXGBE_FILTER_PROTOCOL_NONE;
6087 }
6088
6089 /* inject a 5-tuple filter to HW */
6090 static inline void
6091 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6092                            struct ixgbe_5tuple_filter *filter)
6093 {
6094         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6095         int i;
6096         uint32_t ftqf, sdpqf;
6097         uint32_t l34timir = 0;
6098         uint8_t mask = 0xff;
6099
6100         i = filter->index;
6101
6102         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6103                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6104         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6105
6106         ftqf = (uint32_t)(filter->filter_info.proto &
6107                 IXGBE_FTQF_PROTOCOL_MASK);
6108         ftqf |= (uint32_t)((filter->filter_info.priority &
6109                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6110         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6111                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6112         if (filter->filter_info.dst_ip_mask == 0)
6113                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6114         if (filter->filter_info.src_port_mask == 0)
6115                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6116         if (filter->filter_info.dst_port_mask == 0)
6117                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6118         if (filter->filter_info.proto_mask == 0)
6119                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6120         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6121         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6122         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6123
6124         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6125         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6126         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6127         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6128
6129         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6130         l34timir |= (uint32_t)(filter->queue <<
6131                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6132         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6133 }
6134
6135 /*
6136  * add a 5tuple filter
6137  *
6138  * @param
6139  * dev: Pointer to struct rte_eth_dev.
6140  * index: the index the filter allocates.
6141  * filter: ponter to the filter that will be added.
6142  * rx_queue: the queue id the filter assigned to.
6143  *
6144  * @return
6145  *    - On success, zero.
6146  *    - On failure, a negative value.
6147  */
6148 static int
6149 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6150                         struct ixgbe_5tuple_filter *filter)
6151 {
6152         struct ixgbe_filter_info *filter_info =
6153                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6154         int i, idx, shift;
6155
6156         /*
6157          * look for an unused 5tuple filter index,
6158          * and insert the filter to list.
6159          */
6160         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6161                 idx = i / (sizeof(uint32_t) * NBBY);
6162                 shift = i % (sizeof(uint32_t) * NBBY);
6163                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6164                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6165                         filter->index = i;
6166                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6167                                           filter,
6168                                           entries);
6169                         break;
6170                 }
6171         }
6172         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6173                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6174                 return -ENOSYS;
6175         }
6176
6177         ixgbe_inject_5tuple_filter(dev, filter);
6178
6179         return 0;
6180 }
6181
6182 /*
6183  * remove a 5tuple filter
6184  *
6185  * @param
6186  * dev: Pointer to struct rte_eth_dev.
6187  * filter: the pointer of the filter will be removed.
6188  */
6189 static void
6190 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6191                         struct ixgbe_5tuple_filter *filter)
6192 {
6193         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6194         struct ixgbe_filter_info *filter_info =
6195                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6196         uint16_t index = filter->index;
6197
6198         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6199                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6200         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6201         rte_free(filter);
6202
6203         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6204         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6205         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6206         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6207         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6208 }
6209
6210 static int
6211 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6212 {
6213         struct ixgbe_hw *hw;
6214         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6215         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6216
6217         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6218
6219         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6220                 return -EINVAL;
6221
6222         /* refuse mtu that requires the support of scattered packets when this
6223          * feature has not been enabled before.
6224          */
6225         if (!rx_conf->enable_scatter &&
6226             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6227              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6228                 return -EINVAL;
6229
6230         /*
6231          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6232          * request of the version 2.0 of the mailbox API.
6233          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6234          * of the mailbox API.
6235          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6236          * prior to 3.11.33 which contains the following change:
6237          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6238          */
6239         ixgbevf_rlpml_set_vf(hw, max_frame);
6240
6241         /* update max frame size */
6242         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6243         return 0;
6244 }
6245
6246 static inline struct ixgbe_5tuple_filter *
6247 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6248                         struct ixgbe_5tuple_filter_info *key)
6249 {
6250         struct ixgbe_5tuple_filter *it;
6251
6252         TAILQ_FOREACH(it, filter_list, entries) {
6253                 if (memcmp(key, &it->filter_info,
6254                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6255                         return it;
6256                 }
6257         }
6258         return NULL;
6259 }
6260
6261 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6262 static inline int
6263 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6264                         struct ixgbe_5tuple_filter_info *filter_info)
6265 {
6266         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6267                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6268                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6269                 return -EINVAL;
6270
6271         switch (filter->dst_ip_mask) {
6272         case UINT32_MAX:
6273                 filter_info->dst_ip_mask = 0;
6274                 filter_info->dst_ip = filter->dst_ip;
6275                 break;
6276         case 0:
6277                 filter_info->dst_ip_mask = 1;
6278                 break;
6279         default:
6280                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6281                 return -EINVAL;
6282         }
6283
6284         switch (filter->src_ip_mask) {
6285         case UINT32_MAX:
6286                 filter_info->src_ip_mask = 0;
6287                 filter_info->src_ip = filter->src_ip;
6288                 break;
6289         case 0:
6290                 filter_info->src_ip_mask = 1;
6291                 break;
6292         default:
6293                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6294                 return -EINVAL;
6295         }
6296
6297         switch (filter->dst_port_mask) {
6298         case UINT16_MAX:
6299                 filter_info->dst_port_mask = 0;
6300                 filter_info->dst_port = filter->dst_port;
6301                 break;
6302         case 0:
6303                 filter_info->dst_port_mask = 1;
6304                 break;
6305         default:
6306                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6307                 return -EINVAL;
6308         }
6309
6310         switch (filter->src_port_mask) {
6311         case UINT16_MAX:
6312                 filter_info->src_port_mask = 0;
6313                 filter_info->src_port = filter->src_port;
6314                 break;
6315         case 0:
6316                 filter_info->src_port_mask = 1;
6317                 break;
6318         default:
6319                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6320                 return -EINVAL;
6321         }
6322
6323         switch (filter->proto_mask) {
6324         case UINT8_MAX:
6325                 filter_info->proto_mask = 0;
6326                 filter_info->proto =
6327                         convert_protocol_type(filter->proto);
6328                 break;
6329         case 0:
6330                 filter_info->proto_mask = 1;
6331                 break;
6332         default:
6333                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6334                 return -EINVAL;
6335         }
6336
6337         filter_info->priority = (uint8_t)filter->priority;
6338         return 0;
6339 }
6340
6341 /*
6342  * add or delete a ntuple filter
6343  *
6344  * @param
6345  * dev: Pointer to struct rte_eth_dev.
6346  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6347  * add: if true, add filter, if false, remove filter
6348  *
6349  * @return
6350  *    - On success, zero.
6351  *    - On failure, a negative value.
6352  */
6353 int
6354 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6355                         struct rte_eth_ntuple_filter *ntuple_filter,
6356                         bool add)
6357 {
6358         struct ixgbe_filter_info *filter_info =
6359                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6360         struct ixgbe_5tuple_filter_info filter_5tuple;
6361         struct ixgbe_5tuple_filter *filter;
6362         int ret;
6363
6364         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6365                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6366                 return -EINVAL;
6367         }
6368
6369         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6370         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6371         if (ret < 0)
6372                 return ret;
6373
6374         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6375                                          &filter_5tuple);
6376         if (filter != NULL && add) {
6377                 PMD_DRV_LOG(ERR, "filter exists.");
6378                 return -EEXIST;
6379         }
6380         if (filter == NULL && !add) {
6381                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6382                 return -ENOENT;
6383         }
6384
6385         if (add) {
6386                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6387                                 sizeof(struct ixgbe_5tuple_filter), 0);
6388                 if (filter == NULL)
6389                         return -ENOMEM;
6390                 rte_memcpy(&filter->filter_info,
6391                                  &filter_5tuple,
6392                                  sizeof(struct ixgbe_5tuple_filter_info));
6393                 filter->queue = ntuple_filter->queue;
6394                 ret = ixgbe_add_5tuple_filter(dev, filter);
6395                 if (ret < 0) {
6396                         rte_free(filter);
6397                         return ret;
6398                 }
6399         } else
6400                 ixgbe_remove_5tuple_filter(dev, filter);
6401
6402         return 0;
6403 }
6404
6405 /*
6406  * get a ntuple filter
6407  *
6408  * @param
6409  * dev: Pointer to struct rte_eth_dev.
6410  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6411  *
6412  * @return
6413  *    - On success, zero.
6414  *    - On failure, a negative value.
6415  */
6416 static int
6417 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6418                         struct rte_eth_ntuple_filter *ntuple_filter)
6419 {
6420         struct ixgbe_filter_info *filter_info =
6421                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6422         struct ixgbe_5tuple_filter_info filter_5tuple;
6423         struct ixgbe_5tuple_filter *filter;
6424         int ret;
6425
6426         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6427                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6428                 return -EINVAL;
6429         }
6430
6431         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6432         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6433         if (ret < 0)
6434                 return ret;
6435
6436         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6437                                          &filter_5tuple);
6438         if (filter == NULL) {
6439                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6440                 return -ENOENT;
6441         }
6442         ntuple_filter->queue = filter->queue;
6443         return 0;
6444 }
6445
6446 /*
6447  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6448  * @dev: pointer to rte_eth_dev structure
6449  * @filter_op:operation will be taken.
6450  * @arg: a pointer to specific structure corresponding to the filter_op
6451  *
6452  * @return
6453  *    - On success, zero.
6454  *    - On failure, a negative value.
6455  */
6456 static int
6457 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6458                                 enum rte_filter_op filter_op,
6459                                 void *arg)
6460 {
6461         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6462         int ret;
6463
6464         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6465
6466         if (filter_op == RTE_ETH_FILTER_NOP)
6467                 return 0;
6468
6469         if (arg == NULL) {
6470                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6471                             filter_op);
6472                 return -EINVAL;
6473         }
6474
6475         switch (filter_op) {
6476         case RTE_ETH_FILTER_ADD:
6477                 ret = ixgbe_add_del_ntuple_filter(dev,
6478                         (struct rte_eth_ntuple_filter *)arg,
6479                         TRUE);
6480                 break;
6481         case RTE_ETH_FILTER_DELETE:
6482                 ret = ixgbe_add_del_ntuple_filter(dev,
6483                         (struct rte_eth_ntuple_filter *)arg,
6484                         FALSE);
6485                 break;
6486         case RTE_ETH_FILTER_GET:
6487                 ret = ixgbe_get_ntuple_filter(dev,
6488                         (struct rte_eth_ntuple_filter *)arg);
6489                 break;
6490         default:
6491                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6492                 ret = -EINVAL;
6493                 break;
6494         }
6495         return ret;
6496 }
6497
6498 int
6499 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6500                         struct rte_eth_ethertype_filter *filter,
6501                         bool add)
6502 {
6503         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6504         struct ixgbe_filter_info *filter_info =
6505                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6506         uint32_t etqf = 0;
6507         uint32_t etqs = 0;
6508         int ret;
6509         struct ixgbe_ethertype_filter ethertype_filter;
6510
6511         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6512                 return -EINVAL;
6513
6514         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6515                 filter->ether_type == ETHER_TYPE_IPv6) {
6516                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6517                         " ethertype filter.", filter->ether_type);
6518                 return -EINVAL;
6519         }
6520
6521         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6522                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6523                 return -EINVAL;
6524         }
6525         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6526                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6527                 return -EINVAL;
6528         }
6529
6530         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6531         if (ret >= 0 && add) {
6532                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6533                             filter->ether_type);
6534                 return -EEXIST;
6535         }
6536         if (ret < 0 && !add) {
6537                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6538                             filter->ether_type);
6539                 return -ENOENT;
6540         }
6541
6542         if (add) {
6543                 etqf = IXGBE_ETQF_FILTER_EN;
6544                 etqf |= (uint32_t)filter->ether_type;
6545                 etqs |= (uint32_t)((filter->queue <<
6546                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6547                                     IXGBE_ETQS_RX_QUEUE);
6548                 etqs |= IXGBE_ETQS_QUEUE_EN;
6549
6550                 ethertype_filter.ethertype = filter->ether_type;
6551                 ethertype_filter.etqf = etqf;
6552                 ethertype_filter.etqs = etqs;
6553                 ethertype_filter.conf = FALSE;
6554                 ret = ixgbe_ethertype_filter_insert(filter_info,
6555                                                     &ethertype_filter);
6556                 if (ret < 0) {
6557                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6558                         return -ENOSPC;
6559                 }
6560         } else {
6561                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6562                 if (ret < 0)
6563                         return -ENOSYS;
6564         }
6565         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6566         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6567         IXGBE_WRITE_FLUSH(hw);
6568
6569         return 0;
6570 }
6571
6572 static int
6573 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6574                         struct rte_eth_ethertype_filter *filter)
6575 {
6576         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6577         struct ixgbe_filter_info *filter_info =
6578                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6579         uint32_t etqf, etqs;
6580         int ret;
6581
6582         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6583         if (ret < 0) {
6584                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6585                             filter->ether_type);
6586                 return -ENOENT;
6587         }
6588
6589         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6590         if (etqf & IXGBE_ETQF_FILTER_EN) {
6591                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6592                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6593                 filter->flags = 0;
6594                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6595                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6596                 return 0;
6597         }
6598         return -ENOENT;
6599 }
6600
6601 /*
6602  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6603  * @dev: pointer to rte_eth_dev structure
6604  * @filter_op:operation will be taken.
6605  * @arg: a pointer to specific structure corresponding to the filter_op
6606  */
6607 static int
6608 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6609                                 enum rte_filter_op filter_op,
6610                                 void *arg)
6611 {
6612         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6613         int ret;
6614
6615         MAC_TYPE_FILTER_SUP(hw->mac.type);
6616
6617         if (filter_op == RTE_ETH_FILTER_NOP)
6618                 return 0;
6619
6620         if (arg == NULL) {
6621                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6622                             filter_op);
6623                 return -EINVAL;
6624         }
6625
6626         switch (filter_op) {
6627         case RTE_ETH_FILTER_ADD:
6628                 ret = ixgbe_add_del_ethertype_filter(dev,
6629                         (struct rte_eth_ethertype_filter *)arg,
6630                         TRUE);
6631                 break;
6632         case RTE_ETH_FILTER_DELETE:
6633                 ret = ixgbe_add_del_ethertype_filter(dev,
6634                         (struct rte_eth_ethertype_filter *)arg,
6635                         FALSE);
6636                 break;
6637         case RTE_ETH_FILTER_GET:
6638                 ret = ixgbe_get_ethertype_filter(dev,
6639                         (struct rte_eth_ethertype_filter *)arg);
6640                 break;
6641         default:
6642                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6643                 ret = -EINVAL;
6644                 break;
6645         }
6646         return ret;
6647 }
6648
6649 static int
6650 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6651                      enum rte_filter_type filter_type,
6652                      enum rte_filter_op filter_op,
6653                      void *arg)
6654 {
6655         int ret = 0;
6656
6657         switch (filter_type) {
6658         case RTE_ETH_FILTER_NTUPLE:
6659                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6660                 break;
6661         case RTE_ETH_FILTER_ETHERTYPE:
6662                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6663                 break;
6664         case RTE_ETH_FILTER_SYN:
6665                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6666                 break;
6667         case RTE_ETH_FILTER_FDIR:
6668                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6669                 break;
6670         case RTE_ETH_FILTER_L2_TUNNEL:
6671                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6672                 break;
6673         case RTE_ETH_FILTER_GENERIC:
6674                 if (filter_op != RTE_ETH_FILTER_GET)
6675                         return -EINVAL;
6676                 *(const void **)arg = &ixgbe_flow_ops;
6677                 break;
6678         default:
6679                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6680                                                         filter_type);
6681                 ret = -EINVAL;
6682                 break;
6683         }
6684
6685         return ret;
6686 }
6687
6688 static u8 *
6689 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6690                         u8 **mc_addr_ptr, u32 *vmdq)
6691 {
6692         u8 *mc_addr;
6693
6694         *vmdq = 0;
6695         mc_addr = *mc_addr_ptr;
6696         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6697         return mc_addr;
6698 }
6699
6700 static int
6701 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6702                           struct ether_addr *mc_addr_set,
6703                           uint32_t nb_mc_addr)
6704 {
6705         struct ixgbe_hw *hw;
6706         u8 *mc_addr_list;
6707
6708         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6709         mc_addr_list = (u8 *)mc_addr_set;
6710         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6711                                          ixgbe_dev_addr_list_itr, TRUE);
6712 }
6713
6714 static uint64_t
6715 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6716 {
6717         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6718         uint64_t systime_cycles;
6719
6720         switch (hw->mac.type) {
6721         case ixgbe_mac_X550:
6722         case ixgbe_mac_X550EM_x:
6723         case ixgbe_mac_X550EM_a:
6724                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6725                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6726                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6727                                 * NSEC_PER_SEC;
6728                 break;
6729         default:
6730                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6731                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6732                                 << 32;
6733         }
6734
6735         return systime_cycles;
6736 }
6737
6738 static uint64_t
6739 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6740 {
6741         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6742         uint64_t rx_tstamp_cycles;
6743
6744         switch (hw->mac.type) {
6745         case ixgbe_mac_X550:
6746         case ixgbe_mac_X550EM_x:
6747         case ixgbe_mac_X550EM_a:
6748                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6749                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6750                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6751                                 * NSEC_PER_SEC;
6752                 break;
6753         default:
6754                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6755                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6756                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6757                                 << 32;
6758         }
6759
6760         return rx_tstamp_cycles;
6761 }
6762
6763 static uint64_t
6764 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6765 {
6766         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6767         uint64_t tx_tstamp_cycles;
6768
6769         switch (hw->mac.type) {
6770         case ixgbe_mac_X550:
6771         case ixgbe_mac_X550EM_x:
6772         case ixgbe_mac_X550EM_a:
6773                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6774                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6775                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6776                                 * NSEC_PER_SEC;
6777                 break;
6778         default:
6779                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6780                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6781                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6782                                 << 32;
6783         }
6784
6785         return tx_tstamp_cycles;
6786 }
6787
6788 static void
6789 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6790 {
6791         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6792         struct ixgbe_adapter *adapter =
6793                 (struct ixgbe_adapter *)dev->data->dev_private;
6794         struct rte_eth_link link;
6795         uint32_t incval = 0;
6796         uint32_t shift = 0;
6797
6798         /* Get current link speed. */
6799         memset(&link, 0, sizeof(link));
6800         ixgbe_dev_link_update(dev, 1);
6801         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6802
6803         switch (link.link_speed) {
6804         case ETH_SPEED_NUM_100M:
6805                 incval = IXGBE_INCVAL_100;
6806                 shift = IXGBE_INCVAL_SHIFT_100;
6807                 break;
6808         case ETH_SPEED_NUM_1G:
6809                 incval = IXGBE_INCVAL_1GB;
6810                 shift = IXGBE_INCVAL_SHIFT_1GB;
6811                 break;
6812         case ETH_SPEED_NUM_10G:
6813         default:
6814                 incval = IXGBE_INCVAL_10GB;
6815                 shift = IXGBE_INCVAL_SHIFT_10GB;
6816                 break;
6817         }
6818
6819         switch (hw->mac.type) {
6820         case ixgbe_mac_X550:
6821         case ixgbe_mac_X550EM_x:
6822         case ixgbe_mac_X550EM_a:
6823                 /* Independent of link speed. */
6824                 incval = 1;
6825                 /* Cycles read will be interpreted as ns. */
6826                 shift = 0;
6827                 /* Fall-through */
6828         case ixgbe_mac_X540:
6829                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6830                 break;
6831         case ixgbe_mac_82599EB:
6832                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6833                 shift -= IXGBE_INCVAL_SHIFT_82599;
6834                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6835                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6836                 break;
6837         default:
6838                 /* Not supported. */
6839                 return;
6840         }
6841
6842         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6843         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6844         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6845
6846         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6847         adapter->systime_tc.cc_shift = shift;
6848         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6849
6850         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6851         adapter->rx_tstamp_tc.cc_shift = shift;
6852         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6853
6854         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6855         adapter->tx_tstamp_tc.cc_shift = shift;
6856         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6857 }
6858
6859 static int
6860 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6861 {
6862         struct ixgbe_adapter *adapter =
6863                         (struct ixgbe_adapter *)dev->data->dev_private;
6864
6865         adapter->systime_tc.nsec += delta;
6866         adapter->rx_tstamp_tc.nsec += delta;
6867         adapter->tx_tstamp_tc.nsec += delta;
6868
6869         return 0;
6870 }
6871
6872 static int
6873 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6874 {
6875         uint64_t ns;
6876         struct ixgbe_adapter *adapter =
6877                         (struct ixgbe_adapter *)dev->data->dev_private;
6878
6879         ns = rte_timespec_to_ns(ts);
6880         /* Set the timecounters to a new value. */
6881         adapter->systime_tc.nsec = ns;
6882         adapter->rx_tstamp_tc.nsec = ns;
6883         adapter->tx_tstamp_tc.nsec = ns;
6884
6885         return 0;
6886 }
6887
6888 static int
6889 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6890 {
6891         uint64_t ns, systime_cycles;
6892         struct ixgbe_adapter *adapter =
6893                         (struct ixgbe_adapter *)dev->data->dev_private;
6894
6895         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6896         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6897         *ts = rte_ns_to_timespec(ns);
6898
6899         return 0;
6900 }
6901
6902 static int
6903 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6904 {
6905         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6906         uint32_t tsync_ctl;
6907         uint32_t tsauxc;
6908
6909         /* Stop the timesync system time. */
6910         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6911         /* Reset the timesync system time value. */
6912         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6913         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6914
6915         /* Enable system time for platforms where it isn't on by default. */
6916         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6917         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6918         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6919
6920         ixgbe_start_timecounters(dev);
6921
6922         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6923         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6924                         (ETHER_TYPE_1588 |
6925                          IXGBE_ETQF_FILTER_EN |
6926                          IXGBE_ETQF_1588));
6927
6928         /* Enable timestamping of received PTP packets. */
6929         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6930         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6931         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6932
6933         /* Enable timestamping of transmitted PTP packets. */
6934         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6935         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6936         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6937
6938         IXGBE_WRITE_FLUSH(hw);
6939
6940         return 0;
6941 }
6942
6943 static int
6944 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6945 {
6946         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6947         uint32_t tsync_ctl;
6948
6949         /* Disable timestamping of transmitted PTP packets. */
6950         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6951         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6952         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6953
6954         /* Disable timestamping of received PTP packets. */
6955         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6956         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6957         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6958
6959         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6960         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6961
6962         /* Stop incrementating the System Time registers. */
6963         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6964
6965         return 0;
6966 }
6967
6968 static int
6969 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6970                                  struct timespec *timestamp,
6971                                  uint32_t flags __rte_unused)
6972 {
6973         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6974         struct ixgbe_adapter *adapter =
6975                 (struct ixgbe_adapter *)dev->data->dev_private;
6976         uint32_t tsync_rxctl;
6977         uint64_t rx_tstamp_cycles;
6978         uint64_t ns;
6979
6980         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6981         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6982                 return -EINVAL;
6983
6984         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6985         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6986         *timestamp = rte_ns_to_timespec(ns);
6987
6988         return  0;
6989 }
6990
6991 static int
6992 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6993                                  struct timespec *timestamp)
6994 {
6995         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6996         struct ixgbe_adapter *adapter =
6997                 (struct ixgbe_adapter *)dev->data->dev_private;
6998         uint32_t tsync_txctl;
6999         uint64_t tx_tstamp_cycles;
7000         uint64_t ns;
7001
7002         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7003         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7004                 return -EINVAL;
7005
7006         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7007         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7008         *timestamp = rte_ns_to_timespec(ns);
7009
7010         return 0;
7011 }
7012
7013 static int
7014 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7015 {
7016         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7017         int count = 0;
7018         int g_ind = 0;
7019         const struct reg_info *reg_group;
7020         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7021                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7022
7023         while ((reg_group = reg_set[g_ind++]))
7024                 count += ixgbe_regs_group_count(reg_group);
7025
7026         return count;
7027 }
7028
7029 static int
7030 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7031 {
7032         int count = 0;
7033         int g_ind = 0;
7034         const struct reg_info *reg_group;
7035
7036         while ((reg_group = ixgbevf_regs[g_ind++]))
7037                 count += ixgbe_regs_group_count(reg_group);
7038
7039         return count;
7040 }
7041
7042 static int
7043 ixgbe_get_regs(struct rte_eth_dev *dev,
7044               struct rte_dev_reg_info *regs)
7045 {
7046         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7047         uint32_t *data = regs->data;
7048         int g_ind = 0;
7049         int count = 0;
7050         const struct reg_info *reg_group;
7051         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7052                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7053
7054         if (data == NULL) {
7055                 regs->length = ixgbe_get_reg_length(dev);
7056                 regs->width = sizeof(uint32_t);
7057                 return 0;
7058         }
7059
7060         /* Support only full register dump */
7061         if ((regs->length == 0) ||
7062             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7063                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7064                         hw->device_id;
7065                 while ((reg_group = reg_set[g_ind++]))
7066                         count += ixgbe_read_regs_group(dev, &data[count],
7067                                 reg_group);
7068                 return 0;
7069         }
7070
7071         return -ENOTSUP;
7072 }
7073
7074 static int
7075 ixgbevf_get_regs(struct rte_eth_dev *dev,
7076                 struct rte_dev_reg_info *regs)
7077 {
7078         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7079         uint32_t *data = regs->data;
7080         int g_ind = 0;
7081         int count = 0;
7082         const struct reg_info *reg_group;
7083
7084         if (data == NULL) {
7085                 regs->length = ixgbevf_get_reg_length(dev);
7086                 regs->width = sizeof(uint32_t);
7087                 return 0;
7088         }
7089
7090         /* Support only full register dump */
7091         if ((regs->length == 0) ||
7092             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7093                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7094                         hw->device_id;
7095                 while ((reg_group = ixgbevf_regs[g_ind++]))
7096                         count += ixgbe_read_regs_group(dev, &data[count],
7097                                                       reg_group);
7098                 return 0;
7099         }
7100
7101         return -ENOTSUP;
7102 }
7103
7104 static int
7105 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7106 {
7107         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7108
7109         /* Return unit is byte count */
7110         return hw->eeprom.word_size * 2;
7111 }
7112
7113 static int
7114 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7115                 struct rte_dev_eeprom_info *in_eeprom)
7116 {
7117         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7118         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7119         uint16_t *data = in_eeprom->data;
7120         int first, length;
7121
7122         first = in_eeprom->offset >> 1;
7123         length = in_eeprom->length >> 1;
7124         if ((first > hw->eeprom.word_size) ||
7125             ((first + length) > hw->eeprom.word_size))
7126                 return -EINVAL;
7127
7128         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7129
7130         return eeprom->ops.read_buffer(hw, first, length, data);
7131 }
7132
7133 static int
7134 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7135                 struct rte_dev_eeprom_info *in_eeprom)
7136 {
7137         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7138         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7139         uint16_t *data = in_eeprom->data;
7140         int first, length;
7141
7142         first = in_eeprom->offset >> 1;
7143         length = in_eeprom->length >> 1;
7144         if ((first > hw->eeprom.word_size) ||
7145             ((first + length) > hw->eeprom.word_size))
7146                 return -EINVAL;
7147
7148         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7149
7150         return eeprom->ops.write_buffer(hw,  first, length, data);
7151 }
7152
7153 uint16_t
7154 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7155         switch (mac_type) {
7156         case ixgbe_mac_X550:
7157         case ixgbe_mac_X550EM_x:
7158         case ixgbe_mac_X550EM_a:
7159                 return ETH_RSS_RETA_SIZE_512;
7160         case ixgbe_mac_X550_vf:
7161         case ixgbe_mac_X550EM_x_vf:
7162         case ixgbe_mac_X550EM_a_vf:
7163                 return ETH_RSS_RETA_SIZE_64;
7164         default:
7165                 return ETH_RSS_RETA_SIZE_128;
7166         }
7167 }
7168
7169 uint32_t
7170 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7171         switch (mac_type) {
7172         case ixgbe_mac_X550:
7173         case ixgbe_mac_X550EM_x:
7174         case ixgbe_mac_X550EM_a:
7175                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7176                         return IXGBE_RETA(reta_idx >> 2);
7177                 else
7178                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7179         case ixgbe_mac_X550_vf:
7180         case ixgbe_mac_X550EM_x_vf:
7181         case ixgbe_mac_X550EM_a_vf:
7182                 return IXGBE_VFRETA(reta_idx >> 2);
7183         default:
7184                 return IXGBE_RETA(reta_idx >> 2);
7185         }
7186 }
7187
7188 uint32_t
7189 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7190         switch (mac_type) {
7191         case ixgbe_mac_X550_vf:
7192         case ixgbe_mac_X550EM_x_vf:
7193         case ixgbe_mac_X550EM_a_vf:
7194                 return IXGBE_VFMRQC;
7195         default:
7196                 return IXGBE_MRQC;
7197         }
7198 }
7199
7200 uint32_t
7201 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7202         switch (mac_type) {
7203         case ixgbe_mac_X550_vf:
7204         case ixgbe_mac_X550EM_x_vf:
7205         case ixgbe_mac_X550EM_a_vf:
7206                 return IXGBE_VFRSSRK(i);
7207         default:
7208                 return IXGBE_RSSRK(i);
7209         }
7210 }
7211
7212 bool
7213 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7214         switch (mac_type) {
7215         case ixgbe_mac_82599_vf:
7216         case ixgbe_mac_X540_vf:
7217                 return 0;
7218         default:
7219                 return 1;
7220         }
7221 }
7222
7223 static int
7224 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7225                         struct rte_eth_dcb_info *dcb_info)
7226 {
7227         struct ixgbe_dcb_config *dcb_config =
7228                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7229         struct ixgbe_dcb_tc_config *tc;
7230         uint8_t i, j;
7231
7232         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7233                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7234         else
7235                 dcb_info->nb_tcs = 1;
7236
7237         if (dcb_config->vt_mode) { /* vt is enabled*/
7238                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7239                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7240                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7241                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7242                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7243                         for (j = 0; j < dcb_info->nb_tcs; j++) {
7244                                 dcb_info->tc_queue.tc_rxq[i][j].base =
7245                                                 i * dcb_info->nb_tcs + j;
7246                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7247                                 dcb_info->tc_queue.tc_txq[i][j].base =
7248                                                 i * dcb_info->nb_tcs + j;
7249                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7250                         }
7251                 }
7252         } else { /* vt is disabled*/
7253                 struct rte_eth_dcb_rx_conf *rx_conf =
7254                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7255                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7256                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7257                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7258                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7259                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7260                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7261                         }
7262                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7263                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7264                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7265                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7266                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7267                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7268                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7269                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7270                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7271                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7272                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7273                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7274                         }
7275                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7276                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7277                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7278                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7279                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7280                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7281                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7282                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7283                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7284                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7285                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7286                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7287                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7288                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7289                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7290                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7291                 }
7292         }
7293         for (i = 0; i < dcb_info->nb_tcs; i++) {
7294                 tc = &dcb_config->tc_config[i];
7295                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7296         }
7297         return 0;
7298 }
7299
7300 /* Update e-tag ether type */
7301 static int
7302 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7303                             uint16_t ether_type)
7304 {
7305         uint32_t etag_etype;
7306
7307         if (hw->mac.type != ixgbe_mac_X550 &&
7308             hw->mac.type != ixgbe_mac_X550EM_x &&
7309             hw->mac.type != ixgbe_mac_X550EM_a) {
7310                 return -ENOTSUP;
7311         }
7312
7313         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7314         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7315         etag_etype |= ether_type;
7316         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7317         IXGBE_WRITE_FLUSH(hw);
7318
7319         return 0;
7320 }
7321
7322 /* Config l2 tunnel ether type */
7323 static int
7324 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7325                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7326 {
7327         int ret = 0;
7328         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7329         struct ixgbe_l2_tn_info *l2_tn_info =
7330                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7331
7332         if (l2_tunnel == NULL)
7333                 return -EINVAL;
7334
7335         switch (l2_tunnel->l2_tunnel_type) {
7336         case RTE_L2_TUNNEL_TYPE_E_TAG:
7337                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7338                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7339                 break;
7340         default:
7341                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7342                 ret = -EINVAL;
7343                 break;
7344         }
7345
7346         return ret;
7347 }
7348
7349 /* Enable e-tag tunnel */
7350 static int
7351 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7352 {
7353         uint32_t etag_etype;
7354
7355         if (hw->mac.type != ixgbe_mac_X550 &&
7356             hw->mac.type != ixgbe_mac_X550EM_x &&
7357             hw->mac.type != ixgbe_mac_X550EM_a) {
7358                 return -ENOTSUP;
7359         }
7360
7361         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7362         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7363         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7364         IXGBE_WRITE_FLUSH(hw);
7365
7366         return 0;
7367 }
7368
7369 /* Enable l2 tunnel */
7370 static int
7371 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7372                            enum rte_eth_tunnel_type l2_tunnel_type)
7373 {
7374         int ret = 0;
7375         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7376         struct ixgbe_l2_tn_info *l2_tn_info =
7377                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7378
7379         switch (l2_tunnel_type) {
7380         case RTE_L2_TUNNEL_TYPE_E_TAG:
7381                 l2_tn_info->e_tag_en = TRUE;
7382                 ret = ixgbe_e_tag_enable(hw);
7383                 break;
7384         default:
7385                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7386                 ret = -EINVAL;
7387                 break;
7388         }
7389
7390         return ret;
7391 }
7392
7393 /* Disable e-tag tunnel */
7394 static int
7395 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7396 {
7397         uint32_t etag_etype;
7398
7399         if (hw->mac.type != ixgbe_mac_X550 &&
7400             hw->mac.type != ixgbe_mac_X550EM_x &&
7401             hw->mac.type != ixgbe_mac_X550EM_a) {
7402                 return -ENOTSUP;
7403         }
7404
7405         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7406         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7407         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7408         IXGBE_WRITE_FLUSH(hw);
7409
7410         return 0;
7411 }
7412
7413 /* Disable l2 tunnel */
7414 static int
7415 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7416                             enum rte_eth_tunnel_type l2_tunnel_type)
7417 {
7418         int ret = 0;
7419         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7420         struct ixgbe_l2_tn_info *l2_tn_info =
7421                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7422
7423         switch (l2_tunnel_type) {
7424         case RTE_L2_TUNNEL_TYPE_E_TAG:
7425                 l2_tn_info->e_tag_en = FALSE;
7426                 ret = ixgbe_e_tag_disable(hw);
7427                 break;
7428         default:
7429                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7430                 ret = -EINVAL;
7431                 break;
7432         }
7433
7434         return ret;
7435 }
7436
7437 static int
7438 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7439                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7440 {
7441         int ret = 0;
7442         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7443         uint32_t i, rar_entries;
7444         uint32_t rar_low, rar_high;
7445
7446         if (hw->mac.type != ixgbe_mac_X550 &&
7447             hw->mac.type != ixgbe_mac_X550EM_x &&
7448             hw->mac.type != ixgbe_mac_X550EM_a) {
7449                 return -ENOTSUP;
7450         }
7451
7452         rar_entries = ixgbe_get_num_rx_addrs(hw);
7453
7454         for (i = 1; i < rar_entries; i++) {
7455                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7456                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7457                 if ((rar_high & IXGBE_RAH_AV) &&
7458                     (rar_high & IXGBE_RAH_ADTYPE) &&
7459                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7460                      l2_tunnel->tunnel_id)) {
7461                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7462                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7463
7464                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7465
7466                         return ret;
7467                 }
7468         }
7469
7470         return ret;
7471 }
7472
7473 static int
7474 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7475                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7476 {
7477         int ret = 0;
7478         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7479         uint32_t i, rar_entries;
7480         uint32_t rar_low, rar_high;
7481
7482         if (hw->mac.type != ixgbe_mac_X550 &&
7483             hw->mac.type != ixgbe_mac_X550EM_x &&
7484             hw->mac.type != ixgbe_mac_X550EM_a) {
7485                 return -ENOTSUP;
7486         }
7487
7488         /* One entry for one tunnel. Try to remove potential existing entry. */
7489         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7490
7491         rar_entries = ixgbe_get_num_rx_addrs(hw);
7492
7493         for (i = 1; i < rar_entries; i++) {
7494                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7495                 if (rar_high & IXGBE_RAH_AV) {
7496                         continue;
7497                 } else {
7498                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7499                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7500                         rar_low = l2_tunnel->tunnel_id;
7501
7502                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7503                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7504
7505                         return ret;
7506                 }
7507         }
7508
7509         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7510                      " Please remove a rule before adding a new one.");
7511         return -EINVAL;
7512 }
7513
7514 static inline struct ixgbe_l2_tn_filter *
7515 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7516                           struct ixgbe_l2_tn_key *key)
7517 {
7518         int ret;
7519
7520         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7521         if (ret < 0)
7522                 return NULL;
7523
7524         return l2_tn_info->hash_map[ret];
7525 }
7526
7527 static inline int
7528 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7529                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7530 {
7531         int ret;
7532
7533         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7534                                &l2_tn_filter->key);
7535
7536         if (ret < 0) {
7537                 PMD_DRV_LOG(ERR,
7538                             "Failed to insert L2 tunnel filter"
7539                             " to hash table %d!",
7540                             ret);
7541                 return ret;
7542         }
7543
7544         l2_tn_info->hash_map[ret] = l2_tn_filter;
7545
7546         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7547
7548         return 0;
7549 }
7550
7551 static inline int
7552 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7553                           struct ixgbe_l2_tn_key *key)
7554 {
7555         int ret;
7556         struct ixgbe_l2_tn_filter *l2_tn_filter;
7557
7558         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7559
7560         if (ret < 0) {
7561                 PMD_DRV_LOG(ERR,
7562                             "No such L2 tunnel filter to delete %d!",
7563                             ret);
7564                 return ret;
7565         }
7566
7567         l2_tn_filter = l2_tn_info->hash_map[ret];
7568         l2_tn_info->hash_map[ret] = NULL;
7569
7570         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7571         rte_free(l2_tn_filter);
7572
7573         return 0;
7574 }
7575
7576 /* Add l2 tunnel filter */
7577 int
7578 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7579                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7580                                bool restore)
7581 {
7582         int ret;
7583         struct ixgbe_l2_tn_info *l2_tn_info =
7584                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7585         struct ixgbe_l2_tn_key key;
7586         struct ixgbe_l2_tn_filter *node;
7587
7588         if (!restore) {
7589                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7590                 key.tn_id = l2_tunnel->tunnel_id;
7591
7592                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7593
7594                 if (node) {
7595                         PMD_DRV_LOG(ERR,
7596                                     "The L2 tunnel filter already exists!");
7597                         return -EINVAL;
7598                 }
7599
7600                 node = rte_zmalloc("ixgbe_l2_tn",
7601                                    sizeof(struct ixgbe_l2_tn_filter),
7602                                    0);
7603                 if (!node)
7604                         return -ENOMEM;
7605
7606                 rte_memcpy(&node->key,
7607                                  &key,
7608                                  sizeof(struct ixgbe_l2_tn_key));
7609                 node->pool = l2_tunnel->pool;
7610                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7611                 if (ret < 0) {
7612                         rte_free(node);
7613                         return ret;
7614                 }
7615         }
7616
7617         switch (l2_tunnel->l2_tunnel_type) {
7618         case RTE_L2_TUNNEL_TYPE_E_TAG:
7619                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7620                 break;
7621         default:
7622                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7623                 ret = -EINVAL;
7624                 break;
7625         }
7626
7627         if ((!restore) && (ret < 0))
7628                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7629
7630         return ret;
7631 }
7632
7633 /* Delete l2 tunnel filter */
7634 int
7635 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7636                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7637 {
7638         int ret;
7639         struct ixgbe_l2_tn_info *l2_tn_info =
7640                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7641         struct ixgbe_l2_tn_key key;
7642
7643         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7644         key.tn_id = l2_tunnel->tunnel_id;
7645         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7646         if (ret < 0)
7647                 return ret;
7648
7649         switch (l2_tunnel->l2_tunnel_type) {
7650         case RTE_L2_TUNNEL_TYPE_E_TAG:
7651                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7652                 break;
7653         default:
7654                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7655                 ret = -EINVAL;
7656                 break;
7657         }
7658
7659         return ret;
7660 }
7661
7662 /**
7663  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7664  * @dev: pointer to rte_eth_dev structure
7665  * @filter_op:operation will be taken.
7666  * @arg: a pointer to specific structure corresponding to the filter_op
7667  */
7668 static int
7669 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7670                                   enum rte_filter_op filter_op,
7671                                   void *arg)
7672 {
7673         int ret;
7674
7675         if (filter_op == RTE_ETH_FILTER_NOP)
7676                 return 0;
7677
7678         if (arg == NULL) {
7679                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7680                             filter_op);
7681                 return -EINVAL;
7682         }
7683
7684         switch (filter_op) {
7685         case RTE_ETH_FILTER_ADD:
7686                 ret = ixgbe_dev_l2_tunnel_filter_add
7687                         (dev,
7688                          (struct rte_eth_l2_tunnel_conf *)arg,
7689                          FALSE);
7690                 break;
7691         case RTE_ETH_FILTER_DELETE:
7692                 ret = ixgbe_dev_l2_tunnel_filter_del
7693                         (dev,
7694                          (struct rte_eth_l2_tunnel_conf *)arg);
7695                 break;
7696         default:
7697                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7698                 ret = -EINVAL;
7699                 break;
7700         }
7701         return ret;
7702 }
7703
7704 static int
7705 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7706 {
7707         int ret = 0;
7708         uint32_t ctrl;
7709         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7710
7711         if (hw->mac.type != ixgbe_mac_X550 &&
7712             hw->mac.type != ixgbe_mac_X550EM_x &&
7713             hw->mac.type != ixgbe_mac_X550EM_a) {
7714                 return -ENOTSUP;
7715         }
7716
7717         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7718         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7719         if (en)
7720                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7721         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7722
7723         return ret;
7724 }
7725
7726 /* Enable l2 tunnel forwarding */
7727 static int
7728 ixgbe_dev_l2_tunnel_forwarding_enable
7729         (struct rte_eth_dev *dev,
7730          enum rte_eth_tunnel_type l2_tunnel_type)
7731 {
7732         struct ixgbe_l2_tn_info *l2_tn_info =
7733                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7734         int ret = 0;
7735
7736         switch (l2_tunnel_type) {
7737         case RTE_L2_TUNNEL_TYPE_E_TAG:
7738                 l2_tn_info->e_tag_fwd_en = TRUE;
7739                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7740                 break;
7741         default:
7742                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7743                 ret = -EINVAL;
7744                 break;
7745         }
7746
7747         return ret;
7748 }
7749
7750 /* Disable l2 tunnel forwarding */
7751 static int
7752 ixgbe_dev_l2_tunnel_forwarding_disable
7753         (struct rte_eth_dev *dev,
7754          enum rte_eth_tunnel_type l2_tunnel_type)
7755 {
7756         struct ixgbe_l2_tn_info *l2_tn_info =
7757                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7758         int ret = 0;
7759
7760         switch (l2_tunnel_type) {
7761         case RTE_L2_TUNNEL_TYPE_E_TAG:
7762                 l2_tn_info->e_tag_fwd_en = FALSE;
7763                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7764                 break;
7765         default:
7766                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7767                 ret = -EINVAL;
7768                 break;
7769         }
7770
7771         return ret;
7772 }
7773
7774 static int
7775 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7776                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7777                              bool en)
7778 {
7779         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7780         int ret = 0;
7781         uint32_t vmtir, vmvir;
7782         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7783
7784         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7785                 PMD_DRV_LOG(ERR,
7786                             "VF id %u should be less than %u",
7787                             l2_tunnel->vf_id,
7788                             pci_dev->max_vfs);
7789                 return -EINVAL;
7790         }
7791
7792         if (hw->mac.type != ixgbe_mac_X550 &&
7793             hw->mac.type != ixgbe_mac_X550EM_x &&
7794             hw->mac.type != ixgbe_mac_X550EM_a) {
7795                 return -ENOTSUP;
7796         }
7797
7798         if (en)
7799                 vmtir = l2_tunnel->tunnel_id;
7800         else
7801                 vmtir = 0;
7802
7803         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7804
7805         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7806         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7807         if (en)
7808                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7809         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7810
7811         return ret;
7812 }
7813
7814 /* Enable l2 tunnel tag insertion */
7815 static int
7816 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7817                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7818 {
7819         int ret = 0;
7820
7821         switch (l2_tunnel->l2_tunnel_type) {
7822         case RTE_L2_TUNNEL_TYPE_E_TAG:
7823                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7824                 break;
7825         default:
7826                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7827                 ret = -EINVAL;
7828                 break;
7829         }
7830
7831         return ret;
7832 }
7833
7834 /* Disable l2 tunnel tag insertion */
7835 static int
7836 ixgbe_dev_l2_tunnel_insertion_disable
7837         (struct rte_eth_dev *dev,
7838          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7839 {
7840         int ret = 0;
7841
7842         switch (l2_tunnel->l2_tunnel_type) {
7843         case RTE_L2_TUNNEL_TYPE_E_TAG:
7844                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7845                 break;
7846         default:
7847                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7848                 ret = -EINVAL;
7849                 break;
7850         }
7851
7852         return ret;
7853 }
7854
7855 static int
7856 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7857                              bool en)
7858 {
7859         int ret = 0;
7860         uint32_t qde;
7861         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7862
7863         if (hw->mac.type != ixgbe_mac_X550 &&
7864             hw->mac.type != ixgbe_mac_X550EM_x &&
7865             hw->mac.type != ixgbe_mac_X550EM_a) {
7866                 return -ENOTSUP;
7867         }
7868
7869         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7870         if (en)
7871                 qde |= IXGBE_QDE_STRIP_TAG;
7872         else
7873                 qde &= ~IXGBE_QDE_STRIP_TAG;
7874         qde &= ~IXGBE_QDE_READ;
7875         qde |= IXGBE_QDE_WRITE;
7876         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7877
7878         return ret;
7879 }
7880
7881 /* Enable l2 tunnel tag stripping */
7882 static int
7883 ixgbe_dev_l2_tunnel_stripping_enable
7884         (struct rte_eth_dev *dev,
7885          enum rte_eth_tunnel_type l2_tunnel_type)
7886 {
7887         int ret = 0;
7888
7889         switch (l2_tunnel_type) {
7890         case RTE_L2_TUNNEL_TYPE_E_TAG:
7891                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7892                 break;
7893         default:
7894                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7895                 ret = -EINVAL;
7896                 break;
7897         }
7898
7899         return ret;
7900 }
7901
7902 /* Disable l2 tunnel tag stripping */
7903 static int
7904 ixgbe_dev_l2_tunnel_stripping_disable
7905         (struct rte_eth_dev *dev,
7906          enum rte_eth_tunnel_type l2_tunnel_type)
7907 {
7908         int ret = 0;
7909
7910         switch (l2_tunnel_type) {
7911         case RTE_L2_TUNNEL_TYPE_E_TAG:
7912                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7913                 break;
7914         default:
7915                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7916                 ret = -EINVAL;
7917                 break;
7918         }
7919
7920         return ret;
7921 }
7922
7923 /* Enable/disable l2 tunnel offload functions */
7924 static int
7925 ixgbe_dev_l2_tunnel_offload_set
7926         (struct rte_eth_dev *dev,
7927          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7928          uint32_t mask,
7929          uint8_t en)
7930 {
7931         int ret = 0;
7932
7933         if (l2_tunnel == NULL)
7934                 return -EINVAL;
7935
7936         ret = -EINVAL;
7937         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7938                 if (en)
7939                         ret = ixgbe_dev_l2_tunnel_enable(
7940                                 dev,
7941                                 l2_tunnel->l2_tunnel_type);
7942                 else
7943                         ret = ixgbe_dev_l2_tunnel_disable(
7944                                 dev,
7945                                 l2_tunnel->l2_tunnel_type);
7946         }
7947
7948         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7949                 if (en)
7950                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7951                                 dev,
7952                                 l2_tunnel);
7953                 else
7954                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7955                                 dev,
7956                                 l2_tunnel);
7957         }
7958
7959         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7960                 if (en)
7961                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7962                                 dev,
7963                                 l2_tunnel->l2_tunnel_type);
7964                 else
7965                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7966                                 dev,
7967                                 l2_tunnel->l2_tunnel_type);
7968         }
7969
7970         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7971                 if (en)
7972                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7973                                 dev,
7974                                 l2_tunnel->l2_tunnel_type);
7975                 else
7976                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7977                                 dev,
7978                                 l2_tunnel->l2_tunnel_type);
7979         }
7980
7981         return ret;
7982 }
7983
7984 static int
7985 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7986                         uint16_t port)
7987 {
7988         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7989         IXGBE_WRITE_FLUSH(hw);
7990
7991         return 0;
7992 }
7993
7994 /* There's only one register for VxLAN UDP port.
7995  * So, we cannot add several ports. Will update it.
7996  */
7997 static int
7998 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7999                      uint16_t port)
8000 {
8001         if (port == 0) {
8002                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8003                 return -EINVAL;
8004         }
8005
8006         return ixgbe_update_vxlan_port(hw, port);
8007 }
8008
8009 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8010  * UDP port, it must have a value.
8011  * So, will reset it to the original value 0.
8012  */
8013 static int
8014 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8015                      uint16_t port)
8016 {
8017         uint16_t cur_port;
8018
8019         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8020
8021         if (cur_port != port) {
8022                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8023                 return -EINVAL;
8024         }
8025
8026         return ixgbe_update_vxlan_port(hw, 0);
8027 }
8028
8029 /* Add UDP tunneling port */
8030 static int
8031 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8032                               struct rte_eth_udp_tunnel *udp_tunnel)
8033 {
8034         int ret = 0;
8035         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8036
8037         if (hw->mac.type != ixgbe_mac_X550 &&
8038             hw->mac.type != ixgbe_mac_X550EM_x &&
8039             hw->mac.type != ixgbe_mac_X550EM_a) {
8040                 return -ENOTSUP;
8041         }
8042
8043         if (udp_tunnel == NULL)
8044                 return -EINVAL;
8045
8046         switch (udp_tunnel->prot_type) {
8047         case RTE_TUNNEL_TYPE_VXLAN:
8048                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8049                 break;
8050
8051         case RTE_TUNNEL_TYPE_GENEVE:
8052         case RTE_TUNNEL_TYPE_TEREDO:
8053                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8054                 ret = -EINVAL;
8055                 break;
8056
8057         default:
8058                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8059                 ret = -EINVAL;
8060                 break;
8061         }
8062
8063         return ret;
8064 }
8065
8066 /* Remove UDP tunneling port */
8067 static int
8068 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8069                               struct rte_eth_udp_tunnel *udp_tunnel)
8070 {
8071         int ret = 0;
8072         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8073
8074         if (hw->mac.type != ixgbe_mac_X550 &&
8075             hw->mac.type != ixgbe_mac_X550EM_x &&
8076             hw->mac.type != ixgbe_mac_X550EM_a) {
8077                 return -ENOTSUP;
8078         }
8079
8080         if (udp_tunnel == NULL)
8081                 return -EINVAL;
8082
8083         switch (udp_tunnel->prot_type) {
8084         case RTE_TUNNEL_TYPE_VXLAN:
8085                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8086                 break;
8087         case RTE_TUNNEL_TYPE_GENEVE:
8088         case RTE_TUNNEL_TYPE_TEREDO:
8089                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8090                 ret = -EINVAL;
8091                 break;
8092         default:
8093                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8094                 ret = -EINVAL;
8095                 break;
8096         }
8097
8098         return ret;
8099 }
8100
8101 static void
8102 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8103 {
8104         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8105
8106         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8107 }
8108
8109 static void
8110 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8111 {
8112         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8113
8114         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8115 }
8116
8117 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8118 {
8119         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8120         u32 in_msg = 0;
8121
8122         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8123                 return;
8124
8125         /* PF reset VF event */
8126         if (in_msg == IXGBE_PF_CONTROL_MSG)
8127                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8128                                               NULL, NULL);
8129 }
8130
8131 static int
8132 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8133 {
8134         uint32_t eicr;
8135         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8136         struct ixgbe_interrupt *intr =
8137                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8138         ixgbevf_intr_disable(hw);
8139
8140         /* read-on-clear nic registers here */
8141         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8142         intr->flags = 0;
8143
8144         /* only one misc vector supported - mailbox */
8145         eicr &= IXGBE_VTEICR_MASK;
8146         if (eicr == IXGBE_MISC_VEC_ID)
8147                 intr->flags |= IXGBE_FLAG_MAILBOX;
8148
8149         return 0;
8150 }
8151
8152 static int
8153 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8154 {
8155         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8156         struct ixgbe_interrupt *intr =
8157                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8158
8159         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8160                 ixgbevf_mbx_process(dev);
8161                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8162         }
8163
8164         ixgbevf_intr_enable(hw);
8165
8166         return 0;
8167 }
8168
8169 static void
8170 ixgbevf_dev_interrupt_handler(void *param)
8171 {
8172         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8173
8174         ixgbevf_dev_interrupt_get_status(dev);
8175         ixgbevf_dev_interrupt_action(dev);
8176 }
8177
8178 /**
8179  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8180  *  @hw: pointer to hardware structure
8181  *
8182  *  Stops the transmit data path and waits for the HW to internally empty
8183  *  the Tx security block
8184  **/
8185 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8186 {
8187 #define IXGBE_MAX_SECTX_POLL 40
8188
8189         int i;
8190         int sectxreg;
8191
8192         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8193         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8194         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8195         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8196                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8197                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8198                         break;
8199                 /* Use interrupt-safe sleep just in case */
8200                 usec_delay(1000);
8201         }
8202
8203         /* For informational purposes only */
8204         if (i >= IXGBE_MAX_SECTX_POLL)
8205                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8206                          "path fully disabled.  Continuing with init.");
8207
8208         return IXGBE_SUCCESS;
8209 }
8210
8211 /**
8212  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8213  *  @hw: pointer to hardware structure
8214  *
8215  *  Enables the transmit data path.
8216  **/
8217 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8218 {
8219         uint32_t sectxreg;
8220
8221         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8222         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8223         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8224         IXGBE_WRITE_FLUSH(hw);
8225
8226         return IXGBE_SUCCESS;
8227 }
8228
8229 /* restore n-tuple filter */
8230 static inline void
8231 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8232 {
8233         struct ixgbe_filter_info *filter_info =
8234                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8235         struct ixgbe_5tuple_filter *node;
8236
8237         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8238                 ixgbe_inject_5tuple_filter(dev, node);
8239         }
8240 }
8241
8242 /* restore ethernet type filter */
8243 static inline void
8244 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8245 {
8246         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8247         struct ixgbe_filter_info *filter_info =
8248                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8249         int i;
8250
8251         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8252                 if (filter_info->ethertype_mask & (1 << i)) {
8253                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8254                                         filter_info->ethertype_filters[i].etqf);
8255                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8256                                         filter_info->ethertype_filters[i].etqs);
8257                         IXGBE_WRITE_FLUSH(hw);
8258                 }
8259         }
8260 }
8261
8262 /* restore SYN filter */
8263 static inline void
8264 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8265 {
8266         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8267         struct ixgbe_filter_info *filter_info =
8268                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8269         uint32_t synqf;
8270
8271         synqf = filter_info->syn_info;
8272
8273         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8274                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8275                 IXGBE_WRITE_FLUSH(hw);
8276         }
8277 }
8278
8279 /* restore L2 tunnel filter */
8280 static inline void
8281 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8282 {
8283         struct ixgbe_l2_tn_info *l2_tn_info =
8284                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8285         struct ixgbe_l2_tn_filter *node;
8286         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8287
8288         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8289                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8290                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8291                 l2_tn_conf.pool           = node->pool;
8292                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8293         }
8294 }
8295
8296 static int
8297 ixgbe_filter_restore(struct rte_eth_dev *dev)
8298 {
8299         ixgbe_ntuple_filter_restore(dev);
8300         ixgbe_ethertype_filter_restore(dev);
8301         ixgbe_syn_filter_restore(dev);
8302         ixgbe_fdir_filter_restore(dev);
8303         ixgbe_l2_tn_filter_restore(dev);
8304
8305         return 0;
8306 }
8307
8308 static void
8309 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8310 {
8311         struct ixgbe_l2_tn_info *l2_tn_info =
8312                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8313         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8314
8315         if (l2_tn_info->e_tag_en)
8316                 (void)ixgbe_e_tag_enable(hw);
8317
8318         if (l2_tn_info->e_tag_fwd_en)
8319                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8320
8321         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8322 }
8323
8324 /* remove all the n-tuple filters */
8325 void
8326 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8327 {
8328         struct ixgbe_filter_info *filter_info =
8329                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8330         struct ixgbe_5tuple_filter *p_5tuple;
8331
8332         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8333                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8334 }
8335
8336 /* remove all the ether type filters */
8337 void
8338 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8339 {
8340         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8341         struct ixgbe_filter_info *filter_info =
8342                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8343         int i;
8344
8345         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8346                 if (filter_info->ethertype_mask & (1 << i) &&
8347                     !filter_info->ethertype_filters[i].conf) {
8348                         (void)ixgbe_ethertype_filter_remove(filter_info,
8349                                                             (uint8_t)i);
8350                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8351                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8352                         IXGBE_WRITE_FLUSH(hw);
8353                 }
8354         }
8355 }
8356
8357 /* remove the SYN filter */
8358 void
8359 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8360 {
8361         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8362         struct ixgbe_filter_info *filter_info =
8363                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8364
8365         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8366                 filter_info->syn_info = 0;
8367
8368                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8369                 IXGBE_WRITE_FLUSH(hw);
8370         }
8371 }
8372
8373 /* remove all the L2 tunnel filters */
8374 int
8375 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8376 {
8377         struct ixgbe_l2_tn_info *l2_tn_info =
8378                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8379         struct ixgbe_l2_tn_filter *l2_tn_filter;
8380         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8381         int ret = 0;
8382
8383         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8384                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8385                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8386                 l2_tn_conf.pool           = l2_tn_filter->pool;
8387                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8388                 if (ret < 0)
8389                         return ret;
8390         }
8391
8392         return 0;
8393 }
8394
8395 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8396 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8397 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8398 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8399 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8400 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");