4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_ethdev_pci.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
63 #include <rte_hash_crc.h>
65 #include "ixgbe_logs.h"
66 #include "base/ixgbe_api.h"
67 #include "base/ixgbe_vf.h"
68 #include "base/ixgbe_common.h"
69 #include "ixgbe_ethdev.h"
70 #include "ixgbe_bypass.h"
71 #include "ixgbe_rxtx.h"
72 #include "base/ixgbe_type.h"
73 #include "base/ixgbe_phy.h"
74 #include "ixgbe_regs.h"
77 * High threshold controlling when to start sending XOFF frames. Must be at
78 * least 8 bytes less than receive packet buffer size. This value is in units
81 #define IXGBE_FC_HI 0x80
84 * Low threshold controlling when to start sending XON frames. This value is
85 * in units of 1024 bytes.
87 #define IXGBE_FC_LO 0x40
89 /* Default minimum inter-interrupt interval for EITR configuration */
90 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
92 /* Timer value included in XOFF frames. */
93 #define IXGBE_FC_PAUSE 0x680
95 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
96 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
97 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
99 #define IXGBE_MMW_SIZE_DEFAULT 0x4
100 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
101 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
104 * Default values for RX/TX configuration
106 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
107 #define IXGBE_DEFAULT_RX_PTHRESH 8
108 #define IXGBE_DEFAULT_RX_HTHRESH 8
109 #define IXGBE_DEFAULT_RX_WTHRESH 0
111 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
112 #define IXGBE_DEFAULT_TX_PTHRESH 32
113 #define IXGBE_DEFAULT_TX_HTHRESH 0
114 #define IXGBE_DEFAULT_TX_WTHRESH 0
115 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
117 /* Bit shift and mask */
118 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
119 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
120 #define IXGBE_8_BIT_WIDTH CHAR_BIT
121 #define IXGBE_8_BIT_MASK UINT8_MAX
123 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
125 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
127 #define IXGBE_HKEY_MAX_INDEX 10
129 /* Additional timesync values. */
130 #define NSEC_PER_SEC 1000000000L
131 #define IXGBE_INCVAL_10GB 0x66666666
132 #define IXGBE_INCVAL_1GB 0x40000000
133 #define IXGBE_INCVAL_100 0x50000000
134 #define IXGBE_INCVAL_SHIFT_10GB 28
135 #define IXGBE_INCVAL_SHIFT_1GB 24
136 #define IXGBE_INCVAL_SHIFT_100 21
137 #define IXGBE_INCVAL_SHIFT_82599 7
138 #define IXGBE_INCPER_SHIFT_82599 24
140 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
142 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
143 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
144 #define DEFAULT_ETAG_ETYPE 0x893f
145 #define IXGBE_ETAG_ETYPE 0x00005084
146 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
147 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
148 #define IXGBE_RAH_ADTYPE 0x40000000
149 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
150 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
151 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
152 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
153 #define IXGBE_QDE_STRIP_TAG 0x00000004
154 #define IXGBE_VTEICR_MASK 0x07
156 #define IXGBE_EXVET_VET_EXT_SHIFT 16
157 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
159 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
160 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
161 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
162 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
163 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
164 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
165 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
166 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
167 static int ixgbe_dev_start(struct rte_eth_dev *dev);
168 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
169 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
170 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
171 static void ixgbe_dev_close(struct rte_eth_dev *dev);
172 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
173 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
174 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
175 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
176 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
177 int wait_to_complete);
178 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
179 struct rte_eth_stats *stats);
180 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
181 struct rte_eth_xstat *xstats, unsigned n);
182 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
183 struct rte_eth_xstat *xstats, unsigned n);
185 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
186 uint64_t *values, unsigned int n);
187 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
188 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
189 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
190 struct rte_eth_xstat_name *xstats_names,
192 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
193 struct rte_eth_xstat_name *xstats_names, unsigned limit);
194 static int ixgbe_dev_xstats_get_names_by_id(
195 struct rte_eth_dev *dev,
196 struct rte_eth_xstat_name *xstats_names,
199 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
203 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
205 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
206 struct rte_eth_dev_info *dev_info);
207 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
208 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
209 struct rte_eth_dev_info *dev_info);
210 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
212 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
213 uint16_t vlan_id, int on);
214 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
215 enum rte_vlan_type vlan_type,
217 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
218 uint16_t queue, bool on);
219 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
221 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
222 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
223 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
224 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
225 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
227 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
228 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
229 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
230 struct rte_eth_fc_conf *fc_conf);
231 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
232 struct rte_eth_fc_conf *fc_conf);
233 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
234 struct rte_eth_pfc_conf *pfc_conf);
235 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
236 struct rte_eth_rss_reta_entry64 *reta_conf,
238 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
239 struct rte_eth_rss_reta_entry64 *reta_conf,
241 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
242 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
243 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
244 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
245 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
246 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
247 struct rte_intr_handle *handle);
248 static void ixgbe_dev_interrupt_handler(void *param);
249 static void ixgbe_dev_interrupt_delayed_handler(void *param);
250 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
251 uint32_t index, uint32_t pool);
252 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
253 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
254 struct ether_addr *mac_addr);
255 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
256 static bool is_device_supported(struct rte_eth_dev *dev,
257 struct rte_pci_driver *drv);
259 /* For Virtual Function support */
260 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
261 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
262 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
263 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
264 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
265 int wait_to_complete);
266 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
267 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
268 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
269 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
270 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
271 struct rte_eth_stats *stats);
272 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
273 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
274 uint16_t vlan_id, int on);
275 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
276 uint16_t queue, int on);
277 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
278 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
279 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
281 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
283 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
284 uint8_t queue, uint8_t msix_vector);
285 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
286 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
287 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
289 /* For Eth VMDQ APIs support */
290 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
291 ether_addr * mac_addr, uint8_t on);
292 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
293 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
294 struct rte_eth_mirror_conf *mirror_conf,
295 uint8_t rule_id, uint8_t on);
296 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
298 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
300 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
302 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
303 uint8_t queue, uint8_t msix_vector);
304 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
306 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
307 struct ether_addr *mac_addr,
308 uint32_t index, uint32_t pool);
309 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
310 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
311 struct ether_addr *mac_addr);
312 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
313 struct rte_eth_syn_filter *filter);
314 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
315 enum rte_filter_op filter_op,
317 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
318 struct ixgbe_5tuple_filter *filter);
319 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
320 struct ixgbe_5tuple_filter *filter);
321 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
322 enum rte_filter_op filter_op,
324 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
325 struct rte_eth_ntuple_filter *filter);
326 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
327 enum rte_filter_op filter_op,
329 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
330 struct rte_eth_ethertype_filter *filter);
331 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
332 enum rte_filter_type filter_type,
333 enum rte_filter_op filter_op,
335 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
337 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
338 struct ether_addr *mc_addr_set,
339 uint32_t nb_mc_addr);
340 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
341 struct rte_eth_dcb_info *dcb_info);
343 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
344 static int ixgbe_get_regs(struct rte_eth_dev *dev,
345 struct rte_dev_reg_info *regs);
346 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
347 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
348 struct rte_dev_eeprom_info *eeprom);
349 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
350 struct rte_dev_eeprom_info *eeprom);
352 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
353 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
354 struct rte_dev_reg_info *regs);
356 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
357 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
358 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
359 struct timespec *timestamp,
361 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
362 struct timespec *timestamp);
363 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
364 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
365 struct timespec *timestamp);
366 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
367 const struct timespec *timestamp);
368 static void ixgbevf_dev_interrupt_handler(void *param);
370 static int ixgbe_dev_l2_tunnel_eth_type_conf
371 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
372 static int ixgbe_dev_l2_tunnel_offload_set
373 (struct rte_eth_dev *dev,
374 struct rte_eth_l2_tunnel_conf *l2_tunnel,
377 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
378 enum rte_filter_op filter_op,
381 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
382 struct rte_eth_udp_tunnel *udp_tunnel);
383 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
384 struct rte_eth_udp_tunnel *udp_tunnel);
385 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
386 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
389 * Define VF Stats MACRO for Non "cleared on read" register
391 #define UPDATE_VF_STAT(reg, last, cur) \
393 uint32_t latest = IXGBE_READ_REG(hw, reg); \
394 cur += (latest - last) & UINT_MAX; \
398 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
400 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
401 u64 new_msb = IXGBE_READ_REG(hw, msb); \
402 u64 latest = ((new_msb << 32) | new_lsb); \
403 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
407 #define IXGBE_SET_HWSTRIP(h, q) do {\
408 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
409 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
410 (h)->bitmap[idx] |= 1 << bit;\
413 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
414 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
415 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
416 (h)->bitmap[idx] &= ~(1 << bit);\
419 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
420 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
421 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
422 (r) = (h)->bitmap[idx] >> bit & 1;\
426 * The set of PCI devices this driver supports
428 static const struct rte_pci_id pci_id_ixgbe_map[] = {
429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
477 #ifdef RTE_LIBRTE_IXGBE_BYPASS
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
480 { .vendor_id = 0, /* sentinel */ },
484 * The set of PCI devices this driver supports (for 82599 VF)
486 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
487 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
488 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
489 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
490 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
491 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
492 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
493 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
494 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
495 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
496 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
497 { .vendor_id = 0, /* sentinel */ },
500 static const struct rte_eth_desc_lim rx_desc_lim = {
501 .nb_max = IXGBE_MAX_RING_DESC,
502 .nb_min = IXGBE_MIN_RING_DESC,
503 .nb_align = IXGBE_RXD_ALIGN,
506 static const struct rte_eth_desc_lim tx_desc_lim = {
507 .nb_max = IXGBE_MAX_RING_DESC,
508 .nb_min = IXGBE_MIN_RING_DESC,
509 .nb_align = IXGBE_TXD_ALIGN,
510 .nb_seg_max = IXGBE_TX_MAX_SEG,
511 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
514 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
515 .dev_configure = ixgbe_dev_configure,
516 .dev_start = ixgbe_dev_start,
517 .dev_stop = ixgbe_dev_stop,
518 .dev_set_link_up = ixgbe_dev_set_link_up,
519 .dev_set_link_down = ixgbe_dev_set_link_down,
520 .dev_close = ixgbe_dev_close,
521 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
522 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
523 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
524 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
525 .link_update = ixgbe_dev_link_update,
526 .stats_get = ixgbe_dev_stats_get,
527 .xstats_get = ixgbe_dev_xstats_get,
528 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
529 .stats_reset = ixgbe_dev_stats_reset,
530 .xstats_reset = ixgbe_dev_xstats_reset,
531 .xstats_get_names = ixgbe_dev_xstats_get_names,
532 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
533 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
534 .fw_version_get = ixgbe_fw_version_get,
535 .dev_infos_get = ixgbe_dev_info_get,
536 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
537 .mtu_set = ixgbe_dev_mtu_set,
538 .vlan_filter_set = ixgbe_vlan_filter_set,
539 .vlan_tpid_set = ixgbe_vlan_tpid_set,
540 .vlan_offload_set = ixgbe_vlan_offload_set,
541 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
542 .rx_queue_start = ixgbe_dev_rx_queue_start,
543 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
544 .tx_queue_start = ixgbe_dev_tx_queue_start,
545 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
546 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
547 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
548 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
549 .rx_queue_release = ixgbe_dev_rx_queue_release,
550 .rx_queue_count = ixgbe_dev_rx_queue_count,
551 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
552 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
553 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
554 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
555 .tx_queue_release = ixgbe_dev_tx_queue_release,
556 .dev_led_on = ixgbe_dev_led_on,
557 .dev_led_off = ixgbe_dev_led_off,
558 .flow_ctrl_get = ixgbe_flow_ctrl_get,
559 .flow_ctrl_set = ixgbe_flow_ctrl_set,
560 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
561 .mac_addr_add = ixgbe_add_rar,
562 .mac_addr_remove = ixgbe_remove_rar,
563 .mac_addr_set = ixgbe_set_default_mac_addr,
564 .uc_hash_table_set = ixgbe_uc_hash_table_set,
565 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
566 .mirror_rule_set = ixgbe_mirror_rule_set,
567 .mirror_rule_reset = ixgbe_mirror_rule_reset,
568 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
569 .reta_update = ixgbe_dev_rss_reta_update,
570 .reta_query = ixgbe_dev_rss_reta_query,
571 .rss_hash_update = ixgbe_dev_rss_hash_update,
572 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
573 .filter_ctrl = ixgbe_dev_filter_ctrl,
574 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
575 .rxq_info_get = ixgbe_rxq_info_get,
576 .txq_info_get = ixgbe_txq_info_get,
577 .timesync_enable = ixgbe_timesync_enable,
578 .timesync_disable = ixgbe_timesync_disable,
579 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
580 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
581 .get_reg = ixgbe_get_regs,
582 .get_eeprom_length = ixgbe_get_eeprom_length,
583 .get_eeprom = ixgbe_get_eeprom,
584 .set_eeprom = ixgbe_set_eeprom,
585 .get_dcb_info = ixgbe_dev_get_dcb_info,
586 .timesync_adjust_time = ixgbe_timesync_adjust_time,
587 .timesync_read_time = ixgbe_timesync_read_time,
588 .timesync_write_time = ixgbe_timesync_write_time,
589 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
590 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
591 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
592 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
593 .tm_ops_get = ixgbe_tm_ops_get,
597 * dev_ops for virtual function, bare necessities for basic vf
598 * operation have been implemented
600 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
601 .dev_configure = ixgbevf_dev_configure,
602 .dev_start = ixgbevf_dev_start,
603 .dev_stop = ixgbevf_dev_stop,
604 .link_update = ixgbevf_dev_link_update,
605 .stats_get = ixgbevf_dev_stats_get,
606 .xstats_get = ixgbevf_dev_xstats_get,
607 .stats_reset = ixgbevf_dev_stats_reset,
608 .xstats_reset = ixgbevf_dev_stats_reset,
609 .xstats_get_names = ixgbevf_dev_xstats_get_names,
610 .dev_close = ixgbevf_dev_close,
611 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
612 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
613 .dev_infos_get = ixgbevf_dev_info_get,
614 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
615 .mtu_set = ixgbevf_dev_set_mtu,
616 .vlan_filter_set = ixgbevf_vlan_filter_set,
617 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
618 .vlan_offload_set = ixgbevf_vlan_offload_set,
619 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
620 .rx_queue_release = ixgbe_dev_rx_queue_release,
621 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
622 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
623 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
624 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
625 .tx_queue_release = ixgbe_dev_tx_queue_release,
626 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
627 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
628 .mac_addr_add = ixgbevf_add_mac_addr,
629 .mac_addr_remove = ixgbevf_remove_mac_addr,
630 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
631 .rxq_info_get = ixgbe_rxq_info_get,
632 .txq_info_get = ixgbe_txq_info_get,
633 .mac_addr_set = ixgbevf_set_default_mac_addr,
634 .get_reg = ixgbevf_get_regs,
635 .reta_update = ixgbe_dev_rss_reta_update,
636 .reta_query = ixgbe_dev_rss_reta_query,
637 .rss_hash_update = ixgbe_dev_rss_hash_update,
638 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
641 /* store statistics names and its offset in stats structure */
642 struct rte_ixgbe_xstats_name_off {
643 char name[RTE_ETH_XSTATS_NAME_SIZE];
647 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
648 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
649 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
650 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
651 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
652 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
653 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
654 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
655 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
656 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
657 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
658 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
659 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
660 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
661 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
662 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
664 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
666 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
667 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
668 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
669 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
670 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
671 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
672 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
673 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
674 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
675 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
676 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
677 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
678 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
679 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
680 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
681 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
682 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
684 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
686 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
687 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
688 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
689 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
691 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
693 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
695 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
697 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
699 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
701 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
704 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
705 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
706 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
708 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
709 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
710 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
711 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
712 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
714 {"rx_fcoe_no_direct_data_placement_ext_buff",
715 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
717 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
719 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
721 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
723 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
725 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
728 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
729 sizeof(rte_ixgbe_stats_strings[0]))
731 /* MACsec statistics */
732 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
733 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
735 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
736 out_pkts_encrypted)},
737 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
738 out_pkts_protected)},
739 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
740 out_octets_encrypted)},
741 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
742 out_octets_protected)},
743 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
745 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
747 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
749 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
750 in_pkts_unknownsci)},
751 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
752 in_octets_decrypted)},
753 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
754 in_octets_validated)},
755 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
757 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
759 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
761 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
763 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
765 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
767 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
769 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
770 in_pkts_notusingsa)},
773 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
774 sizeof(rte_ixgbe_macsec_strings[0]))
776 /* Per-queue statistics */
777 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
778 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
779 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
780 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
781 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
784 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
785 sizeof(rte_ixgbe_rxq_strings[0]))
786 #define IXGBE_NB_RXQ_PRIO_VALUES 8
788 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
789 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
790 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
791 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
795 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
796 sizeof(rte_ixgbe_txq_strings[0]))
797 #define IXGBE_NB_TXQ_PRIO_VALUES 8
799 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
800 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
803 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
804 sizeof(rte_ixgbevf_stats_strings[0]))
807 * Atomically reads the link status information from global
808 * structure rte_eth_dev.
811 * - Pointer to the structure rte_eth_dev to read from.
812 * - Pointer to the buffer to be saved with the link status.
815 * - On success, zero.
816 * - On failure, negative value.
819 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
820 struct rte_eth_link *link)
822 struct rte_eth_link *dst = link;
823 struct rte_eth_link *src = &(dev->data->dev_link);
825 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
826 *(uint64_t *)src) == 0)
833 * Atomically writes the link status information into global
834 * structure rte_eth_dev.
837 * - Pointer to the structure rte_eth_dev to read from.
838 * - Pointer to the buffer to be saved with the link status.
841 * - On success, zero.
842 * - On failure, negative value.
845 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
846 struct rte_eth_link *link)
848 struct rte_eth_link *dst = &(dev->data->dev_link);
849 struct rte_eth_link *src = link;
851 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
852 *(uint64_t *)src) == 0)
859 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
862 ixgbe_is_sfp(struct ixgbe_hw *hw)
864 switch (hw->phy.type) {
865 case ixgbe_phy_sfp_avago:
866 case ixgbe_phy_sfp_ftl:
867 case ixgbe_phy_sfp_intel:
868 case ixgbe_phy_sfp_unknown:
869 case ixgbe_phy_sfp_passive_tyco:
870 case ixgbe_phy_sfp_passive_unknown:
877 static inline int32_t
878 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
883 status = ixgbe_reset_hw(hw);
885 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
886 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
887 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
888 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
889 IXGBE_WRITE_FLUSH(hw);
891 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
892 status = IXGBE_SUCCESS;
897 ixgbe_enable_intr(struct rte_eth_dev *dev)
899 struct ixgbe_interrupt *intr =
900 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
901 struct ixgbe_hw *hw =
902 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
904 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
905 IXGBE_WRITE_FLUSH(hw);
909 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
912 ixgbe_disable_intr(struct ixgbe_hw *hw)
914 PMD_INIT_FUNC_TRACE();
916 if (hw->mac.type == ixgbe_mac_82598EB) {
917 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
919 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
920 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
921 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
923 IXGBE_WRITE_FLUSH(hw);
927 * This function resets queue statistics mapping registers.
928 * From Niantic datasheet, Initialization of Statistics section:
929 * "...if software requires the queue counters, the RQSMR and TQSM registers
930 * must be re-programmed following a device reset.
933 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
937 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
938 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
939 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
945 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
950 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
951 #define NB_QMAP_FIELDS_PER_QSM_REG 4
952 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
954 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
955 struct ixgbe_stat_mapping_registers *stat_mappings =
956 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
957 uint32_t qsmr_mask = 0;
958 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
962 if ((hw->mac.type != ixgbe_mac_82599EB) &&
963 (hw->mac.type != ixgbe_mac_X540) &&
964 (hw->mac.type != ixgbe_mac_X550) &&
965 (hw->mac.type != ixgbe_mac_X550EM_x) &&
966 (hw->mac.type != ixgbe_mac_X550EM_a))
969 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
970 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
973 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
974 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
975 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
978 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
980 /* Now clear any previous stat_idx set */
981 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
983 stat_mappings->tqsm[n] &= ~clearing_mask;
985 stat_mappings->rqsmr[n] &= ~clearing_mask;
987 q_map = (uint32_t)stat_idx;
988 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
989 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
991 stat_mappings->tqsm[n] |= qsmr_mask;
993 stat_mappings->rqsmr[n] |= qsmr_mask;
995 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
996 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
998 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
999 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1001 /* Now write the mapping in the appropriate register */
1003 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1004 stat_mappings->rqsmr[n], n);
1005 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1007 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1008 stat_mappings->tqsm[n], n);
1009 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1015 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1017 struct ixgbe_stat_mapping_registers *stat_mappings =
1018 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1019 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1022 /* write whatever was in stat mapping table to the NIC */
1023 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1025 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1028 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1033 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1036 struct ixgbe_dcb_tc_config *tc;
1037 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1039 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1040 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1041 for (i = 0; i < dcb_max_tc; i++) {
1042 tc = &dcb_config->tc_config[i];
1043 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1044 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1045 (uint8_t)(100/dcb_max_tc + (i & 1));
1046 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1047 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1048 (uint8_t)(100/dcb_max_tc + (i & 1));
1049 tc->pfc = ixgbe_dcb_pfc_disabled;
1052 /* Initialize default user to priority mapping, UPx->TC0 */
1053 tc = &dcb_config->tc_config[0];
1054 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1055 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1056 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1057 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1058 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1060 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1061 dcb_config->pfc_mode_enable = false;
1062 dcb_config->vt_mode = true;
1063 dcb_config->round_robin_enable = false;
1064 /* support all DCB capabilities in 82599 */
1065 dcb_config->support.capabilities = 0xFF;
1067 /*we only support 4 Tcs for X540, X550 */
1068 if (hw->mac.type == ixgbe_mac_X540 ||
1069 hw->mac.type == ixgbe_mac_X550 ||
1070 hw->mac.type == ixgbe_mac_X550EM_x ||
1071 hw->mac.type == ixgbe_mac_X550EM_a) {
1072 dcb_config->num_tcs.pg_tcs = 4;
1073 dcb_config->num_tcs.pfc_tcs = 4;
1078 * Ensure that all locks are released before first NVM or PHY access
1081 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1086 * Phy lock should not fail in this early stage. If this is the case,
1087 * it is due to an improper exit of the application.
1088 * So force the release of the faulty lock. Release of common lock
1089 * is done automatically by swfw_sync function.
1091 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1092 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1093 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1095 ixgbe_release_swfw_semaphore(hw, mask);
1098 * These ones are more tricky since they are common to all ports; but
1099 * swfw_sync retries last long enough (1s) to be almost sure that if
1100 * lock can not be taken it is due to an improper lock of the
1103 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1104 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1105 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1107 ixgbe_release_swfw_semaphore(hw, mask);
1111 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1112 * It returns 0 on success.
1115 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1117 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1118 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1119 struct ixgbe_hw *hw =
1120 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1121 struct ixgbe_vfta *shadow_vfta =
1122 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1123 struct ixgbe_hwstrip *hwstrip =
1124 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1125 struct ixgbe_dcb_config *dcb_config =
1126 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1127 struct ixgbe_filter_info *filter_info =
1128 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1129 struct ixgbe_bw_conf *bw_conf =
1130 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1135 PMD_INIT_FUNC_TRACE();
1137 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1138 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1139 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1140 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1143 * For secondary processes, we don't initialise any further as primary
1144 * has already done this work. Only check we don't need a different
1145 * RX and TX function.
1147 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1148 struct ixgbe_tx_queue *txq;
1149 /* TX queue function in primary, set by last queue initialized
1150 * Tx queue may not initialized by primary process
1152 if (eth_dev->data->tx_queues) {
1153 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1154 ixgbe_set_tx_function(eth_dev, txq);
1156 /* Use default TX function if we get here */
1157 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1158 "Using default TX function.");
1161 ixgbe_set_rx_function(eth_dev);
1166 rte_eth_copy_pci_info(eth_dev, pci_dev);
1167 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1169 /* Vendor and Device ID need to be set before init of shared code */
1170 hw->device_id = pci_dev->id.device_id;
1171 hw->vendor_id = pci_dev->id.vendor_id;
1172 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1173 hw->allow_unsupported_sfp = 1;
1175 /* Initialize the shared code (base driver) */
1176 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1177 diag = ixgbe_bypass_init_shared_code(hw);
1179 diag = ixgbe_init_shared_code(hw);
1180 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1182 if (diag != IXGBE_SUCCESS) {
1183 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1187 /* pick up the PCI bus settings for reporting later */
1188 ixgbe_get_bus_info(hw);
1190 /* Unlock any pending hardware semaphore */
1191 ixgbe_swfw_lock_reset(hw);
1193 /* Initialize DCB configuration*/
1194 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1195 ixgbe_dcb_init(hw, dcb_config);
1196 /* Get Hardware Flow Control setting */
1197 hw->fc.requested_mode = ixgbe_fc_full;
1198 hw->fc.current_mode = ixgbe_fc_full;
1199 hw->fc.pause_time = IXGBE_FC_PAUSE;
1200 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1201 hw->fc.low_water[i] = IXGBE_FC_LO;
1202 hw->fc.high_water[i] = IXGBE_FC_HI;
1204 hw->fc.send_xon = 1;
1206 /* Make sure we have a good EEPROM before we read from it */
1207 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1208 if (diag != IXGBE_SUCCESS) {
1209 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1213 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1214 diag = ixgbe_bypass_init_hw(hw);
1216 diag = ixgbe_init_hw(hw);
1217 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1220 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1221 * is called too soon after the kernel driver unbinding/binding occurs.
1222 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1223 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1224 * also called. See ixgbe_identify_phy_82599(). The reason for the
1225 * failure is not known, and only occuts when virtualisation features
1226 * are disabled in the bios. A delay of 100ms was found to be enough by
1227 * trial-and-error, and is doubled to be safe.
1229 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1231 diag = ixgbe_init_hw(hw);
1234 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1235 diag = IXGBE_SUCCESS;
1237 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1238 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1239 "LOM. Please be aware there may be issues associated "
1240 "with your hardware.");
1241 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1242 "please contact your Intel or hardware representative "
1243 "who provided you with this hardware.");
1244 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1245 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1247 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1251 /* Reset the hw statistics */
1252 ixgbe_dev_stats_reset(eth_dev);
1254 /* disable interrupt */
1255 ixgbe_disable_intr(hw);
1257 /* reset mappings for queue statistics hw counters*/
1258 ixgbe_reset_qstat_mappings(hw);
1260 /* Allocate memory for storing MAC addresses */
1261 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1262 hw->mac.num_rar_entries, 0);
1263 if (eth_dev->data->mac_addrs == NULL) {
1265 "Failed to allocate %u bytes needed to store "
1267 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1270 /* Copy the permanent MAC address */
1271 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1272 ð_dev->data->mac_addrs[0]);
1274 /* Allocate memory for storing hash filter MAC addresses */
1275 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1276 IXGBE_VMDQ_NUM_UC_MAC, 0);
1277 if (eth_dev->data->hash_mac_addrs == NULL) {
1279 "Failed to allocate %d bytes needed to store MAC addresses",
1280 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1284 /* initialize the vfta */
1285 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1287 /* initialize the hw strip bitmap*/
1288 memset(hwstrip, 0, sizeof(*hwstrip));
1290 /* initialize PF if max_vfs not zero */
1291 ixgbe_pf_host_init(eth_dev);
1293 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1294 /* let hardware know driver is loaded */
1295 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1296 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1297 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1298 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1299 IXGBE_WRITE_FLUSH(hw);
1301 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1302 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1303 (int) hw->mac.type, (int) hw->phy.type,
1304 (int) hw->phy.sfp_type);
1306 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1307 (int) hw->mac.type, (int) hw->phy.type);
1309 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1310 eth_dev->data->port_id, pci_dev->id.vendor_id,
1311 pci_dev->id.device_id);
1313 rte_intr_callback_register(intr_handle,
1314 ixgbe_dev_interrupt_handler, eth_dev);
1316 /* enable uio/vfio intr/eventfd mapping */
1317 rte_intr_enable(intr_handle);
1319 /* enable support intr */
1320 ixgbe_enable_intr(eth_dev);
1322 /* initialize filter info */
1323 memset(filter_info, 0,
1324 sizeof(struct ixgbe_filter_info));
1326 /* initialize 5tuple filter list */
1327 TAILQ_INIT(&filter_info->fivetuple_list);
1329 /* initialize flow director filter list & hash */
1330 ixgbe_fdir_filter_init(eth_dev);
1332 /* initialize l2 tunnel filter list & hash */
1333 ixgbe_l2_tn_filter_init(eth_dev);
1335 TAILQ_INIT(&filter_ntuple_list);
1336 TAILQ_INIT(&filter_ethertype_list);
1337 TAILQ_INIT(&filter_syn_list);
1338 TAILQ_INIT(&filter_fdir_list);
1339 TAILQ_INIT(&filter_l2_tunnel_list);
1340 TAILQ_INIT(&ixgbe_flow_list);
1342 /* initialize bandwidth configuration info */
1343 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1345 /* initialize Traffic Manager configuration */
1346 ixgbe_tm_conf_init(eth_dev);
1352 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1354 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1355 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1356 struct ixgbe_hw *hw;
1358 PMD_INIT_FUNC_TRACE();
1360 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1363 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1365 if (hw->adapter_stopped == 0)
1366 ixgbe_dev_close(eth_dev);
1368 eth_dev->dev_ops = NULL;
1369 eth_dev->rx_pkt_burst = NULL;
1370 eth_dev->tx_pkt_burst = NULL;
1372 /* Unlock any pending hardware semaphore */
1373 ixgbe_swfw_lock_reset(hw);
1375 /* disable uio intr before callback unregister */
1376 rte_intr_disable(intr_handle);
1377 rte_intr_callback_unregister(intr_handle,
1378 ixgbe_dev_interrupt_handler, eth_dev);
1380 /* uninitialize PF if max_vfs not zero */
1381 ixgbe_pf_host_uninit(eth_dev);
1383 rte_free(eth_dev->data->mac_addrs);
1384 eth_dev->data->mac_addrs = NULL;
1386 rte_free(eth_dev->data->hash_mac_addrs);
1387 eth_dev->data->hash_mac_addrs = NULL;
1389 /* remove all the fdir filters & hash */
1390 ixgbe_fdir_filter_uninit(eth_dev);
1392 /* remove all the L2 tunnel filters & hash */
1393 ixgbe_l2_tn_filter_uninit(eth_dev);
1395 /* Remove all ntuple filters of the device */
1396 ixgbe_ntuple_filter_uninit(eth_dev);
1398 /* clear all the filters list */
1399 ixgbe_filterlist_flush();
1401 /* Remove all Traffic Manager configuration */
1402 ixgbe_tm_conf_uninit(eth_dev);
1407 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1409 struct ixgbe_filter_info *filter_info =
1410 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1411 struct ixgbe_5tuple_filter *p_5tuple;
1413 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1414 TAILQ_REMOVE(&filter_info->fivetuple_list,
1419 memset(filter_info->fivetuple_mask, 0,
1420 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1425 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1427 struct ixgbe_hw_fdir_info *fdir_info =
1428 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1429 struct ixgbe_fdir_filter *fdir_filter;
1431 if (fdir_info->hash_map)
1432 rte_free(fdir_info->hash_map);
1433 if (fdir_info->hash_handle)
1434 rte_hash_free(fdir_info->hash_handle);
1436 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1437 TAILQ_REMOVE(&fdir_info->fdir_list,
1440 rte_free(fdir_filter);
1446 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1448 struct ixgbe_l2_tn_info *l2_tn_info =
1449 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1450 struct ixgbe_l2_tn_filter *l2_tn_filter;
1452 if (l2_tn_info->hash_map)
1453 rte_free(l2_tn_info->hash_map);
1454 if (l2_tn_info->hash_handle)
1455 rte_hash_free(l2_tn_info->hash_handle);
1457 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1458 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1461 rte_free(l2_tn_filter);
1467 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1469 struct ixgbe_hw_fdir_info *fdir_info =
1470 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1471 char fdir_hash_name[RTE_HASH_NAMESIZE];
1472 struct rte_hash_parameters fdir_hash_params = {
1473 .name = fdir_hash_name,
1474 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1475 .key_len = sizeof(union ixgbe_atr_input),
1476 .hash_func = rte_hash_crc,
1477 .hash_func_init_val = 0,
1478 .socket_id = rte_socket_id(),
1481 TAILQ_INIT(&fdir_info->fdir_list);
1482 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1483 "fdir_%s", eth_dev->device->name);
1484 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1485 if (!fdir_info->hash_handle) {
1486 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1489 fdir_info->hash_map = rte_zmalloc("ixgbe",
1490 sizeof(struct ixgbe_fdir_filter *) *
1491 IXGBE_MAX_FDIR_FILTER_NUM,
1493 if (!fdir_info->hash_map) {
1495 "Failed to allocate memory for fdir hash map!");
1498 fdir_info->mask_added = FALSE;
1503 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1505 struct ixgbe_l2_tn_info *l2_tn_info =
1506 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1507 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1508 struct rte_hash_parameters l2_tn_hash_params = {
1509 .name = l2_tn_hash_name,
1510 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1511 .key_len = sizeof(struct ixgbe_l2_tn_key),
1512 .hash_func = rte_hash_crc,
1513 .hash_func_init_val = 0,
1514 .socket_id = rte_socket_id(),
1517 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1518 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1519 "l2_tn_%s", eth_dev->device->name);
1520 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1521 if (!l2_tn_info->hash_handle) {
1522 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1525 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1526 sizeof(struct ixgbe_l2_tn_filter *) *
1527 IXGBE_MAX_L2_TN_FILTER_NUM,
1529 if (!l2_tn_info->hash_map) {
1531 "Failed to allocate memory for L2 TN hash map!");
1534 l2_tn_info->e_tag_en = FALSE;
1535 l2_tn_info->e_tag_fwd_en = FALSE;
1536 l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1541 * Negotiate mailbox API version with the PF.
1542 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1543 * Then we try to negotiate starting with the most recent one.
1544 * If all negotiation attempts fail, then we will proceed with
1545 * the default one (ixgbe_mbox_api_10).
1548 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1552 /* start with highest supported, proceed down */
1553 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1560 i != RTE_DIM(sup_ver) &&
1561 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1567 generate_random_mac_addr(struct ether_addr *mac_addr)
1571 /* Set Organizationally Unique Identifier (OUI) prefix. */
1572 mac_addr->addr_bytes[0] = 0x00;
1573 mac_addr->addr_bytes[1] = 0x09;
1574 mac_addr->addr_bytes[2] = 0xC0;
1575 /* Force indication of locally assigned MAC address. */
1576 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1577 /* Generate the last 3 bytes of the MAC address with a random number. */
1578 random = rte_rand();
1579 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1583 * Virtual Function device init
1586 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1590 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1591 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1592 struct ixgbe_hw *hw =
1593 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1594 struct ixgbe_vfta *shadow_vfta =
1595 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1596 struct ixgbe_hwstrip *hwstrip =
1597 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1598 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1600 PMD_INIT_FUNC_TRACE();
1602 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1603 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1604 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1606 /* for secondary processes, we don't initialise any further as primary
1607 * has already done this work. Only check we don't need a different
1610 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1611 struct ixgbe_tx_queue *txq;
1612 /* TX queue function in primary, set by last queue initialized
1613 * Tx queue may not initialized by primary process
1615 if (eth_dev->data->tx_queues) {
1616 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1617 ixgbe_set_tx_function(eth_dev, txq);
1619 /* Use default TX function if we get here */
1620 PMD_INIT_LOG(NOTICE,
1621 "No TX queues configured yet. Using default TX function.");
1624 ixgbe_set_rx_function(eth_dev);
1629 rte_eth_copy_pci_info(eth_dev, pci_dev);
1630 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1632 hw->device_id = pci_dev->id.device_id;
1633 hw->vendor_id = pci_dev->id.vendor_id;
1634 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1636 /* initialize the vfta */
1637 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1639 /* initialize the hw strip bitmap*/
1640 memset(hwstrip, 0, sizeof(*hwstrip));
1642 /* Initialize the shared code (base driver) */
1643 diag = ixgbe_init_shared_code(hw);
1644 if (diag != IXGBE_SUCCESS) {
1645 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1649 /* init_mailbox_params */
1650 hw->mbx.ops.init_params(hw);
1652 /* Reset the hw statistics */
1653 ixgbevf_dev_stats_reset(eth_dev);
1655 /* Disable the interrupts for VF */
1656 ixgbevf_intr_disable(hw);
1658 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1659 diag = hw->mac.ops.reset_hw(hw);
1662 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1663 * the underlying PF driver has not assigned a MAC address to the VF.
1664 * In this case, assign a random MAC address.
1666 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1667 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1671 /* negotiate mailbox API version to use with the PF. */
1672 ixgbevf_negotiate_api(hw);
1674 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1675 ixgbevf_get_queues(hw, &tcs, &tc);
1677 /* Allocate memory for storing MAC addresses */
1678 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1679 hw->mac.num_rar_entries, 0);
1680 if (eth_dev->data->mac_addrs == NULL) {
1682 "Failed to allocate %u bytes needed to store "
1684 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1688 /* Generate a random MAC address, if none was assigned by PF. */
1689 if (is_zero_ether_addr(perm_addr)) {
1690 generate_random_mac_addr(perm_addr);
1691 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1693 rte_free(eth_dev->data->mac_addrs);
1694 eth_dev->data->mac_addrs = NULL;
1697 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1698 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1699 "%02x:%02x:%02x:%02x:%02x:%02x",
1700 perm_addr->addr_bytes[0],
1701 perm_addr->addr_bytes[1],
1702 perm_addr->addr_bytes[2],
1703 perm_addr->addr_bytes[3],
1704 perm_addr->addr_bytes[4],
1705 perm_addr->addr_bytes[5]);
1708 /* Copy the permanent MAC address */
1709 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1711 /* reset the hardware with the new settings */
1712 diag = hw->mac.ops.start_hw(hw);
1718 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1722 rte_intr_callback_register(intr_handle,
1723 ixgbevf_dev_interrupt_handler, eth_dev);
1724 rte_intr_enable(intr_handle);
1725 ixgbevf_intr_enable(hw);
1727 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1728 eth_dev->data->port_id, pci_dev->id.vendor_id,
1729 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1734 /* Virtual Function device uninit */
1737 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1739 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1740 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1741 struct ixgbe_hw *hw;
1743 PMD_INIT_FUNC_TRACE();
1745 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1748 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1750 if (hw->adapter_stopped == 0)
1751 ixgbevf_dev_close(eth_dev);
1753 eth_dev->dev_ops = NULL;
1754 eth_dev->rx_pkt_burst = NULL;
1755 eth_dev->tx_pkt_burst = NULL;
1757 /* Disable the interrupts for VF */
1758 ixgbevf_intr_disable(hw);
1760 rte_free(eth_dev->data->mac_addrs);
1761 eth_dev->data->mac_addrs = NULL;
1763 rte_intr_disable(intr_handle);
1764 rte_intr_callback_unregister(intr_handle,
1765 ixgbevf_dev_interrupt_handler, eth_dev);
1770 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1771 struct rte_pci_device *pci_dev)
1773 return rte_eth_dev_pci_generic_probe(pci_dev,
1774 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1777 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1779 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1782 static struct rte_pci_driver rte_ixgbe_pmd = {
1783 .id_table = pci_id_ixgbe_map,
1784 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1785 .probe = eth_ixgbe_pci_probe,
1786 .remove = eth_ixgbe_pci_remove,
1789 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1790 struct rte_pci_device *pci_dev)
1792 return rte_eth_dev_pci_generic_probe(pci_dev,
1793 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1796 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1798 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1802 * virtual function driver struct
1804 static struct rte_pci_driver rte_ixgbevf_pmd = {
1805 .id_table = pci_id_ixgbevf_map,
1806 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1807 .probe = eth_ixgbevf_pci_probe,
1808 .remove = eth_ixgbevf_pci_remove,
1812 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1814 struct ixgbe_hw *hw =
1815 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1816 struct ixgbe_vfta *shadow_vfta =
1817 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1822 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1823 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1824 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1829 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1831 /* update local VFTA copy */
1832 shadow_vfta->vfta[vid_idx] = vfta;
1838 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1841 ixgbe_vlan_hw_strip_enable(dev, queue);
1843 ixgbe_vlan_hw_strip_disable(dev, queue);
1847 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1848 enum rte_vlan_type vlan_type,
1851 struct ixgbe_hw *hw =
1852 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1857 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1858 qinq &= IXGBE_DMATXCTL_GDV;
1860 switch (vlan_type) {
1861 case ETH_VLAN_TYPE_INNER:
1863 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1864 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1865 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1866 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1867 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1868 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1869 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1872 PMD_DRV_LOG(ERR, "Inner type is not supported"
1876 case ETH_VLAN_TYPE_OUTER:
1878 /* Only the high 16-bits is valid */
1879 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1880 IXGBE_EXVET_VET_EXT_SHIFT);
1882 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1883 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1884 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1885 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1886 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1887 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1888 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1894 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1902 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1904 struct ixgbe_hw *hw =
1905 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1908 PMD_INIT_FUNC_TRACE();
1910 /* Filter Table Disable */
1911 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1912 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1914 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1918 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1920 struct ixgbe_hw *hw =
1921 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922 struct ixgbe_vfta *shadow_vfta =
1923 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1927 PMD_INIT_FUNC_TRACE();
1929 /* Filter Table Enable */
1930 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1931 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1932 vlnctrl |= IXGBE_VLNCTRL_VFE;
1934 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1936 /* write whatever is in local vfta copy */
1937 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1938 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1942 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1944 struct ixgbe_hwstrip *hwstrip =
1945 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1946 struct ixgbe_rx_queue *rxq;
1948 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1952 IXGBE_SET_HWSTRIP(hwstrip, queue);
1954 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1956 if (queue >= dev->data->nb_rx_queues)
1959 rxq = dev->data->rx_queues[queue];
1962 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1964 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1968 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1970 struct ixgbe_hw *hw =
1971 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1974 PMD_INIT_FUNC_TRACE();
1976 if (hw->mac.type == ixgbe_mac_82598EB) {
1977 /* No queue level support */
1978 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1982 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1983 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1984 ctrl &= ~IXGBE_RXDCTL_VME;
1985 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1987 /* record those setting for HW strip per queue */
1988 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1992 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1994 struct ixgbe_hw *hw =
1995 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1998 PMD_INIT_FUNC_TRACE();
2000 if (hw->mac.type == ixgbe_mac_82598EB) {
2001 /* No queue level supported */
2002 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2006 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2007 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2008 ctrl |= IXGBE_RXDCTL_VME;
2009 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2011 /* record those setting for HW strip per queue */
2012 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2016 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2018 struct ixgbe_hw *hw =
2019 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2022 struct ixgbe_rx_queue *rxq;
2024 PMD_INIT_FUNC_TRACE();
2026 if (hw->mac.type == ixgbe_mac_82598EB) {
2027 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2028 ctrl &= ~IXGBE_VLNCTRL_VME;
2029 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2031 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2032 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2033 rxq = dev->data->rx_queues[i];
2034 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2035 ctrl &= ~IXGBE_RXDCTL_VME;
2036 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2038 /* record those setting for HW strip per queue */
2039 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2045 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2047 struct ixgbe_hw *hw =
2048 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2051 struct ixgbe_rx_queue *rxq;
2053 PMD_INIT_FUNC_TRACE();
2055 if (hw->mac.type == ixgbe_mac_82598EB) {
2056 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2057 ctrl |= IXGBE_VLNCTRL_VME;
2058 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2060 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2061 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2062 rxq = dev->data->rx_queues[i];
2063 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2064 ctrl |= IXGBE_RXDCTL_VME;
2065 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2067 /* record those setting for HW strip per queue */
2068 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2074 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2076 struct ixgbe_hw *hw =
2077 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2080 PMD_INIT_FUNC_TRACE();
2082 /* DMATXCTRL: Geric Double VLAN Disable */
2083 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2084 ctrl &= ~IXGBE_DMATXCTL_GDV;
2085 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2087 /* CTRL_EXT: Global Double VLAN Disable */
2088 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2089 ctrl &= ~IXGBE_EXTENDED_VLAN;
2090 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2095 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2097 struct ixgbe_hw *hw =
2098 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2101 PMD_INIT_FUNC_TRACE();
2103 /* DMATXCTRL: Geric Double VLAN Enable */
2104 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2105 ctrl |= IXGBE_DMATXCTL_GDV;
2106 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2108 /* CTRL_EXT: Global Double VLAN Enable */
2109 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2110 ctrl |= IXGBE_EXTENDED_VLAN;
2111 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2113 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2114 if (hw->mac.type == ixgbe_mac_X550 ||
2115 hw->mac.type == ixgbe_mac_X550EM_x ||
2116 hw->mac.type == ixgbe_mac_X550EM_a) {
2117 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2118 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2119 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2123 * VET EXT field in the EXVET register = 0x8100 by default
2124 * So no need to change. Same to VT field of DMATXCTL register
2129 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2131 if (mask & ETH_VLAN_STRIP_MASK) {
2132 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2133 ixgbe_vlan_hw_strip_enable_all(dev);
2135 ixgbe_vlan_hw_strip_disable_all(dev);
2138 if (mask & ETH_VLAN_FILTER_MASK) {
2139 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2140 ixgbe_vlan_hw_filter_enable(dev);
2142 ixgbe_vlan_hw_filter_disable(dev);
2145 if (mask & ETH_VLAN_EXTEND_MASK) {
2146 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2147 ixgbe_vlan_hw_extend_enable(dev);
2149 ixgbe_vlan_hw_extend_disable(dev);
2154 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2156 struct ixgbe_hw *hw =
2157 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2158 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2159 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2161 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2162 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2166 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2168 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2173 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2176 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2182 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2183 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2189 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2191 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2192 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2193 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2194 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2196 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2197 /* check multi-queue mode */
2198 switch (dev_conf->rxmode.mq_mode) {
2199 case ETH_MQ_RX_VMDQ_DCB:
2200 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2202 case ETH_MQ_RX_VMDQ_DCB_RSS:
2203 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2204 PMD_INIT_LOG(ERR, "SRIOV active,"
2205 " unsupported mq_mode rx %d.",
2206 dev_conf->rxmode.mq_mode);
2209 case ETH_MQ_RX_VMDQ_RSS:
2210 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2211 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2212 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2213 PMD_INIT_LOG(ERR, "SRIOV is active,"
2214 " invalid queue number"
2215 " for VMDQ RSS, allowed"
2216 " value are 1, 2 or 4.");
2220 case ETH_MQ_RX_VMDQ_ONLY:
2221 case ETH_MQ_RX_NONE:
2222 /* if nothing mq mode configure, use default scheme */
2223 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2224 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2225 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2227 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2228 /* SRIOV only works in VMDq enable mode */
2229 PMD_INIT_LOG(ERR, "SRIOV is active,"
2230 " wrong mq_mode rx %d.",
2231 dev_conf->rxmode.mq_mode);
2235 switch (dev_conf->txmode.mq_mode) {
2236 case ETH_MQ_TX_VMDQ_DCB:
2237 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2238 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2240 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2241 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2245 /* check valid queue number */
2246 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2247 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2248 PMD_INIT_LOG(ERR, "SRIOV is active,"
2249 " nb_rx_q=%d nb_tx_q=%d queue number"
2250 " must be less than or equal to %d.",
2252 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2256 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2257 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2261 /* check configuration for vmdb+dcb mode */
2262 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2263 const struct rte_eth_vmdq_dcb_conf *conf;
2265 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2266 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2267 IXGBE_VMDQ_DCB_NB_QUEUES);
2270 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2271 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2272 conf->nb_queue_pools == ETH_32_POOLS)) {
2273 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2274 " nb_queue_pools must be %d or %d.",
2275 ETH_16_POOLS, ETH_32_POOLS);
2279 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2280 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2282 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2283 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2284 IXGBE_VMDQ_DCB_NB_QUEUES);
2287 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2288 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2289 conf->nb_queue_pools == ETH_32_POOLS)) {
2290 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2291 " nb_queue_pools != %d and"
2292 " nb_queue_pools != %d.",
2293 ETH_16_POOLS, ETH_32_POOLS);
2298 /* For DCB mode check our configuration before we go further */
2299 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2300 const struct rte_eth_dcb_rx_conf *conf;
2302 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2303 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2304 IXGBE_DCB_NB_QUEUES);
2307 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2308 if (!(conf->nb_tcs == ETH_4_TCS ||
2309 conf->nb_tcs == ETH_8_TCS)) {
2310 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2311 " and nb_tcs != %d.",
2312 ETH_4_TCS, ETH_8_TCS);
2317 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2318 const struct rte_eth_dcb_tx_conf *conf;
2320 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2321 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2322 IXGBE_DCB_NB_QUEUES);
2325 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2326 if (!(conf->nb_tcs == ETH_4_TCS ||
2327 conf->nb_tcs == ETH_8_TCS)) {
2328 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2329 " and nb_tcs != %d.",
2330 ETH_4_TCS, ETH_8_TCS);
2336 * When DCB/VT is off, maximum number of queues changes,
2337 * except for 82598EB, which remains constant.
2339 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2340 hw->mac.type != ixgbe_mac_82598EB) {
2341 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2343 "Neither VT nor DCB are enabled, "
2345 IXGBE_NONE_MODE_TX_NB_QUEUES);
2354 ixgbe_dev_configure(struct rte_eth_dev *dev)
2356 struct ixgbe_interrupt *intr =
2357 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2358 struct ixgbe_adapter *adapter =
2359 (struct ixgbe_adapter *)dev->data->dev_private;
2362 PMD_INIT_FUNC_TRACE();
2363 /* multipe queue mode checking */
2364 ret = ixgbe_check_mq_mode(dev);
2366 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2371 /* set flag to update link status after init */
2372 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2375 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2376 * allocation or vector Rx preconditions we will reset it.
2378 adapter->rx_bulk_alloc_allowed = true;
2379 adapter->rx_vec_allowed = true;
2385 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2387 struct ixgbe_hw *hw =
2388 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2389 struct ixgbe_interrupt *intr =
2390 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2393 /* only set up it on X550EM_X */
2394 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2395 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2396 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2397 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2398 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2399 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2404 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2405 uint16_t tx_rate, uint64_t q_msk)
2407 struct ixgbe_hw *hw;
2408 struct ixgbe_vf_info *vfinfo;
2409 struct rte_eth_link link;
2410 uint8_t nb_q_per_pool;
2411 uint32_t queue_stride;
2412 uint32_t queue_idx, idx = 0, vf_idx;
2414 uint16_t total_rate = 0;
2415 struct rte_pci_device *pci_dev;
2417 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2418 rte_eth_link_get_nowait(dev->data->port_id, &link);
2420 if (vf >= pci_dev->max_vfs)
2423 if (tx_rate > link.link_speed)
2429 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2430 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2431 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2432 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2433 queue_idx = vf * queue_stride;
2434 queue_end = queue_idx + nb_q_per_pool - 1;
2435 if (queue_end >= hw->mac.max_tx_queues)
2439 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2442 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2444 total_rate += vfinfo[vf_idx].tx_rate[idx];
2450 /* Store tx_rate for this vf. */
2451 for (idx = 0; idx < nb_q_per_pool; idx++) {
2452 if (((uint64_t)0x1 << idx) & q_msk) {
2453 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2454 vfinfo[vf].tx_rate[idx] = tx_rate;
2455 total_rate += tx_rate;
2459 if (total_rate > dev->data->dev_link.link_speed) {
2460 /* Reset stored TX rate of the VF if it causes exceed
2463 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2467 /* Set RTTBCNRC of each queue/pool for vf X */
2468 for (; queue_idx <= queue_end; queue_idx++) {
2470 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2478 * Configure device link speed and setup link.
2479 * It returns 0 on success.
2482 ixgbe_dev_start(struct rte_eth_dev *dev)
2484 struct ixgbe_hw *hw =
2485 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2486 struct ixgbe_vf_info *vfinfo =
2487 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2488 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2489 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2490 uint32_t intr_vector = 0;
2491 int err, link_up = 0, negotiate = 0;
2496 uint32_t *link_speeds;
2497 struct ixgbe_tm_conf *tm_conf =
2498 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2500 PMD_INIT_FUNC_TRACE();
2502 /* IXGBE devices don't support:
2503 * - half duplex (checked afterwards for valid speeds)
2504 * - fixed speed: TODO implement
2506 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2507 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2508 dev->data->port_id);
2512 /* disable uio/vfio intr/eventfd mapping */
2513 rte_intr_disable(intr_handle);
2516 hw->adapter_stopped = 0;
2517 ixgbe_stop_adapter(hw);
2519 /* reinitialize adapter
2520 * this calls reset and start
2522 status = ixgbe_pf_reset_hw(hw);
2525 hw->mac.ops.start_hw(hw);
2526 hw->mac.get_link_status = true;
2528 /* configure PF module if SRIOV enabled */
2529 ixgbe_pf_host_configure(dev);
2531 ixgbe_dev_phy_intr_setup(dev);
2533 /* check and configure queue intr-vector mapping */
2534 if ((rte_intr_cap_multiple(intr_handle) ||
2535 !RTE_ETH_DEV_SRIOV(dev).active) &&
2536 dev->data->dev_conf.intr_conf.rxq != 0) {
2537 intr_vector = dev->data->nb_rx_queues;
2538 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2539 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2540 IXGBE_MAX_INTR_QUEUE_NUM);
2543 if (rte_intr_efd_enable(intr_handle, intr_vector))
2547 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2548 intr_handle->intr_vec =
2549 rte_zmalloc("intr_vec",
2550 dev->data->nb_rx_queues * sizeof(int), 0);
2551 if (intr_handle->intr_vec == NULL) {
2552 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2553 " intr_vec", dev->data->nb_rx_queues);
2558 /* confiugre msix for sleep until rx interrupt */
2559 ixgbe_configure_msix(dev);
2561 /* initialize transmission unit */
2562 ixgbe_dev_tx_init(dev);
2564 /* This can fail when allocating mbufs for descriptor rings */
2565 err = ixgbe_dev_rx_init(dev);
2567 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2571 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2572 ETH_VLAN_EXTEND_MASK;
2573 ixgbe_vlan_offload_set(dev, mask);
2575 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2576 /* Enable vlan filtering for VMDq */
2577 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2580 /* Configure DCB hw */
2581 ixgbe_configure_dcb(dev);
2583 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2584 err = ixgbe_fdir_configure(dev);
2589 /* Restore vf rate limit */
2590 if (vfinfo != NULL) {
2591 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2592 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2593 if (vfinfo[vf].tx_rate[idx] != 0)
2594 ixgbe_set_vf_rate_limit(
2596 vfinfo[vf].tx_rate[idx],
2600 ixgbe_restore_statistics_mapping(dev);
2602 err = ixgbe_dev_rxtx_start(dev);
2604 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2608 /* Skip link setup if loopback mode is enabled for 82599. */
2609 if (hw->mac.type == ixgbe_mac_82599EB &&
2610 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2611 goto skip_link_setup;
2613 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2614 err = hw->mac.ops.setup_sfp(hw);
2619 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2620 /* Turn on the copper */
2621 ixgbe_set_phy_power(hw, true);
2623 /* Turn on the laser */
2624 ixgbe_enable_tx_laser(hw);
2627 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2630 dev->data->dev_link.link_status = link_up;
2632 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2636 link_speeds = &dev->data->dev_conf.link_speeds;
2637 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2638 ETH_LINK_SPEED_10G)) {
2639 PMD_INIT_LOG(ERR, "Invalid link setting");
2644 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2645 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2646 IXGBE_LINK_SPEED_82599_AUTONEG :
2647 IXGBE_LINK_SPEED_82598_AUTONEG;
2649 if (*link_speeds & ETH_LINK_SPEED_10G)
2650 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2651 if (*link_speeds & ETH_LINK_SPEED_1G)
2652 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2653 if (*link_speeds & ETH_LINK_SPEED_100M)
2654 speed |= IXGBE_LINK_SPEED_100_FULL;
2657 err = ixgbe_setup_link(hw, speed, link_up);
2663 if (rte_intr_allow_others(intr_handle)) {
2664 /* check if lsc interrupt is enabled */
2665 if (dev->data->dev_conf.intr_conf.lsc != 0)
2666 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2668 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2669 ixgbe_dev_macsec_interrupt_setup(dev);
2671 rte_intr_callback_unregister(intr_handle,
2672 ixgbe_dev_interrupt_handler, dev);
2673 if (dev->data->dev_conf.intr_conf.lsc != 0)
2674 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2675 " no intr multiplex");
2678 /* check if rxq interrupt is enabled */
2679 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2680 rte_intr_dp_is_en(intr_handle))
2681 ixgbe_dev_rxq_interrupt_setup(dev);
2683 /* enable uio/vfio intr/eventfd mapping */
2684 rte_intr_enable(intr_handle);
2686 /* resume enabled intr since hw reset */
2687 ixgbe_enable_intr(dev);
2688 ixgbe_l2_tunnel_conf(dev);
2689 ixgbe_filter_restore(dev);
2691 if (tm_conf->root && !tm_conf->committed)
2692 PMD_DRV_LOG(WARNING,
2693 "please call hierarchy_commit() "
2694 "before starting the port");
2699 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2700 ixgbe_dev_clear_queues(dev);
2705 * Stop device: disable rx and tx functions to allow for reconfiguring.
2708 ixgbe_dev_stop(struct rte_eth_dev *dev)
2710 struct rte_eth_link link;
2711 struct ixgbe_hw *hw =
2712 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2713 struct ixgbe_vf_info *vfinfo =
2714 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2715 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2716 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2718 struct ixgbe_tm_conf *tm_conf =
2719 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2721 PMD_INIT_FUNC_TRACE();
2723 /* disable interrupts */
2724 ixgbe_disable_intr(hw);
2727 ixgbe_pf_reset_hw(hw);
2728 hw->adapter_stopped = 0;
2731 ixgbe_stop_adapter(hw);
2733 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2734 vfinfo[vf].clear_to_send = false;
2736 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2737 /* Turn off the copper */
2738 ixgbe_set_phy_power(hw, false);
2740 /* Turn off the laser */
2741 ixgbe_disable_tx_laser(hw);
2744 ixgbe_dev_clear_queues(dev);
2746 /* Clear stored conf */
2747 dev->data->scattered_rx = 0;
2750 /* Clear recorded link status */
2751 memset(&link, 0, sizeof(link));
2752 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2754 if (!rte_intr_allow_others(intr_handle))
2755 /* resume to the default handler */
2756 rte_intr_callback_register(intr_handle,
2757 ixgbe_dev_interrupt_handler,
2760 /* Clean datapath event and queue/vec mapping */
2761 rte_intr_efd_disable(intr_handle);
2762 if (intr_handle->intr_vec != NULL) {
2763 rte_free(intr_handle->intr_vec);
2764 intr_handle->intr_vec = NULL;
2767 /* reset hierarchy commit */
2768 tm_conf->committed = false;
2772 * Set device link up: enable tx.
2775 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2777 struct ixgbe_hw *hw =
2778 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2779 if (hw->mac.type == ixgbe_mac_82599EB) {
2780 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2781 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2782 /* Not suported in bypass mode */
2783 PMD_INIT_LOG(ERR, "Set link up is not supported "
2784 "by device id 0x%x", hw->device_id);
2790 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2791 /* Turn on the copper */
2792 ixgbe_set_phy_power(hw, true);
2794 /* Turn on the laser */
2795 ixgbe_enable_tx_laser(hw);
2802 * Set device link down: disable tx.
2805 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2807 struct ixgbe_hw *hw =
2808 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2809 if (hw->mac.type == ixgbe_mac_82599EB) {
2810 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2811 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2812 /* Not suported in bypass mode */
2813 PMD_INIT_LOG(ERR, "Set link down is not supported "
2814 "by device id 0x%x", hw->device_id);
2820 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2821 /* Turn off the copper */
2822 ixgbe_set_phy_power(hw, false);
2824 /* Turn off the laser */
2825 ixgbe_disable_tx_laser(hw);
2832 * Reest and stop device.
2835 ixgbe_dev_close(struct rte_eth_dev *dev)
2837 struct ixgbe_hw *hw =
2838 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2840 PMD_INIT_FUNC_TRACE();
2842 ixgbe_pf_reset_hw(hw);
2844 ixgbe_dev_stop(dev);
2845 hw->adapter_stopped = 1;
2847 ixgbe_dev_free_queues(dev);
2849 ixgbe_disable_pcie_master(hw);
2851 /* reprogram the RAR[0] in case user changed it. */
2852 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2856 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2857 struct ixgbe_hw_stats *hw_stats,
2858 struct ixgbe_macsec_stats *macsec_stats,
2859 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2860 uint64_t *total_qprc, uint64_t *total_qprdc)
2862 uint32_t bprc, lxon, lxoff, total;
2863 uint32_t delta_gprc = 0;
2865 /* Workaround for RX byte count not including CRC bytes when CRC
2866 * strip is enabled. CRC bytes are removed from counters when crc_strip
2869 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2870 IXGBE_HLREG0_RXCRCSTRP);
2872 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2873 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2874 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2875 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2877 for (i = 0; i < 8; i++) {
2878 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2880 /* global total per queue */
2881 hw_stats->mpc[i] += mp;
2882 /* Running comprehensive total for stats display */
2883 *total_missed_rx += hw_stats->mpc[i];
2884 if (hw->mac.type == ixgbe_mac_82598EB) {
2885 hw_stats->rnbc[i] +=
2886 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2887 hw_stats->pxonrxc[i] +=
2888 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2889 hw_stats->pxoffrxc[i] +=
2890 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2892 hw_stats->pxonrxc[i] +=
2893 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2894 hw_stats->pxoffrxc[i] +=
2895 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2896 hw_stats->pxon2offc[i] +=
2897 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2899 hw_stats->pxontxc[i] +=
2900 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2901 hw_stats->pxofftxc[i] +=
2902 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2904 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2905 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2906 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2907 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2909 delta_gprc += delta_qprc;
2911 hw_stats->qprc[i] += delta_qprc;
2912 hw_stats->qptc[i] += delta_qptc;
2914 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2915 hw_stats->qbrc[i] +=
2916 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2918 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2920 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2921 hw_stats->qbtc[i] +=
2922 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2924 hw_stats->qprdc[i] += delta_qprdc;
2925 *total_qprdc += hw_stats->qprdc[i];
2927 *total_qprc += hw_stats->qprc[i];
2928 *total_qbrc += hw_stats->qbrc[i];
2930 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2931 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2932 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2935 * An errata states that gprc actually counts good + missed packets:
2936 * Workaround to set gprc to summated queue packet receives
2938 hw_stats->gprc = *total_qprc;
2940 if (hw->mac.type != ixgbe_mac_82598EB) {
2941 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2942 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2943 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2944 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2945 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2946 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2947 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2948 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2950 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2951 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2952 /* 82598 only has a counter in the high register */
2953 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2954 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2955 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2957 uint64_t old_tpr = hw_stats->tpr;
2959 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2960 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2963 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2965 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2966 hw_stats->gptc += delta_gptc;
2967 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2968 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2971 * Workaround: mprc hardware is incorrectly counting
2972 * broadcasts, so for now we subtract those.
2974 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2975 hw_stats->bprc += bprc;
2976 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2977 if (hw->mac.type == ixgbe_mac_82598EB)
2978 hw_stats->mprc -= bprc;
2980 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2981 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2982 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2983 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2984 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2985 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2987 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2988 hw_stats->lxontxc += lxon;
2989 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2990 hw_stats->lxofftxc += lxoff;
2991 total = lxon + lxoff;
2993 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2994 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2995 hw_stats->gptc -= total;
2996 hw_stats->mptc -= total;
2997 hw_stats->ptc64 -= total;
2998 hw_stats->gotc -= total * ETHER_MIN_LEN;
3000 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3001 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3002 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3003 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3004 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3005 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3006 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3007 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3008 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3009 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3010 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3011 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3012 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3013 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3014 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3015 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3016 /* Only read FCOE on 82599 */
3017 if (hw->mac.type != ixgbe_mac_82598EB) {
3018 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3019 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3020 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3021 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3022 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3025 /* Flow Director Stats registers */
3026 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3027 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3029 /* MACsec Stats registers */
3030 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3031 macsec_stats->out_pkts_encrypted +=
3032 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3033 macsec_stats->out_pkts_protected +=
3034 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3035 macsec_stats->out_octets_encrypted +=
3036 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3037 macsec_stats->out_octets_protected +=
3038 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3039 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3040 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3041 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3042 macsec_stats->in_pkts_unknownsci +=
3043 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3044 macsec_stats->in_octets_decrypted +=
3045 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3046 macsec_stats->in_octets_validated +=
3047 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3048 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3049 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3050 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3051 for (i = 0; i < 2; i++) {
3052 macsec_stats->in_pkts_ok +=
3053 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3054 macsec_stats->in_pkts_invalid +=
3055 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3056 macsec_stats->in_pkts_notvalid +=
3057 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3059 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3060 macsec_stats->in_pkts_notusingsa +=
3061 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3065 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3068 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3070 struct ixgbe_hw *hw =
3071 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3072 struct ixgbe_hw_stats *hw_stats =
3073 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3074 struct ixgbe_macsec_stats *macsec_stats =
3075 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3076 dev->data->dev_private);
3077 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3080 total_missed_rx = 0;
3085 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3086 &total_qbrc, &total_qprc, &total_qprdc);
3091 /* Fill out the rte_eth_stats statistics structure */
3092 stats->ipackets = total_qprc;
3093 stats->ibytes = total_qbrc;
3094 stats->opackets = hw_stats->gptc;
3095 stats->obytes = hw_stats->gotc;
3097 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3098 stats->q_ipackets[i] = hw_stats->qprc[i];
3099 stats->q_opackets[i] = hw_stats->qptc[i];
3100 stats->q_ibytes[i] = hw_stats->qbrc[i];
3101 stats->q_obytes[i] = hw_stats->qbtc[i];
3102 stats->q_errors[i] = hw_stats->qprdc[i];
3106 stats->imissed = total_missed_rx;
3107 stats->ierrors = hw_stats->crcerrs +
3123 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3125 struct ixgbe_hw_stats *stats =
3126 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3128 /* HW registers are cleared on read */
3129 ixgbe_dev_stats_get(dev, NULL);
3131 /* Reset software totals */
3132 memset(stats, 0, sizeof(*stats));
3135 /* This function calculates the number of xstats based on the current config */
3137 ixgbe_xstats_calc_num(void) {
3138 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3139 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3140 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3143 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3144 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3146 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3147 unsigned stat, i, count;
3149 if (xstats_names != NULL) {
3152 /* Note: limit >= cnt_stats checked upstream
3153 * in rte_eth_xstats_names()
3156 /* Extended stats from ixgbe_hw_stats */
3157 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3158 snprintf(xstats_names[count].name,
3159 sizeof(xstats_names[count].name),
3161 rte_ixgbe_stats_strings[i].name);
3166 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3167 snprintf(xstats_names[count].name,
3168 sizeof(xstats_names[count].name),
3170 rte_ixgbe_macsec_strings[i].name);
3174 /* RX Priority Stats */
3175 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3176 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3177 snprintf(xstats_names[count].name,
3178 sizeof(xstats_names[count].name),
3179 "rx_priority%u_%s", i,
3180 rte_ixgbe_rxq_strings[stat].name);
3185 /* TX Priority Stats */
3186 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3187 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3188 snprintf(xstats_names[count].name,
3189 sizeof(xstats_names[count].name),
3190 "tx_priority%u_%s", i,
3191 rte_ixgbe_txq_strings[stat].name);
3199 static int ixgbe_dev_xstats_get_names_by_id(
3200 struct rte_eth_dev *dev,
3201 struct rte_eth_xstat_name *xstats_names,
3202 const uint64_t *ids,
3206 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3207 unsigned int stat, i, count;
3209 if (xstats_names != NULL) {
3212 /* Note: limit >= cnt_stats checked upstream
3213 * in rte_eth_xstats_names()
3216 /* Extended stats from ixgbe_hw_stats */
3217 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3218 snprintf(xstats_names[count].name,
3219 sizeof(xstats_names[count].name),
3221 rte_ixgbe_stats_strings[i].name);
3226 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3227 snprintf(xstats_names[count].name,
3228 sizeof(xstats_names[count].name),
3230 rte_ixgbe_macsec_strings[i].name);
3234 /* RX Priority Stats */
3235 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3236 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3237 snprintf(xstats_names[count].name,
3238 sizeof(xstats_names[count].name),
3239 "rx_priority%u_%s", i,
3240 rte_ixgbe_rxq_strings[stat].name);
3245 /* TX Priority Stats */
3246 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3247 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3248 snprintf(xstats_names[count].name,
3249 sizeof(xstats_names[count].name),
3250 "tx_priority%u_%s", i,
3251 rte_ixgbe_txq_strings[stat].name);
3260 uint16_t size = ixgbe_xstats_calc_num();
3261 struct rte_eth_xstat_name xstats_names_copy[size];
3263 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3266 for (i = 0; i < limit; i++) {
3267 if (ids[i] >= size) {
3268 PMD_INIT_LOG(ERR, "id value isn't valid");
3271 strcpy(xstats_names[i].name,
3272 xstats_names_copy[ids[i]].name);
3277 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3278 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3282 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3285 if (xstats_names != NULL)
3286 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3287 snprintf(xstats_names[i].name,
3288 sizeof(xstats_names[i].name),
3289 "%s", rte_ixgbevf_stats_strings[i].name);
3290 return IXGBEVF_NB_XSTATS;
3294 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3297 struct ixgbe_hw *hw =
3298 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3299 struct ixgbe_hw_stats *hw_stats =
3300 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3301 struct ixgbe_macsec_stats *macsec_stats =
3302 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3303 dev->data->dev_private);
3304 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3305 unsigned i, stat, count = 0;
3307 count = ixgbe_xstats_calc_num();
3312 total_missed_rx = 0;
3317 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3318 &total_qbrc, &total_qprc, &total_qprdc);
3320 /* If this is a reset xstats is NULL, and we have cleared the
3321 * registers by reading them.
3326 /* Extended stats from ixgbe_hw_stats */
3328 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3329 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3330 rte_ixgbe_stats_strings[i].offset);
3331 xstats[count].id = count;
3336 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3337 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3338 rte_ixgbe_macsec_strings[i].offset);
3339 xstats[count].id = count;
3343 /* RX Priority Stats */
3344 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3345 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3346 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3347 rte_ixgbe_rxq_strings[stat].offset +
3348 (sizeof(uint64_t) * i));
3349 xstats[count].id = count;
3354 /* TX Priority Stats */
3355 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3356 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3357 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3358 rte_ixgbe_txq_strings[stat].offset +
3359 (sizeof(uint64_t) * i));
3360 xstats[count].id = count;
3368 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3369 uint64_t *values, unsigned int n)
3372 struct ixgbe_hw *hw =
3373 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3374 struct ixgbe_hw_stats *hw_stats =
3375 IXGBE_DEV_PRIVATE_TO_STATS(
3376 dev->data->dev_private);
3377 struct ixgbe_macsec_stats *macsec_stats =
3378 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3379 dev->data->dev_private);
3380 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3381 unsigned int i, stat, count = 0;
3383 count = ixgbe_xstats_calc_num();
3385 if (!ids && n < count)
3388 total_missed_rx = 0;
3393 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3394 &total_missed_rx, &total_qbrc, &total_qprc,
3397 /* If this is a reset xstats is NULL, and we have cleared the
3398 * registers by reading them.
3400 if (!ids && !values)
3403 /* Extended stats from ixgbe_hw_stats */
3405 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3406 values[count] = *(uint64_t *)(((char *)hw_stats) +
3407 rte_ixgbe_stats_strings[i].offset);
3412 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3413 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3414 rte_ixgbe_macsec_strings[i].offset);
3418 /* RX Priority Stats */
3419 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3420 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3422 *(uint64_t *)(((char *)hw_stats) +
3423 rte_ixgbe_rxq_strings[stat].offset +
3424 (sizeof(uint64_t) * i));
3429 /* TX Priority Stats */
3430 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3431 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3433 *(uint64_t *)(((char *)hw_stats) +
3434 rte_ixgbe_txq_strings[stat].offset +
3435 (sizeof(uint64_t) * i));
3443 uint16_t size = ixgbe_xstats_calc_num();
3444 uint64_t values_copy[size];
3446 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3448 for (i = 0; i < n; i++) {
3449 if (ids[i] >= size) {
3450 PMD_INIT_LOG(ERR, "id value isn't valid");
3453 values[i] = values_copy[ids[i]];
3459 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3461 struct ixgbe_hw_stats *stats =
3462 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3463 struct ixgbe_macsec_stats *macsec_stats =
3464 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3465 dev->data->dev_private);
3467 unsigned count = ixgbe_xstats_calc_num();
3469 /* HW registers are cleared on read */
3470 ixgbe_dev_xstats_get(dev, NULL, count);
3472 /* Reset software totals */
3473 memset(stats, 0, sizeof(*stats));
3474 memset(macsec_stats, 0, sizeof(*macsec_stats));
3478 ixgbevf_update_stats(struct rte_eth_dev *dev)
3480 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3481 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3482 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3484 /* Good Rx packet, include VF loopback */
3485 UPDATE_VF_STAT(IXGBE_VFGPRC,
3486 hw_stats->last_vfgprc, hw_stats->vfgprc);
3488 /* Good Rx octets, include VF loopback */
3489 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3490 hw_stats->last_vfgorc, hw_stats->vfgorc);
3492 /* Good Tx packet, include VF loopback */
3493 UPDATE_VF_STAT(IXGBE_VFGPTC,
3494 hw_stats->last_vfgptc, hw_stats->vfgptc);
3496 /* Good Tx octets, include VF loopback */
3497 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3498 hw_stats->last_vfgotc, hw_stats->vfgotc);
3500 /* Rx Multicst Packet */
3501 UPDATE_VF_STAT(IXGBE_VFMPRC,
3502 hw_stats->last_vfmprc, hw_stats->vfmprc);
3506 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3509 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3510 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3513 if (n < IXGBEVF_NB_XSTATS)
3514 return IXGBEVF_NB_XSTATS;
3516 ixgbevf_update_stats(dev);
3521 /* Extended stats */
3522 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3524 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3525 rte_ixgbevf_stats_strings[i].offset);
3528 return IXGBEVF_NB_XSTATS;
3532 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3534 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3535 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3537 ixgbevf_update_stats(dev);
3542 stats->ipackets = hw_stats->vfgprc;
3543 stats->ibytes = hw_stats->vfgorc;
3544 stats->opackets = hw_stats->vfgptc;
3545 stats->obytes = hw_stats->vfgotc;
3549 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3551 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3552 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3554 /* Sync HW register to the last stats */
3555 ixgbevf_dev_stats_get(dev, NULL);
3557 /* reset HW current stats*/
3558 hw_stats->vfgprc = 0;
3559 hw_stats->vfgorc = 0;
3560 hw_stats->vfgptc = 0;
3561 hw_stats->vfgotc = 0;
3565 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3567 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3568 u16 eeprom_verh, eeprom_verl;
3572 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3573 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3575 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3576 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3578 ret += 1; /* add the size of '\0' */
3579 if (fw_size < (u32)ret)
3586 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3588 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3589 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3590 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3592 dev_info->pci_dev = pci_dev;
3593 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3594 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3595 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3597 * When DCB/VT is off, maximum number of queues changes,
3598 * except for 82598EB, which remains constant.
3600 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3601 hw->mac.type != ixgbe_mac_82598EB)
3602 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3604 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3605 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3606 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3607 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3608 dev_info->max_vfs = pci_dev->max_vfs;
3609 if (hw->mac.type == ixgbe_mac_82598EB)
3610 dev_info->max_vmdq_pools = ETH_16_POOLS;
3612 dev_info->max_vmdq_pools = ETH_64_POOLS;
3613 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3614 dev_info->rx_offload_capa =
3615 DEV_RX_OFFLOAD_VLAN_STRIP |
3616 DEV_RX_OFFLOAD_IPV4_CKSUM |
3617 DEV_RX_OFFLOAD_UDP_CKSUM |
3618 DEV_RX_OFFLOAD_TCP_CKSUM;
3621 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3624 if ((hw->mac.type == ixgbe_mac_82599EB ||
3625 hw->mac.type == ixgbe_mac_X540) &&
3626 !RTE_ETH_DEV_SRIOV(dev).active)
3627 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3629 if (hw->mac.type == ixgbe_mac_82599EB ||
3630 hw->mac.type == ixgbe_mac_X540)
3631 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3633 if (hw->mac.type == ixgbe_mac_X550 ||
3634 hw->mac.type == ixgbe_mac_X550EM_x ||
3635 hw->mac.type == ixgbe_mac_X550EM_a)
3636 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3638 dev_info->tx_offload_capa =
3639 DEV_TX_OFFLOAD_VLAN_INSERT |
3640 DEV_TX_OFFLOAD_IPV4_CKSUM |
3641 DEV_TX_OFFLOAD_UDP_CKSUM |
3642 DEV_TX_OFFLOAD_TCP_CKSUM |
3643 DEV_TX_OFFLOAD_SCTP_CKSUM |
3644 DEV_TX_OFFLOAD_TCP_TSO;
3646 if (hw->mac.type == ixgbe_mac_82599EB ||
3647 hw->mac.type == ixgbe_mac_X540)
3648 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3650 if (hw->mac.type == ixgbe_mac_X550 ||
3651 hw->mac.type == ixgbe_mac_X550EM_x ||
3652 hw->mac.type == ixgbe_mac_X550EM_a)
3653 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3655 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3657 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3658 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3659 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3661 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3665 dev_info->default_txconf = (struct rte_eth_txconf) {
3667 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3668 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3669 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3671 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3672 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3673 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3674 ETH_TXQ_FLAGS_NOOFFLOADS,
3677 dev_info->rx_desc_lim = rx_desc_lim;
3678 dev_info->tx_desc_lim = tx_desc_lim;
3680 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3681 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3682 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3684 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3685 if (hw->mac.type == ixgbe_mac_X540 ||
3686 hw->mac.type == ixgbe_mac_X540_vf ||
3687 hw->mac.type == ixgbe_mac_X550 ||
3688 hw->mac.type == ixgbe_mac_X550_vf) {
3689 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3693 static const uint32_t *
3694 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3696 static const uint32_t ptypes[] = {
3697 /* For non-vec functions,
3698 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3699 * for vec functions,
3700 * refers to _recv_raw_pkts_vec().
3704 RTE_PTYPE_L3_IPV4_EXT,
3706 RTE_PTYPE_L3_IPV6_EXT,
3710 RTE_PTYPE_TUNNEL_IP,
3711 RTE_PTYPE_INNER_L3_IPV6,
3712 RTE_PTYPE_INNER_L3_IPV6_EXT,
3713 RTE_PTYPE_INNER_L4_TCP,
3714 RTE_PTYPE_INNER_L4_UDP,
3718 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3719 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3720 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3721 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3724 #if defined(RTE_ARCH_X86)
3725 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3726 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3733 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3734 struct rte_eth_dev_info *dev_info)
3736 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3737 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3739 dev_info->pci_dev = pci_dev;
3740 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3741 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3742 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3743 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3744 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3745 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3746 dev_info->max_vfs = pci_dev->max_vfs;
3747 if (hw->mac.type == ixgbe_mac_82598EB)
3748 dev_info->max_vmdq_pools = ETH_16_POOLS;
3750 dev_info->max_vmdq_pools = ETH_64_POOLS;
3751 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3752 DEV_RX_OFFLOAD_IPV4_CKSUM |
3753 DEV_RX_OFFLOAD_UDP_CKSUM |
3754 DEV_RX_OFFLOAD_TCP_CKSUM;
3755 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3756 DEV_TX_OFFLOAD_IPV4_CKSUM |
3757 DEV_TX_OFFLOAD_UDP_CKSUM |
3758 DEV_TX_OFFLOAD_TCP_CKSUM |
3759 DEV_TX_OFFLOAD_SCTP_CKSUM |
3760 DEV_TX_OFFLOAD_TCP_TSO;
3762 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3764 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3765 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3766 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3768 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3772 dev_info->default_txconf = (struct rte_eth_txconf) {
3774 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3775 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3776 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3778 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3779 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3780 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3781 ETH_TXQ_FLAGS_NOOFFLOADS,
3784 dev_info->rx_desc_lim = rx_desc_lim;
3785 dev_info->tx_desc_lim = tx_desc_lim;
3789 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3790 int *link_up, int wait_to_complete)
3793 * for a quick link status checking, wait_to_compelet == 0,
3794 * skip PF link status checking
3796 bool no_pflink_check = wait_to_complete == 0;
3797 struct ixgbe_mbx_info *mbx = &hw->mbx;
3798 struct ixgbe_mac_info *mac = &hw->mac;
3799 uint32_t links_reg, in_msg;
3802 /* If we were hit with a reset drop the link */
3803 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3804 mac->get_link_status = true;
3806 if (!mac->get_link_status)
3809 /* if link status is down no point in checking to see if pf is up */
3810 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3811 if (!(links_reg & IXGBE_LINKS_UP))
3814 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3815 * before the link status is correct
3817 if (mac->type == ixgbe_mac_82599_vf) {
3820 for (i = 0; i < 5; i++) {
3822 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3824 if (!(links_reg & IXGBE_LINKS_UP))
3829 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3830 case IXGBE_LINKS_SPEED_10G_82599:
3831 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3832 if (hw->mac.type >= ixgbe_mac_X550) {
3833 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3834 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3837 case IXGBE_LINKS_SPEED_1G_82599:
3838 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3840 case IXGBE_LINKS_SPEED_100_82599:
3841 *speed = IXGBE_LINK_SPEED_100_FULL;
3842 if (hw->mac.type == ixgbe_mac_X550) {
3843 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3844 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3847 case IXGBE_LINKS_SPEED_10_X550EM_A:
3848 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3849 /* Since Reserved in older MAC's */
3850 if (hw->mac.type >= ixgbe_mac_X550)
3851 *speed = IXGBE_LINK_SPEED_10_FULL;
3854 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3857 if (no_pflink_check) {
3858 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3859 mac->get_link_status = true;
3861 mac->get_link_status = false;
3865 /* if the read failed it could just be a mailbox collision, best wait
3866 * until we are called again and don't report an error
3868 if (mbx->ops.read(hw, &in_msg, 1, 0))
3871 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3872 /* msg is not CTS and is NACK we must have lost CTS status */
3873 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3878 /* the pf is talking, if we timed out in the past we reinit */
3879 if (!mbx->timeout) {
3884 /* if we passed all the tests above then the link is up and we no
3885 * longer need to check for link
3887 mac->get_link_status = false;
3890 *link_up = !mac->get_link_status;
3894 /* return 0 means link status changed, -1 means not changed */
3896 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3897 int wait_to_complete, int vf)
3899 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3900 struct rte_eth_link link, old;
3901 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3902 struct ixgbe_interrupt *intr =
3903 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3908 bool autoneg = false;
3910 link.link_status = ETH_LINK_DOWN;
3911 link.link_speed = 0;
3912 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3913 memset(&old, 0, sizeof(old));
3914 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3916 hw->mac.get_link_status = true;
3918 if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3919 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3920 speed = hw->phy.autoneg_advertised;
3922 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3923 ixgbe_setup_link(hw, speed, true);
3926 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3927 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3931 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3933 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3936 link.link_speed = ETH_SPEED_NUM_100M;
3937 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3938 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3939 if (link.link_status == old.link_status)
3945 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3946 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3947 if (link.link_status == old.link_status)
3951 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3952 link.link_status = ETH_LINK_UP;
3953 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3955 switch (link_speed) {
3957 case IXGBE_LINK_SPEED_UNKNOWN:
3958 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3959 link.link_speed = ETH_SPEED_NUM_100M;
3962 case IXGBE_LINK_SPEED_100_FULL:
3963 link.link_speed = ETH_SPEED_NUM_100M;
3966 case IXGBE_LINK_SPEED_1GB_FULL:
3967 link.link_speed = ETH_SPEED_NUM_1G;
3970 case IXGBE_LINK_SPEED_10GB_FULL:
3971 link.link_speed = ETH_SPEED_NUM_10G;
3974 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3976 if (link.link_status == old.link_status)
3983 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3985 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
3989 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3991 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
3995 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3997 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4000 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4001 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4002 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4006 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4008 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4011 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4012 fctrl &= (~IXGBE_FCTRL_UPE);
4013 if (dev->data->all_multicast == 1)
4014 fctrl |= IXGBE_FCTRL_MPE;
4016 fctrl &= (~IXGBE_FCTRL_MPE);
4017 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4021 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4023 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4026 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4027 fctrl |= IXGBE_FCTRL_MPE;
4028 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4032 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4034 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4037 if (dev->data->promiscuous == 1)
4038 return; /* must remain in all_multicast mode */
4040 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4041 fctrl &= (~IXGBE_FCTRL_MPE);
4042 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4046 * It clears the interrupt causes and enables the interrupt.
4047 * It will be called once only during nic initialized.
4050 * Pointer to struct rte_eth_dev.
4052 * Enable or Disable.
4055 * - On success, zero.
4056 * - On failure, a negative value.
4059 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4061 struct ixgbe_interrupt *intr =
4062 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4064 ixgbe_dev_link_status_print(dev);
4066 intr->mask |= IXGBE_EICR_LSC;
4068 intr->mask &= ~IXGBE_EICR_LSC;
4074 * It clears the interrupt causes and enables the interrupt.
4075 * It will be called once only during nic initialized.
4078 * Pointer to struct rte_eth_dev.
4081 * - On success, zero.
4082 * - On failure, a negative value.
4085 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4087 struct ixgbe_interrupt *intr =
4088 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4090 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4096 * It clears the interrupt causes and enables the interrupt.
4097 * It will be called once only during nic initialized.
4100 * Pointer to struct rte_eth_dev.
4103 * - On success, zero.
4104 * - On failure, a negative value.
4107 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4109 struct ixgbe_interrupt *intr =
4110 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4112 intr->mask |= IXGBE_EICR_LINKSEC;
4118 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4121 * Pointer to struct rte_eth_dev.
4124 * - On success, zero.
4125 * - On failure, a negative value.
4128 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4131 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4132 struct ixgbe_interrupt *intr =
4133 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4135 /* clear all cause mask */
4136 ixgbe_disable_intr(hw);
4138 /* read-on-clear nic registers here */
4139 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4140 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4144 /* set flag for async link update */
4145 if (eicr & IXGBE_EICR_LSC)
4146 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4148 if (eicr & IXGBE_EICR_MAILBOX)
4149 intr->flags |= IXGBE_FLAG_MAILBOX;
4151 if (eicr & IXGBE_EICR_LINKSEC)
4152 intr->flags |= IXGBE_FLAG_MACSEC;
4154 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4155 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4156 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4157 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4163 * It gets and then prints the link status.
4166 * Pointer to struct rte_eth_dev.
4169 * - On success, zero.
4170 * - On failure, a negative value.
4173 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4175 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4176 struct rte_eth_link link;
4178 memset(&link, 0, sizeof(link));
4179 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4180 if (link.link_status) {
4181 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4182 (int)(dev->data->port_id),
4183 (unsigned)link.link_speed,
4184 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4185 "full-duplex" : "half-duplex");
4187 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4188 (int)(dev->data->port_id));
4190 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4191 pci_dev->addr.domain,
4193 pci_dev->addr.devid,
4194 pci_dev->addr.function);
4198 * It executes link_update after knowing an interrupt occurred.
4201 * Pointer to struct rte_eth_dev.
4204 * - On success, zero.
4205 * - On failure, a negative value.
4208 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4209 struct rte_intr_handle *intr_handle)
4211 struct ixgbe_interrupt *intr =
4212 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4214 struct rte_eth_link link;
4215 struct ixgbe_hw *hw =
4216 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4218 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4220 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4221 ixgbe_pf_mbx_process(dev);
4222 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4225 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4226 ixgbe_handle_lasi(hw);
4227 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4230 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4231 /* get the link status before link update, for predicting later */
4232 memset(&link, 0, sizeof(link));
4233 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4235 ixgbe_dev_link_update(dev, 0);
4238 if (!link.link_status)
4239 /* handle it 1 sec later, wait it being stable */
4240 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4241 /* likely to down */
4243 /* handle it 4 sec later, wait it being stable */
4244 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4246 ixgbe_dev_link_status_print(dev);
4247 if (rte_eal_alarm_set(timeout * 1000,
4248 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4249 PMD_DRV_LOG(ERR, "Error setting alarm");
4251 /* remember original mask */
4252 intr->mask_original = intr->mask;
4253 /* only disable lsc interrupt */
4254 intr->mask &= ~IXGBE_EIMS_LSC;
4258 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4259 ixgbe_enable_intr(dev);
4260 rte_intr_enable(intr_handle);
4266 * Interrupt handler which shall be registered for alarm callback for delayed
4267 * handling specific interrupt to wait for the stable nic state. As the
4268 * NIC interrupt state is not stable for ixgbe after link is just down,
4269 * it needs to wait 4 seconds to get the stable status.
4272 * Pointer to interrupt handle.
4274 * The address of parameter (struct rte_eth_dev *) regsitered before.
4280 ixgbe_dev_interrupt_delayed_handler(void *param)
4282 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4283 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4284 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4285 struct ixgbe_interrupt *intr =
4286 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4287 struct ixgbe_hw *hw =
4288 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4291 ixgbe_disable_intr(hw);
4293 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4294 if (eicr & IXGBE_EICR_MAILBOX)
4295 ixgbe_pf_mbx_process(dev);
4297 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4298 ixgbe_handle_lasi(hw);
4299 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4302 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4303 ixgbe_dev_link_update(dev, 0);
4304 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4305 ixgbe_dev_link_status_print(dev);
4306 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4310 if (intr->flags & IXGBE_FLAG_MACSEC) {
4311 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4313 intr->flags &= ~IXGBE_FLAG_MACSEC;
4316 /* restore original mask */
4317 intr->mask = intr->mask_original;
4318 intr->mask_original = 0;
4320 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4321 ixgbe_enable_intr(dev);
4322 rte_intr_enable(intr_handle);
4326 * Interrupt handler triggered by NIC for handling
4327 * specific interrupt.
4330 * Pointer to interrupt handle.
4332 * The address of parameter (struct rte_eth_dev *) regsitered before.
4338 ixgbe_dev_interrupt_handler(void *param)
4340 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4342 ixgbe_dev_interrupt_get_status(dev);
4343 ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4347 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4349 struct ixgbe_hw *hw;
4351 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4352 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4356 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4358 struct ixgbe_hw *hw;
4360 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4361 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4365 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4367 struct ixgbe_hw *hw;
4373 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4375 fc_conf->pause_time = hw->fc.pause_time;
4376 fc_conf->high_water = hw->fc.high_water[0];
4377 fc_conf->low_water = hw->fc.low_water[0];
4378 fc_conf->send_xon = hw->fc.send_xon;
4379 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4382 * Return rx_pause status according to actual setting of
4385 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4386 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4392 * Return tx_pause status according to actual setting of
4395 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4396 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4401 if (rx_pause && tx_pause)
4402 fc_conf->mode = RTE_FC_FULL;
4404 fc_conf->mode = RTE_FC_RX_PAUSE;
4406 fc_conf->mode = RTE_FC_TX_PAUSE;
4408 fc_conf->mode = RTE_FC_NONE;
4414 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4416 struct ixgbe_hw *hw;
4418 uint32_t rx_buf_size;
4419 uint32_t max_high_water;
4421 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4428 PMD_INIT_FUNC_TRACE();
4430 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4431 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4432 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4435 * At least reserve one Ethernet frame for watermark
4436 * high_water/low_water in kilo bytes for ixgbe
4438 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4439 if ((fc_conf->high_water > max_high_water) ||
4440 (fc_conf->high_water < fc_conf->low_water)) {
4441 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4442 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4446 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4447 hw->fc.pause_time = fc_conf->pause_time;
4448 hw->fc.high_water[0] = fc_conf->high_water;
4449 hw->fc.low_water[0] = fc_conf->low_water;
4450 hw->fc.send_xon = fc_conf->send_xon;
4451 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4453 err = ixgbe_fc_enable(hw);
4455 /* Not negotiated is not an error case */
4456 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4458 /* check if we want to forward MAC frames - driver doesn't have native
4459 * capability to do that, so we'll write the registers ourselves */
4461 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4463 /* set or clear MFLCN.PMCF bit depending on configuration */
4464 if (fc_conf->mac_ctrl_frame_fwd != 0)
4465 mflcn |= IXGBE_MFLCN_PMCF;
4467 mflcn &= ~IXGBE_MFLCN_PMCF;
4469 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4470 IXGBE_WRITE_FLUSH(hw);
4475 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4480 * ixgbe_pfc_enable_generic - Enable flow control
4481 * @hw: pointer to hardware structure
4482 * @tc_num: traffic class number
4483 * Enable flow control according to the current settings.
4486 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4489 uint32_t mflcn_reg, fccfg_reg;
4491 uint32_t fcrtl, fcrth;
4495 /* Validate the water mark configuration */
4496 if (!hw->fc.pause_time) {
4497 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4501 /* Low water mark of zero causes XOFF floods */
4502 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4503 /* High/Low water can not be 0 */
4504 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4505 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4506 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4510 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4511 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4512 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4516 /* Negotiate the fc mode to use */
4517 ixgbe_fc_autoneg(hw);
4519 /* Disable any previous flow control settings */
4520 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4521 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4523 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4524 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4526 switch (hw->fc.current_mode) {
4529 * If the count of enabled RX Priority Flow control >1,
4530 * and the TX pause can not be disabled
4533 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4534 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4535 if (reg & IXGBE_FCRTH_FCEN)
4539 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4541 case ixgbe_fc_rx_pause:
4543 * Rx Flow control is enabled and Tx Flow control is
4544 * disabled by software override. Since there really
4545 * isn't a way to advertise that we are capable of RX
4546 * Pause ONLY, we will advertise that we support both
4547 * symmetric and asymmetric Rx PAUSE. Later, we will
4548 * disable the adapter's ability to send PAUSE frames.
4550 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4552 * If the count of enabled RX Priority Flow control >1,
4553 * and the TX pause can not be disabled
4556 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4557 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4558 if (reg & IXGBE_FCRTH_FCEN)
4562 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4564 case ixgbe_fc_tx_pause:
4566 * Tx Flow control is enabled, and Rx Flow control is
4567 * disabled by software override.
4569 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4572 /* Flow control (both Rx and Tx) is enabled by SW override. */
4573 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4574 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4577 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4578 ret_val = IXGBE_ERR_CONFIG;
4582 /* Set 802.3x based flow control settings. */
4583 mflcn_reg |= IXGBE_MFLCN_DPF;
4584 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4585 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4587 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4588 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4589 hw->fc.high_water[tc_num]) {
4590 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4591 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4592 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4594 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4596 * In order to prevent Tx hangs when the internal Tx
4597 * switch is enabled we must set the high water mark
4598 * to the maximum FCRTH value. This allows the Tx
4599 * switch to function even under heavy Rx workloads.
4601 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4603 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4605 /* Configure pause time (2 TCs per register) */
4606 reg = hw->fc.pause_time * 0x00010001;
4607 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4608 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4610 /* Configure flow control refresh threshold value */
4611 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4618 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4620 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4621 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4623 if (hw->mac.type != ixgbe_mac_82598EB) {
4624 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4630 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4633 uint32_t rx_buf_size;
4634 uint32_t max_high_water;
4636 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4637 struct ixgbe_hw *hw =
4638 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4639 struct ixgbe_dcb_config *dcb_config =
4640 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4642 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4649 PMD_INIT_FUNC_TRACE();
4651 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4652 tc_num = map[pfc_conf->priority];
4653 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4654 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4656 * At least reserve one Ethernet frame for watermark
4657 * high_water/low_water in kilo bytes for ixgbe
4659 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4660 if ((pfc_conf->fc.high_water > max_high_water) ||
4661 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4662 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4663 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4667 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4668 hw->fc.pause_time = pfc_conf->fc.pause_time;
4669 hw->fc.send_xon = pfc_conf->fc.send_xon;
4670 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4671 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4673 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4675 /* Not negotiated is not an error case */
4676 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4679 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4684 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4685 struct rte_eth_rss_reta_entry64 *reta_conf,
4688 uint16_t i, sp_reta_size;
4691 uint16_t idx, shift;
4692 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4695 PMD_INIT_FUNC_TRACE();
4697 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4698 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4703 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4704 if (reta_size != sp_reta_size) {
4705 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4706 "(%d) doesn't match the number hardware can supported "
4707 "(%d)", reta_size, sp_reta_size);
4711 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4712 idx = i / RTE_RETA_GROUP_SIZE;
4713 shift = i % RTE_RETA_GROUP_SIZE;
4714 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4718 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4719 if (mask == IXGBE_4_BIT_MASK)
4722 r = IXGBE_READ_REG(hw, reta_reg);
4723 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4724 if (mask & (0x1 << j))
4725 reta |= reta_conf[idx].reta[shift + j] <<
4728 reta |= r & (IXGBE_8_BIT_MASK <<
4731 IXGBE_WRITE_REG(hw, reta_reg, reta);
4738 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4739 struct rte_eth_rss_reta_entry64 *reta_conf,
4742 uint16_t i, sp_reta_size;
4745 uint16_t idx, shift;
4746 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4749 PMD_INIT_FUNC_TRACE();
4750 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4751 if (reta_size != sp_reta_size) {
4752 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4753 "(%d) doesn't match the number hardware can supported "
4754 "(%d)", reta_size, sp_reta_size);
4758 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4759 idx = i / RTE_RETA_GROUP_SIZE;
4760 shift = i % RTE_RETA_GROUP_SIZE;
4761 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4766 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4767 reta = IXGBE_READ_REG(hw, reta_reg);
4768 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4769 if (mask & (0x1 << j))
4770 reta_conf[idx].reta[shift + j] =
4771 ((reta >> (CHAR_BIT * j)) &
4780 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4781 uint32_t index, uint32_t pool)
4783 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4784 uint32_t enable_addr = 1;
4786 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4791 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4793 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4795 ixgbe_clear_rar(hw, index);
4799 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4801 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4803 ixgbe_remove_rar(dev, 0);
4805 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4809 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4811 if (strcmp(dev->device->driver->name, drv->driver.name))
4818 is_ixgbe_supported(struct rte_eth_dev *dev)
4820 return is_device_supported(dev, &rte_ixgbe_pmd);
4824 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4828 struct ixgbe_hw *hw;
4829 struct rte_eth_dev_info dev_info;
4830 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4831 struct rte_eth_dev_data *dev_data = dev->data;
4833 ixgbe_dev_info_get(dev, &dev_info);
4835 /* check that mtu is within the allowed range */
4836 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4839 /* If device is started, refuse mtu that requires the support of
4840 * scattered packets when this feature has not been enabled before.
4842 if (dev_data->dev_started && !dev_data->scattered_rx &&
4843 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4844 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4845 PMD_INIT_LOG(ERR, "Stop port first.");
4849 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4850 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4852 /* switch to jumbo mode if needed */
4853 if (frame_size > ETHER_MAX_LEN) {
4854 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4855 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4857 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4858 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4860 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4862 /* update max frame size */
4863 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4865 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4866 maxfrs &= 0x0000FFFF;
4867 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4868 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4874 * Virtual Function operations
4877 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4879 PMD_INIT_FUNC_TRACE();
4881 /* Clear interrupt mask to stop from interrupts being generated */
4882 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4884 IXGBE_WRITE_FLUSH(hw);
4888 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4890 PMD_INIT_FUNC_TRACE();
4892 /* VF enable interrupt autoclean */
4893 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4894 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4895 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4897 IXGBE_WRITE_FLUSH(hw);
4901 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4903 struct rte_eth_conf *conf = &dev->data->dev_conf;
4904 struct ixgbe_adapter *adapter =
4905 (struct ixgbe_adapter *)dev->data->dev_private;
4907 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4908 dev->data->port_id);
4911 * VF has no ability to enable/disable HW CRC
4912 * Keep the persistent behavior the same as Host PF
4914 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4915 if (!conf->rxmode.hw_strip_crc) {
4916 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4917 conf->rxmode.hw_strip_crc = 1;
4920 if (conf->rxmode.hw_strip_crc) {
4921 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4922 conf->rxmode.hw_strip_crc = 0;
4927 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4928 * allocation or vector Rx preconditions we will reset it.
4930 adapter->rx_bulk_alloc_allowed = true;
4931 adapter->rx_vec_allowed = true;
4937 ixgbevf_dev_start(struct rte_eth_dev *dev)
4939 struct ixgbe_hw *hw =
4940 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4941 uint32_t intr_vector = 0;
4942 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4943 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4947 PMD_INIT_FUNC_TRACE();
4949 hw->mac.ops.reset_hw(hw);
4950 hw->mac.get_link_status = true;
4952 /* negotiate mailbox API version to use with the PF. */
4953 ixgbevf_negotiate_api(hw);
4955 ixgbevf_dev_tx_init(dev);
4957 /* This can fail when allocating mbufs for descriptor rings */
4958 err = ixgbevf_dev_rx_init(dev);
4960 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4961 ixgbe_dev_clear_queues(dev);
4966 ixgbevf_set_vfta_all(dev, 1);
4969 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4970 ETH_VLAN_EXTEND_MASK;
4971 ixgbevf_vlan_offload_set(dev, mask);
4973 ixgbevf_dev_rxtx_start(dev);
4975 /* check and configure queue intr-vector mapping */
4976 if (dev->data->dev_conf.intr_conf.rxq != 0) {
4977 intr_vector = dev->data->nb_rx_queues;
4978 if (rte_intr_efd_enable(intr_handle, intr_vector))
4982 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4983 intr_handle->intr_vec =
4984 rte_zmalloc("intr_vec",
4985 dev->data->nb_rx_queues * sizeof(int), 0);
4986 if (intr_handle->intr_vec == NULL) {
4987 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4988 " intr_vec", dev->data->nb_rx_queues);
4992 ixgbevf_configure_msix(dev);
4994 rte_intr_enable(intr_handle);
4996 /* Re-enable interrupt for VF */
4997 ixgbevf_intr_enable(hw);
5003 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5005 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5006 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5007 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5009 PMD_INIT_FUNC_TRACE();
5011 ixgbevf_intr_disable(hw);
5013 hw->adapter_stopped = 1;
5014 ixgbe_stop_adapter(hw);
5017 * Clear what we set, but we still keep shadow_vfta to
5018 * restore after device starts
5020 ixgbevf_set_vfta_all(dev, 0);
5022 /* Clear stored conf */
5023 dev->data->scattered_rx = 0;
5025 ixgbe_dev_clear_queues(dev);
5027 /* Clean datapath event and queue/vec mapping */
5028 rte_intr_efd_disable(intr_handle);
5029 if (intr_handle->intr_vec != NULL) {
5030 rte_free(intr_handle->intr_vec);
5031 intr_handle->intr_vec = NULL;
5036 ixgbevf_dev_close(struct rte_eth_dev *dev)
5038 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5040 PMD_INIT_FUNC_TRACE();
5044 ixgbevf_dev_stop(dev);
5046 ixgbe_dev_free_queues(dev);
5049 * Remove the VF MAC address ro ensure
5050 * that the VF traffic goes to the PF
5051 * after stop, close and detach of the VF
5053 ixgbevf_remove_mac_addr(dev, 0);
5056 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5058 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5059 struct ixgbe_vfta *shadow_vfta =
5060 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5061 int i = 0, j = 0, vfta = 0, mask = 1;
5063 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5064 vfta = shadow_vfta->vfta[i];
5067 for (j = 0; j < 32; j++) {
5069 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5079 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5081 struct ixgbe_hw *hw =
5082 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5083 struct ixgbe_vfta *shadow_vfta =
5084 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5085 uint32_t vid_idx = 0;
5086 uint32_t vid_bit = 0;
5089 PMD_INIT_FUNC_TRACE();
5091 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5092 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5094 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5097 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5098 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5100 /* Save what we set and retore it after device reset */
5102 shadow_vfta->vfta[vid_idx] |= vid_bit;
5104 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5110 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5112 struct ixgbe_hw *hw =
5113 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5116 PMD_INIT_FUNC_TRACE();
5118 if (queue >= hw->mac.max_rx_queues)
5121 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5123 ctrl |= IXGBE_RXDCTL_VME;
5125 ctrl &= ~IXGBE_RXDCTL_VME;
5126 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5128 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5132 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5134 struct ixgbe_hw *hw =
5135 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5139 /* VF function only support hw strip feature, others are not support */
5140 if (mask & ETH_VLAN_STRIP_MASK) {
5141 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5143 for (i = 0; i < hw->mac.max_rx_queues; i++)
5144 ixgbevf_vlan_strip_queue_set(dev, i, on);
5149 ixgbe_vt_check(struct ixgbe_hw *hw)
5153 /* if Virtualization Technology is enabled */
5154 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5155 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5156 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5164 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5166 uint32_t vector = 0;
5168 switch (hw->mac.mc_filter_type) {
5169 case 0: /* use bits [47:36] of the address */
5170 vector = ((uc_addr->addr_bytes[4] >> 4) |
5171 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5173 case 1: /* use bits [46:35] of the address */
5174 vector = ((uc_addr->addr_bytes[4] >> 3) |
5175 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5177 case 2: /* use bits [45:34] of the address */
5178 vector = ((uc_addr->addr_bytes[4] >> 2) |
5179 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5181 case 3: /* use bits [43:32] of the address */
5182 vector = ((uc_addr->addr_bytes[4]) |
5183 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5185 default: /* Invalid mc_filter_type */
5189 /* vector can only be 12-bits or boundary will be exceeded */
5195 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5203 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5204 const uint32_t ixgbe_uta_bit_shift = 5;
5205 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5206 const uint32_t bit1 = 0x1;
5208 struct ixgbe_hw *hw =
5209 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5210 struct ixgbe_uta_info *uta_info =
5211 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5213 /* The UTA table only exists on 82599 hardware and newer */
5214 if (hw->mac.type < ixgbe_mac_82599EB)
5217 vector = ixgbe_uta_vector(hw, mac_addr);
5218 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5219 uta_shift = vector & ixgbe_uta_bit_mask;
5221 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5225 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5227 uta_info->uta_in_use++;
5228 reg_val |= (bit1 << uta_shift);
5229 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5231 uta_info->uta_in_use--;
5232 reg_val &= ~(bit1 << uta_shift);
5233 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5236 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5238 if (uta_info->uta_in_use > 0)
5239 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5240 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5242 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5248 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5251 struct ixgbe_hw *hw =
5252 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5253 struct ixgbe_uta_info *uta_info =
5254 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5256 /* The UTA table only exists on 82599 hardware and newer */
5257 if (hw->mac.type < ixgbe_mac_82599EB)
5261 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5262 uta_info->uta_shadow[i] = ~0;
5263 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5266 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5267 uta_info->uta_shadow[i] = 0;
5268 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5276 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5278 uint32_t new_val = orig_val;
5280 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5281 new_val |= IXGBE_VMOLR_AUPE;
5282 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5283 new_val |= IXGBE_VMOLR_ROMPE;
5284 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5285 new_val |= IXGBE_VMOLR_ROPE;
5286 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5287 new_val |= IXGBE_VMOLR_BAM;
5288 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5289 new_val |= IXGBE_VMOLR_MPE;
5294 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5295 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5296 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5297 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5298 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5299 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5300 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5303 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5304 struct rte_eth_mirror_conf *mirror_conf,
5305 uint8_t rule_id, uint8_t on)
5307 uint32_t mr_ctl, vlvf;
5308 uint32_t mp_lsb = 0;
5309 uint32_t mv_msb = 0;
5310 uint32_t mv_lsb = 0;
5311 uint32_t mp_msb = 0;
5314 uint64_t vlan_mask = 0;
5316 const uint8_t pool_mask_offset = 32;
5317 const uint8_t vlan_mask_offset = 32;
5318 const uint8_t dst_pool_offset = 8;
5319 const uint8_t rule_mr_offset = 4;
5320 const uint8_t mirror_rule_mask = 0x0F;
5322 struct ixgbe_mirror_info *mr_info =
5323 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5324 struct ixgbe_hw *hw =
5325 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5326 uint8_t mirror_type = 0;
5328 if (ixgbe_vt_check(hw) < 0)
5331 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5334 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5335 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5336 mirror_conf->rule_type);
5340 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5341 mirror_type |= IXGBE_MRCTL_VLME;
5342 /* Check if vlan id is valid and find conresponding VLAN ID
5345 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5346 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5347 /* search vlan id related pool vlan filter
5350 reg_index = ixgbe_find_vlvf_slot(
5352 mirror_conf->vlan.vlan_id[i],
5356 vlvf = IXGBE_READ_REG(hw,
5357 IXGBE_VLVF(reg_index));
5358 if ((vlvf & IXGBE_VLVF_VIEN) &&
5359 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5360 mirror_conf->vlan.vlan_id[i]))
5361 vlan_mask |= (1ULL << reg_index);
5368 mv_lsb = vlan_mask & 0xFFFFFFFF;
5369 mv_msb = vlan_mask >> vlan_mask_offset;
5371 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5372 mirror_conf->vlan.vlan_mask;
5373 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5374 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5375 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5376 mirror_conf->vlan.vlan_id[i];
5381 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5382 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5383 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5388 * if enable pool mirror, write related pool mask register,if disable
5389 * pool mirror, clear PFMRVM register
5391 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5392 mirror_type |= IXGBE_MRCTL_VPME;
5394 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5395 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5396 mr_info->mr_conf[rule_id].pool_mask =
5397 mirror_conf->pool_mask;
5402 mr_info->mr_conf[rule_id].pool_mask = 0;
5405 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5406 mirror_type |= IXGBE_MRCTL_UPME;
5407 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5408 mirror_type |= IXGBE_MRCTL_DPME;
5410 /* read mirror control register and recalculate it */
5411 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5414 mr_ctl |= mirror_type;
5415 mr_ctl &= mirror_rule_mask;
5416 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5418 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5421 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5422 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5424 /* write mirrror control register */
5425 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5427 /* write pool mirrror control register */
5428 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5429 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5430 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5433 /* write VLAN mirrror control register */
5434 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5435 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5436 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5444 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5447 uint32_t lsb_val = 0;
5448 uint32_t msb_val = 0;
5449 const uint8_t rule_mr_offset = 4;
5451 struct ixgbe_hw *hw =
5452 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5453 struct ixgbe_mirror_info *mr_info =
5454 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5456 if (ixgbe_vt_check(hw) < 0)
5459 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5462 memset(&mr_info->mr_conf[rule_id], 0,
5463 sizeof(struct rte_eth_mirror_conf));
5465 /* clear PFVMCTL register */
5466 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5468 /* clear pool mask register */
5469 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5470 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5472 /* clear vlan mask register */
5473 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5474 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5480 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5482 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5483 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5485 struct ixgbe_hw *hw =
5486 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5488 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5489 mask |= (1 << IXGBE_MISC_VEC_ID);
5490 RTE_SET_USED(queue_id);
5491 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5493 rte_intr_enable(intr_handle);
5499 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5502 struct ixgbe_hw *hw =
5503 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5505 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5506 mask &= ~(1 << IXGBE_MISC_VEC_ID);
5507 RTE_SET_USED(queue_id);
5508 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5514 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5516 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5517 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5519 struct ixgbe_hw *hw =
5520 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5521 struct ixgbe_interrupt *intr =
5522 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5524 if (queue_id < 16) {
5525 ixgbe_disable_intr(hw);
5526 intr->mask |= (1 << queue_id);
5527 ixgbe_enable_intr(dev);
5528 } else if (queue_id < 32) {
5529 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5530 mask &= (1 << queue_id);
5531 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5532 } else if (queue_id < 64) {
5533 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5534 mask &= (1 << (queue_id - 32));
5535 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5537 rte_intr_enable(intr_handle);
5543 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5546 struct ixgbe_hw *hw =
5547 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5548 struct ixgbe_interrupt *intr =
5549 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5551 if (queue_id < 16) {
5552 ixgbe_disable_intr(hw);
5553 intr->mask &= ~(1 << queue_id);
5554 ixgbe_enable_intr(dev);
5555 } else if (queue_id < 32) {
5556 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5557 mask &= ~(1 << queue_id);
5558 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5559 } else if (queue_id < 64) {
5560 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5561 mask &= ~(1 << (queue_id - 32));
5562 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5569 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5570 uint8_t queue, uint8_t msix_vector)
5574 if (direction == -1) {
5576 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5577 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5580 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5582 /* rx or tx cause */
5583 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5584 idx = ((16 * (queue & 1)) + (8 * direction));
5585 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5586 tmp &= ~(0xFF << idx);
5587 tmp |= (msix_vector << idx);
5588 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5593 * set the IVAR registers, mapping interrupt causes to vectors
5595 * pointer to ixgbe_hw struct
5597 * 0 for Rx, 1 for Tx, -1 for other causes
5599 * queue to map the corresponding interrupt to
5601 * the vector to map to the corresponding queue
5604 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5605 uint8_t queue, uint8_t msix_vector)
5609 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5610 if (hw->mac.type == ixgbe_mac_82598EB) {
5611 if (direction == -1)
5613 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5614 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5615 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5616 tmp |= (msix_vector << (8 * (queue & 0x3)));
5617 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5618 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5619 (hw->mac.type == ixgbe_mac_X540) ||
5620 (hw->mac.type == ixgbe_mac_X550)) {
5621 if (direction == -1) {
5623 idx = ((queue & 1) * 8);
5624 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5625 tmp &= ~(0xFF << idx);
5626 tmp |= (msix_vector << idx);
5627 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5629 /* rx or tx causes */
5630 idx = ((16 * (queue & 1)) + (8 * direction));
5631 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5632 tmp &= ~(0xFF << idx);
5633 tmp |= (msix_vector << idx);
5634 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5640 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5642 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5643 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5644 struct ixgbe_hw *hw =
5645 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5647 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5649 /* Configure VF other cause ivar */
5650 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5652 /* won't configure msix register if no mapping is done
5653 * between intr vector and event fd.
5655 if (!rte_intr_dp_is_en(intr_handle))
5658 /* Configure all RX queues of VF */
5659 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5660 /* Force all queue use vector 0,
5661 * as IXGBE_VF_MAXMSIVECOTR = 1
5663 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5664 intr_handle->intr_vec[q_idx] = vector_idx;
5669 * Sets up the hardware to properly generate MSI-X interrupts
5671 * board private structure
5674 ixgbe_configure_msix(struct rte_eth_dev *dev)
5676 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5677 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5678 struct ixgbe_hw *hw =
5679 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5680 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5681 uint32_t vec = IXGBE_MISC_VEC_ID;
5685 /* won't configure msix register if no mapping is done
5686 * between intr vector and event fd
5688 if (!rte_intr_dp_is_en(intr_handle))
5691 if (rte_intr_allow_others(intr_handle))
5692 vec = base = IXGBE_RX_VEC_START;
5694 /* setup GPIE for MSI-x mode */
5695 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5696 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5697 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5698 /* auto clearing and auto setting corresponding bits in EIMS
5699 * when MSI-X interrupt is triggered
5701 if (hw->mac.type == ixgbe_mac_82598EB) {
5702 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5704 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5705 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5707 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5709 /* Populate the IVAR table and set the ITR values to the
5710 * corresponding register.
5712 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5714 /* by default, 1:1 mapping */
5715 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5716 intr_handle->intr_vec[queue_id] = vec;
5717 if (vec < base + intr_handle->nb_efd - 1)
5721 switch (hw->mac.type) {
5722 case ixgbe_mac_82598EB:
5723 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5726 case ixgbe_mac_82599EB:
5727 case ixgbe_mac_X540:
5728 case ixgbe_mac_X550:
5729 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5734 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5735 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5737 /* set up to autoclear timer, and the vectors */
5738 mask = IXGBE_EIMS_ENABLE_MASK;
5739 mask &= ~(IXGBE_EIMS_OTHER |
5740 IXGBE_EIMS_MAILBOX |
5743 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5747 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5748 uint16_t queue_idx, uint16_t tx_rate)
5750 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5751 uint32_t rf_dec, rf_int;
5753 uint16_t link_speed = dev->data->dev_link.link_speed;
5755 if (queue_idx >= hw->mac.max_tx_queues)
5759 /* Calculate the rate factor values to set */
5760 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5761 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5762 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5764 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5765 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5766 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5767 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5773 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5774 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5777 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5778 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5779 IXGBE_MAX_JUMBO_FRAME_SIZE))
5780 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5781 IXGBE_MMW_SIZE_JUMBO_FRAME);
5783 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5784 IXGBE_MMW_SIZE_DEFAULT);
5786 /* Set RTTBCNRC of queue X */
5787 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5788 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5789 IXGBE_WRITE_FLUSH(hw);
5795 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5796 __attribute__((unused)) uint32_t index,
5797 __attribute__((unused)) uint32_t pool)
5799 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5803 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5804 * operation. Trap this case to avoid exhausting the [very limited]
5805 * set of PF resources used to store VF MAC addresses.
5807 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5809 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5811 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5812 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5813 mac_addr->addr_bytes[0],
5814 mac_addr->addr_bytes[1],
5815 mac_addr->addr_bytes[2],
5816 mac_addr->addr_bytes[3],
5817 mac_addr->addr_bytes[4],
5818 mac_addr->addr_bytes[5],
5824 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5826 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5827 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5828 struct ether_addr *mac_addr;
5833 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5834 * not support the deletion of a given MAC address.
5835 * Instead, it imposes to delete all MAC addresses, then to add again
5836 * all MAC addresses with the exception of the one to be deleted.
5838 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5841 * Add again all MAC addresses, with the exception of the deleted one
5842 * and of the permanent MAC address.
5844 for (i = 0, mac_addr = dev->data->mac_addrs;
5845 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5846 /* Skip the deleted MAC address */
5849 /* Skip NULL MAC addresses */
5850 if (is_zero_ether_addr(mac_addr))
5852 /* Skip the permanent MAC address */
5853 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5855 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5858 "Adding again MAC address "
5859 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5861 mac_addr->addr_bytes[0],
5862 mac_addr->addr_bytes[1],
5863 mac_addr->addr_bytes[2],
5864 mac_addr->addr_bytes[3],
5865 mac_addr->addr_bytes[4],
5866 mac_addr->addr_bytes[5],
5872 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5874 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5876 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5880 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5881 struct rte_eth_syn_filter *filter,
5884 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5885 struct ixgbe_filter_info *filter_info =
5886 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5890 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5893 syn_info = filter_info->syn_info;
5896 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5898 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5899 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5901 if (filter->hig_pri)
5902 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5904 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5906 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5907 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5909 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5912 filter_info->syn_info = synqf;
5913 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5914 IXGBE_WRITE_FLUSH(hw);
5919 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5920 struct rte_eth_syn_filter *filter)
5922 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5923 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5925 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5926 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5927 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5934 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5935 enum rte_filter_op filter_op,
5938 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5941 MAC_TYPE_FILTER_SUP(hw->mac.type);
5943 if (filter_op == RTE_ETH_FILTER_NOP)
5947 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5952 switch (filter_op) {
5953 case RTE_ETH_FILTER_ADD:
5954 ret = ixgbe_syn_filter_set(dev,
5955 (struct rte_eth_syn_filter *)arg,
5958 case RTE_ETH_FILTER_DELETE:
5959 ret = ixgbe_syn_filter_set(dev,
5960 (struct rte_eth_syn_filter *)arg,
5963 case RTE_ETH_FILTER_GET:
5964 ret = ixgbe_syn_filter_get(dev,
5965 (struct rte_eth_syn_filter *)arg);
5968 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
5977 static inline enum ixgbe_5tuple_protocol
5978 convert_protocol_type(uint8_t protocol_value)
5980 if (protocol_value == IPPROTO_TCP)
5981 return IXGBE_FILTER_PROTOCOL_TCP;
5982 else if (protocol_value == IPPROTO_UDP)
5983 return IXGBE_FILTER_PROTOCOL_UDP;
5984 else if (protocol_value == IPPROTO_SCTP)
5985 return IXGBE_FILTER_PROTOCOL_SCTP;
5987 return IXGBE_FILTER_PROTOCOL_NONE;
5990 /* inject a 5-tuple filter to HW */
5992 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
5993 struct ixgbe_5tuple_filter *filter)
5995 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5997 uint32_t ftqf, sdpqf;
5998 uint32_t l34timir = 0;
5999 uint8_t mask = 0xff;
6003 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6004 IXGBE_SDPQF_DSTPORT_SHIFT);
6005 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6007 ftqf = (uint32_t)(filter->filter_info.proto &
6008 IXGBE_FTQF_PROTOCOL_MASK);
6009 ftqf |= (uint32_t)((filter->filter_info.priority &
6010 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6011 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6012 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6013 if (filter->filter_info.dst_ip_mask == 0)
6014 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6015 if (filter->filter_info.src_port_mask == 0)
6016 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6017 if (filter->filter_info.dst_port_mask == 0)
6018 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6019 if (filter->filter_info.proto_mask == 0)
6020 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6021 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6022 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6023 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6025 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6026 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6027 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6028 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6030 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6031 l34timir |= (uint32_t)(filter->queue <<
6032 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6033 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6037 * add a 5tuple filter
6040 * dev: Pointer to struct rte_eth_dev.
6041 * index: the index the filter allocates.
6042 * filter: ponter to the filter that will be added.
6043 * rx_queue: the queue id the filter assigned to.
6046 * - On success, zero.
6047 * - On failure, a negative value.
6050 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6051 struct ixgbe_5tuple_filter *filter)
6053 struct ixgbe_filter_info *filter_info =
6054 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6058 * look for an unused 5tuple filter index,
6059 * and insert the filter to list.
6061 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6062 idx = i / (sizeof(uint32_t) * NBBY);
6063 shift = i % (sizeof(uint32_t) * NBBY);
6064 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6065 filter_info->fivetuple_mask[idx] |= 1 << shift;
6067 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6073 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6074 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6078 ixgbe_inject_5tuple_filter(dev, filter);
6084 * remove a 5tuple filter
6087 * dev: Pointer to struct rte_eth_dev.
6088 * filter: the pointer of the filter will be removed.
6091 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6092 struct ixgbe_5tuple_filter *filter)
6094 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6095 struct ixgbe_filter_info *filter_info =
6096 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6097 uint16_t index = filter->index;
6099 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6100 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6101 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6104 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6105 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6106 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6107 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6108 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6112 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6114 struct ixgbe_hw *hw;
6115 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6116 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6118 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6120 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6123 /* refuse mtu that requires the support of scattered packets when this
6124 * feature has not been enabled before.
6126 if (!rx_conf->enable_scatter &&
6127 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6128 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6132 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6133 * request of the version 2.0 of the mailbox API.
6134 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6135 * of the mailbox API.
6136 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6137 * prior to 3.11.33 which contains the following change:
6138 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6140 ixgbevf_rlpml_set_vf(hw, max_frame);
6142 /* update max frame size */
6143 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6147 static inline struct ixgbe_5tuple_filter *
6148 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6149 struct ixgbe_5tuple_filter_info *key)
6151 struct ixgbe_5tuple_filter *it;
6153 TAILQ_FOREACH(it, filter_list, entries) {
6154 if (memcmp(key, &it->filter_info,
6155 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6162 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6164 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6165 struct ixgbe_5tuple_filter_info *filter_info)
6167 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6168 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6169 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6172 switch (filter->dst_ip_mask) {
6174 filter_info->dst_ip_mask = 0;
6175 filter_info->dst_ip = filter->dst_ip;
6178 filter_info->dst_ip_mask = 1;
6181 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6185 switch (filter->src_ip_mask) {
6187 filter_info->src_ip_mask = 0;
6188 filter_info->src_ip = filter->src_ip;
6191 filter_info->src_ip_mask = 1;
6194 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6198 switch (filter->dst_port_mask) {
6200 filter_info->dst_port_mask = 0;
6201 filter_info->dst_port = filter->dst_port;
6204 filter_info->dst_port_mask = 1;
6207 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6211 switch (filter->src_port_mask) {
6213 filter_info->src_port_mask = 0;
6214 filter_info->src_port = filter->src_port;
6217 filter_info->src_port_mask = 1;
6220 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6224 switch (filter->proto_mask) {
6226 filter_info->proto_mask = 0;
6227 filter_info->proto =
6228 convert_protocol_type(filter->proto);
6231 filter_info->proto_mask = 1;
6234 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6238 filter_info->priority = (uint8_t)filter->priority;
6243 * add or delete a ntuple filter
6246 * dev: Pointer to struct rte_eth_dev.
6247 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6248 * add: if true, add filter, if false, remove filter
6251 * - On success, zero.
6252 * - On failure, a negative value.
6255 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6256 struct rte_eth_ntuple_filter *ntuple_filter,
6259 struct ixgbe_filter_info *filter_info =
6260 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6261 struct ixgbe_5tuple_filter_info filter_5tuple;
6262 struct ixgbe_5tuple_filter *filter;
6265 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6266 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6270 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6271 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6275 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6277 if (filter != NULL && add) {
6278 PMD_DRV_LOG(ERR, "filter exists.");
6281 if (filter == NULL && !add) {
6282 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6287 filter = rte_zmalloc("ixgbe_5tuple_filter",
6288 sizeof(struct ixgbe_5tuple_filter), 0);
6291 (void)rte_memcpy(&filter->filter_info,
6293 sizeof(struct ixgbe_5tuple_filter_info));
6294 filter->queue = ntuple_filter->queue;
6295 ret = ixgbe_add_5tuple_filter(dev, filter);
6301 ixgbe_remove_5tuple_filter(dev, filter);
6307 * get a ntuple filter
6310 * dev: Pointer to struct rte_eth_dev.
6311 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6314 * - On success, zero.
6315 * - On failure, a negative value.
6318 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6319 struct rte_eth_ntuple_filter *ntuple_filter)
6321 struct ixgbe_filter_info *filter_info =
6322 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6323 struct ixgbe_5tuple_filter_info filter_5tuple;
6324 struct ixgbe_5tuple_filter *filter;
6327 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6328 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6332 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6333 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6337 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6339 if (filter == NULL) {
6340 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6343 ntuple_filter->queue = filter->queue;
6348 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6349 * @dev: pointer to rte_eth_dev structure
6350 * @filter_op:operation will be taken.
6351 * @arg: a pointer to specific structure corresponding to the filter_op
6354 * - On success, zero.
6355 * - On failure, a negative value.
6358 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6359 enum rte_filter_op filter_op,
6362 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6365 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6367 if (filter_op == RTE_ETH_FILTER_NOP)
6371 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6376 switch (filter_op) {
6377 case RTE_ETH_FILTER_ADD:
6378 ret = ixgbe_add_del_ntuple_filter(dev,
6379 (struct rte_eth_ntuple_filter *)arg,
6382 case RTE_ETH_FILTER_DELETE:
6383 ret = ixgbe_add_del_ntuple_filter(dev,
6384 (struct rte_eth_ntuple_filter *)arg,
6387 case RTE_ETH_FILTER_GET:
6388 ret = ixgbe_get_ntuple_filter(dev,
6389 (struct rte_eth_ntuple_filter *)arg);
6392 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6400 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6401 struct rte_eth_ethertype_filter *filter,
6404 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6405 struct ixgbe_filter_info *filter_info =
6406 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6410 struct ixgbe_ethertype_filter ethertype_filter;
6412 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6415 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6416 filter->ether_type == ETHER_TYPE_IPv6) {
6417 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6418 " ethertype filter.", filter->ether_type);
6422 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6423 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6426 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6427 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6431 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6432 if (ret >= 0 && add) {
6433 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6434 filter->ether_type);
6437 if (ret < 0 && !add) {
6438 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6439 filter->ether_type);
6444 etqf = IXGBE_ETQF_FILTER_EN;
6445 etqf |= (uint32_t)filter->ether_type;
6446 etqs |= (uint32_t)((filter->queue <<
6447 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6448 IXGBE_ETQS_RX_QUEUE);
6449 etqs |= IXGBE_ETQS_QUEUE_EN;
6451 ethertype_filter.ethertype = filter->ether_type;
6452 ethertype_filter.etqf = etqf;
6453 ethertype_filter.etqs = etqs;
6454 ethertype_filter.conf = FALSE;
6455 ret = ixgbe_ethertype_filter_insert(filter_info,
6458 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6462 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6466 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6467 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6468 IXGBE_WRITE_FLUSH(hw);
6474 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6475 struct rte_eth_ethertype_filter *filter)
6477 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6478 struct ixgbe_filter_info *filter_info =
6479 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6480 uint32_t etqf, etqs;
6483 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6485 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6486 filter->ether_type);
6490 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6491 if (etqf & IXGBE_ETQF_FILTER_EN) {
6492 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6493 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6495 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6496 IXGBE_ETQS_RX_QUEUE_SHIFT;
6503 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6504 * @dev: pointer to rte_eth_dev structure
6505 * @filter_op:operation will be taken.
6506 * @arg: a pointer to specific structure corresponding to the filter_op
6509 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6510 enum rte_filter_op filter_op,
6513 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6516 MAC_TYPE_FILTER_SUP(hw->mac.type);
6518 if (filter_op == RTE_ETH_FILTER_NOP)
6522 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6527 switch (filter_op) {
6528 case RTE_ETH_FILTER_ADD:
6529 ret = ixgbe_add_del_ethertype_filter(dev,
6530 (struct rte_eth_ethertype_filter *)arg,
6533 case RTE_ETH_FILTER_DELETE:
6534 ret = ixgbe_add_del_ethertype_filter(dev,
6535 (struct rte_eth_ethertype_filter *)arg,
6538 case RTE_ETH_FILTER_GET:
6539 ret = ixgbe_get_ethertype_filter(dev,
6540 (struct rte_eth_ethertype_filter *)arg);
6543 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6551 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6552 enum rte_filter_type filter_type,
6553 enum rte_filter_op filter_op,
6558 switch (filter_type) {
6559 case RTE_ETH_FILTER_NTUPLE:
6560 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6562 case RTE_ETH_FILTER_ETHERTYPE:
6563 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6565 case RTE_ETH_FILTER_SYN:
6566 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6568 case RTE_ETH_FILTER_FDIR:
6569 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6571 case RTE_ETH_FILTER_L2_TUNNEL:
6572 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6574 case RTE_ETH_FILTER_GENERIC:
6575 if (filter_op != RTE_ETH_FILTER_GET)
6577 *(const void **)arg = &ixgbe_flow_ops;
6580 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6590 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6591 u8 **mc_addr_ptr, u32 *vmdq)
6596 mc_addr = *mc_addr_ptr;
6597 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6602 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6603 struct ether_addr *mc_addr_set,
6604 uint32_t nb_mc_addr)
6606 struct ixgbe_hw *hw;
6609 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6610 mc_addr_list = (u8 *)mc_addr_set;
6611 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6612 ixgbe_dev_addr_list_itr, TRUE);
6616 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6618 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6619 uint64_t systime_cycles;
6621 switch (hw->mac.type) {
6622 case ixgbe_mac_X550:
6623 case ixgbe_mac_X550EM_x:
6624 case ixgbe_mac_X550EM_a:
6625 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6626 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6627 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6631 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6632 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6636 return systime_cycles;
6640 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6642 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6643 uint64_t rx_tstamp_cycles;
6645 switch (hw->mac.type) {
6646 case ixgbe_mac_X550:
6647 case ixgbe_mac_X550EM_x:
6648 case ixgbe_mac_X550EM_a:
6649 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6650 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6651 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6655 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6656 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6657 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6661 return rx_tstamp_cycles;
6665 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6667 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6668 uint64_t tx_tstamp_cycles;
6670 switch (hw->mac.type) {
6671 case ixgbe_mac_X550:
6672 case ixgbe_mac_X550EM_x:
6673 case ixgbe_mac_X550EM_a:
6674 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6675 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6676 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6680 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6681 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6682 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6686 return tx_tstamp_cycles;
6690 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6692 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6693 struct ixgbe_adapter *adapter =
6694 (struct ixgbe_adapter *)dev->data->dev_private;
6695 struct rte_eth_link link;
6696 uint32_t incval = 0;
6699 /* Get current link speed. */
6700 memset(&link, 0, sizeof(link));
6701 ixgbe_dev_link_update(dev, 1);
6702 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6704 switch (link.link_speed) {
6705 case ETH_SPEED_NUM_100M:
6706 incval = IXGBE_INCVAL_100;
6707 shift = IXGBE_INCVAL_SHIFT_100;
6709 case ETH_SPEED_NUM_1G:
6710 incval = IXGBE_INCVAL_1GB;
6711 shift = IXGBE_INCVAL_SHIFT_1GB;
6713 case ETH_SPEED_NUM_10G:
6715 incval = IXGBE_INCVAL_10GB;
6716 shift = IXGBE_INCVAL_SHIFT_10GB;
6720 switch (hw->mac.type) {
6721 case ixgbe_mac_X550:
6722 case ixgbe_mac_X550EM_x:
6723 case ixgbe_mac_X550EM_a:
6724 /* Independent of link speed. */
6726 /* Cycles read will be interpreted as ns. */
6729 case ixgbe_mac_X540:
6730 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6732 case ixgbe_mac_82599EB:
6733 incval >>= IXGBE_INCVAL_SHIFT_82599;
6734 shift -= IXGBE_INCVAL_SHIFT_82599;
6735 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6736 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6739 /* Not supported. */
6743 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6744 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6745 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6747 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6748 adapter->systime_tc.cc_shift = shift;
6749 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6751 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6752 adapter->rx_tstamp_tc.cc_shift = shift;
6753 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6755 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6756 adapter->tx_tstamp_tc.cc_shift = shift;
6757 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6761 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6763 struct ixgbe_adapter *adapter =
6764 (struct ixgbe_adapter *)dev->data->dev_private;
6766 adapter->systime_tc.nsec += delta;
6767 adapter->rx_tstamp_tc.nsec += delta;
6768 adapter->tx_tstamp_tc.nsec += delta;
6774 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6777 struct ixgbe_adapter *adapter =
6778 (struct ixgbe_adapter *)dev->data->dev_private;
6780 ns = rte_timespec_to_ns(ts);
6781 /* Set the timecounters to a new value. */
6782 adapter->systime_tc.nsec = ns;
6783 adapter->rx_tstamp_tc.nsec = ns;
6784 adapter->tx_tstamp_tc.nsec = ns;
6790 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6792 uint64_t ns, systime_cycles;
6793 struct ixgbe_adapter *adapter =
6794 (struct ixgbe_adapter *)dev->data->dev_private;
6796 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6797 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6798 *ts = rte_ns_to_timespec(ns);
6804 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6806 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6810 /* Stop the timesync system time. */
6811 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6812 /* Reset the timesync system time value. */
6813 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6814 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6816 /* Enable system time for platforms where it isn't on by default. */
6817 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6818 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6819 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6821 ixgbe_start_timecounters(dev);
6823 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6824 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6826 IXGBE_ETQF_FILTER_EN |
6829 /* Enable timestamping of received PTP packets. */
6830 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6831 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6832 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6834 /* Enable timestamping of transmitted PTP packets. */
6835 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6836 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6837 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6839 IXGBE_WRITE_FLUSH(hw);
6845 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6847 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6850 /* Disable timestamping of transmitted PTP packets. */
6851 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6852 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6853 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6855 /* Disable timestamping of received PTP packets. */
6856 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6857 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6858 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6860 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6861 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6863 /* Stop incrementating the System Time registers. */
6864 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6870 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6871 struct timespec *timestamp,
6872 uint32_t flags __rte_unused)
6874 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6875 struct ixgbe_adapter *adapter =
6876 (struct ixgbe_adapter *)dev->data->dev_private;
6877 uint32_t tsync_rxctl;
6878 uint64_t rx_tstamp_cycles;
6881 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6882 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6885 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6886 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6887 *timestamp = rte_ns_to_timespec(ns);
6893 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6894 struct timespec *timestamp)
6896 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6897 struct ixgbe_adapter *adapter =
6898 (struct ixgbe_adapter *)dev->data->dev_private;
6899 uint32_t tsync_txctl;
6900 uint64_t tx_tstamp_cycles;
6903 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6904 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6907 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6908 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6909 *timestamp = rte_ns_to_timespec(ns);
6915 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6917 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6920 const struct reg_info *reg_group;
6921 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6922 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6924 while ((reg_group = reg_set[g_ind++]))
6925 count += ixgbe_regs_group_count(reg_group);
6931 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6935 const struct reg_info *reg_group;
6937 while ((reg_group = ixgbevf_regs[g_ind++]))
6938 count += ixgbe_regs_group_count(reg_group);
6944 ixgbe_get_regs(struct rte_eth_dev *dev,
6945 struct rte_dev_reg_info *regs)
6947 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6948 uint32_t *data = regs->data;
6951 const struct reg_info *reg_group;
6952 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6953 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6956 regs->length = ixgbe_get_reg_length(dev);
6957 regs->width = sizeof(uint32_t);
6961 /* Support only full register dump */
6962 if ((regs->length == 0) ||
6963 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6964 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6966 while ((reg_group = reg_set[g_ind++]))
6967 count += ixgbe_read_regs_group(dev, &data[count],
6976 ixgbevf_get_regs(struct rte_eth_dev *dev,
6977 struct rte_dev_reg_info *regs)
6979 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6980 uint32_t *data = regs->data;
6983 const struct reg_info *reg_group;
6986 regs->length = ixgbevf_get_reg_length(dev);
6987 regs->width = sizeof(uint32_t);
6991 /* Support only full register dump */
6992 if ((regs->length == 0) ||
6993 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6994 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6996 while ((reg_group = ixgbevf_regs[g_ind++]))
6997 count += ixgbe_read_regs_group(dev, &data[count],
7006 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7008 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7010 /* Return unit is byte count */
7011 return hw->eeprom.word_size * 2;
7015 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7016 struct rte_dev_eeprom_info *in_eeprom)
7018 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7019 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7020 uint16_t *data = in_eeprom->data;
7023 first = in_eeprom->offset >> 1;
7024 length = in_eeprom->length >> 1;
7025 if ((first > hw->eeprom.word_size) ||
7026 ((first + length) > hw->eeprom.word_size))
7029 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7031 return eeprom->ops.read_buffer(hw, first, length, data);
7035 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7036 struct rte_dev_eeprom_info *in_eeprom)
7038 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7039 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7040 uint16_t *data = in_eeprom->data;
7043 first = in_eeprom->offset >> 1;
7044 length = in_eeprom->length >> 1;
7045 if ((first > hw->eeprom.word_size) ||
7046 ((first + length) > hw->eeprom.word_size))
7049 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7051 return eeprom->ops.write_buffer(hw, first, length, data);
7055 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7057 case ixgbe_mac_X550:
7058 case ixgbe_mac_X550EM_x:
7059 case ixgbe_mac_X550EM_a:
7060 return ETH_RSS_RETA_SIZE_512;
7061 case ixgbe_mac_X550_vf:
7062 case ixgbe_mac_X550EM_x_vf:
7063 case ixgbe_mac_X550EM_a_vf:
7064 return ETH_RSS_RETA_SIZE_64;
7066 return ETH_RSS_RETA_SIZE_128;
7071 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7073 case ixgbe_mac_X550:
7074 case ixgbe_mac_X550EM_x:
7075 case ixgbe_mac_X550EM_a:
7076 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7077 return IXGBE_RETA(reta_idx >> 2);
7079 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7080 case ixgbe_mac_X550_vf:
7081 case ixgbe_mac_X550EM_x_vf:
7082 case ixgbe_mac_X550EM_a_vf:
7083 return IXGBE_VFRETA(reta_idx >> 2);
7085 return IXGBE_RETA(reta_idx >> 2);
7090 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7092 case ixgbe_mac_X550_vf:
7093 case ixgbe_mac_X550EM_x_vf:
7094 case ixgbe_mac_X550EM_a_vf:
7095 return IXGBE_VFMRQC;
7102 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7104 case ixgbe_mac_X550_vf:
7105 case ixgbe_mac_X550EM_x_vf:
7106 case ixgbe_mac_X550EM_a_vf:
7107 return IXGBE_VFRSSRK(i);
7109 return IXGBE_RSSRK(i);
7114 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7116 case ixgbe_mac_82599_vf:
7117 case ixgbe_mac_X540_vf:
7125 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7126 struct rte_eth_dcb_info *dcb_info)
7128 struct ixgbe_dcb_config *dcb_config =
7129 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7130 struct ixgbe_dcb_tc_config *tc;
7133 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7134 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7136 dcb_info->nb_tcs = 1;
7138 if (dcb_config->vt_mode) { /* vt is enabled*/
7139 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7140 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7141 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7142 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7143 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7144 for (j = 0; j < dcb_info->nb_tcs; j++) {
7145 dcb_info->tc_queue.tc_rxq[i][j].base =
7146 i * dcb_info->nb_tcs + j;
7147 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7148 dcb_info->tc_queue.tc_txq[i][j].base =
7149 i * dcb_info->nb_tcs + j;
7150 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7153 } else { /* vt is disabled*/
7154 struct rte_eth_dcb_rx_conf *rx_conf =
7155 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7156 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7157 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7158 if (dcb_info->nb_tcs == ETH_4_TCS) {
7159 for (i = 0; i < dcb_info->nb_tcs; i++) {
7160 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7161 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7163 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7164 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7165 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7166 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7167 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7168 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7169 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7170 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7171 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7172 for (i = 0; i < dcb_info->nb_tcs; i++) {
7173 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7174 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7176 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7177 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7178 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7179 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7180 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7181 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7182 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7183 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7184 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7185 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7186 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7187 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7188 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7189 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7190 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7191 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7194 for (i = 0; i < dcb_info->nb_tcs; i++) {
7195 tc = &dcb_config->tc_config[i];
7196 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7201 /* Update e-tag ether type */
7203 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7204 uint16_t ether_type)
7206 uint32_t etag_etype;
7208 if (hw->mac.type != ixgbe_mac_X550 &&
7209 hw->mac.type != ixgbe_mac_X550EM_x &&
7210 hw->mac.type != ixgbe_mac_X550EM_a) {
7214 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7215 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7216 etag_etype |= ether_type;
7217 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7218 IXGBE_WRITE_FLUSH(hw);
7223 /* Config l2 tunnel ether type */
7225 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7226 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7229 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7230 struct ixgbe_l2_tn_info *l2_tn_info =
7231 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7233 if (l2_tunnel == NULL)
7236 switch (l2_tunnel->l2_tunnel_type) {
7237 case RTE_L2_TUNNEL_TYPE_E_TAG:
7238 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7239 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7242 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7250 /* Enable e-tag tunnel */
7252 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7254 uint32_t etag_etype;
7256 if (hw->mac.type != ixgbe_mac_X550 &&
7257 hw->mac.type != ixgbe_mac_X550EM_x &&
7258 hw->mac.type != ixgbe_mac_X550EM_a) {
7262 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7263 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7264 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7265 IXGBE_WRITE_FLUSH(hw);
7270 /* Enable l2 tunnel */
7272 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7273 enum rte_eth_tunnel_type l2_tunnel_type)
7276 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7277 struct ixgbe_l2_tn_info *l2_tn_info =
7278 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7280 switch (l2_tunnel_type) {
7281 case RTE_L2_TUNNEL_TYPE_E_TAG:
7282 l2_tn_info->e_tag_en = TRUE;
7283 ret = ixgbe_e_tag_enable(hw);
7286 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7294 /* Disable e-tag tunnel */
7296 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7298 uint32_t etag_etype;
7300 if (hw->mac.type != ixgbe_mac_X550 &&
7301 hw->mac.type != ixgbe_mac_X550EM_x &&
7302 hw->mac.type != ixgbe_mac_X550EM_a) {
7306 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7307 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7308 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7309 IXGBE_WRITE_FLUSH(hw);
7314 /* Disable l2 tunnel */
7316 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7317 enum rte_eth_tunnel_type l2_tunnel_type)
7320 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7321 struct ixgbe_l2_tn_info *l2_tn_info =
7322 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7324 switch (l2_tunnel_type) {
7325 case RTE_L2_TUNNEL_TYPE_E_TAG:
7326 l2_tn_info->e_tag_en = FALSE;
7327 ret = ixgbe_e_tag_disable(hw);
7330 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7339 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7340 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7343 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7344 uint32_t i, rar_entries;
7345 uint32_t rar_low, rar_high;
7347 if (hw->mac.type != ixgbe_mac_X550 &&
7348 hw->mac.type != ixgbe_mac_X550EM_x &&
7349 hw->mac.type != ixgbe_mac_X550EM_a) {
7353 rar_entries = ixgbe_get_num_rx_addrs(hw);
7355 for (i = 1; i < rar_entries; i++) {
7356 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7357 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7358 if ((rar_high & IXGBE_RAH_AV) &&
7359 (rar_high & IXGBE_RAH_ADTYPE) &&
7360 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7361 l2_tunnel->tunnel_id)) {
7362 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7363 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7365 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7375 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7376 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7379 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7380 uint32_t i, rar_entries;
7381 uint32_t rar_low, rar_high;
7383 if (hw->mac.type != ixgbe_mac_X550 &&
7384 hw->mac.type != ixgbe_mac_X550EM_x &&
7385 hw->mac.type != ixgbe_mac_X550EM_a) {
7389 /* One entry for one tunnel. Try to remove potential existing entry. */
7390 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7392 rar_entries = ixgbe_get_num_rx_addrs(hw);
7394 for (i = 1; i < rar_entries; i++) {
7395 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7396 if (rar_high & IXGBE_RAH_AV) {
7399 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7400 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7401 rar_low = l2_tunnel->tunnel_id;
7403 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7404 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7410 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7411 " Please remove a rule before adding a new one.");
7415 static inline struct ixgbe_l2_tn_filter *
7416 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7417 struct ixgbe_l2_tn_key *key)
7421 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7425 return l2_tn_info->hash_map[ret];
7429 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7430 struct ixgbe_l2_tn_filter *l2_tn_filter)
7434 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7435 &l2_tn_filter->key);
7439 "Failed to insert L2 tunnel filter"
7440 " to hash table %d!",
7445 l2_tn_info->hash_map[ret] = l2_tn_filter;
7447 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7453 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7454 struct ixgbe_l2_tn_key *key)
7457 struct ixgbe_l2_tn_filter *l2_tn_filter;
7459 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7463 "No such L2 tunnel filter to delete %d!",
7468 l2_tn_filter = l2_tn_info->hash_map[ret];
7469 l2_tn_info->hash_map[ret] = NULL;
7471 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7472 rte_free(l2_tn_filter);
7477 /* Add l2 tunnel filter */
7479 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7480 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7484 struct ixgbe_l2_tn_info *l2_tn_info =
7485 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7486 struct ixgbe_l2_tn_key key;
7487 struct ixgbe_l2_tn_filter *node;
7490 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7491 key.tn_id = l2_tunnel->tunnel_id;
7493 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7497 "The L2 tunnel filter already exists!");
7501 node = rte_zmalloc("ixgbe_l2_tn",
7502 sizeof(struct ixgbe_l2_tn_filter),
7507 (void)rte_memcpy(&node->key,
7509 sizeof(struct ixgbe_l2_tn_key));
7510 node->pool = l2_tunnel->pool;
7511 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7518 switch (l2_tunnel->l2_tunnel_type) {
7519 case RTE_L2_TUNNEL_TYPE_E_TAG:
7520 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7523 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7528 if ((!restore) && (ret < 0))
7529 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7534 /* Delete l2 tunnel filter */
7536 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7537 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7540 struct ixgbe_l2_tn_info *l2_tn_info =
7541 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7542 struct ixgbe_l2_tn_key key;
7544 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7545 key.tn_id = l2_tunnel->tunnel_id;
7546 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7550 switch (l2_tunnel->l2_tunnel_type) {
7551 case RTE_L2_TUNNEL_TYPE_E_TAG:
7552 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7555 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7564 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7565 * @dev: pointer to rte_eth_dev structure
7566 * @filter_op:operation will be taken.
7567 * @arg: a pointer to specific structure corresponding to the filter_op
7570 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7571 enum rte_filter_op filter_op,
7576 if (filter_op == RTE_ETH_FILTER_NOP)
7580 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7585 switch (filter_op) {
7586 case RTE_ETH_FILTER_ADD:
7587 ret = ixgbe_dev_l2_tunnel_filter_add
7589 (struct rte_eth_l2_tunnel_conf *)arg,
7592 case RTE_ETH_FILTER_DELETE:
7593 ret = ixgbe_dev_l2_tunnel_filter_del
7595 (struct rte_eth_l2_tunnel_conf *)arg);
7598 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7606 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7610 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7612 if (hw->mac.type != ixgbe_mac_X550 &&
7613 hw->mac.type != ixgbe_mac_X550EM_x &&
7614 hw->mac.type != ixgbe_mac_X550EM_a) {
7618 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7619 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7621 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7622 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7627 /* Enable l2 tunnel forwarding */
7629 ixgbe_dev_l2_tunnel_forwarding_enable
7630 (struct rte_eth_dev *dev,
7631 enum rte_eth_tunnel_type l2_tunnel_type)
7633 struct ixgbe_l2_tn_info *l2_tn_info =
7634 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7637 switch (l2_tunnel_type) {
7638 case RTE_L2_TUNNEL_TYPE_E_TAG:
7639 l2_tn_info->e_tag_fwd_en = TRUE;
7640 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7643 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7651 /* Disable l2 tunnel forwarding */
7653 ixgbe_dev_l2_tunnel_forwarding_disable
7654 (struct rte_eth_dev *dev,
7655 enum rte_eth_tunnel_type l2_tunnel_type)
7657 struct ixgbe_l2_tn_info *l2_tn_info =
7658 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7661 switch (l2_tunnel_type) {
7662 case RTE_L2_TUNNEL_TYPE_E_TAG:
7663 l2_tn_info->e_tag_fwd_en = FALSE;
7664 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7667 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7676 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7677 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7680 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7682 uint32_t vmtir, vmvir;
7683 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7685 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7687 "VF id %u should be less than %u",
7693 if (hw->mac.type != ixgbe_mac_X550 &&
7694 hw->mac.type != ixgbe_mac_X550EM_x &&
7695 hw->mac.type != ixgbe_mac_X550EM_a) {
7700 vmtir = l2_tunnel->tunnel_id;
7704 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7706 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7707 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7709 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7710 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7715 /* Enable l2 tunnel tag insertion */
7717 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7718 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7722 switch (l2_tunnel->l2_tunnel_type) {
7723 case RTE_L2_TUNNEL_TYPE_E_TAG:
7724 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7727 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7735 /* Disable l2 tunnel tag insertion */
7737 ixgbe_dev_l2_tunnel_insertion_disable
7738 (struct rte_eth_dev *dev,
7739 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7743 switch (l2_tunnel->l2_tunnel_type) {
7744 case RTE_L2_TUNNEL_TYPE_E_TAG:
7745 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7748 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7757 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7762 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7764 if (hw->mac.type != ixgbe_mac_X550 &&
7765 hw->mac.type != ixgbe_mac_X550EM_x &&
7766 hw->mac.type != ixgbe_mac_X550EM_a) {
7770 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7772 qde |= IXGBE_QDE_STRIP_TAG;
7774 qde &= ~IXGBE_QDE_STRIP_TAG;
7775 qde &= ~IXGBE_QDE_READ;
7776 qde |= IXGBE_QDE_WRITE;
7777 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7782 /* Enable l2 tunnel tag stripping */
7784 ixgbe_dev_l2_tunnel_stripping_enable
7785 (struct rte_eth_dev *dev,
7786 enum rte_eth_tunnel_type l2_tunnel_type)
7790 switch (l2_tunnel_type) {
7791 case RTE_L2_TUNNEL_TYPE_E_TAG:
7792 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7795 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7803 /* Disable l2 tunnel tag stripping */
7805 ixgbe_dev_l2_tunnel_stripping_disable
7806 (struct rte_eth_dev *dev,
7807 enum rte_eth_tunnel_type l2_tunnel_type)
7811 switch (l2_tunnel_type) {
7812 case RTE_L2_TUNNEL_TYPE_E_TAG:
7813 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7816 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7824 /* Enable/disable l2 tunnel offload functions */
7826 ixgbe_dev_l2_tunnel_offload_set
7827 (struct rte_eth_dev *dev,
7828 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7834 if (l2_tunnel == NULL)
7838 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7840 ret = ixgbe_dev_l2_tunnel_enable(
7842 l2_tunnel->l2_tunnel_type);
7844 ret = ixgbe_dev_l2_tunnel_disable(
7846 l2_tunnel->l2_tunnel_type);
7849 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7851 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7855 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7860 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7862 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7864 l2_tunnel->l2_tunnel_type);
7866 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7868 l2_tunnel->l2_tunnel_type);
7871 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7873 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7875 l2_tunnel->l2_tunnel_type);
7877 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7879 l2_tunnel->l2_tunnel_type);
7886 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7889 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7890 IXGBE_WRITE_FLUSH(hw);
7895 /* There's only one register for VxLAN UDP port.
7896 * So, we cannot add several ports. Will update it.
7899 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7903 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7907 return ixgbe_update_vxlan_port(hw, port);
7910 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7911 * UDP port, it must have a value.
7912 * So, will reset it to the original value 0.
7915 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7920 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7922 if (cur_port != port) {
7923 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7927 return ixgbe_update_vxlan_port(hw, 0);
7930 /* Add UDP tunneling port */
7932 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7933 struct rte_eth_udp_tunnel *udp_tunnel)
7936 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7938 if (hw->mac.type != ixgbe_mac_X550 &&
7939 hw->mac.type != ixgbe_mac_X550EM_x &&
7940 hw->mac.type != ixgbe_mac_X550EM_a) {
7944 if (udp_tunnel == NULL)
7947 switch (udp_tunnel->prot_type) {
7948 case RTE_TUNNEL_TYPE_VXLAN:
7949 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7952 case RTE_TUNNEL_TYPE_GENEVE:
7953 case RTE_TUNNEL_TYPE_TEREDO:
7954 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7959 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7967 /* Remove UDP tunneling port */
7969 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7970 struct rte_eth_udp_tunnel *udp_tunnel)
7973 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7975 if (hw->mac.type != ixgbe_mac_X550 &&
7976 hw->mac.type != ixgbe_mac_X550EM_x &&
7977 hw->mac.type != ixgbe_mac_X550EM_a) {
7981 if (udp_tunnel == NULL)
7984 switch (udp_tunnel->prot_type) {
7985 case RTE_TUNNEL_TYPE_VXLAN:
7986 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7988 case RTE_TUNNEL_TYPE_GENEVE:
7989 case RTE_TUNNEL_TYPE_TEREDO:
7990 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7994 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8003 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8005 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8007 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8011 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8013 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8015 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8018 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8020 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8023 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8026 /* PF reset VF event */
8027 if (in_msg == IXGBE_PF_CONTROL_MSG)
8028 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8033 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8036 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8037 struct ixgbe_interrupt *intr =
8038 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8039 ixgbevf_intr_disable(hw);
8041 /* read-on-clear nic registers here */
8042 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8045 /* only one misc vector supported - mailbox */
8046 eicr &= IXGBE_VTEICR_MASK;
8047 if (eicr == IXGBE_MISC_VEC_ID)
8048 intr->flags |= IXGBE_FLAG_MAILBOX;
8054 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8056 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8057 struct ixgbe_interrupt *intr =
8058 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8060 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8061 ixgbevf_mbx_process(dev);
8062 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8065 ixgbevf_intr_enable(hw);
8071 ixgbevf_dev_interrupt_handler(void *param)
8073 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8075 ixgbevf_dev_interrupt_get_status(dev);
8076 ixgbevf_dev_interrupt_action(dev);
8080 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8081 * @hw: pointer to hardware structure
8083 * Stops the transmit data path and waits for the HW to internally empty
8084 * the Tx security block
8086 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8088 #define IXGBE_MAX_SECTX_POLL 40
8093 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8094 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8095 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8096 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8097 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8098 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8100 /* Use interrupt-safe sleep just in case */
8104 /* For informational purposes only */
8105 if (i >= IXGBE_MAX_SECTX_POLL)
8106 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8107 "path fully disabled. Continuing with init.");
8109 return IXGBE_SUCCESS;
8113 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8114 * @hw: pointer to hardware structure
8116 * Enables the transmit data path.
8118 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8122 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8123 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8124 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8125 IXGBE_WRITE_FLUSH(hw);
8127 return IXGBE_SUCCESS;
8130 /* restore n-tuple filter */
8132 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8134 struct ixgbe_filter_info *filter_info =
8135 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8136 struct ixgbe_5tuple_filter *node;
8138 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8139 ixgbe_inject_5tuple_filter(dev, node);
8143 /* restore ethernet type filter */
8145 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8147 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8148 struct ixgbe_filter_info *filter_info =
8149 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8152 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8153 if (filter_info->ethertype_mask & (1 << i)) {
8154 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8155 filter_info->ethertype_filters[i].etqf);
8156 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8157 filter_info->ethertype_filters[i].etqs);
8158 IXGBE_WRITE_FLUSH(hw);
8163 /* restore SYN filter */
8165 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8167 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8168 struct ixgbe_filter_info *filter_info =
8169 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8172 synqf = filter_info->syn_info;
8174 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8175 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8176 IXGBE_WRITE_FLUSH(hw);
8180 /* restore L2 tunnel filter */
8182 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8184 struct ixgbe_l2_tn_info *l2_tn_info =
8185 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8186 struct ixgbe_l2_tn_filter *node;
8187 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8189 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8190 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8191 l2_tn_conf.tunnel_id = node->key.tn_id;
8192 l2_tn_conf.pool = node->pool;
8193 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8198 ixgbe_filter_restore(struct rte_eth_dev *dev)
8200 ixgbe_ntuple_filter_restore(dev);
8201 ixgbe_ethertype_filter_restore(dev);
8202 ixgbe_syn_filter_restore(dev);
8203 ixgbe_fdir_filter_restore(dev);
8204 ixgbe_l2_tn_filter_restore(dev);
8210 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8212 struct ixgbe_l2_tn_info *l2_tn_info =
8213 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8214 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8216 if (l2_tn_info->e_tag_en)
8217 (void)ixgbe_e_tag_enable(hw);
8219 if (l2_tn_info->e_tag_fwd_en)
8220 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8222 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8225 /* remove all the n-tuple filters */
8227 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8229 struct ixgbe_filter_info *filter_info =
8230 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8231 struct ixgbe_5tuple_filter *p_5tuple;
8233 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8234 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8237 /* remove all the ether type filters */
8239 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8241 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8242 struct ixgbe_filter_info *filter_info =
8243 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8246 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8247 if (filter_info->ethertype_mask & (1 << i) &&
8248 !filter_info->ethertype_filters[i].conf) {
8249 (void)ixgbe_ethertype_filter_remove(filter_info,
8251 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8252 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8253 IXGBE_WRITE_FLUSH(hw);
8258 /* remove the SYN filter */
8260 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8262 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8263 struct ixgbe_filter_info *filter_info =
8264 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8266 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8267 filter_info->syn_info = 0;
8269 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8270 IXGBE_WRITE_FLUSH(hw);
8274 /* remove all the L2 tunnel filters */
8276 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8278 struct ixgbe_l2_tn_info *l2_tn_info =
8279 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8280 struct ixgbe_l2_tn_filter *l2_tn_filter;
8281 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8284 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8285 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8286 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8287 l2_tn_conf.pool = l2_tn_filter->pool;
8288 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8296 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8297 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8298 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8299 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8300 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8301 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");