drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63 #include <rte_hash_crc.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "base/ixgbe_api.h"
  67 #include "base/ixgbe_vf.h"
  68 #include "base/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71 #include "ixgbe_rxtx.h"
  72 #include "base/ixgbe_type.h"
  73 #include "base/ixgbe_phy.h"
  74 #include "ixgbe_regs.h"
  75
  76 #include "rte_pmd_ixgbe.h"
  77
  78 /*
  79  * High threshold controlling when to start sending XOFF frames. Must be at
  80  * least 8 bytes less than receive packet buffer size. This value is in units
  81  * of 1024 bytes.
  82  */
  83 #define IXGBE_FC_HI    0x80
  84
  85 /*
  86  * Low threshold controlling when to start sending XON frames. This value is
  87  * in units of 1024 bytes.
  88  */
  89 #define IXGBE_FC_LO    0x40
  90
  91 /* Default minimum inter-interrupt interval for EITR configuration */
  92 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  93
  94 /* Timer value included in XOFF frames. */
  95 #define IXGBE_FC_PAUSE 0x680
  96
  97 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  98 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  99 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
 100
 101 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 102 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 103 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 104
 105 /*
 106  *  Default values for RX/TX configuration
 107  */
 108 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 109 #define IXGBE_DEFAULT_RX_PTHRESH      8
 110 #define IXGBE_DEFAULT_RX_HTHRESH      8
 111 #define IXGBE_DEFAULT_RX_WTHRESH      0
 112
 113 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 114 #define IXGBE_DEFAULT_TX_PTHRESH      32
 115 #define IXGBE_DEFAULT_TX_HTHRESH      0
 116 #define IXGBE_DEFAULT_TX_WTHRESH      0
 117 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 118
 119 /* Bit shift and mask */
 120 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 121 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 122 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 123 #define IXGBE_8_BIT_MASK   UINT8_MAX
 124
 125 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 126
 127 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 128
 129 #define IXGBE_HKEY_MAX_INDEX 10
 130
 131 /* Additional timesync values. */
 132 #define NSEC_PER_SEC             1000000000L
 133 #define IXGBE_INCVAL_10GB        0x66666666
 134 #define IXGBE_INCVAL_1GB         0x40000000
 135 #define IXGBE_INCVAL_100         0x50000000
 136 #define IXGBE_INCVAL_SHIFT_10GB  28
 137 #define IXGBE_INCVAL_SHIFT_1GB   24
 138 #define IXGBE_INCVAL_SHIFT_100   21
 139 #define IXGBE_INCVAL_SHIFT_82599 7
 140 #define IXGBE_INCPER_SHIFT_82599 24
 141
 142 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 143
 144 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 145 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 146 #define DEFAULT_ETAG_ETYPE                     0x893f
 147 #define IXGBE_ETAG_ETYPE                       0x00005084
 148 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 149 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 150 #define IXGBE_RAH_ADTYPE                       0x40000000
 151 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 152 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 153 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 154 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 155 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 156 #define IXGBE_VTEICR_MASK                      0x07
 157
 158 enum ixgbevf_xcast_modes {
 159         IXGBEVF_XCAST_MODE_NONE = 0,
 160         IXGBEVF_XCAST_MODE_MULTI,
 161         IXGBEVF_XCAST_MODE_ALLMULTI,
 162 };
 163
 164 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 165 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 166
 167 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 168 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 169 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 170 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 171 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 172 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 173 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 174 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 175 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 177 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 178 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 179 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 180 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 181 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 182 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 183 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 184 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 185                                 int wait_to_complete);
 186 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 187                                 struct rte_eth_stats *stats);
 188 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_xstat *xstats, unsigned n);
 190 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 191                                   struct rte_eth_xstat *xstats, unsigned n);
 192 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 193 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 194 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 195         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 196 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 197         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 198 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 199                                              uint16_t queue_id,
 200                                              uint8_t stat_idx,
 201                                              uint8_t is_rx);
 202 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 203                                  size_t fw_size);
 204 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 205                                struct rte_eth_dev_info *dev_info);
 206 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 207 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 208                                  struct rte_eth_dev_info *dev_info);
 209 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 210
 211 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 212                 uint16_t vlan_id, int on);
 213 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 214                                enum rte_vlan_type vlan_type,
 215                                uint16_t tpid_id);
 216 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 217                 uint16_t queue, bool on);
 218 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 219                 int on);
 220 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 221 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 222 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 223 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 224 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 225
 226 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 228 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 229                                struct rte_eth_fc_conf *fc_conf);
 230 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 231                                struct rte_eth_fc_conf *fc_conf);
 232 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 233                 struct rte_eth_pfc_conf *pfc_conf);
 234 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 235                         struct rte_eth_rss_reta_entry64 *reta_conf,
 236                         uint16_t reta_size);
 237 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 238                         struct rte_eth_rss_reta_entry64 *reta_conf,
 239                         uint16_t reta_size);
 240 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 241 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 242 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 243 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 244 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 245 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 246                                       struct rte_intr_handle *handle);
 247 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 248                 void *param);
 249 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 250 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 251                 uint32_t index, uint32_t pool);
 252 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 253 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 254                                            struct ether_addr *mac_addr);
 255 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 256 static int is_ixgbe_pmd(const char *driver_name);
 257
 258 /* For Virtual Function support */
 259 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 260 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 261 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 262 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 263 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 264 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 265 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 266 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 267 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 268                 struct rte_eth_stats *stats);
 269 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 270 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 271                 uint16_t vlan_id, int on);
 272 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 273                 uint16_t queue, int on);
 274 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 275 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 276 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 277                                             uint16_t queue_id);
 278 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 279                                              uint16_t queue_id);
 280 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 281                                  uint8_t queue, uint8_t msix_vector);
 282 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 283 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 284 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 285
 286 /* For Eth VMDQ APIs support */
 287 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 288                 ether_addr * mac_addr, uint8_t on);
 289 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 290 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 291                 struct rte_eth_mirror_conf *mirror_conf,
 292                 uint8_t rule_id, uint8_t on);
 293 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 294                 uint8_t rule_id);
 295 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 296                                           uint16_t queue_id);
 297 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 298                                            uint16_t queue_id);
 299 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 300                                uint8_t queue, uint8_t msix_vector);
 301 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 302
 303 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 304                 uint16_t queue_idx, uint16_t tx_rate);
 305
 306 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 307                                  struct ether_addr *mac_addr,
 308                                  uint32_t index, uint32_t pool);
 309 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 310 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 311                                              struct ether_addr *mac_addr);
 312 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 313                         struct rte_eth_syn_filter *filter,
 314                         bool add);
 315 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 316                         struct rte_eth_syn_filter *filter);
 317 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 318                         enum rte_filter_op filter_op,
 319                         void *arg);
 320 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 321                         struct ixgbe_5tuple_filter *filter);
 322 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 323                         struct ixgbe_5tuple_filter *filter);
 324 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 325                         struct rte_eth_ntuple_filter *filter,
 326                         bool add);
 327 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 328                                 enum rte_filter_op filter_op,
 329                                 void *arg);
 330 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 331                         struct rte_eth_ntuple_filter *filter);
 332 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 333                         struct rte_eth_ethertype_filter *filter,
 334                         bool add);
 335 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 336                                 enum rte_filter_op filter_op,
 337                                 void *arg);
 338 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 339                         struct rte_eth_ethertype_filter *filter);
 340 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 341                      enum rte_filter_type filter_type,
 342                      enum rte_filter_op filter_op,
 343                      void *arg);
 344 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 345
 346 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 347                                       struct ether_addr *mc_addr_set,
 348                                       uint32_t nb_mc_addr);
 349 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 350                                    struct rte_eth_dcb_info *dcb_info);
 351
 352 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 353 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 354                             struct rte_dev_reg_info *regs);
 355 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 356 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 357                                 struct rte_dev_eeprom_info *eeprom);
 358 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 359                                 struct rte_dev_eeprom_info *eeprom);
 360
 361 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 362 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 363                                 struct rte_dev_reg_info *regs);
 364
 365 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 366 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 367 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 368                                             struct timespec *timestamp,
 369                                             uint32_t flags);
 370 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 371                                             struct timespec *timestamp);
 372 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 373 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 374                                    struct timespec *timestamp);
 375 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 376                                    const struct timespec *timestamp);
 377 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 378                                           void *param);
 379
 380 static int ixgbe_dev_l2_tunnel_eth_type_conf
 381         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 382 static int ixgbe_dev_l2_tunnel_offload_set
 383         (struct rte_eth_dev *dev,
 384          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 385          uint32_t mask,
 386          uint8_t en);
 387 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 388                                              enum rte_filter_op filter_op,
 389                                              void *arg);
 390
 391 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 392                                          struct rte_eth_udp_tunnel *udp_tunnel);
 393 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 394                                          struct rte_eth_udp_tunnel *udp_tunnel);
 395 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 396 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 397
 398 /*
 399  * Define VF Stats MACRO for Non "cleared on read" register
 400  */
 401 #define UPDATE_VF_STAT(reg, last, cur)                          \
 402 {                                                               \
 403         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 404         cur += (latest - last) & UINT_MAX;                      \
 405         last = latest;                                          \
 406 }
 407
 408 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 409 {                                                                \
 410         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 411         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 412         u64 latest = ((new_msb << 32) | new_lsb);                \
 413         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 414         last = latest;                                           \
 415 }
 416
 417 #define IXGBE_SET_HWSTRIP(h, q) do {\
 418                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 419                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 420                 (h)->bitmap[idx] |= 1 << bit;\
 421         } while (0)
 422
 423 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 424                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 425                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 426                 (h)->bitmap[idx] &= ~(1 << bit);\
 427         } while (0)
 428
 429 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 430                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 431                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 432                 (r) = (h)->bitmap[idx] >> bit & 1;\
 433         } while (0)
 434
 435 /*
 436  * The set of PCI devices this driver supports
 437  */
 438 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 492 #ifdef RTE_NIC_BYPASS
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 494 #endif
 495         { .vendor_id = 0, /* sentinel */ },
 496 };
 497
 498 /*
 499  * The set of PCI devices this driver supports (for 82599 VF)
 500  */
 501 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 504         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 505         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 506         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 507         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 508         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 509         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 510         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 511         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 512         { .vendor_id = 0, /* sentinel */ },
 513 };
 514
 515 static const struct rte_eth_desc_lim rx_desc_lim = {
 516         .nb_max = IXGBE_MAX_RING_DESC,
 517         .nb_min = IXGBE_MIN_RING_DESC,
 518         .nb_align = IXGBE_RXD_ALIGN,
 519 };
 520
 521 static const struct rte_eth_desc_lim tx_desc_lim = {
 522         .nb_max = IXGBE_MAX_RING_DESC,
 523         .nb_min = IXGBE_MIN_RING_DESC,
 524         .nb_align = IXGBE_TXD_ALIGN,
 525         .nb_seg_max = IXGBE_TX_MAX_SEG,
 526         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 527 };
 528
 529 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 530         .dev_configure        = ixgbe_dev_configure,
 531         .dev_start            = ixgbe_dev_start,
 532         .dev_stop             = ixgbe_dev_stop,
 533         .dev_set_link_up    = ixgbe_dev_set_link_up,
 534         .dev_set_link_down  = ixgbe_dev_set_link_down,
 535         .dev_close            = ixgbe_dev_close,
 536         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 537         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 538         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 539         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 540         .link_update          = ixgbe_dev_link_update,
 541         .stats_get            = ixgbe_dev_stats_get,
 542         .xstats_get           = ixgbe_dev_xstats_get,
 543         .stats_reset          = ixgbe_dev_stats_reset,
 544         .xstats_reset         = ixgbe_dev_xstats_reset,
 545         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 546         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 547         .fw_version_get       = ixgbe_fw_version_get,
 548         .dev_infos_get        = ixgbe_dev_info_get,
 549         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 550         .mtu_set              = ixgbe_dev_mtu_set,
 551         .vlan_filter_set      = ixgbe_vlan_filter_set,
 552         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 553         .vlan_offload_set     = ixgbe_vlan_offload_set,
 554         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 555         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 556         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 557         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 558         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 559         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 560         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 561         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 562         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 563         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 564         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 565         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 566         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 567         .dev_led_on           = ixgbe_dev_led_on,
 568         .dev_led_off          = ixgbe_dev_led_off,
 569         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 570         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 571         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 572         .mac_addr_add         = ixgbe_add_rar,
 573         .mac_addr_remove      = ixgbe_remove_rar,
 574         .mac_addr_set         = ixgbe_set_default_mac_addr,
 575         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 576         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 577         .mirror_rule_set      = ixgbe_mirror_rule_set,
 578         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 579         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 580         .reta_update          = ixgbe_dev_rss_reta_update,
 581         .reta_query           = ixgbe_dev_rss_reta_query,
 582 #ifdef RTE_NIC_BYPASS
 583         .bypass_init          = ixgbe_bypass_init,
 584         .bypass_state_set     = ixgbe_bypass_state_store,
 585         .bypass_state_show    = ixgbe_bypass_state_show,
 586         .bypass_event_set     = ixgbe_bypass_event_store,
 587         .bypass_event_show    = ixgbe_bypass_event_show,
 588         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 589         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 590         .bypass_ver_show      = ixgbe_bypass_ver_show,
 591         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 592 #endif /* RTE_NIC_BYPASS */
 593         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 594         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 595         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 596         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 597         .rxq_info_get         = ixgbe_rxq_info_get,
 598         .txq_info_get         = ixgbe_txq_info_get,
 599         .timesync_enable      = ixgbe_timesync_enable,
 600         .timesync_disable     = ixgbe_timesync_disable,
 601         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 602         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 603         .get_reg              = ixgbe_get_regs,
 604         .get_eeprom_length    = ixgbe_get_eeprom_length,
 605         .get_eeprom           = ixgbe_get_eeprom,
 606         .set_eeprom           = ixgbe_set_eeprom,
 607         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 608         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 609         .timesync_read_time   = ixgbe_timesync_read_time,
 610         .timesync_write_time  = ixgbe_timesync_write_time,
 611         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 612         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 613         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 614         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 615 };
 616
 617 /*
 618  * dev_ops for virtual function, bare necessities for basic vf
 619  * operation have been implemented
 620  */
 621 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 622         .dev_configure        = ixgbevf_dev_configure,
 623         .dev_start            = ixgbevf_dev_start,
 624         .dev_stop             = ixgbevf_dev_stop,
 625         .link_update          = ixgbe_dev_link_update,
 626         .stats_get            = ixgbevf_dev_stats_get,
 627         .xstats_get           = ixgbevf_dev_xstats_get,
 628         .stats_reset          = ixgbevf_dev_stats_reset,
 629         .xstats_reset         = ixgbevf_dev_stats_reset,
 630         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 631         .dev_close            = ixgbevf_dev_close,
 632         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 633         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 634         .dev_infos_get        = ixgbevf_dev_info_get,
 635         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 636         .mtu_set              = ixgbevf_dev_set_mtu,
 637         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 638         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 639         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 640         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 641         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 642         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 643         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 644         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 645         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 646         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 647         .mac_addr_add         = ixgbevf_add_mac_addr,
 648         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 649         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 650         .rxq_info_get         = ixgbe_rxq_info_get,
 651         .txq_info_get         = ixgbe_txq_info_get,
 652         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 653         .get_reg              = ixgbevf_get_regs,
 654         .reta_update          = ixgbe_dev_rss_reta_update,
 655         .reta_query           = ixgbe_dev_rss_reta_query,
 656         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 657         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 658 };
 659
 660 /* store statistics names and its offset in stats structure */
 661 struct rte_ixgbe_xstats_name_off {
 662         char name[RTE_ETH_XSTATS_NAME_SIZE];
 663         unsigned offset;
 664 };
 665
 666 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 667         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 668         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 669         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 670         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 671         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 672         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 673         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 674         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 675         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 676         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 677         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 678         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 679         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 680         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 681         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 682                 prc1023)},
 683         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 684                 prc1522)},
 685         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 686         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 687         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 688         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 689         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 690         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 691         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 692         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 693         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 694         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 695         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 696         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 697         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 698         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 699         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 700         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 701         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 702                 ptc1023)},
 703         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 704                 ptc1522)},
 705         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 706         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 707         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 708         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 709
 710         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 711                 fdirustat_add)},
 712         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 713                 fdirustat_remove)},
 714         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 715                 fdirfstat_fadd)},
 716         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 717                 fdirfstat_fremove)},
 718         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 719                 fdirmatch)},
 720         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 721                 fdirmiss)},
 722
 723         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 724         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 725         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 726                 fclast)},
 727         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 728         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 729         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 730         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 731         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 732                 fcoe_noddp)},
 733         {"rx_fcoe_no_direct_data_placement_ext_buff",
 734                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 735
 736         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 737                 lxontxc)},
 738         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 739                 lxonrxc)},
 740         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 741                 lxofftxc)},
 742         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 743                 lxoffrxc)},
 744         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 745 };
 746
 747 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 748                            sizeof(rte_ixgbe_stats_strings[0]))
 749
 750 /* MACsec statistics */
 751 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 752         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 753                 out_pkts_untagged)},
 754         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 755                 out_pkts_encrypted)},
 756         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 757                 out_pkts_protected)},
 758         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 759                 out_octets_encrypted)},
 760         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 761                 out_octets_protected)},
 762         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 763                 in_pkts_untagged)},
 764         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 765                 in_pkts_badtag)},
 766         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 767                 in_pkts_nosci)},
 768         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 769                 in_pkts_unknownsci)},
 770         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 771                 in_octets_decrypted)},
 772         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 773                 in_octets_validated)},
 774         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 775                 in_pkts_unchecked)},
 776         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 777                 in_pkts_delayed)},
 778         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 779                 in_pkts_late)},
 780         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 781                 in_pkts_ok)},
 782         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 783                 in_pkts_invalid)},
 784         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 785                 in_pkts_notvalid)},
 786         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 787                 in_pkts_unusedsa)},
 788         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 789                 in_pkts_notusingsa)},
 790 };
 791
 792 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 793                            sizeof(rte_ixgbe_macsec_strings[0]))
 794
 795 /* Per-queue statistics */
 796 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 797         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 798         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 799         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 800         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 801 };
 802
 803 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 804                            sizeof(rte_ixgbe_rxq_strings[0]))
 805 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 806
 807 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 808         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 809         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 810         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 811                 pxon2offc)},
 812 };
 813
 814 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 815                            sizeof(rte_ixgbe_txq_strings[0]))
 816 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 817
 818 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 819         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 820 };
 821
 822 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 823                 sizeof(rte_ixgbevf_stats_strings[0]))
 824
 825 /**
 826  * Atomically reads the link status information from global
 827  * structure rte_eth_dev.
 828  *
 829  * @param dev
 830  *   - Pointer to the structure rte_eth_dev to read from.
 831  *   - Pointer to the buffer to be saved with the link status.
 832  *
 833  * @return
 834  *   - On success, zero.
 835  *   - On failure, negative value.
 836  */
 837 static inline int
 838 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 839                                 struct rte_eth_link *link)
 840 {
 841         struct rte_eth_link *dst = link;
 842         struct rte_eth_link *src = &(dev->data->dev_link);
 843
 844         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 845                                         *(uint64_t *)src) == 0)
 846                 return -1;
 847
 848         return 0;
 849 }
 850
 851 /**
 852  * Atomically writes the link status information into global
 853  * structure rte_eth_dev.
 854  *
 855  * @param dev
 856  *   - Pointer to the structure rte_eth_dev to read from.
 857  *   - Pointer to the buffer to be saved with the link status.
 858  *
 859  * @return
 860  *   - On success, zero.
 861  *   - On failure, negative value.
 862  */
 863 static inline int
 864 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 865                                 struct rte_eth_link *link)
 866 {
 867         struct rte_eth_link *dst = &(dev->data->dev_link);
 868         struct rte_eth_link *src = link;
 869
 870         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 871                                         *(uint64_t *)src) == 0)
 872                 return -1;
 873
 874         return 0;
 875 }
 876
 877 /*
 878  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 879  */
 880 static inline int
 881 ixgbe_is_sfp(struct ixgbe_hw *hw)
 882 {
 883         switch (hw->phy.type) {
 884         case ixgbe_phy_sfp_avago:
 885         case ixgbe_phy_sfp_ftl:
 886         case ixgbe_phy_sfp_intel:
 887         case ixgbe_phy_sfp_unknown:
 888         case ixgbe_phy_sfp_passive_tyco:
 889         case ixgbe_phy_sfp_passive_unknown:
 890                 return 1;
 891         default:
 892                 return 0;
 893         }
 894 }
 895
 896 static inline int32_t
 897 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 898 {
 899         uint32_t ctrl_ext;
 900         int32_t status;
 901
 902         status = ixgbe_reset_hw(hw);
 903
 904         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 905         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 906         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 907         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 908         IXGBE_WRITE_FLUSH(hw);
 909
 910         return status;
 911 }
 912
 913 static inline void
 914 ixgbe_enable_intr(struct rte_eth_dev *dev)
 915 {
 916         struct ixgbe_interrupt *intr =
 917                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 918         struct ixgbe_hw *hw =
 919                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 920
 921         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 922         IXGBE_WRITE_FLUSH(hw);
 923 }
 924
 925 /*
 926  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 927  */
 928 static void
 929 ixgbe_disable_intr(struct ixgbe_hw *hw)
 930 {
 931         PMD_INIT_FUNC_TRACE();
 932
 933         if (hw->mac.type == ixgbe_mac_82598EB) {
 934                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 935         } else {
 936                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 937                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 938                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 939         }
 940         IXGBE_WRITE_FLUSH(hw);
 941 }
 942
 943 /*
 944  * This function resets queue statistics mapping registers.
 945  * From Niantic datasheet, Initialization of Statistics section:
 946  * "...if software requires the queue counters, the RQSMR and TQSM registers
 947  * must be re-programmed following a device reset.
 948  */
 949 static void
 950 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 951 {
 952         uint32_t i;
 953
 954         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 955                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 956                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 957         }
 958 }
 959
 960
 961 static int
 962 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 963                                   uint16_t queue_id,
 964                                   uint8_t stat_idx,
 965                                   uint8_t is_rx)
 966 {
 967 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 968 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 969 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 970
 971         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 972         struct ixgbe_stat_mapping_registers *stat_mappings =
 973                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 974         uint32_t qsmr_mask = 0;
 975         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 976         uint32_t q_map;
 977         uint8_t n, offset;
 978
 979         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 980                 (hw->mac.type != ixgbe_mac_X540) &&
 981                 (hw->mac.type != ixgbe_mac_X550) &&
 982                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 983                 (hw->mac.type != ixgbe_mac_X550EM_a))
 984                 return -ENOSYS;
 985
 986         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 987                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 988                      queue_id, stat_idx);
 989
 990         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 991         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 992                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 993                 return -EIO;
 994         }
 995         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 996
 997         /* Now clear any previous stat_idx set */
 998         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 999         if (!is_rx)
1000                 stat_mappings->tqsm[n] &= ~clearing_mask;
1001         else
1002                 stat_mappings->rqsmr[n] &= ~clearing_mask;
1003
1004         q_map = (uint32_t)stat_idx;
1005         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
1006         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
1007         if (!is_rx)
1008                 stat_mappings->tqsm[n] |= qsmr_mask;
1009         else
1010                 stat_mappings->rqsmr[n] |= qsmr_mask;
1011
1012         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1013                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1014                      queue_id, stat_idx);
1015         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1016                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1017
1018         /* Now write the mapping in the appropriate register */
1019         if (is_rx) {
1020                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1021                              stat_mappings->rqsmr[n], n);
1022                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1023         } else {
1024                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1025                              stat_mappings->tqsm[n], n);
1026                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1027         }
1028         return 0;
1029 }
1030
1031 static void
1032 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1033 {
1034         struct ixgbe_stat_mapping_registers *stat_mappings =
1035                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1036         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037         int i;
1038
1039         /* write whatever was in stat mapping table to the NIC */
1040         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1041                 /* rx */
1042                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1043
1044                 /* tx */
1045                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1046         }
1047 }
1048
1049 static void
1050 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1051 {
1052         uint8_t i;
1053         struct ixgbe_dcb_tc_config *tc;
1054         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1055
1056         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1057         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1058         for (i = 0; i < dcb_max_tc; i++) {
1059                 tc = &dcb_config->tc_config[i];
1060                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1061                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1062                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1063                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1064                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1065                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1066                 tc->pfc = ixgbe_dcb_pfc_disabled;
1067         }
1068
1069         /* Initialize default user to priority mapping, UPx->TC0 */
1070         tc = &dcb_config->tc_config[0];
1071         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1072         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1073         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1074                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1075                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1076         }
1077         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1078         dcb_config->pfc_mode_enable = false;
1079         dcb_config->vt_mode = true;
1080         dcb_config->round_robin_enable = false;
1081         /* support all DCB capabilities in 82599 */
1082         dcb_config->support.capabilities = 0xFF;
1083
1084         /*we only support 4 Tcs for X540, X550 */
1085         if (hw->mac.type == ixgbe_mac_X540 ||
1086                 hw->mac.type == ixgbe_mac_X550 ||
1087                 hw->mac.type == ixgbe_mac_X550EM_x ||
1088                 hw->mac.type == ixgbe_mac_X550EM_a) {
1089                 dcb_config->num_tcs.pg_tcs = 4;
1090                 dcb_config->num_tcs.pfc_tcs = 4;
1091         }
1092 }
1093
1094 /*
1095  * Ensure that all locks are released before first NVM or PHY access
1096  */
1097 static void
1098 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1099 {
1100         uint16_t mask;
1101
1102         /*
1103          * Phy lock should not fail in this early stage. If this is the case,
1104          * it is due to an improper exit of the application.
1105          * So force the release of the faulty lock. Release of common lock
1106          * is done automatically by swfw_sync function.
1107          */
1108         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1109         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1110                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1111         }
1112         ixgbe_release_swfw_semaphore(hw, mask);
1113
1114         /*
1115          * These ones are more tricky since they are common to all ports; but
1116          * swfw_sync retries last long enough (1s) to be almost sure that if
1117          * lock can not be taken it is due to an improper lock of the
1118          * semaphore.
1119          */
1120         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1121         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1122                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1123         }
1124         ixgbe_release_swfw_semaphore(hw, mask);
1125 }
1126
1127 /*
1128  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1129  * It returns 0 on success.
1130  */
1131 static int
1132 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1133 {
1134         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1135         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1136         struct ixgbe_hw *hw =
1137                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1138         struct ixgbe_vfta *shadow_vfta =
1139                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1140         struct ixgbe_hwstrip *hwstrip =
1141                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1142         struct ixgbe_dcb_config *dcb_config =
1143                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1144         struct ixgbe_filter_info *filter_info =
1145                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1146         uint32_t ctrl_ext;
1147         uint16_t csum;
1148         int diag, i;
1149
1150         PMD_INIT_FUNC_TRACE();
1151
1152         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1153         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1154         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1155         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1156
1157         /*
1158          * For secondary processes, we don't initialise any further as primary
1159          * has already done this work. Only check we don't need a different
1160          * RX and TX function.
1161          */
1162         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1163                 struct ixgbe_tx_queue *txq;
1164                 /* TX queue function in primary, set by last queue initialized
1165                  * Tx queue may not initialized by primary process
1166                  */
1167                 if (eth_dev->data->tx_queues) {
1168                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1169                         ixgbe_set_tx_function(eth_dev, txq);
1170                 } else {
1171                         /* Use default TX function if we get here */
1172                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1173                                      "Using default TX function.");
1174                 }
1175
1176                 ixgbe_set_rx_function(eth_dev);
1177
1178                 return 0;
1179         }
1180
1181         rte_eth_copy_pci_info(eth_dev, pci_dev);
1182         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1183
1184         /* Vendor and Device ID need to be set before init of shared code */
1185         hw->device_id = pci_dev->id.device_id;
1186         hw->vendor_id = pci_dev->id.vendor_id;
1187         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1188         hw->allow_unsupported_sfp = 1;
1189
1190         /* Initialize the shared code (base driver) */
1191 #ifdef RTE_NIC_BYPASS
1192         diag = ixgbe_bypass_init_shared_code(hw);
1193 #else
1194         diag = ixgbe_init_shared_code(hw);
1195 #endif /* RTE_NIC_BYPASS */
1196
1197         if (diag != IXGBE_SUCCESS) {
1198                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1199                 return -EIO;
1200         }
1201
1202         /* pick up the PCI bus settings for reporting later */
1203         ixgbe_get_bus_info(hw);
1204
1205         /* Unlock any pending hardware semaphore */
1206         ixgbe_swfw_lock_reset(hw);
1207
1208         /* Initialize DCB configuration*/
1209         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1210         ixgbe_dcb_init(hw, dcb_config);
1211         /* Get Hardware Flow Control setting */
1212         hw->fc.requested_mode = ixgbe_fc_full;
1213         hw->fc.current_mode = ixgbe_fc_full;
1214         hw->fc.pause_time = IXGBE_FC_PAUSE;
1215         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1216                 hw->fc.low_water[i] = IXGBE_FC_LO;
1217                 hw->fc.high_water[i] = IXGBE_FC_HI;
1218         }
1219         hw->fc.send_xon = 1;
1220
1221         /* Make sure we have a good EEPROM before we read from it */
1222         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1223         if (diag != IXGBE_SUCCESS) {
1224                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1225                 return -EIO;
1226         }
1227
1228 #ifdef RTE_NIC_BYPASS
1229         diag = ixgbe_bypass_init_hw(hw);
1230 #else
1231         diag = ixgbe_init_hw(hw);
1232 #endif /* RTE_NIC_BYPASS */
1233
1234         /*
1235          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1236          * is called too soon after the kernel driver unbinding/binding occurs.
1237          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1238          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1239          * also called. See ixgbe_identify_phy_82599(). The reason for the
1240          * failure is not known, and only occuts when virtualisation features
1241          * are disabled in the bios. A delay of 100ms  was found to be enough by
1242          * trial-and-error, and is doubled to be safe.
1243          */
1244         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1245                 rte_delay_ms(200);
1246                 diag = ixgbe_init_hw(hw);
1247         }
1248
1249         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1250                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1251                              "LOM.  Please be aware there may be issues associated "
1252                              "with your hardware.");
1253                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1254                              "please contact your Intel or hardware representative "
1255                              "who provided you with this hardware.");
1256         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1257                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1258         if (diag) {
1259                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1260                 return -EIO;
1261         }
1262
1263         /* Reset the hw statistics */
1264         ixgbe_dev_stats_reset(eth_dev);
1265
1266         /* disable interrupt */
1267         ixgbe_disable_intr(hw);
1268
1269         /* reset mappings for queue statistics hw counters*/
1270         ixgbe_reset_qstat_mappings(hw);
1271
1272         /* Allocate memory for storing MAC addresses */
1273         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1274                                                hw->mac.num_rar_entries, 0);
1275         if (eth_dev->data->mac_addrs == NULL) {
1276                 PMD_INIT_LOG(ERR,
1277                              "Failed to allocate %u bytes needed to store "
1278                              "MAC addresses",
1279                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1280                 return -ENOMEM;
1281         }
1282         /* Copy the permanent MAC address */
1283         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1284                         &eth_dev->data->mac_addrs[0]);
1285
1286         /* Allocate memory for storing hash filter MAC addresses */
1287         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1288                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1289         if (eth_dev->data->hash_mac_addrs == NULL) {
1290                 PMD_INIT_LOG(ERR,
1291                              "Failed to allocate %d bytes needed to store MAC addresses",
1292                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1293                 return -ENOMEM;
1294         }
1295
1296         /* initialize the vfta */
1297         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1298
1299         /* initialize the hw strip bitmap*/
1300         memset(hwstrip, 0, sizeof(*hwstrip));
1301
1302         /* initialize PF if max_vfs not zero */
1303         ixgbe_pf_host_init(eth_dev);
1304
1305         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1306         /* let hardware know driver is loaded */
1307         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1308         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1309         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1310         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1311         IXGBE_WRITE_FLUSH(hw);
1312
1313         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1314                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1315                              (int) hw->mac.type, (int) hw->phy.type,
1316                              (int) hw->phy.sfp_type);
1317         else
1318                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1319                              (int) hw->mac.type, (int) hw->phy.type);
1320
1321         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1322                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1323                      pci_dev->id.device_id);
1324
1325         rte_intr_callback_register(intr_handle,
1326                                    ixgbe_dev_interrupt_handler, eth_dev);
1327
1328         /* enable uio/vfio intr/eventfd mapping */
1329         rte_intr_enable(intr_handle);
1330
1331         /* enable support intr */
1332         ixgbe_enable_intr(eth_dev);
1333
1334         /* initialize filter info */
1335         memset(filter_info, 0,
1336                sizeof(struct ixgbe_filter_info));
1337
1338         /* initialize 5tuple filter list */
1339         TAILQ_INIT(&filter_info->fivetuple_list);
1340
1341         /* initialize flow director filter list & hash */
1342         ixgbe_fdir_filter_init(eth_dev);
1343
1344         /* initialize l2 tunnel filter list & hash */
1345         ixgbe_l2_tn_filter_init(eth_dev);
1346         return 0;
1347 }
1348
1349 static int
1350 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1351 {
1352         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1353         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1354         struct ixgbe_hw *hw;
1355
1356         PMD_INIT_FUNC_TRACE();
1357
1358         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1359                 return -EPERM;
1360
1361         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1362
1363         if (hw->adapter_stopped == 0)
1364                 ixgbe_dev_close(eth_dev);
1365
1366         eth_dev->dev_ops = NULL;
1367         eth_dev->rx_pkt_burst = NULL;
1368         eth_dev->tx_pkt_burst = NULL;
1369
1370         /* Unlock any pending hardware semaphore */
1371         ixgbe_swfw_lock_reset(hw);
1372
1373         /* disable uio intr before callback unregister */
1374         rte_intr_disable(intr_handle);
1375         rte_intr_callback_unregister(intr_handle,
1376                                      ixgbe_dev_interrupt_handler, eth_dev);
1377
1378         /* uninitialize PF if max_vfs not zero */
1379         ixgbe_pf_host_uninit(eth_dev);
1380
1381         rte_free(eth_dev->data->mac_addrs);
1382         eth_dev->data->mac_addrs = NULL;
1383
1384         rte_free(eth_dev->data->hash_mac_addrs);
1385         eth_dev->data->hash_mac_addrs = NULL;
1386
1387         /* remove all the fdir filters & hash */
1388         ixgbe_fdir_filter_uninit(eth_dev);
1389
1390         /* remove all the L2 tunnel filters & hash */
1391         ixgbe_l2_tn_filter_uninit(eth_dev);
1392
1393         /* Remove all ntuple filters of the device */
1394         ixgbe_ntuple_filter_uninit(eth_dev);
1395
1396         return 0;
1397 }
1398
1399 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1400 {
1401         struct ixgbe_filter_info *filter_info =
1402                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1403         struct ixgbe_5tuple_filter *p_5tuple;
1404
1405         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1406                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1407                              p_5tuple,
1408                              entries);
1409                 rte_free(p_5tuple);
1410         }
1411         memset(filter_info->fivetuple_mask, 0,
1412                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1413
1414         return 0;
1415 }
1416
1417 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1418 {
1419         struct ixgbe_hw_fdir_info *fdir_info =
1420                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1421         struct ixgbe_fdir_filter *fdir_filter;
1422
1423                 if (fdir_info->hash_map)
1424                 rte_free(fdir_info->hash_map);
1425         if (fdir_info->hash_handle)
1426                 rte_hash_free(fdir_info->hash_handle);
1427
1428         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1429                 TAILQ_REMOVE(&fdir_info->fdir_list,
1430                              fdir_filter,
1431                              entries);
1432                 rte_free(fdir_filter);
1433         }
1434
1435         return 0;
1436 }
1437
1438 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1439 {
1440         struct ixgbe_l2_tn_info *l2_tn_info =
1441                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1442         struct ixgbe_l2_tn_filter *l2_tn_filter;
1443
1444         if (l2_tn_info->hash_map)
1445                 rte_free(l2_tn_info->hash_map);
1446         if (l2_tn_info->hash_handle)
1447                 rte_hash_free(l2_tn_info->hash_handle);
1448
1449         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1450                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1451                              l2_tn_filter,
1452                              entries);
1453                 rte_free(l2_tn_filter);
1454         }
1455
1456         return 0;
1457 }
1458
1459 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1460 {
1461         struct ixgbe_hw_fdir_info *fdir_info =
1462                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1463         char fdir_hash_name[RTE_HASH_NAMESIZE];
1464         struct rte_hash_parameters fdir_hash_params = {
1465                 .name = fdir_hash_name,
1466                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1467                 .key_len = sizeof(union ixgbe_atr_input),
1468                 .hash_func = rte_hash_crc,
1469                 .hash_func_init_val = 0,
1470                 .socket_id = rte_socket_id(),
1471         };
1472
1473         TAILQ_INIT(&fdir_info->fdir_list);
1474         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1475                  "fdir_%s", eth_dev->data->name);
1476         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1477         if (!fdir_info->hash_handle) {
1478                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1479                 return -EINVAL;
1480         }
1481         fdir_info->hash_map = rte_zmalloc("ixgbe",
1482                                           sizeof(struct ixgbe_fdir_filter *) *
1483                                           IXGBE_MAX_FDIR_FILTER_NUM,
1484                                           0);
1485         if (!fdir_info->hash_map) {
1486                 PMD_INIT_LOG(ERR,
1487                              "Failed to allocate memory for fdir hash map!");
1488                 return -ENOMEM;
1489         }
1490         fdir_info->mask_added = FALSE;
1491
1492         return 0;
1493 }
1494
1495 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1496 {
1497         struct ixgbe_l2_tn_info *l2_tn_info =
1498                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1499         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1500         struct rte_hash_parameters l2_tn_hash_params = {
1501                 .name = l2_tn_hash_name,
1502                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1503                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1504                 .hash_func = rte_hash_crc,
1505                 .hash_func_init_val = 0,
1506                 .socket_id = rte_socket_id(),
1507         };
1508
1509         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1510         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1511                  "l2_tn_%s", eth_dev->data->name);
1512         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1513         if (!l2_tn_info->hash_handle) {
1514                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1515                 return -EINVAL;
1516         }
1517         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1518                                    sizeof(struct ixgbe_l2_tn_filter *) *
1519                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1520                                    0);
1521         if (!l2_tn_info->hash_map) {
1522                 PMD_INIT_LOG(ERR,
1523                         "Failed to allocate memory for L2 TN hash map!");
1524                 return -ENOMEM;
1525         }
1526         l2_tn_info->e_tag_en = FALSE;
1527         l2_tn_info->e_tag_fwd_en = FALSE;
1528         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1529
1530         return 0;
1531 }
1532 /*
1533  * Negotiate mailbox API version with the PF.
1534  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1535  * Then we try to negotiate starting with the most recent one.
1536  * If all negotiation attempts fail, then we will proceed with
1537  * the default one (ixgbe_mbox_api_10).
1538  */
1539 static void
1540 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1541 {
1542         int32_t i;
1543
1544         /* start with highest supported, proceed down */
1545         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1546                 ixgbe_mbox_api_12,
1547                 ixgbe_mbox_api_11,
1548                 ixgbe_mbox_api_10,
1549         };
1550
1551         for (i = 0;
1552                         i != RTE_DIM(sup_ver) &&
1553                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1554                         i++)
1555                 ;
1556 }
1557
1558 static void
1559 generate_random_mac_addr(struct ether_addr *mac_addr)
1560 {
1561         uint64_t random;
1562
1563         /* Set Organizationally Unique Identifier (OUI) prefix. */
1564         mac_addr->addr_bytes[0] = 0x00;
1565         mac_addr->addr_bytes[1] = 0x09;
1566         mac_addr->addr_bytes[2] = 0xC0;
1567         /* Force indication of locally assigned MAC address. */
1568         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1569         /* Generate the last 3 bytes of the MAC address with a random number. */
1570         random = rte_rand();
1571         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1572 }
1573
1574 /*
1575  * Virtual Function device init
1576  */
1577 static int
1578 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1579 {
1580         int diag;
1581         uint32_t tc, tcs;
1582         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1583         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1584         struct ixgbe_hw *hw =
1585                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1586         struct ixgbe_vfta *shadow_vfta =
1587                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1588         struct ixgbe_hwstrip *hwstrip =
1589                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1590         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1591
1592         PMD_INIT_FUNC_TRACE();
1593
1594         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1595         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1596         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1597
1598         /* for secondary processes, we don't initialise any further as primary
1599          * has already done this work. Only check we don't need a different
1600          * RX function
1601          */
1602         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1603                 struct ixgbe_tx_queue *txq;
1604                 /* TX queue function in primary, set by last queue initialized
1605                  * Tx queue may not initialized by primary process
1606                  */
1607                 if (eth_dev->data->tx_queues) {
1608                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1609                         ixgbe_set_tx_function(eth_dev, txq);
1610                 } else {
1611                         /* Use default TX function if we get here */
1612                         PMD_INIT_LOG(NOTICE,
1613                                      "No TX queues configured yet. Using default TX function.");
1614                 }
1615
1616                 ixgbe_set_rx_function(eth_dev);
1617
1618                 return 0;
1619         }
1620
1621         rte_eth_copy_pci_info(eth_dev, pci_dev);
1622         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1623
1624         hw->device_id = pci_dev->id.device_id;
1625         hw->vendor_id = pci_dev->id.vendor_id;
1626         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1627
1628         /* initialize the vfta */
1629         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1630
1631         /* initialize the hw strip bitmap*/
1632         memset(hwstrip, 0, sizeof(*hwstrip));
1633
1634         /* Initialize the shared code (base driver) */
1635         diag = ixgbe_init_shared_code(hw);
1636         if (diag != IXGBE_SUCCESS) {
1637                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1638                 return -EIO;
1639         }
1640
1641         /* init_mailbox_params */
1642         hw->mbx.ops.init_params(hw);
1643
1644         /* Reset the hw statistics */
1645         ixgbevf_dev_stats_reset(eth_dev);
1646
1647         /* Disable the interrupts for VF */
1648         ixgbevf_intr_disable(hw);
1649
1650         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1651         diag = hw->mac.ops.reset_hw(hw);
1652
1653         /*
1654          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1655          * the underlying PF driver has not assigned a MAC address to the VF.
1656          * In this case, assign a random MAC address.
1657          */
1658         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1659                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1660                 return diag;
1661         }
1662
1663         /* negotiate mailbox API version to use with the PF. */
1664         ixgbevf_negotiate_api(hw);
1665
1666         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1667         ixgbevf_get_queues(hw, &tcs, &tc);
1668
1669         /* Allocate memory for storing MAC addresses */
1670         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1671                                                hw->mac.num_rar_entries, 0);
1672         if (eth_dev->data->mac_addrs == NULL) {
1673                 PMD_INIT_LOG(ERR,
1674                              "Failed to allocate %u bytes needed to store "
1675                              "MAC addresses",
1676                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1677                 return -ENOMEM;
1678         }
1679
1680         /* Generate a random MAC address, if none was assigned by PF. */
1681         if (is_zero_ether_addr(perm_addr)) {
1682                 generate_random_mac_addr(perm_addr);
1683                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1684                 if (diag) {
1685                         rte_free(eth_dev->data->mac_addrs);
1686                         eth_dev->data->mac_addrs = NULL;
1687                         return diag;
1688                 }
1689                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1690                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1691                              "%02x:%02x:%02x:%02x:%02x:%02x",
1692                              perm_addr->addr_bytes[0],
1693                              perm_addr->addr_bytes[1],
1694                              perm_addr->addr_bytes[2],
1695                              perm_addr->addr_bytes[3],
1696                              perm_addr->addr_bytes[4],
1697                              perm_addr->addr_bytes[5]);
1698         }
1699
1700         /* Copy the permanent MAC address */
1701         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1702
1703         /* reset the hardware with the new settings */
1704         diag = hw->mac.ops.start_hw(hw);
1705         switch (diag) {
1706         case  0:
1707                 break;
1708
1709         default:
1710                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1711                 return -EIO;
1712         }
1713
1714         rte_intr_callback_register(intr_handle,
1715                                    ixgbevf_dev_interrupt_handler, eth_dev);
1716         rte_intr_enable(intr_handle);
1717         ixgbevf_intr_enable(hw);
1718
1719         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1720                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1721                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1722
1723         return 0;
1724 }
1725
1726 /* Virtual Function device uninit */
1727
1728 static int
1729 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1730 {
1731         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1732         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1733         struct ixgbe_hw *hw;
1734
1735         PMD_INIT_FUNC_TRACE();
1736
1737         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1738                 return -EPERM;
1739
1740         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1741
1742         if (hw->adapter_stopped == 0)
1743                 ixgbevf_dev_close(eth_dev);
1744
1745         eth_dev->dev_ops = NULL;
1746         eth_dev->rx_pkt_burst = NULL;
1747         eth_dev->tx_pkt_burst = NULL;
1748
1749         /* Disable the interrupts for VF */
1750         ixgbevf_intr_disable(hw);
1751
1752         rte_free(eth_dev->data->mac_addrs);
1753         eth_dev->data->mac_addrs = NULL;
1754
1755         rte_intr_disable(intr_handle);
1756         rte_intr_callback_unregister(intr_handle,
1757                                      ixgbevf_dev_interrupt_handler, eth_dev);
1758
1759         return 0;
1760 }
1761
1762 static struct eth_driver rte_ixgbe_pmd = {
1763         .pci_drv = {
1764                 .id_table = pci_id_ixgbe_map,
1765                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1766                 .probe = rte_eth_dev_pci_probe,
1767                 .remove = rte_eth_dev_pci_remove,
1768         },
1769         .eth_dev_init = eth_ixgbe_dev_init,
1770         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1771         .dev_private_size = sizeof(struct ixgbe_adapter),
1772 };
1773
1774 /*
1775  * virtual function driver struct
1776  */
1777 static struct eth_driver rte_ixgbevf_pmd = {
1778         .pci_drv = {
1779                 .id_table = pci_id_ixgbevf_map,
1780                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1781                 .probe = rte_eth_dev_pci_probe,
1782                 .remove = rte_eth_dev_pci_remove,
1783         },
1784         .eth_dev_init = eth_ixgbevf_dev_init,
1785         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1786         .dev_private_size = sizeof(struct ixgbe_adapter),
1787 };
1788
1789 static int
1790 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1791 {
1792         struct ixgbe_hw *hw =
1793                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1794         struct ixgbe_vfta *shadow_vfta =
1795                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1796         uint32_t vfta;
1797         uint32_t vid_idx;
1798         uint32_t vid_bit;
1799
1800         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1801         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1802         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1803         if (on)
1804                 vfta |= vid_bit;
1805         else
1806                 vfta &= ~vid_bit;
1807         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1808
1809         /* update local VFTA copy */
1810         shadow_vfta->vfta[vid_idx] = vfta;
1811
1812         return 0;
1813 }
1814
1815 static void
1816 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1817 {
1818         if (on)
1819                 ixgbe_vlan_hw_strip_enable(dev, queue);
1820         else
1821                 ixgbe_vlan_hw_strip_disable(dev, queue);
1822 }
1823
1824 static int
1825 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1826                     enum rte_vlan_type vlan_type,
1827                     uint16_t tpid)
1828 {
1829         struct ixgbe_hw *hw =
1830                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1831         int ret = 0;
1832         uint32_t reg;
1833         uint32_t qinq;
1834
1835         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1836         qinq &= IXGBE_DMATXCTL_GDV;
1837
1838         switch (vlan_type) {
1839         case ETH_VLAN_TYPE_INNER:
1840                 if (qinq) {
1841                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1842                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1843                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1844                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1845                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1846                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1847                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1848                 } else {
1849                         ret = -ENOTSUP;
1850                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1851                                     " by single VLAN");
1852                 }
1853                 break;
1854         case ETH_VLAN_TYPE_OUTER:
1855                 if (qinq) {
1856                         /* Only the high 16-bits is valid */
1857                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1858                                         IXGBE_EXVET_VET_EXT_SHIFT);
1859                 } else {
1860                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1861                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1862                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1863                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1864                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1865                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1866                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1867                 }
1868
1869                 break;
1870         default:
1871                 ret = -EINVAL;
1872                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1873                 break;
1874         }
1875
1876         return ret;
1877 }
1878
1879 void
1880 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1881 {
1882         struct ixgbe_hw *hw =
1883                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1884         uint32_t vlnctrl;
1885
1886         PMD_INIT_FUNC_TRACE();
1887
1888         /* Filter Table Disable */
1889         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1890         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1891
1892         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1893 }
1894
1895 void
1896 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1897 {
1898         struct ixgbe_hw *hw =
1899                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1900         struct ixgbe_vfta *shadow_vfta =
1901                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1902         uint32_t vlnctrl;
1903         uint16_t i;
1904
1905         PMD_INIT_FUNC_TRACE();
1906
1907         /* Filter Table Enable */
1908         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1909         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1910         vlnctrl |= IXGBE_VLNCTRL_VFE;
1911
1912         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1913
1914         /* write whatever is in local vfta copy */
1915         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1916                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1917 }
1918
1919 static void
1920 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1921 {
1922         struct ixgbe_hwstrip *hwstrip =
1923                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1924         struct ixgbe_rx_queue *rxq;
1925
1926         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1927                 return;
1928
1929         if (on)
1930                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1931         else
1932                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1933
1934         if (queue >= dev->data->nb_rx_queues)
1935                 return;
1936
1937         rxq = dev->data->rx_queues[queue];
1938
1939         if (on)
1940                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1941         else
1942                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1943 }
1944
1945 static void
1946 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1947 {
1948         struct ixgbe_hw *hw =
1949                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1950         uint32_t ctrl;
1951
1952         PMD_INIT_FUNC_TRACE();
1953
1954         if (hw->mac.type == ixgbe_mac_82598EB) {
1955                 /* No queue level support */
1956                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1957                 return;
1958         }
1959
1960         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1961         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1962         ctrl &= ~IXGBE_RXDCTL_VME;
1963         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1964
1965         /* record those setting for HW strip per queue */
1966         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1967 }
1968
1969 static void
1970 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1971 {
1972         struct ixgbe_hw *hw =
1973                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1974         uint32_t ctrl;
1975
1976         PMD_INIT_FUNC_TRACE();
1977
1978         if (hw->mac.type == ixgbe_mac_82598EB) {
1979                 /* No queue level supported */
1980                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1981                 return;
1982         }
1983
1984         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1985         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1986         ctrl |= IXGBE_RXDCTL_VME;
1987         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1988
1989         /* record those setting for HW strip per queue */
1990         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1991 }
1992
1993 void
1994 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1995 {
1996         struct ixgbe_hw *hw =
1997                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1998         uint32_t ctrl;
1999         uint16_t i;
2000         struct ixgbe_rx_queue *rxq;
2001
2002         PMD_INIT_FUNC_TRACE();
2003
2004         if (hw->mac.type == ixgbe_mac_82598EB) {
2005                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2006                 ctrl &= ~IXGBE_VLNCTRL_VME;
2007                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2008         } else {
2009                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2010                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2011                         rxq = dev->data->rx_queues[i];
2012                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2013                         ctrl &= ~IXGBE_RXDCTL_VME;
2014                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2015
2016                         /* record those setting for HW strip per queue */
2017                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2018                 }
2019         }
2020 }
2021
2022 void
2023 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2024 {
2025         struct ixgbe_hw *hw =
2026                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2027         uint32_t ctrl;
2028         uint16_t i;
2029         struct ixgbe_rx_queue *rxq;
2030
2031         PMD_INIT_FUNC_TRACE();
2032
2033         if (hw->mac.type == ixgbe_mac_82598EB) {
2034                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2035                 ctrl |= IXGBE_VLNCTRL_VME;
2036                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2037         } else {
2038                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2039                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2040                         rxq = dev->data->rx_queues[i];
2041                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2042                         ctrl |= IXGBE_RXDCTL_VME;
2043                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2044
2045                         /* record those setting for HW strip per queue */
2046                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2047                 }
2048         }
2049 }
2050
2051 static void
2052 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2053 {
2054         struct ixgbe_hw *hw =
2055                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2056         uint32_t ctrl;
2057
2058         PMD_INIT_FUNC_TRACE();
2059
2060         /* DMATXCTRL: Geric Double VLAN Disable */
2061         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2062         ctrl &= ~IXGBE_DMATXCTL_GDV;
2063         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2064
2065         /* CTRL_EXT: Global Double VLAN Disable */
2066         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2067         ctrl &= ~IXGBE_EXTENDED_VLAN;
2068         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2069
2070 }
2071
2072 static void
2073 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2074 {
2075         struct ixgbe_hw *hw =
2076                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2077         uint32_t ctrl;
2078
2079         PMD_INIT_FUNC_TRACE();
2080
2081         /* DMATXCTRL: Geric Double VLAN Enable */
2082         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2083         ctrl |= IXGBE_DMATXCTL_GDV;
2084         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2085
2086         /* CTRL_EXT: Global Double VLAN Enable */
2087         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2088         ctrl |= IXGBE_EXTENDED_VLAN;
2089         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2090
2091         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2092         if (hw->mac.type == ixgbe_mac_X550 ||
2093             hw->mac.type == ixgbe_mac_X550EM_x ||
2094             hw->mac.type == ixgbe_mac_X550EM_a) {
2095                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2096                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2097                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2098         }
2099
2100         /*
2101          * VET EXT field in the EXVET register = 0x8100 by default
2102          * So no need to change. Same to VT field of DMATXCTL register
2103          */
2104 }
2105
2106 static void
2107 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2108 {
2109         if (mask & ETH_VLAN_STRIP_MASK) {
2110                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2111                         ixgbe_vlan_hw_strip_enable_all(dev);
2112                 else
2113                         ixgbe_vlan_hw_strip_disable_all(dev);
2114         }
2115
2116         if (mask & ETH_VLAN_FILTER_MASK) {
2117                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2118                         ixgbe_vlan_hw_filter_enable(dev);
2119                 else
2120                         ixgbe_vlan_hw_filter_disable(dev);
2121         }
2122
2123         if (mask & ETH_VLAN_EXTEND_MASK) {
2124                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2125                         ixgbe_vlan_hw_extend_enable(dev);
2126                 else
2127                         ixgbe_vlan_hw_extend_disable(dev);
2128         }
2129 }
2130
2131 static void
2132 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2133 {
2134         struct ixgbe_hw *hw =
2135                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2136         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2137         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2138
2139         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2140         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2141 }
2142
2143 static int
2144 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2145 {
2146         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2147
2148         switch (nb_rx_q) {
2149         case 1:
2150         case 2:
2151                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2152                 break;
2153         case 4:
2154                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2155                 break;
2156         default:
2157                 return -EINVAL;
2158         }
2159
2160         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2161         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2162
2163         return 0;
2164 }
2165
2166 static int
2167 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2168 {
2169         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2170         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2171         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2172         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2173
2174         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2175                 /* check multi-queue mode */
2176                 switch (dev_conf->rxmode.mq_mode) {
2177                 case ETH_MQ_RX_VMDQ_DCB:
2178                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2179                         break;
2180                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2181                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2182                         PMD_INIT_LOG(ERR, "SRIOV active,"
2183                                         " unsupported mq_mode rx %d.",
2184                                         dev_conf->rxmode.mq_mode);
2185                         return -EINVAL;
2186                 case ETH_MQ_RX_RSS:
2187                 case ETH_MQ_RX_VMDQ_RSS:
2188                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2189                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2190                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2191                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2192                                                 " invalid queue number"
2193                                                 " for VMDQ RSS, allowed"
2194                                                 " value are 1, 2 or 4.");
2195                                         return -EINVAL;
2196                                 }
2197                         break;
2198                 case ETH_MQ_RX_VMDQ_ONLY:
2199                 case ETH_MQ_RX_NONE:
2200                         /* if nothing mq mode configure, use default scheme */
2201                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2202                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2203                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2204                         break;
2205                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2206                         /* SRIOV only works in VMDq enable mode */
2207                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2208                                         " wrong mq_mode rx %d.",
2209                                         dev_conf->rxmode.mq_mode);
2210                         return -EINVAL;
2211                 }
2212
2213                 switch (dev_conf->txmode.mq_mode) {
2214                 case ETH_MQ_TX_VMDQ_DCB:
2215                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2216                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2217                         break;
2218                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2219                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2220                         break;
2221                 }
2222
2223                 /* check valid queue number */
2224                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2225                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2226                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2227                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2228                                         " must be less than or equal to %d.",
2229                                         nb_rx_q, nb_tx_q,
2230                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2231                         return -EINVAL;
2232                 }
2233         } else {
2234                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2235                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2236                                           " not supported.");
2237                         return -EINVAL;
2238                 }
2239                 /* check configuration for vmdb+dcb mode */
2240                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2241                         const struct rte_eth_vmdq_dcb_conf *conf;
2242
2243                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2244                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2245                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2246                                 return -EINVAL;
2247                         }
2248                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2249                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2250                                conf->nb_queue_pools == ETH_32_POOLS)) {
2251                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2252                                                 " nb_queue_pools must be %d or %d.",
2253                                                 ETH_16_POOLS, ETH_32_POOLS);
2254                                 return -EINVAL;
2255                         }
2256                 }
2257                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2258                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2259
2260                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2261                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2262                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2263                                 return -EINVAL;
2264                         }
2265                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2266                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2267                                conf->nb_queue_pools == ETH_32_POOLS)) {
2268                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2269                                                 " nb_queue_pools != %d and"
2270                                                 " nb_queue_pools != %d.",
2271                                                 ETH_16_POOLS, ETH_32_POOLS);
2272                                 return -EINVAL;
2273                         }
2274                 }
2275
2276                 /* For DCB mode check our configuration before we go further */
2277                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2278                         const struct rte_eth_dcb_rx_conf *conf;
2279
2280                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2281                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2282                                                  IXGBE_DCB_NB_QUEUES);
2283                                 return -EINVAL;
2284                         }
2285                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2286                         if (!(conf->nb_tcs == ETH_4_TCS ||
2287                                conf->nb_tcs == ETH_8_TCS)) {
2288                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2289                                                 " and nb_tcs != %d.",
2290                                                 ETH_4_TCS, ETH_8_TCS);
2291                                 return -EINVAL;
2292                         }
2293                 }
2294
2295                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2296                         const struct rte_eth_dcb_tx_conf *conf;
2297
2298                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2299                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2300                                                  IXGBE_DCB_NB_QUEUES);
2301                                 return -EINVAL;
2302                         }
2303                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2304                         if (!(conf->nb_tcs == ETH_4_TCS ||
2305                                conf->nb_tcs == ETH_8_TCS)) {
2306                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2307                                                 " and nb_tcs != %d.",
2308                                                 ETH_4_TCS, ETH_8_TCS);
2309                                 return -EINVAL;
2310                         }
2311                 }
2312
2313                 /*
2314                  * When DCB/VT is off, maximum number of queues changes,
2315                  * except for 82598EB, which remains constant.
2316                  */
2317                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2318                                 hw->mac.type != ixgbe_mac_82598EB) {
2319                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2320                                 PMD_INIT_LOG(ERR,
2321                                              "Neither VT nor DCB are enabled, "
2322                                              "nb_tx_q > %d.",
2323                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2324                                 return -EINVAL;
2325                         }
2326                 }
2327         }
2328         return 0;
2329 }
2330
2331 static int
2332 ixgbe_dev_configure(struct rte_eth_dev *dev)
2333 {
2334         struct ixgbe_interrupt *intr =
2335                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2336         struct ixgbe_adapter *adapter =
2337                 (struct ixgbe_adapter *)dev->data->dev_private;
2338         int ret;
2339
2340         PMD_INIT_FUNC_TRACE();
2341         /* multipe queue mode checking */
2342         ret  = ixgbe_check_mq_mode(dev);
2343         if (ret != 0) {
2344                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2345                             ret);
2346                 return ret;
2347         }
2348
2349         /* set flag to update link status after init */
2350         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2351
2352         /*
2353          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2354          * allocation or vector Rx preconditions we will reset it.
2355          */
2356         adapter->rx_bulk_alloc_allowed = true;
2357         adapter->rx_vec_allowed = true;
2358
2359         return 0;
2360 }
2361
2362 static void
2363 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2364 {
2365         struct ixgbe_hw *hw =
2366                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2367         struct ixgbe_interrupt *intr =
2368                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2369         uint32_t gpie;
2370
2371         /* only set up it on X550EM_X */
2372         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2373                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2374                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2375                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2376                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2377                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2378         }
2379 }
2380
2381 /*
2382  * Configure device link speed and setup link.
2383  * It returns 0 on success.
2384  */
2385 static int
2386 ixgbe_dev_start(struct rte_eth_dev *dev)
2387 {
2388         struct ixgbe_hw *hw =
2389                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2390         struct ixgbe_vf_info *vfinfo =
2391                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2392         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2393         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2394         uint32_t intr_vector = 0;
2395         int err, link_up = 0, negotiate = 0;
2396         uint32_t speed = 0;
2397         int mask = 0;
2398         int status;
2399         uint16_t vf, idx;
2400         uint32_t *link_speeds;
2401
2402         PMD_INIT_FUNC_TRACE();
2403
2404         /* IXGBE devices don't support:
2405         *    - half duplex (checked afterwards for valid speeds)
2406         *    - fixed speed: TODO implement
2407         */
2408         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2409                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2410                              dev->data->port_id);
2411                 return -EINVAL;
2412         }
2413
2414         /* disable uio/vfio intr/eventfd mapping */
2415         rte_intr_disable(intr_handle);
2416
2417         /* stop adapter */
2418         hw->adapter_stopped = 0;
2419         ixgbe_stop_adapter(hw);
2420
2421         /* reinitialize adapter
2422          * this calls reset and start
2423          */
2424         status = ixgbe_pf_reset_hw(hw);
2425         if (status != 0)
2426                 return -1;
2427         hw->mac.ops.start_hw(hw);
2428         hw->mac.get_link_status = true;
2429
2430         /* configure PF module if SRIOV enabled */
2431         ixgbe_pf_host_configure(dev);
2432
2433         ixgbe_dev_phy_intr_setup(dev);
2434
2435         /* check and configure queue intr-vector mapping */
2436         if ((rte_intr_cap_multiple(intr_handle) ||
2437              !RTE_ETH_DEV_SRIOV(dev).active) &&
2438             dev->data->dev_conf.intr_conf.rxq != 0) {
2439                 intr_vector = dev->data->nb_rx_queues;
2440                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2441                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2442                                         IXGBE_MAX_INTR_QUEUE_NUM);
2443                         return -ENOTSUP;
2444                 }
2445                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2446                         return -1;
2447         }
2448
2449         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2450                 intr_handle->intr_vec =
2451                         rte_zmalloc("intr_vec",
2452                                     dev->data->nb_rx_queues * sizeof(int), 0);
2453                 if (intr_handle->intr_vec == NULL) {
2454                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2455                                      " intr_vec\n", dev->data->nb_rx_queues);
2456                         return -ENOMEM;
2457                 }
2458         }
2459
2460         /* confiugre msix for sleep until rx interrupt */
2461         ixgbe_configure_msix(dev);
2462
2463         /* initialize transmission unit */
2464         ixgbe_dev_tx_init(dev);
2465
2466         /* This can fail when allocating mbufs for descriptor rings */
2467         err = ixgbe_dev_rx_init(dev);
2468         if (err) {
2469                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2470                 goto error;
2471         }
2472
2473     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2474                 ETH_VLAN_EXTEND_MASK;
2475         ixgbe_vlan_offload_set(dev, mask);
2476
2477         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2478                 /* Enable vlan filtering for VMDq */
2479                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2480         }
2481
2482         /* Configure DCB hw */
2483         ixgbe_configure_dcb(dev);
2484
2485         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2486                 err = ixgbe_fdir_configure(dev);
2487                 if (err)
2488                         goto error;
2489         }
2490
2491         /* Restore vf rate limit */
2492         if (vfinfo != NULL) {
2493                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2494                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2495                                 if (vfinfo[vf].tx_rate[idx] != 0)
2496                                         rte_pmd_ixgbe_set_vf_rate_limit(
2497                                                 dev->data->port_id, vf,
2498                                                 vfinfo[vf].tx_rate[idx],
2499                                                 1 << idx);
2500         }
2501
2502         ixgbe_restore_statistics_mapping(dev);
2503
2504         err = ixgbe_dev_rxtx_start(dev);
2505         if (err < 0) {
2506                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2507                 goto error;
2508         }
2509
2510         /* Skip link setup if loopback mode is enabled for 82599. */
2511         if (hw->mac.type == ixgbe_mac_82599EB &&
2512                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2513                 goto skip_link_setup;
2514
2515         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2516                 err = hw->mac.ops.setup_sfp(hw);
2517                 if (err)
2518                         goto error;
2519         }
2520
2521         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2522                 /* Turn on the copper */
2523                 ixgbe_set_phy_power(hw, true);
2524         } else {
2525                 /* Turn on the laser */
2526                 ixgbe_enable_tx_laser(hw);
2527         }
2528
2529         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2530         if (err)
2531                 goto error;
2532         dev->data->dev_link.link_status = link_up;
2533
2534         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2535         if (err)
2536                 goto error;
2537
2538         link_speeds = &dev->data->dev_conf.link_speeds;
2539         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2540                         ETH_LINK_SPEED_10G)) {
2541                 PMD_INIT_LOG(ERR, "Invalid link setting");
2542                 goto error;
2543         }
2544
2545         speed = 0x0;
2546         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2547                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2548                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2549                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2550         } else {
2551                 if (*link_speeds & ETH_LINK_SPEED_10G)
2552                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2553                 if (*link_speeds & ETH_LINK_SPEED_1G)
2554                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2555                 if (*link_speeds & ETH_LINK_SPEED_100M)
2556                         speed |= IXGBE_LINK_SPEED_100_FULL;
2557         }
2558
2559         err = ixgbe_setup_link(hw, speed, link_up);
2560         if (err)
2561                 goto error;
2562
2563 skip_link_setup:
2564
2565         if (rte_intr_allow_others(intr_handle)) {
2566                 /* check if lsc interrupt is enabled */
2567                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2568                         ixgbe_dev_lsc_interrupt_setup(dev);
2569                 ixgbe_dev_macsec_interrupt_setup(dev);
2570         } else {
2571                 rte_intr_callback_unregister(intr_handle,
2572                                              ixgbe_dev_interrupt_handler, dev);
2573                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2574                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2575                                      " no intr multiplex\n");
2576         }
2577
2578         /* check if rxq interrupt is enabled */
2579         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2580             rte_intr_dp_is_en(intr_handle))
2581                 ixgbe_dev_rxq_interrupt_setup(dev);
2582
2583         /* enable uio/vfio intr/eventfd mapping */
2584         rte_intr_enable(intr_handle);
2585
2586         /* resume enabled intr since hw reset */
2587         ixgbe_enable_intr(dev);
2588         ixgbe_l2_tunnel_conf(dev);
2589         ixgbe_filter_restore(dev);
2590
2591         return 0;
2592
2593 error:
2594         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2595         ixgbe_dev_clear_queues(dev);
2596         return -EIO;
2597 }
2598
2599 /*
2600  * Stop device: disable rx and tx functions to allow for reconfiguring.
2601  */
2602 static void
2603 ixgbe_dev_stop(struct rte_eth_dev *dev)
2604 {
2605         struct rte_eth_link link;
2606         struct ixgbe_hw *hw =
2607                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2608         struct ixgbe_vf_info *vfinfo =
2609                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2610         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2611         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2612         int vf;
2613
2614         PMD_INIT_FUNC_TRACE();
2615
2616         /* disable interrupts */
2617         ixgbe_disable_intr(hw);
2618
2619         /* reset the NIC */
2620         ixgbe_pf_reset_hw(hw);
2621         hw->adapter_stopped = 0;
2622
2623         /* stop adapter */
2624         ixgbe_stop_adapter(hw);
2625
2626         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2627                 vfinfo[vf].clear_to_send = false;
2628
2629         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2630                 /* Turn off the copper */
2631                 ixgbe_set_phy_power(hw, false);
2632         } else {
2633                 /* Turn off the laser */
2634                 ixgbe_disable_tx_laser(hw);
2635         }
2636
2637         ixgbe_dev_clear_queues(dev);
2638
2639         /* Clear stored conf */
2640         dev->data->scattered_rx = 0;
2641         dev->data->lro = 0;
2642
2643         /* Clear recorded link status */
2644         memset(&link, 0, sizeof(link));
2645         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2646
2647         if (!rte_intr_allow_others(intr_handle))
2648                 /* resume to the default handler */
2649                 rte_intr_callback_register(intr_handle,
2650                                            ixgbe_dev_interrupt_handler,
2651                                            (void *)dev);
2652
2653         /* Clean datapath event and queue/vec mapping */
2654         rte_intr_efd_disable(intr_handle);
2655         if (intr_handle->intr_vec != NULL) {
2656                 rte_free(intr_handle->intr_vec);
2657                 intr_handle->intr_vec = NULL;
2658         }
2659 }
2660
2661 /*
2662  * Set device link up: enable tx.
2663  */
2664 static int
2665 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2666 {
2667         struct ixgbe_hw *hw =
2668                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2669         if (hw->mac.type == ixgbe_mac_82599EB) {
2670 #ifdef RTE_NIC_BYPASS
2671                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2672                         /* Not suported in bypass mode */
2673                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2674                                      "by device id 0x%x", hw->device_id);
2675                         return -ENOTSUP;
2676                 }
2677 #endif
2678         }
2679
2680         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2681                 /* Turn on the copper */
2682                 ixgbe_set_phy_power(hw, true);
2683         } else {
2684                 /* Turn on the laser */
2685                 ixgbe_enable_tx_laser(hw);
2686         }
2687
2688         return 0;
2689 }
2690
2691 /*
2692  * Set device link down: disable tx.
2693  */
2694 static int
2695 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2696 {
2697         struct ixgbe_hw *hw =
2698                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2699         if (hw->mac.type == ixgbe_mac_82599EB) {
2700 #ifdef RTE_NIC_BYPASS
2701                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2702                         /* Not suported in bypass mode */
2703                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2704                                      "by device id 0x%x", hw->device_id);
2705                         return -ENOTSUP;
2706                 }
2707 #endif
2708         }
2709
2710         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2711                 /* Turn off the copper */
2712                 ixgbe_set_phy_power(hw, false);
2713         } else {
2714                 /* Turn off the laser */
2715                 ixgbe_disable_tx_laser(hw);
2716         }
2717
2718         return 0;
2719 }
2720
2721 /*
2722  * Reest and stop device.
2723  */
2724 static void
2725 ixgbe_dev_close(struct rte_eth_dev *dev)
2726 {
2727         struct ixgbe_hw *hw =
2728                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2729
2730         PMD_INIT_FUNC_TRACE();
2731
2732         ixgbe_pf_reset_hw(hw);
2733
2734         ixgbe_dev_stop(dev);
2735         hw->adapter_stopped = 1;
2736
2737         ixgbe_dev_free_queues(dev);
2738
2739         ixgbe_disable_pcie_master(hw);
2740
2741         /* reprogram the RAR[0] in case user changed it. */
2742         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2743 }
2744
2745 static void
2746 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2747                            struct ixgbe_hw_stats *hw_stats,
2748                            struct ixgbe_macsec_stats *macsec_stats,
2749                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2750                            uint64_t *total_qprc, uint64_t *total_qprdc)
2751 {
2752         uint32_t bprc, lxon, lxoff, total;
2753         uint32_t delta_gprc = 0;
2754         unsigned i;
2755         /* Workaround for RX byte count not including CRC bytes when CRC
2756          * strip is enabled. CRC bytes are removed from counters when crc_strip
2757          * is disabled.
2758          */
2759         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2760                         IXGBE_HLREG0_RXCRCSTRP);
2761
2762         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2763         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2764         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2765         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2766
2767         for (i = 0; i < 8; i++) {
2768                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2769
2770                 /* global total per queue */
2771                 hw_stats->mpc[i] += mp;
2772                 /* Running comprehensive total for stats display */
2773                 *total_missed_rx += hw_stats->mpc[i];
2774                 if (hw->mac.type == ixgbe_mac_82598EB) {
2775                         hw_stats->rnbc[i] +=
2776                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2777                         hw_stats->pxonrxc[i] +=
2778                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2779                         hw_stats->pxoffrxc[i] +=
2780                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2781                 } else {
2782                         hw_stats->pxonrxc[i] +=
2783                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2784                         hw_stats->pxoffrxc[i] +=
2785                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2786                         hw_stats->pxon2offc[i] +=
2787                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2788                 }
2789                 hw_stats->pxontxc[i] +=
2790                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2791                 hw_stats->pxofftxc[i] +=
2792                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2793         }
2794         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2795                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2796                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2797                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2798
2799                 delta_gprc += delta_qprc;
2800
2801                 hw_stats->qprc[i] += delta_qprc;
2802                 hw_stats->qptc[i] += delta_qptc;
2803
2804                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2805                 hw_stats->qbrc[i] +=
2806                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2807                 if (crc_strip == 0)
2808                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2809
2810                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2811                 hw_stats->qbtc[i] +=
2812                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2813
2814                 hw_stats->qprdc[i] += delta_qprdc;
2815                 *total_qprdc += hw_stats->qprdc[i];
2816
2817                 *total_qprc += hw_stats->qprc[i];
2818                 *total_qbrc += hw_stats->qbrc[i];
2819         }
2820         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2821         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2822         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2823
2824         /*
2825          * An errata states that gprc actually counts good + missed packets:
2826          * Workaround to set gprc to summated queue packet receives
2827          */
2828         hw_stats->gprc = *total_qprc;
2829
2830         if (hw->mac.type != ixgbe_mac_82598EB) {
2831                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2832                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2833                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2834                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2835                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2836                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2837                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2838                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2839         } else {
2840                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2841                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2842                 /* 82598 only has a counter in the high register */
2843                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2844                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2845                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2846         }
2847         uint64_t old_tpr = hw_stats->tpr;
2848
2849         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2850         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2851
2852         if (crc_strip == 0)
2853                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2854
2855         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2856         hw_stats->gptc += delta_gptc;
2857         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2858         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2859
2860         /*
2861          * Workaround: mprc hardware is incorrectly counting
2862          * broadcasts, so for now we subtract those.
2863          */
2864         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2865         hw_stats->bprc += bprc;
2866         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2867         if (hw->mac.type == ixgbe_mac_82598EB)
2868                 hw_stats->mprc -= bprc;
2869
2870         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2871         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2872         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2873         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2874         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2875         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2876
2877         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2878         hw_stats->lxontxc += lxon;
2879         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2880         hw_stats->lxofftxc += lxoff;
2881         total = lxon + lxoff;
2882
2883         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2884         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2885         hw_stats->gptc -= total;
2886         hw_stats->mptc -= total;
2887         hw_stats->ptc64 -= total;
2888         hw_stats->gotc -= total * ETHER_MIN_LEN;
2889
2890         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2891         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2892         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2893         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2894         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2895         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2896         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2897         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2898         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2899         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2900         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2901         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2902         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2903         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2904         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2905         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2906         /* Only read FCOE on 82599 */
2907         if (hw->mac.type != ixgbe_mac_82598EB) {
2908                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2909                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2910                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2911                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2912                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2913         }
2914
2915         /* Flow Director Stats registers */
2916         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2917         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2918
2919         /* MACsec Stats registers */
2920         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
2921         macsec_stats->out_pkts_encrypted +=
2922                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
2923         macsec_stats->out_pkts_protected +=
2924                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
2925         macsec_stats->out_octets_encrypted +=
2926                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
2927         macsec_stats->out_octets_protected +=
2928                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
2929         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
2930         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
2931         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
2932         macsec_stats->in_pkts_unknownsci +=
2933                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
2934         macsec_stats->in_octets_decrypted +=
2935                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
2936         macsec_stats->in_octets_validated +=
2937                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
2938         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
2939         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
2940         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
2941         for (i = 0; i < 2; i++) {
2942                 macsec_stats->in_pkts_ok +=
2943                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
2944                 macsec_stats->in_pkts_invalid +=
2945                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
2946                 macsec_stats->in_pkts_notvalid +=
2947                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
2948         }
2949         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
2950         macsec_stats->in_pkts_notusingsa +=
2951                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
2952 }
2953
2954 /*
2955  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2956  */
2957 static void
2958 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2959 {
2960         struct ixgbe_hw *hw =
2961                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2962         struct ixgbe_hw_stats *hw_stats =
2963                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2964         struct ixgbe_macsec_stats *macsec_stats =
2965                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2966                                 dev->data->dev_private);
2967         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2968         unsigned i;
2969
2970         total_missed_rx = 0;
2971         total_qbrc = 0;
2972         total_qprc = 0;
2973         total_qprdc = 0;
2974
2975         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2976                         &total_qbrc, &total_qprc, &total_qprdc);
2977
2978         if (stats == NULL)
2979                 return;
2980
2981         /* Fill out the rte_eth_stats statistics structure */
2982         stats->ipackets = total_qprc;
2983         stats->ibytes = total_qbrc;
2984         stats->opackets = hw_stats->gptc;
2985         stats->obytes = hw_stats->gotc;
2986
2987         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2988                 stats->q_ipackets[i] = hw_stats->qprc[i];
2989                 stats->q_opackets[i] = hw_stats->qptc[i];
2990                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2991                 stats->q_obytes[i] = hw_stats->qbtc[i];
2992                 stats->q_errors[i] = hw_stats->qprdc[i];
2993         }
2994
2995         /* Rx Errors */
2996         stats->imissed  = total_missed_rx;
2997         stats->ierrors  = hw_stats->crcerrs +
2998                           hw_stats->mspdc +
2999                           hw_stats->rlec +
3000                           hw_stats->ruc +
3001                           hw_stats->roc +
3002                           hw_stats->illerrc +
3003                           hw_stats->errbc +
3004                           hw_stats->rfc +
3005                           hw_stats->fccrc +
3006                           hw_stats->fclast;
3007
3008         /* Tx Errors */
3009         stats->oerrors  = 0;
3010 }
3011
3012 static void
3013 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3014 {
3015         struct ixgbe_hw_stats *stats =
3016                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3017
3018         /* HW registers are cleared on read */
3019         ixgbe_dev_stats_get(dev, NULL);
3020
3021         /* Reset software totals */
3022         memset(stats, 0, sizeof(*stats));
3023 }
3024
3025 /* This function calculates the number of xstats based on the current config */
3026 static unsigned
3027 ixgbe_xstats_calc_num(void) {
3028         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3029                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3030                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3031 }
3032
3033 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3034         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
3035 {
3036         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3037         unsigned stat, i, count;
3038
3039         if (xstats_names != NULL) {
3040                 count = 0;
3041
3042                 /* Note: limit >= cnt_stats checked upstream
3043                  * in rte_eth_xstats_names()
3044                  */
3045
3046                 /* Extended stats from ixgbe_hw_stats */
3047                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3048                         snprintf(xstats_names[count].name,
3049                                 sizeof(xstats_names[count].name),
3050                                 "%s",
3051                                 rte_ixgbe_stats_strings[i].name);
3052                         count++;
3053                 }
3054
3055                 /* MACsec Stats */
3056                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3057                         snprintf(xstats_names[count].name,
3058                                 sizeof(xstats_names[count].name),
3059                                 "%s",
3060                                 rte_ixgbe_macsec_strings[i].name);
3061                         count++;
3062                 }
3063
3064                 /* RX Priority Stats */
3065                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3066                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3067                                 snprintf(xstats_names[count].name,
3068                                         sizeof(xstats_names[count].name),
3069                                         "rx_priority%u_%s", i,
3070                                         rte_ixgbe_rxq_strings[stat].name);
3071                                 count++;
3072                         }
3073                 }
3074
3075                 /* TX Priority Stats */
3076                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3077                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3078                                 snprintf(xstats_names[count].name,
3079                                         sizeof(xstats_names[count].name),
3080                                         "tx_priority%u_%s", i,
3081                                         rte_ixgbe_txq_strings[stat].name);
3082                                 count++;
3083                         }
3084                 }
3085         }
3086         return cnt_stats;
3087 }
3088
3089 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3090         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3091 {
3092         unsigned i;
3093
3094         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3095                 return -ENOMEM;
3096
3097         if (xstats_names != NULL)
3098                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3099                         snprintf(xstats_names[i].name,
3100                                 sizeof(xstats_names[i].name),
3101                                 "%s", rte_ixgbevf_stats_strings[i].name);
3102         return IXGBEVF_NB_XSTATS;
3103 }
3104
3105 static int
3106 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3107                                          unsigned n)
3108 {
3109         struct ixgbe_hw *hw =
3110                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3111         struct ixgbe_hw_stats *hw_stats =
3112                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3113         struct ixgbe_macsec_stats *macsec_stats =
3114                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3115                                 dev->data->dev_private);
3116         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3117         unsigned i, stat, count = 0;
3118
3119         count = ixgbe_xstats_calc_num();
3120
3121         if (n < count)
3122                 return count;
3123
3124         total_missed_rx = 0;
3125         total_qbrc = 0;
3126         total_qprc = 0;
3127         total_qprdc = 0;
3128
3129         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3130                         &total_qbrc, &total_qprc, &total_qprdc);
3131
3132         /* If this is a reset xstats is NULL, and we have cleared the
3133          * registers by reading them.
3134          */
3135         if (!xstats)
3136                 return 0;
3137
3138         /* Extended stats from ixgbe_hw_stats */
3139         count = 0;
3140         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3141                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3142                                 rte_ixgbe_stats_strings[i].offset);
3143                 xstats[count].id = count;
3144                 count++;
3145         }
3146
3147         /* MACsec Stats */
3148         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3149                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3150                                 rte_ixgbe_macsec_strings[i].offset);
3151                 xstats[count].id = count;
3152                 count++;
3153         }
3154
3155         /* RX Priority Stats */
3156         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3157                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3158                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3159                                         rte_ixgbe_rxq_strings[stat].offset +
3160                                         (sizeof(uint64_t) * i));
3161                         xstats[count].id = count;
3162                         count++;
3163                 }
3164         }
3165
3166         /* TX Priority Stats */
3167         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3168                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3169                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3170                                         rte_ixgbe_txq_strings[stat].offset +
3171                                         (sizeof(uint64_t) * i));
3172                         xstats[count].id = count;
3173                         count++;
3174                 }
3175         }
3176         return count;
3177 }
3178
3179 static void
3180 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3181 {
3182         struct ixgbe_hw_stats *stats =
3183                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3184         struct ixgbe_macsec_stats *macsec_stats =
3185                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3186                                 dev->data->dev_private);
3187
3188         unsigned count = ixgbe_xstats_calc_num();
3189
3190         /* HW registers are cleared on read */
3191         ixgbe_dev_xstats_get(dev, NULL, count);
3192
3193         /* Reset software totals */
3194         memset(stats, 0, sizeof(*stats));
3195         memset(macsec_stats, 0, sizeof(*macsec_stats));
3196 }
3197
3198 static void
3199 ixgbevf_update_stats(struct rte_eth_dev *dev)
3200 {
3201         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3202         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3203                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3204
3205         /* Good Rx packet, include VF loopback */
3206         UPDATE_VF_STAT(IXGBE_VFGPRC,
3207             hw_stats->last_vfgprc, hw_stats->vfgprc);
3208
3209         /* Good Rx octets, include VF loopback */
3210         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3211             hw_stats->last_vfgorc, hw_stats->vfgorc);
3212
3213         /* Good Tx packet, include VF loopback */
3214         UPDATE_VF_STAT(IXGBE_VFGPTC,
3215             hw_stats->last_vfgptc, hw_stats->vfgptc);
3216
3217         /* Good Tx octets, include VF loopback */
3218         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3219             hw_stats->last_vfgotc, hw_stats->vfgotc);
3220
3221         /* Rx Multicst Packet */
3222         UPDATE_VF_STAT(IXGBE_VFMPRC,
3223             hw_stats->last_vfmprc, hw_stats->vfmprc);
3224 }
3225
3226 static int
3227 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3228                        unsigned n)
3229 {
3230         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3231                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3232         unsigned i;
3233
3234         if (n < IXGBEVF_NB_XSTATS)
3235                 return IXGBEVF_NB_XSTATS;
3236
3237         ixgbevf_update_stats(dev);
3238
3239         if (!xstats)
3240                 return 0;
3241
3242         /* Extended stats */
3243         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3244                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3245                         rte_ixgbevf_stats_strings[i].offset);
3246         }
3247
3248         return IXGBEVF_NB_XSTATS;
3249 }
3250
3251 static void
3252 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3253 {
3254         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3255                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3256
3257         ixgbevf_update_stats(dev);
3258
3259         if (stats == NULL)
3260                 return;
3261
3262         stats->ipackets = hw_stats->vfgprc;
3263         stats->ibytes = hw_stats->vfgorc;
3264         stats->opackets = hw_stats->vfgptc;
3265         stats->obytes = hw_stats->vfgotc;
3266 }
3267
3268 static void
3269 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3270 {
3271         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3272                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3273
3274         /* Sync HW register to the last stats */
3275         ixgbevf_dev_stats_get(dev, NULL);
3276
3277         /* reset HW current stats*/
3278         hw_stats->vfgprc = 0;
3279         hw_stats->vfgorc = 0;
3280         hw_stats->vfgptc = 0;
3281         hw_stats->vfgotc = 0;
3282 }
3283
3284 static int
3285 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3286 {
3287         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3288         u16 eeprom_verh, eeprom_verl;
3289         u32 etrack_id;
3290         int ret;
3291
3292         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3293         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3294
3295         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3296         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3297
3298         ret += 1; /* add the size of '\0' */
3299         if (fw_size < (u32)ret)
3300                 return ret;
3301         else
3302                 return 0;
3303 }
3304
3305 static void
3306 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3307 {
3308         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3309         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3310         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3311
3312         dev_info->pci_dev = pci_dev;
3313         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3314         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3315         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3316                 /*
3317                  * When DCB/VT is off, maximum number of queues changes,
3318                  * except for 82598EB, which remains constant.
3319                  */
3320                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3321                                 hw->mac.type != ixgbe_mac_82598EB)
3322                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3323         }
3324         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3325         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3326         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3327         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3328         dev_info->max_vfs = pci_dev->max_vfs;
3329         if (hw->mac.type == ixgbe_mac_82598EB)
3330                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3331         else
3332                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3333         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3334         dev_info->rx_offload_capa =
3335                 DEV_RX_OFFLOAD_VLAN_STRIP |
3336                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3337                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3338                 DEV_RX_OFFLOAD_TCP_CKSUM;
3339
3340         /*
3341          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3342          * mode.
3343          */
3344         if ((hw->mac.type == ixgbe_mac_82599EB ||
3345              hw->mac.type == ixgbe_mac_X540) &&
3346             !RTE_ETH_DEV_SRIOV(dev).active)
3347                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3348
3349         if (hw->mac.type == ixgbe_mac_82599EB ||
3350             hw->mac.type == ixgbe_mac_X540)
3351                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3352
3353         if (hw->mac.type == ixgbe_mac_X550 ||
3354             hw->mac.type == ixgbe_mac_X550EM_x ||
3355             hw->mac.type == ixgbe_mac_X550EM_a)
3356                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3357
3358         dev_info->tx_offload_capa =
3359                 DEV_TX_OFFLOAD_VLAN_INSERT |
3360                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3361                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3362                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3363                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3364                 DEV_TX_OFFLOAD_TCP_TSO;
3365
3366         if (hw->mac.type == ixgbe_mac_82599EB ||
3367             hw->mac.type == ixgbe_mac_X540)
3368                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3369
3370         if (hw->mac.type == ixgbe_mac_X550 ||
3371             hw->mac.type == ixgbe_mac_X550EM_x ||
3372             hw->mac.type == ixgbe_mac_X550EM_a)
3373                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3374
3375         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3376                 .rx_thresh = {
3377                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3378                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3379                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3380                 },
3381                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3382                 .rx_drop_en = 0,
3383         };
3384
3385         dev_info->default_txconf = (struct rte_eth_txconf) {
3386                 .tx_thresh = {
3387                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3388                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3389                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3390                 },
3391                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3392                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3393                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3394                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3395         };
3396
3397         dev_info->rx_desc_lim = rx_desc_lim;
3398         dev_info->tx_desc_lim = tx_desc_lim;
3399
3400         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3401         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3402         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3403
3404         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3405         if (hw->mac.type == ixgbe_mac_X540 ||
3406             hw->mac.type == ixgbe_mac_X540_vf ||
3407             hw->mac.type == ixgbe_mac_X550 ||
3408             hw->mac.type == ixgbe_mac_X550_vf) {
3409                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3410         }
3411 }
3412
3413 static const uint32_t *
3414 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3415 {
3416         static const uint32_t ptypes[] = {
3417                 /* For non-vec functions,
3418                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3419                  * for vec functions,
3420                  * refers to _recv_raw_pkts_vec().
3421                  */
3422                 RTE_PTYPE_L2_ETHER,
3423                 RTE_PTYPE_L3_IPV4,
3424                 RTE_PTYPE_L3_IPV4_EXT,
3425                 RTE_PTYPE_L3_IPV6,
3426                 RTE_PTYPE_L3_IPV6_EXT,
3427                 RTE_PTYPE_L4_SCTP,
3428                 RTE_PTYPE_L4_TCP,
3429                 RTE_PTYPE_L4_UDP,
3430                 RTE_PTYPE_TUNNEL_IP,
3431                 RTE_PTYPE_INNER_L3_IPV6,
3432                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3433                 RTE_PTYPE_INNER_L4_TCP,
3434                 RTE_PTYPE_INNER_L4_UDP,
3435                 RTE_PTYPE_UNKNOWN
3436         };
3437
3438         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3439             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3440             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3441             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3442                 return ptypes;
3443         return NULL;
3444 }
3445
3446 static void
3447 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3448                      struct rte_eth_dev_info *dev_info)
3449 {
3450         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3451         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3452
3453         dev_info->pci_dev = pci_dev;
3454         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3455         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3456         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3457         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3458         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3459         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3460         dev_info->max_vfs = pci_dev->max_vfs;
3461         if (hw->mac.type == ixgbe_mac_82598EB)
3462                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3463         else
3464                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3465         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3466                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3467                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3468                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3469         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3470                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3471                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3472                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3473                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3474                                 DEV_TX_OFFLOAD_TCP_TSO;
3475
3476         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3477                 .rx_thresh = {
3478                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3479                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3480                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3481                 },
3482                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3483                 .rx_drop_en = 0,
3484         };
3485
3486         dev_info->default_txconf = (struct rte_eth_txconf) {
3487                 .tx_thresh = {
3488                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3489                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3490                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3491                 },
3492                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3493                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3494                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3495                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3496         };
3497
3498         dev_info->rx_desc_lim = rx_desc_lim;
3499         dev_info->tx_desc_lim = tx_desc_lim;
3500 }
3501
3502 /* return 0 means link status changed, -1 means not changed */
3503 static int
3504 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3505 {
3506         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3507         struct rte_eth_link link, old;
3508         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3509         int link_up;
3510         int diag;
3511
3512         link.link_status = ETH_LINK_DOWN;
3513         link.link_speed = 0;
3514         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3515         memset(&old, 0, sizeof(old));
3516         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3517
3518         hw->mac.get_link_status = true;
3519
3520         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3521         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3522                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3523         else
3524                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3525
3526         if (diag != 0) {
3527                 link.link_speed = ETH_SPEED_NUM_100M;
3528                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3529                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3530                 if (link.link_status == old.link_status)
3531                         return -1;
3532                 return 0;
3533         }
3534
3535         if (link_up == 0) {
3536                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3537                 if (link.link_status == old.link_status)
3538                         return -1;
3539                 return 0;
3540         }
3541         link.link_status = ETH_LINK_UP;
3542         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3543
3544         switch (link_speed) {
3545         default:
3546         case IXGBE_LINK_SPEED_UNKNOWN:
3547                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3548                 link.link_speed = ETH_SPEED_NUM_100M;
3549                 break;
3550
3551         case IXGBE_LINK_SPEED_100_FULL:
3552                 link.link_speed = ETH_SPEED_NUM_100M;
3553                 break;
3554
3555         case IXGBE_LINK_SPEED_1GB_FULL:
3556                 link.link_speed = ETH_SPEED_NUM_1G;
3557                 break;
3558
3559         case IXGBE_LINK_SPEED_10GB_FULL:
3560                 link.link_speed = ETH_SPEED_NUM_10G;
3561                 break;
3562         }
3563         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3564
3565         if (link.link_status == old.link_status)
3566                 return -1;
3567
3568         return 0;
3569 }
3570
3571 static void
3572 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3573 {
3574         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3575         uint32_t fctrl;
3576
3577         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3578         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3579         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3580 }
3581
3582 static void
3583 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3584 {
3585         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3586         uint32_t fctrl;
3587
3588         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3589         fctrl &= (~IXGBE_FCTRL_UPE);
3590         if (dev->data->all_multicast == 1)
3591                 fctrl |= IXGBE_FCTRL_MPE;
3592         else
3593                 fctrl &= (~IXGBE_FCTRL_MPE);
3594         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3595 }
3596
3597 static void
3598 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3599 {
3600         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3601         uint32_t fctrl;
3602
3603         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3604         fctrl |= IXGBE_FCTRL_MPE;
3605         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3606 }
3607
3608 static void
3609 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3610 {
3611         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3612         uint32_t fctrl;
3613
3614         if (dev->data->promiscuous == 1)
3615                 return; /* must remain in all_multicast mode */
3616
3617         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3618         fctrl &= (~IXGBE_FCTRL_MPE);
3619         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3620 }
3621
3622 /**
3623  * It clears the interrupt causes and enables the interrupt.
3624  * It will be called once only during nic initialized.
3625  *
3626  * @param dev
3627  *  Pointer to struct rte_eth_dev.
3628  *
3629  * @return
3630  *  - On success, zero.
3631  *  - On failure, a negative value.
3632  */
3633 static int
3634 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3635 {
3636         struct ixgbe_interrupt *intr =
3637                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3638
3639         ixgbe_dev_link_status_print(dev);
3640         intr->mask |= IXGBE_EICR_LSC;
3641
3642         return 0;
3643 }
3644
3645 /**
3646  * It clears the interrupt causes and enables the interrupt.
3647  * It will be called once only during nic initialized.
3648  *
3649  * @param dev
3650  *  Pointer to struct rte_eth_dev.
3651  *
3652  * @return
3653  *  - On success, zero.
3654  *  - On failure, a negative value.
3655  */
3656 static int
3657 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3658 {
3659         struct ixgbe_interrupt *intr =
3660                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3661
3662         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3663
3664         return 0;
3665 }
3666
3667 /**
3668  * It clears the interrupt causes and enables the interrupt.
3669  * It will be called once only during nic initialized.
3670  *
3671  * @param dev
3672  *  Pointer to struct rte_eth_dev.
3673  *
3674  * @return
3675  *  - On success, zero.
3676  *  - On failure, a negative value.
3677  */
3678 static int
3679 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3680 {
3681         struct ixgbe_interrupt *intr =
3682                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3683
3684         intr->mask |= IXGBE_EICR_LINKSEC;
3685
3686         return 0;
3687 }
3688
3689 /*
3690  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3691  *
3692  * @param dev
3693  *  Pointer to struct rte_eth_dev.
3694  *
3695  * @return
3696  *  - On success, zero.
3697  *  - On failure, a negative value.
3698  */
3699 static int
3700 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3701 {
3702         uint32_t eicr;
3703         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3704         struct ixgbe_interrupt *intr =
3705                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3706
3707         /* clear all cause mask */
3708         ixgbe_disable_intr(hw);
3709
3710         /* read-on-clear nic registers here */
3711         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3712         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3713
3714         intr->flags = 0;
3715
3716         /* set flag for async link update */
3717         if (eicr & IXGBE_EICR_LSC)
3718                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3719
3720         if (eicr & IXGBE_EICR_MAILBOX)
3721                 intr->flags |= IXGBE_FLAG_MAILBOX;
3722
3723         if (eicr & IXGBE_EICR_LINKSEC)
3724                 intr->flags |= IXGBE_FLAG_MACSEC;
3725
3726         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3727             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3728             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3729                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3730
3731         return 0;
3732 }
3733
3734 /**
3735  * It gets and then prints the link status.
3736  *
3737  * @param dev
3738  *  Pointer to struct rte_eth_dev.
3739  *
3740  * @return
3741  *  - On success, zero.
3742  *  - On failure, a negative value.
3743  */
3744 static void
3745 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3746 {
3747         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3748         struct rte_eth_link link;
3749
3750         memset(&link, 0, sizeof(link));
3751         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3752         if (link.link_status) {
3753                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3754                                         (int)(dev->data->port_id),
3755                                         (unsigned)link.link_speed,
3756                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3757                                         "full-duplex" : "half-duplex");
3758         } else {
3759                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3760                                 (int)(dev->data->port_id));
3761         }
3762         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3763                                 pci_dev->addr.domain,
3764                                 pci_dev->addr.bus,
3765                                 pci_dev->addr.devid,
3766                                 pci_dev->addr.function);
3767 }
3768
3769 /*
3770  * It executes link_update after knowing an interrupt occurred.
3771  *
3772  * @param dev
3773  *  Pointer to struct rte_eth_dev.
3774  *
3775  * @return
3776  *  - On success, zero.
3777  *  - On failure, a negative value.
3778  */
3779 static int
3780 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3781                            struct rte_intr_handle *intr_handle)
3782 {
3783         struct ixgbe_interrupt *intr =
3784                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3785         int64_t timeout;
3786         struct rte_eth_link link;
3787         int intr_enable_delay = false;
3788         struct ixgbe_hw *hw =
3789                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3790
3791         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3792
3793         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3794                 ixgbe_pf_mbx_process(dev);
3795                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3796         }
3797
3798         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3799                 ixgbe_handle_lasi(hw);
3800                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3801         }
3802
3803         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3804                 /* get the link status before link update, for predicting later */
3805                 memset(&link, 0, sizeof(link));
3806                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3807
3808                 ixgbe_dev_link_update(dev, 0);
3809
3810                 /* likely to up */
3811                 if (!link.link_status)
3812                         /* handle it 1 sec later, wait it being stable */
3813                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3814                 /* likely to down */
3815                 else
3816                         /* handle it 4 sec later, wait it being stable */
3817                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3818
3819                 ixgbe_dev_link_status_print(dev);
3820
3821                 intr_enable_delay = true;
3822         }
3823
3824         if (intr_enable_delay) {
3825                 if (rte_eal_alarm_set(timeout * 1000,
3826                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3827                         PMD_DRV_LOG(ERR, "Error setting alarm");
3828         } else {
3829                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3830                 ixgbe_enable_intr(dev);
3831                 rte_intr_enable(intr_handle);
3832         }
3833
3834
3835         return 0;
3836 }
3837
3838 /**
3839  * Interrupt handler which shall be registered for alarm callback for delayed
3840  * handling specific interrupt to wait for the stable nic state. As the
3841  * NIC interrupt state is not stable for ixgbe after link is just down,
3842  * it needs to wait 4 seconds to get the stable status.
3843  *
3844  * @param handle
3845  *  Pointer to interrupt handle.
3846  * @param param
3847  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3848  *
3849  * @return
3850  *  void
3851  */
3852 static void
3853 ixgbe_dev_interrupt_delayed_handler(void *param)
3854 {
3855         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3856         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3857         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3858         struct ixgbe_interrupt *intr =
3859                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3860         struct ixgbe_hw *hw =
3861                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3862         uint32_t eicr;
3863
3864         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3865         if (eicr & IXGBE_EICR_MAILBOX)
3866                 ixgbe_pf_mbx_process(dev);
3867
3868         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3869                 ixgbe_handle_lasi(hw);
3870                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3871         }
3872
3873         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3874                 ixgbe_dev_link_update(dev, 0);
3875                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3876                 ixgbe_dev_link_status_print(dev);
3877                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3878         }
3879
3880         if (intr->flags & IXGBE_FLAG_MACSEC) {
3881                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3882                                               NULL);
3883                 intr->flags &= ~IXGBE_FLAG_MACSEC;
3884         }
3885
3886         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3887         ixgbe_enable_intr(dev);
3888         rte_intr_enable(intr_handle);
3889 }
3890
3891 /**
3892  * Interrupt handler triggered by NIC  for handling
3893  * specific interrupt.
3894  *
3895  * @param handle
3896  *  Pointer to interrupt handle.
3897  * @param param
3898  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3899  *
3900  * @return
3901  *  void
3902  */
3903 static void
3904 ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
3905                             void *param)
3906 {
3907         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3908
3909         ixgbe_dev_interrupt_get_status(dev);
3910         ixgbe_dev_interrupt_action(dev, handle);
3911 }
3912
3913 static int
3914 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3915 {
3916         struct ixgbe_hw *hw;
3917
3918         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3919         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3920 }
3921
3922 static int
3923 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3924 {
3925         struct ixgbe_hw *hw;
3926
3927         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3928         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3929 }
3930
3931 static int
3932 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3933 {
3934         struct ixgbe_hw *hw;
3935         uint32_t mflcn_reg;
3936         uint32_t fccfg_reg;
3937         int rx_pause;
3938         int tx_pause;
3939
3940         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3941
3942         fc_conf->pause_time = hw->fc.pause_time;
3943         fc_conf->high_water = hw->fc.high_water[0];
3944         fc_conf->low_water = hw->fc.low_water[0];
3945         fc_conf->send_xon = hw->fc.send_xon;
3946         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3947
3948         /*
3949          * Return rx_pause status according to actual setting of
3950          * MFLCN register.
3951          */
3952         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3953         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3954                 rx_pause = 1;
3955         else
3956                 rx_pause = 0;
3957
3958         /*
3959          * Return tx_pause status according to actual setting of
3960          * FCCFG register.
3961          */
3962         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3963         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3964                 tx_pause = 1;
3965         else
3966                 tx_pause = 0;
3967
3968         if (rx_pause && tx_pause)
3969                 fc_conf->mode = RTE_FC_FULL;
3970         else if (rx_pause)
3971                 fc_conf->mode = RTE_FC_RX_PAUSE;
3972         else if (tx_pause)
3973                 fc_conf->mode = RTE_FC_TX_PAUSE;
3974         else
3975                 fc_conf->mode = RTE_FC_NONE;
3976
3977         return 0;
3978 }
3979
3980 static int
3981 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3982 {
3983         struct ixgbe_hw *hw;
3984         int err;
3985         uint32_t rx_buf_size;
3986         uint32_t max_high_water;
3987         uint32_t mflcn;
3988         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3989                 ixgbe_fc_none,
3990                 ixgbe_fc_rx_pause,
3991                 ixgbe_fc_tx_pause,
3992                 ixgbe_fc_full
3993         };
3994
3995         PMD_INIT_FUNC_TRACE();
3996
3997         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3998         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3999         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4000
4001         /*
4002          * At least reserve one Ethernet frame for watermark
4003          * high_water/low_water in kilo bytes for ixgbe
4004          */
4005         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4006         if ((fc_conf->high_water > max_high_water) ||
4007                 (fc_conf->high_water < fc_conf->low_water)) {
4008                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4009                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4010                 return -EINVAL;
4011         }
4012
4013         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4014         hw->fc.pause_time     = fc_conf->pause_time;
4015         hw->fc.high_water[0]  = fc_conf->high_water;
4016         hw->fc.low_water[0]   = fc_conf->low_water;
4017         hw->fc.send_xon       = fc_conf->send_xon;
4018         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4019
4020         err = ixgbe_fc_enable(hw);
4021
4022         /* Not negotiated is not an error case */
4023         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4024
4025                 /* check if we want to forward MAC frames - driver doesn't have native
4026                  * capability to do that, so we'll write the registers ourselves */
4027
4028                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4029
4030                 /* set or clear MFLCN.PMCF bit depending on configuration */
4031                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4032                         mflcn |= IXGBE_MFLCN_PMCF;
4033                 else
4034                         mflcn &= ~IXGBE_MFLCN_PMCF;
4035
4036                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4037                 IXGBE_WRITE_FLUSH(hw);
4038
4039                 return 0;
4040         }
4041
4042         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4043         return -EIO;
4044 }
4045
4046 /**
4047  *  ixgbe_pfc_enable_generic - Enable flow control
4048  *  @hw: pointer to hardware structure
4049  *  @tc_num: traffic class number
4050  *  Enable flow control according to the current settings.
4051  */
4052 static int
4053 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4054 {
4055         int ret_val = 0;
4056         uint32_t mflcn_reg, fccfg_reg;
4057         uint32_t reg;
4058         uint32_t fcrtl, fcrth;
4059         uint8_t i;
4060         uint8_t nb_rx_en;
4061
4062         /* Validate the water mark configuration */
4063         if (!hw->fc.pause_time) {
4064                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4065                 goto out;
4066         }
4067
4068         /* Low water mark of zero causes XOFF floods */
4069         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4070                  /* High/Low water can not be 0 */
4071                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4072                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4073                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4074                         goto out;
4075                 }
4076
4077                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4078                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4079                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4080                         goto out;
4081                 }
4082         }
4083         /* Negotiate the fc mode to use */
4084         ixgbe_fc_autoneg(hw);
4085
4086         /* Disable any previous flow control settings */
4087         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4088         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4089
4090         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4091         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4092
4093         switch (hw->fc.current_mode) {
4094         case ixgbe_fc_none:
4095                 /*
4096                  * If the count of enabled RX Priority Flow control >1,
4097                  * and the TX pause can not be disabled
4098                  */
4099                 nb_rx_en = 0;
4100                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4101                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4102                         if (reg & IXGBE_FCRTH_FCEN)
4103                                 nb_rx_en++;
4104                 }
4105                 if (nb_rx_en > 1)
4106                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4107                 break;
4108         case ixgbe_fc_rx_pause:
4109                 /*
4110                  * Rx Flow control is enabled and Tx Flow control is
4111                  * disabled by software override. Since there really
4112                  * isn't a way to advertise that we are capable of RX
4113                  * Pause ONLY, we will advertise that we support both
4114                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4115                  * disable the adapter's ability to send PAUSE frames.
4116                  */
4117                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4118                 /*
4119                  * If the count of enabled RX Priority Flow control >1,
4120                  * and the TX pause can not be disabled
4121                  */
4122                 nb_rx_en = 0;
4123                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4124                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4125                         if (reg & IXGBE_FCRTH_FCEN)
4126                                 nb_rx_en++;
4127                 }
4128                 if (nb_rx_en > 1)
4129                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4130                 break;
4131         case ixgbe_fc_tx_pause:
4132                 /*
4133                  * Tx Flow control is enabled, and Rx Flow control is
4134                  * disabled by software override.
4135                  */
4136                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4137                 break;
4138         case ixgbe_fc_full:
4139                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4140                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4141                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4142                 break;
4143         default:
4144                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4145                 ret_val = IXGBE_ERR_CONFIG;
4146                 goto out;
4147         }
4148
4149         /* Set 802.3x based flow control settings. */
4150         mflcn_reg |= IXGBE_MFLCN_DPF;
4151         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4152         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4153
4154         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4155         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4156                 hw->fc.high_water[tc_num]) {
4157                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4158                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4159                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4160         } else {
4161                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4162                 /*
4163                  * In order to prevent Tx hangs when the internal Tx
4164                  * switch is enabled we must set the high water mark
4165                  * to the maximum FCRTH value.  This allows the Tx
4166                  * switch to function even under heavy Rx workloads.
4167                  */
4168                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4169         }
4170         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4171
4172         /* Configure pause time (2 TCs per register) */
4173         reg = hw->fc.pause_time * 0x00010001;
4174         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4175                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4176
4177         /* Configure flow control refresh threshold value */
4178         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4179
4180 out:
4181         return ret_val;
4182 }
4183
4184 static int
4185 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4186 {
4187         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4188         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4189
4190         if (hw->mac.type != ixgbe_mac_82598EB) {
4191                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4192         }
4193         return ret_val;
4194 }
4195
4196 static int
4197 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4198 {
4199         int err;
4200         uint32_t rx_buf_size;
4201         uint32_t max_high_water;
4202         uint8_t tc_num;
4203         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4204         struct ixgbe_hw *hw =
4205                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4206         struct ixgbe_dcb_config *dcb_config =
4207                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4208
4209         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4210                 ixgbe_fc_none,
4211                 ixgbe_fc_rx_pause,
4212                 ixgbe_fc_tx_pause,
4213                 ixgbe_fc_full
4214         };
4215
4216         PMD_INIT_FUNC_TRACE();
4217
4218         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4219         tc_num = map[pfc_conf->priority];
4220         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4221         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4222         /*
4223          * At least reserve one Ethernet frame for watermark
4224          * high_water/low_water in kilo bytes for ixgbe
4225          */
4226         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4227         if ((pfc_conf->fc.high_water > max_high_water) ||
4228             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4229                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4230                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4231                 return -EINVAL;
4232         }
4233
4234         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4235         hw->fc.pause_time = pfc_conf->fc.pause_time;
4236         hw->fc.send_xon = pfc_conf->fc.send_xon;
4237         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4238         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4239
4240         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4241
4242         /* Not negotiated is not an error case */
4243         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4244                 return 0;
4245
4246         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4247         return -EIO;
4248 }
4249
4250 static int
4251 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4252                           struct rte_eth_rss_reta_entry64 *reta_conf,
4253                           uint16_t reta_size)
4254 {
4255         uint16_t i, sp_reta_size;
4256         uint8_t j, mask;
4257         uint32_t reta, r;
4258         uint16_t idx, shift;
4259         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4260         uint32_t reta_reg;
4261
4262         PMD_INIT_FUNC_TRACE();
4263
4264         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4265                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4266                         "NIC.");
4267                 return -ENOTSUP;
4268         }
4269
4270         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4271         if (reta_size != sp_reta_size) {
4272                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4273                         "(%d) doesn't match the number hardware can supported "
4274                         "(%d)\n", reta_size, sp_reta_size);
4275                 return -EINVAL;
4276         }
4277
4278         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4279                 idx = i / RTE_RETA_GROUP_SIZE;
4280                 shift = i % RTE_RETA_GROUP_SIZE;
4281                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4282                                                 IXGBE_4_BIT_MASK);
4283                 if (!mask)
4284                         continue;
4285                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4286                 if (mask == IXGBE_4_BIT_MASK)
4287                         r = 0;
4288                 else
4289                         r = IXGBE_READ_REG(hw, reta_reg);
4290                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4291                         if (mask & (0x1 << j))
4292                                 reta |= reta_conf[idx].reta[shift + j] <<
4293                                                         (CHAR_BIT * j);
4294                         else
4295                                 reta |= r & (IXGBE_8_BIT_MASK <<
4296                                                 (CHAR_BIT * j));
4297                 }
4298                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4299         }
4300
4301         return 0;
4302 }
4303
4304 static int
4305 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4306                          struct rte_eth_rss_reta_entry64 *reta_conf,
4307                          uint16_t reta_size)
4308 {
4309         uint16_t i, sp_reta_size;
4310         uint8_t j, mask;
4311         uint32_t reta;
4312         uint16_t idx, shift;
4313         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4314         uint32_t reta_reg;
4315
4316         PMD_INIT_FUNC_TRACE();
4317         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4318         if (reta_size != sp_reta_size) {
4319                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4320                         "(%d) doesn't match the number hardware can supported "
4321                         "(%d)\n", reta_size, sp_reta_size);
4322                 return -EINVAL;
4323         }
4324
4325         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4326                 idx = i / RTE_RETA_GROUP_SIZE;
4327                 shift = i % RTE_RETA_GROUP_SIZE;
4328                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4329                                                 IXGBE_4_BIT_MASK);
4330                 if (!mask)
4331                         continue;
4332
4333                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4334                 reta = IXGBE_READ_REG(hw, reta_reg);
4335                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4336                         if (mask & (0x1 << j))
4337                                 reta_conf[idx].reta[shift + j] =
4338                                         ((reta >> (CHAR_BIT * j)) &
4339                                                 IXGBE_8_BIT_MASK);
4340                 }
4341         }
4342
4343         return 0;
4344 }
4345
4346 static void
4347 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4348                                 uint32_t index, uint32_t pool)
4349 {
4350         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4351         uint32_t enable_addr = 1;
4352
4353         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4354 }
4355
4356 static void
4357 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4358 {
4359         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4360
4361         ixgbe_clear_rar(hw, index);
4362 }
4363
4364 static void
4365 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4366 {
4367         ixgbe_remove_rar(dev, 0);
4368
4369         ixgbe_add_rar(dev, addr, 0, 0);
4370 }
4371
4372 static int
4373 is_ixgbe_pmd(const char *driver_name)
4374 {
4375         if (!strstr(driver_name, "ixgbe"))
4376                 return -ENOTSUP;
4377
4378         if (strstr(driver_name, "ixgbe_vf"))
4379                 return -ENOTSUP;
4380
4381         return 0;
4382 }
4383
4384 int
4385 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4386                 struct ether_addr *mac_addr)
4387 {
4388         struct ixgbe_hw *hw;
4389         struct ixgbe_vf_info *vfinfo;
4390         int rar_entry;
4391         uint8_t *new_mac = (uint8_t *)(mac_addr);
4392         struct rte_eth_dev *dev;
4393         struct rte_eth_dev_info dev_info;
4394
4395         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4396
4397         dev = &rte_eth_devices[port];
4398         rte_eth_dev_info_get(port, &dev_info);
4399
4400         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4401                 return -ENOTSUP;
4402
4403         if (vf >= dev_info.max_vfs)
4404                 return -EINVAL;
4405
4406         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4407         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4408         rar_entry = hw->mac.num_rar_entries - (vf + 1);
4409
4410         if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4411                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4412                                 ETHER_ADDR_LEN);
4413                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4414                                 IXGBE_RAH_AV);
4415         }
4416         return -EINVAL;
4417 }
4418
4419 static int
4420 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4421 {
4422         uint32_t hlreg0;
4423         uint32_t maxfrs;
4424         struct ixgbe_hw *hw;
4425         struct rte_eth_dev_info dev_info;
4426         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4427
4428         ixgbe_dev_info_get(dev, &dev_info);
4429
4430         /* check that mtu is within the allowed range */
4431         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4432                 return -EINVAL;
4433
4434         /* refuse mtu that requires the support of scattered packets when this
4435          * feature has not been enabled before.
4436          */
4437         if (!dev->data->scattered_rx &&
4438             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4439              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4440                 return -EINVAL;
4441
4442         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4443         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4444
4445         /* switch to jumbo mode if needed */
4446         if (frame_size > ETHER_MAX_LEN) {
4447                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4448                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4449         } else {
4450                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4451                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4452         }
4453         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4454
4455         /* update max frame size */
4456         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4457
4458         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4459         maxfrs &= 0x0000FFFF;
4460         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4461         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4462
4463         return 0;
4464 }
4465
4466 /*
4467  * Virtual Function operations
4468  */
4469 static void
4470 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4471 {
4472         PMD_INIT_FUNC_TRACE();
4473
4474         /* Clear interrupt mask to stop from interrupts being generated */
4475         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4476
4477         IXGBE_WRITE_FLUSH(hw);
4478 }
4479
4480 static void
4481 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4482 {
4483         PMD_INIT_FUNC_TRACE();
4484
4485         /* VF enable interrupt autoclean */
4486         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4487         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4488         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4489
4490         IXGBE_WRITE_FLUSH(hw);
4491 }
4492
4493 static int
4494 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4495 {
4496         struct rte_eth_conf *conf = &dev->data->dev_conf;
4497         struct ixgbe_adapter *adapter =
4498                         (struct ixgbe_adapter *)dev->data->dev_private;
4499
4500         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4501                      dev->data->port_id);
4502
4503         /*
4504          * VF has no ability to enable/disable HW CRC
4505          * Keep the persistent behavior the same as Host PF
4506          */
4507 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4508         if (!conf->rxmode.hw_strip_crc) {
4509                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4510                 conf->rxmode.hw_strip_crc = 1;
4511         }
4512 #else
4513         if (conf->rxmode.hw_strip_crc) {
4514                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4515                 conf->rxmode.hw_strip_crc = 0;
4516         }
4517 #endif
4518
4519         /*
4520          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4521          * allocation or vector Rx preconditions we will reset it.
4522          */
4523         adapter->rx_bulk_alloc_allowed = true;
4524         adapter->rx_vec_allowed = true;
4525
4526         return 0;
4527 }
4528
4529 static int
4530 ixgbevf_dev_start(struct rte_eth_dev *dev)
4531 {
4532         struct ixgbe_hw *hw =
4533                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4534         uint32_t intr_vector = 0;
4535         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4536         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4537
4538         int err, mask = 0;
4539
4540         PMD_INIT_FUNC_TRACE();
4541
4542         hw->mac.ops.reset_hw(hw);
4543         hw->mac.get_link_status = true;
4544
4545         /* negotiate mailbox API version to use with the PF. */
4546         ixgbevf_negotiate_api(hw);
4547
4548         ixgbevf_dev_tx_init(dev);
4549
4550         /* This can fail when allocating mbufs for descriptor rings */
4551         err = ixgbevf_dev_rx_init(dev);
4552         if (err) {
4553                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4554                 ixgbe_dev_clear_queues(dev);
4555                 return err;
4556         }
4557
4558         /* Set vfta */
4559         ixgbevf_set_vfta_all(dev, 1);
4560
4561         /* Set HW strip */
4562         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4563                 ETH_VLAN_EXTEND_MASK;
4564         ixgbevf_vlan_offload_set(dev, mask);
4565
4566         ixgbevf_dev_rxtx_start(dev);
4567
4568         /* check and configure queue intr-vector mapping */
4569         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4570                 intr_vector = dev->data->nb_rx_queues;
4571                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4572                         return -1;
4573         }
4574
4575         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4576                 intr_handle->intr_vec =
4577                         rte_zmalloc("intr_vec",
4578                                     dev->data->nb_rx_queues * sizeof(int), 0);
4579                 if (intr_handle->intr_vec == NULL) {
4580                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4581                                      " intr_vec\n", dev->data->nb_rx_queues);
4582                         return -ENOMEM;
4583                 }
4584         }
4585         ixgbevf_configure_msix(dev);
4586
4587         rte_intr_enable(intr_handle);
4588
4589         /* Re-enable interrupt for VF */
4590         ixgbevf_intr_enable(hw);
4591
4592         return 0;
4593 }
4594
4595 static void
4596 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4597 {
4598         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4599         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4600         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4601
4602         PMD_INIT_FUNC_TRACE();
4603
4604         ixgbevf_intr_disable(hw);
4605
4606         hw->adapter_stopped = 1;
4607         ixgbe_stop_adapter(hw);
4608
4609         /*
4610           * Clear what we set, but we still keep shadow_vfta to
4611           * restore after device starts
4612           */
4613         ixgbevf_set_vfta_all(dev, 0);
4614
4615         /* Clear stored conf */
4616         dev->data->scattered_rx = 0;
4617
4618         ixgbe_dev_clear_queues(dev);
4619
4620         /* Clean datapath event and queue/vec mapping */
4621         rte_intr_efd_disable(intr_handle);
4622         if (intr_handle->intr_vec != NULL) {
4623                 rte_free(intr_handle->intr_vec);
4624                 intr_handle->intr_vec = NULL;
4625         }
4626 }
4627
4628 static void
4629 ixgbevf_dev_close(struct rte_eth_dev *dev)
4630 {
4631         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4632
4633         PMD_INIT_FUNC_TRACE();
4634
4635         ixgbe_reset_hw(hw);
4636
4637         ixgbevf_dev_stop(dev);
4638
4639         ixgbe_dev_free_queues(dev);
4640
4641         /**
4642          * Remove the VF MAC address ro ensure
4643          * that the VF traffic goes to the PF
4644          * after stop, close and detach of the VF
4645          **/
4646         ixgbevf_remove_mac_addr(dev, 0);
4647 }
4648
4649 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4650 {
4651         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4652         struct ixgbe_vfta *shadow_vfta =
4653                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4654         int i = 0, j = 0, vfta = 0, mask = 1;
4655
4656         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4657                 vfta = shadow_vfta->vfta[i];
4658                 if (vfta) {
4659                         mask = 1;
4660                         for (j = 0; j < 32; j++) {
4661                                 if (vfta & mask)
4662                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4663                                                        on, false);
4664                                 mask <<= 1;
4665                         }
4666                 }
4667         }
4668
4669 }
4670
4671 static int
4672 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4673 {
4674         struct ixgbe_hw *hw =
4675                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4676         struct ixgbe_vfta *shadow_vfta =
4677                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4678         uint32_t vid_idx = 0;
4679         uint32_t vid_bit = 0;
4680         int ret = 0;
4681
4682         PMD_INIT_FUNC_TRACE();
4683
4684         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4685         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4686         if (ret) {
4687                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4688                 return ret;
4689         }
4690         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4691         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4692
4693         /* Save what we set and retore it after device reset */
4694         if (on)
4695                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4696         else
4697                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4698
4699         return 0;
4700 }
4701
4702 static void
4703 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4704 {
4705         struct ixgbe_hw *hw =
4706                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4707         uint32_t ctrl;
4708
4709         PMD_INIT_FUNC_TRACE();
4710
4711         if (queue >= hw->mac.max_rx_queues)
4712                 return;
4713
4714         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4715         if (on)
4716                 ctrl |= IXGBE_RXDCTL_VME;
4717         else
4718                 ctrl &= ~IXGBE_RXDCTL_VME;
4719         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4720
4721         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4722 }
4723
4724 static void
4725 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4726 {
4727         struct ixgbe_hw *hw =
4728                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4729         uint16_t i;
4730         int on = 0;
4731
4732         /* VF function only support hw strip feature, others are not support */
4733         if (mask & ETH_VLAN_STRIP_MASK) {
4734                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4735
4736                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4737                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4738         }
4739 }
4740
4741 static int
4742 ixgbe_vt_check(struct ixgbe_hw *hw)
4743 {
4744         uint32_t reg_val;
4745
4746         /* if Virtualization Technology is enabled */
4747         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4748         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4749                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
4750                 return -1;
4751         }
4752
4753         return 0;
4754 }
4755
4756 static uint32_t
4757 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4758 {
4759         uint32_t vector = 0;
4760
4761         switch (hw->mac.mc_filter_type) {
4762         case 0:   /* use bits [47:36] of the address */
4763                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4764                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4765                 break;
4766         case 1:   /* use bits [46:35] of the address */
4767                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4768                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4769                 break;
4770         case 2:   /* use bits [45:34] of the address */
4771                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4772                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4773                 break;
4774         case 3:   /* use bits [43:32] of the address */
4775                 vector = ((uc_addr->addr_bytes[4]) |
4776                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4777                 break;
4778         default:  /* Invalid mc_filter_type */
4779                 break;
4780         }
4781
4782         /* vector can only be 12-bits or boundary will be exceeded */
4783         vector &= 0xFFF;
4784         return vector;
4785 }
4786
4787 static int
4788 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4789                         uint8_t on)
4790 {
4791         uint32_t vector;
4792         uint32_t uta_idx;
4793         uint32_t reg_val;
4794         uint32_t uta_shift;
4795         uint32_t rc;
4796         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4797         const uint32_t ixgbe_uta_bit_shift = 5;
4798         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4799         const uint32_t bit1 = 0x1;
4800
4801         struct ixgbe_hw *hw =
4802                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4803         struct ixgbe_uta_info *uta_info =
4804                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4805
4806         /* The UTA table only exists on 82599 hardware and newer */
4807         if (hw->mac.type < ixgbe_mac_82599EB)
4808                 return -ENOTSUP;
4809
4810         vector = ixgbe_uta_vector(hw, mac_addr);
4811         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4812         uta_shift = vector & ixgbe_uta_bit_mask;
4813
4814         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4815         if (rc == on)
4816                 return 0;
4817
4818         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4819         if (on) {
4820                 uta_info->uta_in_use++;
4821                 reg_val |= (bit1 << uta_shift);
4822                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4823         } else {
4824                 uta_info->uta_in_use--;
4825                 reg_val &= ~(bit1 << uta_shift);
4826                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4827         }
4828
4829         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4830
4831         if (uta_info->uta_in_use > 0)
4832                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4833                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4834         else
4835                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4836
4837         return 0;
4838 }
4839
4840 static int
4841 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4842 {
4843         int i;
4844         struct ixgbe_hw *hw =
4845                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4846         struct ixgbe_uta_info *uta_info =
4847                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4848
4849         /* The UTA table only exists on 82599 hardware and newer */
4850         if (hw->mac.type < ixgbe_mac_82599EB)
4851                 return -ENOTSUP;
4852
4853         if (on) {
4854                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4855                         uta_info->uta_shadow[i] = ~0;
4856                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4857                 }
4858         } else {
4859                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4860                         uta_info->uta_shadow[i] = 0;
4861                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4862                 }
4863         }
4864         return 0;
4865
4866 }
4867
4868 uint32_t
4869 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4870 {
4871         uint32_t new_val = orig_val;
4872
4873         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4874                 new_val |= IXGBE_VMOLR_AUPE;
4875         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4876                 new_val |= IXGBE_VMOLR_ROMPE;
4877         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4878                 new_val |= IXGBE_VMOLR_ROPE;
4879         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4880                 new_val |= IXGBE_VMOLR_BAM;
4881         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4882                 new_val |= IXGBE_VMOLR_MPE;
4883
4884         return new_val;
4885 }
4886
4887
4888 int
4889 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4890 {
4891         struct ixgbe_hw *hw;
4892         struct ixgbe_mac_info *mac;
4893         struct rte_eth_dev *dev;
4894         struct rte_eth_dev_info dev_info;
4895
4896         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4897
4898         dev = &rte_eth_devices[port];
4899         rte_eth_dev_info_get(port, &dev_info);
4900
4901         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4902                 return -ENOTSUP;
4903
4904         if (vf >= dev_info.max_vfs)
4905                 return -EINVAL;
4906
4907         if (on > 1)
4908                 return -EINVAL;
4909
4910         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4911         mac = &hw->mac;
4912
4913         mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4914
4915         return 0;
4916 }
4917
4918 int
4919 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4920 {
4921         struct ixgbe_hw *hw;
4922         struct ixgbe_mac_info *mac;
4923         struct rte_eth_dev *dev;
4924         struct rte_eth_dev_info dev_info;
4925
4926         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4927
4928         dev = &rte_eth_devices[port];
4929         rte_eth_dev_info_get(port, &dev_info);
4930
4931         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4932                 return -ENOTSUP;
4933
4934         if (vf >= dev_info.max_vfs)
4935                 return -EINVAL;
4936
4937         if (on > 1)
4938                 return -EINVAL;
4939
4940         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4941         mac = &hw->mac;
4942         mac->ops.set_mac_anti_spoofing(hw, on, vf);
4943
4944         return 0;
4945 }
4946
4947 int
4948 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4949 {
4950         struct ixgbe_hw *hw;
4951         uint32_t ctrl;
4952         struct rte_eth_dev *dev;
4953         struct rte_eth_dev_info dev_info;
4954
4955         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4956
4957         dev = &rte_eth_devices[port];
4958         rte_eth_dev_info_get(port, &dev_info);
4959
4960         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4961                 return -ENOTSUP;
4962
4963         if (vf >= dev_info.max_vfs)
4964                 return -EINVAL;
4965
4966         if (vlan_id > ETHER_MAX_VLAN_ID)
4967                 return -EINVAL;
4968
4969         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4970         ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4971         if (vlan_id) {
4972                 ctrl = vlan_id;
4973                 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4974         } else {
4975                 ctrl = 0;
4976         }
4977
4978         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4979
4980         return 0;
4981 }
4982
4983 int
4984 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4985 {
4986         struct ixgbe_hw *hw;
4987         uint32_t ctrl;
4988         struct rte_eth_dev *dev;
4989         struct rte_eth_dev_info dev_info;
4990
4991         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4992
4993         dev = &rte_eth_devices[port];
4994         rte_eth_dev_info_get(port, &dev_info);
4995
4996         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4997                 return -ENOTSUP;
4998
4999         if (on > 1)
5000                 return -EINVAL;
5001
5002         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5003         ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5004         /* enable or disable VMDQ loopback */
5005         if (on)
5006                 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
5007         else
5008                 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
5009
5010         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
5011
5012         return 0;
5013 }
5014
5015 int
5016 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
5017 {
5018         struct ixgbe_hw *hw;
5019         uint32_t reg_value;
5020         int i;
5021         int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
5022         struct rte_eth_dev *dev;
5023         struct rte_eth_dev_info dev_info;
5024
5025         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5026
5027         dev = &rte_eth_devices[port];
5028         rte_eth_dev_info_get(port, &dev_info);
5029
5030         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5031                 return -ENOTSUP;
5032
5033         if (on > 1)
5034                 return -EINVAL;
5035
5036         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5037         for (i = 0; i <= num_queues; i++) {
5038                 reg_value = IXGBE_QDE_WRITE |
5039                                 (i << IXGBE_QDE_IDX_SHIFT) |
5040                                 (on & IXGBE_QDE_ENABLE);
5041                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
5042         }
5043
5044         return 0;
5045 }
5046
5047 int
5048 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
5049 {
5050         struct ixgbe_hw *hw;
5051         uint32_t reg_value;
5052         struct rte_eth_dev *dev;
5053         struct rte_eth_dev_info dev_info;
5054
5055         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5056
5057         dev = &rte_eth_devices[port];
5058         rte_eth_dev_info_get(port, &dev_info);
5059
5060         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5061                 return -ENOTSUP;
5062
5063         /* only support VF's 0 to 63 */
5064         if ((vf >= dev_info.max_vfs) || (vf > 63))
5065                 return -EINVAL;
5066
5067         if (on > 1)
5068                 return -EINVAL;
5069
5070         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5071         reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
5072         if (on)
5073                 reg_value |= IXGBE_SRRCTL_DROP_EN;
5074         else
5075                 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
5076
5077         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
5078
5079         return 0;
5080 }
5081
5082 int
5083 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
5084 {
5085         struct rte_eth_dev *dev;
5086         struct rte_eth_dev_info dev_info;
5087         uint16_t queues_per_pool;
5088         uint32_t q;
5089
5090         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5091
5092         dev = &rte_eth_devices[port];
5093         rte_eth_dev_info_get(port, &dev_info);
5094
5095         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5096                 return -ENOTSUP;
5097
5098         if (vf >= dev_info.max_vfs)
5099                 return -EINVAL;
5100
5101         if (on > 1)
5102                 return -EINVAL;
5103
5104         RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
5105
5106         /* The PF has 128 queue pairs and in SRIOV configuration
5107          * those queues will be assigned to VF's, so RXDCTL
5108          * registers will be dealing with queues which will be
5109          * assigned to VF's.
5110          * Let's say we have SRIOV configured with 31 VF's then the
5111          * first 124 queues 0-123 will be allocated to VF's and only
5112          * the last 4 queues 123-127 will be assigned to the PF.
5113          */
5114
5115         queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
5116
5117         for (q = 0; q < queues_per_pool; q++)
5118                 (*dev->dev_ops->vlan_strip_queue_set)(dev,
5119                                 q + vf * queues_per_pool, on);
5120         return 0;
5121 }
5122
5123 int
5124 rte_pmd_ixgbe_set_vf_rxmode(uint8_t port, uint16_t vf, uint16_t rx_mask, uint8_t on)
5125 {
5126         int val = 0;
5127         struct rte_eth_dev *dev;
5128         struct rte_eth_dev_info dev_info;
5129         struct ixgbe_hw *hw;
5130         uint32_t vmolr;
5131
5132         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5133
5134         dev = &rte_eth_devices[port];
5135         rte_eth_dev_info_get(port, &dev_info);
5136
5137         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5138                 return -ENOTSUP;
5139
5140         if (vf >= dev_info.max_vfs)
5141                 return -EINVAL;
5142
5143         if (on > 1)
5144                 return -EINVAL;
5145
5146         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5147         vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
5148
5149         if (hw->mac.type == ixgbe_mac_82598EB) {
5150                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
5151                              " on 82599 hardware and newer");
5152                 return -ENOTSUP;
5153         }
5154         if (ixgbe_vt_check(hw) < 0)
5155                 return -ENOTSUP;
5156
5157         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
5158
5159         if (on)
5160                 vmolr |= val;
5161         else
5162                 vmolr &= ~val;
5163
5164         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
5165
5166         return 0;
5167 }
5168
5169 int
5170 rte_pmd_ixgbe_set_vf_rx(uint8_t port, uint16_t vf, uint8_t on)
5171 {
5172         struct rte_eth_dev *dev;
5173         struct rte_eth_dev_info dev_info;
5174         uint32_t reg, addr;
5175         uint32_t val;
5176         const uint8_t bit1 = 0x1;
5177         struct ixgbe_hw *hw;
5178
5179         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5180
5181         dev = &rte_eth_devices[port];
5182         rte_eth_dev_info_get(port, &dev_info);
5183
5184         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5185                 return -ENOTSUP;
5186
5187         if (vf >= dev_info.max_vfs)
5188                 return -EINVAL;
5189
5190         if (on > 1)
5191                 return -EINVAL;
5192
5193         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5194
5195         if (ixgbe_vt_check(hw) < 0)
5196                 return -ENOTSUP;
5197
5198         /* for vf >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
5199         if (vf >= 32) {
5200                 addr = IXGBE_VFRE(1);
5201                 val = bit1 << (vf - 32);
5202         } else {
5203                 addr = IXGBE_VFRE(0);
5204                 val = bit1 << vf;
5205         }
5206
5207         reg = IXGBE_READ_REG(hw, addr);
5208
5209         if (on)
5210                 reg |= val;
5211         else
5212                 reg &= ~val;
5213
5214         IXGBE_WRITE_REG(hw, addr, reg);
5215
5216         return 0;
5217 }
5218
5219 int
5220 rte_pmd_ixgbe_set_vf_tx(uint8_t port, uint16_t vf, uint8_t on)
5221 {
5222         struct rte_eth_dev *dev;
5223         struct rte_eth_dev_info dev_info;
5224         uint32_t reg, addr;
5225         uint32_t val;
5226         const uint8_t bit1 = 0x1;
5227
5228         struct ixgbe_hw *hw;
5229
5230         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5231
5232         dev = &rte_eth_devices[port];
5233         rte_eth_dev_info_get(port, &dev_info);
5234
5235         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5236                 return -ENOTSUP;
5237
5238         if (vf >= dev_info.max_vfs)
5239                 return -EINVAL;
5240
5241         if (on > 1)
5242                 return -EINVAL;
5243
5244         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5245         if (ixgbe_vt_check(hw) < 0)
5246                 return -ENOTSUP;
5247
5248         /* for vf >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
5249         if (vf >= 32) {
5250                 addr = IXGBE_VFTE(1);
5251                 val = bit1 << (vf - 32);
5252         } else {
5253                 addr = IXGBE_VFTE(0);
5254                 val = bit1 << vf;
5255         }
5256
5257         reg = IXGBE_READ_REG(hw, addr);
5258
5259         if (on)
5260                 reg |= val;
5261         else
5262                 reg &= ~val;
5263
5264         IXGBE_WRITE_REG(hw, addr, reg);
5265
5266         return 0;
5267 }
5268
5269 int
5270 rte_pmd_ixgbe_set_vf_vlan_filter(uint8_t port, uint16_t vlan,
5271                         uint64_t vf_mask, uint8_t vlan_on)
5272 {
5273         struct rte_eth_dev *dev;
5274         struct rte_eth_dev_info dev_info;
5275         int ret = 0;
5276         uint16_t vf_idx;
5277         struct ixgbe_hw *hw;
5278
5279         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5280
5281         dev = &rte_eth_devices[port];
5282         rte_eth_dev_info_get(port, &dev_info);
5283
5284         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5285                 return -ENOTSUP;
5286
5287         if ((vlan > ETHER_MAX_VLAN_ID) || (vf_mask == 0))
5288                 return -EINVAL;
5289
5290         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5291         if (ixgbe_vt_check(hw) < 0)
5292                 return -ENOTSUP;
5293
5294         for (vf_idx = 0; vf_idx < 64; vf_idx++) {
5295                 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
5296                         ret = hw->mac.ops.set_vfta(hw, vlan, vf_idx,
5297                                                    vlan_on, false);
5298                         if (ret < 0)
5299                                 return ret;
5300                 }
5301         }
5302
5303         return ret;
5304 }
5305
5306 int rte_pmd_ixgbe_set_vf_rate_limit(uint8_t port, uint16_t vf,
5307         uint16_t tx_rate, uint64_t q_msk)
5308 {
5309         struct rte_eth_dev *dev;
5310         struct rte_eth_dev_info dev_info;
5311         struct ixgbe_hw *hw;
5312         struct ixgbe_vf_info *vfinfo;
5313         struct rte_eth_link link;
5314         uint8_t  nb_q_per_pool;
5315         uint32_t queue_stride;
5316         uint32_t queue_idx, idx = 0, vf_idx;
5317         uint32_t queue_end;
5318         uint16_t total_rate = 0;
5319         struct rte_pci_device *pci_dev;
5320
5321         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5322
5323         dev = &rte_eth_devices[port];
5324         rte_eth_dev_info_get(port, &dev_info);
5325         rte_eth_link_get_nowait(port, &link);
5326
5327         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5328                 return -ENOTSUP;
5329
5330         if (vf >= dev_info.max_vfs)
5331                 return -EINVAL;
5332
5333         if (tx_rate > link.link_speed)
5334                 return -EINVAL;
5335
5336         if (q_msk == 0)
5337                 return 0;
5338
5339         pci_dev = IXGBE_DEV_TO_PCI(dev);
5340         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5341         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5342         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5343         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5344         queue_idx = vf * queue_stride;
5345         queue_end = queue_idx + nb_q_per_pool - 1;
5346         if (queue_end >= hw->mac.max_tx_queues)
5347                 return -EINVAL;
5348
5349         if (vfinfo) {
5350                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5351                         if (vf_idx == vf)
5352                                 continue;
5353                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5354                                 idx++)
5355                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5356                 }
5357         } else {
5358                 return -EINVAL;
5359         }
5360
5361         /* Store tx_rate for this vf. */
5362         for (idx = 0; idx < nb_q_per_pool; idx++) {
5363                 if (((uint64_t)0x1 << idx) & q_msk) {
5364                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5365                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5366                         total_rate += tx_rate;
5367                 }
5368         }
5369
5370         if (total_rate > dev->data->dev_link.link_speed) {
5371                 /* Reset stored TX rate of the VF if it causes exceed
5372                  * link speed.
5373                  */
5374                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5375                 return -EINVAL;
5376         }
5377
5378         /* Set RTTBCNRC of each queue/pool for vf X  */
5379         for (; queue_idx <= queue_end; queue_idx++) {
5380                 if (0x1 & q_msk)
5381                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5382                 q_msk = q_msk >> 1;
5383         }
5384
5385         return 0;
5386 }
5387
5388 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5389 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5390 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5391 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5392 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5393         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5394         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5395
5396 static int
5397 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5398                         struct rte_eth_mirror_conf *mirror_conf,
5399                         uint8_t rule_id, uint8_t on)
5400 {
5401         uint32_t mr_ctl, vlvf;
5402         uint32_t mp_lsb = 0;
5403         uint32_t mv_msb = 0;
5404         uint32_t mv_lsb = 0;
5405         uint32_t mp_msb = 0;
5406         uint8_t i = 0;
5407         int reg_index = 0;
5408         uint64_t vlan_mask = 0;
5409
5410         const uint8_t pool_mask_offset = 32;
5411         const uint8_t vlan_mask_offset = 32;
5412         const uint8_t dst_pool_offset = 8;
5413         const uint8_t rule_mr_offset  = 4;
5414         const uint8_t mirror_rule_mask = 0x0F;
5415
5416         struct ixgbe_mirror_info *mr_info =
5417                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5418         struct ixgbe_hw *hw =
5419                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5420         uint8_t mirror_type = 0;
5421
5422         if (ixgbe_vt_check(hw) < 0)
5423                 return -ENOTSUP;
5424
5425         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5426                 return -EINVAL;
5427
5428         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5429                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5430                         mirror_conf->rule_type);
5431                 return -EINVAL;
5432         }
5433
5434         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5435                 mirror_type |= IXGBE_MRCTL_VLME;
5436                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5437                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5438                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5439                                 /* search vlan id related pool vlan filter index */
5440                                 reg_index = ixgbe_find_vlvf_slot(hw,
5441                                                  mirror_conf->vlan.vlan_id[i],
5442                                                  false);
5443                                 if (reg_index < 0)
5444                                         return -EINVAL;
5445                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5446                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5447                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5448                                       mirror_conf->vlan.vlan_id[i]))
5449                                         vlan_mask |= (1ULL << reg_index);
5450                                 else
5451                                         return -EINVAL;
5452                         }
5453                 }
5454
5455                 if (on) {
5456                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5457                         mv_msb = vlan_mask >> vlan_mask_offset;
5458
5459                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5460                                                 mirror_conf->vlan.vlan_mask;
5461                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5462                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5463                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5464                                                 mirror_conf->vlan.vlan_id[i];
5465                         }
5466                 } else {
5467                         mv_lsb = 0;
5468                         mv_msb = 0;
5469                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5470                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5471                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5472                 }
5473         }
5474
5475         /*
5476          * if enable pool mirror, write related pool mask register,if disable
5477          * pool mirror, clear PFMRVM register
5478          */
5479         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5480                 mirror_type |= IXGBE_MRCTL_VPME;
5481                 if (on) {
5482                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5483                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5484                         mr_info->mr_conf[rule_id].pool_mask =
5485                                         mirror_conf->pool_mask;
5486
5487                 } else {
5488                         mp_lsb = 0;
5489                         mp_msb = 0;
5490                         mr_info->mr_conf[rule_id].pool_mask = 0;
5491                 }
5492         }
5493         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5494                 mirror_type |= IXGBE_MRCTL_UPME;
5495         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5496                 mirror_type |= IXGBE_MRCTL_DPME;
5497
5498         /* read  mirror control register and recalculate it */
5499         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5500
5501         if (on) {
5502                 mr_ctl |= mirror_type;
5503                 mr_ctl &= mirror_rule_mask;
5504                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5505         } else
5506                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5507
5508         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5509         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5510
5511         /* write mirrror control  register */
5512         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5513
5514         /* write pool mirrror control  register */
5515         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5516                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5517                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5518                                 mp_msb);
5519         }
5520         /* write VLAN mirrror control  register */
5521         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5522                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5523                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5524                                 mv_msb);
5525         }
5526
5527         return 0;
5528 }
5529
5530 static int
5531 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5532 {
5533         int mr_ctl = 0;
5534         uint32_t lsb_val = 0;
5535         uint32_t msb_val = 0;
5536         const uint8_t rule_mr_offset = 4;
5537
5538         struct ixgbe_hw *hw =
5539                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5540         struct ixgbe_mirror_info *mr_info =
5541                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5542
5543         if (ixgbe_vt_check(hw) < 0)
5544                 return -ENOTSUP;
5545
5546         memset(&mr_info->mr_conf[rule_id], 0,
5547                 sizeof(struct rte_eth_mirror_conf));
5548
5549         /* clear PFVMCTL register */
5550         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5551
5552         /* clear pool mask register */
5553         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5554         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5555
5556         /* clear vlan mask register */
5557         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5558         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5559
5560         return 0;
5561 }
5562
5563 static int
5564 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5565 {
5566         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5567         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5568         uint32_t mask;
5569         struct ixgbe_hw *hw =
5570                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5571
5572         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5573         mask |= (1 << IXGBE_MISC_VEC_ID);
5574         RTE_SET_USED(queue_id);
5575         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5576
5577         rte_intr_enable(intr_handle);
5578
5579         return 0;
5580 }
5581
5582 static int
5583 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5584 {
5585         uint32_t mask;
5586         struct ixgbe_hw *hw =
5587                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5588
5589         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5590         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5591         RTE_SET_USED(queue_id);
5592         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5593
5594         return 0;
5595 }
5596
5597 static int
5598 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5599 {
5600         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5601         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5602         uint32_t mask;
5603         struct ixgbe_hw *hw =
5604                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5605         struct ixgbe_interrupt *intr =
5606                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5607
5608         if (queue_id < 16) {
5609                 ixgbe_disable_intr(hw);
5610                 intr->mask |= (1 << queue_id);
5611                 ixgbe_enable_intr(dev);
5612         } else if (queue_id < 32) {
5613                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5614                 mask &= (1 << queue_id);
5615                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5616         } else if (queue_id < 64) {
5617                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5618                 mask &= (1 << (queue_id - 32));
5619                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5620         }
5621         rte_intr_enable(intr_handle);
5622
5623         return 0;
5624 }
5625
5626 static int
5627 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5628 {
5629         uint32_t mask;
5630         struct ixgbe_hw *hw =
5631                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5632         struct ixgbe_interrupt *intr =
5633                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5634
5635         if (queue_id < 16) {
5636                 ixgbe_disable_intr(hw);
5637                 intr->mask &= ~(1 << queue_id);
5638                 ixgbe_enable_intr(dev);
5639         } else if (queue_id < 32) {
5640                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5641                 mask &= ~(1 << queue_id);
5642                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5643         } else if (queue_id < 64) {
5644                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5645                 mask &= ~(1 << (queue_id - 32));
5646                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5647         }
5648
5649         return 0;
5650 }
5651
5652 static void
5653 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5654                      uint8_t queue, uint8_t msix_vector)
5655 {
5656         uint32_t tmp, idx;
5657
5658         if (direction == -1) {
5659                 /* other causes */
5660                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5661                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5662                 tmp &= ~0xFF;
5663                 tmp |= msix_vector;
5664                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5665         } else {
5666                 /* rx or tx cause */
5667                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5668                 idx = ((16 * (queue & 1)) + (8 * direction));
5669                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5670                 tmp &= ~(0xFF << idx);
5671                 tmp |= (msix_vector << idx);
5672                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5673         }
5674 }
5675
5676 /**
5677  * set the IVAR registers, mapping interrupt causes to vectors
5678  * @param hw
5679  *  pointer to ixgbe_hw struct
5680  * @direction
5681  *  0 for Rx, 1 for Tx, -1 for other causes
5682  * @queue
5683  *  queue to map the corresponding interrupt to
5684  * @msix_vector
5685  *  the vector to map to the corresponding queue
5686  */
5687 static void
5688 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5689                    uint8_t queue, uint8_t msix_vector)
5690 {
5691         uint32_t tmp, idx;
5692
5693         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5694         if (hw->mac.type == ixgbe_mac_82598EB) {
5695                 if (direction == -1)
5696                         direction = 0;
5697                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5698                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5699                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5700                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5701                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5702         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5703                         (hw->mac.type == ixgbe_mac_X540)) {
5704                 if (direction == -1) {
5705                         /* other causes */
5706                         idx = ((queue & 1) * 8);
5707                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5708                         tmp &= ~(0xFF << idx);
5709                         tmp |= (msix_vector << idx);
5710                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5711                 } else {
5712                         /* rx or tx causes */
5713                         idx = ((16 * (queue & 1)) + (8 * direction));
5714                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5715                         tmp &= ~(0xFF << idx);
5716                         tmp |= (msix_vector << idx);
5717                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5718                 }
5719         }
5720 }
5721
5722 static void
5723 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5724 {
5725         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5726         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5727         struct ixgbe_hw *hw =
5728                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5729         uint32_t q_idx;
5730         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5731
5732         /* Configure VF other cause ivar */
5733         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5734
5735         /* won't configure msix register if no mapping is done
5736          * between intr vector and event fd.
5737          */
5738         if (!rte_intr_dp_is_en(intr_handle))
5739                 return;
5740
5741         /* Configure all RX queues of VF */
5742         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5743                 /* Force all queue use vector 0,
5744                  * as IXGBE_VF_MAXMSIVECOTR = 1
5745                  */
5746                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5747                 intr_handle->intr_vec[q_idx] = vector_idx;
5748         }
5749 }
5750
5751 /**
5752  * Sets up the hardware to properly generate MSI-X interrupts
5753  * @hw
5754  *  board private structure
5755  */
5756 static void
5757 ixgbe_configure_msix(struct rte_eth_dev *dev)
5758 {
5759         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5760         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5761         struct ixgbe_hw *hw =
5762                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5763         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5764         uint32_t vec = IXGBE_MISC_VEC_ID;
5765         uint32_t mask;
5766         uint32_t gpie;
5767
5768         /* won't configure msix register if no mapping is done
5769          * between intr vector and event fd
5770          */
5771         if (!rte_intr_dp_is_en(intr_handle))
5772                 return;
5773
5774         if (rte_intr_allow_others(intr_handle))
5775                 vec = base = IXGBE_RX_VEC_START;
5776
5777         /* setup GPIE for MSI-x mode */
5778         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5779         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5780                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5781         /* auto clearing and auto setting corresponding bits in EIMS
5782          * when MSI-X interrupt is triggered
5783          */
5784         if (hw->mac.type == ixgbe_mac_82598EB) {
5785                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5786         } else {
5787                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5788                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5789         }
5790         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5791
5792         /* Populate the IVAR table and set the ITR values to the
5793          * corresponding register.
5794          */
5795         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5796              queue_id++) {
5797                 /* by default, 1:1 mapping */
5798                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5799                 intr_handle->intr_vec[queue_id] = vec;
5800                 if (vec < base + intr_handle->nb_efd - 1)
5801                         vec++;
5802         }
5803
5804         switch (hw->mac.type) {
5805         case ixgbe_mac_82598EB:
5806                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5807                                    IXGBE_MISC_VEC_ID);
5808                 break;
5809         case ixgbe_mac_82599EB:
5810         case ixgbe_mac_X540:
5811                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5812                 break;
5813         default:
5814                 break;
5815         }
5816         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5817                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5818
5819         /* set up to autoclear timer, and the vectors */
5820         mask = IXGBE_EIMS_ENABLE_MASK;
5821         mask &= ~(IXGBE_EIMS_OTHER |
5822                   IXGBE_EIMS_MAILBOX |
5823                   IXGBE_EIMS_LSC);
5824
5825         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5826 }
5827
5828 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5829         uint16_t queue_idx, uint16_t tx_rate)
5830 {
5831         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5832         uint32_t rf_dec, rf_int;
5833         uint32_t bcnrc_val;
5834         uint16_t link_speed = dev->data->dev_link.link_speed;
5835
5836         if (queue_idx >= hw->mac.max_tx_queues)
5837                 return -EINVAL;
5838
5839         if (tx_rate != 0) {
5840                 /* Calculate the rate factor values to set */
5841                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5842                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5843                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5844
5845                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5846                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5847                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5848                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5849         } else {
5850                 bcnrc_val = 0;
5851         }
5852
5853         /*
5854          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5855          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5856          * set as 0x4.
5857          */
5858         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5859                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5860                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5861                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5862                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5863         else
5864                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5865                         IXGBE_MMW_SIZE_DEFAULT);
5866
5867         /* Set RTTBCNRC of queue X */
5868         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5869         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5870         IXGBE_WRITE_FLUSH(hw);
5871
5872         return 0;
5873 }
5874
5875 static void
5876 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5877                      __attribute__((unused)) uint32_t index,
5878                      __attribute__((unused)) uint32_t pool)
5879 {
5880         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5881         int diag;
5882
5883         /*
5884          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5885          * operation. Trap this case to avoid exhausting the [very limited]
5886          * set of PF resources used to store VF MAC addresses.
5887          */
5888         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5889                 return;
5890         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5891         if (diag == 0)
5892                 return;
5893         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5894 }
5895
5896 static void
5897 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5898 {
5899         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5900         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5901         struct ether_addr *mac_addr;
5902         uint32_t i;
5903         int diag;
5904
5905         /*
5906          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5907          * not support the deletion of a given MAC address.
5908          * Instead, it imposes to delete all MAC addresses, then to add again
5909          * all MAC addresses with the exception of the one to be deleted.
5910          */
5911         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5912
5913         /*
5914          * Add again all MAC addresses, with the exception of the deleted one
5915          * and of the permanent MAC address.
5916          */
5917         for (i = 0, mac_addr = dev->data->mac_addrs;
5918              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5919                 /* Skip the deleted MAC address */
5920                 if (i == index)
5921                         continue;
5922                 /* Skip NULL MAC addresses */
5923                 if (is_zero_ether_addr(mac_addr))
5924                         continue;
5925                 /* Skip the permanent MAC address */
5926                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5927                         continue;
5928                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5929                 if (diag != 0)
5930                         PMD_DRV_LOG(ERR,
5931                                     "Adding again MAC address "
5932                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5933                                     "diag=%d",
5934                                     mac_addr->addr_bytes[0],
5935                                     mac_addr->addr_bytes[1],
5936                                     mac_addr->addr_bytes[2],
5937                                     mac_addr->addr_bytes[3],
5938                                     mac_addr->addr_bytes[4],
5939                                     mac_addr->addr_bytes[5],
5940                                     diag);
5941         }
5942 }
5943
5944 static void
5945 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5946 {
5947         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5948
5949         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5950 }
5951
5952 #define MAC_TYPE_FILTER_SUP(type)    do {\
5953         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5954                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5955                 (type) != ixgbe_mac_X550EM_a)\
5956                 return -ENOTSUP;\
5957 } while (0)
5958
5959 static int
5960 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5961                         struct rte_eth_syn_filter *filter,
5962                         bool add)
5963 {
5964         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5965         struct ixgbe_filter_info *filter_info =
5966                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5967         uint32_t syn_info;
5968         uint32_t synqf;
5969
5970         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5971                 return -EINVAL;
5972
5973         syn_info = filter_info->syn_info;
5974
5975         if (add) {
5976                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5977                         return -EINVAL;
5978                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5979                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5980
5981                 if (filter->hig_pri)
5982                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5983                 else
5984                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5985         } else {
5986                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5987                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5988                         return -ENOENT;
5989                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5990         }
5991
5992         filter_info->syn_info = synqf;
5993         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5994         IXGBE_WRITE_FLUSH(hw);
5995         return 0;
5996 }
5997
5998 static int
5999 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6000                         struct rte_eth_syn_filter *filter)
6001 {
6002         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6003         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6004
6005         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6006                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6007                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6008                 return 0;
6009         }
6010         return -ENOENT;
6011 }
6012
6013 static int
6014 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6015                         enum rte_filter_op filter_op,
6016                         void *arg)
6017 {
6018         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6019         int ret;
6020
6021         MAC_TYPE_FILTER_SUP(hw->mac.type);
6022
6023         if (filter_op == RTE_ETH_FILTER_NOP)
6024                 return 0;
6025
6026         if (arg == NULL) {
6027                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6028                             filter_op);
6029                 return -EINVAL;
6030         }
6031
6032         switch (filter_op) {
6033         case RTE_ETH_FILTER_ADD:
6034                 ret = ixgbe_syn_filter_set(dev,
6035                                 (struct rte_eth_syn_filter *)arg,
6036                                 TRUE);
6037                 break;
6038         case RTE_ETH_FILTER_DELETE:
6039                 ret = ixgbe_syn_filter_set(dev,
6040                                 (struct rte_eth_syn_filter *)arg,
6041                                 FALSE);
6042                 break;
6043         case RTE_ETH_FILTER_GET:
6044                 ret = ixgbe_syn_filter_get(dev,
6045                                 (struct rte_eth_syn_filter *)arg);
6046                 break;
6047         default:
6048                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
6049                 ret = -EINVAL;
6050                 break;
6051         }
6052
6053         return ret;
6054 }
6055
6056
6057 static inline enum ixgbe_5tuple_protocol
6058 convert_protocol_type(uint8_t protocol_value)
6059 {
6060         if (protocol_value == IPPROTO_TCP)
6061                 return IXGBE_FILTER_PROTOCOL_TCP;
6062         else if (protocol_value == IPPROTO_UDP)
6063                 return IXGBE_FILTER_PROTOCOL_UDP;
6064         else if (protocol_value == IPPROTO_SCTP)
6065                 return IXGBE_FILTER_PROTOCOL_SCTP;
6066         else
6067                 return IXGBE_FILTER_PROTOCOL_NONE;
6068 }
6069
6070 /* inject a 5-tuple filter to HW */
6071 static inline void
6072 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6073                            struct ixgbe_5tuple_filter *filter)
6074 {
6075         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6076         int i;
6077         uint32_t ftqf, sdpqf;
6078         uint32_t l34timir = 0;
6079         uint8_t mask = 0xff;
6080
6081         i = filter->index;
6082
6083         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6084                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6085         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6086
6087         ftqf = (uint32_t)(filter->filter_info.proto &
6088                 IXGBE_FTQF_PROTOCOL_MASK);
6089         ftqf |= (uint32_t)((filter->filter_info.priority &
6090                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6091         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6092                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6093         if (filter->filter_info.dst_ip_mask == 0)
6094                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6095         if (filter->filter_info.src_port_mask == 0)
6096                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6097         if (filter->filter_info.dst_port_mask == 0)
6098                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6099         if (filter->filter_info.proto_mask == 0)
6100                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6101         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6102         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6103         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6104
6105         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6106         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6107         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6108         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6109
6110         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6111         l34timir |= (uint32_t)(filter->queue <<
6112                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6113         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6114 }
6115
6116 /*
6117  * add a 5tuple filter
6118  *
6119  * @param
6120  * dev: Pointer to struct rte_eth_dev.
6121  * index: the index the filter allocates.
6122  * filter: ponter to the filter that will be added.
6123  * rx_queue: the queue id the filter assigned to.
6124  *
6125  * @return
6126  *    - On success, zero.
6127  *    - On failure, a negative value.
6128  */
6129 static int
6130 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6131                         struct ixgbe_5tuple_filter *filter)
6132 {
6133         struct ixgbe_filter_info *filter_info =
6134                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6135         int i, idx, shift;
6136
6137         /*
6138          * look for an unused 5tuple filter index,
6139          * and insert the filter to list.
6140          */
6141         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6142                 idx = i / (sizeof(uint32_t) * NBBY);
6143                 shift = i % (sizeof(uint32_t) * NBBY);
6144                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6145                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6146                         filter->index = i;
6147                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6148                                           filter,
6149                                           entries);
6150                         break;
6151                 }
6152         }
6153         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6154                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6155                 return -ENOSYS;
6156         }
6157
6158         ixgbe_inject_5tuple_filter(dev, filter);
6159
6160         return 0;
6161 }
6162
6163 /*
6164  * remove a 5tuple filter
6165  *
6166  * @param
6167  * dev: Pointer to struct rte_eth_dev.
6168  * filter: the pointer of the filter will be removed.
6169  */
6170 static void
6171 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6172                         struct ixgbe_5tuple_filter *filter)
6173 {
6174         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6175         struct ixgbe_filter_info *filter_info =
6176                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6177         uint16_t index = filter->index;
6178
6179         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6180                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6181         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6182         rte_free(filter);
6183
6184         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6185         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6186         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6187         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6188         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6189 }
6190
6191 static int
6192 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6193 {
6194         struct ixgbe_hw *hw;
6195         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6196
6197         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6198
6199         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6200                 return -EINVAL;
6201
6202         /* refuse mtu that requires the support of scattered packets when this
6203          * feature has not been enabled before.
6204          */
6205         if (!dev->data->scattered_rx &&
6206             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6207              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6208                 return -EINVAL;
6209
6210         /*
6211          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6212          * request of the version 2.0 of the mailbox API.
6213          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6214          * of the mailbox API.
6215          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6216          * prior to 3.11.33 which contains the following change:
6217          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6218          */
6219         ixgbevf_rlpml_set_vf(hw, max_frame);
6220
6221         /* update max frame size */
6222         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6223         return 0;
6224 }
6225
6226 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
6227         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
6228                 return -ENOTSUP;\
6229 } while (0)
6230
6231 static inline struct ixgbe_5tuple_filter *
6232 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6233                         struct ixgbe_5tuple_filter_info *key)
6234 {
6235         struct ixgbe_5tuple_filter *it;
6236
6237         TAILQ_FOREACH(it, filter_list, entries) {
6238                 if (memcmp(key, &it->filter_info,
6239                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6240                         return it;
6241                 }
6242         }
6243         return NULL;
6244 }
6245
6246 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6247 static inline int
6248 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6249                         struct ixgbe_5tuple_filter_info *filter_info)
6250 {
6251         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6252                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6253                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6254                 return -EINVAL;
6255
6256         switch (filter->dst_ip_mask) {
6257         case UINT32_MAX:
6258                 filter_info->dst_ip_mask = 0;
6259                 filter_info->dst_ip = filter->dst_ip;
6260                 break;
6261         case 0:
6262                 filter_info->dst_ip_mask = 1;
6263                 break;
6264         default:
6265                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6266                 return -EINVAL;
6267         }
6268
6269         switch (filter->src_ip_mask) {
6270         case UINT32_MAX:
6271                 filter_info->src_ip_mask = 0;
6272                 filter_info->src_ip = filter->src_ip;
6273                 break;
6274         case 0:
6275                 filter_info->src_ip_mask = 1;
6276                 break;
6277         default:
6278                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6279                 return -EINVAL;
6280         }
6281
6282         switch (filter->dst_port_mask) {
6283         case UINT16_MAX:
6284                 filter_info->dst_port_mask = 0;
6285                 filter_info->dst_port = filter->dst_port;
6286                 break;
6287         case 0:
6288                 filter_info->dst_port_mask = 1;
6289                 break;
6290         default:
6291                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6292                 return -EINVAL;
6293         }
6294
6295         switch (filter->src_port_mask) {
6296         case UINT16_MAX:
6297                 filter_info->src_port_mask = 0;
6298                 filter_info->src_port = filter->src_port;
6299                 break;
6300         case 0:
6301                 filter_info->src_port_mask = 1;
6302                 break;
6303         default:
6304                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6305                 return -EINVAL;
6306         }
6307
6308         switch (filter->proto_mask) {
6309         case UINT8_MAX:
6310                 filter_info->proto_mask = 0;
6311                 filter_info->proto =
6312                         convert_protocol_type(filter->proto);
6313                 break;
6314         case 0:
6315                 filter_info->proto_mask = 1;
6316                 break;
6317         default:
6318                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6319                 return -EINVAL;
6320         }
6321
6322         filter_info->priority = (uint8_t)filter->priority;
6323         return 0;
6324 }
6325
6326 /*
6327  * add or delete a ntuple filter
6328  *
6329  * @param
6330  * dev: Pointer to struct rte_eth_dev.
6331  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6332  * add: if true, add filter, if false, remove filter
6333  *
6334  * @return
6335  *    - On success, zero.
6336  *    - On failure, a negative value.
6337  */
6338 static int
6339 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6340                         struct rte_eth_ntuple_filter *ntuple_filter,
6341                         bool add)
6342 {
6343         struct ixgbe_filter_info *filter_info =
6344                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6345         struct ixgbe_5tuple_filter_info filter_5tuple;
6346         struct ixgbe_5tuple_filter *filter;
6347         int ret;
6348
6349         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6350                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6351                 return -EINVAL;
6352         }
6353
6354         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6355         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6356         if (ret < 0)
6357                 return ret;
6358
6359         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6360                                          &filter_5tuple);
6361         if (filter != NULL && add) {
6362                 PMD_DRV_LOG(ERR, "filter exists.");
6363                 return -EEXIST;
6364         }
6365         if (filter == NULL && !add) {
6366                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6367                 return -ENOENT;
6368         }
6369
6370         if (add) {
6371                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6372                                 sizeof(struct ixgbe_5tuple_filter), 0);
6373                 if (filter == NULL)
6374                         return -ENOMEM;
6375                 (void)rte_memcpy(&filter->filter_info,
6376                                  &filter_5tuple,
6377                                  sizeof(struct ixgbe_5tuple_filter_info));
6378                 filter->queue = ntuple_filter->queue;
6379                 ret = ixgbe_add_5tuple_filter(dev, filter);
6380                 if (ret < 0) {
6381                         rte_free(filter);
6382                         return ret;
6383                 }
6384         } else
6385                 ixgbe_remove_5tuple_filter(dev, filter);
6386
6387         return 0;
6388 }
6389
6390 /*
6391  * get a ntuple filter
6392  *
6393  * @param
6394  * dev: Pointer to struct rte_eth_dev.
6395  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6396  *
6397  * @return
6398  *    - On success, zero.
6399  *    - On failure, a negative value.
6400  */
6401 static int
6402 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6403                         struct rte_eth_ntuple_filter *ntuple_filter)
6404 {
6405         struct ixgbe_filter_info *filter_info =
6406                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6407         struct ixgbe_5tuple_filter_info filter_5tuple;
6408         struct ixgbe_5tuple_filter *filter;
6409         int ret;
6410
6411         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6412                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6413                 return -EINVAL;
6414         }
6415
6416         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6417         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6418         if (ret < 0)
6419                 return ret;
6420
6421         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6422                                          &filter_5tuple);
6423         if (filter == NULL) {
6424                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6425                 return -ENOENT;
6426         }
6427         ntuple_filter->queue = filter->queue;
6428         return 0;
6429 }
6430
6431 /*
6432  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6433  * @dev: pointer to rte_eth_dev structure
6434  * @filter_op:operation will be taken.
6435  * @arg: a pointer to specific structure corresponding to the filter_op
6436  *
6437  * @return
6438  *    - On success, zero.
6439  *    - On failure, a negative value.
6440  */
6441 static int
6442 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6443                                 enum rte_filter_op filter_op,
6444                                 void *arg)
6445 {
6446         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6447         int ret;
6448
6449         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6450
6451         if (filter_op == RTE_ETH_FILTER_NOP)
6452                 return 0;
6453
6454         if (arg == NULL) {
6455                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6456                             filter_op);
6457                 return -EINVAL;
6458         }
6459
6460         switch (filter_op) {
6461         case RTE_ETH_FILTER_ADD:
6462                 ret = ixgbe_add_del_ntuple_filter(dev,
6463                         (struct rte_eth_ntuple_filter *)arg,
6464                         TRUE);
6465                 break;
6466         case RTE_ETH_FILTER_DELETE:
6467                 ret = ixgbe_add_del_ntuple_filter(dev,
6468                         (struct rte_eth_ntuple_filter *)arg,
6469                         FALSE);
6470                 break;
6471         case RTE_ETH_FILTER_GET:
6472                 ret = ixgbe_get_ntuple_filter(dev,
6473                         (struct rte_eth_ntuple_filter *)arg);
6474                 break;
6475         default:
6476                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6477                 ret = -EINVAL;
6478                 break;
6479         }
6480         return ret;
6481 }
6482
6483 static int
6484 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6485                         struct rte_eth_ethertype_filter *filter,
6486                         bool add)
6487 {
6488         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6489         struct ixgbe_filter_info *filter_info =
6490                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6491         uint32_t etqf = 0;
6492         uint32_t etqs = 0;
6493         int ret;
6494         struct ixgbe_ethertype_filter ethertype_filter;
6495
6496         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6497                 return -EINVAL;
6498
6499         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6500                 filter->ether_type == ETHER_TYPE_IPv6) {
6501                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6502                         " ethertype filter.", filter->ether_type);
6503                 return -EINVAL;
6504         }
6505
6506         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6507                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6508                 return -EINVAL;
6509         }
6510         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6511                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6512                 return -EINVAL;
6513         }
6514
6515         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6516         if (ret >= 0 && add) {
6517                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6518                             filter->ether_type);
6519                 return -EEXIST;
6520         }
6521         if (ret < 0 && !add) {
6522                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6523                             filter->ether_type);
6524                 return -ENOENT;
6525         }
6526
6527         if (add) {
6528                 etqf = IXGBE_ETQF_FILTER_EN;
6529                 etqf |= (uint32_t)filter->ether_type;
6530                 etqs |= (uint32_t)((filter->queue <<
6531                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6532                                     IXGBE_ETQS_RX_QUEUE);
6533                 etqs |= IXGBE_ETQS_QUEUE_EN;
6534
6535                 ethertype_filter.ethertype = filter->ether_type;
6536                 ethertype_filter.etqf = etqf;
6537                 ethertype_filter.etqs = etqs;
6538                 ethertype_filter.conf = FALSE;
6539                 ret = ixgbe_ethertype_filter_insert(filter_info,
6540                                                     &ethertype_filter);
6541                 if (ret < 0) {
6542                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6543                         return -ENOSPC;
6544                 }
6545         } else {
6546                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6547                 if (ret < 0)
6548                         return -ENOSYS;
6549         }
6550         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6551         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6552         IXGBE_WRITE_FLUSH(hw);
6553
6554         return 0;
6555 }
6556
6557 static int
6558 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6559                         struct rte_eth_ethertype_filter *filter)
6560 {
6561         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6562         struct ixgbe_filter_info *filter_info =
6563                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6564         uint32_t etqf, etqs;
6565         int ret;
6566
6567         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6568         if (ret < 0) {
6569                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6570                             filter->ether_type);
6571                 return -ENOENT;
6572         }
6573
6574         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6575         if (etqf & IXGBE_ETQF_FILTER_EN) {
6576                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6577                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6578                 filter->flags = 0;
6579                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6580                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6581                 return 0;
6582         }
6583         return -ENOENT;
6584 }
6585
6586 /*
6587  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6588  * @dev: pointer to rte_eth_dev structure
6589  * @filter_op:operation will be taken.
6590  * @arg: a pointer to specific structure corresponding to the filter_op
6591  */
6592 static int
6593 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6594                                 enum rte_filter_op filter_op,
6595                                 void *arg)
6596 {
6597         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6598         int ret;
6599
6600         MAC_TYPE_FILTER_SUP(hw->mac.type);
6601
6602         if (filter_op == RTE_ETH_FILTER_NOP)
6603                 return 0;
6604
6605         if (arg == NULL) {
6606                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6607                             filter_op);
6608                 return -EINVAL;
6609         }
6610
6611         switch (filter_op) {
6612         case RTE_ETH_FILTER_ADD:
6613                 ret = ixgbe_add_del_ethertype_filter(dev,
6614                         (struct rte_eth_ethertype_filter *)arg,
6615                         TRUE);
6616                 break;
6617         case RTE_ETH_FILTER_DELETE:
6618                 ret = ixgbe_add_del_ethertype_filter(dev,
6619                         (struct rte_eth_ethertype_filter *)arg,
6620                         FALSE);
6621                 break;
6622         case RTE_ETH_FILTER_GET:
6623                 ret = ixgbe_get_ethertype_filter(dev,
6624                         (struct rte_eth_ethertype_filter *)arg);
6625                 break;
6626         default:
6627                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6628                 ret = -EINVAL;
6629                 break;
6630         }
6631         return ret;
6632 }
6633
6634 static int
6635 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6636                      enum rte_filter_type filter_type,
6637                      enum rte_filter_op filter_op,
6638                      void *arg)
6639 {
6640         int ret = 0;
6641
6642         switch (filter_type) {
6643         case RTE_ETH_FILTER_NTUPLE:
6644                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6645                 break;
6646         case RTE_ETH_FILTER_ETHERTYPE:
6647                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6648                 break;
6649         case RTE_ETH_FILTER_SYN:
6650                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6651                 break;
6652         case RTE_ETH_FILTER_FDIR:
6653                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6654                 break;
6655         case RTE_ETH_FILTER_L2_TUNNEL:
6656                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6657                 break;
6658         case RTE_ETH_FILTER_GENERIC:
6659                 if (filter_op != RTE_ETH_FILTER_GET)
6660                         return -EINVAL;
6661                 *(const void **)arg = &ixgbe_flow_ops;
6662                 break;
6663         default:
6664                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6665                                                         filter_type);
6666                 ret = -EINVAL;
6667                 break;
6668         }
6669
6670         return ret;
6671 }
6672
6673 static u8 *
6674 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6675                         u8 **mc_addr_ptr, u32 *vmdq)
6676 {
6677         u8 *mc_addr;
6678
6679         *vmdq = 0;
6680         mc_addr = *mc_addr_ptr;
6681         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6682         return mc_addr;
6683 }
6684
6685 static int
6686 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6687                           struct ether_addr *mc_addr_set,
6688                           uint32_t nb_mc_addr)
6689 {
6690         struct ixgbe_hw *hw;
6691         u8 *mc_addr_list;
6692
6693         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6694         mc_addr_list = (u8 *)mc_addr_set;
6695         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6696                                          ixgbe_dev_addr_list_itr, TRUE);
6697 }
6698
6699 static uint64_t
6700 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6701 {
6702         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6703         uint64_t systime_cycles;
6704
6705         switch (hw->mac.type) {
6706         case ixgbe_mac_X550:
6707         case ixgbe_mac_X550EM_x:
6708         case ixgbe_mac_X550EM_a:
6709                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6710                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6711                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6712                                 * NSEC_PER_SEC;
6713                 break;
6714         default:
6715                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6716                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6717                                 << 32;
6718         }
6719
6720         return systime_cycles;
6721 }
6722
6723 static uint64_t
6724 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6725 {
6726         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6727         uint64_t rx_tstamp_cycles;
6728
6729         switch (hw->mac.type) {
6730         case ixgbe_mac_X550:
6731         case ixgbe_mac_X550EM_x:
6732         case ixgbe_mac_X550EM_a:
6733                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6734                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6735                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6736                                 * NSEC_PER_SEC;
6737                 break;
6738         default:
6739                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6740                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6741                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6742                                 << 32;
6743         }
6744
6745         return rx_tstamp_cycles;
6746 }
6747
6748 static uint64_t
6749 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6750 {
6751         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6752         uint64_t tx_tstamp_cycles;
6753
6754         switch (hw->mac.type) {
6755         case ixgbe_mac_X550:
6756         case ixgbe_mac_X550EM_x:
6757         case ixgbe_mac_X550EM_a:
6758                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6759                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6760                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6761                                 * NSEC_PER_SEC;
6762                 break;
6763         default:
6764                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6765                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6766                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6767                                 << 32;
6768         }
6769
6770         return tx_tstamp_cycles;
6771 }
6772
6773 static void
6774 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6775 {
6776         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6777         struct ixgbe_adapter *adapter =
6778                 (struct ixgbe_adapter *)dev->data->dev_private;
6779         struct rte_eth_link link;
6780         uint32_t incval = 0;
6781         uint32_t shift = 0;
6782
6783         /* Get current link speed. */
6784         memset(&link, 0, sizeof(link));
6785         ixgbe_dev_link_update(dev, 1);
6786         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6787
6788         switch (link.link_speed) {
6789         case ETH_SPEED_NUM_100M:
6790                 incval = IXGBE_INCVAL_100;
6791                 shift = IXGBE_INCVAL_SHIFT_100;
6792                 break;
6793         case ETH_SPEED_NUM_1G:
6794                 incval = IXGBE_INCVAL_1GB;
6795                 shift = IXGBE_INCVAL_SHIFT_1GB;
6796                 break;
6797         case ETH_SPEED_NUM_10G:
6798         default:
6799                 incval = IXGBE_INCVAL_10GB;
6800                 shift = IXGBE_INCVAL_SHIFT_10GB;
6801                 break;
6802         }
6803
6804         switch (hw->mac.type) {
6805         case ixgbe_mac_X550:
6806         case ixgbe_mac_X550EM_x:
6807         case ixgbe_mac_X550EM_a:
6808                 /* Independent of link speed. */
6809                 incval = 1;
6810                 /* Cycles read will be interpreted as ns. */
6811                 shift = 0;
6812                 /* Fall-through */
6813         case ixgbe_mac_X540:
6814                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6815                 break;
6816         case ixgbe_mac_82599EB:
6817                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6818                 shift -= IXGBE_INCVAL_SHIFT_82599;
6819                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6820                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6821                 break;
6822         default:
6823                 /* Not supported. */
6824                 return;
6825         }
6826
6827         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6828         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6829         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6830
6831         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6832         adapter->systime_tc.cc_shift = shift;
6833         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6834
6835         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6836         adapter->rx_tstamp_tc.cc_shift = shift;
6837         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6838
6839         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6840         adapter->tx_tstamp_tc.cc_shift = shift;
6841         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6842 }
6843
6844 static int
6845 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6846 {
6847         struct ixgbe_adapter *adapter =
6848                         (struct ixgbe_adapter *)dev->data->dev_private;
6849
6850         adapter->systime_tc.nsec += delta;
6851         adapter->rx_tstamp_tc.nsec += delta;
6852         adapter->tx_tstamp_tc.nsec += delta;
6853
6854         return 0;
6855 }
6856
6857 static int
6858 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6859 {
6860         uint64_t ns;
6861         struct ixgbe_adapter *adapter =
6862                         (struct ixgbe_adapter *)dev->data->dev_private;
6863
6864         ns = rte_timespec_to_ns(ts);
6865         /* Set the timecounters to a new value. */
6866         adapter->systime_tc.nsec = ns;
6867         adapter->rx_tstamp_tc.nsec = ns;
6868         adapter->tx_tstamp_tc.nsec = ns;
6869
6870         return 0;
6871 }
6872
6873 static int
6874 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6875 {
6876         uint64_t ns, systime_cycles;
6877         struct ixgbe_adapter *adapter =
6878                         (struct ixgbe_adapter *)dev->data->dev_private;
6879
6880         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6881         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6882         *ts = rte_ns_to_timespec(ns);
6883
6884         return 0;
6885 }
6886
6887 static int
6888 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6889 {
6890         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6891         uint32_t tsync_ctl;
6892         uint32_t tsauxc;
6893
6894         /* Stop the timesync system time. */
6895         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6896         /* Reset the timesync system time value. */
6897         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6898         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6899
6900         /* Enable system time for platforms where it isn't on by default. */
6901         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6902         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6903         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6904
6905         ixgbe_start_timecounters(dev);
6906
6907         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6908         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6909                         (ETHER_TYPE_1588 |
6910                          IXGBE_ETQF_FILTER_EN |
6911                          IXGBE_ETQF_1588));
6912
6913         /* Enable timestamping of received PTP packets. */
6914         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6915         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6916         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6917
6918         /* Enable timestamping of transmitted PTP packets. */
6919         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6920         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6921         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6922
6923         IXGBE_WRITE_FLUSH(hw);
6924
6925         return 0;
6926 }
6927
6928 static int
6929 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6930 {
6931         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6932         uint32_t tsync_ctl;
6933
6934         /* Disable timestamping of transmitted PTP packets. */
6935         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6936         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6937         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6938
6939         /* Disable timestamping of received PTP packets. */
6940         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6941         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6942         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6943
6944         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6945         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6946
6947         /* Stop incrementating the System Time registers. */
6948         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6949
6950         return 0;
6951 }
6952
6953 static int
6954 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6955                                  struct timespec *timestamp,
6956                                  uint32_t flags __rte_unused)
6957 {
6958         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6959         struct ixgbe_adapter *adapter =
6960                 (struct ixgbe_adapter *)dev->data->dev_private;
6961         uint32_t tsync_rxctl;
6962         uint64_t rx_tstamp_cycles;
6963         uint64_t ns;
6964
6965         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6966         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6967                 return -EINVAL;
6968
6969         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6970         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6971         *timestamp = rte_ns_to_timespec(ns);
6972
6973         return  0;
6974 }
6975
6976 static int
6977 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6978                                  struct timespec *timestamp)
6979 {
6980         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6981         struct ixgbe_adapter *adapter =
6982                 (struct ixgbe_adapter *)dev->data->dev_private;
6983         uint32_t tsync_txctl;
6984         uint64_t tx_tstamp_cycles;
6985         uint64_t ns;
6986
6987         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6988         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6989                 return -EINVAL;
6990
6991         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6992         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6993         *timestamp = rte_ns_to_timespec(ns);
6994
6995         return 0;
6996 }
6997
6998 static int
6999 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7000 {
7001         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7002         int count = 0;
7003         int g_ind = 0;
7004         const struct reg_info *reg_group;
7005         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7006                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7007
7008         while ((reg_group = reg_set[g_ind++]))
7009                 count += ixgbe_regs_group_count(reg_group);
7010
7011         return count;
7012 }
7013
7014 static int
7015 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7016 {
7017         int count = 0;
7018         int g_ind = 0;
7019         const struct reg_info *reg_group;
7020
7021         while ((reg_group = ixgbevf_regs[g_ind++]))
7022                 count += ixgbe_regs_group_count(reg_group);
7023
7024         return count;
7025 }
7026
7027 static int
7028 ixgbe_get_regs(struct rte_eth_dev *dev,
7029               struct rte_dev_reg_info *regs)
7030 {
7031         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7032         uint32_t *data = regs->data;
7033         int g_ind = 0;
7034         int count = 0;
7035         const struct reg_info *reg_group;
7036         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7037                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7038
7039         if (data == NULL) {
7040                 regs->length = ixgbe_get_reg_length(dev);
7041                 regs->width = sizeof(uint32_t);
7042                 return 0;
7043         }
7044
7045         /* Support only full register dump */
7046         if ((regs->length == 0) ||
7047             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7048                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7049                         hw->device_id;
7050                 while ((reg_group = reg_set[g_ind++]))
7051                         count += ixgbe_read_regs_group(dev, &data[count],
7052                                 reg_group);
7053                 return 0;
7054         }
7055
7056         return -ENOTSUP;
7057 }
7058
7059 static int
7060 ixgbevf_get_regs(struct rte_eth_dev *dev,
7061                 struct rte_dev_reg_info *regs)
7062 {
7063         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7064         uint32_t *data = regs->data;
7065         int g_ind = 0;
7066         int count = 0;
7067         const struct reg_info *reg_group;
7068
7069         if (data == NULL) {
7070                 regs->length = ixgbevf_get_reg_length(dev);
7071                 regs->width = sizeof(uint32_t);
7072                 return 0;
7073         }
7074
7075         /* Support only full register dump */
7076         if ((regs->length == 0) ||
7077             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7078                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7079                         hw->device_id;
7080                 while ((reg_group = ixgbevf_regs[g_ind++]))
7081                         count += ixgbe_read_regs_group(dev, &data[count],
7082                                                       reg_group);
7083                 return 0;
7084         }
7085
7086         return -ENOTSUP;
7087 }
7088
7089 static int
7090 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7091 {
7092         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7093
7094         /* Return unit is byte count */
7095         return hw->eeprom.word_size * 2;
7096 }
7097
7098 static int
7099 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7100                 struct rte_dev_eeprom_info *in_eeprom)
7101 {
7102         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7103         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7104         uint16_t *data = in_eeprom->data;
7105         int first, length;
7106
7107         first = in_eeprom->offset >> 1;
7108         length = in_eeprom->length >> 1;
7109         if ((first > hw->eeprom.word_size) ||
7110             ((first + length) > hw->eeprom.word_size))
7111                 return -EINVAL;
7112
7113         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7114
7115         return eeprom->ops.read_buffer(hw, first, length, data);
7116 }
7117
7118 static int
7119 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7120                 struct rte_dev_eeprom_info *in_eeprom)
7121 {
7122         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7123         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7124         uint16_t *data = in_eeprom->data;
7125         int first, length;
7126
7127         first = in_eeprom->offset >> 1;
7128         length = in_eeprom->length >> 1;
7129         if ((first > hw->eeprom.word_size) ||
7130             ((first + length) > hw->eeprom.word_size))
7131                 return -EINVAL;
7132
7133         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7134
7135         return eeprom->ops.write_buffer(hw,  first, length, data);
7136 }
7137
7138 uint16_t
7139 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7140         switch (mac_type) {
7141         case ixgbe_mac_X550:
7142         case ixgbe_mac_X550EM_x:
7143         case ixgbe_mac_X550EM_a:
7144                 return ETH_RSS_RETA_SIZE_512;
7145         case ixgbe_mac_X550_vf:
7146         case ixgbe_mac_X550EM_x_vf:
7147         case ixgbe_mac_X550EM_a_vf:
7148                 return ETH_RSS_RETA_SIZE_64;
7149         default:
7150                 return ETH_RSS_RETA_SIZE_128;
7151         }
7152 }
7153
7154 uint32_t
7155 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7156         switch (mac_type) {
7157         case ixgbe_mac_X550:
7158         case ixgbe_mac_X550EM_x:
7159         case ixgbe_mac_X550EM_a:
7160                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7161                         return IXGBE_RETA(reta_idx >> 2);
7162                 else
7163                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7164         case ixgbe_mac_X550_vf:
7165         case ixgbe_mac_X550EM_x_vf:
7166         case ixgbe_mac_X550EM_a_vf:
7167                 return IXGBE_VFRETA(reta_idx >> 2);
7168         default:
7169                 return IXGBE_RETA(reta_idx >> 2);
7170         }
7171 }
7172
7173 uint32_t
7174 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7175         switch (mac_type) {
7176         case ixgbe_mac_X550_vf:
7177         case ixgbe_mac_X550EM_x_vf:
7178         case ixgbe_mac_X550EM_a_vf:
7179                 return IXGBE_VFMRQC;
7180         default:
7181                 return IXGBE_MRQC;
7182         }
7183 }
7184
7185 uint32_t
7186 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7187         switch (mac_type) {
7188         case ixgbe_mac_X550_vf:
7189         case ixgbe_mac_X550EM_x_vf:
7190         case ixgbe_mac_X550EM_a_vf:
7191                 return IXGBE_VFRSSRK(i);
7192         default:
7193                 return IXGBE_RSSRK(i);
7194         }
7195 }
7196
7197 bool
7198 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7199         switch (mac_type) {
7200         case ixgbe_mac_82599_vf:
7201         case ixgbe_mac_X540_vf:
7202                 return 0;
7203         default:
7204                 return 1;
7205         }
7206 }
7207
7208 static int
7209 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7210                         struct rte_eth_dcb_info *dcb_info)
7211 {
7212         struct ixgbe_dcb_config *dcb_config =
7213                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7214         struct ixgbe_dcb_tc_config *tc;
7215         uint8_t i, j;
7216
7217         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7218                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7219         else
7220                 dcb_info->nb_tcs = 1;
7221
7222         if (dcb_config->vt_mode) { /* vt is enabled*/
7223                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7224                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7225                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7226                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7227                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7228                         for (j = 0; j < dcb_info->nb_tcs; j++) {
7229                                 dcb_info->tc_queue.tc_rxq[i][j].base =
7230                                                 i * dcb_info->nb_tcs + j;
7231                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7232                                 dcb_info->tc_queue.tc_txq[i][j].base =
7233                                                 i * dcb_info->nb_tcs + j;
7234                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7235                         }
7236                 }
7237         } else { /* vt is disabled*/
7238                 struct rte_eth_dcb_rx_conf *rx_conf =
7239                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7240                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7241                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7242                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7243                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7244                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7245                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7246                         }
7247                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7248                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7249                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7250                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7251                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7252                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7253                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7254                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7255                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7256                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7257                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7258                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7259                         }
7260                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7261                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7262                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7263                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7264                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7265                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7266                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7267                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7268                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7269                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7270                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7271                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7272                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7273                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7274                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7275                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7276                 }
7277         }
7278         for (i = 0; i < dcb_info->nb_tcs; i++) {
7279                 tc = &dcb_config->tc_config[i];
7280                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7281         }
7282         return 0;
7283 }
7284
7285 /* Update e-tag ether type */
7286 static int
7287 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7288                             uint16_t ether_type)
7289 {
7290         uint32_t etag_etype;
7291
7292         if (hw->mac.type != ixgbe_mac_X550 &&
7293             hw->mac.type != ixgbe_mac_X550EM_x &&
7294             hw->mac.type != ixgbe_mac_X550EM_a) {
7295                 return -ENOTSUP;
7296         }
7297
7298         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7299         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7300         etag_etype |= ether_type;
7301         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7302         IXGBE_WRITE_FLUSH(hw);
7303
7304         return 0;
7305 }
7306
7307 /* Config l2 tunnel ether type */
7308 static int
7309 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7310                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7311 {
7312         int ret = 0;
7313         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7314         struct ixgbe_l2_tn_info *l2_tn_info =
7315                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7316
7317         if (l2_tunnel == NULL)
7318                 return -EINVAL;
7319
7320         switch (l2_tunnel->l2_tunnel_type) {
7321         case RTE_L2_TUNNEL_TYPE_E_TAG:
7322                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7323                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7324                 break;
7325         default:
7326                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7327                 ret = -EINVAL;
7328                 break;
7329         }
7330
7331         return ret;
7332 }
7333
7334 /* Enable e-tag tunnel */
7335 static int
7336 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7337 {
7338         uint32_t etag_etype;
7339
7340         if (hw->mac.type != ixgbe_mac_X550 &&
7341             hw->mac.type != ixgbe_mac_X550EM_x &&
7342             hw->mac.type != ixgbe_mac_X550EM_a) {
7343                 return -ENOTSUP;
7344         }
7345
7346         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7347         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7348         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7349         IXGBE_WRITE_FLUSH(hw);
7350
7351         return 0;
7352 }
7353
7354 /* Enable l2 tunnel */
7355 static int
7356 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7357                            enum rte_eth_tunnel_type l2_tunnel_type)
7358 {
7359         int ret = 0;
7360         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7361         struct ixgbe_l2_tn_info *l2_tn_info =
7362                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7363
7364         switch (l2_tunnel_type) {
7365         case RTE_L2_TUNNEL_TYPE_E_TAG:
7366                 l2_tn_info->e_tag_en = TRUE;
7367                 ret = ixgbe_e_tag_enable(hw);
7368                 break;
7369         default:
7370                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7371                 ret = -EINVAL;
7372                 break;
7373         }
7374
7375         return ret;
7376 }
7377
7378 /* Disable e-tag tunnel */
7379 static int
7380 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7381 {
7382         uint32_t etag_etype;
7383
7384         if (hw->mac.type != ixgbe_mac_X550 &&
7385             hw->mac.type != ixgbe_mac_X550EM_x &&
7386             hw->mac.type != ixgbe_mac_X550EM_a) {
7387                 return -ENOTSUP;
7388         }
7389
7390         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7391         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7392         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7393         IXGBE_WRITE_FLUSH(hw);
7394
7395         return 0;
7396 }
7397
7398 /* Disable l2 tunnel */
7399 static int
7400 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7401                             enum rte_eth_tunnel_type l2_tunnel_type)
7402 {
7403         int ret = 0;
7404         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7405         struct ixgbe_l2_tn_info *l2_tn_info =
7406                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7407
7408         switch (l2_tunnel_type) {
7409         case RTE_L2_TUNNEL_TYPE_E_TAG:
7410                 l2_tn_info->e_tag_en = FALSE;
7411                 ret = ixgbe_e_tag_disable(hw);
7412                 break;
7413         default:
7414                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7415                 ret = -EINVAL;
7416                 break;
7417         }
7418
7419         return ret;
7420 }
7421
7422 static int
7423 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7424                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7425 {
7426         int ret = 0;
7427         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7428         uint32_t i, rar_entries;
7429         uint32_t rar_low, rar_high;
7430
7431         if (hw->mac.type != ixgbe_mac_X550 &&
7432             hw->mac.type != ixgbe_mac_X550EM_x &&
7433             hw->mac.type != ixgbe_mac_X550EM_a) {
7434                 return -ENOTSUP;
7435         }
7436
7437         rar_entries = ixgbe_get_num_rx_addrs(hw);
7438
7439         for (i = 1; i < rar_entries; i++) {
7440                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7441                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7442                 if ((rar_high & IXGBE_RAH_AV) &&
7443                     (rar_high & IXGBE_RAH_ADTYPE) &&
7444                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7445                      l2_tunnel->tunnel_id)) {
7446                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7447                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7448
7449                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7450
7451                         return ret;
7452                 }
7453         }
7454
7455         return ret;
7456 }
7457
7458 static int
7459 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7460                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7461 {
7462         int ret = 0;
7463         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7464         uint32_t i, rar_entries;
7465         uint32_t rar_low, rar_high;
7466
7467         if (hw->mac.type != ixgbe_mac_X550 &&
7468             hw->mac.type != ixgbe_mac_X550EM_x &&
7469             hw->mac.type != ixgbe_mac_X550EM_a) {
7470                 return -ENOTSUP;
7471         }
7472
7473         /* One entry for one tunnel. Try to remove potential existing entry. */
7474         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7475
7476         rar_entries = ixgbe_get_num_rx_addrs(hw);
7477
7478         for (i = 1; i < rar_entries; i++) {
7479                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7480                 if (rar_high & IXGBE_RAH_AV) {
7481                         continue;
7482                 } else {
7483                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7484                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7485                         rar_low = l2_tunnel->tunnel_id;
7486
7487                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7488                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7489
7490                         return ret;
7491                 }
7492         }
7493
7494         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7495                      " Please remove a rule before adding a new one.");
7496         return -EINVAL;
7497 }
7498
7499 static inline struct ixgbe_l2_tn_filter *
7500 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7501                           struct ixgbe_l2_tn_key *key)
7502 {
7503         int ret;
7504
7505         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7506         if (ret < 0)
7507                 return NULL;
7508
7509         return l2_tn_info->hash_map[ret];
7510 }
7511
7512 static inline int
7513 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7514                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7515 {
7516         int ret;
7517
7518         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7519                                &l2_tn_filter->key);
7520
7521         if (ret < 0) {
7522                 PMD_DRV_LOG(ERR,
7523                             "Failed to insert L2 tunnel filter"
7524                             " to hash table %d!",
7525                             ret);
7526                 return ret;
7527         }
7528
7529         l2_tn_info->hash_map[ret] = l2_tn_filter;
7530
7531         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7532
7533         return 0;
7534 }
7535
7536 static inline int
7537 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7538                           struct ixgbe_l2_tn_key *key)
7539 {
7540         int ret;
7541         struct ixgbe_l2_tn_filter *l2_tn_filter;
7542
7543         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7544
7545         if (ret < 0) {
7546                 PMD_DRV_LOG(ERR,
7547                             "No such L2 tunnel filter to delete %d!",
7548                             ret);
7549                 return ret;
7550         }
7551
7552         l2_tn_filter = l2_tn_info->hash_map[ret];
7553         l2_tn_info->hash_map[ret] = NULL;
7554
7555         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7556         rte_free(l2_tn_filter);
7557
7558         return 0;
7559 }
7560
7561 /* Add l2 tunnel filter */
7562 static int
7563 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7564                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7565                                bool restore)
7566 {
7567         int ret;
7568         struct ixgbe_l2_tn_info *l2_tn_info =
7569                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7570         struct ixgbe_l2_tn_key key;
7571         struct ixgbe_l2_tn_filter *node;
7572
7573         if (!restore) {
7574                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7575                 key.tn_id = l2_tunnel->tunnel_id;
7576
7577                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7578
7579                 if (node) {
7580                         PMD_DRV_LOG(ERR,
7581                                     "The L2 tunnel filter already exists!");
7582                         return -EINVAL;
7583                 }
7584
7585                 node = rte_zmalloc("ixgbe_l2_tn",
7586                                    sizeof(struct ixgbe_l2_tn_filter),
7587                                    0);
7588                 if (!node)
7589                         return -ENOMEM;
7590
7591                 (void)rte_memcpy(&node->key,
7592                                  &key,
7593                                  sizeof(struct ixgbe_l2_tn_key));
7594                 node->pool = l2_tunnel->pool;
7595                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7596                 if (ret < 0) {
7597                         rte_free(node);
7598                         return ret;
7599                 }
7600         }
7601
7602         switch (l2_tunnel->l2_tunnel_type) {
7603         case RTE_L2_TUNNEL_TYPE_E_TAG:
7604                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7605                 break;
7606         default:
7607                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7608                 ret = -EINVAL;
7609                 break;
7610         }
7611
7612         if ((!restore) && (ret < 0))
7613                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7614
7615         return ret;
7616 }
7617
7618 /* Delete l2 tunnel filter */
7619 static int
7620 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7621                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7622 {
7623         int ret;
7624         struct ixgbe_l2_tn_info *l2_tn_info =
7625                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7626         struct ixgbe_l2_tn_key key;
7627
7628         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7629         key.tn_id = l2_tunnel->tunnel_id;
7630         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7631         if (ret < 0)
7632                 return ret;
7633
7634         switch (l2_tunnel->l2_tunnel_type) {
7635         case RTE_L2_TUNNEL_TYPE_E_TAG:
7636                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7637                 break;
7638         default:
7639                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7640                 ret = -EINVAL;
7641                 break;
7642         }
7643
7644         return ret;
7645 }
7646
7647 /**
7648  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7649  * @dev: pointer to rte_eth_dev structure
7650  * @filter_op:operation will be taken.
7651  * @arg: a pointer to specific structure corresponding to the filter_op
7652  */
7653 static int
7654 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7655                                   enum rte_filter_op filter_op,
7656                                   void *arg)
7657 {
7658         int ret;
7659
7660         if (filter_op == RTE_ETH_FILTER_NOP)
7661                 return 0;
7662
7663         if (arg == NULL) {
7664                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7665                             filter_op);
7666                 return -EINVAL;
7667         }
7668
7669         switch (filter_op) {
7670         case RTE_ETH_FILTER_ADD:
7671                 ret = ixgbe_dev_l2_tunnel_filter_add
7672                         (dev,
7673                          (struct rte_eth_l2_tunnel_conf *)arg,
7674                          FALSE);
7675                 break;
7676         case RTE_ETH_FILTER_DELETE:
7677                 ret = ixgbe_dev_l2_tunnel_filter_del
7678                         (dev,
7679                          (struct rte_eth_l2_tunnel_conf *)arg);
7680                 break;
7681         default:
7682                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7683                 ret = -EINVAL;
7684                 break;
7685         }
7686         return ret;
7687 }
7688
7689 static int
7690 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7691 {
7692         int ret = 0;
7693         uint32_t ctrl;
7694         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7695
7696         if (hw->mac.type != ixgbe_mac_X550 &&
7697             hw->mac.type != ixgbe_mac_X550EM_x &&
7698             hw->mac.type != ixgbe_mac_X550EM_a) {
7699                 return -ENOTSUP;
7700         }
7701
7702         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7703         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7704         if (en)
7705                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7706         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7707
7708         return ret;
7709 }
7710
7711 /* Enable l2 tunnel forwarding */
7712 static int
7713 ixgbe_dev_l2_tunnel_forwarding_enable
7714         (struct rte_eth_dev *dev,
7715          enum rte_eth_tunnel_type l2_tunnel_type)
7716 {
7717         struct ixgbe_l2_tn_info *l2_tn_info =
7718                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7719         int ret = 0;
7720
7721         switch (l2_tunnel_type) {
7722         case RTE_L2_TUNNEL_TYPE_E_TAG:
7723                 l2_tn_info->e_tag_fwd_en = TRUE;
7724                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7725                 break;
7726         default:
7727                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7728                 ret = -EINVAL;
7729                 break;
7730         }
7731
7732         return ret;
7733 }
7734
7735 /* Disable l2 tunnel forwarding */
7736 static int
7737 ixgbe_dev_l2_tunnel_forwarding_disable
7738         (struct rte_eth_dev *dev,
7739          enum rte_eth_tunnel_type l2_tunnel_type)
7740 {
7741         struct ixgbe_l2_tn_info *l2_tn_info =
7742                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7743         int ret = 0;
7744
7745         switch (l2_tunnel_type) {
7746         case RTE_L2_TUNNEL_TYPE_E_TAG:
7747                 l2_tn_info->e_tag_fwd_en = FALSE;
7748                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7749                 break;
7750         default:
7751                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7752                 ret = -EINVAL;
7753                 break;
7754         }
7755
7756         return ret;
7757 }
7758
7759 static int
7760 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7761                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7762                              bool en)
7763 {
7764         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7765         int ret = 0;
7766         uint32_t vmtir, vmvir;
7767         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7768
7769         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7770                 PMD_DRV_LOG(ERR,
7771                             "VF id %u should be less than %u",
7772                             l2_tunnel->vf_id,
7773                             pci_dev->max_vfs);
7774                 return -EINVAL;
7775         }
7776
7777         if (hw->mac.type != ixgbe_mac_X550 &&
7778             hw->mac.type != ixgbe_mac_X550EM_x &&
7779             hw->mac.type != ixgbe_mac_X550EM_a) {
7780                 return -ENOTSUP;
7781         }
7782
7783         if (en)
7784                 vmtir = l2_tunnel->tunnel_id;
7785         else
7786                 vmtir = 0;
7787
7788         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7789
7790         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7791         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7792         if (en)
7793                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7794         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7795
7796         return ret;
7797 }
7798
7799 /* Enable l2 tunnel tag insertion */
7800 static int
7801 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7802                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7803 {
7804         int ret = 0;
7805
7806         switch (l2_tunnel->l2_tunnel_type) {
7807         case RTE_L2_TUNNEL_TYPE_E_TAG:
7808                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7809                 break;
7810         default:
7811                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7812                 ret = -EINVAL;
7813                 break;
7814         }
7815
7816         return ret;
7817 }
7818
7819 /* Disable l2 tunnel tag insertion */
7820 static int
7821 ixgbe_dev_l2_tunnel_insertion_disable
7822         (struct rte_eth_dev *dev,
7823          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7824 {
7825         int ret = 0;
7826
7827         switch (l2_tunnel->l2_tunnel_type) {
7828         case RTE_L2_TUNNEL_TYPE_E_TAG:
7829                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7830                 break;
7831         default:
7832                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7833                 ret = -EINVAL;
7834                 break;
7835         }
7836
7837         return ret;
7838 }
7839
7840 static int
7841 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7842                              bool en)
7843 {
7844         int ret = 0;
7845         uint32_t qde;
7846         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7847
7848         if (hw->mac.type != ixgbe_mac_X550 &&
7849             hw->mac.type != ixgbe_mac_X550EM_x &&
7850             hw->mac.type != ixgbe_mac_X550EM_a) {
7851                 return -ENOTSUP;
7852         }
7853
7854         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7855         if (en)
7856                 qde |= IXGBE_QDE_STRIP_TAG;
7857         else
7858                 qde &= ~IXGBE_QDE_STRIP_TAG;
7859         qde &= ~IXGBE_QDE_READ;
7860         qde |= IXGBE_QDE_WRITE;
7861         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7862
7863         return ret;
7864 }
7865
7866 /* Enable l2 tunnel tag stripping */
7867 static int
7868 ixgbe_dev_l2_tunnel_stripping_enable
7869         (struct rte_eth_dev *dev,
7870          enum rte_eth_tunnel_type l2_tunnel_type)
7871 {
7872         int ret = 0;
7873
7874         switch (l2_tunnel_type) {
7875         case RTE_L2_TUNNEL_TYPE_E_TAG:
7876                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7877                 break;
7878         default:
7879                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7880                 ret = -EINVAL;
7881                 break;
7882         }
7883
7884         return ret;
7885 }
7886
7887 /* Disable l2 tunnel tag stripping */
7888 static int
7889 ixgbe_dev_l2_tunnel_stripping_disable
7890         (struct rte_eth_dev *dev,
7891          enum rte_eth_tunnel_type l2_tunnel_type)
7892 {
7893         int ret = 0;
7894
7895         switch (l2_tunnel_type) {
7896         case RTE_L2_TUNNEL_TYPE_E_TAG:
7897                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7898                 break;
7899         default:
7900                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7901                 ret = -EINVAL;
7902                 break;
7903         }
7904
7905         return ret;
7906 }
7907
7908 /* Enable/disable l2 tunnel offload functions */
7909 static int
7910 ixgbe_dev_l2_tunnel_offload_set
7911         (struct rte_eth_dev *dev,
7912          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7913          uint32_t mask,
7914          uint8_t en)
7915 {
7916         int ret = 0;
7917
7918         if (l2_tunnel == NULL)
7919                 return -EINVAL;
7920
7921         ret = -EINVAL;
7922         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7923                 if (en)
7924                         ret = ixgbe_dev_l2_tunnel_enable(
7925                                 dev,
7926                                 l2_tunnel->l2_tunnel_type);
7927                 else
7928                         ret = ixgbe_dev_l2_tunnel_disable(
7929                                 dev,
7930                                 l2_tunnel->l2_tunnel_type);
7931         }
7932
7933         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7934                 if (en)
7935                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7936                                 dev,
7937                                 l2_tunnel);
7938                 else
7939                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7940                                 dev,
7941                                 l2_tunnel);
7942         }
7943
7944         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7945                 if (en)
7946                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7947                                 dev,
7948                                 l2_tunnel->l2_tunnel_type);
7949                 else
7950                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7951                                 dev,
7952                                 l2_tunnel->l2_tunnel_type);
7953         }
7954
7955         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7956                 if (en)
7957                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7958                                 dev,
7959                                 l2_tunnel->l2_tunnel_type);
7960                 else
7961                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7962                                 dev,
7963                                 l2_tunnel->l2_tunnel_type);
7964         }
7965
7966         return ret;
7967 }
7968
7969 static int
7970 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7971                         uint16_t port)
7972 {
7973         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7974         IXGBE_WRITE_FLUSH(hw);
7975
7976         return 0;
7977 }
7978
7979 /* There's only one register for VxLAN UDP port.
7980  * So, we cannot add several ports. Will update it.
7981  */
7982 static int
7983 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7984                      uint16_t port)
7985 {
7986         if (port == 0) {
7987                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7988                 return -EINVAL;
7989         }
7990
7991         return ixgbe_update_vxlan_port(hw, port);
7992 }
7993
7994 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7995  * UDP port, it must have a value.
7996  * So, will reset it to the original value 0.
7997  */
7998 static int
7999 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8000                      uint16_t port)
8001 {
8002         uint16_t cur_port;
8003
8004         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8005
8006         if (cur_port != port) {
8007                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8008                 return -EINVAL;
8009         }
8010
8011         return ixgbe_update_vxlan_port(hw, 0);
8012 }
8013
8014 /* Add UDP tunneling port */
8015 static int
8016 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8017                               struct rte_eth_udp_tunnel *udp_tunnel)
8018 {
8019         int ret = 0;
8020         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8021
8022         if (hw->mac.type != ixgbe_mac_X550 &&
8023             hw->mac.type != ixgbe_mac_X550EM_x &&
8024             hw->mac.type != ixgbe_mac_X550EM_a) {
8025                 return -ENOTSUP;
8026         }
8027
8028         if (udp_tunnel == NULL)
8029                 return -EINVAL;
8030
8031         switch (udp_tunnel->prot_type) {
8032         case RTE_TUNNEL_TYPE_VXLAN:
8033                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8034                 break;
8035
8036         case RTE_TUNNEL_TYPE_GENEVE:
8037         case RTE_TUNNEL_TYPE_TEREDO:
8038                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8039                 ret = -EINVAL;
8040                 break;
8041
8042         default:
8043                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8044                 ret = -EINVAL;
8045                 break;
8046         }
8047
8048         return ret;
8049 }
8050
8051 /* Remove UDP tunneling port */
8052 static int
8053 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8054                               struct rte_eth_udp_tunnel *udp_tunnel)
8055 {
8056         int ret = 0;
8057         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8058
8059         if (hw->mac.type != ixgbe_mac_X550 &&
8060             hw->mac.type != ixgbe_mac_X550EM_x &&
8061             hw->mac.type != ixgbe_mac_X550EM_a) {
8062                 return -ENOTSUP;
8063         }
8064
8065         if (udp_tunnel == NULL)
8066                 return -EINVAL;
8067
8068         switch (udp_tunnel->prot_type) {
8069         case RTE_TUNNEL_TYPE_VXLAN:
8070                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8071                 break;
8072         case RTE_TUNNEL_TYPE_GENEVE:
8073         case RTE_TUNNEL_TYPE_TEREDO:
8074                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8075                 ret = -EINVAL;
8076                 break;
8077         default:
8078                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8079                 ret = -EINVAL;
8080                 break;
8081         }
8082
8083         return ret;
8084 }
8085
8086 static void
8087 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8088 {
8089         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8090
8091         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8092 }
8093
8094 static void
8095 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8096 {
8097         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8098
8099         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
8100 }
8101
8102 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8103 {
8104         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8105         u32 in_msg = 0;
8106
8107         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8108                 return;
8109
8110         /* PF reset VF event */
8111         if (in_msg == IXGBE_PF_CONTROL_MSG)
8112                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
8113 }
8114
8115 static int
8116 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8117 {
8118         uint32_t eicr;
8119         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8120         struct ixgbe_interrupt *intr =
8121                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8122         ixgbevf_intr_disable(hw);
8123
8124         /* read-on-clear nic registers here */
8125         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8126         intr->flags = 0;
8127
8128         /* only one misc vector supported - mailbox */
8129         eicr &= IXGBE_VTEICR_MASK;
8130         if (eicr == IXGBE_MISC_VEC_ID)
8131                 intr->flags |= IXGBE_FLAG_MAILBOX;
8132
8133         return 0;
8134 }
8135
8136 static int
8137 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8138 {
8139         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8140         struct ixgbe_interrupt *intr =
8141                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8142
8143         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8144                 ixgbevf_mbx_process(dev);
8145                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8146         }
8147
8148         ixgbevf_intr_enable(hw);
8149
8150         return 0;
8151 }
8152
8153 static void
8154 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
8155                               void *param)
8156 {
8157         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8158
8159         ixgbevf_dev_interrupt_get_status(dev);
8160         ixgbevf_dev_interrupt_action(dev);
8161 }
8162
8163 /**
8164  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8165  *  @hw: pointer to hardware structure
8166  *
8167  *  Stops the transmit data path and waits for the HW to internally empty
8168  *  the Tx security block
8169  **/
8170 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8171 {
8172 #define IXGBE_MAX_SECTX_POLL 40
8173
8174         int i;
8175         int sectxreg;
8176
8177         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8178         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8179         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8180         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8181                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8182                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8183                         break;
8184                 /* Use interrupt-safe sleep just in case */
8185                 usec_delay(1000);
8186         }
8187
8188         /* For informational purposes only */
8189         if (i >= IXGBE_MAX_SECTX_POLL)
8190                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8191                          "path fully disabled.  Continuing with init.\n");
8192
8193         return IXGBE_SUCCESS;
8194 }
8195
8196 /**
8197  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8198  *  @hw: pointer to hardware structure
8199  *
8200  *  Enables the transmit data path.
8201  **/
8202 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8203 {
8204         uint32_t sectxreg;
8205
8206         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8207         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8208         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8209         IXGBE_WRITE_FLUSH(hw);
8210
8211         return IXGBE_SUCCESS;
8212 }
8213
8214 int
8215 rte_pmd_ixgbe_macsec_enable(uint8_t port, uint8_t en, uint8_t rp)
8216 {
8217         struct ixgbe_hw *hw;
8218         struct rte_eth_dev *dev;
8219         uint32_t ctrl;
8220
8221         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8222
8223         dev = &rte_eth_devices[port];
8224         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8225
8226         /* Stop the data paths */
8227         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8228                 return -ENOTSUP;
8229         /*
8230          * Workaround:
8231          * As no ixgbe_disable_sec_rx_path equivalent is
8232          * implemented for tx in the base code, and we are
8233          * not allowed to modify the base code in DPDK, so
8234          * just call the hand-written one directly for now.
8235          * The hardware support has been checked by
8236          * ixgbe_disable_sec_rx_path().
8237          */
8238         ixgbe_disable_sec_tx_path_generic(hw);
8239
8240         /* Enable Ethernet CRC (required by MACsec offload) */
8241         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8242         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8243         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8244
8245         /* Enable the TX and RX crypto engines */
8246         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8247         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8248         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8249
8250         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8251         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8252         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8253
8254         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8255         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8256         ctrl |= 0x3;
8257         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8258
8259         /* Enable SA lookup */
8260         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8261         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8262         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8263                      IXGBE_LSECTXCTRL_AUTH;
8264         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8265         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8266         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8267         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8268
8269         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8270         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8271         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8272         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8273         if (rp)
8274                 ctrl |= IXGBE_LSECRXCTRL_RP;
8275         else
8276                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8277         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8278
8279         /* Start the data paths */
8280         ixgbe_enable_sec_rx_path(hw);
8281         /*
8282          * Workaround:
8283          * As no ixgbe_enable_sec_rx_path equivalent is
8284          * implemented for tx in the base code, and we are
8285          * not allowed to modify the base code in DPDK, so
8286          * just call the hand-written one directly for now.
8287          */
8288         ixgbe_enable_sec_tx_path_generic(hw);
8289
8290         return 0;
8291 }
8292
8293 int
8294 rte_pmd_ixgbe_macsec_disable(uint8_t port)
8295 {
8296         struct ixgbe_hw *hw;
8297         struct rte_eth_dev *dev;
8298         uint32_t ctrl;
8299
8300         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8301
8302         dev = &rte_eth_devices[port];
8303         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8304
8305         /* Stop the data paths */
8306         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8307                 return -ENOTSUP;
8308         /*
8309          * Workaround:
8310          * As no ixgbe_disable_sec_rx_path equivalent is
8311          * implemented for tx in the base code, and we are
8312          * not allowed to modify the base code in DPDK, so
8313          * just call the hand-written one directly for now.
8314          * The hardware support has been checked by
8315          * ixgbe_disable_sec_rx_path().
8316          */
8317         ixgbe_disable_sec_tx_path_generic(hw);
8318
8319         /* Disable the TX and RX crypto engines */
8320         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8321         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8322         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8323
8324         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8325         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8326         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8327
8328         /* Disable SA lookup */
8329         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8330         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8331         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8332         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8333
8334         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8335         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8336         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8337         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8338
8339         /* Start the data paths */
8340         ixgbe_enable_sec_rx_path(hw);
8341         /*
8342          * Workaround:
8343          * As no ixgbe_enable_sec_rx_path equivalent is
8344          * implemented for tx in the base code, and we are
8345          * not allowed to modify the base code in DPDK, so
8346          * just call the hand-written one directly for now.
8347          */
8348         ixgbe_enable_sec_tx_path_generic(hw);
8349
8350         return 0;
8351 }
8352
8353 int
8354 rte_pmd_ixgbe_macsec_config_txsc(uint8_t port, uint8_t *mac)
8355 {
8356         struct ixgbe_hw *hw;
8357         struct rte_eth_dev *dev;
8358         uint32_t ctrl;
8359
8360         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8361
8362         dev = &rte_eth_devices[port];
8363         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8364
8365         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8366         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl);
8367
8368         ctrl = mac[4] | (mac[5] << 8);
8369         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl);
8370
8371         return 0;
8372 }
8373
8374 int
8375 rte_pmd_ixgbe_macsec_config_rxsc(uint8_t port, uint8_t *mac, uint16_t pi)
8376 {
8377         struct ixgbe_hw *hw;
8378         struct rte_eth_dev *dev;
8379         uint32_t ctrl;
8380
8381         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8382
8383         dev = &rte_eth_devices[port];
8384         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8385
8386         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8387         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl);
8388
8389         pi = rte_cpu_to_be_16(pi);
8390         ctrl = mac[4] | (mac[5] << 8) | (pi << 16);
8391         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl);
8392
8393         return 0;
8394 }
8395
8396 int
8397 rte_pmd_ixgbe_macsec_select_txsa(uint8_t port, uint8_t idx, uint8_t an,
8398                                  uint32_t pn, uint8_t *key)
8399 {
8400         struct ixgbe_hw *hw;
8401         struct rte_eth_dev *dev;
8402         uint32_t ctrl, i;
8403
8404         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8405
8406         dev = &rte_eth_devices[port];
8407         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8408
8409         if (idx != 0 && idx != 1)
8410                 return -EINVAL;
8411
8412         if (an >= 4)
8413                 return -EINVAL;
8414
8415         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8416
8417         /* Set the PN and key */
8418         pn = rte_cpu_to_be_32(pn);
8419         if (idx == 0) {
8420                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn);
8421
8422                 for (i = 0; i < 4; i++) {
8423                         ctrl = (key[i * 4 + 0] <<  0) |
8424                                (key[i * 4 + 1] <<  8) |
8425                                (key[i * 4 + 2] << 16) |
8426                                (key[i * 4 + 3] << 24);
8427                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl);
8428                 }
8429         } else {
8430                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn);
8431
8432                 for (i = 0; i < 4; i++) {
8433                         ctrl = (key[i * 4 + 0] <<  0) |
8434                                (key[i * 4 + 1] <<  8) |
8435                                (key[i * 4 + 2] << 16) |
8436                                (key[i * 4 + 3] << 24);
8437                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl);
8438                 }
8439         }
8440
8441         /* Set AN and select the SA */
8442         ctrl = (an << idx * 2) | (idx << 4);
8443         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl);
8444
8445         return 0;
8446 }
8447
8448 int
8449 rte_pmd_ixgbe_macsec_select_rxsa(uint8_t port, uint8_t idx, uint8_t an,
8450                                  uint32_t pn, uint8_t *key)
8451 {
8452         struct ixgbe_hw *hw;
8453         struct rte_eth_dev *dev;
8454         uint32_t ctrl, i;
8455
8456         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8457
8458         dev = &rte_eth_devices[port];
8459         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8460
8461         if (idx != 0 && idx != 1)
8462                 return -EINVAL;
8463
8464         if (an >= 4)
8465                 return -EINVAL;
8466
8467         /* Set the PN */
8468         pn = rte_cpu_to_be_32(pn);
8469         IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn);
8470
8471         /* Set the key */
8472         for (i = 0; i < 4; i++) {
8473                 ctrl = (key[i * 4 + 0] <<  0) |
8474                        (key[i * 4 + 1] <<  8) |
8475                        (key[i * 4 + 2] << 16) |
8476                        (key[i * 4 + 3] << 24);
8477                 IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl);
8478         }
8479
8480         /* Set the AN and validate the SA */
8481         ctrl = an | (1 << 2);
8482         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl);
8483
8484         return 0;
8485 }
8486
8487 /* restore n-tuple filter */
8488 static inline void
8489 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8490 {
8491         struct ixgbe_filter_info *filter_info =
8492                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8493         struct ixgbe_5tuple_filter *node;
8494
8495         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8496                 ixgbe_inject_5tuple_filter(dev, node);
8497         }
8498 }
8499
8500 /* restore ethernet type filter */
8501 static inline void
8502 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8503 {
8504         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8505         struct ixgbe_filter_info *filter_info =
8506                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8507         int i;
8508
8509         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8510                 if (filter_info->ethertype_mask & (1 << i)) {
8511                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8512                                         filter_info->ethertype_filters[i].etqf);
8513                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8514                                         filter_info->ethertype_filters[i].etqs);
8515                         IXGBE_WRITE_FLUSH(hw);
8516                 }
8517         }
8518 }
8519
8520 /* restore SYN filter */
8521 static inline void
8522 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8523 {
8524         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8525         struct ixgbe_filter_info *filter_info =
8526                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8527         uint32_t synqf;
8528
8529         synqf = filter_info->syn_info;
8530
8531         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8532                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8533                 IXGBE_WRITE_FLUSH(hw);
8534         }
8535 }
8536
8537 /* restore L2 tunnel filter */
8538 static inline void
8539 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8540 {
8541         struct ixgbe_l2_tn_info *l2_tn_info =
8542                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8543         struct ixgbe_l2_tn_filter *node;
8544         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8545
8546         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8547                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8548                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8549                 l2_tn_conf.pool           = node->pool;
8550                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8551         }
8552 }
8553
8554 static int
8555 ixgbe_filter_restore(struct rte_eth_dev *dev)
8556 {
8557         ixgbe_ntuple_filter_restore(dev);
8558         ixgbe_ethertype_filter_restore(dev);
8559         ixgbe_syn_filter_restore(dev);
8560         ixgbe_fdir_filter_restore(dev);
8561         ixgbe_l2_tn_filter_restore(dev);
8562
8563         return 0;
8564 }
8565
8566 static void
8567 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8568 {
8569         struct ixgbe_l2_tn_info *l2_tn_info =
8570                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8571         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8572
8573         if (l2_tn_info->e_tag_en)
8574                 (void)ixgbe_e_tag_enable(hw);
8575
8576         if (l2_tn_info->e_tag_fwd_en)
8577                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8578
8579         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8580 }
8581
8582 /* remove all the n-tuple filters */
8583 void
8584 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8585 {
8586         struct ixgbe_filter_info *filter_info =
8587                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8588         struct ixgbe_5tuple_filter *p_5tuple;
8589
8590         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8591                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8592 }
8593
8594 /* remove all the ether type filters */
8595 void
8596 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8597 {
8598         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8599         struct ixgbe_filter_info *filter_info =
8600                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8601         int i;
8602
8603         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8604                 if (filter_info->ethertype_mask & (1 << i) &&
8605                     !filter_info->ethertype_filters[i].conf) {
8606                         (void)ixgbe_ethertype_filter_remove(filter_info,
8607                                                             (uint8_t)i);
8608                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8609                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8610                         IXGBE_WRITE_FLUSH(hw);
8611                 }
8612         }
8613 }
8614
8615 /* remove the SYN filter */
8616 void
8617 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8618 {
8619         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8620         struct ixgbe_filter_info *filter_info =
8621                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8622
8623         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8624                 filter_info->syn_info = 0;
8625
8626                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8627                 IXGBE_WRITE_FLUSH(hw);
8628         }
8629 }
8630
8631 /* remove all the L2 tunnel filters */
8632 int
8633 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8634 {
8635         struct ixgbe_l2_tn_info *l2_tn_info =
8636                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8637         struct ixgbe_l2_tn_filter *l2_tn_filter;
8638         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8639         int ret = 0;
8640
8641         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8642                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8643                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8644                 l2_tn_conf.pool           = l2_tn_filter->pool;
8645                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8646                 if (ret < 0)
8647                         return ret;
8648         }
8649
8650         return 0;
8651 }
8652
8653 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
8654 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8655 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8656 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
8657 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8658 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");