drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_atomic.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_eal.h>
  27 #include <rte_alarm.h>
  28 #include <rte_ether.h>
  29 #include <rte_ethdev.h>
  30 #include <rte_ethdev_pci.h>
  31 #include <rte_malloc.h>
  32 #include <rte_random.h>
  33 #include <rte_dev.h>
  34 #include <rte_hash_crc.h>
  35 #ifdef RTE_LIBRTE_SECURITY
  36 #include <rte_security_driver.h>
  37 #endif
  38
  39 #include "ixgbe_logs.h"
  40 #include "base/ixgbe_api.h"
  41 #include "base/ixgbe_vf.h"
  42 #include "base/ixgbe_common.h"
  43 #include "ixgbe_ethdev.h"
  44 #include "ixgbe_bypass.h"
  45 #include "ixgbe_rxtx.h"
  46 #include "base/ixgbe_type.h"
  47 #include "base/ixgbe_phy.h"
  48 #include "ixgbe_regs.h"
  49
  50 /*
  51  * High threshold controlling when to start sending XOFF frames. Must be at
  52  * least 8 bytes less than receive packet buffer size. This value is in units
  53  * of 1024 bytes.
  54  */
  55 #define IXGBE_FC_HI    0x80
  56
  57 /*
  58  * Low threshold controlling when to start sending XON frames. This value is
  59  * in units of 1024 bytes.
  60  */
  61 #define IXGBE_FC_LO    0x40
  62
  63 /* Default minimum inter-interrupt interval for EITR configuration */
  64 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  65
  66 /* Timer value included in XOFF frames. */
  67 #define IXGBE_FC_PAUSE 0x680
  68
  69 /*Default value of Max Rx Queue*/
  70 #define IXGBE_MAX_RX_QUEUE_NUM 128
  71
  72 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  73 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  74 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  75
  76 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  77 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  78 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  79
  80 /*
  81  *  Default values for RX/TX configuration
  82  */
  83 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  84 #define IXGBE_DEFAULT_RX_PTHRESH      8
  85 #define IXGBE_DEFAULT_RX_HTHRESH      8
  86 #define IXGBE_DEFAULT_RX_WTHRESH      0
  87
  88 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  89 #define IXGBE_DEFAULT_TX_PTHRESH      32
  90 #define IXGBE_DEFAULT_TX_HTHRESH      0
  91 #define IXGBE_DEFAULT_TX_WTHRESH      0
  92 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  93
  94 /* Bit shift and mask */
  95 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  96 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  97 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  98 #define IXGBE_8_BIT_MASK   UINT8_MAX
  99
 100 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 101
 102 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 103
 104 #define IXGBE_HKEY_MAX_INDEX 10
 105
 106 /* Additional timesync values. */
 107 #define NSEC_PER_SEC             1000000000L
 108 #define IXGBE_INCVAL_10GB        0x66666666
 109 #define IXGBE_INCVAL_1GB         0x40000000
 110 #define IXGBE_INCVAL_100         0x50000000
 111 #define IXGBE_INCVAL_SHIFT_10GB  28
 112 #define IXGBE_INCVAL_SHIFT_1GB   24
 113 #define IXGBE_INCVAL_SHIFT_100   21
 114 #define IXGBE_INCVAL_SHIFT_82599 7
 115 #define IXGBE_INCPER_SHIFT_82599 24
 116
 117 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 118
 119 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 120 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 121 #define DEFAULT_ETAG_ETYPE                     0x893f
 122 #define IXGBE_ETAG_ETYPE                       0x00005084
 123 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 124 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 125 #define IXGBE_RAH_ADTYPE                       0x40000000
 126 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 127 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 128 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 129 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 130 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 131 #define IXGBE_VTEICR_MASK                      0x07
 132
 133 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 134 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 135
 136 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 137 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 138 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 139 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 143 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 144 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 147 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 148 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 149 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 151 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 152 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 153 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 155                                 int wait_to_complete);
 156 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 157                                 struct rte_eth_stats *stats);
 158 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_xstat *xstats, unsigned n);
 160 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 161                                   struct rte_eth_xstat *xstats, unsigned n);
 162 static int
 163 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 164                 uint64_t *values, unsigned int n);
 165 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 166 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 167 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 168         struct rte_eth_xstat_name *xstats_names,
 169         unsigned int size);
 170 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 171         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 172 static int ixgbe_dev_xstats_get_names_by_id(
 173         struct rte_eth_dev *dev,
 174         struct rte_eth_xstat_name *xstats_names,
 175         const uint64_t *ids,
 176         unsigned int limit);
 177 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 178                                              uint16_t queue_id,
 179                                              uint8_t stat_idx,
 180                                              uint8_t is_rx);
 181 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 182                                  size_t fw_size);
 183 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 184                                struct rte_eth_dev_info *dev_info);
 185 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 186 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 187                                  struct rte_eth_dev_info *dev_info);
 188 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 189
 190 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 191                 uint16_t vlan_id, int on);
 192 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 193                                enum rte_vlan_type vlan_type,
 194                                uint16_t tpid_id);
 195 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 196                 uint16_t queue, bool on);
 197 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 198                 int on);
 199 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 200 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 201 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 202 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 203 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 204
 205 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 206 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 207 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 208                                struct rte_eth_fc_conf *fc_conf);
 209 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 210                                struct rte_eth_fc_conf *fc_conf);
 211 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 212                 struct rte_eth_pfc_conf *pfc_conf);
 213 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 214                         struct rte_eth_rss_reta_entry64 *reta_conf,
 215                         uint16_t reta_size);
 216 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 217                         struct rte_eth_rss_reta_entry64 *reta_conf,
 218                         uint16_t reta_size);
 219 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 220 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 221 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 222 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 223 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 224 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 225                                       struct rte_intr_handle *handle);
 226 static void ixgbe_dev_interrupt_handler(void *param);
 227 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 228 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 229                          uint32_t index, uint32_t pool);
 230 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 231 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 232                                            struct ether_addr *mac_addr);
 233 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 234 static bool is_device_supported(struct rte_eth_dev *dev,
 235                                 struct rte_pci_driver *drv);
 236
 237 /* For Virtual Function support */
 238 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 239 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 240 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 241 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 242 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 243                                    int wait_to_complete);
 244 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 245 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 246 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 247 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 248 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 249 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 250                 struct rte_eth_stats *stats);
 251 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 252 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 253                 uint16_t vlan_id, int on);
 254 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 255                 uint16_t queue, int on);
 256 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 257 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 258 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 259                                             uint16_t queue_id);
 260 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 261                                              uint16_t queue_id);
 262 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 263                                  uint8_t queue, uint8_t msix_vector);
 264 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 265 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 266 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 267
 268 /* For Eth VMDQ APIs support */
 269 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 270                 ether_addr * mac_addr, uint8_t on);
 271 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 272 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 273                 struct rte_eth_mirror_conf *mirror_conf,
 274                 uint8_t rule_id, uint8_t on);
 275 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 276                 uint8_t rule_id);
 277 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 278                                           uint16_t queue_id);
 279 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 280                                            uint16_t queue_id);
 281 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 282                                uint8_t queue, uint8_t msix_vector);
 283 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 284
 285 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 286                                 struct ether_addr *mac_addr,
 287                                 uint32_t index, uint32_t pool);
 288 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 289 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 290                                              struct ether_addr *mac_addr);
 291 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 292                         struct rte_eth_syn_filter *filter);
 293 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 294                         enum rte_filter_op filter_op,
 295                         void *arg);
 296 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 297                         struct ixgbe_5tuple_filter *filter);
 298 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 299                         struct ixgbe_5tuple_filter *filter);
 300 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 301                                 enum rte_filter_op filter_op,
 302                                 void *arg);
 303 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 304                         struct rte_eth_ntuple_filter *filter);
 305 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 306                                 enum rte_filter_op filter_op,
 307                                 void *arg);
 308 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 309                         struct rte_eth_ethertype_filter *filter);
 310 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 311                      enum rte_filter_type filter_type,
 312                      enum rte_filter_op filter_op,
 313                      void *arg);
 314 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 315
 316 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 317                                       struct ether_addr *mc_addr_set,
 318                                       uint32_t nb_mc_addr);
 319 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 320                                    struct rte_eth_dcb_info *dcb_info);
 321
 322 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 323 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 324                             struct rte_dev_reg_info *regs);
 325 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 326 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 327                                 struct rte_dev_eeprom_info *eeprom);
 328 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 329                                 struct rte_dev_eeprom_info *eeprom);
 330
 331 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 332 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 333                                 struct rte_dev_reg_info *regs);
 334
 335 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 336 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 337 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 338                                             struct timespec *timestamp,
 339                                             uint32_t flags);
 340 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 341                                             struct timespec *timestamp);
 342 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 343 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 344                                    struct timespec *timestamp);
 345 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 346                                    const struct timespec *timestamp);
 347 static void ixgbevf_dev_interrupt_handler(void *param);
 348
 349 static int ixgbe_dev_l2_tunnel_eth_type_conf
 350         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 351 static int ixgbe_dev_l2_tunnel_offload_set
 352         (struct rte_eth_dev *dev,
 353          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 354          uint32_t mask,
 355          uint8_t en);
 356 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 357                                              enum rte_filter_op filter_op,
 358                                              void *arg);
 359
 360 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 361                                          struct rte_eth_udp_tunnel *udp_tunnel);
 362 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 363                                          struct rte_eth_udp_tunnel *udp_tunnel);
 364 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 365 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 366
 367 /*
 368  * Define VF Stats MACRO for Non "cleared on read" register
 369  */
 370 #define UPDATE_VF_STAT(reg, last, cur)                          \
 371 {                                                               \
 372         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 373         cur += (latest - last) & UINT_MAX;                      \
 374         last = latest;                                          \
 375 }
 376
 377 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 378 {                                                                \
 379         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 380         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 381         u64 latest = ((new_msb << 32) | new_lsb);                \
 382         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 383         last = latest;                                           \
 384 }
 385
 386 #define IXGBE_SET_HWSTRIP(h, q) do {\
 387                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 388                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 389                 (h)->bitmap[idx] |= 1 << bit;\
 390         } while (0)
 391
 392 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 393                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 394                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 395                 (h)->bitmap[idx] &= ~(1 << bit);\
 396         } while (0)
 397
 398 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 399                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 400                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 401                 (r) = (h)->bitmap[idx] >> bit & 1;\
 402         } while (0)
 403
 404 int ixgbe_logtype_init;
 405 int ixgbe_logtype_driver;
 406
 407 /*
 408  * The set of PCI devices this driver supports
 409  */
 410 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 411         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 459 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 461 #endif
 462         { .vendor_id = 0, /* sentinel */ },
 463 };
 464
 465 /*
 466  * The set of PCI devices this driver supports (for 82599 VF)
 467  */
 468 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 479         { .vendor_id = 0, /* sentinel */ },
 480 };
 481
 482 static const struct rte_eth_desc_lim rx_desc_lim = {
 483         .nb_max = IXGBE_MAX_RING_DESC,
 484         .nb_min = IXGBE_MIN_RING_DESC,
 485         .nb_align = IXGBE_RXD_ALIGN,
 486 };
 487
 488 static const struct rte_eth_desc_lim tx_desc_lim = {
 489         .nb_max = IXGBE_MAX_RING_DESC,
 490         .nb_min = IXGBE_MIN_RING_DESC,
 491         .nb_align = IXGBE_TXD_ALIGN,
 492         .nb_seg_max = IXGBE_TX_MAX_SEG,
 493         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 494 };
 495
 496 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 497         .dev_configure        = ixgbe_dev_configure,
 498         .dev_start            = ixgbe_dev_start,
 499         .dev_stop             = ixgbe_dev_stop,
 500         .dev_set_link_up    = ixgbe_dev_set_link_up,
 501         .dev_set_link_down  = ixgbe_dev_set_link_down,
 502         .dev_close            = ixgbe_dev_close,
 503         .dev_reset            = ixgbe_dev_reset,
 504         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 505         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 506         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 507         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 508         .link_update          = ixgbe_dev_link_update,
 509         .stats_get            = ixgbe_dev_stats_get,
 510         .xstats_get           = ixgbe_dev_xstats_get,
 511         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 512         .stats_reset          = ixgbe_dev_stats_reset,
 513         .xstats_reset         = ixgbe_dev_xstats_reset,
 514         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 515         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 516         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 517         .fw_version_get       = ixgbe_fw_version_get,
 518         .dev_infos_get        = ixgbe_dev_info_get,
 519         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 520         .mtu_set              = ixgbe_dev_mtu_set,
 521         .vlan_filter_set      = ixgbe_vlan_filter_set,
 522         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 523         .vlan_offload_set     = ixgbe_vlan_offload_set,
 524         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 525         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 526         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 527         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 528         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 529         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 530         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 531         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 532         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 533         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 534         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 535         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 536         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 537         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 538         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 539         .dev_led_on           = ixgbe_dev_led_on,
 540         .dev_led_off          = ixgbe_dev_led_off,
 541         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 542         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 543         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 544         .mac_addr_add         = ixgbe_add_rar,
 545         .mac_addr_remove      = ixgbe_remove_rar,
 546         .mac_addr_set         = ixgbe_set_default_mac_addr,
 547         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 548         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 549         .mirror_rule_set      = ixgbe_mirror_rule_set,
 550         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 551         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 552         .reta_update          = ixgbe_dev_rss_reta_update,
 553         .reta_query           = ixgbe_dev_rss_reta_query,
 554         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 555         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 556         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 557         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 558         .rxq_info_get         = ixgbe_rxq_info_get,
 559         .txq_info_get         = ixgbe_txq_info_get,
 560         .timesync_enable      = ixgbe_timesync_enable,
 561         .timesync_disable     = ixgbe_timesync_disable,
 562         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 563         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 564         .get_reg              = ixgbe_get_regs,
 565         .get_eeprom_length    = ixgbe_get_eeprom_length,
 566         .get_eeprom           = ixgbe_get_eeprom,
 567         .set_eeprom           = ixgbe_set_eeprom,
 568         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 569         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 570         .timesync_read_time   = ixgbe_timesync_read_time,
 571         .timesync_write_time  = ixgbe_timesync_write_time,
 572         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 573         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 574         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 575         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 576         .tm_ops_get           = ixgbe_tm_ops_get,
 577 };
 578
 579 /*
 580  * dev_ops for virtual function, bare necessities for basic vf
 581  * operation have been implemented
 582  */
 583 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 584         .dev_configure        = ixgbevf_dev_configure,
 585         .dev_start            = ixgbevf_dev_start,
 586         .dev_stop             = ixgbevf_dev_stop,
 587         .link_update          = ixgbevf_dev_link_update,
 588         .stats_get            = ixgbevf_dev_stats_get,
 589         .xstats_get           = ixgbevf_dev_xstats_get,
 590         .stats_reset          = ixgbevf_dev_stats_reset,
 591         .xstats_reset         = ixgbevf_dev_stats_reset,
 592         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 593         .dev_close            = ixgbevf_dev_close,
 594         .dev_reset            = ixgbevf_dev_reset,
 595         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 596         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 597         .dev_infos_get        = ixgbevf_dev_info_get,
 598         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 599         .mtu_set              = ixgbevf_dev_set_mtu,
 600         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 601         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 602         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 603         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 604         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 605         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 606         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 607         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 608         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 609         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 610         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 611         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 612         .mac_addr_add         = ixgbevf_add_mac_addr,
 613         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 614         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 615         .rxq_info_get         = ixgbe_rxq_info_get,
 616         .txq_info_get         = ixgbe_txq_info_get,
 617         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 618         .get_reg              = ixgbevf_get_regs,
 619         .reta_update          = ixgbe_dev_rss_reta_update,
 620         .reta_query           = ixgbe_dev_rss_reta_query,
 621         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 622         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 623 };
 624
 625 /* store statistics names and its offset in stats structure */
 626 struct rte_ixgbe_xstats_name_off {
 627         char name[RTE_ETH_XSTATS_NAME_SIZE];
 628         unsigned offset;
 629 };
 630
 631 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 632         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 633         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 634         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 635         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 636         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 637         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 638         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 639         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 640         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 641         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 642         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 643         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 644         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 645         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 646         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 647                 prc1023)},
 648         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 649                 prc1522)},
 650         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 651         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 652         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 653         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 654         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 655         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 656         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 657         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 658         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 659         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 660         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 661         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 662         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 663         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 664         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 665         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 666         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 667                 ptc1023)},
 668         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 669                 ptc1522)},
 670         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 671         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 672         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 673         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 674
 675         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 676                 fdirustat_add)},
 677         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 678                 fdirustat_remove)},
 679         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 680                 fdirfstat_fadd)},
 681         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 682                 fdirfstat_fremove)},
 683         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 684                 fdirmatch)},
 685         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 686                 fdirmiss)},
 687
 688         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 689         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 690         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 691                 fclast)},
 692         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 693         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 694         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 695         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 696         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 697                 fcoe_noddp)},
 698         {"rx_fcoe_no_direct_data_placement_ext_buff",
 699                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 700
 701         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 702                 lxontxc)},
 703         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 704                 lxonrxc)},
 705         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 706                 lxofftxc)},
 707         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 708                 lxoffrxc)},
 709         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 710 };
 711
 712 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 713                            sizeof(rte_ixgbe_stats_strings[0]))
 714
 715 /* MACsec statistics */
 716 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 717         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 718                 out_pkts_untagged)},
 719         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 720                 out_pkts_encrypted)},
 721         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 722                 out_pkts_protected)},
 723         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 724                 out_octets_encrypted)},
 725         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 726                 out_octets_protected)},
 727         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 728                 in_pkts_untagged)},
 729         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 730                 in_pkts_badtag)},
 731         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 732                 in_pkts_nosci)},
 733         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 734                 in_pkts_unknownsci)},
 735         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 736                 in_octets_decrypted)},
 737         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 738                 in_octets_validated)},
 739         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 740                 in_pkts_unchecked)},
 741         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 742                 in_pkts_delayed)},
 743         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 744                 in_pkts_late)},
 745         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 746                 in_pkts_ok)},
 747         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_invalid)},
 749         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 750                 in_pkts_notvalid)},
 751         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 752                 in_pkts_unusedsa)},
 753         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_notusingsa)},
 755 };
 756
 757 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 758                            sizeof(rte_ixgbe_macsec_strings[0]))
 759
 760 /* Per-queue statistics */
 761 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 762         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 763         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 764         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 765         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 766 };
 767
 768 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 769                            sizeof(rte_ixgbe_rxq_strings[0]))
 770 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 771
 772 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 773         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 774         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 775         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 776                 pxon2offc)},
 777 };
 778
 779 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 780                            sizeof(rte_ixgbe_txq_strings[0]))
 781 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 782
 783 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 784         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 785 };
 786
 787 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 788                 sizeof(rte_ixgbevf_stats_strings[0]))
 789
 790 /**
 791  * Atomically reads the link status information from global
 792  * structure rte_eth_dev.
 793  *
 794  * @param dev
 795  *   - Pointer to the structure rte_eth_dev to read from.
 796  *   - Pointer to the buffer to be saved with the link status.
 797  *
 798  * @return
 799  *   - On success, zero.
 800  *   - On failure, negative value.
 801  */
 802 static inline int
 803 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 804                                 struct rte_eth_link *link)
 805 {
 806         struct rte_eth_link *dst = link;
 807         struct rte_eth_link *src = &(dev->data->dev_link);
 808
 809         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 810                                         *(uint64_t *)src) == 0)
 811                 return -1;
 812
 813         return 0;
 814 }
 815
 816 /**
 817  * Atomically writes the link status information into global
 818  * structure rte_eth_dev.
 819  *
 820  * @param dev
 821  *   - Pointer to the structure rte_eth_dev to read from.
 822  *   - Pointer to the buffer to be saved with the link status.
 823  *
 824  * @return
 825  *   - On success, zero.
 826  *   - On failure, negative value.
 827  */
 828 static inline int
 829 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 830                                 struct rte_eth_link *link)
 831 {
 832         struct rte_eth_link *dst = &(dev->data->dev_link);
 833         struct rte_eth_link *src = link;
 834
 835         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 836                                         *(uint64_t *)src) == 0)
 837                 return -1;
 838
 839         return 0;
 840 }
 841
 842 /*
 843  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 844  */
 845 static inline int
 846 ixgbe_is_sfp(struct ixgbe_hw *hw)
 847 {
 848         switch (hw->phy.type) {
 849         case ixgbe_phy_sfp_avago:
 850         case ixgbe_phy_sfp_ftl:
 851         case ixgbe_phy_sfp_intel:
 852         case ixgbe_phy_sfp_unknown:
 853         case ixgbe_phy_sfp_passive_tyco:
 854         case ixgbe_phy_sfp_passive_unknown:
 855                 return 1;
 856         default:
 857                 return 0;
 858         }
 859 }
 860
 861 static inline int32_t
 862 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 863 {
 864         uint32_t ctrl_ext;
 865         int32_t status;
 866
 867         status = ixgbe_reset_hw(hw);
 868
 869         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 870         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 871         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 872         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 873         IXGBE_WRITE_FLUSH(hw);
 874
 875         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 876                 status = IXGBE_SUCCESS;
 877         return status;
 878 }
 879
 880 static inline void
 881 ixgbe_enable_intr(struct rte_eth_dev *dev)
 882 {
 883         struct ixgbe_interrupt *intr =
 884                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 885         struct ixgbe_hw *hw =
 886                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 887
 888         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 889         IXGBE_WRITE_FLUSH(hw);
 890 }
 891
 892 /*
 893  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 894  */
 895 static void
 896 ixgbe_disable_intr(struct ixgbe_hw *hw)
 897 {
 898         PMD_INIT_FUNC_TRACE();
 899
 900         if (hw->mac.type == ixgbe_mac_82598EB) {
 901                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 902         } else {
 903                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 904                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 905                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 906         }
 907         IXGBE_WRITE_FLUSH(hw);
 908 }
 909
 910 /*
 911  * This function resets queue statistics mapping registers.
 912  * From Niantic datasheet, Initialization of Statistics section:
 913  * "...if software requires the queue counters, the RQSMR and TQSM registers
 914  * must be re-programmed following a device reset.
 915  */
 916 static void
 917 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 918 {
 919         uint32_t i;
 920
 921         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 922                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 923                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 924         }
 925 }
 926
 927
 928 static int
 929 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 930                                   uint16_t queue_id,
 931                                   uint8_t stat_idx,
 932                                   uint8_t is_rx)
 933 {
 934 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 935 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 936 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 937
 938         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 939         struct ixgbe_stat_mapping_registers *stat_mappings =
 940                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 941         uint32_t qsmr_mask = 0;
 942         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 943         uint32_t q_map;
 944         uint8_t n, offset;
 945
 946         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 947                 (hw->mac.type != ixgbe_mac_X540) &&
 948                 (hw->mac.type != ixgbe_mac_X550) &&
 949                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 950                 (hw->mac.type != ixgbe_mac_X550EM_a))
 951                 return -ENOSYS;
 952
 953         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 954                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 955                      queue_id, stat_idx);
 956
 957         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 958         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 959                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 960                 return -EIO;
 961         }
 962         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 963
 964         /* Now clear any previous stat_idx set */
 965         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 966         if (!is_rx)
 967                 stat_mappings->tqsm[n] &= ~clearing_mask;
 968         else
 969                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 970
 971         q_map = (uint32_t)stat_idx;
 972         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 973         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 974         if (!is_rx)
 975                 stat_mappings->tqsm[n] |= qsmr_mask;
 976         else
 977                 stat_mappings->rqsmr[n] |= qsmr_mask;
 978
 979         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 980                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 981                      queue_id, stat_idx);
 982         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 983                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 984
 985         /* Now write the mapping in the appropriate register */
 986         if (is_rx) {
 987                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 988                              stat_mappings->rqsmr[n], n);
 989                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 990         } else {
 991                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 992                              stat_mappings->tqsm[n], n);
 993                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 994         }
 995         return 0;
 996 }
 997
 998 static void
 999 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1000 {
1001         struct ixgbe_stat_mapping_registers *stat_mappings =
1002                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1003         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1004         int i;
1005
1006         /* write whatever was in stat mapping table to the NIC */
1007         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1008                 /* rx */
1009                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1010
1011                 /* tx */
1012                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1013         }
1014 }
1015
1016 static void
1017 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1018 {
1019         uint8_t i;
1020         struct ixgbe_dcb_tc_config *tc;
1021         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1022
1023         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1024         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1025         for (i = 0; i < dcb_max_tc; i++) {
1026                 tc = &dcb_config->tc_config[i];
1027                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1028                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1029                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1030                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1031                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1032                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1033                 tc->pfc = ixgbe_dcb_pfc_disabled;
1034         }
1035
1036         /* Initialize default user to priority mapping, UPx->TC0 */
1037         tc = &dcb_config->tc_config[0];
1038         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1039         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1040         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1041                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1042                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1043         }
1044         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1045         dcb_config->pfc_mode_enable = false;
1046         dcb_config->vt_mode = true;
1047         dcb_config->round_robin_enable = false;
1048         /* support all DCB capabilities in 82599 */
1049         dcb_config->support.capabilities = 0xFF;
1050
1051         /*we only support 4 Tcs for X540, X550 */
1052         if (hw->mac.type == ixgbe_mac_X540 ||
1053                 hw->mac.type == ixgbe_mac_X550 ||
1054                 hw->mac.type == ixgbe_mac_X550EM_x ||
1055                 hw->mac.type == ixgbe_mac_X550EM_a) {
1056                 dcb_config->num_tcs.pg_tcs = 4;
1057                 dcb_config->num_tcs.pfc_tcs = 4;
1058         }
1059 }
1060
1061 /*
1062  * Ensure that all locks are released before first NVM or PHY access
1063  */
1064 static void
1065 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1066 {
1067         uint16_t mask;
1068
1069         /*
1070          * Phy lock should not fail in this early stage. If this is the case,
1071          * it is due to an improper exit of the application.
1072          * So force the release of the faulty lock. Release of common lock
1073          * is done automatically by swfw_sync function.
1074          */
1075         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1076         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1077                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1078         }
1079         ixgbe_release_swfw_semaphore(hw, mask);
1080
1081         /*
1082          * These ones are more tricky since they are common to all ports; but
1083          * swfw_sync retries last long enough (1s) to be almost sure that if
1084          * lock can not be taken it is due to an improper lock of the
1085          * semaphore.
1086          */
1087         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1088         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1089                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1090         }
1091         ixgbe_release_swfw_semaphore(hw, mask);
1092 }
1093
1094 /*
1095  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1096  * It returns 0 on success.
1097  */
1098 static int
1099 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1100 {
1101         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1102         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1103         struct ixgbe_hw *hw =
1104                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1105         struct ixgbe_vfta *shadow_vfta =
1106                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1107         struct ixgbe_hwstrip *hwstrip =
1108                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1109         struct ixgbe_dcb_config *dcb_config =
1110                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1111         struct ixgbe_filter_info *filter_info =
1112                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1113         struct ixgbe_bw_conf *bw_conf =
1114                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1115         uint32_t ctrl_ext;
1116         uint16_t csum;
1117         int diag, i;
1118
1119         PMD_INIT_FUNC_TRACE();
1120
1121         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1122         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1123         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1124         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1125
1126         /*
1127          * For secondary processes, we don't initialise any further as primary
1128          * has already done this work. Only check we don't need a different
1129          * RX and TX function.
1130          */
1131         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1132                 struct ixgbe_tx_queue *txq;
1133                 /* TX queue function in primary, set by last queue initialized
1134                  * Tx queue may not initialized by primary process
1135                  */
1136                 if (eth_dev->data->tx_queues) {
1137                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1138                         ixgbe_set_tx_function(eth_dev, txq);
1139                 } else {
1140                         /* Use default TX function if we get here */
1141                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1142                                      "Using default TX function.");
1143                 }
1144
1145                 ixgbe_set_rx_function(eth_dev);
1146
1147                 return 0;
1148         }
1149
1150 #ifdef RTE_LIBRTE_SECURITY
1151         /* Initialize security_ctx only for primary process*/
1152         eth_dev->security_ctx = ixgbe_ipsec_ctx_create(eth_dev);
1153         if (eth_dev->security_ctx == NULL)
1154                 return -ENOMEM;
1155 #endif
1156
1157         rte_eth_copy_pci_info(eth_dev, pci_dev);
1158
1159         /* Vendor and Device ID need to be set before init of shared code */
1160         hw->device_id = pci_dev->id.device_id;
1161         hw->vendor_id = pci_dev->id.vendor_id;
1162         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1163         hw->allow_unsupported_sfp = 1;
1164
1165         /* Initialize the shared code (base driver) */
1166 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1167         diag = ixgbe_bypass_init_shared_code(hw);
1168 #else
1169         diag = ixgbe_init_shared_code(hw);
1170 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1171
1172         if (diag != IXGBE_SUCCESS) {
1173                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1174                 return -EIO;
1175         }
1176
1177         /* pick up the PCI bus settings for reporting later */
1178         ixgbe_get_bus_info(hw);
1179
1180         /* Unlock any pending hardware semaphore */
1181         ixgbe_swfw_lock_reset(hw);
1182
1183         /* Initialize DCB configuration*/
1184         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1185         ixgbe_dcb_init(hw, dcb_config);
1186         /* Get Hardware Flow Control setting */
1187         hw->fc.requested_mode = ixgbe_fc_full;
1188         hw->fc.current_mode = ixgbe_fc_full;
1189         hw->fc.pause_time = IXGBE_FC_PAUSE;
1190         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1191                 hw->fc.low_water[i] = IXGBE_FC_LO;
1192                 hw->fc.high_water[i] = IXGBE_FC_HI;
1193         }
1194         hw->fc.send_xon = 1;
1195
1196         /* Make sure we have a good EEPROM before we read from it */
1197         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1198         if (diag != IXGBE_SUCCESS) {
1199                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1200                 return -EIO;
1201         }
1202
1203 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1204         diag = ixgbe_bypass_init_hw(hw);
1205 #else
1206         diag = ixgbe_init_hw(hw);
1207 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1208
1209         /*
1210          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1211          * is called too soon after the kernel driver unbinding/binding occurs.
1212          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1213          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1214          * also called. See ixgbe_identify_phy_82599(). The reason for the
1215          * failure is not known, and only occuts when virtualisation features
1216          * are disabled in the bios. A delay of 100ms  was found to be enough by
1217          * trial-and-error, and is doubled to be safe.
1218          */
1219         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1220                 rte_delay_ms(200);
1221                 diag = ixgbe_init_hw(hw);
1222         }
1223
1224         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1225                 diag = IXGBE_SUCCESS;
1226
1227         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1228                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1229                              "LOM.  Please be aware there may be issues associated "
1230                              "with your hardware.");
1231                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1232                              "please contact your Intel or hardware representative "
1233                              "who provided you with this hardware.");
1234         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1235                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1236         if (diag) {
1237                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1238                 return -EIO;
1239         }
1240
1241         /* Reset the hw statistics */
1242         ixgbe_dev_stats_reset(eth_dev);
1243
1244         /* disable interrupt */
1245         ixgbe_disable_intr(hw);
1246
1247         /* reset mappings for queue statistics hw counters*/
1248         ixgbe_reset_qstat_mappings(hw);
1249
1250         /* Allocate memory for storing MAC addresses */
1251         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1252                                                hw->mac.num_rar_entries, 0);
1253         if (eth_dev->data->mac_addrs == NULL) {
1254                 PMD_INIT_LOG(ERR,
1255                              "Failed to allocate %u bytes needed to store "
1256                              "MAC addresses",
1257                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1258                 return -ENOMEM;
1259         }
1260         /* Copy the permanent MAC address */
1261         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1262                         &eth_dev->data->mac_addrs[0]);
1263
1264         /* Allocate memory for storing hash filter MAC addresses */
1265         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1266                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1267         if (eth_dev->data->hash_mac_addrs == NULL) {
1268                 PMD_INIT_LOG(ERR,
1269                              "Failed to allocate %d bytes needed to store MAC addresses",
1270                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1271                 return -ENOMEM;
1272         }
1273
1274         /* initialize the vfta */
1275         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1276
1277         /* initialize the hw strip bitmap*/
1278         memset(hwstrip, 0, sizeof(*hwstrip));
1279
1280         /* initialize PF if max_vfs not zero */
1281         ixgbe_pf_host_init(eth_dev);
1282
1283         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1284         /* let hardware know driver is loaded */
1285         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1286         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1287         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1288         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1289         IXGBE_WRITE_FLUSH(hw);
1290
1291         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1292                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1293                              (int) hw->mac.type, (int) hw->phy.type,
1294                              (int) hw->phy.sfp_type);
1295         else
1296                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1297                              (int) hw->mac.type, (int) hw->phy.type);
1298
1299         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1300                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1301                      pci_dev->id.device_id);
1302
1303         rte_intr_callback_register(intr_handle,
1304                                    ixgbe_dev_interrupt_handler, eth_dev);
1305
1306         /* enable uio/vfio intr/eventfd mapping */
1307         rte_intr_enable(intr_handle);
1308
1309         /* enable support intr */
1310         ixgbe_enable_intr(eth_dev);
1311
1312         /* initialize filter info */
1313         memset(filter_info, 0,
1314                sizeof(struct ixgbe_filter_info));
1315
1316         /* initialize 5tuple filter list */
1317         TAILQ_INIT(&filter_info->fivetuple_list);
1318
1319         /* initialize flow director filter list & hash */
1320         ixgbe_fdir_filter_init(eth_dev);
1321
1322         /* initialize l2 tunnel filter list & hash */
1323         ixgbe_l2_tn_filter_init(eth_dev);
1324
1325         /* initialize flow filter lists */
1326         ixgbe_filterlist_init();
1327
1328         /* initialize bandwidth configuration info */
1329         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1330
1331         /* initialize Traffic Manager configuration */
1332         ixgbe_tm_conf_init(eth_dev);
1333
1334         return 0;
1335 }
1336
1337 static int
1338 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1339 {
1340         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1341         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1342         struct ixgbe_hw *hw;
1343
1344         PMD_INIT_FUNC_TRACE();
1345
1346         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1347                 return -EPERM;
1348
1349         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1350
1351         if (hw->adapter_stopped == 0)
1352                 ixgbe_dev_close(eth_dev);
1353
1354         eth_dev->dev_ops = NULL;
1355         eth_dev->rx_pkt_burst = NULL;
1356         eth_dev->tx_pkt_burst = NULL;
1357
1358         /* Unlock any pending hardware semaphore */
1359         ixgbe_swfw_lock_reset(hw);
1360
1361         /* disable uio intr before callback unregister */
1362         rte_intr_disable(intr_handle);
1363         rte_intr_callback_unregister(intr_handle,
1364                                      ixgbe_dev_interrupt_handler, eth_dev);
1365
1366         /* uninitialize PF if max_vfs not zero */
1367         ixgbe_pf_host_uninit(eth_dev);
1368
1369         rte_free(eth_dev->data->mac_addrs);
1370         eth_dev->data->mac_addrs = NULL;
1371
1372         rte_free(eth_dev->data->hash_mac_addrs);
1373         eth_dev->data->hash_mac_addrs = NULL;
1374
1375         /* remove all the fdir filters & hash */
1376         ixgbe_fdir_filter_uninit(eth_dev);
1377
1378         /* remove all the L2 tunnel filters & hash */
1379         ixgbe_l2_tn_filter_uninit(eth_dev);
1380
1381         /* Remove all ntuple filters of the device */
1382         ixgbe_ntuple_filter_uninit(eth_dev);
1383
1384         /* clear all the filters list */
1385         ixgbe_filterlist_flush();
1386
1387         /* Remove all Traffic Manager configuration */
1388         ixgbe_tm_conf_uninit(eth_dev);
1389
1390 #ifdef RTE_LIBRTE_SECURITY
1391         rte_free(eth_dev->security_ctx);
1392 #endif
1393
1394         return 0;
1395 }
1396
1397 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1398 {
1399         struct ixgbe_filter_info *filter_info =
1400                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1401         struct ixgbe_5tuple_filter *p_5tuple;
1402
1403         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1404                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1405                              p_5tuple,
1406                              entries);
1407                 rte_free(p_5tuple);
1408         }
1409         memset(filter_info->fivetuple_mask, 0,
1410                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1411
1412         return 0;
1413 }
1414
1415 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1416 {
1417         struct ixgbe_hw_fdir_info *fdir_info =
1418                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1419         struct ixgbe_fdir_filter *fdir_filter;
1420
1421                 if (fdir_info->hash_map)
1422                 rte_free(fdir_info->hash_map);
1423         if (fdir_info->hash_handle)
1424                 rte_hash_free(fdir_info->hash_handle);
1425
1426         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1427                 TAILQ_REMOVE(&fdir_info->fdir_list,
1428                              fdir_filter,
1429                              entries);
1430                 rte_free(fdir_filter);
1431         }
1432
1433         return 0;
1434 }
1435
1436 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1437 {
1438         struct ixgbe_l2_tn_info *l2_tn_info =
1439                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1440         struct ixgbe_l2_tn_filter *l2_tn_filter;
1441
1442         if (l2_tn_info->hash_map)
1443                 rte_free(l2_tn_info->hash_map);
1444         if (l2_tn_info->hash_handle)
1445                 rte_hash_free(l2_tn_info->hash_handle);
1446
1447         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1448                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1449                              l2_tn_filter,
1450                              entries);
1451                 rte_free(l2_tn_filter);
1452         }
1453
1454         return 0;
1455 }
1456
1457 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1458 {
1459         struct ixgbe_hw_fdir_info *fdir_info =
1460                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1461         char fdir_hash_name[RTE_HASH_NAMESIZE];
1462         struct rte_hash_parameters fdir_hash_params = {
1463                 .name = fdir_hash_name,
1464                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1465                 .key_len = sizeof(union ixgbe_atr_input),
1466                 .hash_func = rte_hash_crc,
1467                 .hash_func_init_val = 0,
1468                 .socket_id = rte_socket_id(),
1469         };
1470
1471         TAILQ_INIT(&fdir_info->fdir_list);
1472         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1473                  "fdir_%s", eth_dev->device->name);
1474         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1475         if (!fdir_info->hash_handle) {
1476                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1477                 return -EINVAL;
1478         }
1479         fdir_info->hash_map = rte_zmalloc("ixgbe",
1480                                           sizeof(struct ixgbe_fdir_filter *) *
1481                                           IXGBE_MAX_FDIR_FILTER_NUM,
1482                                           0);
1483         if (!fdir_info->hash_map) {
1484                 PMD_INIT_LOG(ERR,
1485                              "Failed to allocate memory for fdir hash map!");
1486                 return -ENOMEM;
1487         }
1488         fdir_info->mask_added = FALSE;
1489
1490         return 0;
1491 }
1492
1493 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1494 {
1495         struct ixgbe_l2_tn_info *l2_tn_info =
1496                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1497         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1498         struct rte_hash_parameters l2_tn_hash_params = {
1499                 .name = l2_tn_hash_name,
1500                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1501                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1502                 .hash_func = rte_hash_crc,
1503                 .hash_func_init_val = 0,
1504                 .socket_id = rte_socket_id(),
1505         };
1506
1507         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1508         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1509                  "l2_tn_%s", eth_dev->device->name);
1510         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1511         if (!l2_tn_info->hash_handle) {
1512                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1513                 return -EINVAL;
1514         }
1515         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1516                                    sizeof(struct ixgbe_l2_tn_filter *) *
1517                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1518                                    0);
1519         if (!l2_tn_info->hash_map) {
1520                 PMD_INIT_LOG(ERR,
1521                         "Failed to allocate memory for L2 TN hash map!");
1522                 return -ENOMEM;
1523         }
1524         l2_tn_info->e_tag_en = FALSE;
1525         l2_tn_info->e_tag_fwd_en = FALSE;
1526         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1527
1528         return 0;
1529 }
1530 /*
1531  * Negotiate mailbox API version with the PF.
1532  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1533  * Then we try to negotiate starting with the most recent one.
1534  * If all negotiation attempts fail, then we will proceed with
1535  * the default one (ixgbe_mbox_api_10).
1536  */
1537 static void
1538 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1539 {
1540         int32_t i;
1541
1542         /* start with highest supported, proceed down */
1543         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1544                 ixgbe_mbox_api_12,
1545                 ixgbe_mbox_api_11,
1546                 ixgbe_mbox_api_10,
1547         };
1548
1549         for (i = 0;
1550                         i != RTE_DIM(sup_ver) &&
1551                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1552                         i++)
1553                 ;
1554 }
1555
1556 static void
1557 generate_random_mac_addr(struct ether_addr *mac_addr)
1558 {
1559         uint64_t random;
1560
1561         /* Set Organizationally Unique Identifier (OUI) prefix. */
1562         mac_addr->addr_bytes[0] = 0x00;
1563         mac_addr->addr_bytes[1] = 0x09;
1564         mac_addr->addr_bytes[2] = 0xC0;
1565         /* Force indication of locally assigned MAC address. */
1566         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1567         /* Generate the last 3 bytes of the MAC address with a random number. */
1568         random = rte_rand();
1569         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1570 }
1571
1572 /*
1573  * Virtual Function device init
1574  */
1575 static int
1576 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1577 {
1578         int diag;
1579         uint32_t tc, tcs;
1580         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1581         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1582         struct ixgbe_hw *hw =
1583                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1584         struct ixgbe_vfta *shadow_vfta =
1585                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1586         struct ixgbe_hwstrip *hwstrip =
1587                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1588         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1589
1590         PMD_INIT_FUNC_TRACE();
1591
1592         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1593         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1594         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1595
1596         /* for secondary processes, we don't initialise any further as primary
1597          * has already done this work. Only check we don't need a different
1598          * RX function
1599          */
1600         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1601                 struct ixgbe_tx_queue *txq;
1602                 /* TX queue function in primary, set by last queue initialized
1603                  * Tx queue may not initialized by primary process
1604                  */
1605                 if (eth_dev->data->tx_queues) {
1606                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1607                         ixgbe_set_tx_function(eth_dev, txq);
1608                 } else {
1609                         /* Use default TX function if we get here */
1610                         PMD_INIT_LOG(NOTICE,
1611                                      "No TX queues configured yet. Using default TX function.");
1612                 }
1613
1614                 ixgbe_set_rx_function(eth_dev);
1615
1616                 return 0;
1617         }
1618
1619         rte_eth_copy_pci_info(eth_dev, pci_dev);
1620
1621         hw->device_id = pci_dev->id.device_id;
1622         hw->vendor_id = pci_dev->id.vendor_id;
1623         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1624
1625         /* initialize the vfta */
1626         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1627
1628         /* initialize the hw strip bitmap*/
1629         memset(hwstrip, 0, sizeof(*hwstrip));
1630
1631         /* Initialize the shared code (base driver) */
1632         diag = ixgbe_init_shared_code(hw);
1633         if (diag != IXGBE_SUCCESS) {
1634                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1635                 return -EIO;
1636         }
1637
1638         /* init_mailbox_params */
1639         hw->mbx.ops.init_params(hw);
1640
1641         /* Reset the hw statistics */
1642         ixgbevf_dev_stats_reset(eth_dev);
1643
1644         /* Disable the interrupts for VF */
1645         ixgbevf_intr_disable(hw);
1646
1647         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1648         diag = hw->mac.ops.reset_hw(hw);
1649
1650         /*
1651          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1652          * the underlying PF driver has not assigned a MAC address to the VF.
1653          * In this case, assign a random MAC address.
1654          */
1655         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1656                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1657                 return diag;
1658         }
1659
1660         /* negotiate mailbox API version to use with the PF. */
1661         ixgbevf_negotiate_api(hw);
1662
1663         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1664         ixgbevf_get_queues(hw, &tcs, &tc);
1665
1666         /* Allocate memory for storing MAC addresses */
1667         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1668                                                hw->mac.num_rar_entries, 0);
1669         if (eth_dev->data->mac_addrs == NULL) {
1670                 PMD_INIT_LOG(ERR,
1671                              "Failed to allocate %u bytes needed to store "
1672                              "MAC addresses",
1673                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1674                 return -ENOMEM;
1675         }
1676
1677         /* Generate a random MAC address, if none was assigned by PF. */
1678         if (is_zero_ether_addr(perm_addr)) {
1679                 generate_random_mac_addr(perm_addr);
1680                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1681                 if (diag) {
1682                         rte_free(eth_dev->data->mac_addrs);
1683                         eth_dev->data->mac_addrs = NULL;
1684                         return diag;
1685                 }
1686                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1687                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1688                              "%02x:%02x:%02x:%02x:%02x:%02x",
1689                              perm_addr->addr_bytes[0],
1690                              perm_addr->addr_bytes[1],
1691                              perm_addr->addr_bytes[2],
1692                              perm_addr->addr_bytes[3],
1693                              perm_addr->addr_bytes[4],
1694                              perm_addr->addr_bytes[5]);
1695         }
1696
1697         /* Copy the permanent MAC address */
1698         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1699
1700         /* reset the hardware with the new settings */
1701         diag = hw->mac.ops.start_hw(hw);
1702         switch (diag) {
1703         case  0:
1704                 break;
1705
1706         default:
1707                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1708                 return -EIO;
1709         }
1710
1711         rte_intr_callback_register(intr_handle,
1712                                    ixgbevf_dev_interrupt_handler, eth_dev);
1713         rte_intr_enable(intr_handle);
1714         ixgbevf_intr_enable(hw);
1715
1716         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1717                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1718                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1719
1720         return 0;
1721 }
1722
1723 /* Virtual Function device uninit */
1724
1725 static int
1726 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1727 {
1728         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1729         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1730         struct ixgbe_hw *hw;
1731
1732         PMD_INIT_FUNC_TRACE();
1733
1734         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1735                 return -EPERM;
1736
1737         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1738
1739         if (hw->adapter_stopped == 0)
1740                 ixgbevf_dev_close(eth_dev);
1741
1742         eth_dev->dev_ops = NULL;
1743         eth_dev->rx_pkt_burst = NULL;
1744         eth_dev->tx_pkt_burst = NULL;
1745
1746         /* Disable the interrupts for VF */
1747         ixgbevf_intr_disable(hw);
1748
1749         rte_free(eth_dev->data->mac_addrs);
1750         eth_dev->data->mac_addrs = NULL;
1751
1752         rte_intr_disable(intr_handle);
1753         rte_intr_callback_unregister(intr_handle,
1754                                      ixgbevf_dev_interrupt_handler, eth_dev);
1755
1756         return 0;
1757 }
1758
1759 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1760         struct rte_pci_device *pci_dev)
1761 {
1762         return rte_eth_dev_pci_generic_probe(pci_dev,
1763                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1764 }
1765
1766 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1767 {
1768         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1769 }
1770
1771 static struct rte_pci_driver rte_ixgbe_pmd = {
1772         .id_table = pci_id_ixgbe_map,
1773         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1774                      RTE_PCI_DRV_IOVA_AS_VA,
1775         .probe = eth_ixgbe_pci_probe,
1776         .remove = eth_ixgbe_pci_remove,
1777 };
1778
1779 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1780         struct rte_pci_device *pci_dev)
1781 {
1782         return rte_eth_dev_pci_generic_probe(pci_dev,
1783                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1784 }
1785
1786 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1787 {
1788         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1789 }
1790
1791 /*
1792  * virtual function driver struct
1793  */
1794 static struct rte_pci_driver rte_ixgbevf_pmd = {
1795         .id_table = pci_id_ixgbevf_map,
1796         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1797         .probe = eth_ixgbevf_pci_probe,
1798         .remove = eth_ixgbevf_pci_remove,
1799 };
1800
1801 static int
1802 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1803 {
1804         struct ixgbe_hw *hw =
1805                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1806         struct ixgbe_vfta *shadow_vfta =
1807                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1808         uint32_t vfta;
1809         uint32_t vid_idx;
1810         uint32_t vid_bit;
1811
1812         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1813         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1814         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1815         if (on)
1816                 vfta |= vid_bit;
1817         else
1818                 vfta &= ~vid_bit;
1819         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1820
1821         /* update local VFTA copy */
1822         shadow_vfta->vfta[vid_idx] = vfta;
1823
1824         return 0;
1825 }
1826
1827 static void
1828 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1829 {
1830         if (on)
1831                 ixgbe_vlan_hw_strip_enable(dev, queue);
1832         else
1833                 ixgbe_vlan_hw_strip_disable(dev, queue);
1834 }
1835
1836 static int
1837 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1838                     enum rte_vlan_type vlan_type,
1839                     uint16_t tpid)
1840 {
1841         struct ixgbe_hw *hw =
1842                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1843         int ret = 0;
1844         uint32_t reg;
1845         uint32_t qinq;
1846
1847         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1848         qinq &= IXGBE_DMATXCTL_GDV;
1849
1850         switch (vlan_type) {
1851         case ETH_VLAN_TYPE_INNER:
1852                 if (qinq) {
1853                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1854                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1855                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1856                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1857                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1858                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1859                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1860                 } else {
1861                         ret = -ENOTSUP;
1862                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1863                                     " by single VLAN");
1864                 }
1865                 break;
1866         case ETH_VLAN_TYPE_OUTER:
1867                 if (qinq) {
1868                         /* Only the high 16-bits is valid */
1869                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1870                                         IXGBE_EXVET_VET_EXT_SHIFT);
1871                 } else {
1872                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1873                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1874                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1875                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1876                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1877                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1878                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1879                 }
1880
1881                 break;
1882         default:
1883                 ret = -EINVAL;
1884                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1885                 break;
1886         }
1887
1888         return ret;
1889 }
1890
1891 void
1892 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1893 {
1894         struct ixgbe_hw *hw =
1895                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1896         uint32_t vlnctrl;
1897
1898         PMD_INIT_FUNC_TRACE();
1899
1900         /* Filter Table Disable */
1901         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1902         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1903
1904         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1905 }
1906
1907 void
1908 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1909 {
1910         struct ixgbe_hw *hw =
1911                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1912         struct ixgbe_vfta *shadow_vfta =
1913                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1914         uint32_t vlnctrl;
1915         uint16_t i;
1916
1917         PMD_INIT_FUNC_TRACE();
1918
1919         /* Filter Table Enable */
1920         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1921         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1922         vlnctrl |= IXGBE_VLNCTRL_VFE;
1923
1924         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1925
1926         /* write whatever is in local vfta copy */
1927         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1928                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1929 }
1930
1931 static void
1932 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1933 {
1934         struct ixgbe_hwstrip *hwstrip =
1935                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1936         struct ixgbe_rx_queue *rxq;
1937
1938         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1939                 return;
1940
1941         if (on)
1942                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1943         else
1944                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1945
1946         if (queue >= dev->data->nb_rx_queues)
1947                 return;
1948
1949         rxq = dev->data->rx_queues[queue];
1950
1951         if (on)
1952                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1953         else
1954                 rxq->vlan_flags = PKT_RX_VLAN;
1955 }
1956
1957 static void
1958 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1959 {
1960         struct ixgbe_hw *hw =
1961                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1962         uint32_t ctrl;
1963
1964         PMD_INIT_FUNC_TRACE();
1965
1966         if (hw->mac.type == ixgbe_mac_82598EB) {
1967                 /* No queue level support */
1968                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1969                 return;
1970         }
1971
1972         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1973         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1974         ctrl &= ~IXGBE_RXDCTL_VME;
1975         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1976
1977         /* record those setting for HW strip per queue */
1978         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1979 }
1980
1981 static void
1982 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1983 {
1984         struct ixgbe_hw *hw =
1985                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1986         uint32_t ctrl;
1987
1988         PMD_INIT_FUNC_TRACE();
1989
1990         if (hw->mac.type == ixgbe_mac_82598EB) {
1991                 /* No queue level supported */
1992                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1993                 return;
1994         }
1995
1996         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1997         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1998         ctrl |= IXGBE_RXDCTL_VME;
1999         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2000
2001         /* record those setting for HW strip per queue */
2002         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2003 }
2004
2005 void
2006 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2007 {
2008         struct ixgbe_hw *hw =
2009                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2010         uint32_t ctrl;
2011         uint16_t i;
2012         struct ixgbe_rx_queue *rxq;
2013
2014         PMD_INIT_FUNC_TRACE();
2015
2016         if (hw->mac.type == ixgbe_mac_82598EB) {
2017                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2018                 ctrl &= ~IXGBE_VLNCTRL_VME;
2019                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2020         } else {
2021                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2022                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2023                         rxq = dev->data->rx_queues[i];
2024                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2025                         ctrl &= ~IXGBE_RXDCTL_VME;
2026                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2027
2028                         /* record those setting for HW strip per queue */
2029                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2030                 }
2031         }
2032 }
2033
2034 void
2035 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2036 {
2037         struct ixgbe_hw *hw =
2038                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2039         uint32_t ctrl;
2040         uint16_t i;
2041         struct ixgbe_rx_queue *rxq;
2042
2043         PMD_INIT_FUNC_TRACE();
2044
2045         if (hw->mac.type == ixgbe_mac_82598EB) {
2046                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2047                 ctrl |= IXGBE_VLNCTRL_VME;
2048                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2049         } else {
2050                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2051                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2052                         rxq = dev->data->rx_queues[i];
2053                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2054                         ctrl |= IXGBE_RXDCTL_VME;
2055                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2056
2057                         /* record those setting for HW strip per queue */
2058                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2059                 }
2060         }
2061 }
2062
2063 static void
2064 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2065 {
2066         struct ixgbe_hw *hw =
2067                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2068         uint32_t ctrl;
2069
2070         PMD_INIT_FUNC_TRACE();
2071
2072         /* DMATXCTRL: Geric Double VLAN Disable */
2073         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2074         ctrl &= ~IXGBE_DMATXCTL_GDV;
2075         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2076
2077         /* CTRL_EXT: Global Double VLAN Disable */
2078         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2079         ctrl &= ~IXGBE_EXTENDED_VLAN;
2080         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2081
2082 }
2083
2084 static void
2085 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2086 {
2087         struct ixgbe_hw *hw =
2088                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2089         uint32_t ctrl;
2090
2091         PMD_INIT_FUNC_TRACE();
2092
2093         /* DMATXCTRL: Geric Double VLAN Enable */
2094         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2095         ctrl |= IXGBE_DMATXCTL_GDV;
2096         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2097
2098         /* CTRL_EXT: Global Double VLAN Enable */
2099         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2100         ctrl |= IXGBE_EXTENDED_VLAN;
2101         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2102
2103         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2104         if (hw->mac.type == ixgbe_mac_X550 ||
2105             hw->mac.type == ixgbe_mac_X550EM_x ||
2106             hw->mac.type == ixgbe_mac_X550EM_a) {
2107                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2108                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2109                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2110         }
2111
2112         /*
2113          * VET EXT field in the EXVET register = 0x8100 by default
2114          * So no need to change. Same to VT field of DMATXCTL register
2115          */
2116 }
2117
2118 static int
2119 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2120 {
2121         if (mask & ETH_VLAN_STRIP_MASK) {
2122                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2123                         ixgbe_vlan_hw_strip_enable_all(dev);
2124                 else
2125                         ixgbe_vlan_hw_strip_disable_all(dev);
2126         }
2127
2128         if (mask & ETH_VLAN_FILTER_MASK) {
2129                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2130                         ixgbe_vlan_hw_filter_enable(dev);
2131                 else
2132                         ixgbe_vlan_hw_filter_disable(dev);
2133         }
2134
2135         if (mask & ETH_VLAN_EXTEND_MASK) {
2136                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2137                         ixgbe_vlan_hw_extend_enable(dev);
2138                 else
2139                         ixgbe_vlan_hw_extend_disable(dev);
2140         }
2141
2142         return 0;
2143 }
2144
2145 static void
2146 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2147 {
2148         struct ixgbe_hw *hw =
2149                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2151         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2152
2153         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2154         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2155 }
2156
2157 static int
2158 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2159 {
2160         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2161
2162         switch (nb_rx_q) {
2163         case 1:
2164         case 2:
2165                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2166                 break;
2167         case 4:
2168                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2169                 break;
2170         default:
2171                 return -EINVAL;
2172         }
2173
2174         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2175                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2176         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2177                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2178         return 0;
2179 }
2180
2181 static int
2182 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2183 {
2184         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2185         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2186         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2187         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2188
2189         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2190                 /* check multi-queue mode */
2191                 switch (dev_conf->rxmode.mq_mode) {
2192                 case ETH_MQ_RX_VMDQ_DCB:
2193                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2194                         break;
2195                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2196                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2197                         PMD_INIT_LOG(ERR, "SRIOV active,"
2198                                         " unsupported mq_mode rx %d.",
2199                                         dev_conf->rxmode.mq_mode);
2200                         return -EINVAL;
2201                 case ETH_MQ_RX_RSS:
2202                 case ETH_MQ_RX_VMDQ_RSS:
2203                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2204                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2205                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2206                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2207                                                 " invalid queue number"
2208                                                 " for VMDQ RSS, allowed"
2209                                                 " value are 1, 2 or 4.");
2210                                         return -EINVAL;
2211                                 }
2212                         break;
2213                 case ETH_MQ_RX_VMDQ_ONLY:
2214                 case ETH_MQ_RX_NONE:
2215                         /* if nothing mq mode configure, use default scheme */
2216                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2217                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2218                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2219                         break;
2220                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2221                         /* SRIOV only works in VMDq enable mode */
2222                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2223                                         " wrong mq_mode rx %d.",
2224                                         dev_conf->rxmode.mq_mode);
2225                         return -EINVAL;
2226                 }
2227
2228                 switch (dev_conf->txmode.mq_mode) {
2229                 case ETH_MQ_TX_VMDQ_DCB:
2230                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2231                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2232                         break;
2233                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2234                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2235                         break;
2236                 }
2237
2238                 /* check valid queue number */
2239                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2240                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2241                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2242                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2243                                         " must be less than or equal to %d.",
2244                                         nb_rx_q, nb_tx_q,
2245                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2246                         return -EINVAL;
2247                 }
2248         } else {
2249                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2250                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2251                                           " not supported.");
2252                         return -EINVAL;
2253                 }
2254                 /* check configuration for vmdb+dcb mode */
2255                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2256                         const struct rte_eth_vmdq_dcb_conf *conf;
2257
2258                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2259                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2260                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2261                                 return -EINVAL;
2262                         }
2263                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2264                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2265                                conf->nb_queue_pools == ETH_32_POOLS)) {
2266                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2267                                                 " nb_queue_pools must be %d or %d.",
2268                                                 ETH_16_POOLS, ETH_32_POOLS);
2269                                 return -EINVAL;
2270                         }
2271                 }
2272                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2273                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2274
2275                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2276                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2277                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2278                                 return -EINVAL;
2279                         }
2280                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2281                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2282                                conf->nb_queue_pools == ETH_32_POOLS)) {
2283                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2284                                                 " nb_queue_pools != %d and"
2285                                                 " nb_queue_pools != %d.",
2286                                                 ETH_16_POOLS, ETH_32_POOLS);
2287                                 return -EINVAL;
2288                         }
2289                 }
2290
2291                 /* For DCB mode check our configuration before we go further */
2292                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2293                         const struct rte_eth_dcb_rx_conf *conf;
2294
2295                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2296                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2297                                                  IXGBE_DCB_NB_QUEUES);
2298                                 return -EINVAL;
2299                         }
2300                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2301                         if (!(conf->nb_tcs == ETH_4_TCS ||
2302                                conf->nb_tcs == ETH_8_TCS)) {
2303                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2304                                                 " and nb_tcs != %d.",
2305                                                 ETH_4_TCS, ETH_8_TCS);
2306                                 return -EINVAL;
2307                         }
2308                 }
2309
2310                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2311                         const struct rte_eth_dcb_tx_conf *conf;
2312
2313                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2314                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2315                                                  IXGBE_DCB_NB_QUEUES);
2316                                 return -EINVAL;
2317                         }
2318                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2319                         if (!(conf->nb_tcs == ETH_4_TCS ||
2320                                conf->nb_tcs == ETH_8_TCS)) {
2321                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2322                                                 " and nb_tcs != %d.",
2323                                                 ETH_4_TCS, ETH_8_TCS);
2324                                 return -EINVAL;
2325                         }
2326                 }
2327
2328                 /*
2329                  * When DCB/VT is off, maximum number of queues changes,
2330                  * except for 82598EB, which remains constant.
2331                  */
2332                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2333                                 hw->mac.type != ixgbe_mac_82598EB) {
2334                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2335                                 PMD_INIT_LOG(ERR,
2336                                              "Neither VT nor DCB are enabled, "
2337                                              "nb_tx_q > %d.",
2338                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2339                                 return -EINVAL;
2340                         }
2341                 }
2342         }
2343         return 0;
2344 }
2345
2346 static int
2347 ixgbe_dev_configure(struct rte_eth_dev *dev)
2348 {
2349         struct ixgbe_interrupt *intr =
2350                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2351         struct ixgbe_adapter *adapter =
2352                 (struct ixgbe_adapter *)dev->data->dev_private;
2353         int ret;
2354
2355         PMD_INIT_FUNC_TRACE();
2356         /* multipe queue mode checking */
2357         ret  = ixgbe_check_mq_mode(dev);
2358         if (ret != 0) {
2359                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2360                             ret);
2361                 return ret;
2362         }
2363
2364         /* set flag to update link status after init */
2365         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2366
2367         /*
2368          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2369          * allocation or vector Rx preconditions we will reset it.
2370          */
2371         adapter->rx_bulk_alloc_allowed = true;
2372         adapter->rx_vec_allowed = true;
2373
2374         return 0;
2375 }
2376
2377 static void
2378 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2379 {
2380         struct ixgbe_hw *hw =
2381                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2382         struct ixgbe_interrupt *intr =
2383                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2384         uint32_t gpie;
2385
2386         /* only set up it on X550EM_X */
2387         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2388                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2389                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2390                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2391                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2392                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2393         }
2394 }
2395
2396 int
2397 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2398                         uint16_t tx_rate, uint64_t q_msk)
2399 {
2400         struct ixgbe_hw *hw;
2401         struct ixgbe_vf_info *vfinfo;
2402         struct rte_eth_link link;
2403         uint8_t  nb_q_per_pool;
2404         uint32_t queue_stride;
2405         uint32_t queue_idx, idx = 0, vf_idx;
2406         uint32_t queue_end;
2407         uint16_t total_rate = 0;
2408         struct rte_pci_device *pci_dev;
2409
2410         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2411         rte_eth_link_get_nowait(dev->data->port_id, &link);
2412
2413         if (vf >= pci_dev->max_vfs)
2414                 return -EINVAL;
2415
2416         if (tx_rate > link.link_speed)
2417                 return -EINVAL;
2418
2419         if (q_msk == 0)
2420                 return 0;
2421
2422         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2423         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2424         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2425         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2426         queue_idx = vf * queue_stride;
2427         queue_end = queue_idx + nb_q_per_pool - 1;
2428         if (queue_end >= hw->mac.max_tx_queues)
2429                 return -EINVAL;
2430
2431         if (vfinfo) {
2432                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2433                         if (vf_idx == vf)
2434                                 continue;
2435                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2436                                 idx++)
2437                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2438                 }
2439         } else {
2440                 return -EINVAL;
2441         }
2442
2443         /* Store tx_rate for this vf. */
2444         for (idx = 0; idx < nb_q_per_pool; idx++) {
2445                 if (((uint64_t)0x1 << idx) & q_msk) {
2446                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2447                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2448                         total_rate += tx_rate;
2449                 }
2450         }
2451
2452         if (total_rate > dev->data->dev_link.link_speed) {
2453                 /* Reset stored TX rate of the VF if it causes exceed
2454                  * link speed.
2455                  */
2456                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2457                 return -EINVAL;
2458         }
2459
2460         /* Set RTTBCNRC of each queue/pool for vf X  */
2461         for (; queue_idx <= queue_end; queue_idx++) {
2462                 if (0x1 & q_msk)
2463                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2464                 q_msk = q_msk >> 1;
2465         }
2466
2467         return 0;
2468 }
2469
2470 /*
2471  * Configure device link speed and setup link.
2472  * It returns 0 on success.
2473  */
2474 static int
2475 ixgbe_dev_start(struct rte_eth_dev *dev)
2476 {
2477         struct ixgbe_hw *hw =
2478                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2479         struct ixgbe_vf_info *vfinfo =
2480                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2481         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2482         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2483         uint32_t intr_vector = 0;
2484         int err, link_up = 0, negotiate = 0;
2485         uint32_t speed = 0;
2486         int mask = 0;
2487         int status;
2488         uint16_t vf, idx;
2489         uint32_t *link_speeds;
2490         struct ixgbe_tm_conf *tm_conf =
2491                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2492
2493         PMD_INIT_FUNC_TRACE();
2494
2495         /* IXGBE devices don't support:
2496         *    - half duplex (checked afterwards for valid speeds)
2497         *    - fixed speed: TODO implement
2498         */
2499         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2500                 PMD_INIT_LOG(ERR,
2501                 "Invalid link_speeds for port %u, fix speed not supported",
2502                                 dev->data->port_id);
2503                 return -EINVAL;
2504         }
2505
2506         /* disable uio/vfio intr/eventfd mapping */
2507         rte_intr_disable(intr_handle);
2508
2509         /* stop adapter */
2510         hw->adapter_stopped = 0;
2511         ixgbe_stop_adapter(hw);
2512
2513         /* reinitialize adapter
2514          * this calls reset and start
2515          */
2516         status = ixgbe_pf_reset_hw(hw);
2517         if (status != 0)
2518                 return -1;
2519         hw->mac.ops.start_hw(hw);
2520         hw->mac.get_link_status = true;
2521
2522         /* configure PF module if SRIOV enabled */
2523         ixgbe_pf_host_configure(dev);
2524
2525         ixgbe_dev_phy_intr_setup(dev);
2526
2527         /* check and configure queue intr-vector mapping */
2528         if ((rte_intr_cap_multiple(intr_handle) ||
2529              !RTE_ETH_DEV_SRIOV(dev).active) &&
2530             dev->data->dev_conf.intr_conf.rxq != 0) {
2531                 intr_vector = dev->data->nb_rx_queues;
2532                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2533                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2534                                         IXGBE_MAX_INTR_QUEUE_NUM);
2535                         return -ENOTSUP;
2536                 }
2537                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2538                         return -1;
2539         }
2540
2541         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2542                 intr_handle->intr_vec =
2543                         rte_zmalloc("intr_vec",
2544                                     dev->data->nb_rx_queues * sizeof(int), 0);
2545                 if (intr_handle->intr_vec == NULL) {
2546                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2547                                      " intr_vec", dev->data->nb_rx_queues);
2548                         return -ENOMEM;
2549                 }
2550         }
2551
2552         /* confiugre msix for sleep until rx interrupt */
2553         ixgbe_configure_msix(dev);
2554
2555         /* initialize transmission unit */
2556         ixgbe_dev_tx_init(dev);
2557
2558         /* This can fail when allocating mbufs for descriptor rings */
2559         err = ixgbe_dev_rx_init(dev);
2560         if (err) {
2561                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2562                 goto error;
2563         }
2564
2565         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2566                 ETH_VLAN_EXTEND_MASK;
2567         err = ixgbe_vlan_offload_set(dev, mask);
2568         if (err) {
2569                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2570                 goto error;
2571         }
2572
2573         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2574                 /* Enable vlan filtering for VMDq */
2575                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2576         }
2577
2578         /* Configure DCB hw */
2579         ixgbe_configure_dcb(dev);
2580
2581         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2582                 err = ixgbe_fdir_configure(dev);
2583                 if (err)
2584                         goto error;
2585         }
2586
2587         /* Restore vf rate limit */
2588         if (vfinfo != NULL) {
2589                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2590                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2591                                 if (vfinfo[vf].tx_rate[idx] != 0)
2592                                         ixgbe_set_vf_rate_limit(
2593                                                 dev, vf,
2594                                                 vfinfo[vf].tx_rate[idx],
2595                                                 1 << idx);
2596         }
2597
2598         ixgbe_restore_statistics_mapping(dev);
2599
2600         err = ixgbe_dev_rxtx_start(dev);
2601         if (err < 0) {
2602                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2603                 goto error;
2604         }
2605
2606         /* Skip link setup if loopback mode is enabled for 82599. */
2607         if (hw->mac.type == ixgbe_mac_82599EB &&
2608                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2609                 goto skip_link_setup;
2610
2611         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2612                 err = hw->mac.ops.setup_sfp(hw);
2613                 if (err)
2614                         goto error;
2615         }
2616
2617         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2618                 /* Turn on the copper */
2619                 ixgbe_set_phy_power(hw, true);
2620         } else {
2621                 /* Turn on the laser */
2622                 ixgbe_enable_tx_laser(hw);
2623         }
2624
2625         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2626         if (err)
2627                 goto error;
2628         dev->data->dev_link.link_status = link_up;
2629
2630         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2631         if (err)
2632                 goto error;
2633
2634         link_speeds = &dev->data->dev_conf.link_speeds;
2635         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2636                         ETH_LINK_SPEED_10G)) {
2637                 PMD_INIT_LOG(ERR, "Invalid link setting");
2638                 goto error;
2639         }
2640
2641         speed = 0x0;
2642         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2643                 switch (hw->mac.type) {
2644                 case ixgbe_mac_82598EB:
2645                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2646                         break;
2647                 case ixgbe_mac_82599EB:
2648                 case ixgbe_mac_X540:
2649                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2650                         break;
2651                 case ixgbe_mac_X550:
2652                 case ixgbe_mac_X550EM_x:
2653                 case ixgbe_mac_X550EM_a:
2654                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2655                         break;
2656                 default:
2657                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2658                 }
2659         } else {
2660                 if (*link_speeds & ETH_LINK_SPEED_10G)
2661                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2662                 if (*link_speeds & ETH_LINK_SPEED_1G)
2663                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2664                 if (*link_speeds & ETH_LINK_SPEED_100M)
2665                         speed |= IXGBE_LINK_SPEED_100_FULL;
2666         }
2667
2668         err = ixgbe_setup_link(hw, speed, link_up);
2669         if (err)
2670                 goto error;
2671
2672 skip_link_setup:
2673
2674         if (rte_intr_allow_others(intr_handle)) {
2675                 /* check if lsc interrupt is enabled */
2676                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2677                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2678                 else
2679                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2680                 ixgbe_dev_macsec_interrupt_setup(dev);
2681         } else {
2682                 rte_intr_callback_unregister(intr_handle,
2683                                              ixgbe_dev_interrupt_handler, dev);
2684                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2685                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2686                                      " no intr multiplex");
2687         }
2688
2689         /* check if rxq interrupt is enabled */
2690         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2691             rte_intr_dp_is_en(intr_handle))
2692                 ixgbe_dev_rxq_interrupt_setup(dev);
2693
2694         /* enable uio/vfio intr/eventfd mapping */
2695         rte_intr_enable(intr_handle);
2696
2697         /* resume enabled intr since hw reset */
2698         ixgbe_enable_intr(dev);
2699         ixgbe_l2_tunnel_conf(dev);
2700         ixgbe_filter_restore(dev);
2701
2702         if (tm_conf->root && !tm_conf->committed)
2703                 PMD_DRV_LOG(WARNING,
2704                             "please call hierarchy_commit() "
2705                             "before starting the port");
2706
2707         return 0;
2708
2709 error:
2710         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2711         ixgbe_dev_clear_queues(dev);
2712         return -EIO;
2713 }
2714
2715 /*
2716  * Stop device: disable rx and tx functions to allow for reconfiguring.
2717  */
2718 static void
2719 ixgbe_dev_stop(struct rte_eth_dev *dev)
2720 {
2721         struct rte_eth_link link;
2722         struct ixgbe_hw *hw =
2723                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2724         struct ixgbe_vf_info *vfinfo =
2725                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2726         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2727         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2728         int vf;
2729         struct ixgbe_tm_conf *tm_conf =
2730                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2731
2732         PMD_INIT_FUNC_TRACE();
2733
2734         /* disable interrupts */
2735         ixgbe_disable_intr(hw);
2736
2737         /* reset the NIC */
2738         ixgbe_pf_reset_hw(hw);
2739         hw->adapter_stopped = 0;
2740
2741         /* stop adapter */
2742         ixgbe_stop_adapter(hw);
2743
2744         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2745                 vfinfo[vf].clear_to_send = false;
2746
2747         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2748                 /* Turn off the copper */
2749                 ixgbe_set_phy_power(hw, false);
2750         } else {
2751                 /* Turn off the laser */
2752                 ixgbe_disable_tx_laser(hw);
2753         }
2754
2755         ixgbe_dev_clear_queues(dev);
2756
2757         /* Clear stored conf */
2758         dev->data->scattered_rx = 0;
2759         dev->data->lro = 0;
2760
2761         /* Clear recorded link status */
2762         memset(&link, 0, sizeof(link));
2763         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2764
2765         if (!rte_intr_allow_others(intr_handle))
2766                 /* resume to the default handler */
2767                 rte_intr_callback_register(intr_handle,
2768                                            ixgbe_dev_interrupt_handler,
2769                                            (void *)dev);
2770
2771         /* Clean datapath event and queue/vec mapping */
2772         rte_intr_efd_disable(intr_handle);
2773         if (intr_handle->intr_vec != NULL) {
2774                 rte_free(intr_handle->intr_vec);
2775                 intr_handle->intr_vec = NULL;
2776         }
2777
2778         /* reset hierarchy commit */
2779         tm_conf->committed = false;
2780 }
2781
2782 /*
2783  * Set device link up: enable tx.
2784  */
2785 static int
2786 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2787 {
2788         struct ixgbe_hw *hw =
2789                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2790         if (hw->mac.type == ixgbe_mac_82599EB) {
2791 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2792                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2793                         /* Not suported in bypass mode */
2794                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2795                                      "by device id 0x%x", hw->device_id);
2796                         return -ENOTSUP;
2797                 }
2798 #endif
2799         }
2800
2801         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2802                 /* Turn on the copper */
2803                 ixgbe_set_phy_power(hw, true);
2804         } else {
2805                 /* Turn on the laser */
2806                 ixgbe_enable_tx_laser(hw);
2807         }
2808
2809         return 0;
2810 }
2811
2812 /*
2813  * Set device link down: disable tx.
2814  */
2815 static int
2816 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2817 {
2818         struct ixgbe_hw *hw =
2819                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2820         if (hw->mac.type == ixgbe_mac_82599EB) {
2821 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2822                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2823                         /* Not suported in bypass mode */
2824                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2825                                      "by device id 0x%x", hw->device_id);
2826                         return -ENOTSUP;
2827                 }
2828 #endif
2829         }
2830
2831         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2832                 /* Turn off the copper */
2833                 ixgbe_set_phy_power(hw, false);
2834         } else {
2835                 /* Turn off the laser */
2836                 ixgbe_disable_tx_laser(hw);
2837         }
2838
2839         return 0;
2840 }
2841
2842 /*
2843  * Reset and stop device.
2844  */
2845 static void
2846 ixgbe_dev_close(struct rte_eth_dev *dev)
2847 {
2848         struct ixgbe_hw *hw =
2849                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2850
2851         PMD_INIT_FUNC_TRACE();
2852
2853         ixgbe_pf_reset_hw(hw);
2854
2855         ixgbe_dev_stop(dev);
2856         hw->adapter_stopped = 1;
2857
2858         ixgbe_dev_free_queues(dev);
2859
2860         ixgbe_disable_pcie_master(hw);
2861
2862         /* reprogram the RAR[0] in case user changed it. */
2863         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2864 }
2865
2866 /*
2867  * Reset PF device.
2868  */
2869 static int
2870 ixgbe_dev_reset(struct rte_eth_dev *dev)
2871 {
2872         int ret;
2873
2874         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2875          * its VF to make them align with it. The detailed notification
2876          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2877          * To avoid unexpected behavior in VF, currently reset of PF with
2878          * SR-IOV activation is not supported. It might be supported later.
2879          */
2880         if (dev->data->sriov.active)
2881                 return -ENOTSUP;
2882
2883         ret = eth_ixgbe_dev_uninit(dev);
2884         if (ret)
2885                 return ret;
2886
2887         ret = eth_ixgbe_dev_init(dev);
2888
2889         return ret;
2890 }
2891
2892 static void
2893 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2894                            struct ixgbe_hw_stats *hw_stats,
2895                            struct ixgbe_macsec_stats *macsec_stats,
2896                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2897                            uint64_t *total_qprc, uint64_t *total_qprdc)
2898 {
2899         uint32_t bprc, lxon, lxoff, total;
2900         uint32_t delta_gprc = 0;
2901         unsigned i;
2902         /* Workaround for RX byte count not including CRC bytes when CRC
2903          * strip is enabled. CRC bytes are removed from counters when crc_strip
2904          * is disabled.
2905          */
2906         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2907                         IXGBE_HLREG0_RXCRCSTRP);
2908
2909         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2910         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2911         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2912         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2913
2914         for (i = 0; i < 8; i++) {
2915                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2916
2917                 /* global total per queue */
2918                 hw_stats->mpc[i] += mp;
2919                 /* Running comprehensive total for stats display */
2920                 *total_missed_rx += hw_stats->mpc[i];
2921                 if (hw->mac.type == ixgbe_mac_82598EB) {
2922                         hw_stats->rnbc[i] +=
2923                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2924                         hw_stats->pxonrxc[i] +=
2925                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2926                         hw_stats->pxoffrxc[i] +=
2927                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2928                 } else {
2929                         hw_stats->pxonrxc[i] +=
2930                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2931                         hw_stats->pxoffrxc[i] +=
2932                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2933                         hw_stats->pxon2offc[i] +=
2934                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2935                 }
2936                 hw_stats->pxontxc[i] +=
2937                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2938                 hw_stats->pxofftxc[i] +=
2939                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2940         }
2941         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2942                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2943                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2944                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2945
2946                 delta_gprc += delta_qprc;
2947
2948                 hw_stats->qprc[i] += delta_qprc;
2949                 hw_stats->qptc[i] += delta_qptc;
2950
2951                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2952                 hw_stats->qbrc[i] +=
2953                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2954                 if (crc_strip == 0)
2955                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2956
2957                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2958                 hw_stats->qbtc[i] +=
2959                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2960
2961                 hw_stats->qprdc[i] += delta_qprdc;
2962                 *total_qprdc += hw_stats->qprdc[i];
2963
2964                 *total_qprc += hw_stats->qprc[i];
2965                 *total_qbrc += hw_stats->qbrc[i];
2966         }
2967         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2968         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2969         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2970
2971         /*
2972          * An errata states that gprc actually counts good + missed packets:
2973          * Workaround to set gprc to summated queue packet receives
2974          */
2975         hw_stats->gprc = *total_qprc;
2976
2977         if (hw->mac.type != ixgbe_mac_82598EB) {
2978                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2979                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2980                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2981                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2982                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2983                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2984                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2985                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2986         } else {
2987                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2988                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2989                 /* 82598 only has a counter in the high register */
2990                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2991                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2992                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2993         }
2994         uint64_t old_tpr = hw_stats->tpr;
2995
2996         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2997         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2998
2999         if (crc_strip == 0)
3000                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3001
3002         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3003         hw_stats->gptc += delta_gptc;
3004         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3005         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3006
3007         /*
3008          * Workaround: mprc hardware is incorrectly counting
3009          * broadcasts, so for now we subtract those.
3010          */
3011         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3012         hw_stats->bprc += bprc;
3013         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3014         if (hw->mac.type == ixgbe_mac_82598EB)
3015                 hw_stats->mprc -= bprc;
3016
3017         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3018         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3019         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3020         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3021         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3022         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3023
3024         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3025         hw_stats->lxontxc += lxon;
3026         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3027         hw_stats->lxofftxc += lxoff;
3028         total = lxon + lxoff;
3029
3030         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3031         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3032         hw_stats->gptc -= total;
3033         hw_stats->mptc -= total;
3034         hw_stats->ptc64 -= total;
3035         hw_stats->gotc -= total * ETHER_MIN_LEN;
3036
3037         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3038         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3039         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3040         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3041         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3042         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3043         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3044         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3045         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3046         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3047         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3048         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3049         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3050         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3051         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3052         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3053         /* Only read FCOE on 82599 */
3054         if (hw->mac.type != ixgbe_mac_82598EB) {
3055                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3056                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3057                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3058                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3059                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3060         }
3061
3062         /* Flow Director Stats registers */
3063         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3064         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3065
3066         /* MACsec Stats registers */
3067         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3068         macsec_stats->out_pkts_encrypted +=
3069                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3070         macsec_stats->out_pkts_protected +=
3071                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3072         macsec_stats->out_octets_encrypted +=
3073                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3074         macsec_stats->out_octets_protected +=
3075                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3076         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3077         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3078         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3079         macsec_stats->in_pkts_unknownsci +=
3080                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3081         macsec_stats->in_octets_decrypted +=
3082                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3083         macsec_stats->in_octets_validated +=
3084                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3085         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3086         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3087         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3088         for (i = 0; i < 2; i++) {
3089                 macsec_stats->in_pkts_ok +=
3090                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3091                 macsec_stats->in_pkts_invalid +=
3092                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3093                 macsec_stats->in_pkts_notvalid +=
3094                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3095         }
3096         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3097         macsec_stats->in_pkts_notusingsa +=
3098                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3099 }
3100
3101 /*
3102  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3103  */
3104 static int
3105 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3106 {
3107         struct ixgbe_hw *hw =
3108                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3109         struct ixgbe_hw_stats *hw_stats =
3110                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3111         struct ixgbe_macsec_stats *macsec_stats =
3112                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3113                                 dev->data->dev_private);
3114         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3115         unsigned i;
3116
3117         total_missed_rx = 0;
3118         total_qbrc = 0;
3119         total_qprc = 0;
3120         total_qprdc = 0;
3121
3122         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3123                         &total_qbrc, &total_qprc, &total_qprdc);
3124
3125         if (stats == NULL)
3126                 return -EINVAL;
3127
3128         /* Fill out the rte_eth_stats statistics structure */
3129         stats->ipackets = total_qprc;
3130         stats->ibytes = total_qbrc;
3131         stats->opackets = hw_stats->gptc;
3132         stats->obytes = hw_stats->gotc;
3133
3134         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3135                 stats->q_ipackets[i] = hw_stats->qprc[i];
3136                 stats->q_opackets[i] = hw_stats->qptc[i];
3137                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3138                 stats->q_obytes[i] = hw_stats->qbtc[i];
3139                 stats->q_errors[i] = hw_stats->qprdc[i];
3140         }
3141
3142         /* Rx Errors */
3143         stats->imissed  = total_missed_rx;
3144         stats->ierrors  = hw_stats->crcerrs +
3145                           hw_stats->mspdc +
3146                           hw_stats->rlec +
3147                           hw_stats->ruc +
3148                           hw_stats->roc +
3149                           hw_stats->illerrc +
3150                           hw_stats->errbc +
3151                           hw_stats->rfc +
3152                           hw_stats->fccrc +
3153                           hw_stats->fclast;
3154
3155         /* Tx Errors */
3156         stats->oerrors  = 0;
3157         return 0;
3158 }
3159
3160 static void
3161 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3162 {
3163         struct ixgbe_hw_stats *stats =
3164                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3165
3166         /* HW registers are cleared on read */
3167         ixgbe_dev_stats_get(dev, NULL);
3168
3169         /* Reset software totals */
3170         memset(stats, 0, sizeof(*stats));
3171 }
3172
3173 /* This function calculates the number of xstats based on the current config */
3174 static unsigned
3175 ixgbe_xstats_calc_num(void) {
3176         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3177                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3178                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3179 }
3180
3181 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3182         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3183 {
3184         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3185         unsigned stat, i, count;
3186
3187         if (xstats_names != NULL) {
3188                 count = 0;
3189
3190                 /* Note: limit >= cnt_stats checked upstream
3191                  * in rte_eth_xstats_names()
3192                  */
3193
3194                 /* Extended stats from ixgbe_hw_stats */
3195                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3196                         snprintf(xstats_names[count].name,
3197                                 sizeof(xstats_names[count].name),
3198                                 "%s",
3199                                 rte_ixgbe_stats_strings[i].name);
3200                         count++;
3201                 }
3202
3203                 /* MACsec Stats */
3204                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3205                         snprintf(xstats_names[count].name,
3206                                 sizeof(xstats_names[count].name),
3207                                 "%s",
3208                                 rte_ixgbe_macsec_strings[i].name);
3209                         count++;
3210                 }
3211
3212                 /* RX Priority Stats */
3213                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3214                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3215                                 snprintf(xstats_names[count].name,
3216                                         sizeof(xstats_names[count].name),
3217                                         "rx_priority%u_%s", i,
3218                                         rte_ixgbe_rxq_strings[stat].name);
3219                                 count++;
3220                         }
3221                 }
3222
3223                 /* TX Priority Stats */
3224                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3225                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3226                                 snprintf(xstats_names[count].name,
3227                                         sizeof(xstats_names[count].name),
3228                                         "tx_priority%u_%s", i,
3229                                         rte_ixgbe_txq_strings[stat].name);
3230                                 count++;
3231                         }
3232                 }
3233         }
3234         return cnt_stats;
3235 }
3236
3237 static int ixgbe_dev_xstats_get_names_by_id(
3238         struct rte_eth_dev *dev,
3239         struct rte_eth_xstat_name *xstats_names,
3240         const uint64_t *ids,
3241         unsigned int limit)
3242 {
3243         if (!ids) {
3244                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3245                 unsigned int stat, i, count;
3246
3247                 if (xstats_names != NULL) {
3248                         count = 0;
3249
3250                         /* Note: limit >= cnt_stats checked upstream
3251                          * in rte_eth_xstats_names()
3252                          */
3253
3254                         /* Extended stats from ixgbe_hw_stats */
3255                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3256                                 snprintf(xstats_names[count].name,
3257                                         sizeof(xstats_names[count].name),
3258                                         "%s",
3259                                         rte_ixgbe_stats_strings[i].name);
3260                                 count++;
3261                         }
3262
3263                         /* MACsec Stats */
3264                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3265                                 snprintf(xstats_names[count].name,
3266                                         sizeof(xstats_names[count].name),
3267                                         "%s",
3268                                         rte_ixgbe_macsec_strings[i].name);
3269                                 count++;
3270                         }
3271
3272                         /* RX Priority Stats */
3273                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3274                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3275                                         snprintf(xstats_names[count].name,
3276                                             sizeof(xstats_names[count].name),
3277                                             "rx_priority%u_%s", i,
3278                                             rte_ixgbe_rxq_strings[stat].name);
3279                                         count++;
3280                                 }
3281                         }
3282
3283                         /* TX Priority Stats */
3284                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3285                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3286                                         snprintf(xstats_names[count].name,
3287                                             sizeof(xstats_names[count].name),
3288                                             "tx_priority%u_%s", i,
3289                                             rte_ixgbe_txq_strings[stat].name);
3290                                         count++;
3291                                 }
3292                         }
3293                 }
3294                 return cnt_stats;
3295         }
3296
3297         uint16_t i;
3298         uint16_t size = ixgbe_xstats_calc_num();
3299         struct rte_eth_xstat_name xstats_names_copy[size];
3300
3301         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3302                         size);
3303
3304         for (i = 0; i < limit; i++) {
3305                 if (ids[i] >= size) {
3306                         PMD_INIT_LOG(ERR, "id value isn't valid");
3307                         return -1;
3308                 }
3309                 strcpy(xstats_names[i].name,
3310                                 xstats_names_copy[ids[i]].name);
3311         }
3312         return limit;
3313 }
3314
3315 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3316         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3317 {
3318         unsigned i;
3319
3320         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3321                 return -ENOMEM;
3322
3323         if (xstats_names != NULL)
3324                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3325                         snprintf(xstats_names[i].name,
3326                                 sizeof(xstats_names[i].name),
3327                                 "%s", rte_ixgbevf_stats_strings[i].name);
3328         return IXGBEVF_NB_XSTATS;
3329 }
3330
3331 static int
3332 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3333                                          unsigned n)
3334 {
3335         struct ixgbe_hw *hw =
3336                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3337         struct ixgbe_hw_stats *hw_stats =
3338                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3339         struct ixgbe_macsec_stats *macsec_stats =
3340                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3341                                 dev->data->dev_private);
3342         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3343         unsigned i, stat, count = 0;
3344
3345         count = ixgbe_xstats_calc_num();
3346
3347         if (n < count)
3348                 return count;
3349
3350         total_missed_rx = 0;
3351         total_qbrc = 0;
3352         total_qprc = 0;
3353         total_qprdc = 0;
3354
3355         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3356                         &total_qbrc, &total_qprc, &total_qprdc);
3357
3358         /* If this is a reset xstats is NULL, and we have cleared the
3359          * registers by reading them.
3360          */
3361         if (!xstats)
3362                 return 0;
3363
3364         /* Extended stats from ixgbe_hw_stats */
3365         count = 0;
3366         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3367                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3368                                 rte_ixgbe_stats_strings[i].offset);
3369                 xstats[count].id = count;
3370                 count++;
3371         }
3372
3373         /* MACsec Stats */
3374         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3375                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3376                                 rte_ixgbe_macsec_strings[i].offset);
3377                 xstats[count].id = count;
3378                 count++;
3379         }
3380
3381         /* RX Priority Stats */
3382         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3383                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3384                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3385                                         rte_ixgbe_rxq_strings[stat].offset +
3386                                         (sizeof(uint64_t) * i));
3387                         xstats[count].id = count;
3388                         count++;
3389                 }
3390         }
3391
3392         /* TX Priority Stats */
3393         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3394                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3395                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3396                                         rte_ixgbe_txq_strings[stat].offset +
3397                                         (sizeof(uint64_t) * i));
3398                         xstats[count].id = count;
3399                         count++;
3400                 }
3401         }
3402         return count;
3403 }
3404
3405 static int
3406 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3407                 uint64_t *values, unsigned int n)
3408 {
3409         if (!ids) {
3410                 struct ixgbe_hw *hw =
3411                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3412                 struct ixgbe_hw_stats *hw_stats =
3413                                 IXGBE_DEV_PRIVATE_TO_STATS(
3414                                                 dev->data->dev_private);
3415                 struct ixgbe_macsec_stats *macsec_stats =
3416                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3417                                         dev->data->dev_private);
3418                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3419                 unsigned int i, stat, count = 0;
3420
3421                 count = ixgbe_xstats_calc_num();
3422
3423                 if (!ids && n < count)
3424                         return count;
3425
3426                 total_missed_rx = 0;
3427                 total_qbrc = 0;
3428                 total_qprc = 0;
3429                 total_qprdc = 0;
3430
3431                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3432                                 &total_missed_rx, &total_qbrc, &total_qprc,
3433                                 &total_qprdc);
3434
3435                 /* If this is a reset xstats is NULL, and we have cleared the
3436                  * registers by reading them.
3437                  */
3438                 if (!ids && !values)
3439                         return 0;
3440
3441                 /* Extended stats from ixgbe_hw_stats */
3442                 count = 0;
3443                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3444                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3445                                         rte_ixgbe_stats_strings[i].offset);
3446                         count++;
3447                 }
3448
3449                 /* MACsec Stats */
3450                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3451                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3452                                         rte_ixgbe_macsec_strings[i].offset);
3453                         count++;
3454                 }
3455
3456                 /* RX Priority Stats */
3457                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3458                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3459                                 values[count] =
3460                                         *(uint64_t *)(((char *)hw_stats) +
3461                                         rte_ixgbe_rxq_strings[stat].offset +
3462                                         (sizeof(uint64_t) * i));
3463                                 count++;
3464                         }
3465                 }
3466
3467                 /* TX Priority Stats */
3468                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3469                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3470                                 values[count] =
3471                                         *(uint64_t *)(((char *)hw_stats) +
3472                                         rte_ixgbe_txq_strings[stat].offset +
3473                                         (sizeof(uint64_t) * i));
3474                                 count++;
3475                         }
3476                 }
3477                 return count;
3478         }
3479
3480         uint16_t i;
3481         uint16_t size = ixgbe_xstats_calc_num();
3482         uint64_t values_copy[size];
3483
3484         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3485
3486         for (i = 0; i < n; i++) {
3487                 if (ids[i] >= size) {
3488                         PMD_INIT_LOG(ERR, "id value isn't valid");
3489                         return -1;
3490                 }
3491                 values[i] = values_copy[ids[i]];
3492         }
3493         return n;
3494 }
3495
3496 static void
3497 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3498 {
3499         struct ixgbe_hw_stats *stats =
3500                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3501         struct ixgbe_macsec_stats *macsec_stats =
3502                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3503                                 dev->data->dev_private);
3504
3505         unsigned count = ixgbe_xstats_calc_num();
3506
3507         /* HW registers are cleared on read */
3508         ixgbe_dev_xstats_get(dev, NULL, count);
3509
3510         /* Reset software totals */
3511         memset(stats, 0, sizeof(*stats));
3512         memset(macsec_stats, 0, sizeof(*macsec_stats));
3513 }
3514
3515 static void
3516 ixgbevf_update_stats(struct rte_eth_dev *dev)
3517 {
3518         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3519         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3520                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3521
3522         /* Good Rx packet, include VF loopback */
3523         UPDATE_VF_STAT(IXGBE_VFGPRC,
3524             hw_stats->last_vfgprc, hw_stats->vfgprc);
3525
3526         /* Good Rx octets, include VF loopback */
3527         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3528             hw_stats->last_vfgorc, hw_stats->vfgorc);
3529
3530         /* Good Tx packet, include VF loopback */
3531         UPDATE_VF_STAT(IXGBE_VFGPTC,
3532             hw_stats->last_vfgptc, hw_stats->vfgptc);
3533
3534         /* Good Tx octets, include VF loopback */
3535         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3536             hw_stats->last_vfgotc, hw_stats->vfgotc);
3537
3538         /* Rx Multicst Packet */
3539         UPDATE_VF_STAT(IXGBE_VFMPRC,
3540             hw_stats->last_vfmprc, hw_stats->vfmprc);
3541 }
3542
3543 static int
3544 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3545                        unsigned n)
3546 {
3547         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3548                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3549         unsigned i;
3550
3551         if (n < IXGBEVF_NB_XSTATS)
3552                 return IXGBEVF_NB_XSTATS;
3553
3554         ixgbevf_update_stats(dev);
3555
3556         if (!xstats)
3557                 return 0;
3558
3559         /* Extended stats */
3560         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3561                 xstats[i].id = i;
3562                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3563                         rte_ixgbevf_stats_strings[i].offset);
3564         }
3565
3566         return IXGBEVF_NB_XSTATS;
3567 }
3568
3569 static int
3570 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3571 {
3572         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3573                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3574
3575         ixgbevf_update_stats(dev);
3576
3577         if (stats == NULL)
3578                 return -EINVAL;
3579
3580         stats->ipackets = hw_stats->vfgprc;
3581         stats->ibytes = hw_stats->vfgorc;
3582         stats->opackets = hw_stats->vfgptc;
3583         stats->obytes = hw_stats->vfgotc;
3584         return 0;
3585 }
3586
3587 static void
3588 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3589 {
3590         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3591                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3592
3593         /* Sync HW register to the last stats */
3594         ixgbevf_dev_stats_get(dev, NULL);
3595
3596         /* reset HW current stats*/
3597         hw_stats->vfgprc = 0;
3598         hw_stats->vfgorc = 0;
3599         hw_stats->vfgptc = 0;
3600         hw_stats->vfgotc = 0;
3601 }
3602
3603 static int
3604 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3605 {
3606         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3607         u16 eeprom_verh, eeprom_verl;
3608         u32 etrack_id;
3609         int ret;
3610
3611         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3612         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3613
3614         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3615         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3616
3617         ret += 1; /* add the size of '\0' */
3618         if (fw_size < (u32)ret)
3619                 return ret;
3620         else
3621                 return 0;
3622 }
3623
3624 static void
3625 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3626 {
3627         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3628         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3629         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3630
3631         dev_info->pci_dev = pci_dev;
3632         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3633         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3634         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3635                 /*
3636                  * When DCB/VT is off, maximum number of queues changes,
3637                  * except for 82598EB, which remains constant.
3638                  */
3639                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3640                                 hw->mac.type != ixgbe_mac_82598EB)
3641                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3642         }
3643         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3644         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3645         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3646         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3647         dev_info->max_vfs = pci_dev->max_vfs;
3648         if (hw->mac.type == ixgbe_mac_82598EB)
3649                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3650         else
3651                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3652         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3653         dev_info->rx_offload_capa =
3654                 DEV_RX_OFFLOAD_VLAN_STRIP |
3655                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3656                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3657                 DEV_RX_OFFLOAD_TCP_CKSUM;
3658
3659         /*
3660          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3661          * mode.
3662          */
3663         if ((hw->mac.type == ixgbe_mac_82599EB ||
3664              hw->mac.type == ixgbe_mac_X540) &&
3665             !RTE_ETH_DEV_SRIOV(dev).active)
3666                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3667
3668         if (hw->mac.type == ixgbe_mac_82599EB ||
3669             hw->mac.type == ixgbe_mac_X540)
3670                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3671
3672         if (hw->mac.type == ixgbe_mac_X550 ||
3673             hw->mac.type == ixgbe_mac_X550EM_x ||
3674             hw->mac.type == ixgbe_mac_X550EM_a)
3675                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3676
3677         dev_info->tx_offload_capa =
3678                 DEV_TX_OFFLOAD_VLAN_INSERT |
3679                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3680                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3681                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3682                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3683                 DEV_TX_OFFLOAD_TCP_TSO;
3684
3685         if (hw->mac.type == ixgbe_mac_82599EB ||
3686             hw->mac.type == ixgbe_mac_X540)
3687                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3688
3689         if (hw->mac.type == ixgbe_mac_X550 ||
3690             hw->mac.type == ixgbe_mac_X550EM_x ||
3691             hw->mac.type == ixgbe_mac_X550EM_a)
3692                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3693
3694 #ifdef RTE_LIBRTE_SECURITY
3695         dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_SECURITY;
3696         dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
3697 #endif
3698
3699         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3700                 .rx_thresh = {
3701                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3702                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3703                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3704                 },
3705                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3706                 .rx_drop_en = 0,
3707         };
3708
3709         dev_info->default_txconf = (struct rte_eth_txconf) {
3710                 .tx_thresh = {
3711                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3712                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3713                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3714                 },
3715                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3716                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3717                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3718                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3719         };
3720
3721         dev_info->rx_desc_lim = rx_desc_lim;
3722         dev_info->tx_desc_lim = tx_desc_lim;
3723
3724         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3725         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3726         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3727
3728         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3729         if (hw->mac.type == ixgbe_mac_X540 ||
3730             hw->mac.type == ixgbe_mac_X540_vf ||
3731             hw->mac.type == ixgbe_mac_X550 ||
3732             hw->mac.type == ixgbe_mac_X550_vf) {
3733                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3734         }
3735         if (hw->mac.type == ixgbe_mac_X550) {
3736                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3737                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3738         }
3739 }
3740
3741 static const uint32_t *
3742 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3743 {
3744         static const uint32_t ptypes[] = {
3745                 /* For non-vec functions,
3746                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3747                  * for vec functions,
3748                  * refers to _recv_raw_pkts_vec().
3749                  */
3750                 RTE_PTYPE_L2_ETHER,
3751                 RTE_PTYPE_L3_IPV4,
3752                 RTE_PTYPE_L3_IPV4_EXT,
3753                 RTE_PTYPE_L3_IPV6,
3754                 RTE_PTYPE_L3_IPV6_EXT,
3755                 RTE_PTYPE_L4_SCTP,
3756                 RTE_PTYPE_L4_TCP,
3757                 RTE_PTYPE_L4_UDP,
3758                 RTE_PTYPE_TUNNEL_IP,
3759                 RTE_PTYPE_INNER_L3_IPV6,
3760                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3761                 RTE_PTYPE_INNER_L4_TCP,
3762                 RTE_PTYPE_INNER_L4_UDP,
3763                 RTE_PTYPE_UNKNOWN
3764         };
3765
3766         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3767             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3768             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3769             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3770                 return ptypes;
3771
3772 #if defined(RTE_ARCH_X86)
3773         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3774             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3775                 return ptypes;
3776 #endif
3777         return NULL;
3778 }
3779
3780 static void
3781 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3782                      struct rte_eth_dev_info *dev_info)
3783 {
3784         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3785         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3786
3787         dev_info->pci_dev = pci_dev;
3788         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3789         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3790         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3791         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3792         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3793         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3794         dev_info->max_vfs = pci_dev->max_vfs;
3795         if (hw->mac.type == ixgbe_mac_82598EB)
3796                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3797         else
3798                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3799         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3800                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3801                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3802                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3803         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3804                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3805                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3806                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3807                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3808                                 DEV_TX_OFFLOAD_TCP_TSO;
3809
3810         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3811                 .rx_thresh = {
3812                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3813                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3814                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3815                 },
3816                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3817                 .rx_drop_en = 0,
3818         };
3819
3820         dev_info->default_txconf = (struct rte_eth_txconf) {
3821                 .tx_thresh = {
3822                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3823                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3824                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3825                 },
3826                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3827                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3828                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3829                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3830         };
3831
3832         dev_info->rx_desc_lim = rx_desc_lim;
3833         dev_info->tx_desc_lim = tx_desc_lim;
3834 }
3835
3836 static int
3837 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3838                    int *link_up, int wait_to_complete)
3839 {
3840         /**
3841          * for a quick link status checking, wait_to_compelet == 0,
3842          * skip PF link status checking
3843          */
3844         bool no_pflink_check = wait_to_complete == 0;
3845         struct ixgbe_mbx_info *mbx = &hw->mbx;
3846         struct ixgbe_mac_info *mac = &hw->mac;
3847         uint32_t links_reg, in_msg;
3848         int ret_val = 0;
3849
3850         /* If we were hit with a reset drop the link */
3851         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3852                 mac->get_link_status = true;
3853
3854         if (!mac->get_link_status)
3855                 goto out;
3856
3857         /* if link status is down no point in checking to see if pf is up */
3858         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3859         if (!(links_reg & IXGBE_LINKS_UP))
3860                 goto out;
3861
3862         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3863          * before the link status is correct
3864          */
3865         if (mac->type == ixgbe_mac_82599_vf) {
3866                 int i;
3867
3868                 for (i = 0; i < 5; i++) {
3869                         rte_delay_us(100);
3870                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3871
3872                         if (!(links_reg & IXGBE_LINKS_UP))
3873                                 goto out;
3874                 }
3875         }
3876
3877         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3878         case IXGBE_LINKS_SPEED_10G_82599:
3879                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3880                 if (hw->mac.type >= ixgbe_mac_X550) {
3881                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3882                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3883                 }
3884                 break;
3885         case IXGBE_LINKS_SPEED_1G_82599:
3886                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3887                 break;
3888         case IXGBE_LINKS_SPEED_100_82599:
3889                 *speed = IXGBE_LINK_SPEED_100_FULL;
3890                 if (hw->mac.type == ixgbe_mac_X550) {
3891                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3892                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3893                 }
3894                 break;
3895         case IXGBE_LINKS_SPEED_10_X550EM_A:
3896                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3897                 /* Since Reserved in older MAC's */
3898                 if (hw->mac.type >= ixgbe_mac_X550)
3899                         *speed = IXGBE_LINK_SPEED_10_FULL;
3900                 break;
3901         default:
3902                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3903         }
3904
3905         if (no_pflink_check) {
3906                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3907                         mac->get_link_status = true;
3908                 else
3909                         mac->get_link_status = false;
3910
3911                 goto out;
3912         }
3913         /* if the read failed it could just be a mailbox collision, best wait
3914          * until we are called again and don't report an error
3915          */
3916         if (mbx->ops.read(hw, &in_msg, 1, 0))
3917                 goto out;
3918
3919         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3920                 /* msg is not CTS and is NACK we must have lost CTS status */
3921                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3922                         ret_val = -1;
3923                 goto out;
3924         }
3925
3926         /* the pf is talking, if we timed out in the past we reinit */
3927         if (!mbx->timeout) {
3928                 ret_val = -1;
3929                 goto out;
3930         }
3931
3932         /* if we passed all the tests above then the link is up and we no
3933          * longer need to check for link
3934          */
3935         mac->get_link_status = false;
3936
3937 out:
3938         *link_up = !mac->get_link_status;
3939         return ret_val;
3940 }
3941
3942 /* return 0 means link status changed, -1 means not changed */
3943 static int
3944 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3945                             int wait_to_complete, int vf)
3946 {
3947         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3948         struct rte_eth_link link, old;
3949         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3950         struct ixgbe_interrupt *intr =
3951                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3952         int link_up;
3953         int diag;
3954         u32 speed = 0;
3955         int wait = 1;
3956         bool autoneg = false;
3957
3958         link.link_status = ETH_LINK_DOWN;
3959         link.link_speed = 0;
3960         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3961         link.link_autoneg = ETH_LINK_AUTONEG;
3962         memset(&old, 0, sizeof(old));
3963         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3964
3965         hw->mac.get_link_status = true;
3966
3967         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3968                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3969                 speed = hw->phy.autoneg_advertised;
3970                 if (!speed)
3971                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3972                 ixgbe_setup_link(hw, speed, true);
3973         }
3974
3975         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3976         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3977                 wait = 0;
3978
3979         if (vf)
3980                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3981         else
3982                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3983
3984         if (diag != 0) {
3985                 link.link_speed = ETH_SPEED_NUM_100M;
3986                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3987                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3988                 if (link.link_status == old.link_status)
3989                         return -1;
3990                 return 0;
3991         }
3992
3993         if (link_up == 0) {
3994                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3995                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3996                 if (link.link_status == old.link_status)
3997                         return -1;
3998                 return 0;
3999         }
4000         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4001         link.link_status = ETH_LINK_UP;
4002         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4003
4004         switch (link_speed) {
4005         default:
4006         case IXGBE_LINK_SPEED_UNKNOWN:
4007                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4008                 link.link_speed = ETH_SPEED_NUM_100M;
4009                 break;
4010
4011         case IXGBE_LINK_SPEED_100_FULL:
4012                 link.link_speed = ETH_SPEED_NUM_100M;
4013                 break;
4014
4015         case IXGBE_LINK_SPEED_1GB_FULL:
4016                 link.link_speed = ETH_SPEED_NUM_1G;
4017                 break;
4018
4019         case IXGBE_LINK_SPEED_2_5GB_FULL:
4020                 link.link_speed = ETH_SPEED_NUM_2_5G;
4021                 break;
4022
4023         case IXGBE_LINK_SPEED_5GB_FULL:
4024                 link.link_speed = ETH_SPEED_NUM_5G;
4025                 break;
4026
4027         case IXGBE_LINK_SPEED_10GB_FULL:
4028                 link.link_speed = ETH_SPEED_NUM_10G;
4029                 break;
4030         }
4031         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4032
4033         if (link.link_status == old.link_status)
4034                 return -1;
4035
4036         return 0;
4037 }
4038
4039 static int
4040 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4041 {
4042         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4043 }
4044
4045 static int
4046 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4047 {
4048         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4049 }
4050
4051 static void
4052 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4053 {
4054         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4055         uint32_t fctrl;
4056
4057         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4058         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4059         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4060 }
4061
4062 static void
4063 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4064 {
4065         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4066         uint32_t fctrl;
4067
4068         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4069         fctrl &= (~IXGBE_FCTRL_UPE);
4070         if (dev->data->all_multicast == 1)
4071                 fctrl |= IXGBE_FCTRL_MPE;
4072         else
4073                 fctrl &= (~IXGBE_FCTRL_MPE);
4074         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4075 }
4076
4077 static void
4078 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4079 {
4080         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4081         uint32_t fctrl;
4082
4083         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4084         fctrl |= IXGBE_FCTRL_MPE;
4085         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4086 }
4087
4088 static void
4089 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4090 {
4091         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4092         uint32_t fctrl;
4093
4094         if (dev->data->promiscuous == 1)
4095                 return; /* must remain in all_multicast mode */
4096
4097         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4098         fctrl &= (~IXGBE_FCTRL_MPE);
4099         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4100 }
4101
4102 /**
4103  * It clears the interrupt causes and enables the interrupt.
4104  * It will be called once only during nic initialized.
4105  *
4106  * @param dev
4107  *  Pointer to struct rte_eth_dev.
4108  * @param on
4109  *  Enable or Disable.
4110  *
4111  * @return
4112  *  - On success, zero.
4113  *  - On failure, a negative value.
4114  */
4115 static int
4116 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4117 {
4118         struct ixgbe_interrupt *intr =
4119                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4120
4121         ixgbe_dev_link_status_print(dev);
4122         if (on)
4123                 intr->mask |= IXGBE_EICR_LSC;
4124         else
4125                 intr->mask &= ~IXGBE_EICR_LSC;
4126
4127         return 0;
4128 }
4129
4130 /**
4131  * It clears the interrupt causes and enables the interrupt.
4132  * It will be called once only during nic initialized.
4133  *
4134  * @param dev
4135  *  Pointer to struct rte_eth_dev.
4136  *
4137  * @return
4138  *  - On success, zero.
4139  *  - On failure, a negative value.
4140  */
4141 static int
4142 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4143 {
4144         struct ixgbe_interrupt *intr =
4145                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4146
4147         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4148
4149         return 0;
4150 }
4151
4152 /**
4153  * It clears the interrupt causes and enables the interrupt.
4154  * It will be called once only during nic initialized.
4155  *
4156  * @param dev
4157  *  Pointer to struct rte_eth_dev.
4158  *
4159  * @return
4160  *  - On success, zero.
4161  *  - On failure, a negative value.
4162  */
4163 static int
4164 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4165 {
4166         struct ixgbe_interrupt *intr =
4167                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4168
4169         intr->mask |= IXGBE_EICR_LINKSEC;
4170
4171         return 0;
4172 }
4173
4174 /*
4175  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4176  *
4177  * @param dev
4178  *  Pointer to struct rte_eth_dev.
4179  *
4180  * @return
4181  *  - On success, zero.
4182  *  - On failure, a negative value.
4183  */
4184 static int
4185 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4186 {
4187         uint32_t eicr;
4188         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4189         struct ixgbe_interrupt *intr =
4190                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4191
4192         /* clear all cause mask */
4193         ixgbe_disable_intr(hw);
4194
4195         /* read-on-clear nic registers here */
4196         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4197         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4198
4199         intr->flags = 0;
4200
4201         /* set flag for async link update */
4202         if (eicr & IXGBE_EICR_LSC)
4203                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4204
4205         if (eicr & IXGBE_EICR_MAILBOX)
4206                 intr->flags |= IXGBE_FLAG_MAILBOX;
4207
4208         if (eicr & IXGBE_EICR_LINKSEC)
4209                 intr->flags |= IXGBE_FLAG_MACSEC;
4210
4211         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4212             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4213             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4214                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4215
4216         return 0;
4217 }
4218
4219 /**
4220  * It gets and then prints the link status.
4221  *
4222  * @param dev
4223  *  Pointer to struct rte_eth_dev.
4224  *
4225  * @return
4226  *  - On success, zero.
4227  *  - On failure, a negative value.
4228  */
4229 static void
4230 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4231 {
4232         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4233         struct rte_eth_link link;
4234
4235         memset(&link, 0, sizeof(link));
4236         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4237         if (link.link_status) {
4238                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4239                                         (int)(dev->data->port_id),
4240                                         (unsigned)link.link_speed,
4241                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4242                                         "full-duplex" : "half-duplex");
4243         } else {
4244                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4245                                 (int)(dev->data->port_id));
4246         }
4247         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4248                                 pci_dev->addr.domain,
4249                                 pci_dev->addr.bus,
4250                                 pci_dev->addr.devid,
4251                                 pci_dev->addr.function);
4252 }
4253
4254 /*
4255  * It executes link_update after knowing an interrupt occurred.
4256  *
4257  * @param dev
4258  *  Pointer to struct rte_eth_dev.
4259  *
4260  * @return
4261  *  - On success, zero.
4262  *  - On failure, a negative value.
4263  */
4264 static int
4265 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4266                            struct rte_intr_handle *intr_handle)
4267 {
4268         struct ixgbe_interrupt *intr =
4269                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4270         int64_t timeout;
4271         struct rte_eth_link link;
4272         struct ixgbe_hw *hw =
4273                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4274
4275         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4276
4277         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4278                 ixgbe_pf_mbx_process(dev);
4279                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4280         }
4281
4282         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4283                 ixgbe_handle_lasi(hw);
4284                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4285         }
4286
4287         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4288                 /* get the link status before link update, for predicting later */
4289                 memset(&link, 0, sizeof(link));
4290                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4291
4292                 ixgbe_dev_link_update(dev, 0);
4293
4294                 /* likely to up */
4295                 if (!link.link_status)
4296                         /* handle it 1 sec later, wait it being stable */
4297                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4298                 /* likely to down */
4299                 else
4300                         /* handle it 4 sec later, wait it being stable */
4301                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4302
4303                 ixgbe_dev_link_status_print(dev);
4304                 if (rte_eal_alarm_set(timeout * 1000,
4305                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4306                         PMD_DRV_LOG(ERR, "Error setting alarm");
4307                 else {
4308                         /* remember original mask */
4309                         intr->mask_original = intr->mask;
4310                         /* only disable lsc interrupt */
4311                         intr->mask &= ~IXGBE_EIMS_LSC;
4312                 }
4313         }
4314
4315         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4316         ixgbe_enable_intr(dev);
4317         rte_intr_enable(intr_handle);
4318
4319         return 0;
4320 }
4321
4322 /**
4323  * Interrupt handler which shall be registered for alarm callback for delayed
4324  * handling specific interrupt to wait for the stable nic state. As the
4325  * NIC interrupt state is not stable for ixgbe after link is just down,
4326  * it needs to wait 4 seconds to get the stable status.
4327  *
4328  * @param handle
4329  *  Pointer to interrupt handle.
4330  * @param param
4331  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4332  *
4333  * @return
4334  *  void
4335  */
4336 static void
4337 ixgbe_dev_interrupt_delayed_handler(void *param)
4338 {
4339         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4340         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4341         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4342         struct ixgbe_interrupt *intr =
4343                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4344         struct ixgbe_hw *hw =
4345                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4346         uint32_t eicr;
4347
4348         ixgbe_disable_intr(hw);
4349
4350         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4351         if (eicr & IXGBE_EICR_MAILBOX)
4352                 ixgbe_pf_mbx_process(dev);
4353
4354         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4355                 ixgbe_handle_lasi(hw);
4356                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4357         }
4358
4359         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4360                 ixgbe_dev_link_update(dev, 0);
4361                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4362                 ixgbe_dev_link_status_print(dev);
4363                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4364                                               NULL, NULL);
4365         }
4366
4367         if (intr->flags & IXGBE_FLAG_MACSEC) {
4368                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4369                                               NULL, NULL);
4370                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4371         }
4372
4373         /* restore original mask */
4374         intr->mask = intr->mask_original;
4375         intr->mask_original = 0;
4376
4377         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4378         ixgbe_enable_intr(dev);
4379         rte_intr_enable(intr_handle);
4380 }
4381
4382 /**
4383  * Interrupt handler triggered by NIC  for handling
4384  * specific interrupt.
4385  *
4386  * @param handle
4387  *  Pointer to interrupt handle.
4388  * @param param
4389  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4390  *
4391  * @return
4392  *  void
4393  */
4394 static void
4395 ixgbe_dev_interrupt_handler(void *param)
4396 {
4397         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4398
4399         ixgbe_dev_interrupt_get_status(dev);
4400         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4401 }
4402
4403 static int
4404 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4405 {
4406         struct ixgbe_hw *hw;
4407
4408         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4409         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4410 }
4411
4412 static int
4413 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4414 {
4415         struct ixgbe_hw *hw;
4416
4417         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4418         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4419 }
4420
4421 static int
4422 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4423 {
4424         struct ixgbe_hw *hw;
4425         uint32_t mflcn_reg;
4426         uint32_t fccfg_reg;
4427         int rx_pause;
4428         int tx_pause;
4429
4430         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4431
4432         fc_conf->pause_time = hw->fc.pause_time;
4433         fc_conf->high_water = hw->fc.high_water[0];
4434         fc_conf->low_water = hw->fc.low_water[0];
4435         fc_conf->send_xon = hw->fc.send_xon;
4436         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4437
4438         /*
4439          * Return rx_pause status according to actual setting of
4440          * MFLCN register.
4441          */
4442         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4443         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4444                 rx_pause = 1;
4445         else
4446                 rx_pause = 0;
4447
4448         /*
4449          * Return tx_pause status according to actual setting of
4450          * FCCFG register.
4451          */
4452         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4453         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4454                 tx_pause = 1;
4455         else
4456                 tx_pause = 0;
4457
4458         if (rx_pause && tx_pause)
4459                 fc_conf->mode = RTE_FC_FULL;
4460         else if (rx_pause)
4461                 fc_conf->mode = RTE_FC_RX_PAUSE;
4462         else if (tx_pause)
4463                 fc_conf->mode = RTE_FC_TX_PAUSE;
4464         else
4465                 fc_conf->mode = RTE_FC_NONE;
4466
4467         return 0;
4468 }
4469
4470 static int
4471 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4472 {
4473         struct ixgbe_hw *hw;
4474         int err;
4475         uint32_t rx_buf_size;
4476         uint32_t max_high_water;
4477         uint32_t mflcn;
4478         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4479                 ixgbe_fc_none,
4480                 ixgbe_fc_rx_pause,
4481                 ixgbe_fc_tx_pause,
4482                 ixgbe_fc_full
4483         };
4484
4485         PMD_INIT_FUNC_TRACE();
4486
4487         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4488         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4489         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4490
4491         /*
4492          * At least reserve one Ethernet frame for watermark
4493          * high_water/low_water in kilo bytes for ixgbe
4494          */
4495         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4496         if ((fc_conf->high_water > max_high_water) ||
4497                 (fc_conf->high_water < fc_conf->low_water)) {
4498                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4499                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4500                 return -EINVAL;
4501         }
4502
4503         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4504         hw->fc.pause_time     = fc_conf->pause_time;
4505         hw->fc.high_water[0]  = fc_conf->high_water;
4506         hw->fc.low_water[0]   = fc_conf->low_water;
4507         hw->fc.send_xon       = fc_conf->send_xon;
4508         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4509
4510         err = ixgbe_fc_enable(hw);
4511
4512         /* Not negotiated is not an error case */
4513         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4514
4515                 /* check if we want to forward MAC frames - driver doesn't have native
4516                  * capability to do that, so we'll write the registers ourselves */
4517
4518                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4519
4520                 /* set or clear MFLCN.PMCF bit depending on configuration */
4521                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4522                         mflcn |= IXGBE_MFLCN_PMCF;
4523                 else
4524                         mflcn &= ~IXGBE_MFLCN_PMCF;
4525
4526                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4527                 IXGBE_WRITE_FLUSH(hw);
4528
4529                 return 0;
4530         }
4531
4532         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4533         return -EIO;
4534 }
4535
4536 /**
4537  *  ixgbe_pfc_enable_generic - Enable flow control
4538  *  @hw: pointer to hardware structure
4539  *  @tc_num: traffic class number
4540  *  Enable flow control according to the current settings.
4541  */
4542 static int
4543 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4544 {
4545         int ret_val = 0;
4546         uint32_t mflcn_reg, fccfg_reg;
4547         uint32_t reg;
4548         uint32_t fcrtl, fcrth;
4549         uint8_t i;
4550         uint8_t nb_rx_en;
4551
4552         /* Validate the water mark configuration */
4553         if (!hw->fc.pause_time) {
4554                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4555                 goto out;
4556         }
4557
4558         /* Low water mark of zero causes XOFF floods */
4559         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4560                  /* High/Low water can not be 0 */
4561                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4562                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4563                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4564                         goto out;
4565                 }
4566
4567                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4568                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4569                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4570                         goto out;
4571                 }
4572         }
4573         /* Negotiate the fc mode to use */
4574         ixgbe_fc_autoneg(hw);
4575
4576         /* Disable any previous flow control settings */
4577         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4578         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4579
4580         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4581         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4582
4583         switch (hw->fc.current_mode) {
4584         case ixgbe_fc_none:
4585                 /*
4586                  * If the count of enabled RX Priority Flow control >1,
4587                  * and the TX pause can not be disabled
4588                  */
4589                 nb_rx_en = 0;
4590                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4591                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4592                         if (reg & IXGBE_FCRTH_FCEN)
4593                                 nb_rx_en++;
4594                 }
4595                 if (nb_rx_en > 1)
4596                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4597                 break;
4598         case ixgbe_fc_rx_pause:
4599                 /*
4600                  * Rx Flow control is enabled and Tx Flow control is
4601                  * disabled by software override. Since there really
4602                  * isn't a way to advertise that we are capable of RX
4603                  * Pause ONLY, we will advertise that we support both
4604                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4605                  * disable the adapter's ability to send PAUSE frames.
4606                  */
4607                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4608                 /*
4609                  * If the count of enabled RX Priority Flow control >1,
4610                  * and the TX pause can not be disabled
4611                  */
4612                 nb_rx_en = 0;
4613                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4614                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4615                         if (reg & IXGBE_FCRTH_FCEN)
4616                                 nb_rx_en++;
4617                 }
4618                 if (nb_rx_en > 1)
4619                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4620                 break;
4621         case ixgbe_fc_tx_pause:
4622                 /*
4623                  * Tx Flow control is enabled, and Rx Flow control is
4624                  * disabled by software override.
4625                  */
4626                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4627                 break;
4628         case ixgbe_fc_full:
4629                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4630                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4631                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4632                 break;
4633         default:
4634                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4635                 ret_val = IXGBE_ERR_CONFIG;
4636                 goto out;
4637         }
4638
4639         /* Set 802.3x based flow control settings. */
4640         mflcn_reg |= IXGBE_MFLCN_DPF;
4641         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4642         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4643
4644         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4645         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4646                 hw->fc.high_water[tc_num]) {
4647                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4648                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4649                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4650         } else {
4651                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4652                 /*
4653                  * In order to prevent Tx hangs when the internal Tx
4654                  * switch is enabled we must set the high water mark
4655                  * to the maximum FCRTH value.  This allows the Tx
4656                  * switch to function even under heavy Rx workloads.
4657                  */
4658                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4659         }
4660         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4661
4662         /* Configure pause time (2 TCs per register) */
4663         reg = hw->fc.pause_time * 0x00010001;
4664         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4665                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4666
4667         /* Configure flow control refresh threshold value */
4668         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4669
4670 out:
4671         return ret_val;
4672 }
4673
4674 static int
4675 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4676 {
4677         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4678         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4679
4680         if (hw->mac.type != ixgbe_mac_82598EB) {
4681                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4682         }
4683         return ret_val;
4684 }
4685
4686 static int
4687 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4688 {
4689         int err;
4690         uint32_t rx_buf_size;
4691         uint32_t max_high_water;
4692         uint8_t tc_num;
4693         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4694         struct ixgbe_hw *hw =
4695                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4696         struct ixgbe_dcb_config *dcb_config =
4697                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4698
4699         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4700                 ixgbe_fc_none,
4701                 ixgbe_fc_rx_pause,
4702                 ixgbe_fc_tx_pause,
4703                 ixgbe_fc_full
4704         };
4705
4706         PMD_INIT_FUNC_TRACE();
4707
4708         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4709         tc_num = map[pfc_conf->priority];
4710         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4711         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4712         /*
4713          * At least reserve one Ethernet frame for watermark
4714          * high_water/low_water in kilo bytes for ixgbe
4715          */
4716         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4717         if ((pfc_conf->fc.high_water > max_high_water) ||
4718             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4719                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4720                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4721                 return -EINVAL;
4722         }
4723
4724         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4725         hw->fc.pause_time = pfc_conf->fc.pause_time;
4726         hw->fc.send_xon = pfc_conf->fc.send_xon;
4727         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4728         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4729
4730         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4731
4732         /* Not negotiated is not an error case */
4733         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4734                 return 0;
4735
4736         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4737         return -EIO;
4738 }
4739
4740 static int
4741 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4742                           struct rte_eth_rss_reta_entry64 *reta_conf,
4743                           uint16_t reta_size)
4744 {
4745         uint16_t i, sp_reta_size;
4746         uint8_t j, mask;
4747         uint32_t reta, r;
4748         uint16_t idx, shift;
4749         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4750         uint32_t reta_reg;
4751
4752         PMD_INIT_FUNC_TRACE();
4753
4754         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4755                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4756                         "NIC.");
4757                 return -ENOTSUP;
4758         }
4759
4760         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4761         if (reta_size != sp_reta_size) {
4762                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4763                         "(%d) doesn't match the number hardware can supported "
4764                         "(%d)", reta_size, sp_reta_size);
4765                 return -EINVAL;
4766         }
4767
4768         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4769                 idx = i / RTE_RETA_GROUP_SIZE;
4770                 shift = i % RTE_RETA_GROUP_SIZE;
4771                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4772                                                 IXGBE_4_BIT_MASK);
4773                 if (!mask)
4774                         continue;
4775                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4776                 if (mask == IXGBE_4_BIT_MASK)
4777                         r = 0;
4778                 else
4779                         r = IXGBE_READ_REG(hw, reta_reg);
4780                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4781                         if (mask & (0x1 << j))
4782                                 reta |= reta_conf[idx].reta[shift + j] <<
4783                                                         (CHAR_BIT * j);
4784                         else
4785                                 reta |= r & (IXGBE_8_BIT_MASK <<
4786                                                 (CHAR_BIT * j));
4787                 }
4788                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4789         }
4790
4791         return 0;
4792 }
4793
4794 static int
4795 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4796                          struct rte_eth_rss_reta_entry64 *reta_conf,
4797                          uint16_t reta_size)
4798 {
4799         uint16_t i, sp_reta_size;
4800         uint8_t j, mask;
4801         uint32_t reta;
4802         uint16_t idx, shift;
4803         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4804         uint32_t reta_reg;
4805
4806         PMD_INIT_FUNC_TRACE();
4807         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4808         if (reta_size != sp_reta_size) {
4809                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4810                         "(%d) doesn't match the number hardware can supported "
4811                         "(%d)", reta_size, sp_reta_size);
4812                 return -EINVAL;
4813         }
4814
4815         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4816                 idx = i / RTE_RETA_GROUP_SIZE;
4817                 shift = i % RTE_RETA_GROUP_SIZE;
4818                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4819                                                 IXGBE_4_BIT_MASK);
4820                 if (!mask)
4821                         continue;
4822
4823                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4824                 reta = IXGBE_READ_REG(hw, reta_reg);
4825                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4826                         if (mask & (0x1 << j))
4827                                 reta_conf[idx].reta[shift + j] =
4828                                         ((reta >> (CHAR_BIT * j)) &
4829                                                 IXGBE_8_BIT_MASK);
4830                 }
4831         }
4832
4833         return 0;
4834 }
4835
4836 static int
4837 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4838                                 uint32_t index, uint32_t pool)
4839 {
4840         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4841         uint32_t enable_addr = 1;
4842
4843         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4844                              pool, enable_addr);
4845 }
4846
4847 static void
4848 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4849 {
4850         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4851
4852         ixgbe_clear_rar(hw, index);
4853 }
4854
4855 static void
4856 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4857 {
4858         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4859
4860         ixgbe_remove_rar(dev, 0);
4861
4862         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4863 }
4864
4865 static bool
4866 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4867 {
4868         if (strcmp(dev->device->driver->name, drv->driver.name))
4869                 return false;
4870
4871         return true;
4872 }
4873
4874 bool
4875 is_ixgbe_supported(struct rte_eth_dev *dev)
4876 {
4877         return is_device_supported(dev, &rte_ixgbe_pmd);
4878 }
4879
4880 static int
4881 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4882 {
4883         uint32_t hlreg0;
4884         uint32_t maxfrs;
4885         struct ixgbe_hw *hw;
4886         struct rte_eth_dev_info dev_info;
4887         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4888         struct rte_eth_dev_data *dev_data = dev->data;
4889
4890         ixgbe_dev_info_get(dev, &dev_info);
4891
4892         /* check that mtu is within the allowed range */
4893         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4894                 return -EINVAL;
4895
4896         /* If device is started, refuse mtu that requires the support of
4897          * scattered packets when this feature has not been enabled before.
4898          */
4899         if (dev_data->dev_started && !dev_data->scattered_rx &&
4900             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4901              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4902                 PMD_INIT_LOG(ERR, "Stop port first.");
4903                 return -EINVAL;
4904         }
4905
4906         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4907         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4908
4909         /* switch to jumbo mode if needed */
4910         if (frame_size > ETHER_MAX_LEN) {
4911                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4912                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4913         } else {
4914                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4915                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4916         }
4917         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4918
4919         /* update max frame size */
4920         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4921
4922         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4923         maxfrs &= 0x0000FFFF;
4924         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4925         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4926
4927         return 0;
4928 }
4929
4930 /*
4931  * Virtual Function operations
4932  */
4933 static void
4934 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4935 {
4936         PMD_INIT_FUNC_TRACE();
4937
4938         /* Clear interrupt mask to stop from interrupts being generated */
4939         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4940
4941         IXGBE_WRITE_FLUSH(hw);
4942 }
4943
4944 static void
4945 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4946 {
4947         PMD_INIT_FUNC_TRACE();
4948
4949         /* VF enable interrupt autoclean */
4950         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4951         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4952         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4953
4954         IXGBE_WRITE_FLUSH(hw);
4955 }
4956
4957 static int
4958 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4959 {
4960         struct rte_eth_conf *conf = &dev->data->dev_conf;
4961         struct ixgbe_adapter *adapter =
4962                         (struct ixgbe_adapter *)dev->data->dev_private;
4963
4964         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4965                      dev->data->port_id);
4966
4967         /*
4968          * VF has no ability to enable/disable HW CRC
4969          * Keep the persistent behavior the same as Host PF
4970          */
4971 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4972         if (!conf->rxmode.hw_strip_crc) {
4973                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4974                 conf->rxmode.hw_strip_crc = 1;
4975         }
4976 #else
4977         if (conf->rxmode.hw_strip_crc) {
4978                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4979                 conf->rxmode.hw_strip_crc = 0;
4980         }
4981 #endif
4982
4983         /*
4984          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4985          * allocation or vector Rx preconditions we will reset it.
4986          */
4987         adapter->rx_bulk_alloc_allowed = true;
4988         adapter->rx_vec_allowed = true;
4989
4990         return 0;
4991 }
4992
4993 static int
4994 ixgbevf_dev_start(struct rte_eth_dev *dev)
4995 {
4996         struct ixgbe_hw *hw =
4997                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4998         uint32_t intr_vector = 0;
4999         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5000         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5001
5002         int err, mask = 0;
5003
5004         PMD_INIT_FUNC_TRACE();
5005
5006         hw->mac.ops.reset_hw(hw);
5007         hw->mac.get_link_status = true;
5008
5009         /* negotiate mailbox API version to use with the PF. */
5010         ixgbevf_negotiate_api(hw);
5011
5012         ixgbevf_dev_tx_init(dev);
5013
5014         /* This can fail when allocating mbufs for descriptor rings */
5015         err = ixgbevf_dev_rx_init(dev);
5016         if (err) {
5017                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5018                 ixgbe_dev_clear_queues(dev);
5019                 return err;
5020         }
5021
5022         /* Set vfta */
5023         ixgbevf_set_vfta_all(dev, 1);
5024
5025         /* Set HW strip */
5026         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5027                 ETH_VLAN_EXTEND_MASK;
5028         err = ixgbevf_vlan_offload_set(dev, mask);
5029         if (err) {
5030                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5031                 ixgbe_dev_clear_queues(dev);
5032                 return err;
5033         }
5034
5035         ixgbevf_dev_rxtx_start(dev);
5036
5037         /* check and configure queue intr-vector mapping */
5038         if (dev->data->dev_conf.intr_conf.rxq != 0) {
5039                 /* According to datasheet, only vector 0/1/2 can be used,
5040                  * now only one vector is used for Rx queue
5041                  */
5042                 intr_vector = 1;
5043                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5044                         return -1;
5045         }
5046
5047         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5048                 intr_handle->intr_vec =
5049                         rte_zmalloc("intr_vec",
5050                                     dev->data->nb_rx_queues * sizeof(int), 0);
5051                 if (intr_handle->intr_vec == NULL) {
5052                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5053                                      " intr_vec", dev->data->nb_rx_queues);
5054                         return -ENOMEM;
5055                 }
5056         }
5057         ixgbevf_configure_msix(dev);
5058
5059         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5060          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5061          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5062          * is not cleared, it will fail when following rte_intr_enable( ) tries
5063          * to map Rx queue interrupt to other VFIO vectors.
5064          * So clear uio/vfio intr/evevnfd first to avoid failure.
5065          */
5066         rte_intr_disable(intr_handle);
5067
5068         rte_intr_enable(intr_handle);
5069
5070         /* Re-enable interrupt for VF */
5071         ixgbevf_intr_enable(hw);
5072
5073         return 0;
5074 }
5075
5076 static void
5077 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5078 {
5079         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5080         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5081         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5082
5083         PMD_INIT_FUNC_TRACE();
5084
5085         ixgbevf_intr_disable(hw);
5086
5087         hw->adapter_stopped = 1;
5088         ixgbe_stop_adapter(hw);
5089
5090         /*
5091           * Clear what we set, but we still keep shadow_vfta to
5092           * restore after device starts
5093           */
5094         ixgbevf_set_vfta_all(dev, 0);
5095
5096         /* Clear stored conf */
5097         dev->data->scattered_rx = 0;
5098
5099         ixgbe_dev_clear_queues(dev);
5100
5101         /* Clean datapath event and queue/vec mapping */
5102         rte_intr_efd_disable(intr_handle);
5103         if (intr_handle->intr_vec != NULL) {
5104                 rte_free(intr_handle->intr_vec);
5105                 intr_handle->intr_vec = NULL;
5106         }
5107 }
5108
5109 static void
5110 ixgbevf_dev_close(struct rte_eth_dev *dev)
5111 {
5112         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5113
5114         PMD_INIT_FUNC_TRACE();
5115
5116         ixgbe_reset_hw(hw);
5117
5118         ixgbevf_dev_stop(dev);
5119
5120         ixgbe_dev_free_queues(dev);
5121
5122         /**
5123          * Remove the VF MAC address ro ensure
5124          * that the VF traffic goes to the PF
5125          * after stop, close and detach of the VF
5126          **/
5127         ixgbevf_remove_mac_addr(dev, 0);
5128 }
5129
5130 /*
5131  * Reset VF device
5132  */
5133 static int
5134 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5135 {
5136         int ret;
5137
5138         ret = eth_ixgbevf_dev_uninit(dev);
5139         if (ret)
5140                 return ret;
5141
5142         ret = eth_ixgbevf_dev_init(dev);
5143
5144         return ret;
5145 }
5146
5147 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5148 {
5149         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5150         struct ixgbe_vfta *shadow_vfta =
5151                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5152         int i = 0, j = 0, vfta = 0, mask = 1;
5153
5154         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5155                 vfta = shadow_vfta->vfta[i];
5156                 if (vfta) {
5157                         mask = 1;
5158                         for (j = 0; j < 32; j++) {
5159                                 if (vfta & mask)
5160                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5161                                                        on, false);
5162                                 mask <<= 1;
5163                         }
5164                 }
5165         }
5166
5167 }
5168
5169 static int
5170 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5171 {
5172         struct ixgbe_hw *hw =
5173                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5174         struct ixgbe_vfta *shadow_vfta =
5175                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5176         uint32_t vid_idx = 0;
5177         uint32_t vid_bit = 0;
5178         int ret = 0;
5179
5180         PMD_INIT_FUNC_TRACE();
5181
5182         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5183         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5184         if (ret) {
5185                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5186                 return ret;
5187         }
5188         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5189         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5190
5191         /* Save what we set and retore it after device reset */
5192         if (on)
5193                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5194         else
5195                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5196
5197         return 0;
5198 }
5199
5200 static void
5201 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5202 {
5203         struct ixgbe_hw *hw =
5204                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5205         uint32_t ctrl;
5206
5207         PMD_INIT_FUNC_TRACE();
5208
5209         if (queue >= hw->mac.max_rx_queues)
5210                 return;
5211
5212         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5213         if (on)
5214                 ctrl |= IXGBE_RXDCTL_VME;
5215         else
5216                 ctrl &= ~IXGBE_RXDCTL_VME;
5217         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5218
5219         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5220 }
5221
5222 static int
5223 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5224 {
5225         struct ixgbe_hw *hw =
5226                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5227         uint16_t i;
5228         int on = 0;
5229
5230         /* VF function only support hw strip feature, others are not support */
5231         if (mask & ETH_VLAN_STRIP_MASK) {
5232                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5233
5234                 for (i = 0; i < hw->mac.max_rx_queues; i++)
5235                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5236         }
5237
5238         return 0;
5239 }
5240
5241 int
5242 ixgbe_vt_check(struct ixgbe_hw *hw)
5243 {
5244         uint32_t reg_val;
5245
5246         /* if Virtualization Technology is enabled */
5247         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5248         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5249                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5250                 return -1;
5251         }
5252
5253         return 0;
5254 }
5255
5256 static uint32_t
5257 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5258 {
5259         uint32_t vector = 0;
5260
5261         switch (hw->mac.mc_filter_type) {
5262         case 0:   /* use bits [47:36] of the address */
5263                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5264                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5265                 break;
5266         case 1:   /* use bits [46:35] of the address */
5267                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5268                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5269                 break;
5270         case 2:   /* use bits [45:34] of the address */
5271                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5272                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5273                 break;
5274         case 3:   /* use bits [43:32] of the address */
5275                 vector = ((uc_addr->addr_bytes[4]) |
5276                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5277                 break;
5278         default:  /* Invalid mc_filter_type */
5279                 break;
5280         }
5281
5282         /* vector can only be 12-bits or boundary will be exceeded */
5283         vector &= 0xFFF;
5284         return vector;
5285 }
5286
5287 static int
5288 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5289                         uint8_t on)
5290 {
5291         uint32_t vector;
5292         uint32_t uta_idx;
5293         uint32_t reg_val;
5294         uint32_t uta_shift;
5295         uint32_t rc;
5296         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5297         const uint32_t ixgbe_uta_bit_shift = 5;
5298         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5299         const uint32_t bit1 = 0x1;
5300
5301         struct ixgbe_hw *hw =
5302                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5303         struct ixgbe_uta_info *uta_info =
5304                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5305
5306         /* The UTA table only exists on 82599 hardware and newer */
5307         if (hw->mac.type < ixgbe_mac_82599EB)
5308                 return -ENOTSUP;
5309
5310         vector = ixgbe_uta_vector(hw, mac_addr);
5311         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5312         uta_shift = vector & ixgbe_uta_bit_mask;
5313
5314         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5315         if (rc == on)
5316                 return 0;
5317
5318         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5319         if (on) {
5320                 uta_info->uta_in_use++;
5321                 reg_val |= (bit1 << uta_shift);
5322                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5323         } else {
5324                 uta_info->uta_in_use--;
5325                 reg_val &= ~(bit1 << uta_shift);
5326                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5327         }
5328
5329         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5330
5331         if (uta_info->uta_in_use > 0)
5332                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5333                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5334         else
5335                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5336
5337         return 0;
5338 }
5339
5340 static int
5341 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5342 {
5343         int i;
5344         struct ixgbe_hw *hw =
5345                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5346         struct ixgbe_uta_info *uta_info =
5347                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5348
5349         /* The UTA table only exists on 82599 hardware and newer */
5350         if (hw->mac.type < ixgbe_mac_82599EB)
5351                 return -ENOTSUP;
5352
5353         if (on) {
5354                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5355                         uta_info->uta_shadow[i] = ~0;
5356                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5357                 }
5358         } else {
5359                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5360                         uta_info->uta_shadow[i] = 0;
5361                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5362                 }
5363         }
5364         return 0;
5365
5366 }
5367
5368 uint32_t
5369 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5370 {
5371         uint32_t new_val = orig_val;
5372
5373         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5374                 new_val |= IXGBE_VMOLR_AUPE;
5375         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5376                 new_val |= IXGBE_VMOLR_ROMPE;
5377         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5378                 new_val |= IXGBE_VMOLR_ROPE;
5379         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5380                 new_val |= IXGBE_VMOLR_BAM;
5381         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5382                 new_val |= IXGBE_VMOLR_MPE;
5383
5384         return new_val;
5385 }
5386
5387 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5388 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5389 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5390 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5391 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5392         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5393         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5394
5395 static int
5396 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5397                       struct rte_eth_mirror_conf *mirror_conf,
5398                       uint8_t rule_id, uint8_t on)
5399 {
5400         uint32_t mr_ctl, vlvf;
5401         uint32_t mp_lsb = 0;
5402         uint32_t mv_msb = 0;
5403         uint32_t mv_lsb = 0;
5404         uint32_t mp_msb = 0;
5405         uint8_t i = 0;
5406         int reg_index = 0;
5407         uint64_t vlan_mask = 0;
5408
5409         const uint8_t pool_mask_offset = 32;
5410         const uint8_t vlan_mask_offset = 32;
5411         const uint8_t dst_pool_offset = 8;
5412         const uint8_t rule_mr_offset  = 4;
5413         const uint8_t mirror_rule_mask = 0x0F;
5414
5415         struct ixgbe_mirror_info *mr_info =
5416                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5417         struct ixgbe_hw *hw =
5418                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5419         uint8_t mirror_type = 0;
5420
5421         if (ixgbe_vt_check(hw) < 0)
5422                 return -ENOTSUP;
5423
5424         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5425                 return -EINVAL;
5426
5427         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5428                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5429                             mirror_conf->rule_type);
5430                 return -EINVAL;
5431         }
5432
5433         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5434                 mirror_type |= IXGBE_MRCTL_VLME;
5435                 /* Check if vlan id is valid and find conresponding VLAN ID
5436                  * index in VLVF
5437                  */
5438                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5439                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5440                                 /* search vlan id related pool vlan filter
5441                                  * index
5442                                  */
5443                                 reg_index = ixgbe_find_vlvf_slot(
5444                                                 hw,
5445                                                 mirror_conf->vlan.vlan_id[i],
5446                                                 false);
5447                                 if (reg_index < 0)
5448                                         return -EINVAL;
5449                                 vlvf = IXGBE_READ_REG(hw,
5450                                                       IXGBE_VLVF(reg_index));
5451                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5452                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5453                                       mirror_conf->vlan.vlan_id[i]))
5454                                         vlan_mask |= (1ULL << reg_index);
5455                                 else
5456                                         return -EINVAL;
5457                         }
5458                 }
5459
5460                 if (on) {
5461                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5462                         mv_msb = vlan_mask >> vlan_mask_offset;
5463
5464                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5465                                                 mirror_conf->vlan.vlan_mask;
5466                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5467                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5468                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5469                                                 mirror_conf->vlan.vlan_id[i];
5470                         }
5471                 } else {
5472                         mv_lsb = 0;
5473                         mv_msb = 0;
5474                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5475                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5476                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5477                 }
5478         }
5479
5480         /**
5481          * if enable pool mirror, write related pool mask register,if disable
5482          * pool mirror, clear PFMRVM register
5483          */
5484         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5485                 mirror_type |= IXGBE_MRCTL_VPME;
5486                 if (on) {
5487                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5488                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5489                         mr_info->mr_conf[rule_id].pool_mask =
5490                                         mirror_conf->pool_mask;
5491
5492                 } else {
5493                         mp_lsb = 0;
5494                         mp_msb = 0;
5495                         mr_info->mr_conf[rule_id].pool_mask = 0;
5496                 }
5497         }
5498         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5499                 mirror_type |= IXGBE_MRCTL_UPME;
5500         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5501                 mirror_type |= IXGBE_MRCTL_DPME;
5502
5503         /* read  mirror control register and recalculate it */
5504         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5505
5506         if (on) {
5507                 mr_ctl |= mirror_type;
5508                 mr_ctl &= mirror_rule_mask;
5509                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5510         } else {
5511                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5512         }
5513
5514         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5515         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5516
5517         /* write mirrror control  register */
5518         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5519
5520         /* write pool mirrror control  register */
5521         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5522                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5523                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5524                                 mp_msb);
5525         }
5526         /* write VLAN mirrror control  register */
5527         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5528                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5529                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5530                                 mv_msb);
5531         }
5532
5533         return 0;
5534 }
5535
5536 static int
5537 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5538 {
5539         int mr_ctl = 0;
5540         uint32_t lsb_val = 0;
5541         uint32_t msb_val = 0;
5542         const uint8_t rule_mr_offset = 4;
5543
5544         struct ixgbe_hw *hw =
5545                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5546         struct ixgbe_mirror_info *mr_info =
5547                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5548
5549         if (ixgbe_vt_check(hw) < 0)
5550                 return -ENOTSUP;
5551
5552         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5553                 return -EINVAL;
5554
5555         memset(&mr_info->mr_conf[rule_id], 0,
5556                sizeof(struct rte_eth_mirror_conf));
5557
5558         /* clear PFVMCTL register */
5559         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5560
5561         /* clear pool mask register */
5562         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5563         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5564
5565         /* clear vlan mask register */
5566         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5567         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5568
5569         return 0;
5570 }
5571
5572 static int
5573 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5574 {
5575         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5576         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5577         uint32_t mask;
5578         struct ixgbe_hw *hw =
5579                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5580         uint32_t vec = IXGBE_MISC_VEC_ID;
5581
5582         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5583         if (rte_intr_allow_others(intr_handle))
5584                 vec = IXGBE_RX_VEC_START;
5585         mask |= (1 << vec);
5586         RTE_SET_USED(queue_id);
5587         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5588
5589         rte_intr_enable(intr_handle);
5590
5591         return 0;
5592 }
5593
5594 static int
5595 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5596 {
5597         uint32_t mask;
5598         struct ixgbe_hw *hw =
5599                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5600         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5601         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5602         uint32_t vec = IXGBE_MISC_VEC_ID;
5603
5604         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5605         if (rte_intr_allow_others(intr_handle))
5606                 vec = IXGBE_RX_VEC_START;
5607         mask &= ~(1 << vec);
5608         RTE_SET_USED(queue_id);
5609         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5610
5611         return 0;
5612 }
5613
5614 static int
5615 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5616 {
5617         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5618         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5619         uint32_t mask;
5620         struct ixgbe_hw *hw =
5621                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5622         struct ixgbe_interrupt *intr =
5623                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5624
5625         if (queue_id < 16) {
5626                 ixgbe_disable_intr(hw);
5627                 intr->mask |= (1 << queue_id);
5628                 ixgbe_enable_intr(dev);
5629         } else if (queue_id < 32) {
5630                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5631                 mask &= (1 << queue_id);
5632                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5633         } else if (queue_id < 64) {
5634                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5635                 mask &= (1 << (queue_id - 32));
5636                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5637         }
5638         rte_intr_enable(intr_handle);
5639
5640         return 0;
5641 }
5642
5643 static int
5644 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5645 {
5646         uint32_t mask;
5647         struct ixgbe_hw *hw =
5648                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5649         struct ixgbe_interrupt *intr =
5650                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5651
5652         if (queue_id < 16) {
5653                 ixgbe_disable_intr(hw);
5654                 intr->mask &= ~(1 << queue_id);
5655                 ixgbe_enable_intr(dev);
5656         } else if (queue_id < 32) {
5657                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5658                 mask &= ~(1 << queue_id);
5659                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5660         } else if (queue_id < 64) {
5661                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5662                 mask &= ~(1 << (queue_id - 32));
5663                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5664         }
5665
5666         return 0;
5667 }
5668
5669 static void
5670 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5671                      uint8_t queue, uint8_t msix_vector)
5672 {
5673         uint32_t tmp, idx;
5674
5675         if (direction == -1) {
5676                 /* other causes */
5677                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5678                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5679                 tmp &= ~0xFF;
5680                 tmp |= msix_vector;
5681                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5682         } else {
5683                 /* rx or tx cause */
5684                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5685                 idx = ((16 * (queue & 1)) + (8 * direction));
5686                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5687                 tmp &= ~(0xFF << idx);
5688                 tmp |= (msix_vector << idx);
5689                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5690         }
5691 }
5692
5693 /**
5694  * set the IVAR registers, mapping interrupt causes to vectors
5695  * @param hw
5696  *  pointer to ixgbe_hw struct
5697  * @direction
5698  *  0 for Rx, 1 for Tx, -1 for other causes
5699  * @queue
5700  *  queue to map the corresponding interrupt to
5701  * @msix_vector
5702  *  the vector to map to the corresponding queue
5703  */
5704 static void
5705 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5706                    uint8_t queue, uint8_t msix_vector)
5707 {
5708         uint32_t tmp, idx;
5709
5710         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5711         if (hw->mac.type == ixgbe_mac_82598EB) {
5712                 if (direction == -1)
5713                         direction = 0;
5714                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5715                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5716                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5717                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5718                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5719         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5720                         (hw->mac.type == ixgbe_mac_X540) ||
5721                         (hw->mac.type == ixgbe_mac_X550)) {
5722                 if (direction == -1) {
5723                         /* other causes */
5724                         idx = ((queue & 1) * 8);
5725                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5726                         tmp &= ~(0xFF << idx);
5727                         tmp |= (msix_vector << idx);
5728                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5729                 } else {
5730                         /* rx or tx causes */
5731                         idx = ((16 * (queue & 1)) + (8 * direction));
5732                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5733                         tmp &= ~(0xFF << idx);
5734                         tmp |= (msix_vector << idx);
5735                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5736                 }
5737         }
5738 }
5739
5740 static void
5741 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5742 {
5743         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5744         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5745         struct ixgbe_hw *hw =
5746                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5747         uint32_t q_idx;
5748         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5749         uint32_t base = IXGBE_MISC_VEC_ID;
5750
5751         /* Configure VF other cause ivar */
5752         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5753
5754         /* won't configure msix register if no mapping is done
5755          * between intr vector and event fd.
5756          */
5757         if (!rte_intr_dp_is_en(intr_handle))
5758                 return;
5759
5760         if (rte_intr_allow_others(intr_handle)) {
5761                 base = IXGBE_RX_VEC_START;
5762                 vector_idx = IXGBE_RX_VEC_START;
5763         }
5764
5765         /* Configure all RX queues of VF */
5766         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5767                 /* Force all queue use vector 0,
5768                  * as IXGBE_VF_MAXMSIVECOTR = 1
5769                  */
5770                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5771                 intr_handle->intr_vec[q_idx] = vector_idx;
5772                 if (vector_idx < base + intr_handle->nb_efd - 1)
5773                         vector_idx++;
5774         }
5775 }
5776
5777 /**
5778  * Sets up the hardware to properly generate MSI-X interrupts
5779  * @hw
5780  *  board private structure
5781  */
5782 static void
5783 ixgbe_configure_msix(struct rte_eth_dev *dev)
5784 {
5785         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5786         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5787         struct ixgbe_hw *hw =
5788                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5789         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5790         uint32_t vec = IXGBE_MISC_VEC_ID;
5791         uint32_t mask;
5792         uint32_t gpie;
5793
5794         /* won't configure msix register if no mapping is done
5795          * between intr vector and event fd
5796          */
5797         if (!rte_intr_dp_is_en(intr_handle))
5798                 return;
5799
5800         if (rte_intr_allow_others(intr_handle))
5801                 vec = base = IXGBE_RX_VEC_START;
5802
5803         /* setup GPIE for MSI-x mode */
5804         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5805         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5806                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5807         /* auto clearing and auto setting corresponding bits in EIMS
5808          * when MSI-X interrupt is triggered
5809          */
5810         if (hw->mac.type == ixgbe_mac_82598EB) {
5811                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5812         } else {
5813                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5814                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5815         }
5816         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5817
5818         /* Populate the IVAR table and set the ITR values to the
5819          * corresponding register.
5820          */
5821         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5822              queue_id++) {
5823                 /* by default, 1:1 mapping */
5824                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5825                 intr_handle->intr_vec[queue_id] = vec;
5826                 if (vec < base + intr_handle->nb_efd - 1)
5827                         vec++;
5828         }
5829
5830         switch (hw->mac.type) {
5831         case ixgbe_mac_82598EB:
5832                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5833                                    IXGBE_MISC_VEC_ID);
5834                 break;
5835         case ixgbe_mac_82599EB:
5836         case ixgbe_mac_X540:
5837         case ixgbe_mac_X550:
5838                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5839                 break;
5840         default:
5841                 break;
5842         }
5843         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5844                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5845
5846         /* set up to autoclear timer, and the vectors */
5847         mask = IXGBE_EIMS_ENABLE_MASK;
5848         mask &= ~(IXGBE_EIMS_OTHER |
5849                   IXGBE_EIMS_MAILBOX |
5850                   IXGBE_EIMS_LSC);
5851
5852         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5853 }
5854
5855 int
5856 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5857                            uint16_t queue_idx, uint16_t tx_rate)
5858 {
5859         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5860         uint32_t rf_dec, rf_int;
5861         uint32_t bcnrc_val;
5862         uint16_t link_speed = dev->data->dev_link.link_speed;
5863
5864         if (queue_idx >= hw->mac.max_tx_queues)
5865                 return -EINVAL;
5866
5867         if (tx_rate != 0) {
5868                 /* Calculate the rate factor values to set */
5869                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5870                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5871                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5872
5873                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5874                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5875                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5876                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5877         } else {
5878                 bcnrc_val = 0;
5879         }
5880
5881         /*
5882          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5883          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5884          * set as 0x4.
5885          */
5886         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5887                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5888                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5889                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5890                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5891         else
5892                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5893                         IXGBE_MMW_SIZE_DEFAULT);
5894
5895         /* Set RTTBCNRC of queue X */
5896         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5897         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5898         IXGBE_WRITE_FLUSH(hw);
5899
5900         return 0;
5901 }
5902
5903 static int
5904 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5905                      __attribute__((unused)) uint32_t index,
5906                      __attribute__((unused)) uint32_t pool)
5907 {
5908         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5909         int diag;
5910
5911         /*
5912          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5913          * operation. Trap this case to avoid exhausting the [very limited]
5914          * set of PF resources used to store VF MAC addresses.
5915          */
5916         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5917                 return -1;
5918         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5919         if (diag != 0)
5920                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5921                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5922                             mac_addr->addr_bytes[0],
5923                             mac_addr->addr_bytes[1],
5924                             mac_addr->addr_bytes[2],
5925                             mac_addr->addr_bytes[3],
5926                             mac_addr->addr_bytes[4],
5927                             mac_addr->addr_bytes[5],
5928                             diag);
5929         return diag;
5930 }
5931
5932 static void
5933 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5934 {
5935         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5936         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5937         struct ether_addr *mac_addr;
5938         uint32_t i;
5939         int diag;
5940
5941         /*
5942          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5943          * not support the deletion of a given MAC address.
5944          * Instead, it imposes to delete all MAC addresses, then to add again
5945          * all MAC addresses with the exception of the one to be deleted.
5946          */
5947         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5948
5949         /*
5950          * Add again all MAC addresses, with the exception of the deleted one
5951          * and of the permanent MAC address.
5952          */
5953         for (i = 0, mac_addr = dev->data->mac_addrs;
5954              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5955                 /* Skip the deleted MAC address */
5956                 if (i == index)
5957                         continue;
5958                 /* Skip NULL MAC addresses */
5959                 if (is_zero_ether_addr(mac_addr))
5960                         continue;
5961                 /* Skip the permanent MAC address */
5962                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5963                         continue;
5964                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5965                 if (diag != 0)
5966                         PMD_DRV_LOG(ERR,
5967                                     "Adding again MAC address "
5968                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5969                                     "diag=%d",
5970                                     mac_addr->addr_bytes[0],
5971                                     mac_addr->addr_bytes[1],
5972                                     mac_addr->addr_bytes[2],
5973                                     mac_addr->addr_bytes[3],
5974                                     mac_addr->addr_bytes[4],
5975                                     mac_addr->addr_bytes[5],
5976                                     diag);
5977         }
5978 }
5979
5980 static void
5981 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5982 {
5983         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5984
5985         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5986 }
5987
5988 int
5989 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5990                         struct rte_eth_syn_filter *filter,
5991                         bool add)
5992 {
5993         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5994         struct ixgbe_filter_info *filter_info =
5995                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5996         uint32_t syn_info;
5997         uint32_t synqf;
5998
5999         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6000                 return -EINVAL;
6001
6002         syn_info = filter_info->syn_info;
6003
6004         if (add) {
6005                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6006                         return -EINVAL;
6007                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6008                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6009
6010                 if (filter->hig_pri)
6011                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6012                 else
6013                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6014         } else {
6015                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6016                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6017                         return -ENOENT;
6018                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6019         }
6020
6021         filter_info->syn_info = synqf;
6022         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6023         IXGBE_WRITE_FLUSH(hw);
6024         return 0;
6025 }
6026
6027 static int
6028 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6029                         struct rte_eth_syn_filter *filter)
6030 {
6031         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6032         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6033
6034         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6035                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6036                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6037                 return 0;
6038         }
6039         return -ENOENT;
6040 }
6041
6042 static int
6043 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6044                         enum rte_filter_op filter_op,
6045                         void *arg)
6046 {
6047         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6048         int ret;
6049
6050         MAC_TYPE_FILTER_SUP(hw->mac.type);
6051
6052         if (filter_op == RTE_ETH_FILTER_NOP)
6053                 return 0;
6054
6055         if (arg == NULL) {
6056                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6057                             filter_op);
6058                 return -EINVAL;
6059         }
6060
6061         switch (filter_op) {
6062         case RTE_ETH_FILTER_ADD:
6063                 ret = ixgbe_syn_filter_set(dev,
6064                                 (struct rte_eth_syn_filter *)arg,
6065                                 TRUE);
6066                 break;
6067         case RTE_ETH_FILTER_DELETE:
6068                 ret = ixgbe_syn_filter_set(dev,
6069                                 (struct rte_eth_syn_filter *)arg,
6070                                 FALSE);
6071                 break;
6072         case RTE_ETH_FILTER_GET:
6073                 ret = ixgbe_syn_filter_get(dev,
6074                                 (struct rte_eth_syn_filter *)arg);
6075                 break;
6076         default:
6077                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6078                 ret = -EINVAL;
6079                 break;
6080         }
6081
6082         return ret;
6083 }
6084
6085
6086 static inline enum ixgbe_5tuple_protocol
6087 convert_protocol_type(uint8_t protocol_value)
6088 {
6089         if (protocol_value == IPPROTO_TCP)
6090                 return IXGBE_FILTER_PROTOCOL_TCP;
6091         else if (protocol_value == IPPROTO_UDP)
6092                 return IXGBE_FILTER_PROTOCOL_UDP;
6093         else if (protocol_value == IPPROTO_SCTP)
6094                 return IXGBE_FILTER_PROTOCOL_SCTP;
6095         else
6096                 return IXGBE_FILTER_PROTOCOL_NONE;
6097 }
6098
6099 /* inject a 5-tuple filter to HW */
6100 static inline void
6101 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6102                            struct ixgbe_5tuple_filter *filter)
6103 {
6104         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6105         int i;
6106         uint32_t ftqf, sdpqf;
6107         uint32_t l34timir = 0;
6108         uint8_t mask = 0xff;
6109
6110         i = filter->index;
6111
6112         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6113                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6114         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6115
6116         ftqf = (uint32_t)(filter->filter_info.proto &
6117                 IXGBE_FTQF_PROTOCOL_MASK);
6118         ftqf |= (uint32_t)((filter->filter_info.priority &
6119                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6120         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6121                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6122         if (filter->filter_info.dst_ip_mask == 0)
6123                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6124         if (filter->filter_info.src_port_mask == 0)
6125                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6126         if (filter->filter_info.dst_port_mask == 0)
6127                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6128         if (filter->filter_info.proto_mask == 0)
6129                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6130         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6131         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6132         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6133
6134         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6135         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6136         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6137         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6138
6139         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6140         l34timir |= (uint32_t)(filter->queue <<
6141                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6142         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6143 }
6144
6145 /*
6146  * add a 5tuple filter
6147  *
6148  * @param
6149  * dev: Pointer to struct rte_eth_dev.
6150  * index: the index the filter allocates.
6151  * filter: ponter to the filter that will be added.
6152  * rx_queue: the queue id the filter assigned to.
6153  *
6154  * @return
6155  *    - On success, zero.
6156  *    - On failure, a negative value.
6157  */
6158 static int
6159 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6160                         struct ixgbe_5tuple_filter *filter)
6161 {
6162         struct ixgbe_filter_info *filter_info =
6163                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6164         int i, idx, shift;
6165
6166         /*
6167          * look for an unused 5tuple filter index,
6168          * and insert the filter to list.
6169          */
6170         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6171                 idx = i / (sizeof(uint32_t) * NBBY);
6172                 shift = i % (sizeof(uint32_t) * NBBY);
6173                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6174                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6175                         filter->index = i;
6176                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6177                                           filter,
6178                                           entries);
6179                         break;
6180                 }
6181         }
6182         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6183                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6184                 return -ENOSYS;
6185         }
6186
6187         ixgbe_inject_5tuple_filter(dev, filter);
6188
6189         return 0;
6190 }
6191
6192 /*
6193  * remove a 5tuple filter
6194  *
6195  * @param
6196  * dev: Pointer to struct rte_eth_dev.
6197  * filter: the pointer of the filter will be removed.
6198  */
6199 static void
6200 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6201                         struct ixgbe_5tuple_filter *filter)
6202 {
6203         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6204         struct ixgbe_filter_info *filter_info =
6205                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6206         uint16_t index = filter->index;
6207
6208         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6209                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6210         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6211         rte_free(filter);
6212
6213         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6214         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6215         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6216         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6217         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6218 }
6219
6220 static int
6221 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6222 {
6223         struct ixgbe_hw *hw;
6224         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6225         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6226
6227         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6228
6229         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6230                 return -EINVAL;
6231
6232         /* refuse mtu that requires the support of scattered packets when this
6233          * feature has not been enabled before.
6234          */
6235         if (!rx_conf->enable_scatter &&
6236             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6237              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6238                 return -EINVAL;
6239
6240         /*
6241          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6242          * request of the version 2.0 of the mailbox API.
6243          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6244          * of the mailbox API.
6245          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6246          * prior to 3.11.33 which contains the following change:
6247          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6248          */
6249         ixgbevf_rlpml_set_vf(hw, max_frame);
6250
6251         /* update max frame size */
6252         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6253         return 0;
6254 }
6255
6256 static inline struct ixgbe_5tuple_filter *
6257 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6258                         struct ixgbe_5tuple_filter_info *key)
6259 {
6260         struct ixgbe_5tuple_filter *it;
6261
6262         TAILQ_FOREACH(it, filter_list, entries) {
6263                 if (memcmp(key, &it->filter_info,
6264                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6265                         return it;
6266                 }
6267         }
6268         return NULL;
6269 }
6270
6271 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6272 static inline int
6273 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6274                         struct ixgbe_5tuple_filter_info *filter_info)
6275 {
6276         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6277                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6278                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6279                 return -EINVAL;
6280
6281         switch (filter->dst_ip_mask) {
6282         case UINT32_MAX:
6283                 filter_info->dst_ip_mask = 0;
6284                 filter_info->dst_ip = filter->dst_ip;
6285                 break;
6286         case 0:
6287                 filter_info->dst_ip_mask = 1;
6288                 break;
6289         default:
6290                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6291                 return -EINVAL;
6292         }
6293
6294         switch (filter->src_ip_mask) {
6295         case UINT32_MAX:
6296                 filter_info->src_ip_mask = 0;
6297                 filter_info->src_ip = filter->src_ip;
6298                 break;
6299         case 0:
6300                 filter_info->src_ip_mask = 1;
6301                 break;
6302         default:
6303                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6304                 return -EINVAL;
6305         }
6306
6307         switch (filter->dst_port_mask) {
6308         case UINT16_MAX:
6309                 filter_info->dst_port_mask = 0;
6310                 filter_info->dst_port = filter->dst_port;
6311                 break;
6312         case 0:
6313                 filter_info->dst_port_mask = 1;
6314                 break;
6315         default:
6316                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6317                 return -EINVAL;
6318         }
6319
6320         switch (filter->src_port_mask) {
6321         case UINT16_MAX:
6322                 filter_info->src_port_mask = 0;
6323                 filter_info->src_port = filter->src_port;
6324                 break;
6325         case 0:
6326                 filter_info->src_port_mask = 1;
6327                 break;
6328         default:
6329                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6330                 return -EINVAL;
6331         }
6332
6333         switch (filter->proto_mask) {
6334         case UINT8_MAX:
6335                 filter_info->proto_mask = 0;
6336                 filter_info->proto =
6337                         convert_protocol_type(filter->proto);
6338                 break;
6339         case 0:
6340                 filter_info->proto_mask = 1;
6341                 break;
6342         default:
6343                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6344                 return -EINVAL;
6345         }
6346
6347         filter_info->priority = (uint8_t)filter->priority;
6348         return 0;
6349 }
6350
6351 /*
6352  * add or delete a ntuple filter
6353  *
6354  * @param
6355  * dev: Pointer to struct rte_eth_dev.
6356  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6357  * add: if true, add filter, if false, remove filter
6358  *
6359  * @return
6360  *    - On success, zero.
6361  *    - On failure, a negative value.
6362  */
6363 int
6364 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6365                         struct rte_eth_ntuple_filter *ntuple_filter,
6366                         bool add)
6367 {
6368         struct ixgbe_filter_info *filter_info =
6369                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6370         struct ixgbe_5tuple_filter_info filter_5tuple;
6371         struct ixgbe_5tuple_filter *filter;
6372         int ret;
6373
6374         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6375                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6376                 return -EINVAL;
6377         }
6378
6379         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6380         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6381         if (ret < 0)
6382                 return ret;
6383
6384         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6385                                          &filter_5tuple);
6386         if (filter != NULL && add) {
6387                 PMD_DRV_LOG(ERR, "filter exists.");
6388                 return -EEXIST;
6389         }
6390         if (filter == NULL && !add) {
6391                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6392                 return -ENOENT;
6393         }
6394
6395         if (add) {
6396                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6397                                 sizeof(struct ixgbe_5tuple_filter), 0);
6398                 if (filter == NULL)
6399                         return -ENOMEM;
6400                 rte_memcpy(&filter->filter_info,
6401                                  &filter_5tuple,
6402                                  sizeof(struct ixgbe_5tuple_filter_info));
6403                 filter->queue = ntuple_filter->queue;
6404                 ret = ixgbe_add_5tuple_filter(dev, filter);
6405                 if (ret < 0) {
6406                         rte_free(filter);
6407                         return ret;
6408                 }
6409         } else
6410                 ixgbe_remove_5tuple_filter(dev, filter);
6411
6412         return 0;
6413 }
6414
6415 /*
6416  * get a ntuple filter
6417  *
6418  * @param
6419  * dev: Pointer to struct rte_eth_dev.
6420  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6421  *
6422  * @return
6423  *    - On success, zero.
6424  *    - On failure, a negative value.
6425  */
6426 static int
6427 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6428                         struct rte_eth_ntuple_filter *ntuple_filter)
6429 {
6430         struct ixgbe_filter_info *filter_info =
6431                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6432         struct ixgbe_5tuple_filter_info filter_5tuple;
6433         struct ixgbe_5tuple_filter *filter;
6434         int ret;
6435
6436         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6437                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6438                 return -EINVAL;
6439         }
6440
6441         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6442         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6443         if (ret < 0)
6444                 return ret;
6445
6446         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6447                                          &filter_5tuple);
6448         if (filter == NULL) {
6449                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6450                 return -ENOENT;
6451         }
6452         ntuple_filter->queue = filter->queue;
6453         return 0;
6454 }
6455
6456 /*
6457  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6458  * @dev: pointer to rte_eth_dev structure
6459  * @filter_op:operation will be taken.
6460  * @arg: a pointer to specific structure corresponding to the filter_op
6461  *
6462  * @return
6463  *    - On success, zero.
6464  *    - On failure, a negative value.
6465  */
6466 static int
6467 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6468                                 enum rte_filter_op filter_op,
6469                                 void *arg)
6470 {
6471         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6472         int ret;
6473
6474         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6475
6476         if (filter_op == RTE_ETH_FILTER_NOP)
6477                 return 0;
6478
6479         if (arg == NULL) {
6480                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6481                             filter_op);
6482                 return -EINVAL;
6483         }
6484
6485         switch (filter_op) {
6486         case RTE_ETH_FILTER_ADD:
6487                 ret = ixgbe_add_del_ntuple_filter(dev,
6488                         (struct rte_eth_ntuple_filter *)arg,
6489                         TRUE);
6490                 break;
6491         case RTE_ETH_FILTER_DELETE:
6492                 ret = ixgbe_add_del_ntuple_filter(dev,
6493                         (struct rte_eth_ntuple_filter *)arg,
6494                         FALSE);
6495                 break;
6496         case RTE_ETH_FILTER_GET:
6497                 ret = ixgbe_get_ntuple_filter(dev,
6498                         (struct rte_eth_ntuple_filter *)arg);
6499                 break;
6500         default:
6501                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6502                 ret = -EINVAL;
6503                 break;
6504         }
6505         return ret;
6506 }
6507
6508 int
6509 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6510                         struct rte_eth_ethertype_filter *filter,
6511                         bool add)
6512 {
6513         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6514         struct ixgbe_filter_info *filter_info =
6515                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6516         uint32_t etqf = 0;
6517         uint32_t etqs = 0;
6518         int ret;
6519         struct ixgbe_ethertype_filter ethertype_filter;
6520
6521         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6522                 return -EINVAL;
6523
6524         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6525                 filter->ether_type == ETHER_TYPE_IPv6) {
6526                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6527                         " ethertype filter.", filter->ether_type);
6528                 return -EINVAL;
6529         }
6530
6531         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6532                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6533                 return -EINVAL;
6534         }
6535         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6536                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6537                 return -EINVAL;
6538         }
6539
6540         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6541         if (ret >= 0 && add) {
6542                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6543                             filter->ether_type);
6544                 return -EEXIST;
6545         }
6546         if (ret < 0 && !add) {
6547                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6548                             filter->ether_type);
6549                 return -ENOENT;
6550         }
6551
6552         if (add) {
6553                 etqf = IXGBE_ETQF_FILTER_EN;
6554                 etqf |= (uint32_t)filter->ether_type;
6555                 etqs |= (uint32_t)((filter->queue <<
6556                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6557                                     IXGBE_ETQS_RX_QUEUE);
6558                 etqs |= IXGBE_ETQS_QUEUE_EN;
6559
6560                 ethertype_filter.ethertype = filter->ether_type;
6561                 ethertype_filter.etqf = etqf;
6562                 ethertype_filter.etqs = etqs;
6563                 ethertype_filter.conf = FALSE;
6564                 ret = ixgbe_ethertype_filter_insert(filter_info,
6565                                                     &ethertype_filter);
6566                 if (ret < 0) {
6567                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6568                         return -ENOSPC;
6569                 }
6570         } else {
6571                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6572                 if (ret < 0)
6573                         return -ENOSYS;
6574         }
6575         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6576         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6577         IXGBE_WRITE_FLUSH(hw);
6578
6579         return 0;
6580 }
6581
6582 static int
6583 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6584                         struct rte_eth_ethertype_filter *filter)
6585 {
6586         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6587         struct ixgbe_filter_info *filter_info =
6588                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6589         uint32_t etqf, etqs;
6590         int ret;
6591
6592         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6593         if (ret < 0) {
6594                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6595                             filter->ether_type);
6596                 return -ENOENT;
6597         }
6598
6599         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6600         if (etqf & IXGBE_ETQF_FILTER_EN) {
6601                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6602                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6603                 filter->flags = 0;
6604                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6605                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6606                 return 0;
6607         }
6608         return -ENOENT;
6609 }
6610
6611 /*
6612  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6613  * @dev: pointer to rte_eth_dev structure
6614  * @filter_op:operation will be taken.
6615  * @arg: a pointer to specific structure corresponding to the filter_op
6616  */
6617 static int
6618 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6619                                 enum rte_filter_op filter_op,
6620                                 void *arg)
6621 {
6622         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6623         int ret;
6624
6625         MAC_TYPE_FILTER_SUP(hw->mac.type);
6626
6627         if (filter_op == RTE_ETH_FILTER_NOP)
6628                 return 0;
6629
6630         if (arg == NULL) {
6631                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6632                             filter_op);
6633                 return -EINVAL;
6634         }
6635
6636         switch (filter_op) {
6637         case RTE_ETH_FILTER_ADD:
6638                 ret = ixgbe_add_del_ethertype_filter(dev,
6639                         (struct rte_eth_ethertype_filter *)arg,
6640                         TRUE);
6641                 break;
6642         case RTE_ETH_FILTER_DELETE:
6643                 ret = ixgbe_add_del_ethertype_filter(dev,
6644                         (struct rte_eth_ethertype_filter *)arg,
6645                         FALSE);
6646                 break;
6647         case RTE_ETH_FILTER_GET:
6648                 ret = ixgbe_get_ethertype_filter(dev,
6649                         (struct rte_eth_ethertype_filter *)arg);
6650                 break;
6651         default:
6652                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6653                 ret = -EINVAL;
6654                 break;
6655         }
6656         return ret;
6657 }
6658
6659 static int
6660 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6661                      enum rte_filter_type filter_type,
6662                      enum rte_filter_op filter_op,
6663                      void *arg)
6664 {
6665         int ret = 0;
6666
6667         switch (filter_type) {
6668         case RTE_ETH_FILTER_NTUPLE:
6669                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6670                 break;
6671         case RTE_ETH_FILTER_ETHERTYPE:
6672                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6673                 break;
6674         case RTE_ETH_FILTER_SYN:
6675                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6676                 break;
6677         case RTE_ETH_FILTER_FDIR:
6678                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6679                 break;
6680         case RTE_ETH_FILTER_L2_TUNNEL:
6681                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6682                 break;
6683         case RTE_ETH_FILTER_GENERIC:
6684                 if (filter_op != RTE_ETH_FILTER_GET)
6685                         return -EINVAL;
6686                 *(const void **)arg = &ixgbe_flow_ops;
6687                 break;
6688         default:
6689                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6690                                                         filter_type);
6691                 ret = -EINVAL;
6692                 break;
6693         }
6694
6695         return ret;
6696 }
6697
6698 static u8 *
6699 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6700                         u8 **mc_addr_ptr, u32 *vmdq)
6701 {
6702         u8 *mc_addr;
6703
6704         *vmdq = 0;
6705         mc_addr = *mc_addr_ptr;
6706         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6707         return mc_addr;
6708 }
6709
6710 static int
6711 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6712                           struct ether_addr *mc_addr_set,
6713                           uint32_t nb_mc_addr)
6714 {
6715         struct ixgbe_hw *hw;
6716         u8 *mc_addr_list;
6717
6718         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6719         mc_addr_list = (u8 *)mc_addr_set;
6720         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6721                                          ixgbe_dev_addr_list_itr, TRUE);
6722 }
6723
6724 static uint64_t
6725 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6726 {
6727         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6728         uint64_t systime_cycles;
6729
6730         switch (hw->mac.type) {
6731         case ixgbe_mac_X550:
6732         case ixgbe_mac_X550EM_x:
6733         case ixgbe_mac_X550EM_a:
6734                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6735                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6736                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6737                                 * NSEC_PER_SEC;
6738                 break;
6739         default:
6740                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6741                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6742                                 << 32;
6743         }
6744
6745         return systime_cycles;
6746 }
6747
6748 static uint64_t
6749 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6750 {
6751         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6752         uint64_t rx_tstamp_cycles;
6753
6754         switch (hw->mac.type) {
6755         case ixgbe_mac_X550:
6756         case ixgbe_mac_X550EM_x:
6757         case ixgbe_mac_X550EM_a:
6758                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6759                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6760                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6761                                 * NSEC_PER_SEC;
6762                 break;
6763         default:
6764                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6765                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6766                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6767                                 << 32;
6768         }
6769
6770         return rx_tstamp_cycles;
6771 }
6772
6773 static uint64_t
6774 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6775 {
6776         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6777         uint64_t tx_tstamp_cycles;
6778
6779         switch (hw->mac.type) {
6780         case ixgbe_mac_X550:
6781         case ixgbe_mac_X550EM_x:
6782         case ixgbe_mac_X550EM_a:
6783                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6784                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6785                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6786                                 * NSEC_PER_SEC;
6787                 break;
6788         default:
6789                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6790                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6791                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6792                                 << 32;
6793         }
6794
6795         return tx_tstamp_cycles;
6796 }
6797
6798 static void
6799 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6800 {
6801         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6802         struct ixgbe_adapter *adapter =
6803                 (struct ixgbe_adapter *)dev->data->dev_private;
6804         struct rte_eth_link link;
6805         uint32_t incval = 0;
6806         uint32_t shift = 0;
6807
6808         /* Get current link speed. */
6809         memset(&link, 0, sizeof(link));
6810         ixgbe_dev_link_update(dev, 1);
6811         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6812
6813         switch (link.link_speed) {
6814         case ETH_SPEED_NUM_100M:
6815                 incval = IXGBE_INCVAL_100;
6816                 shift = IXGBE_INCVAL_SHIFT_100;
6817                 break;
6818         case ETH_SPEED_NUM_1G:
6819                 incval = IXGBE_INCVAL_1GB;
6820                 shift = IXGBE_INCVAL_SHIFT_1GB;
6821                 break;
6822         case ETH_SPEED_NUM_10G:
6823         default:
6824                 incval = IXGBE_INCVAL_10GB;
6825                 shift = IXGBE_INCVAL_SHIFT_10GB;
6826                 break;
6827         }
6828
6829         switch (hw->mac.type) {
6830         case ixgbe_mac_X550:
6831         case ixgbe_mac_X550EM_x:
6832         case ixgbe_mac_X550EM_a:
6833                 /* Independent of link speed. */
6834                 incval = 1;
6835                 /* Cycles read will be interpreted as ns. */
6836                 shift = 0;
6837                 /* Fall-through */
6838         case ixgbe_mac_X540:
6839                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6840                 break;
6841         case ixgbe_mac_82599EB:
6842                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6843                 shift -= IXGBE_INCVAL_SHIFT_82599;
6844                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6845                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6846                 break;
6847         default:
6848                 /* Not supported. */
6849                 return;
6850         }
6851
6852         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6853         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6854         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6855
6856         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6857         adapter->systime_tc.cc_shift = shift;
6858         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6859
6860         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6861         adapter->rx_tstamp_tc.cc_shift = shift;
6862         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6863
6864         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6865         adapter->tx_tstamp_tc.cc_shift = shift;
6866         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6867 }
6868
6869 static int
6870 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6871 {
6872         struct ixgbe_adapter *adapter =
6873                         (struct ixgbe_adapter *)dev->data->dev_private;
6874
6875         adapter->systime_tc.nsec += delta;
6876         adapter->rx_tstamp_tc.nsec += delta;
6877         adapter->tx_tstamp_tc.nsec += delta;
6878
6879         return 0;
6880 }
6881
6882 static int
6883 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6884 {
6885         uint64_t ns;
6886         struct ixgbe_adapter *adapter =
6887                         (struct ixgbe_adapter *)dev->data->dev_private;
6888
6889         ns = rte_timespec_to_ns(ts);
6890         /* Set the timecounters to a new value. */
6891         adapter->systime_tc.nsec = ns;
6892         adapter->rx_tstamp_tc.nsec = ns;
6893         adapter->tx_tstamp_tc.nsec = ns;
6894
6895         return 0;
6896 }
6897
6898 static int
6899 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6900 {
6901         uint64_t ns, systime_cycles;
6902         struct ixgbe_adapter *adapter =
6903                         (struct ixgbe_adapter *)dev->data->dev_private;
6904
6905         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6906         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6907         *ts = rte_ns_to_timespec(ns);
6908
6909         return 0;
6910 }
6911
6912 static int
6913 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6914 {
6915         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6916         uint32_t tsync_ctl;
6917         uint32_t tsauxc;
6918
6919         /* Stop the timesync system time. */
6920         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6921         /* Reset the timesync system time value. */
6922         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6923         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6924
6925         /* Enable system time for platforms where it isn't on by default. */
6926         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6927         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6928         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6929
6930         ixgbe_start_timecounters(dev);
6931
6932         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6933         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6934                         (ETHER_TYPE_1588 |
6935                          IXGBE_ETQF_FILTER_EN |
6936                          IXGBE_ETQF_1588));
6937
6938         /* Enable timestamping of received PTP packets. */
6939         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6940         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6941         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6942
6943         /* Enable timestamping of transmitted PTP packets. */
6944         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6945         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6946         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6947
6948         IXGBE_WRITE_FLUSH(hw);
6949
6950         return 0;
6951 }
6952
6953 static int
6954 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6955 {
6956         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6957         uint32_t tsync_ctl;
6958
6959         /* Disable timestamping of transmitted PTP packets. */
6960         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6961         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6962         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6963
6964         /* Disable timestamping of received PTP packets. */
6965         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6966         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6967         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6968
6969         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6970         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6971
6972         /* Stop incrementating the System Time registers. */
6973         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6974
6975         return 0;
6976 }
6977
6978 static int
6979 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6980                                  struct timespec *timestamp,
6981                                  uint32_t flags __rte_unused)
6982 {
6983         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6984         struct ixgbe_adapter *adapter =
6985                 (struct ixgbe_adapter *)dev->data->dev_private;
6986         uint32_t tsync_rxctl;
6987         uint64_t rx_tstamp_cycles;
6988         uint64_t ns;
6989
6990         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6991         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6992                 return -EINVAL;
6993
6994         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6995         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6996         *timestamp = rte_ns_to_timespec(ns);
6997
6998         return  0;
6999 }
7000
7001 static int
7002 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7003                                  struct timespec *timestamp)
7004 {
7005         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7006         struct ixgbe_adapter *adapter =
7007                 (struct ixgbe_adapter *)dev->data->dev_private;
7008         uint32_t tsync_txctl;
7009         uint64_t tx_tstamp_cycles;
7010         uint64_t ns;
7011
7012         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7013         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7014                 return -EINVAL;
7015
7016         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7017         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7018         *timestamp = rte_ns_to_timespec(ns);
7019
7020         return 0;
7021 }
7022
7023 static int
7024 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7025 {
7026         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7027         int count = 0;
7028         int g_ind = 0;
7029         const struct reg_info *reg_group;
7030         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7031                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7032
7033         while ((reg_group = reg_set[g_ind++]))
7034                 count += ixgbe_regs_group_count(reg_group);
7035
7036         return count;
7037 }
7038
7039 static int
7040 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7041 {
7042         int count = 0;
7043         int g_ind = 0;
7044         const struct reg_info *reg_group;
7045
7046         while ((reg_group = ixgbevf_regs[g_ind++]))
7047                 count += ixgbe_regs_group_count(reg_group);
7048
7049         return count;
7050 }
7051
7052 static int
7053 ixgbe_get_regs(struct rte_eth_dev *dev,
7054               struct rte_dev_reg_info *regs)
7055 {
7056         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7057         uint32_t *data = regs->data;
7058         int g_ind = 0;
7059         int count = 0;
7060         const struct reg_info *reg_group;
7061         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7062                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7063
7064         if (data == NULL) {
7065                 regs->length = ixgbe_get_reg_length(dev);
7066                 regs->width = sizeof(uint32_t);
7067                 return 0;
7068         }
7069
7070         /* Support only full register dump */
7071         if ((regs->length == 0) ||
7072             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7073                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7074                         hw->device_id;
7075                 while ((reg_group = reg_set[g_ind++]))
7076                         count += ixgbe_read_regs_group(dev, &data[count],
7077                                 reg_group);
7078                 return 0;
7079         }
7080
7081         return -ENOTSUP;
7082 }
7083
7084 static int
7085 ixgbevf_get_regs(struct rte_eth_dev *dev,
7086                 struct rte_dev_reg_info *regs)
7087 {
7088         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7089         uint32_t *data = regs->data;
7090         int g_ind = 0;
7091         int count = 0;
7092         const struct reg_info *reg_group;
7093
7094         if (data == NULL) {
7095                 regs->length = ixgbevf_get_reg_length(dev);
7096                 regs->width = sizeof(uint32_t);
7097                 return 0;
7098         }
7099
7100         /* Support only full register dump */
7101         if ((regs->length == 0) ||
7102             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7103                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7104                         hw->device_id;
7105                 while ((reg_group = ixgbevf_regs[g_ind++]))
7106                         count += ixgbe_read_regs_group(dev, &data[count],
7107                                                       reg_group);
7108                 return 0;
7109         }
7110
7111         return -ENOTSUP;
7112 }
7113
7114 static int
7115 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7116 {
7117         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7118
7119         /* Return unit is byte count */
7120         return hw->eeprom.word_size * 2;
7121 }
7122
7123 static int
7124 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7125                 struct rte_dev_eeprom_info *in_eeprom)
7126 {
7127         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7128         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7129         uint16_t *data = in_eeprom->data;
7130         int first, length;
7131
7132         first = in_eeprom->offset >> 1;
7133         length = in_eeprom->length >> 1;
7134         if ((first > hw->eeprom.word_size) ||
7135             ((first + length) > hw->eeprom.word_size))
7136                 return -EINVAL;
7137
7138         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7139
7140         return eeprom->ops.read_buffer(hw, first, length, data);
7141 }
7142
7143 static int
7144 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7145                 struct rte_dev_eeprom_info *in_eeprom)
7146 {
7147         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7148         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7149         uint16_t *data = in_eeprom->data;
7150         int first, length;
7151
7152         first = in_eeprom->offset >> 1;
7153         length = in_eeprom->length >> 1;
7154         if ((first > hw->eeprom.word_size) ||
7155             ((first + length) > hw->eeprom.word_size))
7156                 return -EINVAL;
7157
7158         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7159
7160         return eeprom->ops.write_buffer(hw,  first, length, data);
7161 }
7162
7163 uint16_t
7164 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7165         switch (mac_type) {
7166         case ixgbe_mac_X550:
7167         case ixgbe_mac_X550EM_x:
7168         case ixgbe_mac_X550EM_a:
7169                 return ETH_RSS_RETA_SIZE_512;
7170         case ixgbe_mac_X550_vf:
7171         case ixgbe_mac_X550EM_x_vf:
7172         case ixgbe_mac_X550EM_a_vf:
7173                 return ETH_RSS_RETA_SIZE_64;
7174         default:
7175                 return ETH_RSS_RETA_SIZE_128;
7176         }
7177 }
7178
7179 uint32_t
7180 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7181         switch (mac_type) {
7182         case ixgbe_mac_X550:
7183         case ixgbe_mac_X550EM_x:
7184         case ixgbe_mac_X550EM_a:
7185                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7186                         return IXGBE_RETA(reta_idx >> 2);
7187                 else
7188                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7189         case ixgbe_mac_X550_vf:
7190         case ixgbe_mac_X550EM_x_vf:
7191         case ixgbe_mac_X550EM_a_vf:
7192                 return IXGBE_VFRETA(reta_idx >> 2);
7193         default:
7194                 return IXGBE_RETA(reta_idx >> 2);
7195         }
7196 }
7197
7198 uint32_t
7199 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7200         switch (mac_type) {
7201         case ixgbe_mac_X550_vf:
7202         case ixgbe_mac_X550EM_x_vf:
7203         case ixgbe_mac_X550EM_a_vf:
7204                 return IXGBE_VFMRQC;
7205         default:
7206                 return IXGBE_MRQC;
7207         }
7208 }
7209
7210 uint32_t
7211 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7212         switch (mac_type) {
7213         case ixgbe_mac_X550_vf:
7214         case ixgbe_mac_X550EM_x_vf:
7215         case ixgbe_mac_X550EM_a_vf:
7216                 return IXGBE_VFRSSRK(i);
7217         default:
7218                 return IXGBE_RSSRK(i);
7219         }
7220 }
7221
7222 bool
7223 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7224         switch (mac_type) {
7225         case ixgbe_mac_82599_vf:
7226         case ixgbe_mac_X540_vf:
7227                 return 0;
7228         default:
7229                 return 1;
7230         }
7231 }
7232
7233 static int
7234 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7235                         struct rte_eth_dcb_info *dcb_info)
7236 {
7237         struct ixgbe_dcb_config *dcb_config =
7238                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7239         struct ixgbe_dcb_tc_config *tc;
7240         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7241         uint8_t nb_tcs;
7242         uint8_t i, j;
7243
7244         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7245                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7246         else
7247                 dcb_info->nb_tcs = 1;
7248
7249         tc_queue = &dcb_info->tc_queue;
7250         nb_tcs = dcb_info->nb_tcs;
7251
7252         if (dcb_config->vt_mode) { /* vt is enabled*/
7253                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7254                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7255                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7256                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7257                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7258                         for (j = 0; j < nb_tcs; j++) {
7259                                 tc_queue->tc_rxq[0][j].base = j;
7260                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7261                                 tc_queue->tc_txq[0][j].base = j;
7262                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7263                         }
7264                 } else {
7265                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7266                                 for (j = 0; j < nb_tcs; j++) {
7267                                         tc_queue->tc_rxq[i][j].base =
7268                                                 i * nb_tcs + j;
7269                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7270                                         tc_queue->tc_txq[i][j].base =
7271                                                 i * nb_tcs + j;
7272                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7273                                 }
7274                         }
7275                 }
7276         } else { /* vt is disabled*/
7277                 struct rte_eth_dcb_rx_conf *rx_conf =
7278                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7279                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7280                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7281                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7282                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7283                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7284                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7285                         }
7286                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7287                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7288                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7289                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7290                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7291                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7292                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7293                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7294                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7295                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7296                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7297                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7298                         }
7299                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7300                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7301                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7302                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7303                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7304                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7305                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7306                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7307                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7308                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7309                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7310                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7311                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7312                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7313                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7314                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7315                 }
7316         }
7317         for (i = 0; i < dcb_info->nb_tcs; i++) {
7318                 tc = &dcb_config->tc_config[i];
7319                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7320         }
7321         return 0;
7322 }
7323
7324 /* Update e-tag ether type */
7325 static int
7326 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7327                             uint16_t ether_type)
7328 {
7329         uint32_t etag_etype;
7330
7331         if (hw->mac.type != ixgbe_mac_X550 &&
7332             hw->mac.type != ixgbe_mac_X550EM_x &&
7333             hw->mac.type != ixgbe_mac_X550EM_a) {
7334                 return -ENOTSUP;
7335         }
7336
7337         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7338         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7339         etag_etype |= ether_type;
7340         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7341         IXGBE_WRITE_FLUSH(hw);
7342
7343         return 0;
7344 }
7345
7346 /* Config l2 tunnel ether type */
7347 static int
7348 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7349                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7350 {
7351         int ret = 0;
7352         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7353         struct ixgbe_l2_tn_info *l2_tn_info =
7354                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7355
7356         if (l2_tunnel == NULL)
7357                 return -EINVAL;
7358
7359         switch (l2_tunnel->l2_tunnel_type) {
7360         case RTE_L2_TUNNEL_TYPE_E_TAG:
7361                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7362                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7363                 break;
7364         default:
7365                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7366                 ret = -EINVAL;
7367                 break;
7368         }
7369
7370         return ret;
7371 }
7372
7373 /* Enable e-tag tunnel */
7374 static int
7375 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7376 {
7377         uint32_t etag_etype;
7378
7379         if (hw->mac.type != ixgbe_mac_X550 &&
7380             hw->mac.type != ixgbe_mac_X550EM_x &&
7381             hw->mac.type != ixgbe_mac_X550EM_a) {
7382                 return -ENOTSUP;
7383         }
7384
7385         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7386         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7387         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7388         IXGBE_WRITE_FLUSH(hw);
7389
7390         return 0;
7391 }
7392
7393 /* Enable l2 tunnel */
7394 static int
7395 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7396                            enum rte_eth_tunnel_type l2_tunnel_type)
7397 {
7398         int ret = 0;
7399         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7400         struct ixgbe_l2_tn_info *l2_tn_info =
7401                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7402
7403         switch (l2_tunnel_type) {
7404         case RTE_L2_TUNNEL_TYPE_E_TAG:
7405                 l2_tn_info->e_tag_en = TRUE;
7406                 ret = ixgbe_e_tag_enable(hw);
7407                 break;
7408         default:
7409                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7410                 ret = -EINVAL;
7411                 break;
7412         }
7413
7414         return ret;
7415 }
7416
7417 /* Disable e-tag tunnel */
7418 static int
7419 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7420 {
7421         uint32_t etag_etype;
7422
7423         if (hw->mac.type != ixgbe_mac_X550 &&
7424             hw->mac.type != ixgbe_mac_X550EM_x &&
7425             hw->mac.type != ixgbe_mac_X550EM_a) {
7426                 return -ENOTSUP;
7427         }
7428
7429         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7430         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7431         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7432         IXGBE_WRITE_FLUSH(hw);
7433
7434         return 0;
7435 }
7436
7437 /* Disable l2 tunnel */
7438 static int
7439 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7440                             enum rte_eth_tunnel_type l2_tunnel_type)
7441 {
7442         int ret = 0;
7443         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7444         struct ixgbe_l2_tn_info *l2_tn_info =
7445                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7446
7447         switch (l2_tunnel_type) {
7448         case RTE_L2_TUNNEL_TYPE_E_TAG:
7449                 l2_tn_info->e_tag_en = FALSE;
7450                 ret = ixgbe_e_tag_disable(hw);
7451                 break;
7452         default:
7453                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7454                 ret = -EINVAL;
7455                 break;
7456         }
7457
7458         return ret;
7459 }
7460
7461 static int
7462 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7463                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7464 {
7465         int ret = 0;
7466         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7467         uint32_t i, rar_entries;
7468         uint32_t rar_low, rar_high;
7469
7470         if (hw->mac.type != ixgbe_mac_X550 &&
7471             hw->mac.type != ixgbe_mac_X550EM_x &&
7472             hw->mac.type != ixgbe_mac_X550EM_a) {
7473                 return -ENOTSUP;
7474         }
7475
7476         rar_entries = ixgbe_get_num_rx_addrs(hw);
7477
7478         for (i = 1; i < rar_entries; i++) {
7479                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7480                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7481                 if ((rar_high & IXGBE_RAH_AV) &&
7482                     (rar_high & IXGBE_RAH_ADTYPE) &&
7483                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7484                      l2_tunnel->tunnel_id)) {
7485                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7486                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7487
7488                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7489
7490                         return ret;
7491                 }
7492         }
7493
7494         return ret;
7495 }
7496
7497 static int
7498 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7499                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7500 {
7501         int ret = 0;
7502         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7503         uint32_t i, rar_entries;
7504         uint32_t rar_low, rar_high;
7505
7506         if (hw->mac.type != ixgbe_mac_X550 &&
7507             hw->mac.type != ixgbe_mac_X550EM_x &&
7508             hw->mac.type != ixgbe_mac_X550EM_a) {
7509                 return -ENOTSUP;
7510         }
7511
7512         /* One entry for one tunnel. Try to remove potential existing entry. */
7513         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7514
7515         rar_entries = ixgbe_get_num_rx_addrs(hw);
7516
7517         for (i = 1; i < rar_entries; i++) {
7518                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7519                 if (rar_high & IXGBE_RAH_AV) {
7520                         continue;
7521                 } else {
7522                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7523                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7524                         rar_low = l2_tunnel->tunnel_id;
7525
7526                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7527                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7528
7529                         return ret;
7530                 }
7531         }
7532
7533         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7534                      " Please remove a rule before adding a new one.");
7535         return -EINVAL;
7536 }
7537
7538 static inline struct ixgbe_l2_tn_filter *
7539 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7540                           struct ixgbe_l2_tn_key *key)
7541 {
7542         int ret;
7543
7544         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7545         if (ret < 0)
7546                 return NULL;
7547
7548         return l2_tn_info->hash_map[ret];
7549 }
7550
7551 static inline int
7552 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7553                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7554 {
7555         int ret;
7556
7557         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7558                                &l2_tn_filter->key);
7559
7560         if (ret < 0) {
7561                 PMD_DRV_LOG(ERR,
7562                             "Failed to insert L2 tunnel filter"
7563                             " to hash table %d!",
7564                             ret);
7565                 return ret;
7566         }
7567
7568         l2_tn_info->hash_map[ret] = l2_tn_filter;
7569
7570         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7571
7572         return 0;
7573 }
7574
7575 static inline int
7576 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7577                           struct ixgbe_l2_tn_key *key)
7578 {
7579         int ret;
7580         struct ixgbe_l2_tn_filter *l2_tn_filter;
7581
7582         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7583
7584         if (ret < 0) {
7585                 PMD_DRV_LOG(ERR,
7586                             "No such L2 tunnel filter to delete %d!",
7587                             ret);
7588                 return ret;
7589         }
7590
7591         l2_tn_filter = l2_tn_info->hash_map[ret];
7592         l2_tn_info->hash_map[ret] = NULL;
7593
7594         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7595         rte_free(l2_tn_filter);
7596
7597         return 0;
7598 }
7599
7600 /* Add l2 tunnel filter */
7601 int
7602 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7603                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7604                                bool restore)
7605 {
7606         int ret;
7607         struct ixgbe_l2_tn_info *l2_tn_info =
7608                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7609         struct ixgbe_l2_tn_key key;
7610         struct ixgbe_l2_tn_filter *node;
7611
7612         if (!restore) {
7613                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7614                 key.tn_id = l2_tunnel->tunnel_id;
7615
7616                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7617
7618                 if (node) {
7619                         PMD_DRV_LOG(ERR,
7620                                     "The L2 tunnel filter already exists!");
7621                         return -EINVAL;
7622                 }
7623
7624                 node = rte_zmalloc("ixgbe_l2_tn",
7625                                    sizeof(struct ixgbe_l2_tn_filter),
7626                                    0);
7627                 if (!node)
7628                         return -ENOMEM;
7629
7630                 rte_memcpy(&node->key,
7631                                  &key,
7632                                  sizeof(struct ixgbe_l2_tn_key));
7633                 node->pool = l2_tunnel->pool;
7634                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7635                 if (ret < 0) {
7636                         rte_free(node);
7637                         return ret;
7638                 }
7639         }
7640
7641         switch (l2_tunnel->l2_tunnel_type) {
7642         case RTE_L2_TUNNEL_TYPE_E_TAG:
7643                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7644                 break;
7645         default:
7646                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7647                 ret = -EINVAL;
7648                 break;
7649         }
7650
7651         if ((!restore) && (ret < 0))
7652                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7653
7654         return ret;
7655 }
7656
7657 /* Delete l2 tunnel filter */
7658 int
7659 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7660                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7661 {
7662         int ret;
7663         struct ixgbe_l2_tn_info *l2_tn_info =
7664                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7665         struct ixgbe_l2_tn_key key;
7666
7667         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7668         key.tn_id = l2_tunnel->tunnel_id;
7669         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7670         if (ret < 0)
7671                 return ret;
7672
7673         switch (l2_tunnel->l2_tunnel_type) {
7674         case RTE_L2_TUNNEL_TYPE_E_TAG:
7675                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7676                 break;
7677         default:
7678                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7679                 ret = -EINVAL;
7680                 break;
7681         }
7682
7683         return ret;
7684 }
7685
7686 /**
7687  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7688  * @dev: pointer to rte_eth_dev structure
7689  * @filter_op:operation will be taken.
7690  * @arg: a pointer to specific structure corresponding to the filter_op
7691  */
7692 static int
7693 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7694                                   enum rte_filter_op filter_op,
7695                                   void *arg)
7696 {
7697         int ret;
7698
7699         if (filter_op == RTE_ETH_FILTER_NOP)
7700                 return 0;
7701
7702         if (arg == NULL) {
7703                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7704                             filter_op);
7705                 return -EINVAL;
7706         }
7707
7708         switch (filter_op) {
7709         case RTE_ETH_FILTER_ADD:
7710                 ret = ixgbe_dev_l2_tunnel_filter_add
7711                         (dev,
7712                          (struct rte_eth_l2_tunnel_conf *)arg,
7713                          FALSE);
7714                 break;
7715         case RTE_ETH_FILTER_DELETE:
7716                 ret = ixgbe_dev_l2_tunnel_filter_del
7717                         (dev,
7718                          (struct rte_eth_l2_tunnel_conf *)arg);
7719                 break;
7720         default:
7721                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7722                 ret = -EINVAL;
7723                 break;
7724         }
7725         return ret;
7726 }
7727
7728 static int
7729 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7730 {
7731         int ret = 0;
7732         uint32_t ctrl;
7733         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7734
7735         if (hw->mac.type != ixgbe_mac_X550 &&
7736             hw->mac.type != ixgbe_mac_X550EM_x &&
7737             hw->mac.type != ixgbe_mac_X550EM_a) {
7738                 return -ENOTSUP;
7739         }
7740
7741         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7742         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7743         if (en)
7744                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7745         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7746
7747         return ret;
7748 }
7749
7750 /* Enable l2 tunnel forwarding */
7751 static int
7752 ixgbe_dev_l2_tunnel_forwarding_enable
7753         (struct rte_eth_dev *dev,
7754          enum rte_eth_tunnel_type l2_tunnel_type)
7755 {
7756         struct ixgbe_l2_tn_info *l2_tn_info =
7757                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7758         int ret = 0;
7759
7760         switch (l2_tunnel_type) {
7761         case RTE_L2_TUNNEL_TYPE_E_TAG:
7762                 l2_tn_info->e_tag_fwd_en = TRUE;
7763                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7764                 break;
7765         default:
7766                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7767                 ret = -EINVAL;
7768                 break;
7769         }
7770
7771         return ret;
7772 }
7773
7774 /* Disable l2 tunnel forwarding */
7775 static int
7776 ixgbe_dev_l2_tunnel_forwarding_disable
7777         (struct rte_eth_dev *dev,
7778          enum rte_eth_tunnel_type l2_tunnel_type)
7779 {
7780         struct ixgbe_l2_tn_info *l2_tn_info =
7781                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7782         int ret = 0;
7783
7784         switch (l2_tunnel_type) {
7785         case RTE_L2_TUNNEL_TYPE_E_TAG:
7786                 l2_tn_info->e_tag_fwd_en = FALSE;
7787                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7788                 break;
7789         default:
7790                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7791                 ret = -EINVAL;
7792                 break;
7793         }
7794
7795         return ret;
7796 }
7797
7798 static int
7799 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7800                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7801                              bool en)
7802 {
7803         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7804         int ret = 0;
7805         uint32_t vmtir, vmvir;
7806         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7807
7808         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7809                 PMD_DRV_LOG(ERR,
7810                             "VF id %u should be less than %u",
7811                             l2_tunnel->vf_id,
7812                             pci_dev->max_vfs);
7813                 return -EINVAL;
7814         }
7815
7816         if (hw->mac.type != ixgbe_mac_X550 &&
7817             hw->mac.type != ixgbe_mac_X550EM_x &&
7818             hw->mac.type != ixgbe_mac_X550EM_a) {
7819                 return -ENOTSUP;
7820         }
7821
7822         if (en)
7823                 vmtir = l2_tunnel->tunnel_id;
7824         else
7825                 vmtir = 0;
7826
7827         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7828
7829         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7830         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7831         if (en)
7832                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7833         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7834
7835         return ret;
7836 }
7837
7838 /* Enable l2 tunnel tag insertion */
7839 static int
7840 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7841                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7842 {
7843         int ret = 0;
7844
7845         switch (l2_tunnel->l2_tunnel_type) {
7846         case RTE_L2_TUNNEL_TYPE_E_TAG:
7847                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7848                 break;
7849         default:
7850                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7851                 ret = -EINVAL;
7852                 break;
7853         }
7854
7855         return ret;
7856 }
7857
7858 /* Disable l2 tunnel tag insertion */
7859 static int
7860 ixgbe_dev_l2_tunnel_insertion_disable
7861         (struct rte_eth_dev *dev,
7862          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7863 {
7864         int ret = 0;
7865
7866         switch (l2_tunnel->l2_tunnel_type) {
7867         case RTE_L2_TUNNEL_TYPE_E_TAG:
7868                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7869                 break;
7870         default:
7871                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7872                 ret = -EINVAL;
7873                 break;
7874         }
7875
7876         return ret;
7877 }
7878
7879 static int
7880 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7881                              bool en)
7882 {
7883         int ret = 0;
7884         uint32_t qde;
7885         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7886
7887         if (hw->mac.type != ixgbe_mac_X550 &&
7888             hw->mac.type != ixgbe_mac_X550EM_x &&
7889             hw->mac.type != ixgbe_mac_X550EM_a) {
7890                 return -ENOTSUP;
7891         }
7892
7893         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7894         if (en)
7895                 qde |= IXGBE_QDE_STRIP_TAG;
7896         else
7897                 qde &= ~IXGBE_QDE_STRIP_TAG;
7898         qde &= ~IXGBE_QDE_READ;
7899         qde |= IXGBE_QDE_WRITE;
7900         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7901
7902         return ret;
7903 }
7904
7905 /* Enable l2 tunnel tag stripping */
7906 static int
7907 ixgbe_dev_l2_tunnel_stripping_enable
7908         (struct rte_eth_dev *dev,
7909          enum rte_eth_tunnel_type l2_tunnel_type)
7910 {
7911         int ret = 0;
7912
7913         switch (l2_tunnel_type) {
7914         case RTE_L2_TUNNEL_TYPE_E_TAG:
7915                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7916                 break;
7917         default:
7918                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7919                 ret = -EINVAL;
7920                 break;
7921         }
7922
7923         return ret;
7924 }
7925
7926 /* Disable l2 tunnel tag stripping */
7927 static int
7928 ixgbe_dev_l2_tunnel_stripping_disable
7929         (struct rte_eth_dev *dev,
7930          enum rte_eth_tunnel_type l2_tunnel_type)
7931 {
7932         int ret = 0;
7933
7934         switch (l2_tunnel_type) {
7935         case RTE_L2_TUNNEL_TYPE_E_TAG:
7936                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7937                 break;
7938         default:
7939                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7940                 ret = -EINVAL;
7941                 break;
7942         }
7943
7944         return ret;
7945 }
7946
7947 /* Enable/disable l2 tunnel offload functions */
7948 static int
7949 ixgbe_dev_l2_tunnel_offload_set
7950         (struct rte_eth_dev *dev,
7951          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7952          uint32_t mask,
7953          uint8_t en)
7954 {
7955         int ret = 0;
7956
7957         if (l2_tunnel == NULL)
7958                 return -EINVAL;
7959
7960         ret = -EINVAL;
7961         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7962                 if (en)
7963                         ret = ixgbe_dev_l2_tunnel_enable(
7964                                 dev,
7965                                 l2_tunnel->l2_tunnel_type);
7966                 else
7967                         ret = ixgbe_dev_l2_tunnel_disable(
7968                                 dev,
7969                                 l2_tunnel->l2_tunnel_type);
7970         }
7971
7972         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7973                 if (en)
7974                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7975                                 dev,
7976                                 l2_tunnel);
7977                 else
7978                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7979                                 dev,
7980                                 l2_tunnel);
7981         }
7982
7983         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7984                 if (en)
7985                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7986                                 dev,
7987                                 l2_tunnel->l2_tunnel_type);
7988                 else
7989                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7990                                 dev,
7991                                 l2_tunnel->l2_tunnel_type);
7992         }
7993
7994         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7995                 if (en)
7996                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7997                                 dev,
7998                                 l2_tunnel->l2_tunnel_type);
7999                 else
8000                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8001                                 dev,
8002                                 l2_tunnel->l2_tunnel_type);
8003         }
8004
8005         return ret;
8006 }
8007
8008 static int
8009 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8010                         uint16_t port)
8011 {
8012         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8013         IXGBE_WRITE_FLUSH(hw);
8014
8015         return 0;
8016 }
8017
8018 /* There's only one register for VxLAN UDP port.
8019  * So, we cannot add several ports. Will update it.
8020  */
8021 static int
8022 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8023                      uint16_t port)
8024 {
8025         if (port == 0) {
8026                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8027                 return -EINVAL;
8028         }
8029
8030         return ixgbe_update_vxlan_port(hw, port);
8031 }
8032
8033 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8034  * UDP port, it must have a value.
8035  * So, will reset it to the original value 0.
8036  */
8037 static int
8038 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8039                      uint16_t port)
8040 {
8041         uint16_t cur_port;
8042
8043         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8044
8045         if (cur_port != port) {
8046                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8047                 return -EINVAL;
8048         }
8049
8050         return ixgbe_update_vxlan_port(hw, 0);
8051 }
8052
8053 /* Add UDP tunneling port */
8054 static int
8055 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8056                               struct rte_eth_udp_tunnel *udp_tunnel)
8057 {
8058         int ret = 0;
8059         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8060
8061         if (hw->mac.type != ixgbe_mac_X550 &&
8062             hw->mac.type != ixgbe_mac_X550EM_x &&
8063             hw->mac.type != ixgbe_mac_X550EM_a) {
8064                 return -ENOTSUP;
8065         }
8066
8067         if (udp_tunnel == NULL)
8068                 return -EINVAL;
8069
8070         switch (udp_tunnel->prot_type) {
8071         case RTE_TUNNEL_TYPE_VXLAN:
8072                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8073                 break;
8074
8075         case RTE_TUNNEL_TYPE_GENEVE:
8076         case RTE_TUNNEL_TYPE_TEREDO:
8077                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8078                 ret = -EINVAL;
8079                 break;
8080
8081         default:
8082                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8083                 ret = -EINVAL;
8084                 break;
8085         }
8086
8087         return ret;
8088 }
8089
8090 /* Remove UDP tunneling port */
8091 static int
8092 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8093                               struct rte_eth_udp_tunnel *udp_tunnel)
8094 {
8095         int ret = 0;
8096         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8097
8098         if (hw->mac.type != ixgbe_mac_X550 &&
8099             hw->mac.type != ixgbe_mac_X550EM_x &&
8100             hw->mac.type != ixgbe_mac_X550EM_a) {
8101                 return -ENOTSUP;
8102         }
8103
8104         if (udp_tunnel == NULL)
8105                 return -EINVAL;
8106
8107         switch (udp_tunnel->prot_type) {
8108         case RTE_TUNNEL_TYPE_VXLAN:
8109                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8110                 break;
8111         case RTE_TUNNEL_TYPE_GENEVE:
8112         case RTE_TUNNEL_TYPE_TEREDO:
8113                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8114                 ret = -EINVAL;
8115                 break;
8116         default:
8117                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8118                 ret = -EINVAL;
8119                 break;
8120         }
8121
8122         return ret;
8123 }
8124
8125 static void
8126 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8127 {
8128         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8129
8130         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8131 }
8132
8133 static void
8134 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8135 {
8136         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8137
8138         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8139 }
8140
8141 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8142 {
8143         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8144         u32 in_msg = 0;
8145
8146         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8147                 return;
8148
8149         /* PF reset VF event */
8150         if (in_msg == IXGBE_PF_CONTROL_MSG)
8151                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8152                                               NULL, NULL);
8153 }
8154
8155 static int
8156 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8157 {
8158         uint32_t eicr;
8159         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8160         struct ixgbe_interrupt *intr =
8161                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8162         ixgbevf_intr_disable(hw);
8163
8164         /* read-on-clear nic registers here */
8165         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8166         intr->flags = 0;
8167
8168         /* only one misc vector supported - mailbox */
8169         eicr &= IXGBE_VTEICR_MASK;
8170         if (eicr == IXGBE_MISC_VEC_ID)
8171                 intr->flags |= IXGBE_FLAG_MAILBOX;
8172
8173         return 0;
8174 }
8175
8176 static int
8177 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8178 {
8179         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8180         struct ixgbe_interrupt *intr =
8181                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8182
8183         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8184                 ixgbevf_mbx_process(dev);
8185                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8186         }
8187
8188         ixgbevf_intr_enable(hw);
8189
8190         return 0;
8191 }
8192
8193 static void
8194 ixgbevf_dev_interrupt_handler(void *param)
8195 {
8196         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8197
8198         ixgbevf_dev_interrupt_get_status(dev);
8199         ixgbevf_dev_interrupt_action(dev);
8200 }
8201
8202 /**
8203  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8204  *  @hw: pointer to hardware structure
8205  *
8206  *  Stops the transmit data path and waits for the HW to internally empty
8207  *  the Tx security block
8208  **/
8209 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8210 {
8211 #define IXGBE_MAX_SECTX_POLL 40
8212
8213         int i;
8214         int sectxreg;
8215
8216         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8217         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8218         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8219         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8220                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8221                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8222                         break;
8223                 /* Use interrupt-safe sleep just in case */
8224                 usec_delay(1000);
8225         }
8226
8227         /* For informational purposes only */
8228         if (i >= IXGBE_MAX_SECTX_POLL)
8229                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8230                          "path fully disabled.  Continuing with init.");
8231
8232         return IXGBE_SUCCESS;
8233 }
8234
8235 /**
8236  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8237  *  @hw: pointer to hardware structure
8238  *
8239  *  Enables the transmit data path.
8240  **/
8241 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8242 {
8243         uint32_t sectxreg;
8244
8245         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8246         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8247         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8248         IXGBE_WRITE_FLUSH(hw);
8249
8250         return IXGBE_SUCCESS;
8251 }
8252
8253 /* restore n-tuple filter */
8254 static inline void
8255 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8256 {
8257         struct ixgbe_filter_info *filter_info =
8258                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8259         struct ixgbe_5tuple_filter *node;
8260
8261         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8262                 ixgbe_inject_5tuple_filter(dev, node);
8263         }
8264 }
8265
8266 /* restore ethernet type filter */
8267 static inline void
8268 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8269 {
8270         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8271         struct ixgbe_filter_info *filter_info =
8272                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8273         int i;
8274
8275         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8276                 if (filter_info->ethertype_mask & (1 << i)) {
8277                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8278                                         filter_info->ethertype_filters[i].etqf);
8279                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8280                                         filter_info->ethertype_filters[i].etqs);
8281                         IXGBE_WRITE_FLUSH(hw);
8282                 }
8283         }
8284 }
8285
8286 /* restore SYN filter */
8287 static inline void
8288 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8289 {
8290         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8291         struct ixgbe_filter_info *filter_info =
8292                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8293         uint32_t synqf;
8294
8295         synqf = filter_info->syn_info;
8296
8297         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8298                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8299                 IXGBE_WRITE_FLUSH(hw);
8300         }
8301 }
8302
8303 /* restore L2 tunnel filter */
8304 static inline void
8305 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8306 {
8307         struct ixgbe_l2_tn_info *l2_tn_info =
8308                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8309         struct ixgbe_l2_tn_filter *node;
8310         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8311
8312         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8313                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8314                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8315                 l2_tn_conf.pool           = node->pool;
8316                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8317         }
8318 }
8319
8320 /* restore rss filter */
8321 static inline void
8322 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8323 {
8324         struct ixgbe_filter_info *filter_info =
8325                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8326
8327         if (filter_info->rss_info.num)
8328                 ixgbe_config_rss_filter(dev,
8329                         &filter_info->rss_info, TRUE);
8330 }
8331
8332 static int
8333 ixgbe_filter_restore(struct rte_eth_dev *dev)
8334 {
8335         ixgbe_ntuple_filter_restore(dev);
8336         ixgbe_ethertype_filter_restore(dev);
8337         ixgbe_syn_filter_restore(dev);
8338         ixgbe_fdir_filter_restore(dev);
8339         ixgbe_l2_tn_filter_restore(dev);
8340         ixgbe_rss_filter_restore(dev);
8341
8342         return 0;
8343 }
8344
8345 static void
8346 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8347 {
8348         struct ixgbe_l2_tn_info *l2_tn_info =
8349                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8350         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8351
8352         if (l2_tn_info->e_tag_en)
8353                 (void)ixgbe_e_tag_enable(hw);
8354
8355         if (l2_tn_info->e_tag_fwd_en)
8356                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8357
8358         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8359 }
8360
8361 /* remove all the n-tuple filters */
8362 void
8363 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8364 {
8365         struct ixgbe_filter_info *filter_info =
8366                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8367         struct ixgbe_5tuple_filter *p_5tuple;
8368
8369         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8370                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8371 }
8372
8373 /* remove all the ether type filters */
8374 void
8375 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8376 {
8377         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8378         struct ixgbe_filter_info *filter_info =
8379                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8380         int i;
8381
8382         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8383                 if (filter_info->ethertype_mask & (1 << i) &&
8384                     !filter_info->ethertype_filters[i].conf) {
8385                         (void)ixgbe_ethertype_filter_remove(filter_info,
8386                                                             (uint8_t)i);
8387                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8388                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8389                         IXGBE_WRITE_FLUSH(hw);
8390                 }
8391         }
8392 }
8393
8394 /* remove the SYN filter */
8395 void
8396 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8397 {
8398         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8399         struct ixgbe_filter_info *filter_info =
8400                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8401
8402         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8403                 filter_info->syn_info = 0;
8404
8405                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8406                 IXGBE_WRITE_FLUSH(hw);
8407         }
8408 }
8409
8410 /* remove all the L2 tunnel filters */
8411 int
8412 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8413 {
8414         struct ixgbe_l2_tn_info *l2_tn_info =
8415                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8416         struct ixgbe_l2_tn_filter *l2_tn_filter;
8417         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8418         int ret = 0;
8419
8420         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8421                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8422                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8423                 l2_tn_conf.pool           = l2_tn_filter->pool;
8424                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8425                 if (ret < 0)
8426                         return ret;
8427         }
8428
8429         return 0;
8430 }
8431
8432 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8433 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8434 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8435 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8436 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8437 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8438
8439 RTE_INIT(ixgbe_init_log);
8440 static void
8441 ixgbe_init_log(void)
8442 {
8443         ixgbe_logtype_init = rte_log_register("pmd.ixgbe.init");
8444         if (ixgbe_logtype_init >= 0)
8445                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8446         ixgbe_logtype_driver = rte_log_register("pmd.ixgbe.driver");
8447         if (ixgbe_logtype_driver >= 0)
8448                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8449 }