4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_ethdev_pci.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
63 #include <rte_hash_crc.h>
64 #include <rte_security_driver.h>
66 #include "ixgbe_logs.h"
67 #include "base/ixgbe_api.h"
68 #include "base/ixgbe_vf.h"
69 #include "base/ixgbe_common.h"
70 #include "ixgbe_ethdev.h"
71 #include "ixgbe_bypass.h"
72 #include "ixgbe_rxtx.h"
73 #include "base/ixgbe_type.h"
74 #include "base/ixgbe_phy.h"
75 #include "ixgbe_regs.h"
78 * High threshold controlling when to start sending XOFF frames. Must be at
79 * least 8 bytes less than receive packet buffer size. This value is in units
82 #define IXGBE_FC_HI 0x80
85 * Low threshold controlling when to start sending XON frames. This value is
86 * in units of 1024 bytes.
88 #define IXGBE_FC_LO 0x40
90 /* Default minimum inter-interrupt interval for EITR configuration */
91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
93 /* Timer value included in XOFF frames. */
94 #define IXGBE_FC_PAUSE 0x680
96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
97 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
98 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
100 #define IXGBE_MMW_SIZE_DEFAULT 0x4
101 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
102 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
105 * Default values for RX/TX configuration
107 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
108 #define IXGBE_DEFAULT_RX_PTHRESH 8
109 #define IXGBE_DEFAULT_RX_HTHRESH 8
110 #define IXGBE_DEFAULT_RX_WTHRESH 0
112 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
113 #define IXGBE_DEFAULT_TX_PTHRESH 32
114 #define IXGBE_DEFAULT_TX_HTHRESH 0
115 #define IXGBE_DEFAULT_TX_WTHRESH 0
116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
118 /* Bit shift and mask */
119 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
120 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
121 #define IXGBE_8_BIT_WIDTH CHAR_BIT
122 #define IXGBE_8_BIT_MASK UINT8_MAX
124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
128 #define IXGBE_HKEY_MAX_INDEX 10
130 /* Additional timesync values. */
131 #define NSEC_PER_SEC 1000000000L
132 #define IXGBE_INCVAL_10GB 0x66666666
133 #define IXGBE_INCVAL_1GB 0x40000000
134 #define IXGBE_INCVAL_100 0x50000000
135 #define IXGBE_INCVAL_SHIFT_10GB 28
136 #define IXGBE_INCVAL_SHIFT_1GB 24
137 #define IXGBE_INCVAL_SHIFT_100 21
138 #define IXGBE_INCVAL_SHIFT_82599 7
139 #define IXGBE_INCPER_SHIFT_82599 24
141 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
143 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
145 #define DEFAULT_ETAG_ETYPE 0x893f
146 #define IXGBE_ETAG_ETYPE 0x00005084
147 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
148 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
149 #define IXGBE_RAH_ADTYPE 0x40000000
150 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
151 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
154 #define IXGBE_QDE_STRIP_TAG 0x00000004
155 #define IXGBE_VTEICR_MASK 0x07
157 #define IXGBE_EXVET_VET_EXT_SHIFT 16
158 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
162 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
163 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
164 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
165 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
166 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
167 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
168 static int ixgbe_dev_start(struct rte_eth_dev *dev);
169 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
170 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
171 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
172 static void ixgbe_dev_close(struct rte_eth_dev *dev);
173 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
174 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
175 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
176 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
177 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
178 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
179 int wait_to_complete);
180 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
181 struct rte_eth_stats *stats);
182 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
183 struct rte_eth_xstat *xstats, unsigned n);
184 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
185 struct rte_eth_xstat *xstats, unsigned n);
187 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
188 uint64_t *values, unsigned int n);
189 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
190 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
191 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
192 struct rte_eth_xstat_name *xstats_names,
194 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
195 struct rte_eth_xstat_name *xstats_names, unsigned limit);
196 static int ixgbe_dev_xstats_get_names_by_id(
197 struct rte_eth_dev *dev,
198 struct rte_eth_xstat_name *xstats_names,
201 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
205 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
207 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
208 struct rte_eth_dev_info *dev_info);
209 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
210 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
211 struct rte_eth_dev_info *dev_info);
212 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
214 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
215 uint16_t vlan_id, int on);
216 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
217 enum rte_vlan_type vlan_type,
219 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
220 uint16_t queue, bool on);
221 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
223 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
224 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
225 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
226 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
227 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
229 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
230 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
231 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
232 struct rte_eth_fc_conf *fc_conf);
233 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
234 struct rte_eth_fc_conf *fc_conf);
235 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
236 struct rte_eth_pfc_conf *pfc_conf);
237 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
238 struct rte_eth_rss_reta_entry64 *reta_conf,
240 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
241 struct rte_eth_rss_reta_entry64 *reta_conf,
243 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
244 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
245 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
246 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
247 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
248 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
249 struct rte_intr_handle *handle);
250 static void ixgbe_dev_interrupt_handler(void *param);
251 static void ixgbe_dev_interrupt_delayed_handler(void *param);
252 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
253 uint32_t index, uint32_t pool);
254 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
255 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
256 struct ether_addr *mac_addr);
257 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
258 static bool is_device_supported(struct rte_eth_dev *dev,
259 struct rte_pci_driver *drv);
261 /* For Virtual Function support */
262 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
263 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
264 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
265 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
266 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
267 int wait_to_complete);
268 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
269 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
270 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
271 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
272 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
273 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
274 struct rte_eth_stats *stats);
275 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
276 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
277 uint16_t vlan_id, int on);
278 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
279 uint16_t queue, int on);
280 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
281 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
282 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
284 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
286 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
287 uint8_t queue, uint8_t msix_vector);
288 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
289 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
290 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
292 /* For Eth VMDQ APIs support */
293 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
294 ether_addr * mac_addr, uint8_t on);
295 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
296 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
297 struct rte_eth_mirror_conf *mirror_conf,
298 uint8_t rule_id, uint8_t on);
299 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
301 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
303 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
305 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
306 uint8_t queue, uint8_t msix_vector);
307 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
309 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
310 struct ether_addr *mac_addr,
311 uint32_t index, uint32_t pool);
312 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
313 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
314 struct ether_addr *mac_addr);
315 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
316 struct rte_eth_syn_filter *filter);
317 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
318 enum rte_filter_op filter_op,
320 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
321 struct ixgbe_5tuple_filter *filter);
322 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
323 struct ixgbe_5tuple_filter *filter);
324 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
325 enum rte_filter_op filter_op,
327 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
328 struct rte_eth_ntuple_filter *filter);
329 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
330 enum rte_filter_op filter_op,
332 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
333 struct rte_eth_ethertype_filter *filter);
334 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
335 enum rte_filter_type filter_type,
336 enum rte_filter_op filter_op,
338 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
340 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
341 struct ether_addr *mc_addr_set,
342 uint32_t nb_mc_addr);
343 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
344 struct rte_eth_dcb_info *dcb_info);
346 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
347 static int ixgbe_get_regs(struct rte_eth_dev *dev,
348 struct rte_dev_reg_info *regs);
349 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
350 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
351 struct rte_dev_eeprom_info *eeprom);
352 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
353 struct rte_dev_eeprom_info *eeprom);
355 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
356 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
357 struct rte_dev_reg_info *regs);
359 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
360 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
361 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
362 struct timespec *timestamp,
364 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
365 struct timespec *timestamp);
366 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
367 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
368 struct timespec *timestamp);
369 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
370 const struct timespec *timestamp);
371 static void ixgbevf_dev_interrupt_handler(void *param);
373 static int ixgbe_dev_l2_tunnel_eth_type_conf
374 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
375 static int ixgbe_dev_l2_tunnel_offload_set
376 (struct rte_eth_dev *dev,
377 struct rte_eth_l2_tunnel_conf *l2_tunnel,
380 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
381 enum rte_filter_op filter_op,
384 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
385 struct rte_eth_udp_tunnel *udp_tunnel);
386 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
387 struct rte_eth_udp_tunnel *udp_tunnel);
388 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
389 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
392 * Define VF Stats MACRO for Non "cleared on read" register
394 #define UPDATE_VF_STAT(reg, last, cur) \
396 uint32_t latest = IXGBE_READ_REG(hw, reg); \
397 cur += (latest - last) & UINT_MAX; \
401 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
403 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
404 u64 new_msb = IXGBE_READ_REG(hw, msb); \
405 u64 latest = ((new_msb << 32) | new_lsb); \
406 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
410 #define IXGBE_SET_HWSTRIP(h, q) do {\
411 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
412 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
413 (h)->bitmap[idx] |= 1 << bit;\
416 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
417 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
418 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
419 (h)->bitmap[idx] &= ~(1 << bit);\
422 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
423 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
424 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
425 (r) = (h)->bitmap[idx] >> bit & 1;\
429 * The set of PCI devices this driver supports
431 static const struct rte_pci_id pci_id_ixgbe_map[] = {
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
480 #ifdef RTE_LIBRTE_IXGBE_BYPASS
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
483 { .vendor_id = 0, /* sentinel */ },
487 * The set of PCI devices this driver supports (for 82599 VF)
489 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
490 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
491 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
492 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
493 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
494 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
495 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
496 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
497 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
498 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
499 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
500 { .vendor_id = 0, /* sentinel */ },
503 static const struct rte_eth_desc_lim rx_desc_lim = {
504 .nb_max = IXGBE_MAX_RING_DESC,
505 .nb_min = IXGBE_MIN_RING_DESC,
506 .nb_align = IXGBE_RXD_ALIGN,
509 static const struct rte_eth_desc_lim tx_desc_lim = {
510 .nb_max = IXGBE_MAX_RING_DESC,
511 .nb_min = IXGBE_MIN_RING_DESC,
512 .nb_align = IXGBE_TXD_ALIGN,
513 .nb_seg_max = IXGBE_TX_MAX_SEG,
514 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
517 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
518 .dev_configure = ixgbe_dev_configure,
519 .dev_start = ixgbe_dev_start,
520 .dev_stop = ixgbe_dev_stop,
521 .dev_set_link_up = ixgbe_dev_set_link_up,
522 .dev_set_link_down = ixgbe_dev_set_link_down,
523 .dev_close = ixgbe_dev_close,
524 .dev_reset = ixgbe_dev_reset,
525 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
526 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
527 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
528 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
529 .link_update = ixgbe_dev_link_update,
530 .stats_get = ixgbe_dev_stats_get,
531 .xstats_get = ixgbe_dev_xstats_get,
532 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
533 .stats_reset = ixgbe_dev_stats_reset,
534 .xstats_reset = ixgbe_dev_xstats_reset,
535 .xstats_get_names = ixgbe_dev_xstats_get_names,
536 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
537 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
538 .fw_version_get = ixgbe_fw_version_get,
539 .dev_infos_get = ixgbe_dev_info_get,
540 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
541 .mtu_set = ixgbe_dev_mtu_set,
542 .vlan_filter_set = ixgbe_vlan_filter_set,
543 .vlan_tpid_set = ixgbe_vlan_tpid_set,
544 .vlan_offload_set = ixgbe_vlan_offload_set,
545 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
546 .rx_queue_start = ixgbe_dev_rx_queue_start,
547 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
548 .tx_queue_start = ixgbe_dev_tx_queue_start,
549 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
550 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
551 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
552 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
553 .rx_queue_release = ixgbe_dev_rx_queue_release,
554 .rx_queue_count = ixgbe_dev_rx_queue_count,
555 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
556 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
557 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
558 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
559 .tx_queue_release = ixgbe_dev_tx_queue_release,
560 .dev_led_on = ixgbe_dev_led_on,
561 .dev_led_off = ixgbe_dev_led_off,
562 .flow_ctrl_get = ixgbe_flow_ctrl_get,
563 .flow_ctrl_set = ixgbe_flow_ctrl_set,
564 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
565 .mac_addr_add = ixgbe_add_rar,
566 .mac_addr_remove = ixgbe_remove_rar,
567 .mac_addr_set = ixgbe_set_default_mac_addr,
568 .uc_hash_table_set = ixgbe_uc_hash_table_set,
569 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
570 .mirror_rule_set = ixgbe_mirror_rule_set,
571 .mirror_rule_reset = ixgbe_mirror_rule_reset,
572 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
573 .reta_update = ixgbe_dev_rss_reta_update,
574 .reta_query = ixgbe_dev_rss_reta_query,
575 .rss_hash_update = ixgbe_dev_rss_hash_update,
576 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
577 .filter_ctrl = ixgbe_dev_filter_ctrl,
578 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
579 .rxq_info_get = ixgbe_rxq_info_get,
580 .txq_info_get = ixgbe_txq_info_get,
581 .timesync_enable = ixgbe_timesync_enable,
582 .timesync_disable = ixgbe_timesync_disable,
583 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
584 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
585 .get_reg = ixgbe_get_regs,
586 .get_eeprom_length = ixgbe_get_eeprom_length,
587 .get_eeprom = ixgbe_get_eeprom,
588 .set_eeprom = ixgbe_set_eeprom,
589 .get_dcb_info = ixgbe_dev_get_dcb_info,
590 .timesync_adjust_time = ixgbe_timesync_adjust_time,
591 .timesync_read_time = ixgbe_timesync_read_time,
592 .timesync_write_time = ixgbe_timesync_write_time,
593 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
594 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
595 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
596 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
597 .tm_ops_get = ixgbe_tm_ops_get,
601 * dev_ops for virtual function, bare necessities for basic vf
602 * operation have been implemented
604 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
605 .dev_configure = ixgbevf_dev_configure,
606 .dev_start = ixgbevf_dev_start,
607 .dev_stop = ixgbevf_dev_stop,
608 .link_update = ixgbevf_dev_link_update,
609 .stats_get = ixgbevf_dev_stats_get,
610 .xstats_get = ixgbevf_dev_xstats_get,
611 .stats_reset = ixgbevf_dev_stats_reset,
612 .xstats_reset = ixgbevf_dev_stats_reset,
613 .xstats_get_names = ixgbevf_dev_xstats_get_names,
614 .dev_close = ixgbevf_dev_close,
615 .dev_reset = ixgbevf_dev_reset,
616 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
617 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
618 .dev_infos_get = ixgbevf_dev_info_get,
619 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
620 .mtu_set = ixgbevf_dev_set_mtu,
621 .vlan_filter_set = ixgbevf_vlan_filter_set,
622 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
623 .vlan_offload_set = ixgbevf_vlan_offload_set,
624 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
625 .rx_queue_release = ixgbe_dev_rx_queue_release,
626 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
627 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
628 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
629 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
630 .tx_queue_release = ixgbe_dev_tx_queue_release,
631 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
632 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
633 .mac_addr_add = ixgbevf_add_mac_addr,
634 .mac_addr_remove = ixgbevf_remove_mac_addr,
635 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
636 .rxq_info_get = ixgbe_rxq_info_get,
637 .txq_info_get = ixgbe_txq_info_get,
638 .mac_addr_set = ixgbevf_set_default_mac_addr,
639 .get_reg = ixgbevf_get_regs,
640 .reta_update = ixgbe_dev_rss_reta_update,
641 .reta_query = ixgbe_dev_rss_reta_query,
642 .rss_hash_update = ixgbe_dev_rss_hash_update,
643 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
646 /* store statistics names and its offset in stats structure */
647 struct rte_ixgbe_xstats_name_off {
648 char name[RTE_ETH_XSTATS_NAME_SIZE];
652 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
653 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
654 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
655 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
656 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
657 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
658 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
659 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
660 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
661 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
662 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
663 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
664 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
665 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
666 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
667 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
669 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
671 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
672 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
673 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
674 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
675 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
676 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
677 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
678 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
679 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
680 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
681 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
682 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
683 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
684 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
685 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
686 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
687 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
689 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
691 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
692 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
693 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
694 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
696 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
698 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
700 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
702 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
704 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
706 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
709 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
710 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
711 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
713 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
714 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
715 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
716 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
717 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
719 {"rx_fcoe_no_direct_data_placement_ext_buff",
720 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
722 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
724 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
726 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
728 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
730 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
733 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
734 sizeof(rte_ixgbe_stats_strings[0]))
736 /* MACsec statistics */
737 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
738 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
740 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
741 out_pkts_encrypted)},
742 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
743 out_pkts_protected)},
744 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
745 out_octets_encrypted)},
746 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
747 out_octets_protected)},
748 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
750 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
752 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
754 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
755 in_pkts_unknownsci)},
756 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
757 in_octets_decrypted)},
758 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
759 in_octets_validated)},
760 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
762 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
764 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
766 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
768 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
770 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
772 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
774 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
775 in_pkts_notusingsa)},
778 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
779 sizeof(rte_ixgbe_macsec_strings[0]))
781 /* Per-queue statistics */
782 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
783 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
784 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
785 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
786 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
789 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
790 sizeof(rte_ixgbe_rxq_strings[0]))
791 #define IXGBE_NB_RXQ_PRIO_VALUES 8
793 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
794 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
795 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
796 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
800 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
801 sizeof(rte_ixgbe_txq_strings[0]))
802 #define IXGBE_NB_TXQ_PRIO_VALUES 8
804 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
805 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
808 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
809 sizeof(rte_ixgbevf_stats_strings[0]))
812 * Atomically reads the link status information from global
813 * structure rte_eth_dev.
816 * - Pointer to the structure rte_eth_dev to read from.
817 * - Pointer to the buffer to be saved with the link status.
820 * - On success, zero.
821 * - On failure, negative value.
824 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
825 struct rte_eth_link *link)
827 struct rte_eth_link *dst = link;
828 struct rte_eth_link *src = &(dev->data->dev_link);
830 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
831 *(uint64_t *)src) == 0)
838 * Atomically writes the link status information into global
839 * structure rte_eth_dev.
842 * - Pointer to the structure rte_eth_dev to read from.
843 * - Pointer to the buffer to be saved with the link status.
846 * - On success, zero.
847 * - On failure, negative value.
850 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
851 struct rte_eth_link *link)
853 struct rte_eth_link *dst = &(dev->data->dev_link);
854 struct rte_eth_link *src = link;
856 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
857 *(uint64_t *)src) == 0)
864 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
867 ixgbe_is_sfp(struct ixgbe_hw *hw)
869 switch (hw->phy.type) {
870 case ixgbe_phy_sfp_avago:
871 case ixgbe_phy_sfp_ftl:
872 case ixgbe_phy_sfp_intel:
873 case ixgbe_phy_sfp_unknown:
874 case ixgbe_phy_sfp_passive_tyco:
875 case ixgbe_phy_sfp_passive_unknown:
882 static inline int32_t
883 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
888 status = ixgbe_reset_hw(hw);
890 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
891 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
892 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
893 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
894 IXGBE_WRITE_FLUSH(hw);
896 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
897 status = IXGBE_SUCCESS;
902 ixgbe_enable_intr(struct rte_eth_dev *dev)
904 struct ixgbe_interrupt *intr =
905 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
906 struct ixgbe_hw *hw =
907 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
909 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
910 IXGBE_WRITE_FLUSH(hw);
914 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
917 ixgbe_disable_intr(struct ixgbe_hw *hw)
919 PMD_INIT_FUNC_TRACE();
921 if (hw->mac.type == ixgbe_mac_82598EB) {
922 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
924 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
925 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
926 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
928 IXGBE_WRITE_FLUSH(hw);
932 * This function resets queue statistics mapping registers.
933 * From Niantic datasheet, Initialization of Statistics section:
934 * "...if software requires the queue counters, the RQSMR and TQSM registers
935 * must be re-programmed following a device reset.
938 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
942 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
943 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
944 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
950 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
955 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
956 #define NB_QMAP_FIELDS_PER_QSM_REG 4
957 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
959 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
960 struct ixgbe_stat_mapping_registers *stat_mappings =
961 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
962 uint32_t qsmr_mask = 0;
963 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
967 if ((hw->mac.type != ixgbe_mac_82599EB) &&
968 (hw->mac.type != ixgbe_mac_X540) &&
969 (hw->mac.type != ixgbe_mac_X550) &&
970 (hw->mac.type != ixgbe_mac_X550EM_x) &&
971 (hw->mac.type != ixgbe_mac_X550EM_a))
974 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
975 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
978 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
979 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
980 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
983 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
985 /* Now clear any previous stat_idx set */
986 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
988 stat_mappings->tqsm[n] &= ~clearing_mask;
990 stat_mappings->rqsmr[n] &= ~clearing_mask;
992 q_map = (uint32_t)stat_idx;
993 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
994 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
996 stat_mappings->tqsm[n] |= qsmr_mask;
998 stat_mappings->rqsmr[n] |= qsmr_mask;
1000 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1001 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1002 queue_id, stat_idx);
1003 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1004 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1006 /* Now write the mapping in the appropriate register */
1008 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1009 stat_mappings->rqsmr[n], n);
1010 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1012 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1013 stat_mappings->tqsm[n], n);
1014 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1020 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1022 struct ixgbe_stat_mapping_registers *stat_mappings =
1023 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1024 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1027 /* write whatever was in stat mapping table to the NIC */
1028 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1030 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1033 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1038 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1041 struct ixgbe_dcb_tc_config *tc;
1042 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1044 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1045 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1046 for (i = 0; i < dcb_max_tc; i++) {
1047 tc = &dcb_config->tc_config[i];
1048 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1049 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1050 (uint8_t)(100/dcb_max_tc + (i & 1));
1051 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1052 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1053 (uint8_t)(100/dcb_max_tc + (i & 1));
1054 tc->pfc = ixgbe_dcb_pfc_disabled;
1057 /* Initialize default user to priority mapping, UPx->TC0 */
1058 tc = &dcb_config->tc_config[0];
1059 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1060 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1061 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1062 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1063 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1065 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1066 dcb_config->pfc_mode_enable = false;
1067 dcb_config->vt_mode = true;
1068 dcb_config->round_robin_enable = false;
1069 /* support all DCB capabilities in 82599 */
1070 dcb_config->support.capabilities = 0xFF;
1072 /*we only support 4 Tcs for X540, X550 */
1073 if (hw->mac.type == ixgbe_mac_X540 ||
1074 hw->mac.type == ixgbe_mac_X550 ||
1075 hw->mac.type == ixgbe_mac_X550EM_x ||
1076 hw->mac.type == ixgbe_mac_X550EM_a) {
1077 dcb_config->num_tcs.pg_tcs = 4;
1078 dcb_config->num_tcs.pfc_tcs = 4;
1083 * Ensure that all locks are released before first NVM or PHY access
1086 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1091 * Phy lock should not fail in this early stage. If this is the case,
1092 * it is due to an improper exit of the application.
1093 * So force the release of the faulty lock. Release of common lock
1094 * is done automatically by swfw_sync function.
1096 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1097 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1098 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1100 ixgbe_release_swfw_semaphore(hw, mask);
1103 * These ones are more tricky since they are common to all ports; but
1104 * swfw_sync retries last long enough (1s) to be almost sure that if
1105 * lock can not be taken it is due to an improper lock of the
1108 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1109 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1110 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1112 ixgbe_release_swfw_semaphore(hw, mask);
1116 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1117 * It returns 0 on success.
1120 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1122 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1123 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1124 struct ixgbe_hw *hw =
1125 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1126 struct ixgbe_vfta *shadow_vfta =
1127 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1128 struct ixgbe_hwstrip *hwstrip =
1129 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1130 struct ixgbe_dcb_config *dcb_config =
1131 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1132 struct ixgbe_filter_info *filter_info =
1133 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1134 struct ixgbe_bw_conf *bw_conf =
1135 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1140 PMD_INIT_FUNC_TRACE();
1142 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1143 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1144 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1145 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1148 * For secondary processes, we don't initialise any further as primary
1149 * has already done this work. Only check we don't need a different
1150 * RX and TX function.
1152 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1153 struct ixgbe_tx_queue *txq;
1154 /* TX queue function in primary, set by last queue initialized
1155 * Tx queue may not initialized by primary process
1157 if (eth_dev->data->tx_queues) {
1158 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1159 ixgbe_set_tx_function(eth_dev, txq);
1161 /* Use default TX function if we get here */
1162 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1163 "Using default TX function.");
1166 ixgbe_set_rx_function(eth_dev);
1171 /* Initialize security_ctx only for primary process*/
1172 eth_dev->security_ctx = ixgbe_ipsec_ctx_create(eth_dev);
1173 if (eth_dev->security_ctx == NULL)
1176 rte_eth_copy_pci_info(eth_dev, pci_dev);
1178 /* Vendor and Device ID need to be set before init of shared code */
1179 hw->device_id = pci_dev->id.device_id;
1180 hw->vendor_id = pci_dev->id.vendor_id;
1181 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1182 hw->allow_unsupported_sfp = 1;
1184 /* Initialize the shared code (base driver) */
1185 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1186 diag = ixgbe_bypass_init_shared_code(hw);
1188 diag = ixgbe_init_shared_code(hw);
1189 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1191 if (diag != IXGBE_SUCCESS) {
1192 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1196 /* pick up the PCI bus settings for reporting later */
1197 ixgbe_get_bus_info(hw);
1199 /* Unlock any pending hardware semaphore */
1200 ixgbe_swfw_lock_reset(hw);
1202 /* Initialize DCB configuration*/
1203 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1204 ixgbe_dcb_init(hw, dcb_config);
1205 /* Get Hardware Flow Control setting */
1206 hw->fc.requested_mode = ixgbe_fc_full;
1207 hw->fc.current_mode = ixgbe_fc_full;
1208 hw->fc.pause_time = IXGBE_FC_PAUSE;
1209 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1210 hw->fc.low_water[i] = IXGBE_FC_LO;
1211 hw->fc.high_water[i] = IXGBE_FC_HI;
1213 hw->fc.send_xon = 1;
1215 /* Make sure we have a good EEPROM before we read from it */
1216 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1217 if (diag != IXGBE_SUCCESS) {
1218 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1222 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1223 diag = ixgbe_bypass_init_hw(hw);
1225 diag = ixgbe_init_hw(hw);
1226 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1229 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1230 * is called too soon after the kernel driver unbinding/binding occurs.
1231 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1232 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1233 * also called. See ixgbe_identify_phy_82599(). The reason for the
1234 * failure is not known, and only occuts when virtualisation features
1235 * are disabled in the bios. A delay of 100ms was found to be enough by
1236 * trial-and-error, and is doubled to be safe.
1238 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1240 diag = ixgbe_init_hw(hw);
1243 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1244 diag = IXGBE_SUCCESS;
1246 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1247 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1248 "LOM. Please be aware there may be issues associated "
1249 "with your hardware.");
1250 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1251 "please contact your Intel or hardware representative "
1252 "who provided you with this hardware.");
1253 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1254 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1256 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1260 /* Reset the hw statistics */
1261 ixgbe_dev_stats_reset(eth_dev);
1263 /* disable interrupt */
1264 ixgbe_disable_intr(hw);
1266 /* reset mappings for queue statistics hw counters*/
1267 ixgbe_reset_qstat_mappings(hw);
1269 /* Allocate memory for storing MAC addresses */
1270 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1271 hw->mac.num_rar_entries, 0);
1272 if (eth_dev->data->mac_addrs == NULL) {
1274 "Failed to allocate %u bytes needed to store "
1276 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1279 /* Copy the permanent MAC address */
1280 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1281 ð_dev->data->mac_addrs[0]);
1283 /* Allocate memory for storing hash filter MAC addresses */
1284 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1285 IXGBE_VMDQ_NUM_UC_MAC, 0);
1286 if (eth_dev->data->hash_mac_addrs == NULL) {
1288 "Failed to allocate %d bytes needed to store MAC addresses",
1289 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1293 /* initialize the vfta */
1294 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1296 /* initialize the hw strip bitmap*/
1297 memset(hwstrip, 0, sizeof(*hwstrip));
1299 /* initialize PF if max_vfs not zero */
1300 ixgbe_pf_host_init(eth_dev);
1302 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1303 /* let hardware know driver is loaded */
1304 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1305 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1306 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1307 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1308 IXGBE_WRITE_FLUSH(hw);
1310 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1311 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1312 (int) hw->mac.type, (int) hw->phy.type,
1313 (int) hw->phy.sfp_type);
1315 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1316 (int) hw->mac.type, (int) hw->phy.type);
1318 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1319 eth_dev->data->port_id, pci_dev->id.vendor_id,
1320 pci_dev->id.device_id);
1322 rte_intr_callback_register(intr_handle,
1323 ixgbe_dev_interrupt_handler, eth_dev);
1325 /* enable uio/vfio intr/eventfd mapping */
1326 rte_intr_enable(intr_handle);
1328 /* enable support intr */
1329 ixgbe_enable_intr(eth_dev);
1331 /* initialize filter info */
1332 memset(filter_info, 0,
1333 sizeof(struct ixgbe_filter_info));
1335 /* initialize 5tuple filter list */
1336 TAILQ_INIT(&filter_info->fivetuple_list);
1338 /* initialize flow director filter list & hash */
1339 ixgbe_fdir_filter_init(eth_dev);
1341 /* initialize l2 tunnel filter list & hash */
1342 ixgbe_l2_tn_filter_init(eth_dev);
1344 /* initialize flow filter lists */
1345 ixgbe_filterlist_init();
1347 /* initialize bandwidth configuration info */
1348 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1350 /* initialize Traffic Manager configuration */
1351 ixgbe_tm_conf_init(eth_dev);
1357 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1359 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1360 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1361 struct ixgbe_hw *hw;
1363 PMD_INIT_FUNC_TRACE();
1365 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1368 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1370 if (hw->adapter_stopped == 0)
1371 ixgbe_dev_close(eth_dev);
1373 eth_dev->dev_ops = NULL;
1374 eth_dev->rx_pkt_burst = NULL;
1375 eth_dev->tx_pkt_burst = NULL;
1377 /* Unlock any pending hardware semaphore */
1378 ixgbe_swfw_lock_reset(hw);
1380 /* disable uio intr before callback unregister */
1381 rte_intr_disable(intr_handle);
1382 rte_intr_callback_unregister(intr_handle,
1383 ixgbe_dev_interrupt_handler, eth_dev);
1385 /* uninitialize PF if max_vfs not zero */
1386 ixgbe_pf_host_uninit(eth_dev);
1388 rte_free(eth_dev->data->mac_addrs);
1389 eth_dev->data->mac_addrs = NULL;
1391 rte_free(eth_dev->data->hash_mac_addrs);
1392 eth_dev->data->hash_mac_addrs = NULL;
1394 /* remove all the fdir filters & hash */
1395 ixgbe_fdir_filter_uninit(eth_dev);
1397 /* remove all the L2 tunnel filters & hash */
1398 ixgbe_l2_tn_filter_uninit(eth_dev);
1400 /* Remove all ntuple filters of the device */
1401 ixgbe_ntuple_filter_uninit(eth_dev);
1403 /* clear all the filters list */
1404 ixgbe_filterlist_flush();
1406 /* Remove all Traffic Manager configuration */
1407 ixgbe_tm_conf_uninit(eth_dev);
1409 rte_free(eth_dev->security_ctx);
1414 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1416 struct ixgbe_filter_info *filter_info =
1417 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1418 struct ixgbe_5tuple_filter *p_5tuple;
1420 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1421 TAILQ_REMOVE(&filter_info->fivetuple_list,
1426 memset(filter_info->fivetuple_mask, 0,
1427 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1432 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1434 struct ixgbe_hw_fdir_info *fdir_info =
1435 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1436 struct ixgbe_fdir_filter *fdir_filter;
1438 if (fdir_info->hash_map)
1439 rte_free(fdir_info->hash_map);
1440 if (fdir_info->hash_handle)
1441 rte_hash_free(fdir_info->hash_handle);
1443 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1444 TAILQ_REMOVE(&fdir_info->fdir_list,
1447 rte_free(fdir_filter);
1453 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1455 struct ixgbe_l2_tn_info *l2_tn_info =
1456 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1457 struct ixgbe_l2_tn_filter *l2_tn_filter;
1459 if (l2_tn_info->hash_map)
1460 rte_free(l2_tn_info->hash_map);
1461 if (l2_tn_info->hash_handle)
1462 rte_hash_free(l2_tn_info->hash_handle);
1464 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1465 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1468 rte_free(l2_tn_filter);
1474 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1476 struct ixgbe_hw_fdir_info *fdir_info =
1477 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1478 char fdir_hash_name[RTE_HASH_NAMESIZE];
1479 struct rte_hash_parameters fdir_hash_params = {
1480 .name = fdir_hash_name,
1481 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1482 .key_len = sizeof(union ixgbe_atr_input),
1483 .hash_func = rte_hash_crc,
1484 .hash_func_init_val = 0,
1485 .socket_id = rte_socket_id(),
1488 TAILQ_INIT(&fdir_info->fdir_list);
1489 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1490 "fdir_%s", eth_dev->device->name);
1491 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1492 if (!fdir_info->hash_handle) {
1493 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1496 fdir_info->hash_map = rte_zmalloc("ixgbe",
1497 sizeof(struct ixgbe_fdir_filter *) *
1498 IXGBE_MAX_FDIR_FILTER_NUM,
1500 if (!fdir_info->hash_map) {
1502 "Failed to allocate memory for fdir hash map!");
1505 fdir_info->mask_added = FALSE;
1510 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1512 struct ixgbe_l2_tn_info *l2_tn_info =
1513 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1514 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1515 struct rte_hash_parameters l2_tn_hash_params = {
1516 .name = l2_tn_hash_name,
1517 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1518 .key_len = sizeof(struct ixgbe_l2_tn_key),
1519 .hash_func = rte_hash_crc,
1520 .hash_func_init_val = 0,
1521 .socket_id = rte_socket_id(),
1524 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1525 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1526 "l2_tn_%s", eth_dev->device->name);
1527 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1528 if (!l2_tn_info->hash_handle) {
1529 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1532 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1533 sizeof(struct ixgbe_l2_tn_filter *) *
1534 IXGBE_MAX_L2_TN_FILTER_NUM,
1536 if (!l2_tn_info->hash_map) {
1538 "Failed to allocate memory for L2 TN hash map!");
1541 l2_tn_info->e_tag_en = FALSE;
1542 l2_tn_info->e_tag_fwd_en = FALSE;
1543 l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1548 * Negotiate mailbox API version with the PF.
1549 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1550 * Then we try to negotiate starting with the most recent one.
1551 * If all negotiation attempts fail, then we will proceed with
1552 * the default one (ixgbe_mbox_api_10).
1555 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1559 /* start with highest supported, proceed down */
1560 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1567 i != RTE_DIM(sup_ver) &&
1568 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1574 generate_random_mac_addr(struct ether_addr *mac_addr)
1578 /* Set Organizationally Unique Identifier (OUI) prefix. */
1579 mac_addr->addr_bytes[0] = 0x00;
1580 mac_addr->addr_bytes[1] = 0x09;
1581 mac_addr->addr_bytes[2] = 0xC0;
1582 /* Force indication of locally assigned MAC address. */
1583 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1584 /* Generate the last 3 bytes of the MAC address with a random number. */
1585 random = rte_rand();
1586 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1590 * Virtual Function device init
1593 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1597 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1598 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1599 struct ixgbe_hw *hw =
1600 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1601 struct ixgbe_vfta *shadow_vfta =
1602 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1603 struct ixgbe_hwstrip *hwstrip =
1604 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1605 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1607 PMD_INIT_FUNC_TRACE();
1609 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1610 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1611 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1613 /* for secondary processes, we don't initialise any further as primary
1614 * has already done this work. Only check we don't need a different
1617 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1618 struct ixgbe_tx_queue *txq;
1619 /* TX queue function in primary, set by last queue initialized
1620 * Tx queue may not initialized by primary process
1622 if (eth_dev->data->tx_queues) {
1623 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1624 ixgbe_set_tx_function(eth_dev, txq);
1626 /* Use default TX function if we get here */
1627 PMD_INIT_LOG(NOTICE,
1628 "No TX queues configured yet. Using default TX function.");
1631 ixgbe_set_rx_function(eth_dev);
1636 rte_eth_copy_pci_info(eth_dev, pci_dev);
1638 hw->device_id = pci_dev->id.device_id;
1639 hw->vendor_id = pci_dev->id.vendor_id;
1640 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1642 /* initialize the vfta */
1643 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1645 /* initialize the hw strip bitmap*/
1646 memset(hwstrip, 0, sizeof(*hwstrip));
1648 /* Initialize the shared code (base driver) */
1649 diag = ixgbe_init_shared_code(hw);
1650 if (diag != IXGBE_SUCCESS) {
1651 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1655 /* init_mailbox_params */
1656 hw->mbx.ops.init_params(hw);
1658 /* Reset the hw statistics */
1659 ixgbevf_dev_stats_reset(eth_dev);
1661 /* Disable the interrupts for VF */
1662 ixgbevf_intr_disable(hw);
1664 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1665 diag = hw->mac.ops.reset_hw(hw);
1668 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1669 * the underlying PF driver has not assigned a MAC address to the VF.
1670 * In this case, assign a random MAC address.
1672 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1673 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1677 /* negotiate mailbox API version to use with the PF. */
1678 ixgbevf_negotiate_api(hw);
1680 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1681 ixgbevf_get_queues(hw, &tcs, &tc);
1683 /* Allocate memory for storing MAC addresses */
1684 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1685 hw->mac.num_rar_entries, 0);
1686 if (eth_dev->data->mac_addrs == NULL) {
1688 "Failed to allocate %u bytes needed to store "
1690 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1694 /* Generate a random MAC address, if none was assigned by PF. */
1695 if (is_zero_ether_addr(perm_addr)) {
1696 generate_random_mac_addr(perm_addr);
1697 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1699 rte_free(eth_dev->data->mac_addrs);
1700 eth_dev->data->mac_addrs = NULL;
1703 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1704 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1705 "%02x:%02x:%02x:%02x:%02x:%02x",
1706 perm_addr->addr_bytes[0],
1707 perm_addr->addr_bytes[1],
1708 perm_addr->addr_bytes[2],
1709 perm_addr->addr_bytes[3],
1710 perm_addr->addr_bytes[4],
1711 perm_addr->addr_bytes[5]);
1714 /* Copy the permanent MAC address */
1715 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1717 /* reset the hardware with the new settings */
1718 diag = hw->mac.ops.start_hw(hw);
1724 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1728 rte_intr_callback_register(intr_handle,
1729 ixgbevf_dev_interrupt_handler, eth_dev);
1730 rte_intr_enable(intr_handle);
1731 ixgbevf_intr_enable(hw);
1733 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1734 eth_dev->data->port_id, pci_dev->id.vendor_id,
1735 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1740 /* Virtual Function device uninit */
1743 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1745 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1746 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1747 struct ixgbe_hw *hw;
1749 PMD_INIT_FUNC_TRACE();
1751 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1754 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1756 if (hw->adapter_stopped == 0)
1757 ixgbevf_dev_close(eth_dev);
1759 eth_dev->dev_ops = NULL;
1760 eth_dev->rx_pkt_burst = NULL;
1761 eth_dev->tx_pkt_burst = NULL;
1763 /* Disable the interrupts for VF */
1764 ixgbevf_intr_disable(hw);
1766 rte_free(eth_dev->data->mac_addrs);
1767 eth_dev->data->mac_addrs = NULL;
1769 rte_intr_disable(intr_handle);
1770 rte_intr_callback_unregister(intr_handle,
1771 ixgbevf_dev_interrupt_handler, eth_dev);
1776 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1777 struct rte_pci_device *pci_dev)
1779 return rte_eth_dev_pci_generic_probe(pci_dev,
1780 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1783 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1785 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1788 static struct rte_pci_driver rte_ixgbe_pmd = {
1789 .id_table = pci_id_ixgbe_map,
1790 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1791 RTE_PCI_DRV_IOVA_AS_VA,
1792 .probe = eth_ixgbe_pci_probe,
1793 .remove = eth_ixgbe_pci_remove,
1796 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1797 struct rte_pci_device *pci_dev)
1799 return rte_eth_dev_pci_generic_probe(pci_dev,
1800 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1803 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1805 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1809 * virtual function driver struct
1811 static struct rte_pci_driver rte_ixgbevf_pmd = {
1812 .id_table = pci_id_ixgbevf_map,
1813 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1814 .probe = eth_ixgbevf_pci_probe,
1815 .remove = eth_ixgbevf_pci_remove,
1819 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1821 struct ixgbe_hw *hw =
1822 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1823 struct ixgbe_vfta *shadow_vfta =
1824 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1829 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1830 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1831 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1836 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1838 /* update local VFTA copy */
1839 shadow_vfta->vfta[vid_idx] = vfta;
1845 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1848 ixgbe_vlan_hw_strip_enable(dev, queue);
1850 ixgbe_vlan_hw_strip_disable(dev, queue);
1854 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1855 enum rte_vlan_type vlan_type,
1858 struct ixgbe_hw *hw =
1859 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1864 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1865 qinq &= IXGBE_DMATXCTL_GDV;
1867 switch (vlan_type) {
1868 case ETH_VLAN_TYPE_INNER:
1870 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1871 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1872 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1873 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1874 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1875 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1876 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1879 PMD_DRV_LOG(ERR, "Inner type is not supported"
1883 case ETH_VLAN_TYPE_OUTER:
1885 /* Only the high 16-bits is valid */
1886 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1887 IXGBE_EXVET_VET_EXT_SHIFT);
1889 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1890 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1891 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1892 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1893 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1894 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1895 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1901 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1909 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1911 struct ixgbe_hw *hw =
1912 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1915 PMD_INIT_FUNC_TRACE();
1917 /* Filter Table Disable */
1918 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1919 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1921 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1925 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1927 struct ixgbe_hw *hw =
1928 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1929 struct ixgbe_vfta *shadow_vfta =
1930 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1934 PMD_INIT_FUNC_TRACE();
1936 /* Filter Table Enable */
1937 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1938 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1939 vlnctrl |= IXGBE_VLNCTRL_VFE;
1941 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1943 /* write whatever is in local vfta copy */
1944 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1945 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1949 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1951 struct ixgbe_hwstrip *hwstrip =
1952 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1953 struct ixgbe_rx_queue *rxq;
1955 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1959 IXGBE_SET_HWSTRIP(hwstrip, queue);
1961 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1963 if (queue >= dev->data->nb_rx_queues)
1966 rxq = dev->data->rx_queues[queue];
1969 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1971 rxq->vlan_flags = PKT_RX_VLAN;
1975 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1977 struct ixgbe_hw *hw =
1978 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1981 PMD_INIT_FUNC_TRACE();
1983 if (hw->mac.type == ixgbe_mac_82598EB) {
1984 /* No queue level support */
1985 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1989 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1990 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1991 ctrl &= ~IXGBE_RXDCTL_VME;
1992 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1994 /* record those setting for HW strip per queue */
1995 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1999 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2001 struct ixgbe_hw *hw =
2002 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2005 PMD_INIT_FUNC_TRACE();
2007 if (hw->mac.type == ixgbe_mac_82598EB) {
2008 /* No queue level supported */
2009 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2013 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2014 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2015 ctrl |= IXGBE_RXDCTL_VME;
2016 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2018 /* record those setting for HW strip per queue */
2019 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2023 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2025 struct ixgbe_hw *hw =
2026 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2029 struct ixgbe_rx_queue *rxq;
2031 PMD_INIT_FUNC_TRACE();
2033 if (hw->mac.type == ixgbe_mac_82598EB) {
2034 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2035 ctrl &= ~IXGBE_VLNCTRL_VME;
2036 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2038 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2039 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2040 rxq = dev->data->rx_queues[i];
2041 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2042 ctrl &= ~IXGBE_RXDCTL_VME;
2043 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2045 /* record those setting for HW strip per queue */
2046 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2052 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2054 struct ixgbe_hw *hw =
2055 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2058 struct ixgbe_rx_queue *rxq;
2060 PMD_INIT_FUNC_TRACE();
2062 if (hw->mac.type == ixgbe_mac_82598EB) {
2063 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2064 ctrl |= IXGBE_VLNCTRL_VME;
2065 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2067 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2068 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2069 rxq = dev->data->rx_queues[i];
2070 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2071 ctrl |= IXGBE_RXDCTL_VME;
2072 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2074 /* record those setting for HW strip per queue */
2075 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2081 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2083 struct ixgbe_hw *hw =
2084 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2087 PMD_INIT_FUNC_TRACE();
2089 /* DMATXCTRL: Geric Double VLAN Disable */
2090 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2091 ctrl &= ~IXGBE_DMATXCTL_GDV;
2092 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2094 /* CTRL_EXT: Global Double VLAN Disable */
2095 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2096 ctrl &= ~IXGBE_EXTENDED_VLAN;
2097 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2102 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2104 struct ixgbe_hw *hw =
2105 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2108 PMD_INIT_FUNC_TRACE();
2110 /* DMATXCTRL: Geric Double VLAN Enable */
2111 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2112 ctrl |= IXGBE_DMATXCTL_GDV;
2113 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2115 /* CTRL_EXT: Global Double VLAN Enable */
2116 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2117 ctrl |= IXGBE_EXTENDED_VLAN;
2118 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2120 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2121 if (hw->mac.type == ixgbe_mac_X550 ||
2122 hw->mac.type == ixgbe_mac_X550EM_x ||
2123 hw->mac.type == ixgbe_mac_X550EM_a) {
2124 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2125 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2126 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2130 * VET EXT field in the EXVET register = 0x8100 by default
2131 * So no need to change. Same to VT field of DMATXCTL register
2136 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2138 if (mask & ETH_VLAN_STRIP_MASK) {
2139 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2140 ixgbe_vlan_hw_strip_enable_all(dev);
2142 ixgbe_vlan_hw_strip_disable_all(dev);
2145 if (mask & ETH_VLAN_FILTER_MASK) {
2146 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2147 ixgbe_vlan_hw_filter_enable(dev);
2149 ixgbe_vlan_hw_filter_disable(dev);
2152 if (mask & ETH_VLAN_EXTEND_MASK) {
2153 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2154 ixgbe_vlan_hw_extend_enable(dev);
2156 ixgbe_vlan_hw_extend_disable(dev);
2163 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2165 struct ixgbe_hw *hw =
2166 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2167 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2168 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2170 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2171 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2175 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2177 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2182 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2185 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2191 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2192 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2198 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2200 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2201 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2202 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2203 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2205 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2206 /* check multi-queue mode */
2207 switch (dev_conf->rxmode.mq_mode) {
2208 case ETH_MQ_RX_VMDQ_DCB:
2209 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2211 case ETH_MQ_RX_VMDQ_DCB_RSS:
2212 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2213 PMD_INIT_LOG(ERR, "SRIOV active,"
2214 " unsupported mq_mode rx %d.",
2215 dev_conf->rxmode.mq_mode);
2218 case ETH_MQ_RX_VMDQ_RSS:
2219 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2220 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2221 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2222 PMD_INIT_LOG(ERR, "SRIOV is active,"
2223 " invalid queue number"
2224 " for VMDQ RSS, allowed"
2225 " value are 1, 2 or 4.");
2229 case ETH_MQ_RX_VMDQ_ONLY:
2230 case ETH_MQ_RX_NONE:
2231 /* if nothing mq mode configure, use default scheme */
2232 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2233 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2234 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2236 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2237 /* SRIOV only works in VMDq enable mode */
2238 PMD_INIT_LOG(ERR, "SRIOV is active,"
2239 " wrong mq_mode rx %d.",
2240 dev_conf->rxmode.mq_mode);
2244 switch (dev_conf->txmode.mq_mode) {
2245 case ETH_MQ_TX_VMDQ_DCB:
2246 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2247 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2249 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2250 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2254 /* check valid queue number */
2255 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2256 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2257 PMD_INIT_LOG(ERR, "SRIOV is active,"
2258 " nb_rx_q=%d nb_tx_q=%d queue number"
2259 " must be less than or equal to %d.",
2261 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2265 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2266 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2270 /* check configuration for vmdb+dcb mode */
2271 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2272 const struct rte_eth_vmdq_dcb_conf *conf;
2274 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2275 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2276 IXGBE_VMDQ_DCB_NB_QUEUES);
2279 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2280 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2281 conf->nb_queue_pools == ETH_32_POOLS)) {
2282 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2283 " nb_queue_pools must be %d or %d.",
2284 ETH_16_POOLS, ETH_32_POOLS);
2288 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2289 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2291 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2292 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2293 IXGBE_VMDQ_DCB_NB_QUEUES);
2296 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2297 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2298 conf->nb_queue_pools == ETH_32_POOLS)) {
2299 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2300 " nb_queue_pools != %d and"
2301 " nb_queue_pools != %d.",
2302 ETH_16_POOLS, ETH_32_POOLS);
2307 /* For DCB mode check our configuration before we go further */
2308 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2309 const struct rte_eth_dcb_rx_conf *conf;
2311 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2312 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2313 IXGBE_DCB_NB_QUEUES);
2316 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2317 if (!(conf->nb_tcs == ETH_4_TCS ||
2318 conf->nb_tcs == ETH_8_TCS)) {
2319 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2320 " and nb_tcs != %d.",
2321 ETH_4_TCS, ETH_8_TCS);
2326 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2327 const struct rte_eth_dcb_tx_conf *conf;
2329 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2330 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2331 IXGBE_DCB_NB_QUEUES);
2334 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2335 if (!(conf->nb_tcs == ETH_4_TCS ||
2336 conf->nb_tcs == ETH_8_TCS)) {
2337 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2338 " and nb_tcs != %d.",
2339 ETH_4_TCS, ETH_8_TCS);
2345 * When DCB/VT is off, maximum number of queues changes,
2346 * except for 82598EB, which remains constant.
2348 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2349 hw->mac.type != ixgbe_mac_82598EB) {
2350 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2352 "Neither VT nor DCB are enabled, "
2354 IXGBE_NONE_MODE_TX_NB_QUEUES);
2363 ixgbe_dev_configure(struct rte_eth_dev *dev)
2365 struct ixgbe_interrupt *intr =
2366 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2367 struct ixgbe_adapter *adapter =
2368 (struct ixgbe_adapter *)dev->data->dev_private;
2371 PMD_INIT_FUNC_TRACE();
2372 /* multipe queue mode checking */
2373 ret = ixgbe_check_mq_mode(dev);
2375 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2380 /* set flag to update link status after init */
2381 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2384 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2385 * allocation or vector Rx preconditions we will reset it.
2387 adapter->rx_bulk_alloc_allowed = true;
2388 adapter->rx_vec_allowed = true;
2394 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2396 struct ixgbe_hw *hw =
2397 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2398 struct ixgbe_interrupt *intr =
2399 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2402 /* only set up it on X550EM_X */
2403 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2404 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2405 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2406 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2407 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2408 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2413 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2414 uint16_t tx_rate, uint64_t q_msk)
2416 struct ixgbe_hw *hw;
2417 struct ixgbe_vf_info *vfinfo;
2418 struct rte_eth_link link;
2419 uint8_t nb_q_per_pool;
2420 uint32_t queue_stride;
2421 uint32_t queue_idx, idx = 0, vf_idx;
2423 uint16_t total_rate = 0;
2424 struct rte_pci_device *pci_dev;
2426 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2427 rte_eth_link_get_nowait(dev->data->port_id, &link);
2429 if (vf >= pci_dev->max_vfs)
2432 if (tx_rate > link.link_speed)
2438 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2439 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2440 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2441 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2442 queue_idx = vf * queue_stride;
2443 queue_end = queue_idx + nb_q_per_pool - 1;
2444 if (queue_end >= hw->mac.max_tx_queues)
2448 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2451 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2453 total_rate += vfinfo[vf_idx].tx_rate[idx];
2459 /* Store tx_rate for this vf. */
2460 for (idx = 0; idx < nb_q_per_pool; idx++) {
2461 if (((uint64_t)0x1 << idx) & q_msk) {
2462 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2463 vfinfo[vf].tx_rate[idx] = tx_rate;
2464 total_rate += tx_rate;
2468 if (total_rate > dev->data->dev_link.link_speed) {
2469 /* Reset stored TX rate of the VF if it causes exceed
2472 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2476 /* Set RTTBCNRC of each queue/pool for vf X */
2477 for (; queue_idx <= queue_end; queue_idx++) {
2479 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2487 * Configure device link speed and setup link.
2488 * It returns 0 on success.
2491 ixgbe_dev_start(struct rte_eth_dev *dev)
2493 struct ixgbe_hw *hw =
2494 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2495 struct ixgbe_vf_info *vfinfo =
2496 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2497 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2498 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2499 uint32_t intr_vector = 0;
2500 int err, link_up = 0, negotiate = 0;
2505 uint32_t *link_speeds;
2506 struct ixgbe_tm_conf *tm_conf =
2507 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2509 PMD_INIT_FUNC_TRACE();
2511 /* IXGBE devices don't support:
2512 * - half duplex (checked afterwards for valid speeds)
2513 * - fixed speed: TODO implement
2515 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2517 "Invalid link_speeds for port %u, fix speed not supported",
2518 dev->data->port_id);
2522 /* disable uio/vfio intr/eventfd mapping */
2523 rte_intr_disable(intr_handle);
2526 hw->adapter_stopped = 0;
2527 ixgbe_stop_adapter(hw);
2529 /* reinitialize adapter
2530 * this calls reset and start
2532 status = ixgbe_pf_reset_hw(hw);
2535 hw->mac.ops.start_hw(hw);
2536 hw->mac.get_link_status = true;
2538 /* configure PF module if SRIOV enabled */
2539 ixgbe_pf_host_configure(dev);
2541 ixgbe_dev_phy_intr_setup(dev);
2543 /* check and configure queue intr-vector mapping */
2544 if ((rte_intr_cap_multiple(intr_handle) ||
2545 !RTE_ETH_DEV_SRIOV(dev).active) &&
2546 dev->data->dev_conf.intr_conf.rxq != 0) {
2547 intr_vector = dev->data->nb_rx_queues;
2548 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2549 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2550 IXGBE_MAX_INTR_QUEUE_NUM);
2553 if (rte_intr_efd_enable(intr_handle, intr_vector))
2557 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2558 intr_handle->intr_vec =
2559 rte_zmalloc("intr_vec",
2560 dev->data->nb_rx_queues * sizeof(int), 0);
2561 if (intr_handle->intr_vec == NULL) {
2562 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2563 " intr_vec", dev->data->nb_rx_queues);
2568 /* confiugre msix for sleep until rx interrupt */
2569 ixgbe_configure_msix(dev);
2571 /* initialize transmission unit */
2572 ixgbe_dev_tx_init(dev);
2574 /* This can fail when allocating mbufs for descriptor rings */
2575 err = ixgbe_dev_rx_init(dev);
2577 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2581 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2582 ETH_VLAN_EXTEND_MASK;
2583 err = ixgbe_vlan_offload_set(dev, mask);
2585 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2589 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2590 /* Enable vlan filtering for VMDq */
2591 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2594 /* Configure DCB hw */
2595 ixgbe_configure_dcb(dev);
2597 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2598 err = ixgbe_fdir_configure(dev);
2603 /* Restore vf rate limit */
2604 if (vfinfo != NULL) {
2605 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2606 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2607 if (vfinfo[vf].tx_rate[idx] != 0)
2608 ixgbe_set_vf_rate_limit(
2610 vfinfo[vf].tx_rate[idx],
2614 ixgbe_restore_statistics_mapping(dev);
2616 err = ixgbe_dev_rxtx_start(dev);
2618 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2622 /* Skip link setup if loopback mode is enabled for 82599. */
2623 if (hw->mac.type == ixgbe_mac_82599EB &&
2624 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2625 goto skip_link_setup;
2627 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2628 err = hw->mac.ops.setup_sfp(hw);
2633 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2634 /* Turn on the copper */
2635 ixgbe_set_phy_power(hw, true);
2637 /* Turn on the laser */
2638 ixgbe_enable_tx_laser(hw);
2641 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2644 dev->data->dev_link.link_status = link_up;
2646 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2650 link_speeds = &dev->data->dev_conf.link_speeds;
2651 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2652 ETH_LINK_SPEED_10G)) {
2653 PMD_INIT_LOG(ERR, "Invalid link setting");
2658 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2659 switch (hw->mac.type) {
2660 case ixgbe_mac_82598EB:
2661 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2663 case ixgbe_mac_82599EB:
2664 case ixgbe_mac_X540:
2665 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2667 case ixgbe_mac_X550:
2668 case ixgbe_mac_X550EM_x:
2669 case ixgbe_mac_X550EM_a:
2670 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2673 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2676 if (*link_speeds & ETH_LINK_SPEED_10G)
2677 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2678 if (*link_speeds & ETH_LINK_SPEED_1G)
2679 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2680 if (*link_speeds & ETH_LINK_SPEED_100M)
2681 speed |= IXGBE_LINK_SPEED_100_FULL;
2684 err = ixgbe_setup_link(hw, speed, link_up);
2690 if (rte_intr_allow_others(intr_handle)) {
2691 /* check if lsc interrupt is enabled */
2692 if (dev->data->dev_conf.intr_conf.lsc != 0)
2693 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2695 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2696 ixgbe_dev_macsec_interrupt_setup(dev);
2698 rte_intr_callback_unregister(intr_handle,
2699 ixgbe_dev_interrupt_handler, dev);
2700 if (dev->data->dev_conf.intr_conf.lsc != 0)
2701 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2702 " no intr multiplex");
2705 /* check if rxq interrupt is enabled */
2706 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2707 rte_intr_dp_is_en(intr_handle))
2708 ixgbe_dev_rxq_interrupt_setup(dev);
2710 /* enable uio/vfio intr/eventfd mapping */
2711 rte_intr_enable(intr_handle);
2713 /* resume enabled intr since hw reset */
2714 ixgbe_enable_intr(dev);
2715 ixgbe_l2_tunnel_conf(dev);
2716 ixgbe_filter_restore(dev);
2718 if (tm_conf->root && !tm_conf->committed)
2719 PMD_DRV_LOG(WARNING,
2720 "please call hierarchy_commit() "
2721 "before starting the port");
2726 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2727 ixgbe_dev_clear_queues(dev);
2732 * Stop device: disable rx and tx functions to allow for reconfiguring.
2735 ixgbe_dev_stop(struct rte_eth_dev *dev)
2737 struct rte_eth_link link;
2738 struct ixgbe_hw *hw =
2739 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2740 struct ixgbe_vf_info *vfinfo =
2741 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2742 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2743 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2745 struct ixgbe_tm_conf *tm_conf =
2746 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2748 PMD_INIT_FUNC_TRACE();
2750 /* disable interrupts */
2751 ixgbe_disable_intr(hw);
2754 ixgbe_pf_reset_hw(hw);
2755 hw->adapter_stopped = 0;
2758 ixgbe_stop_adapter(hw);
2760 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2761 vfinfo[vf].clear_to_send = false;
2763 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2764 /* Turn off the copper */
2765 ixgbe_set_phy_power(hw, false);
2767 /* Turn off the laser */
2768 ixgbe_disable_tx_laser(hw);
2771 ixgbe_dev_clear_queues(dev);
2773 /* Clear stored conf */
2774 dev->data->scattered_rx = 0;
2777 /* Clear recorded link status */
2778 memset(&link, 0, sizeof(link));
2779 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2781 if (!rte_intr_allow_others(intr_handle))
2782 /* resume to the default handler */
2783 rte_intr_callback_register(intr_handle,
2784 ixgbe_dev_interrupt_handler,
2787 /* Clean datapath event and queue/vec mapping */
2788 rte_intr_efd_disable(intr_handle);
2789 if (intr_handle->intr_vec != NULL) {
2790 rte_free(intr_handle->intr_vec);
2791 intr_handle->intr_vec = NULL;
2794 /* reset hierarchy commit */
2795 tm_conf->committed = false;
2799 * Set device link up: enable tx.
2802 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2804 struct ixgbe_hw *hw =
2805 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2806 if (hw->mac.type == ixgbe_mac_82599EB) {
2807 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2808 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2809 /* Not suported in bypass mode */
2810 PMD_INIT_LOG(ERR, "Set link up is not supported "
2811 "by device id 0x%x", hw->device_id);
2817 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2818 /* Turn on the copper */
2819 ixgbe_set_phy_power(hw, true);
2821 /* Turn on the laser */
2822 ixgbe_enable_tx_laser(hw);
2829 * Set device link down: disable tx.
2832 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2834 struct ixgbe_hw *hw =
2835 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2836 if (hw->mac.type == ixgbe_mac_82599EB) {
2837 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2838 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2839 /* Not suported in bypass mode */
2840 PMD_INIT_LOG(ERR, "Set link down is not supported "
2841 "by device id 0x%x", hw->device_id);
2847 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2848 /* Turn off the copper */
2849 ixgbe_set_phy_power(hw, false);
2851 /* Turn off the laser */
2852 ixgbe_disable_tx_laser(hw);
2859 * Reset and stop device.
2862 ixgbe_dev_close(struct rte_eth_dev *dev)
2864 struct ixgbe_hw *hw =
2865 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2867 PMD_INIT_FUNC_TRACE();
2869 ixgbe_pf_reset_hw(hw);
2871 ixgbe_dev_stop(dev);
2872 hw->adapter_stopped = 1;
2874 ixgbe_dev_free_queues(dev);
2876 ixgbe_disable_pcie_master(hw);
2878 /* reprogram the RAR[0] in case user changed it. */
2879 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2886 ixgbe_dev_reset(struct rte_eth_dev *dev)
2890 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2891 * its VF to make them align with it. The detailed notification
2892 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2893 * To avoid unexpected behavior in VF, currently reset of PF with
2894 * SR-IOV activation is not supported. It might be supported later.
2896 if (dev->data->sriov.active)
2899 ret = eth_ixgbe_dev_uninit(dev);
2903 ret = eth_ixgbe_dev_init(dev);
2909 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2910 struct ixgbe_hw_stats *hw_stats,
2911 struct ixgbe_macsec_stats *macsec_stats,
2912 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2913 uint64_t *total_qprc, uint64_t *total_qprdc)
2915 uint32_t bprc, lxon, lxoff, total;
2916 uint32_t delta_gprc = 0;
2918 /* Workaround for RX byte count not including CRC bytes when CRC
2919 * strip is enabled. CRC bytes are removed from counters when crc_strip
2922 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2923 IXGBE_HLREG0_RXCRCSTRP);
2925 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2926 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2927 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2928 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2930 for (i = 0; i < 8; i++) {
2931 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2933 /* global total per queue */
2934 hw_stats->mpc[i] += mp;
2935 /* Running comprehensive total for stats display */
2936 *total_missed_rx += hw_stats->mpc[i];
2937 if (hw->mac.type == ixgbe_mac_82598EB) {
2938 hw_stats->rnbc[i] +=
2939 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2940 hw_stats->pxonrxc[i] +=
2941 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2942 hw_stats->pxoffrxc[i] +=
2943 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2945 hw_stats->pxonrxc[i] +=
2946 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2947 hw_stats->pxoffrxc[i] +=
2948 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2949 hw_stats->pxon2offc[i] +=
2950 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2952 hw_stats->pxontxc[i] +=
2953 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2954 hw_stats->pxofftxc[i] +=
2955 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2957 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2958 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2959 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2960 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2962 delta_gprc += delta_qprc;
2964 hw_stats->qprc[i] += delta_qprc;
2965 hw_stats->qptc[i] += delta_qptc;
2967 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2968 hw_stats->qbrc[i] +=
2969 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2971 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2973 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2974 hw_stats->qbtc[i] +=
2975 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2977 hw_stats->qprdc[i] += delta_qprdc;
2978 *total_qprdc += hw_stats->qprdc[i];
2980 *total_qprc += hw_stats->qprc[i];
2981 *total_qbrc += hw_stats->qbrc[i];
2983 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2984 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2985 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2988 * An errata states that gprc actually counts good + missed packets:
2989 * Workaround to set gprc to summated queue packet receives
2991 hw_stats->gprc = *total_qprc;
2993 if (hw->mac.type != ixgbe_mac_82598EB) {
2994 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2995 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2996 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2997 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2998 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2999 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3000 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3001 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3003 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3004 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3005 /* 82598 only has a counter in the high register */
3006 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3007 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3008 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3010 uint64_t old_tpr = hw_stats->tpr;
3012 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3013 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3016 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3018 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3019 hw_stats->gptc += delta_gptc;
3020 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3021 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3024 * Workaround: mprc hardware is incorrectly counting
3025 * broadcasts, so for now we subtract those.
3027 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3028 hw_stats->bprc += bprc;
3029 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3030 if (hw->mac.type == ixgbe_mac_82598EB)
3031 hw_stats->mprc -= bprc;
3033 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3034 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3035 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3036 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3037 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3038 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3040 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3041 hw_stats->lxontxc += lxon;
3042 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3043 hw_stats->lxofftxc += lxoff;
3044 total = lxon + lxoff;
3046 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3047 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3048 hw_stats->gptc -= total;
3049 hw_stats->mptc -= total;
3050 hw_stats->ptc64 -= total;
3051 hw_stats->gotc -= total * ETHER_MIN_LEN;
3053 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3054 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3055 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3056 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3057 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3058 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3059 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3060 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3061 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3062 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3063 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3064 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3065 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3066 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3067 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3068 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3069 /* Only read FCOE on 82599 */
3070 if (hw->mac.type != ixgbe_mac_82598EB) {
3071 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3072 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3073 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3074 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3075 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3078 /* Flow Director Stats registers */
3079 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3080 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3082 /* MACsec Stats registers */
3083 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3084 macsec_stats->out_pkts_encrypted +=
3085 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3086 macsec_stats->out_pkts_protected +=
3087 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3088 macsec_stats->out_octets_encrypted +=
3089 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3090 macsec_stats->out_octets_protected +=
3091 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3092 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3093 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3094 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3095 macsec_stats->in_pkts_unknownsci +=
3096 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3097 macsec_stats->in_octets_decrypted +=
3098 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3099 macsec_stats->in_octets_validated +=
3100 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3101 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3102 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3103 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3104 for (i = 0; i < 2; i++) {
3105 macsec_stats->in_pkts_ok +=
3106 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3107 macsec_stats->in_pkts_invalid +=
3108 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3109 macsec_stats->in_pkts_notvalid +=
3110 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3112 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3113 macsec_stats->in_pkts_notusingsa +=
3114 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3118 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3121 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3123 struct ixgbe_hw *hw =
3124 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3125 struct ixgbe_hw_stats *hw_stats =
3126 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3127 struct ixgbe_macsec_stats *macsec_stats =
3128 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3129 dev->data->dev_private);
3130 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3133 total_missed_rx = 0;
3138 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3139 &total_qbrc, &total_qprc, &total_qprdc);
3144 /* Fill out the rte_eth_stats statistics structure */
3145 stats->ipackets = total_qprc;
3146 stats->ibytes = total_qbrc;
3147 stats->opackets = hw_stats->gptc;
3148 stats->obytes = hw_stats->gotc;
3150 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3151 stats->q_ipackets[i] = hw_stats->qprc[i];
3152 stats->q_opackets[i] = hw_stats->qptc[i];
3153 stats->q_ibytes[i] = hw_stats->qbrc[i];
3154 stats->q_obytes[i] = hw_stats->qbtc[i];
3155 stats->q_errors[i] = hw_stats->qprdc[i];
3159 stats->imissed = total_missed_rx;
3160 stats->ierrors = hw_stats->crcerrs +
3177 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3179 struct ixgbe_hw_stats *stats =
3180 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3182 /* HW registers are cleared on read */
3183 ixgbe_dev_stats_get(dev, NULL);
3185 /* Reset software totals */
3186 memset(stats, 0, sizeof(*stats));
3189 /* This function calculates the number of xstats based on the current config */
3191 ixgbe_xstats_calc_num(void) {
3192 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3193 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3194 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3197 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3198 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3200 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3201 unsigned stat, i, count;
3203 if (xstats_names != NULL) {
3206 /* Note: limit >= cnt_stats checked upstream
3207 * in rte_eth_xstats_names()
3210 /* Extended stats from ixgbe_hw_stats */
3211 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3212 snprintf(xstats_names[count].name,
3213 sizeof(xstats_names[count].name),
3215 rte_ixgbe_stats_strings[i].name);
3220 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3221 snprintf(xstats_names[count].name,
3222 sizeof(xstats_names[count].name),
3224 rte_ixgbe_macsec_strings[i].name);
3228 /* RX Priority Stats */
3229 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3230 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3231 snprintf(xstats_names[count].name,
3232 sizeof(xstats_names[count].name),
3233 "rx_priority%u_%s", i,
3234 rte_ixgbe_rxq_strings[stat].name);
3239 /* TX Priority Stats */
3240 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3241 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3242 snprintf(xstats_names[count].name,
3243 sizeof(xstats_names[count].name),
3244 "tx_priority%u_%s", i,
3245 rte_ixgbe_txq_strings[stat].name);
3253 static int ixgbe_dev_xstats_get_names_by_id(
3254 struct rte_eth_dev *dev,
3255 struct rte_eth_xstat_name *xstats_names,
3256 const uint64_t *ids,
3260 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3261 unsigned int stat, i, count;
3263 if (xstats_names != NULL) {
3266 /* Note: limit >= cnt_stats checked upstream
3267 * in rte_eth_xstats_names()
3270 /* Extended stats from ixgbe_hw_stats */
3271 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3272 snprintf(xstats_names[count].name,
3273 sizeof(xstats_names[count].name),
3275 rte_ixgbe_stats_strings[i].name);
3280 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3281 snprintf(xstats_names[count].name,
3282 sizeof(xstats_names[count].name),
3284 rte_ixgbe_macsec_strings[i].name);
3288 /* RX Priority Stats */
3289 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3290 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3291 snprintf(xstats_names[count].name,
3292 sizeof(xstats_names[count].name),
3293 "rx_priority%u_%s", i,
3294 rte_ixgbe_rxq_strings[stat].name);
3299 /* TX Priority Stats */
3300 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3301 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3302 snprintf(xstats_names[count].name,
3303 sizeof(xstats_names[count].name),
3304 "tx_priority%u_%s", i,
3305 rte_ixgbe_txq_strings[stat].name);
3314 uint16_t size = ixgbe_xstats_calc_num();
3315 struct rte_eth_xstat_name xstats_names_copy[size];
3317 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3320 for (i = 0; i < limit; i++) {
3321 if (ids[i] >= size) {
3322 PMD_INIT_LOG(ERR, "id value isn't valid");
3325 strcpy(xstats_names[i].name,
3326 xstats_names_copy[ids[i]].name);
3331 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3332 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3336 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3339 if (xstats_names != NULL)
3340 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3341 snprintf(xstats_names[i].name,
3342 sizeof(xstats_names[i].name),
3343 "%s", rte_ixgbevf_stats_strings[i].name);
3344 return IXGBEVF_NB_XSTATS;
3348 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3351 struct ixgbe_hw *hw =
3352 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3353 struct ixgbe_hw_stats *hw_stats =
3354 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3355 struct ixgbe_macsec_stats *macsec_stats =
3356 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3357 dev->data->dev_private);
3358 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3359 unsigned i, stat, count = 0;
3361 count = ixgbe_xstats_calc_num();
3366 total_missed_rx = 0;
3371 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3372 &total_qbrc, &total_qprc, &total_qprdc);
3374 /* If this is a reset xstats is NULL, and we have cleared the
3375 * registers by reading them.
3380 /* Extended stats from ixgbe_hw_stats */
3382 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3383 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3384 rte_ixgbe_stats_strings[i].offset);
3385 xstats[count].id = count;
3390 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3391 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3392 rte_ixgbe_macsec_strings[i].offset);
3393 xstats[count].id = count;
3397 /* RX Priority Stats */
3398 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3399 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3400 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3401 rte_ixgbe_rxq_strings[stat].offset +
3402 (sizeof(uint64_t) * i));
3403 xstats[count].id = count;
3408 /* TX Priority Stats */
3409 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3410 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3411 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3412 rte_ixgbe_txq_strings[stat].offset +
3413 (sizeof(uint64_t) * i));
3414 xstats[count].id = count;
3422 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3423 uint64_t *values, unsigned int n)
3426 struct ixgbe_hw *hw =
3427 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3428 struct ixgbe_hw_stats *hw_stats =
3429 IXGBE_DEV_PRIVATE_TO_STATS(
3430 dev->data->dev_private);
3431 struct ixgbe_macsec_stats *macsec_stats =
3432 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3433 dev->data->dev_private);
3434 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3435 unsigned int i, stat, count = 0;
3437 count = ixgbe_xstats_calc_num();
3439 if (!ids && n < count)
3442 total_missed_rx = 0;
3447 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3448 &total_missed_rx, &total_qbrc, &total_qprc,
3451 /* If this is a reset xstats is NULL, and we have cleared the
3452 * registers by reading them.
3454 if (!ids && !values)
3457 /* Extended stats from ixgbe_hw_stats */
3459 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3460 values[count] = *(uint64_t *)(((char *)hw_stats) +
3461 rte_ixgbe_stats_strings[i].offset);
3466 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3467 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3468 rte_ixgbe_macsec_strings[i].offset);
3472 /* RX Priority Stats */
3473 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3474 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3476 *(uint64_t *)(((char *)hw_stats) +
3477 rte_ixgbe_rxq_strings[stat].offset +
3478 (sizeof(uint64_t) * i));
3483 /* TX Priority Stats */
3484 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3485 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3487 *(uint64_t *)(((char *)hw_stats) +
3488 rte_ixgbe_txq_strings[stat].offset +
3489 (sizeof(uint64_t) * i));
3497 uint16_t size = ixgbe_xstats_calc_num();
3498 uint64_t values_copy[size];
3500 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3502 for (i = 0; i < n; i++) {
3503 if (ids[i] >= size) {
3504 PMD_INIT_LOG(ERR, "id value isn't valid");
3507 values[i] = values_copy[ids[i]];
3513 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3515 struct ixgbe_hw_stats *stats =
3516 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3517 struct ixgbe_macsec_stats *macsec_stats =
3518 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3519 dev->data->dev_private);
3521 unsigned count = ixgbe_xstats_calc_num();
3523 /* HW registers are cleared on read */
3524 ixgbe_dev_xstats_get(dev, NULL, count);
3526 /* Reset software totals */
3527 memset(stats, 0, sizeof(*stats));
3528 memset(macsec_stats, 0, sizeof(*macsec_stats));
3532 ixgbevf_update_stats(struct rte_eth_dev *dev)
3534 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3535 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3536 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3538 /* Good Rx packet, include VF loopback */
3539 UPDATE_VF_STAT(IXGBE_VFGPRC,
3540 hw_stats->last_vfgprc, hw_stats->vfgprc);
3542 /* Good Rx octets, include VF loopback */
3543 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3544 hw_stats->last_vfgorc, hw_stats->vfgorc);
3546 /* Good Tx packet, include VF loopback */
3547 UPDATE_VF_STAT(IXGBE_VFGPTC,
3548 hw_stats->last_vfgptc, hw_stats->vfgptc);
3550 /* Good Tx octets, include VF loopback */
3551 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3552 hw_stats->last_vfgotc, hw_stats->vfgotc);
3554 /* Rx Multicst Packet */
3555 UPDATE_VF_STAT(IXGBE_VFMPRC,
3556 hw_stats->last_vfmprc, hw_stats->vfmprc);
3560 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3563 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3564 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3567 if (n < IXGBEVF_NB_XSTATS)
3568 return IXGBEVF_NB_XSTATS;
3570 ixgbevf_update_stats(dev);
3575 /* Extended stats */
3576 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3578 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3579 rte_ixgbevf_stats_strings[i].offset);
3582 return IXGBEVF_NB_XSTATS;
3586 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3588 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3589 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3591 ixgbevf_update_stats(dev);
3596 stats->ipackets = hw_stats->vfgprc;
3597 stats->ibytes = hw_stats->vfgorc;
3598 stats->opackets = hw_stats->vfgptc;
3599 stats->obytes = hw_stats->vfgotc;
3604 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3606 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3607 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3609 /* Sync HW register to the last stats */
3610 ixgbevf_dev_stats_get(dev, NULL);
3612 /* reset HW current stats*/
3613 hw_stats->vfgprc = 0;
3614 hw_stats->vfgorc = 0;
3615 hw_stats->vfgptc = 0;
3616 hw_stats->vfgotc = 0;
3620 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3622 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3623 u16 eeprom_verh, eeprom_verl;
3627 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3628 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3630 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3631 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3633 ret += 1; /* add the size of '\0' */
3634 if (fw_size < (u32)ret)
3641 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3643 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3644 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3645 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3647 dev_info->pci_dev = pci_dev;
3648 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3649 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3650 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3652 * When DCB/VT is off, maximum number of queues changes,
3653 * except for 82598EB, which remains constant.
3655 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3656 hw->mac.type != ixgbe_mac_82598EB)
3657 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3659 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3660 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3661 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3662 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3663 dev_info->max_vfs = pci_dev->max_vfs;
3664 if (hw->mac.type == ixgbe_mac_82598EB)
3665 dev_info->max_vmdq_pools = ETH_16_POOLS;
3667 dev_info->max_vmdq_pools = ETH_64_POOLS;
3668 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3669 dev_info->rx_offload_capa =
3670 DEV_RX_OFFLOAD_VLAN_STRIP |
3671 DEV_RX_OFFLOAD_IPV4_CKSUM |
3672 DEV_RX_OFFLOAD_UDP_CKSUM |
3673 DEV_RX_OFFLOAD_TCP_CKSUM;
3676 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3679 if ((hw->mac.type == ixgbe_mac_82599EB ||
3680 hw->mac.type == ixgbe_mac_X540) &&
3681 !RTE_ETH_DEV_SRIOV(dev).active)
3682 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3684 if (hw->mac.type == ixgbe_mac_82599EB ||
3685 hw->mac.type == ixgbe_mac_X540)
3686 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3688 if (hw->mac.type == ixgbe_mac_X550 ||
3689 hw->mac.type == ixgbe_mac_X550EM_x ||
3690 hw->mac.type == ixgbe_mac_X550EM_a)
3691 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3693 dev_info->tx_offload_capa =
3694 DEV_TX_OFFLOAD_VLAN_INSERT |
3695 DEV_TX_OFFLOAD_IPV4_CKSUM |
3696 DEV_TX_OFFLOAD_UDP_CKSUM |
3697 DEV_TX_OFFLOAD_TCP_CKSUM |
3698 DEV_TX_OFFLOAD_SCTP_CKSUM |
3699 DEV_TX_OFFLOAD_TCP_TSO;
3701 if (hw->mac.type == ixgbe_mac_82599EB ||
3702 hw->mac.type == ixgbe_mac_X540)
3703 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3705 if (hw->mac.type == ixgbe_mac_X550 ||
3706 hw->mac.type == ixgbe_mac_X550EM_x ||
3707 hw->mac.type == ixgbe_mac_X550EM_a)
3708 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3710 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_SECURITY;
3711 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
3713 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3715 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3716 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3717 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3719 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3723 dev_info->default_txconf = (struct rte_eth_txconf) {
3725 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3726 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3727 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3729 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3730 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3731 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3732 ETH_TXQ_FLAGS_NOOFFLOADS,
3735 dev_info->rx_desc_lim = rx_desc_lim;
3736 dev_info->tx_desc_lim = tx_desc_lim;
3738 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3739 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3740 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3742 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3743 if (hw->mac.type == ixgbe_mac_X540 ||
3744 hw->mac.type == ixgbe_mac_X540_vf ||
3745 hw->mac.type == ixgbe_mac_X550 ||
3746 hw->mac.type == ixgbe_mac_X550_vf) {
3747 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3749 if (hw->mac.type == ixgbe_mac_X550) {
3750 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3751 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3755 static const uint32_t *
3756 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3758 static const uint32_t ptypes[] = {
3759 /* For non-vec functions,
3760 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3761 * for vec functions,
3762 * refers to _recv_raw_pkts_vec().
3766 RTE_PTYPE_L3_IPV4_EXT,
3768 RTE_PTYPE_L3_IPV6_EXT,
3772 RTE_PTYPE_TUNNEL_IP,
3773 RTE_PTYPE_INNER_L3_IPV6,
3774 RTE_PTYPE_INNER_L3_IPV6_EXT,
3775 RTE_PTYPE_INNER_L4_TCP,
3776 RTE_PTYPE_INNER_L4_UDP,
3780 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3781 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3782 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3783 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3786 #if defined(RTE_ARCH_X86)
3787 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3788 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3795 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3796 struct rte_eth_dev_info *dev_info)
3798 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3799 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3801 dev_info->pci_dev = pci_dev;
3802 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3803 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3804 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3805 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3806 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3807 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3808 dev_info->max_vfs = pci_dev->max_vfs;
3809 if (hw->mac.type == ixgbe_mac_82598EB)
3810 dev_info->max_vmdq_pools = ETH_16_POOLS;
3812 dev_info->max_vmdq_pools = ETH_64_POOLS;
3813 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3814 DEV_RX_OFFLOAD_IPV4_CKSUM |
3815 DEV_RX_OFFLOAD_UDP_CKSUM |
3816 DEV_RX_OFFLOAD_TCP_CKSUM;
3817 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3818 DEV_TX_OFFLOAD_IPV4_CKSUM |
3819 DEV_TX_OFFLOAD_UDP_CKSUM |
3820 DEV_TX_OFFLOAD_TCP_CKSUM |
3821 DEV_TX_OFFLOAD_SCTP_CKSUM |
3822 DEV_TX_OFFLOAD_TCP_TSO;
3824 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3826 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3827 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3828 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3830 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3834 dev_info->default_txconf = (struct rte_eth_txconf) {
3836 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3837 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3838 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3840 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3841 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3842 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3843 ETH_TXQ_FLAGS_NOOFFLOADS,
3846 dev_info->rx_desc_lim = rx_desc_lim;
3847 dev_info->tx_desc_lim = tx_desc_lim;
3851 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3852 int *link_up, int wait_to_complete)
3855 * for a quick link status checking, wait_to_compelet == 0,
3856 * skip PF link status checking
3858 bool no_pflink_check = wait_to_complete == 0;
3859 struct ixgbe_mbx_info *mbx = &hw->mbx;
3860 struct ixgbe_mac_info *mac = &hw->mac;
3861 uint32_t links_reg, in_msg;
3864 /* If we were hit with a reset drop the link */
3865 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3866 mac->get_link_status = true;
3868 if (!mac->get_link_status)
3871 /* if link status is down no point in checking to see if pf is up */
3872 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3873 if (!(links_reg & IXGBE_LINKS_UP))
3876 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3877 * before the link status is correct
3879 if (mac->type == ixgbe_mac_82599_vf) {
3882 for (i = 0; i < 5; i++) {
3884 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3886 if (!(links_reg & IXGBE_LINKS_UP))
3891 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3892 case IXGBE_LINKS_SPEED_10G_82599:
3893 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3894 if (hw->mac.type >= ixgbe_mac_X550) {
3895 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3896 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3899 case IXGBE_LINKS_SPEED_1G_82599:
3900 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3902 case IXGBE_LINKS_SPEED_100_82599:
3903 *speed = IXGBE_LINK_SPEED_100_FULL;
3904 if (hw->mac.type == ixgbe_mac_X550) {
3905 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3906 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3909 case IXGBE_LINKS_SPEED_10_X550EM_A:
3910 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3911 /* Since Reserved in older MAC's */
3912 if (hw->mac.type >= ixgbe_mac_X550)
3913 *speed = IXGBE_LINK_SPEED_10_FULL;
3916 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3919 if (no_pflink_check) {
3920 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3921 mac->get_link_status = true;
3923 mac->get_link_status = false;
3927 /* if the read failed it could just be a mailbox collision, best wait
3928 * until we are called again and don't report an error
3930 if (mbx->ops.read(hw, &in_msg, 1, 0))
3933 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3934 /* msg is not CTS and is NACK we must have lost CTS status */
3935 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3940 /* the pf is talking, if we timed out in the past we reinit */
3941 if (!mbx->timeout) {
3946 /* if we passed all the tests above then the link is up and we no
3947 * longer need to check for link
3949 mac->get_link_status = false;
3952 *link_up = !mac->get_link_status;
3956 /* return 0 means link status changed, -1 means not changed */
3958 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3959 int wait_to_complete, int vf)
3961 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3962 struct rte_eth_link link, old;
3963 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3964 struct ixgbe_interrupt *intr =
3965 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3970 bool autoneg = false;
3972 link.link_status = ETH_LINK_DOWN;
3973 link.link_speed = 0;
3974 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3975 link.link_autoneg = ETH_LINK_AUTONEG;
3976 memset(&old, 0, sizeof(old));
3977 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3979 hw->mac.get_link_status = true;
3981 if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3982 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3983 speed = hw->phy.autoneg_advertised;
3985 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3986 ixgbe_setup_link(hw, speed, true);
3989 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3990 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3994 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3996 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3999 link.link_speed = ETH_SPEED_NUM_100M;
4000 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4001 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4002 if (link.link_status == old.link_status)
4008 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4009 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4010 if (link.link_status == old.link_status)
4014 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4015 link.link_status = ETH_LINK_UP;
4016 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4018 switch (link_speed) {
4020 case IXGBE_LINK_SPEED_UNKNOWN:
4021 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4022 link.link_speed = ETH_SPEED_NUM_100M;
4025 case IXGBE_LINK_SPEED_100_FULL:
4026 link.link_speed = ETH_SPEED_NUM_100M;
4029 case IXGBE_LINK_SPEED_1GB_FULL:
4030 link.link_speed = ETH_SPEED_NUM_1G;
4033 case IXGBE_LINK_SPEED_2_5GB_FULL:
4034 link.link_speed = ETH_SPEED_NUM_2_5G;
4037 case IXGBE_LINK_SPEED_5GB_FULL:
4038 link.link_speed = ETH_SPEED_NUM_5G;
4041 case IXGBE_LINK_SPEED_10GB_FULL:
4042 link.link_speed = ETH_SPEED_NUM_10G;
4045 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4047 if (link.link_status == old.link_status)
4054 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4056 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4060 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4062 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4066 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4068 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4071 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4072 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4073 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4077 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4079 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4082 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4083 fctrl &= (~IXGBE_FCTRL_UPE);
4084 if (dev->data->all_multicast == 1)
4085 fctrl |= IXGBE_FCTRL_MPE;
4087 fctrl &= (~IXGBE_FCTRL_MPE);
4088 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4092 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4094 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4097 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4098 fctrl |= IXGBE_FCTRL_MPE;
4099 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4103 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4105 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4108 if (dev->data->promiscuous == 1)
4109 return; /* must remain in all_multicast mode */
4111 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4112 fctrl &= (~IXGBE_FCTRL_MPE);
4113 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4117 * It clears the interrupt causes and enables the interrupt.
4118 * It will be called once only during nic initialized.
4121 * Pointer to struct rte_eth_dev.
4123 * Enable or Disable.
4126 * - On success, zero.
4127 * - On failure, a negative value.
4130 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4132 struct ixgbe_interrupt *intr =
4133 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4135 ixgbe_dev_link_status_print(dev);
4137 intr->mask |= IXGBE_EICR_LSC;
4139 intr->mask &= ~IXGBE_EICR_LSC;
4145 * It clears the interrupt causes and enables the interrupt.
4146 * It will be called once only during nic initialized.
4149 * Pointer to struct rte_eth_dev.
4152 * - On success, zero.
4153 * - On failure, a negative value.
4156 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4158 struct ixgbe_interrupt *intr =
4159 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4161 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4167 * It clears the interrupt causes and enables the interrupt.
4168 * It will be called once only during nic initialized.
4171 * Pointer to struct rte_eth_dev.
4174 * - On success, zero.
4175 * - On failure, a negative value.
4178 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4180 struct ixgbe_interrupt *intr =
4181 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4183 intr->mask |= IXGBE_EICR_LINKSEC;
4189 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4192 * Pointer to struct rte_eth_dev.
4195 * - On success, zero.
4196 * - On failure, a negative value.
4199 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4202 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4203 struct ixgbe_interrupt *intr =
4204 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4206 /* clear all cause mask */
4207 ixgbe_disable_intr(hw);
4209 /* read-on-clear nic registers here */
4210 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4211 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4215 /* set flag for async link update */
4216 if (eicr & IXGBE_EICR_LSC)
4217 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4219 if (eicr & IXGBE_EICR_MAILBOX)
4220 intr->flags |= IXGBE_FLAG_MAILBOX;
4222 if (eicr & IXGBE_EICR_LINKSEC)
4223 intr->flags |= IXGBE_FLAG_MACSEC;
4225 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4226 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4227 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4228 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4234 * It gets and then prints the link status.
4237 * Pointer to struct rte_eth_dev.
4240 * - On success, zero.
4241 * - On failure, a negative value.
4244 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4246 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4247 struct rte_eth_link link;
4249 memset(&link, 0, sizeof(link));
4250 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4251 if (link.link_status) {
4252 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4253 (int)(dev->data->port_id),
4254 (unsigned)link.link_speed,
4255 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4256 "full-duplex" : "half-duplex");
4258 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4259 (int)(dev->data->port_id));
4261 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4262 pci_dev->addr.domain,
4264 pci_dev->addr.devid,
4265 pci_dev->addr.function);
4269 * It executes link_update after knowing an interrupt occurred.
4272 * Pointer to struct rte_eth_dev.
4275 * - On success, zero.
4276 * - On failure, a negative value.
4279 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4280 struct rte_intr_handle *intr_handle)
4282 struct ixgbe_interrupt *intr =
4283 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4285 struct rte_eth_link link;
4286 struct ixgbe_hw *hw =
4287 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4289 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4291 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4292 ixgbe_pf_mbx_process(dev);
4293 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4296 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4297 ixgbe_handle_lasi(hw);
4298 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4301 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4302 /* get the link status before link update, for predicting later */
4303 memset(&link, 0, sizeof(link));
4304 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4306 ixgbe_dev_link_update(dev, 0);
4309 if (!link.link_status)
4310 /* handle it 1 sec later, wait it being stable */
4311 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4312 /* likely to down */
4314 /* handle it 4 sec later, wait it being stable */
4315 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4317 ixgbe_dev_link_status_print(dev);
4318 if (rte_eal_alarm_set(timeout * 1000,
4319 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4320 PMD_DRV_LOG(ERR, "Error setting alarm");
4322 /* remember original mask */
4323 intr->mask_original = intr->mask;
4324 /* only disable lsc interrupt */
4325 intr->mask &= ~IXGBE_EIMS_LSC;
4329 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4330 ixgbe_enable_intr(dev);
4331 rte_intr_enable(intr_handle);
4337 * Interrupt handler which shall be registered for alarm callback for delayed
4338 * handling specific interrupt to wait for the stable nic state. As the
4339 * NIC interrupt state is not stable for ixgbe after link is just down,
4340 * it needs to wait 4 seconds to get the stable status.
4343 * Pointer to interrupt handle.
4345 * The address of parameter (struct rte_eth_dev *) regsitered before.
4351 ixgbe_dev_interrupt_delayed_handler(void *param)
4353 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4354 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4355 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4356 struct ixgbe_interrupt *intr =
4357 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4358 struct ixgbe_hw *hw =
4359 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4362 ixgbe_disable_intr(hw);
4364 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4365 if (eicr & IXGBE_EICR_MAILBOX)
4366 ixgbe_pf_mbx_process(dev);
4368 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4369 ixgbe_handle_lasi(hw);
4370 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4373 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4374 ixgbe_dev_link_update(dev, 0);
4375 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4376 ixgbe_dev_link_status_print(dev);
4377 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4381 if (intr->flags & IXGBE_FLAG_MACSEC) {
4382 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4384 intr->flags &= ~IXGBE_FLAG_MACSEC;
4387 /* restore original mask */
4388 intr->mask = intr->mask_original;
4389 intr->mask_original = 0;
4391 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4392 ixgbe_enable_intr(dev);
4393 rte_intr_enable(intr_handle);
4397 * Interrupt handler triggered by NIC for handling
4398 * specific interrupt.
4401 * Pointer to interrupt handle.
4403 * The address of parameter (struct rte_eth_dev *) regsitered before.
4409 ixgbe_dev_interrupt_handler(void *param)
4411 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4413 ixgbe_dev_interrupt_get_status(dev);
4414 ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4418 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4420 struct ixgbe_hw *hw;
4422 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4423 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4427 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4429 struct ixgbe_hw *hw;
4431 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4432 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4436 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4438 struct ixgbe_hw *hw;
4444 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4446 fc_conf->pause_time = hw->fc.pause_time;
4447 fc_conf->high_water = hw->fc.high_water[0];
4448 fc_conf->low_water = hw->fc.low_water[0];
4449 fc_conf->send_xon = hw->fc.send_xon;
4450 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4453 * Return rx_pause status according to actual setting of
4456 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4457 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4463 * Return tx_pause status according to actual setting of
4466 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4467 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4472 if (rx_pause && tx_pause)
4473 fc_conf->mode = RTE_FC_FULL;
4475 fc_conf->mode = RTE_FC_RX_PAUSE;
4477 fc_conf->mode = RTE_FC_TX_PAUSE;
4479 fc_conf->mode = RTE_FC_NONE;
4485 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4487 struct ixgbe_hw *hw;
4489 uint32_t rx_buf_size;
4490 uint32_t max_high_water;
4492 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4499 PMD_INIT_FUNC_TRACE();
4501 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4502 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4503 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4506 * At least reserve one Ethernet frame for watermark
4507 * high_water/low_water in kilo bytes for ixgbe
4509 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4510 if ((fc_conf->high_water > max_high_water) ||
4511 (fc_conf->high_water < fc_conf->low_water)) {
4512 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4513 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4517 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4518 hw->fc.pause_time = fc_conf->pause_time;
4519 hw->fc.high_water[0] = fc_conf->high_water;
4520 hw->fc.low_water[0] = fc_conf->low_water;
4521 hw->fc.send_xon = fc_conf->send_xon;
4522 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4524 err = ixgbe_fc_enable(hw);
4526 /* Not negotiated is not an error case */
4527 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4529 /* check if we want to forward MAC frames - driver doesn't have native
4530 * capability to do that, so we'll write the registers ourselves */
4532 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4534 /* set or clear MFLCN.PMCF bit depending on configuration */
4535 if (fc_conf->mac_ctrl_frame_fwd != 0)
4536 mflcn |= IXGBE_MFLCN_PMCF;
4538 mflcn &= ~IXGBE_MFLCN_PMCF;
4540 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4541 IXGBE_WRITE_FLUSH(hw);
4546 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4551 * ixgbe_pfc_enable_generic - Enable flow control
4552 * @hw: pointer to hardware structure
4553 * @tc_num: traffic class number
4554 * Enable flow control according to the current settings.
4557 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4560 uint32_t mflcn_reg, fccfg_reg;
4562 uint32_t fcrtl, fcrth;
4566 /* Validate the water mark configuration */
4567 if (!hw->fc.pause_time) {
4568 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4572 /* Low water mark of zero causes XOFF floods */
4573 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4574 /* High/Low water can not be 0 */
4575 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4576 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4577 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4581 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4582 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4583 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4587 /* Negotiate the fc mode to use */
4588 ixgbe_fc_autoneg(hw);
4590 /* Disable any previous flow control settings */
4591 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4592 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4594 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4595 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4597 switch (hw->fc.current_mode) {
4600 * If the count of enabled RX Priority Flow control >1,
4601 * and the TX pause can not be disabled
4604 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4605 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4606 if (reg & IXGBE_FCRTH_FCEN)
4610 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4612 case ixgbe_fc_rx_pause:
4614 * Rx Flow control is enabled and Tx Flow control is
4615 * disabled by software override. Since there really
4616 * isn't a way to advertise that we are capable of RX
4617 * Pause ONLY, we will advertise that we support both
4618 * symmetric and asymmetric Rx PAUSE. Later, we will
4619 * disable the adapter's ability to send PAUSE frames.
4621 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4623 * If the count of enabled RX Priority Flow control >1,
4624 * and the TX pause can not be disabled
4627 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4628 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4629 if (reg & IXGBE_FCRTH_FCEN)
4633 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4635 case ixgbe_fc_tx_pause:
4637 * Tx Flow control is enabled, and Rx Flow control is
4638 * disabled by software override.
4640 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4643 /* Flow control (both Rx and Tx) is enabled by SW override. */
4644 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4645 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4648 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4649 ret_val = IXGBE_ERR_CONFIG;
4653 /* Set 802.3x based flow control settings. */
4654 mflcn_reg |= IXGBE_MFLCN_DPF;
4655 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4656 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4658 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4659 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4660 hw->fc.high_water[tc_num]) {
4661 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4662 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4663 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4665 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4667 * In order to prevent Tx hangs when the internal Tx
4668 * switch is enabled we must set the high water mark
4669 * to the maximum FCRTH value. This allows the Tx
4670 * switch to function even under heavy Rx workloads.
4672 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4674 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4676 /* Configure pause time (2 TCs per register) */
4677 reg = hw->fc.pause_time * 0x00010001;
4678 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4679 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4681 /* Configure flow control refresh threshold value */
4682 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4689 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4691 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4692 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4694 if (hw->mac.type != ixgbe_mac_82598EB) {
4695 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4701 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4704 uint32_t rx_buf_size;
4705 uint32_t max_high_water;
4707 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4708 struct ixgbe_hw *hw =
4709 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4710 struct ixgbe_dcb_config *dcb_config =
4711 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4713 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4720 PMD_INIT_FUNC_TRACE();
4722 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4723 tc_num = map[pfc_conf->priority];
4724 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4725 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4727 * At least reserve one Ethernet frame for watermark
4728 * high_water/low_water in kilo bytes for ixgbe
4730 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4731 if ((pfc_conf->fc.high_water > max_high_water) ||
4732 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4733 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4734 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4738 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4739 hw->fc.pause_time = pfc_conf->fc.pause_time;
4740 hw->fc.send_xon = pfc_conf->fc.send_xon;
4741 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4742 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4744 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4746 /* Not negotiated is not an error case */
4747 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4750 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4755 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4756 struct rte_eth_rss_reta_entry64 *reta_conf,
4759 uint16_t i, sp_reta_size;
4762 uint16_t idx, shift;
4763 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4766 PMD_INIT_FUNC_TRACE();
4768 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4769 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4774 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4775 if (reta_size != sp_reta_size) {
4776 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4777 "(%d) doesn't match the number hardware can supported "
4778 "(%d)", reta_size, sp_reta_size);
4782 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4783 idx = i / RTE_RETA_GROUP_SIZE;
4784 shift = i % RTE_RETA_GROUP_SIZE;
4785 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4789 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4790 if (mask == IXGBE_4_BIT_MASK)
4793 r = IXGBE_READ_REG(hw, reta_reg);
4794 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4795 if (mask & (0x1 << j))
4796 reta |= reta_conf[idx].reta[shift + j] <<
4799 reta |= r & (IXGBE_8_BIT_MASK <<
4802 IXGBE_WRITE_REG(hw, reta_reg, reta);
4809 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4810 struct rte_eth_rss_reta_entry64 *reta_conf,
4813 uint16_t i, sp_reta_size;
4816 uint16_t idx, shift;
4817 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4820 PMD_INIT_FUNC_TRACE();
4821 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4822 if (reta_size != sp_reta_size) {
4823 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4824 "(%d) doesn't match the number hardware can supported "
4825 "(%d)", reta_size, sp_reta_size);
4829 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4830 idx = i / RTE_RETA_GROUP_SIZE;
4831 shift = i % RTE_RETA_GROUP_SIZE;
4832 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4837 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4838 reta = IXGBE_READ_REG(hw, reta_reg);
4839 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4840 if (mask & (0x1 << j))
4841 reta_conf[idx].reta[shift + j] =
4842 ((reta >> (CHAR_BIT * j)) &
4851 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4852 uint32_t index, uint32_t pool)
4854 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4855 uint32_t enable_addr = 1;
4857 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4862 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4864 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4866 ixgbe_clear_rar(hw, index);
4870 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4872 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4874 ixgbe_remove_rar(dev, 0);
4876 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4880 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4882 if (strcmp(dev->device->driver->name, drv->driver.name))
4889 is_ixgbe_supported(struct rte_eth_dev *dev)
4891 return is_device_supported(dev, &rte_ixgbe_pmd);
4895 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4899 struct ixgbe_hw *hw;
4900 struct rte_eth_dev_info dev_info;
4901 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4902 struct rte_eth_dev_data *dev_data = dev->data;
4904 ixgbe_dev_info_get(dev, &dev_info);
4906 /* check that mtu is within the allowed range */
4907 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4910 /* If device is started, refuse mtu that requires the support of
4911 * scattered packets when this feature has not been enabled before.
4913 if (dev_data->dev_started && !dev_data->scattered_rx &&
4914 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4915 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4916 PMD_INIT_LOG(ERR, "Stop port first.");
4920 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4921 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4923 /* switch to jumbo mode if needed */
4924 if (frame_size > ETHER_MAX_LEN) {
4925 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4926 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4928 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4929 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4931 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4933 /* update max frame size */
4934 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4936 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4937 maxfrs &= 0x0000FFFF;
4938 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4939 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4945 * Virtual Function operations
4948 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4950 PMD_INIT_FUNC_TRACE();
4952 /* Clear interrupt mask to stop from interrupts being generated */
4953 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4955 IXGBE_WRITE_FLUSH(hw);
4959 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4961 PMD_INIT_FUNC_TRACE();
4963 /* VF enable interrupt autoclean */
4964 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4965 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4966 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4968 IXGBE_WRITE_FLUSH(hw);
4972 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4974 struct rte_eth_conf *conf = &dev->data->dev_conf;
4975 struct ixgbe_adapter *adapter =
4976 (struct ixgbe_adapter *)dev->data->dev_private;
4978 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4979 dev->data->port_id);
4982 * VF has no ability to enable/disable HW CRC
4983 * Keep the persistent behavior the same as Host PF
4985 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4986 if (!conf->rxmode.hw_strip_crc) {
4987 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4988 conf->rxmode.hw_strip_crc = 1;
4991 if (conf->rxmode.hw_strip_crc) {
4992 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4993 conf->rxmode.hw_strip_crc = 0;
4998 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4999 * allocation or vector Rx preconditions we will reset it.
5001 adapter->rx_bulk_alloc_allowed = true;
5002 adapter->rx_vec_allowed = true;
5008 ixgbevf_dev_start(struct rte_eth_dev *dev)
5010 struct ixgbe_hw *hw =
5011 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5012 uint32_t intr_vector = 0;
5013 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5014 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5018 PMD_INIT_FUNC_TRACE();
5020 hw->mac.ops.reset_hw(hw);
5021 hw->mac.get_link_status = true;
5023 /* negotiate mailbox API version to use with the PF. */
5024 ixgbevf_negotiate_api(hw);
5026 ixgbevf_dev_tx_init(dev);
5028 /* This can fail when allocating mbufs for descriptor rings */
5029 err = ixgbevf_dev_rx_init(dev);
5031 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5032 ixgbe_dev_clear_queues(dev);
5037 ixgbevf_set_vfta_all(dev, 1);
5040 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5041 ETH_VLAN_EXTEND_MASK;
5042 err = ixgbevf_vlan_offload_set(dev, mask);
5044 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5045 ixgbe_dev_clear_queues(dev);
5049 ixgbevf_dev_rxtx_start(dev);
5051 /* check and configure queue intr-vector mapping */
5052 if (dev->data->dev_conf.intr_conf.rxq != 0) {
5053 /* According to datasheet, only vector 0/1/2 can be used,
5054 * now only one vector is used for Rx queue
5057 if (rte_intr_efd_enable(intr_handle, intr_vector))
5061 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5062 intr_handle->intr_vec =
5063 rte_zmalloc("intr_vec",
5064 dev->data->nb_rx_queues * sizeof(int), 0);
5065 if (intr_handle->intr_vec == NULL) {
5066 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5067 " intr_vec", dev->data->nb_rx_queues);
5071 ixgbevf_configure_msix(dev);
5073 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5074 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5075 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5076 * is not cleared, it will fail when following rte_intr_enable( ) tries
5077 * to map Rx queue interrupt to other VFIO vectors.
5078 * So clear uio/vfio intr/evevnfd first to avoid failure.
5080 rte_intr_disable(intr_handle);
5082 rte_intr_enable(intr_handle);
5084 /* Re-enable interrupt for VF */
5085 ixgbevf_intr_enable(hw);
5091 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5093 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5094 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5095 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5097 PMD_INIT_FUNC_TRACE();
5099 ixgbevf_intr_disable(hw);
5101 hw->adapter_stopped = 1;
5102 ixgbe_stop_adapter(hw);
5105 * Clear what we set, but we still keep shadow_vfta to
5106 * restore after device starts
5108 ixgbevf_set_vfta_all(dev, 0);
5110 /* Clear stored conf */
5111 dev->data->scattered_rx = 0;
5113 ixgbe_dev_clear_queues(dev);
5115 /* Clean datapath event and queue/vec mapping */
5116 rte_intr_efd_disable(intr_handle);
5117 if (intr_handle->intr_vec != NULL) {
5118 rte_free(intr_handle->intr_vec);
5119 intr_handle->intr_vec = NULL;
5124 ixgbevf_dev_close(struct rte_eth_dev *dev)
5126 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5128 PMD_INIT_FUNC_TRACE();
5132 ixgbevf_dev_stop(dev);
5134 ixgbe_dev_free_queues(dev);
5137 * Remove the VF MAC address ro ensure
5138 * that the VF traffic goes to the PF
5139 * after stop, close and detach of the VF
5141 ixgbevf_remove_mac_addr(dev, 0);
5148 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5152 ret = eth_ixgbevf_dev_uninit(dev);
5156 ret = eth_ixgbevf_dev_init(dev);
5161 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5163 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5164 struct ixgbe_vfta *shadow_vfta =
5165 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5166 int i = 0, j = 0, vfta = 0, mask = 1;
5168 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5169 vfta = shadow_vfta->vfta[i];
5172 for (j = 0; j < 32; j++) {
5174 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5184 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5186 struct ixgbe_hw *hw =
5187 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5188 struct ixgbe_vfta *shadow_vfta =
5189 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5190 uint32_t vid_idx = 0;
5191 uint32_t vid_bit = 0;
5194 PMD_INIT_FUNC_TRACE();
5196 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5197 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5199 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5202 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5203 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5205 /* Save what we set and retore it after device reset */
5207 shadow_vfta->vfta[vid_idx] |= vid_bit;
5209 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5215 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5217 struct ixgbe_hw *hw =
5218 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5221 PMD_INIT_FUNC_TRACE();
5223 if (queue >= hw->mac.max_rx_queues)
5226 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5228 ctrl |= IXGBE_RXDCTL_VME;
5230 ctrl &= ~IXGBE_RXDCTL_VME;
5231 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5233 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5237 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5239 struct ixgbe_hw *hw =
5240 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5244 /* VF function only support hw strip feature, others are not support */
5245 if (mask & ETH_VLAN_STRIP_MASK) {
5246 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5248 for (i = 0; i < hw->mac.max_rx_queues; i++)
5249 ixgbevf_vlan_strip_queue_set(dev, i, on);
5256 ixgbe_vt_check(struct ixgbe_hw *hw)
5260 /* if Virtualization Technology is enabled */
5261 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5262 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5263 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5271 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5273 uint32_t vector = 0;
5275 switch (hw->mac.mc_filter_type) {
5276 case 0: /* use bits [47:36] of the address */
5277 vector = ((uc_addr->addr_bytes[4] >> 4) |
5278 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5280 case 1: /* use bits [46:35] of the address */
5281 vector = ((uc_addr->addr_bytes[4] >> 3) |
5282 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5284 case 2: /* use bits [45:34] of the address */
5285 vector = ((uc_addr->addr_bytes[4] >> 2) |
5286 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5288 case 3: /* use bits [43:32] of the address */
5289 vector = ((uc_addr->addr_bytes[4]) |
5290 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5292 default: /* Invalid mc_filter_type */
5296 /* vector can only be 12-bits or boundary will be exceeded */
5302 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5310 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5311 const uint32_t ixgbe_uta_bit_shift = 5;
5312 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5313 const uint32_t bit1 = 0x1;
5315 struct ixgbe_hw *hw =
5316 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5317 struct ixgbe_uta_info *uta_info =
5318 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5320 /* The UTA table only exists on 82599 hardware and newer */
5321 if (hw->mac.type < ixgbe_mac_82599EB)
5324 vector = ixgbe_uta_vector(hw, mac_addr);
5325 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5326 uta_shift = vector & ixgbe_uta_bit_mask;
5328 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5332 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5334 uta_info->uta_in_use++;
5335 reg_val |= (bit1 << uta_shift);
5336 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5338 uta_info->uta_in_use--;
5339 reg_val &= ~(bit1 << uta_shift);
5340 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5343 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5345 if (uta_info->uta_in_use > 0)
5346 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5347 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5349 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5355 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5358 struct ixgbe_hw *hw =
5359 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5360 struct ixgbe_uta_info *uta_info =
5361 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5363 /* The UTA table only exists on 82599 hardware and newer */
5364 if (hw->mac.type < ixgbe_mac_82599EB)
5368 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5369 uta_info->uta_shadow[i] = ~0;
5370 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5373 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5374 uta_info->uta_shadow[i] = 0;
5375 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5383 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5385 uint32_t new_val = orig_val;
5387 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5388 new_val |= IXGBE_VMOLR_AUPE;
5389 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5390 new_val |= IXGBE_VMOLR_ROMPE;
5391 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5392 new_val |= IXGBE_VMOLR_ROPE;
5393 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5394 new_val |= IXGBE_VMOLR_BAM;
5395 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5396 new_val |= IXGBE_VMOLR_MPE;
5401 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5402 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5403 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5404 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5405 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5406 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5407 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5410 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5411 struct rte_eth_mirror_conf *mirror_conf,
5412 uint8_t rule_id, uint8_t on)
5414 uint32_t mr_ctl, vlvf;
5415 uint32_t mp_lsb = 0;
5416 uint32_t mv_msb = 0;
5417 uint32_t mv_lsb = 0;
5418 uint32_t mp_msb = 0;
5421 uint64_t vlan_mask = 0;
5423 const uint8_t pool_mask_offset = 32;
5424 const uint8_t vlan_mask_offset = 32;
5425 const uint8_t dst_pool_offset = 8;
5426 const uint8_t rule_mr_offset = 4;
5427 const uint8_t mirror_rule_mask = 0x0F;
5429 struct ixgbe_mirror_info *mr_info =
5430 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5431 struct ixgbe_hw *hw =
5432 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5433 uint8_t mirror_type = 0;
5435 if (ixgbe_vt_check(hw) < 0)
5438 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5441 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5442 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5443 mirror_conf->rule_type);
5447 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5448 mirror_type |= IXGBE_MRCTL_VLME;
5449 /* Check if vlan id is valid and find conresponding VLAN ID
5452 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5453 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5454 /* search vlan id related pool vlan filter
5457 reg_index = ixgbe_find_vlvf_slot(
5459 mirror_conf->vlan.vlan_id[i],
5463 vlvf = IXGBE_READ_REG(hw,
5464 IXGBE_VLVF(reg_index));
5465 if ((vlvf & IXGBE_VLVF_VIEN) &&
5466 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5467 mirror_conf->vlan.vlan_id[i]))
5468 vlan_mask |= (1ULL << reg_index);
5475 mv_lsb = vlan_mask & 0xFFFFFFFF;
5476 mv_msb = vlan_mask >> vlan_mask_offset;
5478 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5479 mirror_conf->vlan.vlan_mask;
5480 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5481 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5482 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5483 mirror_conf->vlan.vlan_id[i];
5488 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5489 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5490 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5495 * if enable pool mirror, write related pool mask register,if disable
5496 * pool mirror, clear PFMRVM register
5498 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5499 mirror_type |= IXGBE_MRCTL_VPME;
5501 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5502 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5503 mr_info->mr_conf[rule_id].pool_mask =
5504 mirror_conf->pool_mask;
5509 mr_info->mr_conf[rule_id].pool_mask = 0;
5512 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5513 mirror_type |= IXGBE_MRCTL_UPME;
5514 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5515 mirror_type |= IXGBE_MRCTL_DPME;
5517 /* read mirror control register and recalculate it */
5518 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5521 mr_ctl |= mirror_type;
5522 mr_ctl &= mirror_rule_mask;
5523 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5525 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5528 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5529 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5531 /* write mirrror control register */
5532 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5534 /* write pool mirrror control register */
5535 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5536 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5537 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5540 /* write VLAN mirrror control register */
5541 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5542 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5543 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5551 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5554 uint32_t lsb_val = 0;
5555 uint32_t msb_val = 0;
5556 const uint8_t rule_mr_offset = 4;
5558 struct ixgbe_hw *hw =
5559 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5560 struct ixgbe_mirror_info *mr_info =
5561 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5563 if (ixgbe_vt_check(hw) < 0)
5566 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5569 memset(&mr_info->mr_conf[rule_id], 0,
5570 sizeof(struct rte_eth_mirror_conf));
5572 /* clear PFVMCTL register */
5573 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5575 /* clear pool mask register */
5576 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5577 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5579 /* clear vlan mask register */
5580 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5581 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5587 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5589 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5590 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5592 struct ixgbe_hw *hw =
5593 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5594 uint32_t vec = IXGBE_MISC_VEC_ID;
5596 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5597 if (rte_intr_allow_others(intr_handle))
5598 vec = IXGBE_RX_VEC_START;
5600 RTE_SET_USED(queue_id);
5601 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5603 rte_intr_enable(intr_handle);
5609 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5612 struct ixgbe_hw *hw =
5613 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5614 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5615 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5616 uint32_t vec = IXGBE_MISC_VEC_ID;
5618 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5619 if (rte_intr_allow_others(intr_handle))
5620 vec = IXGBE_RX_VEC_START;
5621 mask &= ~(1 << vec);
5622 RTE_SET_USED(queue_id);
5623 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5629 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5631 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5632 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5634 struct ixgbe_hw *hw =
5635 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5636 struct ixgbe_interrupt *intr =
5637 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5639 if (queue_id < 16) {
5640 ixgbe_disable_intr(hw);
5641 intr->mask |= (1 << queue_id);
5642 ixgbe_enable_intr(dev);
5643 } else if (queue_id < 32) {
5644 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5645 mask &= (1 << queue_id);
5646 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5647 } else if (queue_id < 64) {
5648 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5649 mask &= (1 << (queue_id - 32));
5650 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5652 rte_intr_enable(intr_handle);
5658 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5661 struct ixgbe_hw *hw =
5662 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5663 struct ixgbe_interrupt *intr =
5664 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5666 if (queue_id < 16) {
5667 ixgbe_disable_intr(hw);
5668 intr->mask &= ~(1 << queue_id);
5669 ixgbe_enable_intr(dev);
5670 } else if (queue_id < 32) {
5671 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5672 mask &= ~(1 << queue_id);
5673 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5674 } else if (queue_id < 64) {
5675 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5676 mask &= ~(1 << (queue_id - 32));
5677 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5684 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5685 uint8_t queue, uint8_t msix_vector)
5689 if (direction == -1) {
5691 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5692 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5695 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5697 /* rx or tx cause */
5698 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5699 idx = ((16 * (queue & 1)) + (8 * direction));
5700 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5701 tmp &= ~(0xFF << idx);
5702 tmp |= (msix_vector << idx);
5703 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5708 * set the IVAR registers, mapping interrupt causes to vectors
5710 * pointer to ixgbe_hw struct
5712 * 0 for Rx, 1 for Tx, -1 for other causes
5714 * queue to map the corresponding interrupt to
5716 * the vector to map to the corresponding queue
5719 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5720 uint8_t queue, uint8_t msix_vector)
5724 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5725 if (hw->mac.type == ixgbe_mac_82598EB) {
5726 if (direction == -1)
5728 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5729 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5730 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5731 tmp |= (msix_vector << (8 * (queue & 0x3)));
5732 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5733 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5734 (hw->mac.type == ixgbe_mac_X540) ||
5735 (hw->mac.type == ixgbe_mac_X550)) {
5736 if (direction == -1) {
5738 idx = ((queue & 1) * 8);
5739 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5740 tmp &= ~(0xFF << idx);
5741 tmp |= (msix_vector << idx);
5742 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5744 /* rx or tx causes */
5745 idx = ((16 * (queue & 1)) + (8 * direction));
5746 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5747 tmp &= ~(0xFF << idx);
5748 tmp |= (msix_vector << idx);
5749 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5755 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5757 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5758 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5759 struct ixgbe_hw *hw =
5760 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5762 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5763 uint32_t base = IXGBE_MISC_VEC_ID;
5765 /* Configure VF other cause ivar */
5766 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5768 /* won't configure msix register if no mapping is done
5769 * between intr vector and event fd.
5771 if (!rte_intr_dp_is_en(intr_handle))
5774 if (rte_intr_allow_others(intr_handle)) {
5775 base = IXGBE_RX_VEC_START;
5776 vector_idx = IXGBE_RX_VEC_START;
5779 /* Configure all RX queues of VF */
5780 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5781 /* Force all queue use vector 0,
5782 * as IXGBE_VF_MAXMSIVECOTR = 1
5784 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5785 intr_handle->intr_vec[q_idx] = vector_idx;
5786 if (vector_idx < base + intr_handle->nb_efd - 1)
5792 * Sets up the hardware to properly generate MSI-X interrupts
5794 * board private structure
5797 ixgbe_configure_msix(struct rte_eth_dev *dev)
5799 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5800 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5801 struct ixgbe_hw *hw =
5802 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5803 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5804 uint32_t vec = IXGBE_MISC_VEC_ID;
5808 /* won't configure msix register if no mapping is done
5809 * between intr vector and event fd
5811 if (!rte_intr_dp_is_en(intr_handle))
5814 if (rte_intr_allow_others(intr_handle))
5815 vec = base = IXGBE_RX_VEC_START;
5817 /* setup GPIE for MSI-x mode */
5818 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5819 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5820 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5821 /* auto clearing and auto setting corresponding bits in EIMS
5822 * when MSI-X interrupt is triggered
5824 if (hw->mac.type == ixgbe_mac_82598EB) {
5825 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5827 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5828 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5830 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5832 /* Populate the IVAR table and set the ITR values to the
5833 * corresponding register.
5835 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5837 /* by default, 1:1 mapping */
5838 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5839 intr_handle->intr_vec[queue_id] = vec;
5840 if (vec < base + intr_handle->nb_efd - 1)
5844 switch (hw->mac.type) {
5845 case ixgbe_mac_82598EB:
5846 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5849 case ixgbe_mac_82599EB:
5850 case ixgbe_mac_X540:
5851 case ixgbe_mac_X550:
5852 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5857 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5858 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5860 /* set up to autoclear timer, and the vectors */
5861 mask = IXGBE_EIMS_ENABLE_MASK;
5862 mask &= ~(IXGBE_EIMS_OTHER |
5863 IXGBE_EIMS_MAILBOX |
5866 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5870 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5871 uint16_t queue_idx, uint16_t tx_rate)
5873 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5874 uint32_t rf_dec, rf_int;
5876 uint16_t link_speed = dev->data->dev_link.link_speed;
5878 if (queue_idx >= hw->mac.max_tx_queues)
5882 /* Calculate the rate factor values to set */
5883 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5884 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5885 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5887 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5888 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5889 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5890 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5896 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5897 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5900 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5901 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5902 IXGBE_MAX_JUMBO_FRAME_SIZE))
5903 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5904 IXGBE_MMW_SIZE_JUMBO_FRAME);
5906 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5907 IXGBE_MMW_SIZE_DEFAULT);
5909 /* Set RTTBCNRC of queue X */
5910 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5911 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5912 IXGBE_WRITE_FLUSH(hw);
5918 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5919 __attribute__((unused)) uint32_t index,
5920 __attribute__((unused)) uint32_t pool)
5922 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5926 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5927 * operation. Trap this case to avoid exhausting the [very limited]
5928 * set of PF resources used to store VF MAC addresses.
5930 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5932 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5934 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5935 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5936 mac_addr->addr_bytes[0],
5937 mac_addr->addr_bytes[1],
5938 mac_addr->addr_bytes[2],
5939 mac_addr->addr_bytes[3],
5940 mac_addr->addr_bytes[4],
5941 mac_addr->addr_bytes[5],
5947 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5949 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5950 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5951 struct ether_addr *mac_addr;
5956 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5957 * not support the deletion of a given MAC address.
5958 * Instead, it imposes to delete all MAC addresses, then to add again
5959 * all MAC addresses with the exception of the one to be deleted.
5961 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5964 * Add again all MAC addresses, with the exception of the deleted one
5965 * and of the permanent MAC address.
5967 for (i = 0, mac_addr = dev->data->mac_addrs;
5968 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5969 /* Skip the deleted MAC address */
5972 /* Skip NULL MAC addresses */
5973 if (is_zero_ether_addr(mac_addr))
5975 /* Skip the permanent MAC address */
5976 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5978 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5981 "Adding again MAC address "
5982 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5984 mac_addr->addr_bytes[0],
5985 mac_addr->addr_bytes[1],
5986 mac_addr->addr_bytes[2],
5987 mac_addr->addr_bytes[3],
5988 mac_addr->addr_bytes[4],
5989 mac_addr->addr_bytes[5],
5995 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5997 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5999 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6003 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6004 struct rte_eth_syn_filter *filter,
6007 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6008 struct ixgbe_filter_info *filter_info =
6009 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6013 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6016 syn_info = filter_info->syn_info;
6019 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6021 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6022 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6024 if (filter->hig_pri)
6025 synqf |= IXGBE_SYN_FILTER_SYNQFP;
6027 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6029 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6030 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6032 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6035 filter_info->syn_info = synqf;
6036 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6037 IXGBE_WRITE_FLUSH(hw);
6042 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6043 struct rte_eth_syn_filter *filter)
6045 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6046 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6048 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6049 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6050 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6057 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6058 enum rte_filter_op filter_op,
6061 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6064 MAC_TYPE_FILTER_SUP(hw->mac.type);
6066 if (filter_op == RTE_ETH_FILTER_NOP)
6070 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6075 switch (filter_op) {
6076 case RTE_ETH_FILTER_ADD:
6077 ret = ixgbe_syn_filter_set(dev,
6078 (struct rte_eth_syn_filter *)arg,
6081 case RTE_ETH_FILTER_DELETE:
6082 ret = ixgbe_syn_filter_set(dev,
6083 (struct rte_eth_syn_filter *)arg,
6086 case RTE_ETH_FILTER_GET:
6087 ret = ixgbe_syn_filter_get(dev,
6088 (struct rte_eth_syn_filter *)arg);
6091 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6100 static inline enum ixgbe_5tuple_protocol
6101 convert_protocol_type(uint8_t protocol_value)
6103 if (protocol_value == IPPROTO_TCP)
6104 return IXGBE_FILTER_PROTOCOL_TCP;
6105 else if (protocol_value == IPPROTO_UDP)
6106 return IXGBE_FILTER_PROTOCOL_UDP;
6107 else if (protocol_value == IPPROTO_SCTP)
6108 return IXGBE_FILTER_PROTOCOL_SCTP;
6110 return IXGBE_FILTER_PROTOCOL_NONE;
6113 /* inject a 5-tuple filter to HW */
6115 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6116 struct ixgbe_5tuple_filter *filter)
6118 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6120 uint32_t ftqf, sdpqf;
6121 uint32_t l34timir = 0;
6122 uint8_t mask = 0xff;
6126 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6127 IXGBE_SDPQF_DSTPORT_SHIFT);
6128 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6130 ftqf = (uint32_t)(filter->filter_info.proto &
6131 IXGBE_FTQF_PROTOCOL_MASK);
6132 ftqf |= (uint32_t)((filter->filter_info.priority &
6133 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6134 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6135 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6136 if (filter->filter_info.dst_ip_mask == 0)
6137 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6138 if (filter->filter_info.src_port_mask == 0)
6139 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6140 if (filter->filter_info.dst_port_mask == 0)
6141 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6142 if (filter->filter_info.proto_mask == 0)
6143 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6144 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6145 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6146 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6148 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6149 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6150 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6151 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6153 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6154 l34timir |= (uint32_t)(filter->queue <<
6155 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6156 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6160 * add a 5tuple filter
6163 * dev: Pointer to struct rte_eth_dev.
6164 * index: the index the filter allocates.
6165 * filter: ponter to the filter that will be added.
6166 * rx_queue: the queue id the filter assigned to.
6169 * - On success, zero.
6170 * - On failure, a negative value.
6173 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6174 struct ixgbe_5tuple_filter *filter)
6176 struct ixgbe_filter_info *filter_info =
6177 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6181 * look for an unused 5tuple filter index,
6182 * and insert the filter to list.
6184 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6185 idx = i / (sizeof(uint32_t) * NBBY);
6186 shift = i % (sizeof(uint32_t) * NBBY);
6187 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6188 filter_info->fivetuple_mask[idx] |= 1 << shift;
6190 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6196 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6197 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6201 ixgbe_inject_5tuple_filter(dev, filter);
6207 * remove a 5tuple filter
6210 * dev: Pointer to struct rte_eth_dev.
6211 * filter: the pointer of the filter will be removed.
6214 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6215 struct ixgbe_5tuple_filter *filter)
6217 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6218 struct ixgbe_filter_info *filter_info =
6219 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6220 uint16_t index = filter->index;
6222 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6223 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6224 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6227 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6228 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6229 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6230 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6231 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6235 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6237 struct ixgbe_hw *hw;
6238 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6239 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6241 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6243 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6246 /* refuse mtu that requires the support of scattered packets when this
6247 * feature has not been enabled before.
6249 if (!rx_conf->enable_scatter &&
6250 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6251 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6255 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6256 * request of the version 2.0 of the mailbox API.
6257 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6258 * of the mailbox API.
6259 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6260 * prior to 3.11.33 which contains the following change:
6261 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6263 ixgbevf_rlpml_set_vf(hw, max_frame);
6265 /* update max frame size */
6266 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6270 static inline struct ixgbe_5tuple_filter *
6271 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6272 struct ixgbe_5tuple_filter_info *key)
6274 struct ixgbe_5tuple_filter *it;
6276 TAILQ_FOREACH(it, filter_list, entries) {
6277 if (memcmp(key, &it->filter_info,
6278 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6285 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6287 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6288 struct ixgbe_5tuple_filter_info *filter_info)
6290 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6291 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6292 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6295 switch (filter->dst_ip_mask) {
6297 filter_info->dst_ip_mask = 0;
6298 filter_info->dst_ip = filter->dst_ip;
6301 filter_info->dst_ip_mask = 1;
6304 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6308 switch (filter->src_ip_mask) {
6310 filter_info->src_ip_mask = 0;
6311 filter_info->src_ip = filter->src_ip;
6314 filter_info->src_ip_mask = 1;
6317 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6321 switch (filter->dst_port_mask) {
6323 filter_info->dst_port_mask = 0;
6324 filter_info->dst_port = filter->dst_port;
6327 filter_info->dst_port_mask = 1;
6330 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6334 switch (filter->src_port_mask) {
6336 filter_info->src_port_mask = 0;
6337 filter_info->src_port = filter->src_port;
6340 filter_info->src_port_mask = 1;
6343 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6347 switch (filter->proto_mask) {
6349 filter_info->proto_mask = 0;
6350 filter_info->proto =
6351 convert_protocol_type(filter->proto);
6354 filter_info->proto_mask = 1;
6357 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6361 filter_info->priority = (uint8_t)filter->priority;
6366 * add or delete a ntuple filter
6369 * dev: Pointer to struct rte_eth_dev.
6370 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6371 * add: if true, add filter, if false, remove filter
6374 * - On success, zero.
6375 * - On failure, a negative value.
6378 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6379 struct rte_eth_ntuple_filter *ntuple_filter,
6382 struct ixgbe_filter_info *filter_info =
6383 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6384 struct ixgbe_5tuple_filter_info filter_5tuple;
6385 struct ixgbe_5tuple_filter *filter;
6388 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6389 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6393 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6394 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6398 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6400 if (filter != NULL && add) {
6401 PMD_DRV_LOG(ERR, "filter exists.");
6404 if (filter == NULL && !add) {
6405 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6410 filter = rte_zmalloc("ixgbe_5tuple_filter",
6411 sizeof(struct ixgbe_5tuple_filter), 0);
6414 rte_memcpy(&filter->filter_info,
6416 sizeof(struct ixgbe_5tuple_filter_info));
6417 filter->queue = ntuple_filter->queue;
6418 ret = ixgbe_add_5tuple_filter(dev, filter);
6424 ixgbe_remove_5tuple_filter(dev, filter);
6430 * get a ntuple filter
6433 * dev: Pointer to struct rte_eth_dev.
6434 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6437 * - On success, zero.
6438 * - On failure, a negative value.
6441 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6442 struct rte_eth_ntuple_filter *ntuple_filter)
6444 struct ixgbe_filter_info *filter_info =
6445 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6446 struct ixgbe_5tuple_filter_info filter_5tuple;
6447 struct ixgbe_5tuple_filter *filter;
6450 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6451 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6455 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6456 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6460 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6462 if (filter == NULL) {
6463 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6466 ntuple_filter->queue = filter->queue;
6471 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6472 * @dev: pointer to rte_eth_dev structure
6473 * @filter_op:operation will be taken.
6474 * @arg: a pointer to specific structure corresponding to the filter_op
6477 * - On success, zero.
6478 * - On failure, a negative value.
6481 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6482 enum rte_filter_op filter_op,
6485 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6488 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6490 if (filter_op == RTE_ETH_FILTER_NOP)
6494 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6499 switch (filter_op) {
6500 case RTE_ETH_FILTER_ADD:
6501 ret = ixgbe_add_del_ntuple_filter(dev,
6502 (struct rte_eth_ntuple_filter *)arg,
6505 case RTE_ETH_FILTER_DELETE:
6506 ret = ixgbe_add_del_ntuple_filter(dev,
6507 (struct rte_eth_ntuple_filter *)arg,
6510 case RTE_ETH_FILTER_GET:
6511 ret = ixgbe_get_ntuple_filter(dev,
6512 (struct rte_eth_ntuple_filter *)arg);
6515 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6523 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6524 struct rte_eth_ethertype_filter *filter,
6527 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6528 struct ixgbe_filter_info *filter_info =
6529 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6533 struct ixgbe_ethertype_filter ethertype_filter;
6535 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6538 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6539 filter->ether_type == ETHER_TYPE_IPv6) {
6540 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6541 " ethertype filter.", filter->ether_type);
6545 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6546 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6549 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6550 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6554 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6555 if (ret >= 0 && add) {
6556 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6557 filter->ether_type);
6560 if (ret < 0 && !add) {
6561 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6562 filter->ether_type);
6567 etqf = IXGBE_ETQF_FILTER_EN;
6568 etqf |= (uint32_t)filter->ether_type;
6569 etqs |= (uint32_t)((filter->queue <<
6570 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6571 IXGBE_ETQS_RX_QUEUE);
6572 etqs |= IXGBE_ETQS_QUEUE_EN;
6574 ethertype_filter.ethertype = filter->ether_type;
6575 ethertype_filter.etqf = etqf;
6576 ethertype_filter.etqs = etqs;
6577 ethertype_filter.conf = FALSE;
6578 ret = ixgbe_ethertype_filter_insert(filter_info,
6581 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6585 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6589 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6590 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6591 IXGBE_WRITE_FLUSH(hw);
6597 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6598 struct rte_eth_ethertype_filter *filter)
6600 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6601 struct ixgbe_filter_info *filter_info =
6602 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6603 uint32_t etqf, etqs;
6606 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6608 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6609 filter->ether_type);
6613 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6614 if (etqf & IXGBE_ETQF_FILTER_EN) {
6615 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6616 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6618 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6619 IXGBE_ETQS_RX_QUEUE_SHIFT;
6626 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6627 * @dev: pointer to rte_eth_dev structure
6628 * @filter_op:operation will be taken.
6629 * @arg: a pointer to specific structure corresponding to the filter_op
6632 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6633 enum rte_filter_op filter_op,
6636 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6639 MAC_TYPE_FILTER_SUP(hw->mac.type);
6641 if (filter_op == RTE_ETH_FILTER_NOP)
6645 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6650 switch (filter_op) {
6651 case RTE_ETH_FILTER_ADD:
6652 ret = ixgbe_add_del_ethertype_filter(dev,
6653 (struct rte_eth_ethertype_filter *)arg,
6656 case RTE_ETH_FILTER_DELETE:
6657 ret = ixgbe_add_del_ethertype_filter(dev,
6658 (struct rte_eth_ethertype_filter *)arg,
6661 case RTE_ETH_FILTER_GET:
6662 ret = ixgbe_get_ethertype_filter(dev,
6663 (struct rte_eth_ethertype_filter *)arg);
6666 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6674 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6675 enum rte_filter_type filter_type,
6676 enum rte_filter_op filter_op,
6681 switch (filter_type) {
6682 case RTE_ETH_FILTER_NTUPLE:
6683 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6685 case RTE_ETH_FILTER_ETHERTYPE:
6686 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6688 case RTE_ETH_FILTER_SYN:
6689 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6691 case RTE_ETH_FILTER_FDIR:
6692 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6694 case RTE_ETH_FILTER_L2_TUNNEL:
6695 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6697 case RTE_ETH_FILTER_GENERIC:
6698 if (filter_op != RTE_ETH_FILTER_GET)
6700 *(const void **)arg = &ixgbe_flow_ops;
6703 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6713 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6714 u8 **mc_addr_ptr, u32 *vmdq)
6719 mc_addr = *mc_addr_ptr;
6720 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6725 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6726 struct ether_addr *mc_addr_set,
6727 uint32_t nb_mc_addr)
6729 struct ixgbe_hw *hw;
6732 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6733 mc_addr_list = (u8 *)mc_addr_set;
6734 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6735 ixgbe_dev_addr_list_itr, TRUE);
6739 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6741 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6742 uint64_t systime_cycles;
6744 switch (hw->mac.type) {
6745 case ixgbe_mac_X550:
6746 case ixgbe_mac_X550EM_x:
6747 case ixgbe_mac_X550EM_a:
6748 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6749 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6750 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6754 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6755 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6759 return systime_cycles;
6763 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6765 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6766 uint64_t rx_tstamp_cycles;
6768 switch (hw->mac.type) {
6769 case ixgbe_mac_X550:
6770 case ixgbe_mac_X550EM_x:
6771 case ixgbe_mac_X550EM_a:
6772 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6773 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6774 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6778 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6779 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6780 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6784 return rx_tstamp_cycles;
6788 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6790 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6791 uint64_t tx_tstamp_cycles;
6793 switch (hw->mac.type) {
6794 case ixgbe_mac_X550:
6795 case ixgbe_mac_X550EM_x:
6796 case ixgbe_mac_X550EM_a:
6797 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6798 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6799 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6803 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6804 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6805 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6809 return tx_tstamp_cycles;
6813 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6815 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6816 struct ixgbe_adapter *adapter =
6817 (struct ixgbe_adapter *)dev->data->dev_private;
6818 struct rte_eth_link link;
6819 uint32_t incval = 0;
6822 /* Get current link speed. */
6823 memset(&link, 0, sizeof(link));
6824 ixgbe_dev_link_update(dev, 1);
6825 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6827 switch (link.link_speed) {
6828 case ETH_SPEED_NUM_100M:
6829 incval = IXGBE_INCVAL_100;
6830 shift = IXGBE_INCVAL_SHIFT_100;
6832 case ETH_SPEED_NUM_1G:
6833 incval = IXGBE_INCVAL_1GB;
6834 shift = IXGBE_INCVAL_SHIFT_1GB;
6836 case ETH_SPEED_NUM_10G:
6838 incval = IXGBE_INCVAL_10GB;
6839 shift = IXGBE_INCVAL_SHIFT_10GB;
6843 switch (hw->mac.type) {
6844 case ixgbe_mac_X550:
6845 case ixgbe_mac_X550EM_x:
6846 case ixgbe_mac_X550EM_a:
6847 /* Independent of link speed. */
6849 /* Cycles read will be interpreted as ns. */
6852 case ixgbe_mac_X540:
6853 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6855 case ixgbe_mac_82599EB:
6856 incval >>= IXGBE_INCVAL_SHIFT_82599;
6857 shift -= IXGBE_INCVAL_SHIFT_82599;
6858 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6859 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6862 /* Not supported. */
6866 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6867 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6868 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6870 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6871 adapter->systime_tc.cc_shift = shift;
6872 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6874 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6875 adapter->rx_tstamp_tc.cc_shift = shift;
6876 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6878 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6879 adapter->tx_tstamp_tc.cc_shift = shift;
6880 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6884 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6886 struct ixgbe_adapter *adapter =
6887 (struct ixgbe_adapter *)dev->data->dev_private;
6889 adapter->systime_tc.nsec += delta;
6890 adapter->rx_tstamp_tc.nsec += delta;
6891 adapter->tx_tstamp_tc.nsec += delta;
6897 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6900 struct ixgbe_adapter *adapter =
6901 (struct ixgbe_adapter *)dev->data->dev_private;
6903 ns = rte_timespec_to_ns(ts);
6904 /* Set the timecounters to a new value. */
6905 adapter->systime_tc.nsec = ns;
6906 adapter->rx_tstamp_tc.nsec = ns;
6907 adapter->tx_tstamp_tc.nsec = ns;
6913 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6915 uint64_t ns, systime_cycles;
6916 struct ixgbe_adapter *adapter =
6917 (struct ixgbe_adapter *)dev->data->dev_private;
6919 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6920 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6921 *ts = rte_ns_to_timespec(ns);
6927 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6929 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6933 /* Stop the timesync system time. */
6934 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6935 /* Reset the timesync system time value. */
6936 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6937 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6939 /* Enable system time for platforms where it isn't on by default. */
6940 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6941 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6942 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6944 ixgbe_start_timecounters(dev);
6946 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6947 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6949 IXGBE_ETQF_FILTER_EN |
6952 /* Enable timestamping of received PTP packets. */
6953 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6954 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6955 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6957 /* Enable timestamping of transmitted PTP packets. */
6958 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6959 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6960 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6962 IXGBE_WRITE_FLUSH(hw);
6968 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6970 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6973 /* Disable timestamping of transmitted PTP packets. */
6974 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6975 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6976 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6978 /* Disable timestamping of received PTP packets. */
6979 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6980 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6981 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6983 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6984 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6986 /* Stop incrementating the System Time registers. */
6987 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6993 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6994 struct timespec *timestamp,
6995 uint32_t flags __rte_unused)
6997 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6998 struct ixgbe_adapter *adapter =
6999 (struct ixgbe_adapter *)dev->data->dev_private;
7000 uint32_t tsync_rxctl;
7001 uint64_t rx_tstamp_cycles;
7004 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7005 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7008 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7009 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7010 *timestamp = rte_ns_to_timespec(ns);
7016 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7017 struct timespec *timestamp)
7019 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7020 struct ixgbe_adapter *adapter =
7021 (struct ixgbe_adapter *)dev->data->dev_private;
7022 uint32_t tsync_txctl;
7023 uint64_t tx_tstamp_cycles;
7026 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7027 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7030 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7031 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7032 *timestamp = rte_ns_to_timespec(ns);
7038 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7040 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7043 const struct reg_info *reg_group;
7044 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7045 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7047 while ((reg_group = reg_set[g_ind++]))
7048 count += ixgbe_regs_group_count(reg_group);
7054 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7058 const struct reg_info *reg_group;
7060 while ((reg_group = ixgbevf_regs[g_ind++]))
7061 count += ixgbe_regs_group_count(reg_group);
7067 ixgbe_get_regs(struct rte_eth_dev *dev,
7068 struct rte_dev_reg_info *regs)
7070 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7071 uint32_t *data = regs->data;
7074 const struct reg_info *reg_group;
7075 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7076 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7079 regs->length = ixgbe_get_reg_length(dev);
7080 regs->width = sizeof(uint32_t);
7084 /* Support only full register dump */
7085 if ((regs->length == 0) ||
7086 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7087 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7089 while ((reg_group = reg_set[g_ind++]))
7090 count += ixgbe_read_regs_group(dev, &data[count],
7099 ixgbevf_get_regs(struct rte_eth_dev *dev,
7100 struct rte_dev_reg_info *regs)
7102 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7103 uint32_t *data = regs->data;
7106 const struct reg_info *reg_group;
7109 regs->length = ixgbevf_get_reg_length(dev);
7110 regs->width = sizeof(uint32_t);
7114 /* Support only full register dump */
7115 if ((regs->length == 0) ||
7116 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7117 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7119 while ((reg_group = ixgbevf_regs[g_ind++]))
7120 count += ixgbe_read_regs_group(dev, &data[count],
7129 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7131 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7133 /* Return unit is byte count */
7134 return hw->eeprom.word_size * 2;
7138 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7139 struct rte_dev_eeprom_info *in_eeprom)
7141 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7142 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7143 uint16_t *data = in_eeprom->data;
7146 first = in_eeprom->offset >> 1;
7147 length = in_eeprom->length >> 1;
7148 if ((first > hw->eeprom.word_size) ||
7149 ((first + length) > hw->eeprom.word_size))
7152 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7154 return eeprom->ops.read_buffer(hw, first, length, data);
7158 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7159 struct rte_dev_eeprom_info *in_eeprom)
7161 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7162 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7163 uint16_t *data = in_eeprom->data;
7166 first = in_eeprom->offset >> 1;
7167 length = in_eeprom->length >> 1;
7168 if ((first > hw->eeprom.word_size) ||
7169 ((first + length) > hw->eeprom.word_size))
7172 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7174 return eeprom->ops.write_buffer(hw, first, length, data);
7178 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7180 case ixgbe_mac_X550:
7181 case ixgbe_mac_X550EM_x:
7182 case ixgbe_mac_X550EM_a:
7183 return ETH_RSS_RETA_SIZE_512;
7184 case ixgbe_mac_X550_vf:
7185 case ixgbe_mac_X550EM_x_vf:
7186 case ixgbe_mac_X550EM_a_vf:
7187 return ETH_RSS_RETA_SIZE_64;
7189 return ETH_RSS_RETA_SIZE_128;
7194 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7196 case ixgbe_mac_X550:
7197 case ixgbe_mac_X550EM_x:
7198 case ixgbe_mac_X550EM_a:
7199 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7200 return IXGBE_RETA(reta_idx >> 2);
7202 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7203 case ixgbe_mac_X550_vf:
7204 case ixgbe_mac_X550EM_x_vf:
7205 case ixgbe_mac_X550EM_a_vf:
7206 return IXGBE_VFRETA(reta_idx >> 2);
7208 return IXGBE_RETA(reta_idx >> 2);
7213 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7215 case ixgbe_mac_X550_vf:
7216 case ixgbe_mac_X550EM_x_vf:
7217 case ixgbe_mac_X550EM_a_vf:
7218 return IXGBE_VFMRQC;
7225 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7227 case ixgbe_mac_X550_vf:
7228 case ixgbe_mac_X550EM_x_vf:
7229 case ixgbe_mac_X550EM_a_vf:
7230 return IXGBE_VFRSSRK(i);
7232 return IXGBE_RSSRK(i);
7237 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7239 case ixgbe_mac_82599_vf:
7240 case ixgbe_mac_X540_vf:
7248 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7249 struct rte_eth_dcb_info *dcb_info)
7251 struct ixgbe_dcb_config *dcb_config =
7252 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7253 struct ixgbe_dcb_tc_config *tc;
7254 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7258 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7259 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7261 dcb_info->nb_tcs = 1;
7263 tc_queue = &dcb_info->tc_queue;
7264 nb_tcs = dcb_info->nb_tcs;
7266 if (dcb_config->vt_mode) { /* vt is enabled*/
7267 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7268 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7269 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7270 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7271 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7272 for (j = 0; j < nb_tcs; j++) {
7273 tc_queue->tc_rxq[0][j].base = j;
7274 tc_queue->tc_rxq[0][j].nb_queue = 1;
7275 tc_queue->tc_txq[0][j].base = j;
7276 tc_queue->tc_txq[0][j].nb_queue = 1;
7279 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7280 for (j = 0; j < nb_tcs; j++) {
7281 tc_queue->tc_rxq[i][j].base =
7283 tc_queue->tc_rxq[i][j].nb_queue = 1;
7284 tc_queue->tc_txq[i][j].base =
7286 tc_queue->tc_txq[i][j].nb_queue = 1;
7290 } else { /* vt is disabled*/
7291 struct rte_eth_dcb_rx_conf *rx_conf =
7292 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7293 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7294 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7295 if (dcb_info->nb_tcs == ETH_4_TCS) {
7296 for (i = 0; i < dcb_info->nb_tcs; i++) {
7297 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7298 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7300 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7301 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7302 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7303 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7304 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7305 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7306 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7307 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7308 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7309 for (i = 0; i < dcb_info->nb_tcs; i++) {
7310 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7311 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7313 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7314 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7315 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7316 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7317 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7318 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7319 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7320 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7321 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7322 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7323 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7324 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7325 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7326 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7327 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7328 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7331 for (i = 0; i < dcb_info->nb_tcs; i++) {
7332 tc = &dcb_config->tc_config[i];
7333 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7338 /* Update e-tag ether type */
7340 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7341 uint16_t ether_type)
7343 uint32_t etag_etype;
7345 if (hw->mac.type != ixgbe_mac_X550 &&
7346 hw->mac.type != ixgbe_mac_X550EM_x &&
7347 hw->mac.type != ixgbe_mac_X550EM_a) {
7351 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7352 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7353 etag_etype |= ether_type;
7354 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7355 IXGBE_WRITE_FLUSH(hw);
7360 /* Config l2 tunnel ether type */
7362 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7363 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7366 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7367 struct ixgbe_l2_tn_info *l2_tn_info =
7368 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7370 if (l2_tunnel == NULL)
7373 switch (l2_tunnel->l2_tunnel_type) {
7374 case RTE_L2_TUNNEL_TYPE_E_TAG:
7375 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7376 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7379 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7387 /* Enable e-tag tunnel */
7389 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7391 uint32_t etag_etype;
7393 if (hw->mac.type != ixgbe_mac_X550 &&
7394 hw->mac.type != ixgbe_mac_X550EM_x &&
7395 hw->mac.type != ixgbe_mac_X550EM_a) {
7399 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7400 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7401 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7402 IXGBE_WRITE_FLUSH(hw);
7407 /* Enable l2 tunnel */
7409 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7410 enum rte_eth_tunnel_type l2_tunnel_type)
7413 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7414 struct ixgbe_l2_tn_info *l2_tn_info =
7415 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7417 switch (l2_tunnel_type) {
7418 case RTE_L2_TUNNEL_TYPE_E_TAG:
7419 l2_tn_info->e_tag_en = TRUE;
7420 ret = ixgbe_e_tag_enable(hw);
7423 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7431 /* Disable e-tag tunnel */
7433 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7435 uint32_t etag_etype;
7437 if (hw->mac.type != ixgbe_mac_X550 &&
7438 hw->mac.type != ixgbe_mac_X550EM_x &&
7439 hw->mac.type != ixgbe_mac_X550EM_a) {
7443 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7444 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7445 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7446 IXGBE_WRITE_FLUSH(hw);
7451 /* Disable l2 tunnel */
7453 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7454 enum rte_eth_tunnel_type l2_tunnel_type)
7457 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7458 struct ixgbe_l2_tn_info *l2_tn_info =
7459 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7461 switch (l2_tunnel_type) {
7462 case RTE_L2_TUNNEL_TYPE_E_TAG:
7463 l2_tn_info->e_tag_en = FALSE;
7464 ret = ixgbe_e_tag_disable(hw);
7467 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7476 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7477 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7480 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7481 uint32_t i, rar_entries;
7482 uint32_t rar_low, rar_high;
7484 if (hw->mac.type != ixgbe_mac_X550 &&
7485 hw->mac.type != ixgbe_mac_X550EM_x &&
7486 hw->mac.type != ixgbe_mac_X550EM_a) {
7490 rar_entries = ixgbe_get_num_rx_addrs(hw);
7492 for (i = 1; i < rar_entries; i++) {
7493 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7494 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7495 if ((rar_high & IXGBE_RAH_AV) &&
7496 (rar_high & IXGBE_RAH_ADTYPE) &&
7497 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7498 l2_tunnel->tunnel_id)) {
7499 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7500 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7502 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7512 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7513 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7516 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7517 uint32_t i, rar_entries;
7518 uint32_t rar_low, rar_high;
7520 if (hw->mac.type != ixgbe_mac_X550 &&
7521 hw->mac.type != ixgbe_mac_X550EM_x &&
7522 hw->mac.type != ixgbe_mac_X550EM_a) {
7526 /* One entry for one tunnel. Try to remove potential existing entry. */
7527 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7529 rar_entries = ixgbe_get_num_rx_addrs(hw);
7531 for (i = 1; i < rar_entries; i++) {
7532 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7533 if (rar_high & IXGBE_RAH_AV) {
7536 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7537 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7538 rar_low = l2_tunnel->tunnel_id;
7540 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7541 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7547 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7548 " Please remove a rule before adding a new one.");
7552 static inline struct ixgbe_l2_tn_filter *
7553 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7554 struct ixgbe_l2_tn_key *key)
7558 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7562 return l2_tn_info->hash_map[ret];
7566 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7567 struct ixgbe_l2_tn_filter *l2_tn_filter)
7571 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7572 &l2_tn_filter->key);
7576 "Failed to insert L2 tunnel filter"
7577 " to hash table %d!",
7582 l2_tn_info->hash_map[ret] = l2_tn_filter;
7584 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7590 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7591 struct ixgbe_l2_tn_key *key)
7594 struct ixgbe_l2_tn_filter *l2_tn_filter;
7596 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7600 "No such L2 tunnel filter to delete %d!",
7605 l2_tn_filter = l2_tn_info->hash_map[ret];
7606 l2_tn_info->hash_map[ret] = NULL;
7608 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7609 rte_free(l2_tn_filter);
7614 /* Add l2 tunnel filter */
7616 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7617 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7621 struct ixgbe_l2_tn_info *l2_tn_info =
7622 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7623 struct ixgbe_l2_tn_key key;
7624 struct ixgbe_l2_tn_filter *node;
7627 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7628 key.tn_id = l2_tunnel->tunnel_id;
7630 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7634 "The L2 tunnel filter already exists!");
7638 node = rte_zmalloc("ixgbe_l2_tn",
7639 sizeof(struct ixgbe_l2_tn_filter),
7644 rte_memcpy(&node->key,
7646 sizeof(struct ixgbe_l2_tn_key));
7647 node->pool = l2_tunnel->pool;
7648 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7655 switch (l2_tunnel->l2_tunnel_type) {
7656 case RTE_L2_TUNNEL_TYPE_E_TAG:
7657 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7660 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7665 if ((!restore) && (ret < 0))
7666 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7671 /* Delete l2 tunnel filter */
7673 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7674 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7677 struct ixgbe_l2_tn_info *l2_tn_info =
7678 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7679 struct ixgbe_l2_tn_key key;
7681 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7682 key.tn_id = l2_tunnel->tunnel_id;
7683 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7687 switch (l2_tunnel->l2_tunnel_type) {
7688 case RTE_L2_TUNNEL_TYPE_E_TAG:
7689 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7692 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7701 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7702 * @dev: pointer to rte_eth_dev structure
7703 * @filter_op:operation will be taken.
7704 * @arg: a pointer to specific structure corresponding to the filter_op
7707 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7708 enum rte_filter_op filter_op,
7713 if (filter_op == RTE_ETH_FILTER_NOP)
7717 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7722 switch (filter_op) {
7723 case RTE_ETH_FILTER_ADD:
7724 ret = ixgbe_dev_l2_tunnel_filter_add
7726 (struct rte_eth_l2_tunnel_conf *)arg,
7729 case RTE_ETH_FILTER_DELETE:
7730 ret = ixgbe_dev_l2_tunnel_filter_del
7732 (struct rte_eth_l2_tunnel_conf *)arg);
7735 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7743 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7747 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7749 if (hw->mac.type != ixgbe_mac_X550 &&
7750 hw->mac.type != ixgbe_mac_X550EM_x &&
7751 hw->mac.type != ixgbe_mac_X550EM_a) {
7755 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7756 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7758 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7759 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7764 /* Enable l2 tunnel forwarding */
7766 ixgbe_dev_l2_tunnel_forwarding_enable
7767 (struct rte_eth_dev *dev,
7768 enum rte_eth_tunnel_type l2_tunnel_type)
7770 struct ixgbe_l2_tn_info *l2_tn_info =
7771 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7774 switch (l2_tunnel_type) {
7775 case RTE_L2_TUNNEL_TYPE_E_TAG:
7776 l2_tn_info->e_tag_fwd_en = TRUE;
7777 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7780 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7788 /* Disable l2 tunnel forwarding */
7790 ixgbe_dev_l2_tunnel_forwarding_disable
7791 (struct rte_eth_dev *dev,
7792 enum rte_eth_tunnel_type l2_tunnel_type)
7794 struct ixgbe_l2_tn_info *l2_tn_info =
7795 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7798 switch (l2_tunnel_type) {
7799 case RTE_L2_TUNNEL_TYPE_E_TAG:
7800 l2_tn_info->e_tag_fwd_en = FALSE;
7801 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7804 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7813 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7814 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7817 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7819 uint32_t vmtir, vmvir;
7820 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7822 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7824 "VF id %u should be less than %u",
7830 if (hw->mac.type != ixgbe_mac_X550 &&
7831 hw->mac.type != ixgbe_mac_X550EM_x &&
7832 hw->mac.type != ixgbe_mac_X550EM_a) {
7837 vmtir = l2_tunnel->tunnel_id;
7841 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7843 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7844 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7846 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7847 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7852 /* Enable l2 tunnel tag insertion */
7854 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7855 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7859 switch (l2_tunnel->l2_tunnel_type) {
7860 case RTE_L2_TUNNEL_TYPE_E_TAG:
7861 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7864 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7872 /* Disable l2 tunnel tag insertion */
7874 ixgbe_dev_l2_tunnel_insertion_disable
7875 (struct rte_eth_dev *dev,
7876 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7880 switch (l2_tunnel->l2_tunnel_type) {
7881 case RTE_L2_TUNNEL_TYPE_E_TAG:
7882 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7885 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7894 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7899 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7901 if (hw->mac.type != ixgbe_mac_X550 &&
7902 hw->mac.type != ixgbe_mac_X550EM_x &&
7903 hw->mac.type != ixgbe_mac_X550EM_a) {
7907 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7909 qde |= IXGBE_QDE_STRIP_TAG;
7911 qde &= ~IXGBE_QDE_STRIP_TAG;
7912 qde &= ~IXGBE_QDE_READ;
7913 qde |= IXGBE_QDE_WRITE;
7914 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7919 /* Enable l2 tunnel tag stripping */
7921 ixgbe_dev_l2_tunnel_stripping_enable
7922 (struct rte_eth_dev *dev,
7923 enum rte_eth_tunnel_type l2_tunnel_type)
7927 switch (l2_tunnel_type) {
7928 case RTE_L2_TUNNEL_TYPE_E_TAG:
7929 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7932 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7940 /* Disable l2 tunnel tag stripping */
7942 ixgbe_dev_l2_tunnel_stripping_disable
7943 (struct rte_eth_dev *dev,
7944 enum rte_eth_tunnel_type l2_tunnel_type)
7948 switch (l2_tunnel_type) {
7949 case RTE_L2_TUNNEL_TYPE_E_TAG:
7950 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7953 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7961 /* Enable/disable l2 tunnel offload functions */
7963 ixgbe_dev_l2_tunnel_offload_set
7964 (struct rte_eth_dev *dev,
7965 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7971 if (l2_tunnel == NULL)
7975 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7977 ret = ixgbe_dev_l2_tunnel_enable(
7979 l2_tunnel->l2_tunnel_type);
7981 ret = ixgbe_dev_l2_tunnel_disable(
7983 l2_tunnel->l2_tunnel_type);
7986 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7988 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7992 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7997 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7999 ret = ixgbe_dev_l2_tunnel_stripping_enable(
8001 l2_tunnel->l2_tunnel_type);
8003 ret = ixgbe_dev_l2_tunnel_stripping_disable(
8005 l2_tunnel->l2_tunnel_type);
8008 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8010 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8012 l2_tunnel->l2_tunnel_type);
8014 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8016 l2_tunnel->l2_tunnel_type);
8023 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8026 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8027 IXGBE_WRITE_FLUSH(hw);
8032 /* There's only one register for VxLAN UDP port.
8033 * So, we cannot add several ports. Will update it.
8036 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8040 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8044 return ixgbe_update_vxlan_port(hw, port);
8047 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8048 * UDP port, it must have a value.
8049 * So, will reset it to the original value 0.
8052 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8057 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8059 if (cur_port != port) {
8060 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8064 return ixgbe_update_vxlan_port(hw, 0);
8067 /* Add UDP tunneling port */
8069 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8070 struct rte_eth_udp_tunnel *udp_tunnel)
8073 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8075 if (hw->mac.type != ixgbe_mac_X550 &&
8076 hw->mac.type != ixgbe_mac_X550EM_x &&
8077 hw->mac.type != ixgbe_mac_X550EM_a) {
8081 if (udp_tunnel == NULL)
8084 switch (udp_tunnel->prot_type) {
8085 case RTE_TUNNEL_TYPE_VXLAN:
8086 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8089 case RTE_TUNNEL_TYPE_GENEVE:
8090 case RTE_TUNNEL_TYPE_TEREDO:
8091 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8096 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8104 /* Remove UDP tunneling port */
8106 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8107 struct rte_eth_udp_tunnel *udp_tunnel)
8110 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8112 if (hw->mac.type != ixgbe_mac_X550 &&
8113 hw->mac.type != ixgbe_mac_X550EM_x &&
8114 hw->mac.type != ixgbe_mac_X550EM_a) {
8118 if (udp_tunnel == NULL)
8121 switch (udp_tunnel->prot_type) {
8122 case RTE_TUNNEL_TYPE_VXLAN:
8123 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8125 case RTE_TUNNEL_TYPE_GENEVE:
8126 case RTE_TUNNEL_TYPE_TEREDO:
8127 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8131 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8140 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8142 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8144 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8148 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8150 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8152 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8155 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8157 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8160 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8163 /* PF reset VF event */
8164 if (in_msg == IXGBE_PF_CONTROL_MSG)
8165 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8170 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8173 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8174 struct ixgbe_interrupt *intr =
8175 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8176 ixgbevf_intr_disable(hw);
8178 /* read-on-clear nic registers here */
8179 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8182 /* only one misc vector supported - mailbox */
8183 eicr &= IXGBE_VTEICR_MASK;
8184 if (eicr == IXGBE_MISC_VEC_ID)
8185 intr->flags |= IXGBE_FLAG_MAILBOX;
8191 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8193 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8194 struct ixgbe_interrupt *intr =
8195 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8197 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8198 ixgbevf_mbx_process(dev);
8199 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8202 ixgbevf_intr_enable(hw);
8208 ixgbevf_dev_interrupt_handler(void *param)
8210 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8212 ixgbevf_dev_interrupt_get_status(dev);
8213 ixgbevf_dev_interrupt_action(dev);
8217 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8218 * @hw: pointer to hardware structure
8220 * Stops the transmit data path and waits for the HW to internally empty
8221 * the Tx security block
8223 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8225 #define IXGBE_MAX_SECTX_POLL 40
8230 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8231 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8232 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8233 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8234 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8235 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8237 /* Use interrupt-safe sleep just in case */
8241 /* For informational purposes only */
8242 if (i >= IXGBE_MAX_SECTX_POLL)
8243 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8244 "path fully disabled. Continuing with init.");
8246 return IXGBE_SUCCESS;
8250 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8251 * @hw: pointer to hardware structure
8253 * Enables the transmit data path.
8255 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8259 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8260 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8261 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8262 IXGBE_WRITE_FLUSH(hw);
8264 return IXGBE_SUCCESS;
8267 /* restore n-tuple filter */
8269 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8271 struct ixgbe_filter_info *filter_info =
8272 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8273 struct ixgbe_5tuple_filter *node;
8275 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8276 ixgbe_inject_5tuple_filter(dev, node);
8280 /* restore ethernet type filter */
8282 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8284 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8285 struct ixgbe_filter_info *filter_info =
8286 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8289 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8290 if (filter_info->ethertype_mask & (1 << i)) {
8291 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8292 filter_info->ethertype_filters[i].etqf);
8293 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8294 filter_info->ethertype_filters[i].etqs);
8295 IXGBE_WRITE_FLUSH(hw);
8300 /* restore SYN filter */
8302 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8304 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8305 struct ixgbe_filter_info *filter_info =
8306 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8309 synqf = filter_info->syn_info;
8311 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8312 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8313 IXGBE_WRITE_FLUSH(hw);
8317 /* restore L2 tunnel filter */
8319 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8321 struct ixgbe_l2_tn_info *l2_tn_info =
8322 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8323 struct ixgbe_l2_tn_filter *node;
8324 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8326 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8327 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8328 l2_tn_conf.tunnel_id = node->key.tn_id;
8329 l2_tn_conf.pool = node->pool;
8330 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8335 ixgbe_filter_restore(struct rte_eth_dev *dev)
8337 ixgbe_ntuple_filter_restore(dev);
8338 ixgbe_ethertype_filter_restore(dev);
8339 ixgbe_syn_filter_restore(dev);
8340 ixgbe_fdir_filter_restore(dev);
8341 ixgbe_l2_tn_filter_restore(dev);
8347 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8349 struct ixgbe_l2_tn_info *l2_tn_info =
8350 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8351 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8353 if (l2_tn_info->e_tag_en)
8354 (void)ixgbe_e_tag_enable(hw);
8356 if (l2_tn_info->e_tag_fwd_en)
8357 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8359 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8362 /* remove all the n-tuple filters */
8364 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8366 struct ixgbe_filter_info *filter_info =
8367 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8368 struct ixgbe_5tuple_filter *p_5tuple;
8370 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8371 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8374 /* remove all the ether type filters */
8376 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8378 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8379 struct ixgbe_filter_info *filter_info =
8380 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8383 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8384 if (filter_info->ethertype_mask & (1 << i) &&
8385 !filter_info->ethertype_filters[i].conf) {
8386 (void)ixgbe_ethertype_filter_remove(filter_info,
8388 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8389 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8390 IXGBE_WRITE_FLUSH(hw);
8395 /* remove the SYN filter */
8397 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8399 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8400 struct ixgbe_filter_info *filter_info =
8401 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8403 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8404 filter_info->syn_info = 0;
8406 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8407 IXGBE_WRITE_FLUSH(hw);
8411 /* remove all the L2 tunnel filters */
8413 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8415 struct ixgbe_l2_tn_info *l2_tn_info =
8416 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8417 struct ixgbe_l2_tn_filter *l2_tn_filter;
8418 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8421 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8422 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8423 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8424 l2_tn_conf.pool = l2_tn_filter->pool;
8425 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8433 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8434 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8435 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8436 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8437 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8438 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");